552 lines
19 KiB
C
552 lines
19 KiB
C
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/* ----------------------------------------------------------------------------
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* ATMEL Microcontroller Software Support - ROUSSET -
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* ----------------------------------------------------------------------------
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* Copyright (c) 2006, Atmel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* - Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the disclaimer below in the documentation and/or
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* other materials provided with the distribution.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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//------------------------------------------------------------------------------
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// Headers
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//------------------------------------------------------------------------------
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#include "mci.h"
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#include <utility/assert.h>
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#include <utility/trace.h>
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//------------------------------------------------------------------------------
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// Local constants
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//------------------------------------------------------------------------------
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/// Bit mask for status register errors.
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#define STATUS_ERRORS (AT91C_MCI_UNRE \
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| AT91C_MCI_OVRE \
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| AT91C_MCI_DTOE \
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| AT91C_MCI_DCRCE \
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| AT91C_MCI_RTOE \
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| AT91C_MCI_RENDE \
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| AT91C_MCI_RCRCE \
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| AT91C_MCI_RDIRE \
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| AT91C_MCI_RINDE)
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/// MCI data timeout configuration with 1048576 MCK cycles between 2 data transfers.
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#define DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)
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#define SDCARD_APP_OP_COND_CMD (41 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO )
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#define MMC_SEND_OP_COND_CMD (1 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD)
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#define DISABLE 0 // Disable MCI interface
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#define ENABLE 1 // Enable MCI interface
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//------------------------------------------------------------------------------
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// Local macros
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//------------------------------------------------------------------------------
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/// Used to write in PMC registers.
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#define WRITE_PMC(pPmc, regName, value) pPmc->regName = (value)
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/// Used to write in MCI registers.
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#define WRITE_MCI(pMci, regName, value) pMci->regName = (value)
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/// Used to read from MCI registers.
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#define READ_MCI(pMci, regName) (pMci->regName)
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//------------------------------------------------------------------------------
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// Global functions
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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/// Enable/disable a MCI driver instance.
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/// \param pMci Pointer to a MCI driver instance.
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/// \param enb 0 for disable MCI and 1 for enable MCI.
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//------------------------------------------------------------------------------
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void MCI_Enable(Mci *pMci, unsigned char enb)
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{
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AT91S_MCI *pMciHw = pMci->pMciHw;
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SANITY_CHECK(pMci);
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SANITY_CHECK(pMci->pMciHw);
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// Set the Control Register: Enable/Disable MCI interface clock
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if(enb == DISABLE) {
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WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);
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}
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else {
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WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);
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}
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}
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//------------------------------------------------------------------------------
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/// Initializes a MCI driver instance and the underlying peripheral.
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/// \param pMci Pointer to a MCI driver instance.
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/// \param pMciHw Pointer to a MCI peripheral.
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/// \param mciId MCI peripheral identifier.
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/// \param mode Slot and type of connected card.
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//------------------------------------------------------------------------------
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void MCI_Init(
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Mci *pMci,
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AT91S_MCI *pMciHw,
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unsigned char mciId,
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unsigned int mode)
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{
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unsigned short clkDiv;
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SANITY_CHECK(pMci);
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SANITY_CHECK(pMciHw);
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SANITY_CHECK((mode == MCI_MMC_SLOTA) || (mode == MCI_MMC_SLOTB)
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|| (mode == MCI_SD_SLOTA) || (mode == MCI_SD_SLOTB));
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// Initialize the MCI driver structure
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pMci->pMciHw = pMciHw;
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pMci->mciId = mciId;
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pMci->semaphore = 1;
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pMci->pCommand = 0;
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// Enable the MCI clock
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WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << mciId));
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// Reset the MCI
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WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);
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// Disable the MCI
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WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);
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// Disable all the interrupts
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WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);
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// Set the Data Timeout Register
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WRITE_MCI(pMciHw, MCI_DTOR, DTOR_1MEGA_CYCLES);
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// Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)
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clkDiv = (BOARD_MCK / (400000 * 2)) - 1;
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WRITE_MCI(pMciHw, MCI_MR, (clkDiv | (AT91C_MCI_PWSDIV & (0x7 << 8))));
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// Set the SDCard Register
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WRITE_MCI(pMciHw, MCI_SDCR, mode);
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// Enable the MCI and the Power Saving
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WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);
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// Disable the MCI peripheral clock.
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WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << mciId));
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}
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//------------------------------------------------------------------------------
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/// Close a MCI driver instance and the underlying peripheral.
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/// \param pMci Pointer to a MCI driver instance.
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/// \param pMciHw Pointer to a MCI peripheral.
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/// \param mciId MCI peripheral identifier.
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//------------------------------------------------------------------------------
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void MCI_Close(Mci *pMci)
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{
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AT91S_MCI *pMciHw = pMci->pMciHw;
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SANITY_CHECK(pMci);
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SANITY_CHECK(pMciHw);
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// Initialize the MCI driver structure
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pMci->semaphore = 1;
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pMci->pCommand = 0;
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// Disable the MCI peripheral clock.
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WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << pMci->mciId));
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// Disable the MCI
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WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);
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// Disable all the interrupts
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WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);
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}
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//------------------------------------------------------------------------------
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/// Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is
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/// MCK/2 and corresponds to CLKDIV = 0
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/// \param pMci Pointer to the low level MCI driver.
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/// \param mciSpeed MCI clock speed in Hz.
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//------------------------------------------------------------------------------
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void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed)
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{
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AT91S_MCI *pMciHw = pMci->pMciHw;
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unsigned int mciMr;
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unsigned short clkdiv;
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SANITY_CHECK(pMci);
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SANITY_CHECK(pMci->pMciHw);
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// Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)
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mciMr = READ_MCI(pMciHw, MCI_MR) & (~AT91C_MCI_CLKDIV);
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// Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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// divided by (2*(CLKDIV+1))
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if (mciSpeed > 0) {
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clkdiv = (BOARD_MCK / (mciSpeed * 2));
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if (clkdiv > 0) {
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clkdiv -= 1;
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}
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}
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else {
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clkdiv = 0;
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}
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WRITE_MCI(pMciHw, MCI_MR, mciMr | clkdiv);
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}
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//------------------------------------------------------------------------------
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/// Configure the MCI SDCBUS in the MCI_SDCR register. Only two modes available
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///
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/// \param pMci Pointer to the low level MCI driver.
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/// \param busWidth MCI bus width mode.
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//------------------------------------------------------------------------------
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void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth)
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{
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AT91S_MCI *pMciHw = pMci->pMciHw;
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unsigned int mciSdcr;
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SANITY_CHECK(pMci);
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SANITY_CHECK(pMci->pMciHw);
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mciSdcr = (READ_MCI(pMciHw, MCI_SDCR) & ~(AT91C_MCI_SCDBUS));
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WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr | busWidth);
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}
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//------------------------------------------------------------------------------
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/// Starts a MCI transfer. This is a non blocking function. It will return
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/// as soon as the transfer is started.
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/// Return 0 if successful; otherwise returns MCI_ERROR_LOCK if the driver is
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/// already in use.
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/// \param pMci Pointer to an MCI driver instance.
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/// \param pCommand Pointer to the command to execute.
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//------------------------------------------------------------------------------
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unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pCommand)
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{
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AT91PS_MCI pMciHw = pMci->pMciHw;
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unsigned int mciIer, mciMr;
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SANITY_CHECK(pMci);
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SANITY_CHECK(pMciHw);
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SANITY_CHECK(pCommand);
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// Try to acquire the MCI semaphore
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if (pMci->semaphore == 0) {
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return MCI_ERROR_LOCK;
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}
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pMci->semaphore--;
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// trace_LOG(trace_DEBUG, "MCI_SendCommand %x %d\n\r", READ_MCI(pMciHw, MCI_SR), pCommand->cmd & 0x3f);
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// Command is now being executed
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pMci->pCommand = pCommand;
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pCommand->status = MCI_STATUS_PENDING;
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// Enable the MCI clock
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WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << pMci->mciId));
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//Disable MCI clock, for multi-block data transfer
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MCI_Enable(pMci, DISABLE);
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// Set PDC data transfer direction
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if(pCommand->blockSize > 0) {
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if(pCommand->isRead) {
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WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);
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}
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else {
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WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);
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}
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}
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// Disable transmitter and receiver
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WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);
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mciMr = READ_MCI(pMciHw, MCI_MR) & (~(AT91C_MCI_BLKLEN | AT91C_MCI_PDCMODE));
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// Command with DATA stage
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if (pCommand->blockSize > 0) {
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// Enable PDC mode and set block size
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if(pCommand->conTrans != MCI_CONTINUE_TRANSFER) {
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WRITE_MCI(pMciHw, MCI_MR, mciMr | AT91C_MCI_PDCMODE | (pCommand->blockSize << 16));
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}
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// DATA transfer from card to host
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if (pCommand->isRead) {
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WRITE_MCI(pMciHw, MCI_RPR, (int) pCommand->pData);
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// If Multiblock command set the BLKR register
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/* if (pCommand->nbBlock > 1) {
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WRITE_MCI(pMciHw, MCI_BLKR, pCommand->nbBlock | (pCommand->blockSize << 16));
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}
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else {
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WRITE_MCI(pMciHw, MCI_BLKR, (pCommand->blockSize << 16));
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}*/
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// Sanity check
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if (pCommand->nbBlock == 0)
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pCommand->nbBlock = 1;
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////////
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if ((pCommand->blockSize & 0x3) != 0) {
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WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);
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}
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else {
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WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4);
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}
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WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);
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mciIer = AT91C_MCI_ENDRX | STATUS_ERRORS;
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// mciIer = AT91C_MCI_RXBUFF | STATUS_ERRORS;
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}
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// DATA transfer from host to card
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else {
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// Sanity check
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if (pCommand->nbBlock == 0)
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pCommand->nbBlock = 1;
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WRITE_MCI(pMciHw, MCI_TPR, (int) pCommand->pData);
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// Update the PDC counter
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if ((pCommand->blockSize & 0x3) != 0) {
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WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);
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}
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else {
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WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4);
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}
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// MCI_BLKE notifies the end of Multiblock command
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mciIer = AT91C_MCI_BLKE | STATUS_ERRORS;
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}
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}
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// No data transfer: stop at the end of the command
|
||
|
|
else {
|
||
|
|
WRITE_MCI(pMciHw, MCI_MR, mciMr);
|
||
|
|
mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS;
|
||
|
|
}
|
||
|
|
// Enable MCI clock
|
||
|
|
MCI_Enable(pMci, ENABLE);
|
||
|
|
|
||
|
|
// Send the command
|
||
|
|
if((pCommand->conTrans != MCI_CONTINUE_TRANSFER)
|
||
|
|
|| (pCommand->blockSize == 0)) {
|
||
|
|
|
||
|
|
WRITE_MCI(pMciHw, MCI_ARGR, pCommand->arg);
|
||
|
|
WRITE_MCI(pMciHw, MCI_CMDR, pCommand->cmd);
|
||
|
|
}
|
||
|
|
|
||
|
|
// In case of transmit, the PDC shall be enabled after sending the command
|
||
|
|
if ((pCommand->blockSize > 0) && !(pCommand->isRead)) {
|
||
|
|
WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);
|
||
|
|
}
|
||
|
|
|
||
|
|
// Ignore data error
|
||
|
|
// if (pCommand->blockSize == 0) {
|
||
|
|
{
|
||
|
|
mciIer &= ~(AT91C_MCI_UNRE | AT91C_MCI_OVRE \
|
||
|
|
| AT91C_MCI_DTOE | AT91C_MCI_DCRCE);
|
||
|
|
}
|
||
|
|
|
||
|
|
// Interrupt enable shall be done after PDC TXTEN and RXTEN
|
||
|
|
WRITE_MCI(pMciHw, MCI_IER, mciIer);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
//------------------------------------------------------------------------------
|
||
|
|
/// Check NOTBUSY and DTIP bits of status register on the given MCI driver.
|
||
|
|
/// Return value, 0 for bus ready, 1 for bus busy
|
||
|
|
/// \param pMci Pointer to a MCI driver instance.
|
||
|
|
//------------------------------------------------------------------------------
|
||
|
|
unsigned char MCI_CheckBusy(Mci *pMci)
|
||
|
|
{
|
||
|
|
AT91S_MCI *pMciHw = pMci->pMciHw;
|
||
|
|
unsigned int status;
|
||
|
|
|
||
|
|
// Enable MCI clock
|
||
|
|
MCI_Enable(pMci, ENABLE);
|
||
|
|
|
||
|
|
status = READ_MCI(pMciHw, MCI_SR);
|
||
|
|
// trace_LOG(trace_DEBUG, "status %x\n\r",status);
|
||
|
|
|
||
|
|
|
||
|
|
if(((status & AT91C_MCI_NOTBUSY)!=0)
|
||
|
|
&& ((status & AT91C_MCI_DTIP)==0)) {
|
||
|
|
|
||
|
|
// Disable MCI clock
|
||
|
|
MCI_Enable(pMci, DISABLE);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//------------------------------------------------------------------------------
|
||
|
|
/// Check BLKE bit of status register on the given MCI driver.
|
||
|
|
/// \param pMci Pointer to a MCI driver instance.
|
||
|
|
//------------------------------------------------------------------------------
|
||
|
|
unsigned char MCI_CheckBlke(Mci *pMci)
|
||
|
|
{
|
||
|
|
AT91S_MCI *pMciHw = pMci->pMciHw;
|
||
|
|
unsigned int status;
|
||
|
|
|
||
|
|
status = READ_MCI(pMciHw, MCI_SR);
|
||
|
|
// trace_LOG(trace_DEBUG, "status %x\n\r",status);
|
||
|
|
|
||
|
|
if((status & AT91C_MCI_BLKE)!=0) {
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//------------------------------------------------------------------------------
|
||
|
|
/// Processes pending events on the given MCI driver.
|
||
|
|
/// \param pMci Pointer to a MCI driver instance.
|
||
|
|
//------------------------------------------------------------------------------
|
||
|
|
void MCI_Handler(Mci *pMci)
|
||
|
|
{
|
||
|
|
AT91S_MCI *pMciHw = pMci->pMciHw;
|
||
|
|
MciCmd *pCommand = pMci->pCommand;
|
||
|
|
unsigned int status;
|
||
|
|
unsigned char i;
|
||
|
|
#if defined(at91rm9200)
|
||
|
|
unsigned int mciCr, mciSdcr, mciMr, mciDtor;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
SANITY_CHECK(pMci);
|
||
|
|
SANITY_CHECK(pMciHw);
|
||
|
|
SANITY_CHECK(pCommand);
|
||
|
|
|
||
|
|
// Read the status register
|
||
|
|
status = READ_MCI(pMciHw, MCI_SR) & READ_MCI(pMciHw, MCI_IMR);
|
||
|
|
// trace_LOG(trace_DEBUG, "status %x\n\r", status);
|
||
|
|
|
||
|
|
// Check if an error has occured
|
||
|
|
if ((status & STATUS_ERRORS) != 0) {
|
||
|
|
|
||
|
|
// Check error code
|
||
|
|
if ((status & STATUS_ERRORS) == AT91C_MCI_RTOE) {
|
||
|
|
|
||
|
|
pCommand->status = MCI_STATUS_NORESPONSE;
|
||
|
|
}
|
||
|
|
// if the command is SEND_OP_COND the CRC error flag is always present
|
||
|
|
// (cf : R3 response)
|
||
|
|
else if (((status & STATUS_ERRORS) != AT91C_MCI_RCRCE)
|
||
|
|
|| ((pCommand->cmd != SDCARD_APP_OP_COND_CMD)
|
||
|
|
&& (pCommand->cmd != MMC_SEND_OP_COND_CMD))) {
|
||
|
|
|
||
|
|
pCommand->status = MCI_STATUS_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Check if a transfer has been completed
|
||
|
|
if (((status & AT91C_MCI_CMDRDY) != 0)
|
||
|
|
|| ((status & AT91C_MCI_ENDRX) != 0)
|
||
|
|
|| ((status & AT91C_MCI_RXBUFF) != 0)
|
||
|
|
|| ((status & AT91C_MCI_ENDTX) != 0)
|
||
|
|
|| ((status & AT91C_MCI_BLKE) != 0)
|
||
|
|
|| ((status & AT91C_MCI_RTOE) != 0)) {
|
||
|
|
|
||
|
|
if (((status & AT91C_MCI_ENDRX) != 0)
|
||
|
|
|| ((status & AT91C_MCI_RXBUFF) != 0)
|
||
|
|
|| ((status & AT91C_MCI_ENDTX) != 0)) {
|
||
|
|
|
||
|
|
MCI_Enable(pMci, DISABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
/// On AT91RM9200-EK, if stop transmission, software reset MCI.
|
||
|
|
#if defined(at91rm9200)
|
||
|
|
if ((pCommand->cmd & AT91C_MCI_TRCMD_STOP) != 0) {
|
||
|
|
mciMr = READ_MCI(pMciHw, MCI_MR);
|
||
|
|
mciSdcr = READ_MCI(pMciHw, MCI_SDCR);
|
||
|
|
mciDtor = READ_MCI(pMciHw, MCI_DTOR);
|
||
|
|
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);
|
||
|
|
// trace_LOG(trace_DEBUG, "reset MCI\n\r");
|
||
|
|
|
||
|
|
WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);
|
||
|
|
WRITE_MCI(pMciHw, MCI_MR, mciMr);
|
||
|
|
WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr);
|
||
|
|
WRITE_MCI(pMciHw, MCI_DTOR, mciDtor);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// If no error occured, the transfer is successful
|
||
|
|
if (pCommand->status == MCI_STATUS_PENDING) {
|
||
|
|
pCommand->status = 0;
|
||
|
|
}
|
||
|
|
#if 0
|
||
|
|
if ((status & AT91C_MCI_CMDRDY) != 0)
|
||
|
|
trace_LOG(trace_DEBUG, ".");
|
||
|
|
if ((status & AT91C_MCI_ENDRX) != 0)
|
||
|
|
trace_LOG(trace_DEBUG, "<");
|
||
|
|
if ((status & AT91C_MCI_ENDTX) != 0)
|
||
|
|
trace_LOG(trace_DEBUG, "-");
|
||
|
|
if ((status & AT91C_MCI_BLKE) != 0)
|
||
|
|
trace_LOG(trace_DEBUG, ">");
|
||
|
|
trace_LOG(trace_DEBUG, "\n\r");
|
||
|
|
#endif
|
||
|
|
// Store the card response in the provided buffer
|
||
|
|
if (pCommand->pResp) {
|
||
|
|
|
||
|
|
for (i=0; i < pCommand->resSize; i++) {
|
||
|
|
|
||
|
|
pCommand->pResp[i] = READ_MCI(pMciHw, MCI_RSPR[0]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Disable interrupts
|
||
|
|
WRITE_MCI(pMciHw, MCI_IDR, READ_MCI(pMciHw, MCI_IMR));
|
||
|
|
|
||
|
|
// Release the semaphore
|
||
|
|
pMci->semaphore++;
|
||
|
|
|
||
|
|
// Invoke the callback associated with the current command (if any)
|
||
|
|
if (pCommand->callback) {
|
||
|
|
(pCommand->callback)(pCommand->status, pCommand);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//------------------------------------------------------------------------------
|
||
|
|
/// Returns 1 if the given MCI transfer is complete; otherwise returns 0.
|
||
|
|
/// \param pCommand Pointer to a MciCmd instance.
|
||
|
|
//------------------------------------------------------------------------------
|
||
|
|
unsigned char MCI_IsTxComplete(MciCmd *pCommand)
|
||
|
|
{
|
||
|
|
if (pCommand->status != MCI_STATUS_PENDING) {
|
||
|
|
if (pCommand->status != 0)
|
||
|
|
printf("MCI_IsTxComplete %d\n\r", pCommand->status);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
}
|