commit b7ab42dd94469d2c4de8105b373d54712bd65800 Author: aixiao Date: Mon Jun 3 16:27:41 2024 +0800 initial diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..e3d1679 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +SOFTWARE/build +SOFTWARE-FreeRTOS/build diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..b38e695 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,9 @@ +[submodule "SOFTWARE/Lib/pico-onewire"] + path = SOFTWARE/Lib/pico-onewire + url = https://github.com/adamboardman/pico-onewire.git +[submodule "SOFTWARE/Server/libconf"] + path = SOFTWARE/Server/libconf + url = https://git.aixiao.me/aixiao/libconf.git +[submodule "SOFTWARE-FreeRTOS/FreeRTOS-Kernel"] + path = SOFTWARE-FreeRTOS/FreeRTOS-Kernel + url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git diff --git a/HARDWARE/DOC/1912111437_Zhengzhou-Winsen-Elec-Tech-MH-Z14_C242511.pdf b/HARDWARE/DOC/1912111437_Zhengzhou-Winsen-Elec-Tech-MH-Z14_C242511.pdf new file mode 100644 index 0000000..d784fc0 Binary files /dev/null and b/HARDWARE/DOC/1912111437_Zhengzhou-Winsen-Elec-Tech-MH-Z14_C242511.pdf differ diff --git a/HARDWARE/DOC/DS18B20.pdf b/HARDWARE/DOC/DS18B20.pdf new file mode 100644 index 0000000..52dc259 Binary files /dev/null and b/HARDWARE/DOC/DS18B20.pdf differ diff --git a/HARDWARE/DOC/HC-12 english datasheets.pdf b/HARDWARE/DOC/HC-12 english datasheets.pdf new file mode 100644 index 0000000..08b2af9 Binary files /dev/null and b/HARDWARE/DOC/HC-12 english datasheets.pdf differ diff --git a/HARDWARE/DOC/ZC05.pdf b/HARDWARE/DOC/ZC05.pdf new file mode 100644 index 0000000..332cdcc Binary files /dev/null and b/HARDWARE/DOC/ZC05.pdf differ diff --git a/HARDWARE/DOC/ZC13.pdf b/HARDWARE/DOC/ZC13.pdf new file mode 100644 index 0000000..e874a91 Binary files /dev/null and b/HARDWARE/DOC/ZC13.pdf differ diff --git a/HARDWARE/DOC/ZE07-CO.pdf b/HARDWARE/DOC/ZE07-CO.pdf new file mode 100644 index 0000000..e482104 Binary files /dev/null and b/HARDWARE/DOC/ZE07-CO.pdf differ diff --git a/HARDWARE/IMG/db.jpg b/HARDWARE/IMG/db.jpg new file mode 100644 index 0000000..beb01f7 Binary files /dev/null and b/HARDWARE/IMG/db.jpg differ diff --git a/HARDWARE/IMG/display.png b/HARDWARE/IMG/display.png new file mode 100644 index 0000000..9468e0f Binary files /dev/null and b/HARDWARE/IMG/display.png differ diff --git a/HARDWARE/ProProject_Danger-alarm_2024-03-21.epro b/HARDWARE/ProProject_Danger-alarm_2024-03-21.epro new file mode 100644 index 0000000..5ce0797 Binary files /dev/null and b/HARDWARE/ProProject_Danger-alarm_2024-03-21.epro differ diff --git a/README.md b/README.md new file mode 100644 index 0000000..e32e5fa --- /dev/null +++ b/README.md @@ -0,0 +1,45 @@ +# 基于 Raspberry Pico / Pico W 的厨房危险(火灾)报警 （Pico W WiFi传输暂时不玩） + * 使用 DS18B20温度传感器 + * 使用 CH4 N55A甲烷气体传感器(进口) (弃用) + * 使用 PASCO2V01 CO2二氧化碳传感器模块(进口模块暂时买不到！) + * 使用 MH-Z14B CO2二氧化碳传感器模块(国产)(0 - 5000ppm) + * 使用 ZE07-CO CO一氧化碳传感器模块(国产) + * 使用 HC-12 433MHZ传感器模块(国产) + * 使用 ZC05/ZC13 可燃气体(天然气 CH4)传感器模块(国产) + +## Build +``` + # 使用WSL Debian GNU/Linux 12 (bookworm) 构建 + # 确保Pico-SDK环境变量 + export PICO_SDK_PATH=/mnt/c/Users/niuyuling/Desktop/raspberry-pico/SDK/pico-sdk + export PICO_EXTRAS_PATH=/mnt/c/Users/niuyuling/Desktop/raspberry-pico/SDK/pico-extras + + apt install cmake gcc-arm-none-eabi gcc g++ + apt install gdb-multiarch automake autoconf build-essential texinfo libtool libftdi-dev libusb-1.0-0-dev + + git clone https://git.aixiao.me/aixiao/Danger-alarm.git + cd Danger-alarm + git submodule init + git submodule update + mkdir -p SOFTWARE/build + cd SOFTWARE/build + #cmake .. + cmake -DPICO_BOARD=pico_w .. + make + + + # 树莓派Zero W 433MHZ HC-12接收服务端构建 + apt install libmysqlclient-dev + cd ~ + git clone https://github.com/WiringPi/WiringPi.git + cd WiringPi + ./build + cd ~/Danger-alarm/SOFTWARE/Server/hc-12 + make clean; make + ./hc-12 + +``` +## display +![brief](HARDWARE/IMG/db.jpg) +![brief](HARDWARE/IMG/display.png) + diff --git a/SOFTWARE-FreeRTOS/CMakeLists.txt b/SOFTWARE-FreeRTOS/CMakeLists.txt new file mode 100644 index 0000000..b9b10b2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/CMakeLists.txt @@ -0,0 +1,79 @@ +cmake_minimum_required(VERSION 3.12) + +# Check if the environment variable PICO_SDK_PATH is set +if(DEFINED ENV{PICO_SDK_PATH}) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) +else() + message(FATAL_ERROR "Environment variable PICO_SDK_PATH is not set. Please set it to the path of the pico-sdk.") +endif() + +# Include the Pico SDK +include(pico_sdk_import.cmake) + +# Pull in FreeRTOS +set( FREERTOS_KERNEL_PATH "../FreeRTOS-Kernel" ) +include(FreeRTOS_Kernel_import.cmake) + +project(main CXX C ASM) +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) + +pico_sdk_init() + + +add_subdirectory( + ../SOFTWARE/Lib/pico-onewire + ${CMAKE_BINARY_DIR}/pico-onewire +) + + +add_executable( + main + ) + +pico_generate_pio_header(main ${CMAKE_CURRENT_LIST_DIR}/Source/uart_tx.pio) +pico_generate_pio_header(main ${CMAKE_CURRENT_LIST_DIR}/Source/uart_rx.pio) + +target_Sources(main PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/Source/common.c + ${CMAKE_CURRENT_LIST_DIR}/Source/main.c + + ) + +target_include_directories(main PRIVATE + ${CMAKE_CURRENT_LIST_DIR} + ${CMAKE_CURRENT_LIST_DIR}/Source + ${CMAKE_CURRENT_LIST_DIR}/Common/include + ) + +target_compile_options(main PUBLIC + ### Gnu/Clang C Options + $<$:-fdiagnostics-color=always> + $<$:-fcolor-diagnostics> + + $<$:-Wall> + $<$:-Wextra> + #$<$:-Werror> + $<$:-Weverything> + ) + +target_link_libraries( + main + pico_one_wire + FreeRTOS-Kernel + FreeRTOS-Kernel-Heap4 + pico_stdlib + pico_util + pico_runtime + pico_multicore + hardware_rtc + hardware_i2c + hardware_uart + hardware_pwm + hardware_adc + hardware_pio + ) + +pico_enable_stdio_uart(main 1) +pico_enable_stdio_usb(main 1) +pico_add_extra_outputs(main) diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/mpu_demo/mpu_demo.c b/SOFTWARE-FreeRTOS/Common/ARMv8M/mpu_demo/mpu_demo.c new file mode 100644 index 0000000..35407cf --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/mpu_demo/mpu_demo.c @@ -0,0 +1,347 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/** + * @brief Size of the shared memory region. + */ +#define SHARED_MEMORY_SIZE 32 + +/** + * @brief Memory region shared between two tasks. + */ +static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ); +#if ( configTOTAL_MPU_REGIONS == 16 ) + static uint8_t ucSharedMemory1[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ); + static uint8_t ucSharedMemory2[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ); + static uint8_t ucSharedMemory3[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ); + static uint8_t ucSharedMemory4[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ); + static uint8_t ucSharedMemory5[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ); + static uint8_t ucSharedMemory6[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ); + static uint8_t ucSharedMemory7[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ); + static uint8_t ucSharedMemory8[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ); +#endif /* configTOTAL_MPU_REGIONS == 16 */ + +/** + * @brief Memory region used to track Memory Fault intentionally caused by the + * RO Access task. + * + * RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal + * memory. Illegal memory access causes Memory Fault and the fault handler + * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We + * recover gracefully from an expected fault by jumping to the next instruction. + * + * @note We are declaring a region of 32 bytes even though we need only one. The + * reason is that the size of an MPU region must be a multiple of 32 bytes. + */ +static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ) = { 0 }; +/*-----------------------------------------------------------*/ + +/** + * @brief Implements the task which has Read Only access to the memory region + * ucSharedMemory. + * + * @param pvParameters[in] Parameters as passed during task creation. + */ +static void prvROAccessTask( void * pvParameters ); + +/** + * @brief Implements the task which has Read Write access to the memory region + * ucSharedMemory. + * + * @param pvParameters[in] Parameters as passed during task creation. + */ +static void prvRWAccessTask( void * pvParameters ); + +/*-----------------------------------------------------------*/ + +static void prvROAccessTask( void * pvParameters ) +{ + uint8_t ucVal; + + /* Unused parameters. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* This task performs the following sequence for all the shared memory + * regions: + * + * 1. Perfrom a read access to the shared memory. Since this task has + * RO access to the shared memory, the read operation is successful. + * + * 2. Set ucROTaskFaultTracker[ 0 ] to 1 before performing a write to + * the shared memory. Since this task has Read Only access to the + * shared memory, the write operation would result in a Memory Fault. + * Setting ucROTaskFaultTracker[ 0 ] to 1 tells the Memory Fault + * Handler that this is an expected fault. The handler recovers from + * the expected fault gracefully by jumping to the next instruction. + * + * 3. Perfrom a write to the shared memory resulting in a memory fault. + * + * 4. Ensure that the write access did generate MemFault and the fault + * handler did clear the ucROTaskFaultTracker[ 0 ]. + */ + /* Perform the above mentioned sequence on ucSharedMemory. */ + ucVal = ucSharedMemory[ 0 ]; + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + ucROTaskFaultTracker[ 0 ] = 1; + ucSharedMemory[ 0 ] = 0; + configASSERT( ucROTaskFaultTracker[ 0 ] == 0 ); + + #if ( configTOTAL_MPU_REGIONS == 16 ) + { + /* Perform the above mentioned sequence on ucSharedMemory1. */ + ucVal = ucSharedMemory1[ 0 ]; + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + ucROTaskFaultTracker[ 0 ] = 1; + ucSharedMemory1[ 0 ] = 0; + configASSERT( ucROTaskFaultTracker[ 0 ] == 0 ); + + /* Perform the above mentioned sequence on ucSharedMemory2. */ + ucVal = ucSharedMemory2[ 0 ]; + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + ucROTaskFaultTracker[ 0 ] = 1; + ucSharedMemory2[ 0 ] = 0; + configASSERT( ucROTaskFaultTracker[ 0 ] == 0 ); + + /* Perform the above mentioned sequence on ucSharedMemory3. */ + ucVal = ucSharedMemory3[ 0 ]; + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + ucROTaskFaultTracker[ 0 ] = 1; + ucSharedMemory3[ 0 ] = 0; + configASSERT( ucROTaskFaultTracker[ 0 ] == 0 ); + + /* Perform the above mentioned sequence on ucSharedMemory4. */ + ucVal = ucSharedMemory4[ 0 ]; + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + ucROTaskFaultTracker[ 0 ] = 1; + ucSharedMemory4[ 0 ] = 0; + configASSERT( ucROTaskFaultTracker[ 0 ] == 0 ); + + /* Perform the above mentioned sequence on ucSharedMemory5. */ + ucVal = ucSharedMemory5[ 0 ]; + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + ucROTaskFaultTracker[ 0 ] = 1; + ucSharedMemory5[ 0 ] = 0; + configASSERT( ucROTaskFaultTracker[ 0 ] == 0 ); + + /* Perform the above mentioned sequence on ucSharedMemory6. */ + ucVal = ucSharedMemory6[ 0 ]; + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + ucROTaskFaultTracker[ 0 ] = 1; + ucSharedMemory6[ 0 ] = 0; + configASSERT( ucROTaskFaultTracker[ 0 ] == 0 ); + + /* Perform the above mentioned sequence on ucSharedMemory7. */ + ucVal = ucSharedMemory7[ 0 ]; + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + ucROTaskFaultTracker[ 0 ] = 1; + ucSharedMemory7[ 0 ] = 0; + configASSERT( ucROTaskFaultTracker[ 0 ] == 0 ); + + /* Perform the above mentioned sequence on ucSharedMemory8. */ + ucVal = ucSharedMemory8[ 0 ]; + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + ucROTaskFaultTracker[ 0 ] = 1; + ucSharedMemory8[ 0 ] = 0; + configASSERT( ucROTaskFaultTracker[ 0 ] == 0 ); + } + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + /* Wait for a second. */ + vTaskDelay( pdMS_TO_TICKS( 1000 ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRWAccessTask( void * pvParameters ) +{ + /* Unused parameters. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* This task has RW access to ucSharedMemory and therefore can write to + * it. */ + ucSharedMemory[ 0 ] = 0; + + #if ( configTOTAL_MPU_REGIONS == 16 ) + { + ucSharedMemory1[ 0 ] = 0; + ucSharedMemory2[ 0 ] = 0; + ucSharedMemory3[ 0 ] = 0; + ucSharedMemory4[ 0 ] = 0; + ucSharedMemory5[ 0 ] = 0; + ucSharedMemory6[ 0 ] = 0; + ucSharedMemory7[ 0 ] = 0; + ucSharedMemory8[ 0 ] = 0; + } + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + /* Wait for a second. */ + vTaskDelay( pdMS_TO_TICKS( 1000 ) ); + } +} +/*-----------------------------------------------------------*/ + +void vStartMPUDemo( void ) +{ + static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); + static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); + TaskParameters_t xROAccessTaskParameters = + { + .pvTaskCode = prvROAccessTask, + .pcName = "ROAccess", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = tskIDLE_PRIORITY, + .puxStackBuffer = xROAccessTaskStack, + .xRegions = + { + { ( void * ) ucSharedMemory, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER }, + #if ( configTOTAL_MPU_REGIONS == 16 ) + { ( void * ) ucSharedMemory1, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory2, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory3, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory4, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory5, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory6, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory7, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory8, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + { ( void * ) ucROTaskFaultTracker, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + { 0, 0, 0 }, + } + }; + TaskParameters_t xRWAccessTaskParameters = + { + .pvTaskCode = prvRWAccessTask, + .pcName = "RWAccess", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = tskIDLE_PRIORITY, + .puxStackBuffer = xRWAccessTaskStack, + .xRegions = + { + { ( void * ) ucSharedMemory, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + #if ( configTOTAL_MPU_REGIONS == 16 ) + { ( void * ) ucSharedMemory1, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory2, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory3, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory4, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory5, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory6, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory7, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucSharedMemory8, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + #endif /* configTOTAL_MPU_REGIONS == 16 */ + { 0, 0, 0 }, + { 0, 0, 0 }, + } + }; + + /* Create an unprivileged task with RO access to ucSharedMemory. */ + xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL ); + + /* Create an unprivileged task with RW access to ucSharedMemory. */ + xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL ); +} +/*-----------------------------------------------------------*/ + +portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress ) +{ + uint32_t ulPC; + uint16_t usOffendingInstruction; + + /* Is this an expected fault? */ + if( ucROTaskFaultTracker[ 0 ] == 1 ) + { + /* Read program counter. */ + ulPC = pulFaultStackAddress[ 6 ]; + + /* Read the offending instruction. */ + usOffendingInstruction = *( uint16_t * ) ulPC; + + /* From ARM docs: + * If the value of bits[15:11] of the halfword being decoded is one of + * the following, the halfword is the first halfword of a 32-bit + * instruction: + * - 0b11101. + * - 0b11110. + * - 0b11111. + * Otherwise, the halfword is a 16-bit instruction. + */ + + /* Extract bits[15:11] of the offending instruction. */ + usOffendingInstruction = usOffendingInstruction & 0xF800; + usOffendingInstruction = ( usOffendingInstruction >> 11 ); + + /* Determine if the offending instruction is a 32-bit instruction or + * a 16-bit instruction. */ + if( ( usOffendingInstruction == 0x001F ) || + ( usOffendingInstruction == 0x001E ) || + ( usOffendingInstruction == 0x001D ) ) + { + /* Since the offending instruction is a 32-bit instruction, + * increment the program counter by 4 to move to the next + * instruction. */ + ulPC += 4; + } + else + { + /* Since the offending instruction is a 16-bit instruction, + * increment the program counter by 2 to move to the next + * instruction. */ + ulPC += 2; + } + + /* Save the new program counter on the stack. */ + pulFaultStackAddress[ 6 ] = ulPC; + + /* Mark the fault as handled. */ + ucROTaskFaultTracker[ 0 ] = 0; + } + else + { + /* This is an unexpected fault - loop forever. */ + for( ; ; ) + { + } + } +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/mpu_demo/mpu_demo.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/mpu_demo/mpu_demo.h new file mode 100644 index 0000000..cef2060 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/mpu_demo/mpu_demo.h @@ -0,0 +1,44 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __MPU_DEMO_H__ +#define __MPU_DEMO_H__ + +/** + * @brief Creates all the tasks for MPU demo. + * + * The MPU demo creates 2 unprivileged tasks - One of which has Read Only access + * to a shared memory region while the other has Read Write access. The task + * with Read Only access then tries to write to the shared memory which results + * in a Memory fault. The fault handler examines that it is the fault generated + * by the task with Read Only access and if so, it recovers from the fault + * gracefully by moving the Program Counter to the next instruction to the one + * which generated the fault. If any other memory access violation occurs, the + * fault handler will get stuck in an infinite loop. + */ +void vStartMPUDemo( void ); + +#endif /* __MPU_DEMO_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/non_secure/reg_test_asm.c b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/non_secure/reg_test_asm.c new file mode 100644 index 0000000..214b9bf --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/non_secure/reg_test_asm.c @@ -0,0 +1,312 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * "Reg tests" - These tests fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + +#include "reg_test_asm.h" +/*-----------------------------------------------------------*/ + +void vRegTest1Asm_NonSecure( void ) /* __attribute__(( naked )) */ +{ + __asm volatile + ( + ".extern ulRegTest1LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r1, #101 \n" + " movs r2, #102 \n" + " movs r3, #103 \n" + " movs r4, #104 \n" + " movs r5, #105 \n" + " movs r6, #106 \n" + " movs r7, #107 \n" + " movs r0, #108 \n" + " mov r8, r0 \n" + " movs r0, #109 \n" + " mov r9, r0 \n" + " movs r0, #110 \n" + " mov r10, r0 \n" + " movs r0, #111 \n" + " mov r11, r0 \n" + " movs r0, #112 \n" + " mov r12, r0 \n" + " movs r0, #100 \n" + " \n" + "reg1_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #100 \n" + " bne reg1_error_loop \n" + " cmp r1, #101 \n" + " bne reg1_error_loop \n" + " cmp r2, #102 \n" + " bne reg1_error_loop \n" + " cmp r3, #103 \n" + " bne reg1_error_loop \n" + " cmp r4, #104 \n" + " bne reg1_error_loop \n" + " cmp r5, #105 \n" + " bne reg1_error_loop \n" + " cmp r6, #106 \n" + " bne reg1_error_loop \n" + " cmp r7, #107 \n" + " bne reg1_error_loop \n" + " movs r0, #108 \n" + " cmp r8, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #109 \n" + " cmp r9, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #110 \n" + " cmp r10, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #111 \n" + " cmp r11, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #112 \n" + " cmp r12, r0 \n" + " bne reg1_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r1 } \n" + " ldr r0, =ulRegTest1LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " \n" + " /* Yield to increase test coverage. */ \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe000ed04 \n" /* NVIC_ICSR. */ + " lsls r0, #28 \n" /* Shift to PendSV bit. */ + " str r0, [r1] \n" + " dsb \n" + " pop { r1 } \n" + " \n" + " /* Start again. */ \n" + " movs r0, #100 \n" + " b reg1_loop \n" + " \n" + "reg1_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg1_error_loop \n" + " nop \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTest2Asm_NonSecure( void ) /* __attribute__(( naked )) */ +{ + __asm volatile + ( + ".extern ulRegTest2LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r1, #1 \n" + " movs r2, #2 \n" + " movs r3, #3 \n" + " movs r4, #4 \n" + " movs r5, #5 \n" + " movs r6, #6 \n" + " movs r7, #7 \n" + " movs r0, #8 \n" + " mov r8, r0 \n" + " movs r0, #9 \n" + " mov r9, r0 \n" + " movs r0, #10 \n" + " mov r10, r0 \n" + " movs r0, #11 \n" + " mov r11, r0 \n" + " movs r0, #12 \n" + " mov r12, r0 \n" + " movs r0, #10 \n" + " \n" + "reg2_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #10 \n" + " bne reg2_error_loop \n" + " cmp r1, #1 \n" + " bne reg2_error_loop \n" + " cmp r2, #2 \n" + " bne reg2_error_loop \n" + " cmp r3, #3 \n" + " bne reg2_error_loop \n" + " cmp r4, #4 \n" + " bne reg2_error_loop \n" + " cmp r5, #5 \n" + " bne reg2_error_loop \n" + " cmp r6, #6 \n" + " bne reg2_error_loop \n" + " cmp r7, #7 \n" + " bne reg2_error_loop \n" + " movs r0, #8 \n" + " cmp r8, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #9 \n" + " cmp r9, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #10 \n" + " cmp r10, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #11 \n" + " cmp r11, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #12 \n" + " cmp r12, r0 \n" + " bne reg2_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r1 } \n" + " ldr r0, =ulRegTest2LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r1 } \n" + " \n" + " /* Start again. */ \n" + " movs r0, #10 \n" + " b reg2_loop \n" + " \n" + "reg2_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg2_error_loop \n" + " nop \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTestAsm_NonSecureCallback( void ) +{ + __asm volatile + ( + ".syntax unified \n" + " \n" + " /* Store callee saved registers. */ \n" + " push { r4-r7 } \n" + " mov r0, r8 \n" + " mov r1, r9 \n" + " mov r2, r10 \n" + " mov r3, r11 \n" + " mov r4, r12 \n" + " push { r0-r4 } \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r1, #151 \n" + " movs r2, #152 \n" + " movs r3, #153 \n" + " movs r4, #154 \n" + " movs r5, #155 \n" + " movs r6, #156 \n" + " movs r7, #157 \n" + " movs r0, #158 \n" + " mov r8, r0 \n" + " movs r0, #159 \n" + " mov r9, r0 \n" + " movs r0, #160 \n" + " mov r10, r0 \n" + " movs r0, #161 \n" + " mov r11, r0 \n" + " movs r0, #162 \n" + " mov r12, r0 \n" + " movs r0, #150 \n" + " \n" + " /* Force a context switch by pending non-secure sv. */ \n" + " push { r0, r1 } \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe000ed04 \n" /* NVIC_ICSR. */ + " lsls r0, #28 \n" /* Shift to PendSV bit. */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0, r1 } \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #150 \n" + " bne reg_nscb_error_loop \n" + " cmp r1, #151 \n" + " bne reg_nscb_error_loop \n" + " cmp r2, #152 \n" + " bne reg_nscb_error_loop \n" + " cmp r3, #153 \n" + " bne reg_nscb_error_loop \n" + " cmp r4, #154 \n" + " bne reg_nscb_error_loop \n" + " cmp r5, #155 \n" + " bne reg_nscb_error_loop \n" + " cmp r6, #156 \n" + " bne reg_nscb_error_loop \n" + " cmp r7, #157 \n" + " bne reg_nscb_error_loop \n" + " movs r0, #158 \n" + " cmp r8, r0 \n" + " bne reg_nscb_error_loop \n" + " movs r0, #159 \n" + " cmp r9, r0 \n" + " bne reg_nscb_error_loop \n" + " movs r0, #160 \n" + " cmp r10, r0 \n" + " bne reg_nscb_error_loop \n" + " movs r0, #161 \n" + " cmp r11, r0 \n" + " bne reg_nscb_error_loop \n" + " movs r0, #162 \n" + " cmp r12, r0 \n" + " bne reg_nscb_error_loop \n" + " \n" + " /* Everything passed, finish. */ \n" + " b reg_nscb_success \n" + " \n" + "reg_nscb_error_loop : \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg_nscb_error_loop \n" + " nop \n" + " \n" + "reg_nscb_success: \n" + " /* Restore callee saved registers. */ \n" + " pop { r0-r4 } \n" + " mov r8, r0 \n" + " mov r9, r1 \n" + " mov r10, r2 \n" + " mov r11, r3 \n" + " mov r12, r4 \n" + " pop { r4-r7 } \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/non_secure/reg_test_asm.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/non_secure/reg_test_asm.h new file mode 100644 index 0000000..6d45c27 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/non_secure/reg_test_asm.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef REG_TEST_ASM_H +#define REG_TEST_ASM_H + +/** + * @brief Functions that implement reg tests in assembly. + * + * These are called from the FreeRTOS tasks on the non-secure side. + */ +void vRegTest1Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest2Asm_NonSecure( void ) __attribute__( ( naked ) ); + +/** + * @brief Function that implements reg tests in assembly. + * + * This is passed as function pointer to the secure side and called + * from the secure side. + */ +void vRegTestAsm_NonSecureCallback( void ); + +#endif /* REG_TEST_ASM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/secure/secure_reg_test_asm.c b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/secure/secure_reg_test_asm.c new file mode 100644 index 0000000..8ef5abf --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/secure/secure_reg_test_asm.c @@ -0,0 +1,151 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Interface includes. */ +#include "secure_reg_test_asm.h" + +/* FreeRTOS includes. */ +#include "secure_port_macros.h" + +/* typedef for non-secure callback function. */ +typedef RegTestCallback_t NonSecureRegTestCallback_t __attribute__( ( cmse_nonsecure_call ) ); +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTestAsm_Secure( void ) +{ + __asm volatile + ( + ".syntax unified \n" + " \n" + " /* Store callee saved registers. */ \n" + " push { r4-r7 } \n" + " mov r0, r8 \n" + " mov r1, r9 \n" + " mov r2, r10 \n" + " mov r3, r11 \n" + " mov r4, r12 \n" + " push { r0-r4 } \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r1, #201 \n" + " movs r2, #202 \n" + " movs r3, #203 \n" + " movs r4, #204 \n" + " movs r5, #205 \n" + " movs r6, #206 \n" + " movs r7, #207 \n" + " movs r0, #208 \n" + " mov r8, r0 \n" + " movs r0, #209 \n" + " mov r9, r0 \n" + " movs r0, #210 \n" + " mov r10, r0 \n" + " movs r0, #211 \n" + " mov r11, r0 \n" + " movs r0, #212 \n" + " mov r12, r0 \n" + " movs r0, #200 \n" + " \n" + " /* Force a context switch by pending non-secure sv. */ \n" + " push { r0, r1 } \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe002ed04 \n" /* NVIC_ICSR_NS. */ + " lsls r0, #28 \n" /* Shift to PendSV bit. */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0, r1 } \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #200 \n" + " bne secure_reg_test_error_loop \n" + " cmp r1, #201 \n" + " bne secure_reg_test_error_loop \n" + " cmp r2, #202 \n" + " bne secure_reg_test_error_loop \n" + " cmp r3, #203 \n" + " bne secure_reg_test_error_loop \n" + " cmp r4, #204 \n" + " bne secure_reg_test_error_loop \n" + " cmp r5, #205 \n" + " bne secure_reg_test_error_loop \n" + " cmp r6, #206 \n" + " bne secure_reg_test_error_loop \n" + " cmp r7, #207 \n" + " bne secure_reg_test_error_loop \n" + " movs r0, #208 \n" + " cmp r8, r0 \n" + " bne secure_reg_test_error_loop \n" + " movs r0, #209 \n" + " cmp r9, r0 \n" + " bne secure_reg_test_error_loop \n" + " movs r0, #210 \n" + " cmp r10, r0 \n" + " bne secure_reg_test_error_loop \n" + " movs r0, #211 \n" + " cmp r11, r0 \n" + " bne secure_reg_test_error_loop \n" + " movs r0, #212 \n" + " cmp r12, r0 \n" + " bne secure_reg_test_error_loop \n" + " \n" + " /* Everything passed, finish. */ \n" + " b secure_reg_test_success \n" + " \n" + "secure_reg_test_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b secure_reg_test_error_loop \n" + " nop \n" + " \n" + "secure_reg_test_success: \n" + " /* Restore callee saved registers. */ \n" + " pop { r0-r4 } \n" + " mov r8, r0 \n" + " mov r9, r1 \n" + " mov r10, r2 \n" + " mov r11, r3 \n" + " mov r12, r4 \n" + " pop { r4-r7 } \n" + ); +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ) +{ + NonSecureRegTestCallback_t pxNonSecureRegTestCallback; + + /* Return function pointer with cleared LSB. */ + pxNonSecureRegTestCallback = ( NonSecureRegTestCallback_t ) cmse_nsfptr_create( pxRegTestCallback ); + + /* Invoke the callback which runs reg tests. */ + pxNonSecureRegTestCallback(); +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/secure/secure_reg_test_asm.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/secure/secure_reg_test_asm.h new file mode 100644 index 0000000..f424f0b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM23/secure/secure_reg_test_asm.h @@ -0,0 +1,49 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SECURE_REG_TEST_ASM_H +#define SECURE_REG_TEST_ASM_H + +/* Callback function pointer definition. */ +typedef void ( * RegTestCallback_t )( void ); + +/** + * @brief Function that implements reg tests for the secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side. + */ +void vRegTestAsm_Secure( void ); + +/** + * @brief Invokes the supplied reg test callback on the non-secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side.. + */ +void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ); + +#endif /* SECURE_REG_TEST_ASM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.c b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.c new file mode 100644 index 0000000..58c1e8f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.c @@ -0,0 +1,1220 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * "Reg tests" - These tests fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + +#include "reg_test_asm.h" +/*-----------------------------------------------------------*/ + +void vRegTest1Asm_NonSecure( void ) /* __attribute__(( naked )) */ +{ + __asm volatile + ( + ".extern ulRegTest1LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #100 \n" + " movs r1, #101 \n" + " movs r2, #102 \n" + " movs r3, #103 \n" + " movs r4, #104 \n" + " movs r5, #105 \n" + " movs r6, #106 \n" + " movs r7, #107 \n" + " mov r8, #108 \n" + " mov r9, #109 \n" + " mov r10, #110 \n" + " mov r11, #111 \n" + " mov r12, #112 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s1, #1.5 \n" + " vmov.f32 s2, #2.5 \n" + " vmov.f32 s3, #3.5 \n" + " vmov.f32 s4, #4.5 \n" + " vmov.f32 s5, #5.5 \n" + " vmov.f32 s6, #6.5 \n" + " vmov.f32 s7, #7.5 \n" + " vmov.f32 s8, #8.5 \n" + " vmov.f32 s9, #9.5 \n" + " vmov.f32 s10, #10.5 \n" + " vmov.f32 s11, #11.5 \n" + " vmov.f32 s12, #12.5 \n" + " vmov.f32 s13, #13.5 \n" + " vmov.f32 s14, #14.5 \n" + " vmov.f32 s15, #1.0 \n" + " vmov.f32 s16, #2.0 \n" + " vmov.f32 s17, #3.0 \n" + " vmov.f32 s18, #4.0 \n" + " vmov.f32 s19, #5.0 \n" + " vmov.f32 s20, #6.0 \n" + " vmov.f32 s21, #7.0 \n" + " vmov.f32 s22, #8.0 \n" + " vmov.f32 s23, #9.0 \n" + " vmov.f32 s24, #10.0 \n" + " vmov.f32 s25, #11.0 \n" + " vmov.f32 s26, #12.0 \n" + " vmov.f32 s27, #13.0 \n" + " vmov.f32 s28, #14.0 \n" + " vmov.f32 s29, #1.5 \n" + " vmov.f32 s30, #2.5 \n" + " vmov.f32 s31, #3.5 \n" + " \n" + "reg1_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #100 \n" + " bne reg1_error_loop \n" + " cmp r1, #101 \n" + " bne reg1_error_loop \n" + " cmp r2, #102 \n" + " bne reg1_error_loop \n" + " cmp r3, #103 \n" + " bne reg1_error_loop \n" + " cmp r4, #104 \n" + " bne reg1_error_loop \n" + " cmp r5, #105 \n" + " bne reg1_error_loop \n" + " cmp r6, #106 \n" + " bne reg1_error_loop \n" + " cmp r7, #107 \n" + " bne reg1_error_loop \n" + " cmp r8, #108 \n" + " bne reg1_error_loop \n" + " cmp r9, #109 \n" + " bne reg1_error_loop \n" + " cmp r10, #110 \n" + " bne reg1_error_loop \n" + " cmp r11, #111 \n" + " bne reg1_error_loop \n" + " cmp r12, #112 \n" + " bne reg1_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s0, #1.5 \n" /* s0 = 1.5. */ + " vcmp.f32 s1, s0 \n" /* Compare s0 and s1. */ + " vmrs APSR_nzcv, FPSCR \n" /* Copy floating point flags (FPSCR flags) to ASPR flags - needed for next bne to work. */ + " bne reg1_error_loop \n" + " vmov.f32 s0, #2.5 \n" + " vcmp.f32 s2, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #3.5 \n" + " vcmp.f32 s3, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #4.5 \n" + " vcmp.f32 s4, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #5.5 \n" + " vcmp.f32 s5, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #6.5 \n" + " vcmp.f32 s6, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #7.5 \n" + " vcmp.f32 s7, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #8.5 \n" + " vcmp.f32 s8, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #9.5 \n" + " vcmp.f32 s9, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #10.5 \n" + " vcmp.f32 s10, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #11.5 \n" + " vcmp.f32 s11, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #12.5 \n" + " vcmp.f32 s12, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #13.5 \n" + " vcmp.f32 s13, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #14.5 \n" + " vcmp.f32 s14, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #1.0 \n" + " vcmp.f32 s15, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #2.0 \n" + " vcmp.f32 s16, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #3.0 \n" + " vcmp.f32 s17, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #4.0 \n" + " vcmp.f32 s18, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #5.0 \n" + " vcmp.f32 s19, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #6.0 \n" + " vcmp.f32 s20, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #7.0 \n" + " vcmp.f32 s21, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #8.0 \n" + " vcmp.f32 s22, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #9.0 \n" + " vcmp.f32 s23, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #10.0 \n" + " vcmp.f32 s24, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #11.0 \n" + " vcmp.f32 s25, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #12.0 \n" + " vcmp.f32 s26, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #13.0 \n" + " vcmp.f32 s27, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #14.0 \n" + " vcmp.f32 s28, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #1.5 \n" + " vcmp.f32 s29, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #2.5 \n" + " vcmp.f32 s30, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " vmov.f32 s0, #3.5 \n" + " vcmp.f32 s31, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg1_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r0, r1 } \n" + " ldr r0, =ulRegTest1LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " \n" + " /* Yield to increase test coverage. */ \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe000ed04 \n" /* NVIC_ICSR. */ + " lsls r0, #28 \n" /* Shift to PendSV bit. */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0, r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg1_loop \n" + " \n" + "reg1_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg1_error_loop \n" + " nop \n" + ".ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTest2Asm_NonSecure( void ) /* __attribute__(( naked )) */ +{ + __asm volatile + ( + ".extern ulRegTest2LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #0 \n" + " movs r1, #1 \n" + " movs r2, #2 \n" + " movs r3, #3 \n" + " movs r4, #4 \n" + " movs r5, #5 \n" + " movs r6, #6 \n" + " movs r7, #7 \n" + " mov r8, #8 \n" + " mov r9, #9 \n" + " movs r10, #10 \n" + " movs r11, #11 \n" + " movs r12, #12 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s1, #1.0 \n" + " vmov.f32 s2, #2.0 \n" + " vmov.f32 s3, #3.0 \n" + " vmov.f32 s4, #4.0 \n" + " vmov.f32 s5, #5.0 \n" + " vmov.f32 s6, #6.0 \n" + " vmov.f32 s7, #7.0 \n" + " vmov.f32 s8, #8.0 \n" + " vmov.f32 s9, #9.0 \n" + " vmov.f32 s10, #10.0 \n" + " vmov.f32 s11, #11.0 \n" + " vmov.f32 s12, #12.0 \n" + " vmov.f32 s13, #13.0 \n" + " vmov.f32 s14, #14.0 \n" + " vmov.f32 s15, #1.5 \n" + " vmov.f32 s16, #2.5 \n" + " vmov.f32 s17, #3.5 \n" + " vmov.f32 s18, #4.5 \n" + " vmov.f32 s19, #5.5 \n" + " vmov.f32 s20, #6.5 \n" + " vmov.f32 s21, #7.5 \n" + " vmov.f32 s22, #8.5 \n" + " vmov.f32 s23, #9.5 \n" + " vmov.f32 s24, #10.5 \n" + " vmov.f32 s25, #11.5 \n" + " vmov.f32 s26, #12.5 \n" + " vmov.f32 s27, #13.5 \n" + " vmov.f32 s28, #14.5 \n" + " vmov.f32 s29, #1.0 \n" + " vmov.f32 s30, #2.0 \n" + " vmov.f32 s31, #3.0 \n" + " \n" + "reg2_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #0 \n" + " bne reg2_error_loop \n" + " cmp r1, #1 \n" + " bne reg2_error_loop \n" + " cmp r2, #2 \n" + " bne reg2_error_loop \n" + " cmp r3, #3 \n" + " bne reg2_error_loop \n" + " cmp r4, #4 \n" + " bne reg2_error_loop \n" + " cmp r5, #5 \n" + " bne reg2_error_loop \n" + " cmp r6, #6 \n" + " bne reg2_error_loop \n" + " cmp r7, #7 \n" + " bne reg2_error_loop \n" + " cmp r8, #8 \n" + " bne reg2_error_loop \n" + " cmp r9, #9 \n" + " bne reg2_error_loop \n" + " cmp r10, #10 \n" + " bne reg2_error_loop \n" + " cmp r11, #11 \n" + " bne reg2_error_loop \n" + " cmp r12, #12 \n" + " bne reg2_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s0, #1.0 \n" + " vcmp.f32 s1, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #2.0 \n" + " vcmp.f32 s2, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #3.0 \n" + " vcmp.f32 s3, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #4.0 \n" + " vcmp.f32 s4, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #5.0 \n" + " vcmp.f32 s5, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #6.0 \n" + " vcmp.f32 s6, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #7.0 \n" + " vcmp.f32 s7, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #8.0 \n" + " vcmp.f32 s8, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #9.0 \n" + " vcmp.f32 s9, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #10.0 \n" + " vcmp.f32 s10, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #11.0 \n" + " vcmp.f32 s11, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #12.0 \n" + " vcmp.f32 s12, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #13.0 \n" + " vcmp.f32 s13, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #14.0 \n" + " vcmp.f32 s14, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #1.5 \n" + " vcmp.f32 s15, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #2.5 \n" + " vcmp.f32 s16, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #3.5 \n" + " vcmp.f32 s17, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #4.5 \n" + " vcmp.f32 s18, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #5.5 \n" + " vcmp.f32 s19, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #6.5 \n" + " vcmp.f32 s20, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #7.5 \n" + " vcmp.f32 s21, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #8.5 \n" + " vcmp.f32 s22, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #9.5 \n" + " vcmp.f32 s23, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #10.5 \n" + " vcmp.f32 s24, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #11.5 \n" + " vcmp.f32 s25, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #12.5 \n" + " vcmp.f32 s26, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #13.5 \n" + " vcmp.f32 s27, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #14.5 \n" + " vcmp.f32 s28, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #1.0 \n" + " vcmp.f32 s29, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #2.0 \n" + " vcmp.f32 s30, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " vmov.f32 s0, #3.0 \n" + " vcmp.f32 s31, s0 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg2_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r0, r1 } \n" + " ldr r0, =ulRegTest2LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r0, r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg2_loop \n" + " \n" + "reg2_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg2_error_loop \n" + " nop \n" + ".ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTest3Asm_NonSecure( void ) /* __attribute__(( naked )) */ +{ + __asm volatile + ( + ".extern ulRegTest3LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #100 \n" + " movs r1, #101 \n" + " movs r2, #102 \n" + " movs r3, #103 \n" + " movs r4, #104 \n" + " movs r5, #105 \n" + " movs r6, #106 \n" + " movs r7, #107 \n" + " mov r8, #108 \n" + " mov r9, #109 \n" + " mov r10, #110 \n" + " mov r11, #111 \n" + " mov r12, #112 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s0, #1.5 \n" + " vmov.f32 s2, #2.0 \n" + " vmov.f32 s3, #3.5 \n" + " vmov.f32 s4, #4.0 \n" + " vmov.f32 s5, #5.5 \n" + " vmov.f32 s6, #6.0 \n" + " vmov.f32 s7, #7.5 \n" + " vmov.f32 s8, #8.0 \n" + " vmov.f32 s9, #9.5 \n" + " vmov.f32 s10, #10.0 \n" + " vmov.f32 s11, #11.5 \n" + " vmov.f32 s12, #12.0 \n" + " vmov.f32 s13, #13.5 \n" + " vmov.f32 s14, #14.0 \n" + " vmov.f32 s15, #1.5 \n" + " vmov.f32 s16, #2.0 \n" + " vmov.f32 s17, #3.5 \n" + " vmov.f32 s18, #4.0 \n" + " vmov.f32 s19, #5.5 \n" + " vmov.f32 s20, #6.0 \n" + " vmov.f32 s21, #7.5 \n" + " vmov.f32 s22, #8.0 \n" + " vmov.f32 s23, #9.5 \n" + " vmov.f32 s24, #10.0 \n" + " vmov.f32 s25, #11.5 \n" + " vmov.f32 s26, #12.0 \n" + " vmov.f32 s27, #13.5 \n" + " vmov.f32 s28, #14.0 \n" + " vmov.f32 s29, #1.5 \n" + " vmov.f32 s30, #2.0 \n" + " vmov.f32 s31, #3.5 \n" + " \n" + "reg3_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #100 \n" + " bne reg3_error_loop \n" + " cmp r1, #101 \n" + " bne reg3_error_loop \n" + " cmp r2, #102 \n" + " bne reg3_error_loop \n" + " cmp r3, #103 \n" + " bne reg3_error_loop \n" + " cmp r4, #104 \n" + " bne reg3_error_loop \n" + " cmp r5, #105 \n" + " bne reg3_error_loop \n" + " cmp r6, #106 \n" + " bne reg3_error_loop \n" + " cmp r7, #107 \n" + " bne reg3_error_loop \n" + " cmp r8, #108 \n" + " bne reg3_error_loop \n" + " cmp r9, #109 \n" + " bne reg3_error_loop \n" + " cmp r10, #110 \n" + " bne reg3_error_loop \n" + " cmp r11, #111 \n" + " bne reg3_error_loop \n" + " cmp r12, #112 \n" + " bne reg3_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s0, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s2, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s3, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #4.0 \n" + " vcmp.f32 s4, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #5.5 \n" + " vcmp.f32 s5, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #6.0 \n" + " vcmp.f32 s6, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #7.5 \n" + " vcmp.f32 s7, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #8.0 \n" + " vcmp.f32 s8, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #9.5 \n" + " vcmp.f32 s9, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #10.0 \n" + " vcmp.f32 s10, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #11.5 \n" + " vcmp.f32 s11, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #12.0 \n" + " vcmp.f32 s12, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #13.5 \n" + " vcmp.f32 s13, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #14.0 \n" + " vcmp.f32 s14, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s15, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s16, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s17, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #4.0 \n" + " vcmp.f32 s18, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #5.5 \n" + " vcmp.f32 s19, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #6.0 \n" + " vcmp.f32 s20, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #7.5 \n" + " vcmp.f32 s21, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #8.0 \n" + " vcmp.f32 s22, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #9.5 \n" + " vcmp.f32 s23, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #10.0 \n" + " vcmp.f32 s24, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #11.5 \n" + " vcmp.f32 s25, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #12.0 \n" + " vcmp.f32 s26, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #13.5 \n" + " vcmp.f32 s27, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #14.0 \n" + " vcmp.f32 s28, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s29, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s30, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s31, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg3_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r0, r1 } \n" + " ldr r0, =ulRegTest3LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " \n" + " /* Yield to increase test coverage. */ \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe000ed04 \n" /* NVIC_ICSR. */ + " lsls r0, #28 \n" /* Shift to PendSV bit. */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0, r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg3_loop \n" + " \n" + "reg3_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg3_error_loop \n" + " nop \n" + ".ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTest4Asm_NonSecure( void ) /* __attribute__(( naked )) */ +{ + __asm volatile + ( + ".extern ulRegTest4LoopCounter \n" + ".syntax unified \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #0 \n" + " movs r1, #1 \n" + " movs r2, #2 \n" + " movs r3, #3 \n" + " movs r4, #4 \n" + " movs r5, #5 \n" + " movs r6, #6 \n" + " movs r7, #7 \n" + " mov r8, #8 \n" + " mov r9, #9 \n" + " movs r10, #10 \n" + " movs r11, #11 \n" + " movs r12, #12 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s0, #1.5 \n" + " vmov.f32 s2, #2.0 \n" + " vmov.f32 s3, #3.0 \n" + " vmov.f32 s4, #4.5 \n" + " vmov.f32 s5, #5.0 \n" + " vmov.f32 s6, #6.0 \n" + " vmov.f32 s7, #7.5 \n" + " vmov.f32 s8, #8.0 \n" + " vmov.f32 s9, #9.0 \n" + " vmov.f32 s10, #10.5 \n" + " vmov.f32 s11, #11.0 \n" + " vmov.f32 s12, #12.0 \n" + " vmov.f32 s13, #13.5 \n" + " vmov.f32 s14, #14.0 \n" + " vmov.f32 s15, #1.0 \n" + " vmov.f32 s16, #2.5 \n" + " vmov.f32 s17, #3.0 \n" + " vmov.f32 s18, #4.0 \n" + " vmov.f32 s19, #5.5 \n" + " vmov.f32 s20, #6.0 \n" + " vmov.f32 s21, #7.0 \n" + " vmov.f32 s22, #8.5 \n" + " vmov.f32 s23, #9.0 \n" + " vmov.f32 s24, #10.0 \n" + " vmov.f32 s25, #11.5 \n" + " vmov.f32 s26, #12.0 \n" + " vmov.f32 s27, #13.0 \n" + " vmov.f32 s28, #14.5 \n" + " vmov.f32 s29, #1.0 \n" + " vmov.f32 s30, #2.0 \n" + " vmov.f32 s31, #3.5 \n" + " \n" + "reg4_loop: \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #0 \n" + " bne reg4_error_loop \n" + " cmp r1, #1 \n" + " bne reg4_error_loop \n" + " cmp r2, #2 \n" + " bne reg4_error_loop \n" + " cmp r3, #3 \n" + " bne reg4_error_loop \n" + " cmp r4, #4 \n" + " bne reg4_error_loop \n" + " cmp r5, #5 \n" + " bne reg4_error_loop \n" + " cmp r6, #6 \n" + " bne reg4_error_loop \n" + " cmp r7, #7 \n" + " bne reg4_error_loop \n" + " cmp r8, #8 \n" + " bne reg4_error_loop \n" + " cmp r9, #9 \n" + " bne reg4_error_loop \n" + " cmp r10, #10 \n" + " bne reg4_error_loop \n" + " cmp r11, #11 \n" + " bne reg4_error_loop \n" + " cmp r12, #12 \n" + " bne reg4_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s0, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s2, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #3.0 \n" + " vcmp.f32 s3, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #4.5 \n" + " vcmp.f32 s4, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #5.0 \n" + " vcmp.f32 s5, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #6.0 \n" + " vcmp.f32 s6, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #7.5 \n" + " vcmp.f32 s7, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #8.0 \n" + " vcmp.f32 s8, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #9.0 \n" + " vcmp.f32 s9, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #10.5 \n" + " vcmp.f32 s10, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #11.0 \n" + " vcmp.f32 s11, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #12.0 \n" + " vcmp.f32 s12, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #13.5 \n" + " vcmp.f32 s13, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #14.0 \n" + " vcmp.f32 s14, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #1.0 \n" + " vcmp.f32 s15, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #2.5 \n" + " vcmp.f32 s16, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #3.0 \n" + " vcmp.f32 s17, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #4.0 \n" + " vcmp.f32 s18, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #5.5 \n" + " vcmp.f32 s19, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #6.0 \n" + " vcmp.f32 s20, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #7.0 \n" + " vcmp.f32 s21, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #8.5 \n" + " vcmp.f32 s22, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #9.0 \n" + " vcmp.f32 s23, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #10.0 \n" + " vcmp.f32 s24, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #11.5 \n" + " vcmp.f32 s25, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #12.0 \n" + " vcmp.f32 s26, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #13.0 \n" + " vcmp.f32 s27, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #14.5 \n" + " vcmp.f32 s28, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #1.0 \n" + " vcmp.f32 s29, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s30, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s31, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg4_error_loop \n" + " \n" + " /* Everything passed, inc the loop counter. */ \n" + " push { r0, r1 } \n" + " ldr r0, =ulRegTest4LoopCounter \n" + " ldr r1, [r0] \n" + " adds r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r0, r1 } \n" + " \n" + " /* Start again. */ \n" + " b reg4_loop \n" + " \n" + "reg4_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg4_error_loop \n" + " nop \n" + ".ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTestAsm_NonSecureCallback( void ) +{ + __asm volatile + ( + ".syntax unified \n" + " \n" + " /* Store callee saved registers. */ \n" + " push { r4-r12 } \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #150 \n" + " movs r1, #151 \n" + " movs r2, #152 \n" + " movs r3, #153 \n" + " movs r4, #154 \n" + " movs r5, #155 \n" + " movs r6, #156 \n" + " movs r7, #157 \n" + " movs r8, #158 \n" + " movs r9, #159 \n" + " movs r10, #160 \n" + " movs r11, #161 \n" + " movs r12, #162 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s0, #1.0 \n" + " vmov.f32 s2, #2.5 \n" + " vmov.f32 s3, #3.5 \n" + " vmov.f32 s4, #4.0 \n" + " vmov.f32 s5, #5.5 \n" + " vmov.f32 s6, #6.5 \n" + " vmov.f32 s7, #7.0 \n" + " vmov.f32 s8, #8.5 \n" + " vmov.f32 s9, #9.5 \n" + " vmov.f32 s10, #10.0 \n" + " vmov.f32 s11, #11.5 \n" + " vmov.f32 s12, #12.5 \n" + " vmov.f32 s13, #13.0 \n" + " vmov.f32 s14, #14.5 \n" + " vmov.f32 s15, #1.5 \n" + " vmov.f32 s16, #2.0 \n" + " vmov.f32 s17, #3.5 \n" + " vmov.f32 s18, #4.5 \n" + " vmov.f32 s19, #5.0 \n" + " vmov.f32 s20, #6.5 \n" + " vmov.f32 s21, #7.5 \n" + " vmov.f32 s22, #8.0 \n" + " vmov.f32 s23, #9.5 \n" + " vmov.f32 s24, #10.5 \n" + " vmov.f32 s25, #11.0 \n" + " vmov.f32 s26, #12.5 \n" + " vmov.f32 s27, #13.5 \n" + " vmov.f32 s28, #14.0 \n" + " vmov.f32 s29, #1.5 \n" + " vmov.f32 s30, #2.5 \n" + " vmov.f32 s31, #3.0 \n" + " \n" + " /* Force a context switch by pending sv. */ \n" + " push { r0, r1 } \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe000ed04 \n" /* NVIC_ICSR. */ + " lsls r0, #28 \n" /* Shift to PendSV bit. */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0, r1 } \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #150 \n" + " bne reg_nscb_error_loop \n" + " cmp r1, #151 \n" + " bne reg_nscb_error_loop \n" + " cmp r2, #152 \n" + " bne reg_nscb_error_loop \n" + " cmp r3, #153 \n" + " bne reg_nscb_error_loop \n" + " cmp r4, #154 \n" + " bne reg_nscb_error_loop \n" + " cmp r5, #155 \n" + " bne reg_nscb_error_loop \n" + " cmp r6, #156 \n" + " bne reg_nscb_error_loop \n" + " cmp r7, #157 \n" + " bne reg_nscb_error_loop \n" + " cmp r8, #158 \n" + " bne reg_nscb_error_loop \n" + " cmp r9, #159 \n" + " bne reg_nscb_error_loop \n" + " cmp r10, #160 \n" + " bne reg_nscb_error_loop \n" + " cmp r11, #161 \n" + " bne reg_nscb_error_loop \n" + " cmp r12, #162 \n" + " bne reg_nscb_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s1, #1.0 \n" + " vcmp.f32 s0, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #2.5 \n" + " vcmp.f32 s2, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s3, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #4.0 \n" + " vcmp.f32 s4, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #5.5 \n" + " vcmp.f32 s5, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #6.5 \n" + " vcmp.f32 s6, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #7.0 \n" + " vcmp.f32 s7, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #8.5 \n" + " vcmp.f32 s8, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #9.5 \n" + " vcmp.f32 s9, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #10.0 \n" + " vcmp.f32 s10, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #11.5 \n" + " vcmp.f32 s11, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #12.5 \n" + " vcmp.f32 s12, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #13.0 \n" + " vcmp.f32 s13, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #14.5 \n" + " vcmp.f32 s14, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s15, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s16, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s17, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #4.5 \n" + " vcmp.f32 s18, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #5.0 \n" + " vcmp.f32 s19, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #6.5 \n" + " vcmp.f32 s20, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #7.5 \n" + " vcmp.f32 s21, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #8.0 \n" + " vcmp.f32 s22, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #9.5 \n" + " vcmp.f32 s23, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #10.5 \n" + " vcmp.f32 s24, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #11.0 \n" + " vcmp.f32 s25, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #12.5 \n" + " vcmp.f32 s26, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #13.5 \n" + " vcmp.f32 s27, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #14.0 \n" + " vcmp.f32 s28, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s29, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #2.5 \n" + " vcmp.f32 s30, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " vmov.f32 s1, #3.0 \n" + " vcmp.f32 s31, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne reg_nscb_error_loop \n" + " \n" + " /* Everything passed, finish. */ \n" + " b reg_nscb_success \n" + " \n" + "reg_nscb_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b reg_nscb_error_loop \n" + " nop \n" + " \n" + "reg_nscb_success: \n" + " /* Restore callee saved registers. */ \n" + " pop { r4-r12 } \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.h new file mode 100644 index 0000000..3e18a05 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/non_secure/reg_test_asm.h @@ -0,0 +1,48 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef REG_TEST_ASM_H +#define REG_TEST_ASM_H + +/** + * @brief Functions that implement reg tests in assembly. + * + * These are called from the FreeRTOS tasks on the non-secure side. + */ +void vRegTest1Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest2Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest3Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest4Asm_NonSecure( void ) __attribute__( ( naked ) ); + +/** + * @brief Function that implements reg tests in assembly. + * + * This is passed as function pointer to the secure side and called + * from the secure side. + */ +void vRegTestAsm_NonSecureCallback( void ); + +#endif /* REG_TEST_ASM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.c b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.c new file mode 100644 index 0000000..c509d89 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.c @@ -0,0 +1,289 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Interface includes. */ +#include "secure_reg_test_asm.h" + +/* FreeRTOS includes. */ +#include "secure_port_macros.h" + +/* typedef for non-secure callback function. */ +typedef RegTestCallback_t NonSecureRegTestCallback_t __attribute__( ( cmse_nonsecure_call ) ); +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTestAsm_Secure( void ) +{ + __asm volatile + ( + ".syntax unified \n" + " \n" + " /* Store callee saved registers. */ \n" + " push { r4-r12 } \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r0, #200 \n" + " movs r1, #201 \n" + " movs r1, #201 \n" + " movs r2, #202 \n" + " movs r3, #203 \n" + " movs r4, #204 \n" + " movs r5, #205 \n" + " movs r6, #206 \n" + " movs r7, #207 \n" + " movs r8, #208 \n" + " movs r9, #209 \n" + " movs r10, #210 \n" + " movs r11, #211 \n" + " movs r12, #212 \n" + " \n" + " /* Fill the FPU registers with known values. */ \n" + " vmov.f32 s0, #1.0 \n" + " vmov.f32 s2, #2.0 \n" + " vmov.f32 s3, #3.5 \n" + " vmov.f32 s4, #4.5 \n" + " vmov.f32 s5, #5.0 \n" + " vmov.f32 s6, #6.0 \n" + " vmov.f32 s7, #7.5 \n" + " vmov.f32 s8, #8.5 \n" + " vmov.f32 s9, #9.0 \n" + " vmov.f32 s10, #10.0 \n" + " vmov.f32 s11, #11.5 \n" + " vmov.f32 s12, #12.5 \n" + " vmov.f32 s13, #13.0 \n" + " vmov.f32 s14, #14.0 \n" + " vmov.f32 s15, #1.5 \n" + " vmov.f32 s16, #2.5 \n" + " vmov.f32 s17, #3.0 \n" + " vmov.f32 s18, #4.0 \n" + " vmov.f32 s19, #5.5 \n" + " vmov.f32 s20, #6.5 \n" + " vmov.f32 s21, #7.0 \n" + " vmov.f32 s22, #8.0 \n" + " vmov.f32 s23, #9.5 \n" + " vmov.f32 s24, #10.5 \n" + " vmov.f32 s25, #11.0 \n" + " vmov.f32 s26, #12.0 \n" + " vmov.f32 s27, #13.5 \n" + " vmov.f32 s28, #14.5 \n" + " vmov.f32 s29, #1.0 \n" + " vmov.f32 s30, #2.0 \n" + " vmov.f32 s31, #3.5 \n" + " \n" + " /* Force a context switch by pending non-secure sv. */ \n" + " push { r0, r1 } \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe002ed04 \n" /* NVIC_ICSR_NS. */ + " lsls r0, #28 \n" /* Shift to PendSV bit. */ + " str r0, [r1] \n" + " dsb \n" + " pop { r0, r1 } \n" + " \n" + " /* Verify that core registers contain correct values. */ \n" + " cmp r0, #200 \n" + " bne secure_reg_test_error_loop \n" + " cmp r1, #201 \n" + " bne secure_reg_test_error_loop \n" + " cmp r2, #202 \n" + " bne secure_reg_test_error_loop \n" + " cmp r3, #203 \n" + " bne secure_reg_test_error_loop \n" + " cmp r4, #204 \n" + " bne secure_reg_test_error_loop \n" + " cmp r5, #205 \n" + " bne secure_reg_test_error_loop \n" + " cmp r6, #206 \n" + " bne secure_reg_test_error_loop \n" + " cmp r7, #207 \n" + " bne secure_reg_test_error_loop \n" + " cmp r8, #208 \n" + " bne secure_reg_test_error_loop \n" + " cmp r9, #209 \n" + " bne secure_reg_test_error_loop \n" + " cmp r10, #210 \n" + " bne secure_reg_test_error_loop \n" + " cmp r11, #211 \n" + " bne secure_reg_test_error_loop \n" + " cmp r12, #212 \n" + " bne secure_reg_test_error_loop \n" + " \n" + " /* Verify that FPU registers contain correct values. */ \n" + " vmov.f32 s1, #1.0 \n" + " vcmp.f32 s0, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s2, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s3, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #4.5 \n" + " vcmp.f32 s4, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #5.0 \n" + " vcmp.f32 s5, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #6.0 \n" + " vcmp.f32 s6, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #7.5 \n" + " vcmp.f32 s7, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #8.5 \n" + " vcmp.f32 s8, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #9.0 \n" + " vcmp.f32 s9, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #10.0 \n" + " vcmp.f32 s10, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #11.5 \n" + " vcmp.f32 s11, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #12.5 \n" + " vcmp.f32 s12, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #13.0 \n" + " vcmp.f32 s13, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #14.0 \n" + " vcmp.f32 s14, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #1.5 \n" + " vcmp.f32 s15, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #2.5 \n" + " vcmp.f32 s16, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #3.0 \n" + " vcmp.f32 s17, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #4.0 \n" + " vcmp.f32 s18, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #5.5 \n" + " vcmp.f32 s19, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #6.5 \n" + " vcmp.f32 s20, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #7.0 \n" + " vcmp.f32 s21, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #8.0 \n" + " vcmp.f32 s22, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #9.5 \n" + " vcmp.f32 s23, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #10.5 \n" + " vcmp.f32 s24, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #11.0 \n" + " vcmp.f32 s25, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #12.0 \n" + " vcmp.f32 s26, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #13.5 \n" + " vcmp.f32 s27, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #14.5 \n" + " vcmp.f32 s28, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #1.0 \n" + " vcmp.f32 s29, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #2.0 \n" + " vcmp.f32 s30, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " vmov.f32 s1, #3.5 \n" + " vcmp.f32 s31, s1 \n" + " vmrs APSR_nzcv, FPSCR \n" + " bne secure_reg_test_error_loop \n" + " \n" + " /* Everything passed, finish. */ \n" + " b secure_reg_test_success \n" + " \n" + "secure_reg_test_error_loop: \n" + " /* If this line is hit then there was an error in \n" + " * a core register value. The loop ensures the \n" + " * loop counter stops incrementing. */ \n" + " b secure_reg_test_error_loop \n" + " nop \n" + " \n" + "secure_reg_test_success: \n" + " /* Restore callee saved registers. */ \n" + " pop { r4-r12 } \n" + ); +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ) +{ + NonSecureRegTestCallback_t pxNonSecureRegTestCallback; + + /* Return function pointer with cleared LSB. */ + pxNonSecureRegTestCallback = ( NonSecureRegTestCallback_t ) cmse_nsfptr_create( pxRegTestCallback ); + + /* Invoke the callback which runs reg tests. */ + pxNonSecureRegTestCallback(); +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.h new file mode 100644 index 0000000..f424f0b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/GCC/ARM_CM33/secure/secure_reg_test_asm.h @@ -0,0 +1,49 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SECURE_REG_TEST_ASM_H +#define SECURE_REG_TEST_ASM_H + +/* Callback function pointer definition. */ +typedef void ( * RegTestCallback_t )( void ); + +/** + * @brief Function that implements reg tests for the secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side. + */ +void vRegTestAsm_Secure( void ); + +/** + * @brief Invokes the supplied reg test callback on the non-secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side.. + */ +void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ); + +#endif /* SECURE_REG_TEST_ASM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/non_secure/reg_test_asm.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/non_secure/reg_test_asm.h new file mode 100644 index 0000000..6d45c27 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/non_secure/reg_test_asm.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef REG_TEST_ASM_H +#define REG_TEST_ASM_H + +/** + * @brief Functions that implement reg tests in assembly. + * + * These are called from the FreeRTOS tasks on the non-secure side. + */ +void vRegTest1Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest2Asm_NonSecure( void ) __attribute__( ( naked ) ); + +/** + * @brief Function that implements reg tests in assembly. + * + * This is passed as function pointer to the secure side and called + * from the secure side. + */ +void vRegTestAsm_NonSecureCallback( void ); + +#endif /* REG_TEST_ASM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/non_secure/reg_test_asm.s b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/non_secure/reg_test_asm.s new file mode 100644 index 0000000..5d5cd7e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/non_secure/reg_test_asm.s @@ -0,0 +1,298 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * "Reg tests" - These tests fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + + EXTERN ulRegTest1LoopCounter + EXTERN ulRegTest2LoopCounter + + PUBLIC vRegTest1Asm_NonSecure + PUBLIC vRegTest2Asm_NonSecure + PUBLIC vRegTestAsm_NonSecureCallback +/*-----------------------------------------------------------*/ + +vRegTest1Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + movs r0, #108 + mov r8, r0 + movs r0, #109 + mov r9, r0 + movs r0, #110 + mov r10, r0 + movs r0, #111 + mov r11, r0 + movs r0, #112 + mov r12, r0 + movs r0, #100 + + reg1_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + movs r0, #108 + cmp r8, r0 + bne reg1_error_loop + movs r0, #109 + cmp r9, r0 + bne reg1_error_loop + movs r0, #110 + cmp r10, r0 + bne reg1_error_loop + movs r0, #111 + cmp r11, r0 + bne reg1_error_loop + movs r0, #112 + cmp r12, r0 + bne reg1_error_loop + + /* Everything passed, inc the loop counter. */ + push { r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsls r0, r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r1 } + + /* Start again. */ + movs r0, #100 + b reg1_loop + + reg1_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg1_error_loop + nop +/*-----------------------------------------------------------*/ + +vRegTest2Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + movs r0, #8 + mov r8, r0 + movs r0, #9 + mov r9, r0 + movs r0, #10 + mov r10, r0 + movs r0, #11 + mov r11, r0 + movs r0, #12 + mov r12, r0 + movs r0, #10 + + reg2_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #10 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + movs r0, #8 + cmp r8, r0 + bne reg2_error_loop + movs r0, #9 + cmp r9, r0 + bne reg2_error_loop + movs r0, #10 + cmp r10, r0 + bne reg2_error_loop + movs r0, #11 + cmp r11, r0 + bne reg2_error_loop + movs r0, #12 + cmp r12, r0 + bne reg2_error_loop + + /* Everything passed, inc the loop counter. */ + push { r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r1 } + + /* Start again. */ + movs r0, #10 + b reg2_loop + + reg2_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg2_error_loop + nop +/*-----------------------------------------------------------*/ + +vRegTestAsm_NonSecureCallback: + /* Store callee saved registers. */ + push { r4-r7 } + mov r0, r8 + mov r1, r9 + mov r2, r10 + mov r3, r11 + mov r4, r12 + push { r0-r4 } + + /* Fill the core registers with known values. */ + movs r1, #151 + movs r2, #152 + movs r3, #153 + movs r4, #154 + movs r5, #155 + movs r6, #156 + movs r7, #157 + movs r0, #158 + mov r8, r0 + movs r0, #159 + mov r9, r0 + movs r0, #160 + mov r10, r0 + movs r0, #161 + mov r11, r0 + movs r0, #162 + mov r12, r0 + movs r0, #150 + + /* Force a context switch by pending non-secure sv. */ + push { r0, r1 } + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsls r0, r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Verify that core registers contain correct values. */ + cmp r0, #150 + bne reg_nscb_error_loop + cmp r1, #151 + bne reg_nscb_error_loop + cmp r2, #152 + bne reg_nscb_error_loop + cmp r3, #153 + bne reg_nscb_error_loop + cmp r4, #154 + bne reg_nscb_error_loop + cmp r5, #155 + bne reg_nscb_error_loop + cmp r6, #156 + bne reg_nscb_error_loop + cmp r7, #157 + bne reg_nscb_error_loop + movs r0, #158 + cmp r8, r0 + bne reg_nscb_error_loop + movs r0, #159 + cmp r9, r0 + bne reg_nscb_error_loop + movs r0, #160 + cmp r10, r0 + bne reg_nscb_error_loop + movs r0, #161 + cmp r11, r0 + bne reg_nscb_error_loop + movs r0, #162 + cmp r12, r0 + bne reg_nscb_error_loop + + /* Everything passed, finish. */ + b reg_nscb_success + + reg_nscb_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg_nscb_error_loop + nop + + reg_nscb_success: + /* Restore callee saved registers. */ + pop { r0-r4 } + mov r8, r0 + mov r9, r1 + mov r10, r2 + mov r11, r3 + mov r12, r4 + pop { r4-r7 } + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/secure/secure_reg_test.c b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/secure/secure_reg_test.c new file mode 100644 index 0000000..12fe2a6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/secure/secure_reg_test.c @@ -0,0 +1,61 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Interface includes. */ +#include "secure_reg_test_asm.h" + +/* FreeRTOS includes. */ +#include "secure_port_macros.h" + +/* Implemented in assembly. */ +extern void vRegTestAsm_SecureImpl( void ); + +/* typedef for non-secure callback function. */ +typedef __cmse_nonsecure_call void ( * NonSecureRegTestCallback_t ) ( void ); +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTestAsm_Secure( void ) +{ + /* Call the function implemented in assembly. */ + vRegTestAsm_SecureImpl(); +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ) +{ + NonSecureRegTestCallback_t pxNonSecureRegTestCallback; + + /* Return function pointer with cleared LSB. */ + pxNonSecureRegTestCallback = ( NonSecureRegTestCallback_t ) cmse_nsfptr_create( pxRegTestCallback ); + + /* Invoke the callback which runs reg tests. */ + pxNonSecureRegTestCallback(); +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/secure/secure_reg_test_asm.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/secure/secure_reg_test_asm.h new file mode 100644 index 0000000..f424f0b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/secure/secure_reg_test_asm.h @@ -0,0 +1,49 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SECURE_REG_TEST_ASM_H +#define SECURE_REG_TEST_ASM_H + +/* Callback function pointer definition. */ +typedef void ( * RegTestCallback_t )( void ); + +/** + * @brief Function that implements reg tests for the secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side. + */ +void vRegTestAsm_Secure( void ); + +/** + * @brief Invokes the supplied reg test callback on the non-secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side.. + */ +void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ); + +#endif /* SECURE_REG_TEST_ASM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/secure/secure_reg_test_asm.s b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/secure/secure_reg_test_asm.s new file mode 100644 index 0000000..c36bdf9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM23/secure/secure_reg_test_asm.s @@ -0,0 +1,127 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + + PUBLIC vRegTestAsm_SecureImpl +/*-----------------------------------------------------------*/ + +vRegTestAsm_SecureImpl: + /* Store callee saved registers. */ + push { r4-r7 } + mov r0, r8 + mov r1, r9 + mov r2, r10 + mov r3, r11 + mov r4, r12 + push { r0-r4 } + + /* Fill the core registers with known values. */ + movs r1, #201 + movs r2, #202 + movs r3, #203 + movs r4, #204 + movs r5, #205 + movs r6, #206 + movs r7, #207 + movs r0, #208 + mov r8, r0 + movs r0, #209 + mov r9, r0 + movs r0, #210 + mov r10, r0 + movs r0, #211 + mov r11, r0 + movs r0, #212 + mov r12, r0 + movs r0, #200 + + /* Force a context switch by pending non-secure sv. */ + push { r0, r1 } + movs r0, #0x01 + ldr r1, =0xe002ed04 /* NVIC_ICSR_NS. */ + lsls r0, r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Verify that core registers contain correct values. */ + cmp r0, #200 + bne secure_reg_test_error_loop + cmp r1, #201 + bne secure_reg_test_error_loop + cmp r2, #202 + bne secure_reg_test_error_loop + cmp r3, #203 + bne secure_reg_test_error_loop + cmp r4, #204 + bne secure_reg_test_error_loop + cmp r5, #205 + bne secure_reg_test_error_loop + cmp r6, #206 + bne secure_reg_test_error_loop + cmp r7, #207 + bne secure_reg_test_error_loop + movs r0, #208 + cmp r8, r0 + bne secure_reg_test_error_loop + movs r0, #209 + cmp r9, r0 + bne secure_reg_test_error_loop + movs r0, #210 + cmp r10, r0 + bne secure_reg_test_error_loop + movs r0, #211 + cmp r11, r0 + bne secure_reg_test_error_loop + movs r0, #212 + cmp r12, r0 + bne secure_reg_test_error_loop + + /* Everything passed, finish. */ + b secure_reg_test_success + + secure_reg_test_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b secure_reg_test_error_loop + nop + + secure_reg_test_success: + /* Restore callee saved registers. */ + pop { r0-r4 } + mov r8, r0 + mov r9, r1 + mov r10, r2 + mov r11, r3 + mov r12, r4 + pop { r4-r7 } + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.h new file mode 100644 index 0000000..3e18a05 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.h @@ -0,0 +1,48 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef REG_TEST_ASM_H +#define REG_TEST_ASM_H + +/** + * @brief Functions that implement reg tests in assembly. + * + * These are called from the FreeRTOS tasks on the non-secure side. + */ +void vRegTest1Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest2Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest3Asm_NonSecure( void ) __attribute__( ( naked ) ); +void vRegTest4Asm_NonSecure( void ) __attribute__( ( naked ) ); + +/** + * @brief Function that implements reg tests in assembly. + * + * This is passed as function pointer to the secure side and called + * from the secure side. + */ +void vRegTestAsm_NonSecureCallback( void ); + +#endif /* REG_TEST_ASM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.s b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.s new file mode 100644 index 0000000..848360f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.s @@ -0,0 +1,1194 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * "Reg tests" - These tests fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + + EXTERN ulRegTest1LoopCounter + EXTERN ulRegTest2LoopCounter + EXTERN ulRegTest3LoopCounter + EXTERN ulRegTest4LoopCounter + + PUBLIC vRegTest1Asm_NonSecure + PUBLIC vRegTest2Asm_NonSecure + PUBLIC vRegTest3Asm_NonSecure + PUBLIC vRegTest4Asm_NonSecure + PUBLIC vRegTestAsm_NonSecureCallback + +/*-----------------------------------------------------------*/ + +vRegTest1Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r0, #100 + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the FPU registers with known values. */ + vmov.f32 s1, #1.5 + vmov.f32 s2, #2.5 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.5 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.5 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.5 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.5 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.5 + vmov.f32 s15, #1.0 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.0 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.0 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.0 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.0 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.5 + vmov.f32 s31, #3.5 + + reg1_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s0, #1.5 /* s0 = 1.5. */ + vcmp.f32 s1, s0 /* Compare s0 and s1. */ + vmrs APSR_nzcv, FPSCR /* Copy floating point flags (FPSCR flags) to ASPR flags - needed for next bne to work. */ + bne reg1_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s2, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s3, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #4.5 + vcmp.f32 s4, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #5.5 + vcmp.f32 s5, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #6.5 + vcmp.f32 s6, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #7.5 + vcmp.f32 s7, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #8.5 + vcmp.f32 s8, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #9.5 + vcmp.f32 s9, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #10.5 + vcmp.f32 s10, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #11.5 + vcmp.f32 s11, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #12.5 + vcmp.f32 s12, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #13.5 + vcmp.f32 s13, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #14.5 + vcmp.f32 s14, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #1.0 + vcmp.f32 s15, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s16, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s17, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #4.0 + vcmp.f32 s18, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #5.0 + vcmp.f32 s19, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #6.0 + vcmp.f32 s20, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #7.0 + vcmp.f32 s21, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #8.0 + vcmp.f32 s22, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #9.0 + vcmp.f32 s23, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #10.0 + vcmp.f32 s24, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #11.0 + vcmp.f32 s25, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #12.0 + vcmp.f32 s26, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #13.0 + vcmp.f32 s27, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #14.0 + vcmp.f32 s28, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #1.5 + vcmp.f32 s29, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s30, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s31, s0 + vmrs APSR_nzcv, FPSCR + bne reg1_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsls r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Start again. */ + b reg1_loop + + reg1_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg1_error_loop + nop + ltorg +/*-----------------------------------------------------------*/ + +vRegTest2Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r0, #0 + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, #8 + mov r9, #9 + movs r10, #10 + movs r11, #11 + movs r12, #12 + + /* Fill the FPU registers with known values. */ + vmov.f32 s1, #1.0 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.0 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.0 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.0 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.0 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.5 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.5 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.5 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.5 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.5 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.0 + + reg2_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #0 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s0, #1.0 + vcmp.f32 s1, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s2, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s3, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #4.0 + vcmp.f32 s4, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #5.0 + vcmp.f32 s5, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #6.0 + vcmp.f32 s6, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #7.0 + vcmp.f32 s7, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #8.0 + vcmp.f32 s8, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #9.0 + vcmp.f32 s9, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #10.0 + vcmp.f32 s10, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #11.0 + vcmp.f32 s11, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #12.0 + vcmp.f32 s12, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #13.0 + vcmp.f32 s13, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #14.0 + vcmp.f32 s14, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #1.5 + vcmp.f32 s15, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #2.5 + vcmp.f32 s16, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #3.5 + vcmp.f32 s17, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #4.5 + vcmp.f32 s18, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #5.5 + vcmp.f32 s19, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #6.5 + vcmp.f32 s20, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #7.5 + vcmp.f32 s21, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #8.5 + vcmp.f32 s22, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #9.5 + vcmp.f32 s23, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #10.5 + vcmp.f32 s24, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #11.5 + vcmp.f32 s25, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #12.5 + vcmp.f32 s26, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #13.5 + vcmp.f32 s27, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #14.5 + vcmp.f32 s28, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #1.0 + vcmp.f32 s29, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #2.0 + vcmp.f32 s30, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + vmov.f32 s0, #3.0 + vcmp.f32 s31, s0 + vmrs APSR_nzcv, FPSCR + bne reg2_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0, r1 } + + /* Start again. */ + b reg2_loop + + reg2_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg2_error_loop + nop + ltorg +/*-----------------------------------------------------------*/ + +vRegTest3Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r0, #100 + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.5 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + + reg3_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #100 + bne reg3_error_loop + cmp r1, #101 + bne reg3_error_loop + cmp r2, #102 + bne reg3_error_loop + cmp r3, #103 + bne reg3_error_loop + cmp r4, #104 + bne reg3_error_loop + cmp r5, #105 + bne reg3_error_loop + cmp r6, #106 + bne reg3_error_loop + cmp r7, #107 + bne reg3_error_loop + cmp r8, #108 + bne reg3_error_loop + cmp r9, #109 + bne reg3_error_loop + cmp r10, #110 + bne reg3_error_loop + cmp r11, #111 + bne reg3_error_loop + cmp r12, #112 + bne reg3_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.5 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne reg3_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest3LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsls r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Start again. */ + b reg3_loop + + reg3_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg3_error_loop + nop + ltorg +/*-----------------------------------------------------------*/ + +vRegTest4Asm_NonSecure: + /* Fill the core registers with known values. */ + movs r0, #0 + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, #8 + mov r9, #9 + movs r10, #10 + movs r11, #11 + movs r12, #12 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.5 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.0 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.5 + vmov.f32 s11, #11.0 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.5 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.0 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.0 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.5 + vmov.f32 s23, #9.0 + vmov.f32 s24, #10.0 + vmov.f32 s25, #11.5 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.0 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + + reg4_loop: + /* Verify that core registers contain correct values. */ + cmp r0, #0 + bne reg4_error_loop + cmp r1, #1 + bne reg4_error_loop + cmp r2, #2 + bne reg4_error_loop + cmp r3, #3 + bne reg4_error_loop + cmp r4, #4 + bne reg4_error_loop + cmp r5, #5 + bne reg4_error_loop + cmp r6, #6 + bne reg4_error_loop + cmp r7, #7 + bne reg4_error_loop + cmp r8, #8 + bne reg4_error_loop + cmp r9, #9 + bne reg4_error_loop + cmp r10, #10 + bne reg4_error_loop + cmp r11, #11 + bne reg4_error_loop + cmp r12, #12 + bne reg4_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.5 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #4.5 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #5.0 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #10.5 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #11.0 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #7.0 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #8.5 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #13.0 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #14.5 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne reg4_error_loop + + /* Everything passed, inc the loop counter. */ + push { r0, r1 } + ldr r0, =ulRegTest4LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0, r1 } + + /* Start again. */ + b reg4_loop + + reg4_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg4_error_loop + nop + ltorg +/*-----------------------------------------------------------*/ + +vRegTestAsm_NonSecureCallback: + /* Store callee saved registers. */ + push { r4-r12 } + + /* Fill the core registers with known values. */ + movs r0, #150 + movs r1, #151 + movs r2, #152 + movs r3, #153 + movs r4, #154 + movs r5, #155 + movs r6, #156 + movs r7, #157 + movs r8, #158 + movs r9, #159 + movs r10, #160 + movs r11, #161 + movs r12, #162 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.0 + vmov.f32 s2, #2.5 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.5 + vmov.f32 s6, #6.5 + vmov.f32 s7, #7.0 + vmov.f32 s8, #8.5 + vmov.f32 s9, #9.5 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.5 + vmov.f32 s13, #13.0 + vmov.f32 s14, #14.5 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.0 + vmov.f32 s17, #3.5 + vmov.f32 s18, #4.5 + vmov.f32 s19, #5.0 + vmov.f32 s20, #6.5 + vmov.f32 s21, #7.5 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.5 + vmov.f32 s25, #11.0 + vmov.f32 s26, #12.5 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.0 + vmov.f32 s29, #1.5 + vmov.f32 s30, #2.5 + vmov.f32 s31, #3.0 + + /* Force a context switch by pending sv. */ + push { r0, r1 } + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_ICSR. */ + lsls r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Verify that core registers contain correct values. */ + cmp r0, #150 + bne reg_nscb_error_loop + cmp r1, #151 + bne reg_nscb_error_loop + cmp r2, #152 + bne reg_nscb_error_loop + cmp r3, #153 + bne reg_nscb_error_loop + cmp r4, #154 + bne reg_nscb_error_loop + cmp r5, #155 + bne reg_nscb_error_loop + cmp r6, #156 + bne reg_nscb_error_loop + cmp r7, #157 + bne reg_nscb_error_loop + cmp r8, #158 + bne reg_nscb_error_loop + cmp r9, #159 + bne reg_nscb_error_loop + cmp r10, #160 + bne reg_nscb_error_loop + cmp r11, #161 + bne reg_nscb_error_loop + cmp r12, #162 + bne reg_nscb_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.0 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #6.5 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #7.0 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #8.5 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #12.5 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #13.0 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #14.5 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #4.5 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #5.0 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #6.5 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #10.5 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #11.0 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #12.5 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne reg_nscb_error_loop + + /* Everything passed, finish. */ + b reg_nscb_success + + reg_nscb_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b reg_nscb_error_loop + nop + + reg_nscb_success: + /* Restore callee saved registers. */ + pop { r4-r12 } + bx lr + ltorg +/*-----------------------------------------------------------*/ + + END diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test.c b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test.c new file mode 100644 index 0000000..12fe2a6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test.c @@ -0,0 +1,61 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Interface includes. */ +#include "secure_reg_test_asm.h" + +/* FreeRTOS includes. */ +#include "secure_port_macros.h" + +/* Implemented in assembly. */ +extern void vRegTestAsm_SecureImpl( void ); + +/* typedef for non-secure callback function. */ +typedef __cmse_nonsecure_call void ( * NonSecureRegTestCallback_t ) ( void ); +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTestAsm_Secure( void ) +{ + /* Call the function implemented in assembly. */ + vRegTestAsm_SecureImpl(); +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ) +{ + NonSecureRegTestCallback_t pxNonSecureRegTestCallback; + + /* Return function pointer with cleared LSB. */ + pxNonSecureRegTestCallback = ( NonSecureRegTestCallback_t ) cmse_nsfptr_create( pxRegTestCallback ); + + /* Invoke the callback which runs reg tests. */ + pxNonSecureRegTestCallback(); +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.h new file mode 100644 index 0000000..f424f0b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.h @@ -0,0 +1,49 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SECURE_REG_TEST_ASM_H +#define SECURE_REG_TEST_ASM_H + +/* Callback function pointer definition. */ +typedef void ( * RegTestCallback_t )( void ); + +/** + * @brief Function that implements reg tests for the secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side. + */ +void vRegTestAsm_Secure( void ); + +/** + * @brief Invokes the supplied reg test callback on the non-secure side. + * + * This function is exported as "non-secure callable" and is called + * from a FreeRTOS task on the non-secure side.. + */ +void vRegTest_NonSecureCallback( RegTestCallback_t pxRegTestCallback ); + +#endif /* SECURE_REG_TEST_ASM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.s b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.s new file mode 100644 index 0000000..942b706 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.s @@ -0,0 +1,265 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + + PUBLIC vRegTestAsm_SecureImpl +/*-----------------------------------------------------------*/ + +vRegTestAsm_SecureImpl: + /* Store callee saved registers. */ + push { r4-r12 } + + /* Fill the core registers with known values. */ + movs r0, #200 + movs r1, #201 + movs r1, #201 + movs r2, #202 + movs r3, #203 + movs r4, #204 + movs r5, #205 + movs r6, #206 + movs r7, #207 + movs r8, #208 + movs r9, #209 + movs r10, #210 + movs r11, #211 + movs r12, #212 + + /* Fill the FPU registers with known values. */ + vmov.f32 s0, #1.0 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.5 + vmov.f32 s4, #4.5 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.5 + vmov.f32 s8, #8.5 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.5 + vmov.f32 s12, #12.5 + vmov.f32 s13, #13.0 + vmov.f32 s14, #14.0 + vmov.f32 s15, #1.5 + vmov.f32 s16, #2.5 + vmov.f32 s17, #3.0 + vmov.f32 s18, #4.0 + vmov.f32 s19, #5.5 + vmov.f32 s20, #6.5 + vmov.f32 s21, #7.0 + vmov.f32 s22, #8.0 + vmov.f32 s23, #9.5 + vmov.f32 s24, #10.5 + vmov.f32 s25, #11.0 + vmov.f32 s26, #12.0 + vmov.f32 s27, #13.5 + vmov.f32 s28, #14.5 + vmov.f32 s29, #1.0 + vmov.f32 s30, #2.0 + vmov.f32 s31, #3.5 + + /* Force a context switch by pending non-secure sv. */ + push { r0, r1 } + movs r0, #0x01 + ldr r1, =0xe002ed04 /* NVIC_ICSR_NS. */ + lsls r0, #28 /* Shift to PendSV bit. */ + str r0, [r1] + dsb + pop { r0, r1 } + + /* Verify that core registers contain correct values. */ + cmp r0, #200 + bne secure_reg_test_error_loop + cmp r1, #201 + bne secure_reg_test_error_loop + cmp r2, #202 + bne secure_reg_test_error_loop + cmp r3, #203 + bne secure_reg_test_error_loop + cmp r4, #204 + bne secure_reg_test_error_loop + cmp r5, #205 + bne secure_reg_test_error_loop + cmp r6, #206 + bne secure_reg_test_error_loop + cmp r7, #207 + bne secure_reg_test_error_loop + cmp r8, #208 + bne secure_reg_test_error_loop + cmp r9, #209 + bne secure_reg_test_error_loop + cmp r10, #210 + bne secure_reg_test_error_loop + cmp r11, #211 + bne secure_reg_test_error_loop + cmp r12, #212 + bne secure_reg_test_error_loop + + /* Verify that FPU registers contain correct values. */ + vmov.f32 s1, #1.0 + vcmp.f32 s0, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s2, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s3, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #4.5 + vcmp.f32 s4, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #5.0 + vcmp.f32 s5, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #6.0 + vcmp.f32 s6, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #7.5 + vcmp.f32 s7, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #8.5 + vcmp.f32 s8, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #9.0 + vcmp.f32 s9, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #10.0 + vcmp.f32 s10, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #11.5 + vcmp.f32 s11, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #12.5 + vcmp.f32 s12, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #13.0 + vcmp.f32 s13, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #14.0 + vcmp.f32 s14, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #1.5 + vcmp.f32 s15, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #2.5 + vcmp.f32 s16, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #3.0 + vcmp.f32 s17, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #4.0 + vcmp.f32 s18, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #5.5 + vcmp.f32 s19, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #6.5 + vcmp.f32 s20, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #7.0 + vcmp.f32 s21, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #8.0 + vcmp.f32 s22, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #9.5 + vcmp.f32 s23, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #10.5 + vcmp.f32 s24, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #11.0 + vcmp.f32 s25, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #12.0 + vcmp.f32 s26, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #13.5 + vcmp.f32 s27, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #14.5 + vcmp.f32 s28, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #1.0 + vcmp.f32 s29, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #2.0 + vcmp.f32 s30, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + vmov.f32 s1, #3.5 + vcmp.f32 s31, s1 + vmrs APSR_nzcv, FPSCR + bne secure_reg_test_error_loop + + /* Everything passed, finish. */ + b secure_reg_test_success + + secure_reg_test_error_loop: + /* If this line is hit then there was an error in + * a core register value. The loop ensures the + * loop counter stops incrementing. */ + b secure_reg_test_error_loop + nop + + secure_reg_test_success: + /* Restore callee saved registers. */ + pop { r4-r12 } + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/nsc_functions.c b/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/nsc_functions.c new file mode 100644 index 0000000..4924985 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/nsc_functions.c @@ -0,0 +1,58 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include "nsc_functions.h" +#include "secure_port_macros.h" + +/** + * @brief Counter returned from NSCFunction. + */ +static uint32_t ulSecureCounter = 0; + +/** + * @brief typedef for non-secure callback. + */ +typedef void ( *NonSecureCallback_t )( void ) __attribute__( ( cmse_nonsecure_call ) ); +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE uint32_t NSCFunction( Callback_t pxCallback ) +{ + NonSecureCallback_t pxNonSecureCallback; + + /* Return function pointer with cleared LSB. */ + pxNonSecureCallback = ( NonSecureCallback_t ) cmse_nsfptr_create( pxCallback ); + + /* Invoke the supplied callback. */ + pxNonSecureCallback(); + + /* Increment the secure side counter. */ + ulSecureCounter += 1; + + /* Return the secure side counter. */ + return ulSecureCounter; +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/nsc_functions.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/nsc_functions.h new file mode 100644 index 0000000..350f679 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/nsc_functions.h @@ -0,0 +1,50 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __NSC_FUNCTIONS_H__ +#define __NSC_FUNCTIONS_H__ + +#include + +/** + * @brief Callback function pointer definition. + */ +typedef void ( * Callback_t ) ( void ); + +/** + * @brief Invokes the supplied callback which is on the non-secure side. + * + * Returns a number which is one more than the value returned in previous + * invocation of this function. Initial invocation returns 1. + * + * @param pxCallback[in] The callback to invoke. + * + * @return A number which is one more than the value returned in previous + * invocation of this function. + */ +uint32_t NSCFunction( Callback_t pxCallback ); + +#endif /* __NSC_FUNCTIONS_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/tz_demo.c b/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/tz_demo.c new file mode 100644 index 0000000..79963ce --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/tz_demo.c @@ -0,0 +1,133 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Non-Secure callable functions. */ +#include "nsc_functions.h" + +/** + * @brief Counter incremented in the callback which is called from the secure + * side. + * + * The size of an MPU region must be a multiple of 32 bytes. Therefore we need + * to declare an array of size 8 to ensure that the total size is 32 bytes - + * even though we only need 4 bytes. If we do not do that, anything placed after + * 4 bytes and upto 32 bytes will also fall in the same MPU region and the task + * having access to ulNonSecureCounter will also have access to all those items. + */ +static uint32_t ulNonSecureCounter[ 8 ] __attribute__( ( aligned( 32 ) ) ) = { 0 }; +/*-----------------------------------------------------------*/ + +/** + * @brief Creates all the tasks for TZ demo. + */ +void vStartTZDemo( void ); + +/** + * @brief Increments the ulNonSecureCounter. + * + * This function is called from the secure side. + */ +static void prvCallback( void ); + +/** + * @brief Implements the task which calls the functions exported from the secure + * side. + * + * @param pvParameters[in] Parameters as passed during task creation. + */ +static void prvSecureCallingTask( void * pvParameters ); +/*-----------------------------------------------------------*/ + +void vStartTZDemo( void ) +{ + static StackType_t xSecureCallingTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) ); + TaskParameters_t xSecureCallingTaskParameters = + { + .pvTaskCode = prvSecureCallingTask, + .pcName = "SecCalling", + .usStackDepth = configMINIMAL_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = tskIDLE_PRIORITY, + .puxStackBuffer = xSecureCallingTaskStack, + .xRegions = + { + { ulNonSecureCounter, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER }, + { 0, 0, 0 }, + { 0, 0, 0 }, + } + }; + + /* Create an unprivileged task which calls secure functions. */ + xTaskCreateRestricted( &( xSecureCallingTaskParameters ), NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvCallback( void ) +{ + /* This function is called from the secure side. Just increment the counter + * here. The check that this counter keeps incrementing is performed in the + * prvSecureCallingTask. */ + ulNonSecureCounter[ 0 ] += 1; +} +/*-----------------------------------------------------------*/ + +static void prvSecureCallingTask( void * pvParameters ) +{ + uint32_t ulLastSecureCounter = 0, ulLastNonSecureCounter = 0; + uint32_t ulCurrentSecureCounter = 0; + + /* This task calls secure side functions. So allocate a secure context for + * it. */ + portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE ); + + for( ; ; ) + { + /* Call the secure side function. It does two things: + * - It calls the supplied function (prvCallback) which in turn + * increments the non-secure counter. + * - It increments the secure counter and returns the incremented value. + * Therefore at the end of this function call both the secure and + * non-secure counters must have been incremented. + */ + ulCurrentSecureCounter = NSCFunction( prvCallback ); + + /* Make sure that both the counters are incremented. */ + configASSERT( ulCurrentSecureCounter == ulLastSecureCounter + 1 ); + configASSERT( ulNonSecureCounter[ 0 ] == ulLastNonSecureCounter + 1 ); + + /* Update the last values for both the counters. */ + ulLastSecureCounter = ulCurrentSecureCounter; + ulLastNonSecureCounter = ulNonSecureCounter[ 0 ]; + + /* Wait for a second. */ + vTaskDelay( pdMS_TO_TICKS( 1000 ) ); + } +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/tz_demo.h b/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/tz_demo.h new file mode 100644 index 0000000..70ced7f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ARMv8M/tz_demo/tz_demo.h @@ -0,0 +1,44 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __TZ_DEMO_H__ +#define __TZ_DEMO_H__ + +/** + * @brief Creates all the tasks for TZ demo. + * + * The Trust Zone (TZ) demo creates an unprivileged task which calls a secure + * side function and passes a pointer to a callback function. The secure side + * function does two things: + * 1. It calls the provided callback function. The callback function increments + * a counter. + * 2. It increments a counter and returns the incremented value. + * After the secure function call finishes, it verifies that both the counters + * are incremented. + */ +void vStartTZDemo( void ); + +#endif /* __TZ_DEMO_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/Full/BlockQ.c b/SOFTWARE-FreeRTOS/Common/Full/BlockQ.c new file mode 100644 index 0000000..0b1205a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/BlockQ.c @@ -0,0 +1,307 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + * \page BlockQC blockQ.c + * \ingroup DemoFiles + *
+ */ + +/* + * Changes from V1.00: + * + + Reversed the priority and block times of the second two demo tasks so + + they operate as per the description above. + + + + Changes from V2.0.0 + + + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + + + + Changes from V4.0.2 + + + + The second set of tasks were created the wrong way around. This has been + + corrected. + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "BlockQ.h" +#include "print.h" + +#define blckqSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE ) +#define blckqNUM_TASK_SETS ( 3 ) + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + QueueHandle_t xQueue; /*< The queue to be used by the task. */ + TickType_t xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile short * psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static void vBlockingQueueProducer( void * pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that + * it is the expected number. */ +static void vBlockingQueueConsumer( void * pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and + * found to be the expected value. + * These are used to check that the tasks are still running. */ +static volatile short sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These + * are used to check that the tasks are still running. */ +static volatile short sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ + xBlockingQueueParameters * pxQueueParameters1, * pxQueueParameters2; + xBlockingQueueParameters * pxQueueParameters3, * pxQueueParameters4; + xBlockingQueueParameters * pxQueueParameters5, * pxQueueParameters6; + const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; + const TickType_t xBlockTime = ( TickType_t ) 1000 / portTICK_PERIOD_MS; + const TickType_t xDontBlock = ( TickType_t ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + * Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + * is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + * wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + * it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + * spawned. */ + xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + * the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + * the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vBlockingQueueProducer( void * pvParameters ) +{ + unsigned short usValue = 0; + xBlockingQueueParameters * pxQueueParameters; + const char * const pcTaskStartMsg = "Blocking queue producer started.\r\n"; + const char * const pcTaskErrorMsg = "Could not post on blocking queue\r\n"; + short sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ; ; ) + { + if( xQueueSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + vPrintDisplayMessage( &pcTaskErrorMsg ); + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + * used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + * consumer will expect the numbers to follow in numerical order. */ + ++usValue; + } + } +} +/*-----------------------------------------------------------*/ + +static void vBlockingQueueConsumer( void * pvParameters ) +{ + unsigned short usData, usExpectedValue = 0; + xBlockingQueueParameters * pxQueueParameters; + const char * const pcTaskStartMsg = "Blocking queue consumer started.\r\n"; + const char * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n"; + short sErrorEverOccurred = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ; ; ) + { + if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + vPrintDisplayMessage( &pcTaskErrorMsg ); + + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + * variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + * round. */ + ++usExpectedValue; + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreBlockingQueuesStillRunning( void ) +{ + static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 }; + static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 }; + portBASE_TYPE xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + * bits and we are only reading them. We also only care to see if they have + * changed or not. + * + * Loop through each check variable and return pdFALSE if any are found not + * to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/PollQ.c b/SOFTWARE-FreeRTOS/Common/Full/PollQ.c new file mode 100644 index 0000000..6aa40dc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/PollQ.c @@ -0,0 +1,221 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/** + * This is a very simple queue test. See the BlockQ. c documentation for a more + * comprehensive version. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + * + * \page PollQC pollQ.c + * \ingroup DemoFiles + *
+ */ + +/* + * Changes from V2.0.0 + * + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "print.h" + +/* Demo program include files. */ +#include "PollQ.h" + +#define pollqSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE ) + +/* The task that posts the incrementing number onto the queue. */ +static void vPolledQueueProducer( void * pvParameters ); + +/* The task that empties the queue. */ +static void vPolledQueueConsumer( void * pvParameters ); + +/* Variables that are used to check that the tasks are still running with no errors. */ +static volatile short sPollingConsumerCount = 0, sPollingProducerCount = 0; +/*-----------------------------------------------------------*/ + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ + static QueueHandle_t xPolledQueue; + const unsigned portBASE_TYPE uxQueueSize = 10; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) ); + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); + xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vPolledQueueProducer( void * pvParameters ) +{ + unsigned short usValue = 0, usLoop; + QueueHandle_t * pxQueue; + const TickType_t xDelay = ( TickType_t ) 200 / portTICK_PERIOD_MS; + const unsigned short usNumToProduce = 3; + const char * const pcTaskStartMsg = "Polled queue producer started.\r\n"; + const char * const pcTaskErrorMsg = "Could not post on polled queue.\r\n"; + short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The queue being used is passed in as the parameter. */ + pxQueue = ( QueueHandle_t * ) pvParameters; + + for( ; ; ) + { + for( usLoop = 0; usLoop < usNumToProduce; ++usLoop ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueSendToBack( *pxQueue, ( void * ) &usValue, ( TickType_t ) 0 ) != pdPASS ) + { + /* We should never find the queue full - this is an error. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sError = pdTRUE; + } + else + { + if( sError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + * check variable. */ + ++sPollingProducerCount; + } + + /* Update the value we are going to post next time around. */ + ++usValue; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + * empties the queue. */ + vTaskDelay( xDelay ); + } +} +/*-----------------------------------------------------------*/ + +static void vPolledQueueConsumer( void * pvParameters ) +{ + unsigned short usData, usExpectedValue = 0; + QueueHandle_t * pxQueue; + const TickType_t xDelay = ( TickType_t ) 200 / portTICK_PERIOD_MS; + const char * const pcTaskStartMsg = "Polled queue consumer started.\r\n"; + const char * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n"; + short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The queue being used is passed in as the parameter. */ + pxQueue = ( QueueHandle_t * ) pvParameters; + + for( ; ; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *pxQueue ) ) + { + if( xQueueReceive( *pxQueue, &usData, ( TickType_t ) 0 ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + * occurred. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sError = pdTRUE; + + /* Catch-up to the value we received so our next expected value + * should again be correct. */ + usExpectedValue = usData; + } + else + { + if( sError == pdFALSE ) + { + /* Only increment the check variable if no errors have + * occurred. */ + ++sPollingConsumerCount; + } + } + + ++usExpectedValue; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + * items in the queue. */ + vTaskDelay( xDelay ); + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +portBASE_TYPE xArePollingQueuesStillRunning( void ) +{ + static short sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0; + portBASE_TYPE xReturn; + + if( ( sLastPollingConsumerCount == sPollingConsumerCount ) || + ( sLastPollingProducerCount == sPollingProducerCount ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + sLastPollingConsumerCount = sPollingConsumerCount; + sLastPollingProducerCount = sPollingProducerCount; + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/comtest.c b/SOFTWARE-FreeRTOS/Common/Full/comtest.c new file mode 100644 index 0000000..67233f5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/comtest.c @@ -0,0 +1,350 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * Creates two tasks that operate on an interrupt driven serial port. A loopback + * connector should be used so that everything that is transmitted is also received. + * The serial port does not use any flow control. On a standard 9way 'D' connector + * pins two and three should be connected together. + * + * The first task repeatedly sends a string to a queue, character at a time. The + * serial port interrupt will empty the queue and transmit the characters. The + * task blocks for a pseudo random period before resending the string. + * + * The second task blocks on a queue waiting for a character to be received. + * Characters received by the serial port interrupt routine are posted onto the + * queue - unblocking the task making it ready to execute. If this is then the + * highest priority task ready to run it will run immediately - with a context + * switch occurring at the end of the interrupt service routine. The task + * receiving characters is spawned with a higher priority than the task + * transmitting the characters. + * + * With the loop back connector in place, one task will transmit a string and the + * other will immediately receive it. The receiving task knows the string it + * expects to receive so can detect an error. + * + * This also creates a third task. This is used to test semaphore usage from an + * ISR and does nothing interesting. + * + * \page ComTestC comtest.c + * \ingroup DemoFiles + *
+ */ + +/* + * Changes from V1.00: + * + + The priority of the Rx task has been lowered. Received characters are + + now processed (read from the queue) at the idle priority, allowing low + + priority tasks to run evenly at times of a high communications overhead. + + + + Changes from V1.01: + + + + The Tx task now waits a pseudo random time between transmissions. + + Previously a fixed period was used but this was not such a good test as + + interrupts fired at regular intervals. + + + + Changes From V1.2.0: + + + + Use vSerialPutString() instead of single character puts. + + Only stop the check variable incrementing after two consecutive errors. + + + + Changed from V1.2.5 + + + + Made the Rx task 2 priorities higher than the Tx task. Previously it was + + only 1. This is done to tie in better with the other demo application + + tasks. + + + + Changes from V2.0.0 + + + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + + Slight modification to task priorities. + + + */ + + +/* Scheduler include files. */ +#include +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "serial.h" +#include "comtest.h" +#include "print.h" + +/* The Tx task will transmit the sequence of characters at a pseudo random + * interval. This is the maximum and minimum block time between sends. */ +#define comTX_MAX_BLOCK_TIME ( ( TickType_t ) 0x15e ) +#define comTX_MIN_BLOCK_TIME ( ( TickType_t ) 0xc8 ) + +#define comMAX_CONSECUTIVE_ERRORS ( 2 ) + +#define comSTACK_SIZE ( ( unsigned short ) 256 ) + +#define comRX_RELATIVE_PRIORITY ( 1 ) + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort; + +/* The transmit function as described at the top of the file. */ +static void vComTxTask( void * pvParameters ); + +/* The receive function as described at the top of the file. */ +static void vComRxTask( void * pvParameters ); + +/* The semaphore test function as described at the top of the file. */ +static void vSemTestTask( void * pvParameters ); + +/* The string that is repeatedly transmitted. */ +const char * const pcMessageToExchange = "Send this message over and over again to check communications interrupts. " + "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n"; + +/* Variables that are incremented on each cycle of each task. These are used to + * check that both tasks are still executing. */ +volatile short sTxCount = 0, sRxCount = 0, sSemCount = 0; + +/* The handle to the semaphore test task. */ +static TaskHandle_t xSemTestTaskHandle = NULL; + +/*-----------------------------------------------------------*/ + +void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, + eCOMPort ePort, + eBaud eBaudRate ) +{ + const unsigned portBASE_TYPE uxBufferLength = 255; + + /* Initialise the com port then spawn both tasks. */ + xPort = xSerialPortInit( ePort, eBaudRate, serNO_PARITY, serBITS_8, serSTOP_1, uxBufferLength ); + xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority, NULL ); + xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority + comRX_RELATIVE_PRIORITY, NULL ); + xTaskCreate( vSemTestTask, "ISRSem", comSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xSemTestTaskHandle ); +} +/*-----------------------------------------------------------*/ + +static void vComTxTask( void * pvParameters ) +{ + const char * const pcTaskStartMsg = "COM Tx task started.\r\n"; + TickType_t xTimeToWait; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ; ; ) + { + /* Send the string to the serial port. */ + vSerialPutString( xPort, pcMessageToExchange, strlen( pcMessageToExchange ) ); + + /* We have posted all the characters in the string - increment the variable + * used to check that this task is still running, then wait before re-sending + * the string. */ + sTxCount++; + + xTimeToWait = xTaskGetTickCount(); + + /* Make sure we don't wait too long... */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* ...but we do want to wait. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + vTaskDelay( xTimeToWait ); + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static void vComRxTask( void * pvParameters ) +{ + const char * const pcTaskStartMsg = "COM Rx task started.\r\n"; + const char * const pcTaskErrorMsg = "COM read error\r\n"; + const char * const pcTaskRestartMsg = "COM resynced\r\n"; + const char * const pcTaskTimeoutMsg = "COM Rx timed out\r\n"; + const TickType_t xBlockTime = ( TickType_t ) 0xffff / portTICK_PERIOD_MS; + const char * pcExpectedChar; + portBASE_TYPE xGotChar; + char cRxedChar; + short sResyncRequired, sConsecutiveErrors, sLatchedError; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The first expected character is the first character in the string. */ + pcExpectedChar = pcMessageToExchange; + sResyncRequired = pdFALSE; + sConsecutiveErrors = 0; + sLatchedError = pdFALSE; + + for( ; ; ) + { + /* Receive a message from the com port interrupt routine. If a message is + * not yet available the call will block the task. */ + xGotChar = xSerialGetChar( xPort, &cRxedChar, xBlockTime ); + + if( xGotChar == pdTRUE ) + { + if( sResyncRequired == pdTRUE ) + { + /* We got out of sequence and are waiting for the start of the next + * transmission of the string. */ + if( cRxedChar == '\n' ) + { + /* This is the end of the message so we can start again - with + * the first character in the string being the next thing we expect + * to receive. */ + pcExpectedChar = pcMessageToExchange; + sResyncRequired = pdFALSE; + + /* Queue a message for printing to say that we are going to try + * again. */ + vPrintDisplayMessage( &pcTaskRestartMsg ); + + /* Stop incrementing the check variable, if consecutive errors occur. */ + sConsecutiveErrors++; + + if( sConsecutiveErrors >= comMAX_CONSECUTIVE_ERRORS ) + { + sLatchedError = pdTRUE; + } + } + } + else + { + /* We have received a character, but is it the expected character? */ + if( cRxedChar != *pcExpectedChar ) + { + /* This was not the expected character so post a message for + * printing to say that an error has occurred. We will then wait + * to resynchronize. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sResyncRequired = pdTRUE; + } + else + { + /* This was the expected character so next time we will expect + * the next character in the string. Wrap back to the beginning + * of the string when the null terminator has been reached. */ + pcExpectedChar++; + + if( *pcExpectedChar == '\0' ) + { + pcExpectedChar = pcMessageToExchange; + + /* We have got through the entire string without error. */ + sConsecutiveErrors = 0; + } + } + } + + /* Increment the count that is used to check that this task is still + * running. This is only done if an error has never occurred. */ + if( sLatchedError == pdFALSE ) + { + sRxCount++; + } + } + else + { + vPrintDisplayMessage( &pcTaskTimeoutMsg ); + } + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static void vSemTestTask( void * pvParameters ) +{ + const char * const pcTaskStartMsg = "ISR Semaphore test started.\r\n"; + portBASE_TYPE xError = pdFALSE; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ; ; ) + { + if( xSerialWaitForSemaphore( xPort ) ) + { + if( xError == pdFALSE ) + { + sSemCount++; + } + } + else + { + xError = pdTRUE; + } + } +} /*lint !e715 !e830 !e818 pvParameters not used but function prototype must be standard for task function. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreComTestTasksStillRunning( void ) +{ + static short sLastTxCount = 0, sLastRxCount = 0, sLastSemCount = 0; + portBASE_TYPE xReturn; + + /* Not too worried about mutual exclusion on these variables as they are 16 + * bits and we are only reading them. We also only care to see if they have + * changed or not. */ + + if( ( sTxCount == sLastTxCount ) || ( sRxCount == sLastRxCount ) || ( sSemCount == sLastSemCount ) ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + sLastTxCount = sTxCount; + sLastRxCount = sRxCount; + sLastSemCount = sSemCount; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vComTestUnsuspendTask( void ) +{ + /* The task that is suspended on the semaphore will be referenced from the + * Suspended list as it is blocking indefinitely. This call just checks that + * the kernel correctly detects this and does not attempt to unsuspend the + * task. */ + xTaskResumeFromISR( xSemTestTaskHandle ); +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/death.c b/SOFTWARE-FreeRTOS/Common/Full/death.c new file mode 100644 index 0000000..36ca459 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/death.c @@ -0,0 +1,202 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * Create a single persistent task which periodically dynamically creates another + * four tasks. The original task is called the creator task, the four tasks it + * creates are called suicidal tasks. + * + * Two of the created suicidal tasks kill one other suicidal task before killing + * themselves - leaving just the original task remaining. + * + * The creator task must be spawned after all of the other demo application tasks + * as it keeps a check on the number of tasks under the scheduler control. The + * number of tasks it expects to see running should never be greater than the + * number of tasks that were in existence when the creator task was spawned, plus + * one set of four suicidal tasks. If this number is exceeded an error is flagged. + * + * \page DeathC death.c + * \ingroup DemoFiles + *
+ */ + +/* + * Changes from V2.0.0 + * + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "death.h" +#include "print.h" + +#define deathSTACK_SIZE ( ( unsigned short ) 512 ) + +/* The task originally created which is responsible for periodically dynamically + * creating another four tasks. */ +static void vCreateTasks( void * pvParameters ); + +/* The task function of the dynamically created tasks. */ +static void vSuicidalTask( void * pvParameters ); + +/* A variable which is incremented every time the dynamic tasks are created. This + * is used to check that the task is still running. */ +static volatile short sCreationCount = 0; + +/* Used to store the number of tasks that were originally running so the creator + * task can tell if any of the suicidal tasks have failed to die. */ +static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0; +static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 5; + +/* Used to store a handle to the tasks that should be killed by a suicidal task, + * before it kills itself. */ +TaskHandle_t xCreatedTask1, xCreatedTask2; + +/*-----------------------------------------------------------*/ + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ) +{ + unsigned portBASE_TYPE * puxPriority; + + /* Create the Creator tasks - passing in as a parameter the priority at which + * the suicidal tasks should be created. */ + puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) ); + *puxPriority = uxPriority; + + xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL ); + + /* Record the number of tasks that are running now so we know if any of the + * suicidal tasks have failed to be killed. */ + uxTasksRunningAtStart = uxTaskGetNumberOfTasks(); +} +/*-----------------------------------------------------------*/ + +static void vSuicidalTask( void * pvParameters ) +{ + portDOUBLE d1, d2; + TaskHandle_t xTaskToKill; + const TickType_t xDelay = ( TickType_t ) 500 / portTICK_PERIOD_MS; + + if( pvParameters != NULL ) + { + /* This task is periodically created four times. Tow created tasks are + * passed a handle to the other task so it can kill it before killing itself. + * The other task is passed in null. */ + xTaskToKill = *( TaskHandle_t * ) pvParameters; + } + else + { + xTaskToKill = NULL; + } + + for( ; ; ) + { + /* Do something random just to use some stack and registers. */ + d1 = 2.4; + d2 = 89.2; + d2 *= d1; + vTaskDelay( xDelay ); + + if( xTaskToKill != NULL ) + { + /* Make sure the other task has a go before we delete it. */ + vTaskDelay( ( TickType_t ) 0 ); + /* Kill the other task that was created by vCreateTasks(). */ + vTaskDelete( xTaskToKill ); + /* Kill ourselves. */ + vTaskDelete( NULL ); + } + } +} /*lint !e818 !e550 Function prototype must be as per standard for task functions. */ +/*-----------------------------------------------------------*/ + +static void vCreateTasks( void * pvParameters ) +{ + const TickType_t xDelay = ( TickType_t ) 1000 / portTICK_PERIOD_MS; + unsigned portBASE_TYPE uxPriority; + const char * const pcTaskStartMsg = "Create task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + uxPriority = *( unsigned portBASE_TYPE * ) pvParameters; + vPortFree( pvParameters ); + + for( ; ; ) + { + /* Just loop round, delaying then creating the four suicidal tasks. */ + vTaskDelay( xDelay ); + + xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 ); + xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL ); + + xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 ); + xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL ); + + ++sCreationCount; + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the creator task is still running and that there + * are not any more than four extra tasks. */ +portBASE_TYPE xIsCreateTaskStillRunning( void ) +{ + static short sLastCreationCount = 0; + short sReturn = pdTRUE; + unsigned portBASE_TYPE uxTasksRunningNow; + + if( sLastCreationCount == sCreationCount ) + { + sReturn = pdFALSE; + } + + sLastCreationCount = sCreationCount; + + uxTasksRunningNow = uxTaskGetNumberOfTasks(); + + if( uxTasksRunningNow < uxTasksRunningAtStart ) + { + sReturn = pdFALSE; + } + else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) + { + sReturn = pdFALSE; + } + else + { + /* Everything is okay. */ + } + + return sReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/dynamic.c b/SOFTWARE-FreeRTOS/Common/Full/dynamic.c new file mode 100644 index 0000000..ee29586 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/dynamic.c @@ -0,0 +1,574 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * The first test creates three tasks - two counter tasks (one continuous count + * and one limited count) and one controller. A "count" variable is shared + * between all three tasks. The two counter tasks should never be in a "ready" + * state at the same time. The controller task runs at the same priority as + * the continuous count task, and at a lower priority than the limited count + * task. + * + * One counter task loops indefinitely, incrementing the shared count variable + * on each iteration. To ensure it has exclusive access to the variable it + * raises it's priority above that of the controller task before each + * increment, lowering it again to it's original priority before starting the + * next iteration. + * + * The other counter task increments the shared count variable on each + * iteration of it's loop until the count has reached a limit of 0xff - at + * which point it suspends itself. It will not start a new loop until the + * controller task has made it "ready" again by calling vTaskResume (). + * This second counter task operates at a higher priority than controller + * task so does not need to worry about mutual exclusion of the counter + * variable. + * + * The controller task is in two sections. The first section controls and + * monitors the continuous count task. When this section is operational the + * limited count task is suspended. Likewise, the second section controls + * and monitors the limited count task. When this section is operational the + * continuous count task is suspended. + * + * In the first section the controller task first takes a copy of the shared + * count variable. To ensure mutual exclusion on the count variable it + * suspends the continuous count task, resuming it again when the copy has been + * taken. The controller task then sleeps for a fixed period - during which + * the continuous count task will execute and increment the shared variable. + * When the controller task wakes it checks that the continuous count task + * has executed by comparing the copy of the shared variable with its current + * value. This time, to ensure mutual exclusion, the scheduler itself is + * suspended with a call to vTaskSuspendAll (). This is for demonstration + * purposes only and is not a recommended technique due to its inefficiency. + * + * After a fixed number of iterations the controller task suspends the + * continuous count task, and moves on to its second section. + * + * At the start of the second section the shared variable is cleared to zero. + * The limited count task is then woken from it's suspension by a call to + * vTaskResume (). As this counter task operates at a higher priority than + * the controller task the controller task should not run again until the + * shared variable has been counted up to the limited value causing the counter + * task to suspend itself. The next line after vTaskResume () is therefore + * a check on the shared variable to ensure everything is as expected. + * + * + * The second test consists of a couple of very simple tasks that post onto a + * queue while the scheduler is suspended. This test was added to test parts + * of the scheduler not exercised by the first test. + * + * + * The final set of two tasks implements a third test. This simply raises the + * priority of a task while the scheduler is suspended. Again this test was + * added to exercise parts of the code not covered by the first test. + * + * \page Priorities dynamic.c + * \ingroup DemoFiles + *
+ */ + +/* + * Changes from V2.0.0 + * + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + + Added a second, simple test that uses the functions + + vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask(). + + + + Changes from V3.1.1 + + + + Added a third simple test that uses the vTaskPrioritySet() function + + while the scheduler is suspended. + + Modified the controller task slightly to test the calling of + + vTaskResumeAll() while the scheduler is suspended. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "dynamic.h" +#include "print.h" + +/* Function that implements the "limited count" task as described above. */ +static void vLimitedIncrementTask( void * pvParameters ); + +/* Function that implements the "continuous count" task as described above. */ +static void vContinuousIncrementTask( void * pvParameters ); + +/* Function that implements the controller task as described above. */ +static void vCounterControlTask( void * pvParameters ); + +/* The simple test functions that check sending and receiving while the + * scheduler is suspended. */ +static void vQueueReceiveWhenSuspendedTask( void * pvParameters ); +static void vQueueSendWhenSuspendedTask( void * pvParameters ); + +/* The simple test functions that check raising and lowering of task priorities + * while the scheduler is suspended. */ +static void prvChangePriorityWhenSuspendedTask( void * pvParameters ); +static void prvChangePriorityHelperTask( void * pvParameters ); + + +/* Demo task specific constants. */ +#define priSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE ) +#define priSLEEP_TIME ( ( TickType_t ) 50 ) +#define priLOOPS ( 5 ) +#define priMAX_COUNT ( ( unsigned long ) 0xff ) +#define priNO_BLOCK ( ( TickType_t ) 0 ) +#define priSUSPENDED_QUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* Handles to the two counter tasks. These could be passed in as parameters + * to the controller task to prevent them having to be file scope. */ +static TaskHandle_t xContinuousIncrementHandle, xLimitedIncrementHandle, xChangePriorityWhenSuspendedHandle; + +/* The shared counter variable. This is passed in as a parameter to the two + * counter variables for demonstration purposes. */ +static unsigned long ulCounter; + +/* Variable used in a similar way by the test that checks the raising and + * lowering of task priorities while the scheduler is suspended. */ +static unsigned long ulPrioritySetCounter; + +/* Variables used to check that the tasks are still operating without error. + * Each complete iteration of the controller task increments this variable + * provided no errors have been found. The variable maintaining the same value + * is therefore indication of an error. */ +static unsigned short usCheckVariable = ( unsigned short ) 0; +static portBASE_TYPE xSuspendedQueueSendError = pdFALSE; +static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE; +static portBASE_TYPE xPriorityRaiseWhenSuspendedError = pdFALSE; + +/* Queue used by the second test. */ +QueueHandle_t xSuspendedTestQueue; + +/*-----------------------------------------------------------*/ + +/* + * Start the seven tasks as described at the top of the file. + * Note that the limited count task is given a higher priority. + */ +void vStartDynamicPriorityTasks( void ) +{ + xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned long ) ); + xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle ); + xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); + xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL ); + xTaskCreate( prvChangePriorityHelperTask, "2nd_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle ); +} +/*-----------------------------------------------------------*/ + +/* + * Just loops around incrementing the shared variable until the limit has been + * reached. Once the limit has been reached it suspends itself. + */ +static void vLimitedIncrementTask( void * pvParameters ) +{ + unsigned long * pulCounter; + + /* Take a pointer to the shared variable from the parameters passed into + * the task. */ + pulCounter = ( unsigned long * ) pvParameters; + + /* This will run before the control task, so the first thing it does is + * suspend - the control task will resume it when ready. */ + vTaskSuspend( NULL ); + + for( ; ; ) + { + /* Just count up to a value then suspend. */ + ( *pulCounter )++; + + if( *pulCounter >= priMAX_COUNT ) + { + vTaskSuspend( NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Just keep counting the shared variable up. The control task will suspend + * this task when it wants. + */ +static void vContinuousIncrementTask( void * pvParameters ) +{ + unsigned long * pulCounter; + unsigned portBASE_TYPE uxOurPriority; + + /* Take a pointer to the shared variable from the parameters passed into + * the task. */ + pulCounter = ( unsigned long * ) pvParameters; + + /* Query our priority so we can raise it when exclusive access to the + * shared variable is required. */ + uxOurPriority = uxTaskPriorityGet( NULL ); + + for( ; ; ) + { + /* Raise our priority above the controller task to ensure a context + * switch does not occur while we are accessing this variable. */ + vTaskPrioritySet( NULL, uxOurPriority + 1 ); + ( *pulCounter )++; + vTaskPrioritySet( NULL, uxOurPriority ); + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +/* + * Controller task as described above. + */ +static void vCounterControlTask( void * pvParameters ) +{ + unsigned long ulLastCounter; + short sLoops; + short sError = pdFALSE; + const char * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n"; + const char * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ; ; ) + { + /* Start with the counter at zero. */ + ulCounter = ( unsigned long ) 0; + + /* First section : */ + + /* Check the continuous count task is running. */ + for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) + { + /* Suspend the continuous count task so we can take a mirror of the + * shared variable without risk of corruption. */ + vTaskSuspend( xContinuousIncrementHandle ); + ulLastCounter = ulCounter; + vTaskResume( xContinuousIncrementHandle ); + + /* Now delay to ensure the other task has processor time. */ + vTaskDelay( priSLEEP_TIME ); + + /* Check the shared variable again. This time to ensure mutual + * exclusion the whole scheduler will be locked. This is just for + * demo purposes! */ + vTaskSuspendAll(); + { + if( ulLastCounter == ulCounter ) + { + /* The shared variable has not changed. There is a problem + * with the continuous count task so flag an error. */ + sError = pdTRUE; + xTaskResumeAll(); + vPrintDisplayMessage( &pcTaskFailMsg ); + vTaskSuspendAll(); + } + } + xTaskResumeAll(); + } + + /* Second section: */ + + /* Suspend the continuous counter task so it stops accessing the shared variable. */ + vTaskSuspend( xContinuousIncrementHandle ); + + /* Reset the variable. */ + ulCounter = ( unsigned long ) 0; + + /* Resume the limited count task which has a higher priority than us. + * We should therefore not return from this call until the limited count + * task has suspended itself with a known value in the counter variable. + * The scheduler suspension is not necessary but is included for test + * purposes. */ + vTaskSuspendAll(); + vTaskResume( xLimitedIncrementHandle ); + xTaskResumeAll(); + + /* Does the counter variable have the expected value? */ + if( ulCounter != priMAX_COUNT ) + { + sError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + + if( sError == pdFALSE ) + { + /* If no errors have occurred then increment the check variable. */ + portENTER_CRITICAL(); + usCheckVariable++; + portEXIT_CRITICAL(); + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Resume the continuous count task and do it all again. */ + vTaskResume( xContinuousIncrementHandle ); + } +} +/*-----------------------------------------------------------*/ + +static void vQueueSendWhenSuspendedTask( void * pvParameters ) +{ + static unsigned long ulValueToSend = ( unsigned long ) 0; + const char * const pcTaskStartMsg = "Queue send while suspended task started.\r\n"; + const char * const pcTaskFailMsg = "Queue send while suspended failed.\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ; ; ) + { + vTaskSuspendAll(); + { + /* We must not block while the scheduler is suspended! */ + if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) + { + if( xSuspendedQueueSendError == pdFALSE ) + { + xTaskResumeAll(); + vPrintDisplayMessage( &pcTaskFailMsg ); + vTaskSuspendAll(); + } + + xSuspendedQueueSendError = pdTRUE; + } + } + xTaskResumeAll(); + + vTaskDelay( priSLEEP_TIME ); + + ++ulValueToSend; + } +} +/*-----------------------------------------------------------*/ + +static void vQueueReceiveWhenSuspendedTask( void * pvParameters ) +{ + static unsigned long ulExpectedValue = ( unsigned long ) 0, ulReceivedValue; + const char * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n"; + const char * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n"; + portBASE_TYPE xGotValue; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ; ; ) + { + do + { + /* Suspending the scheduler here is fairly pointless and + * undesirable for a normal application. It is done here purely + * to test the scheduler. The inner xTaskResumeAll() should + * never return pdTRUE as the scheduler is still locked by the + * outer call. */ + vTaskSuspendAll(); + { + vTaskSuspendAll(); + { + xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); + } + + if( xTaskResumeAll() ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + } + xTaskResumeAll(); + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } while( xGotValue == pdFALSE ); + + if( ulReceivedValue != ulExpectedValue ) + { + if( xSuspendedQueueReceiveError == pdFALSE ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + } + + xSuspendedQueueReceiveError = pdTRUE; + } + + ++ulExpectedValue; + } +} +/*-----------------------------------------------------------*/ + +static void prvChangePriorityWhenSuspendedTask( void * pvParameters ) +{ + const char * const pcTaskStartMsg = "Priority change when suspended task started.\r\n"; + const char * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ; ; ) + { + /* Start with the counter at 0 so we know what the counter should be + * when we check it next. */ + ulPrioritySetCounter = ( unsigned long ) 0; + + /* Resume the helper task. At this time it has a priority lower than + * ours so no context switch should occur. */ + vTaskResume( xChangePriorityWhenSuspendedHandle ); + + /* Check to ensure the task just resumed has not executed. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned long ) 0 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + + /* Now try raising the priority while the scheduler is suspended. */ + vTaskSuspendAll(); + { + vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) ); + + /* Again, even though the helper task has a priority greater than + * ours, it should not have executed yet because the scheduler is + * suspended. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned long ) 0 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + } + xTaskResumeAll(); + + /* Now the scheduler has been resumed the helper task should + * immediately preempt us and execute. When it executes it will increment + * the ulPrioritySetCounter exactly once before suspending itself. + * + * We should now always find the counter set to 1. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned long ) 1 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + + /* Delay until we try this again. */ + vTaskDelay( priSLEEP_TIME * 2 ); + + /* Set the priority of the helper task back ready for the next + * execution of this task. */ + vTaskSuspendAll(); + vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY ); + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +static void prvChangePriorityHelperTask( void * pvParameters ) +{ + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* This is the helper task for prvChangePriorityWhenSuspendedTask(). + * It has it's priority raised and lowered. When it runs it simply + * increments the counter then suspends itself again. This allows + * prvChangePriorityWhenSuspendedTask() to know how many times it has + * executed. */ + ulPrioritySetCounter++; + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +/* Called to check that all the created tasks are still running without error. */ +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ) +{ +/* Keep a history of the check variables so we know if it has been incremented + * since the last call. */ + static unsigned short usLastTaskCheck = ( unsigned short ) 0; + portBASE_TYPE xReturn = pdTRUE; + + /* Check the tasks are still running by ensuring the check variable + * is still incrementing. */ + + if( usCheckVariable == usLastTaskCheck ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( xSuspendedQueueSendError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xSuspendedQueueReceiveError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xPriorityRaiseWhenSuspendedError == pdTRUE ) + { + xReturn = pdFALSE; + } + + usLastTaskCheck = usCheckVariable; + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/events.c b/SOFTWARE-FreeRTOS/Common/Full/events.c new file mode 100644 index 0000000..9745fdb --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/events.c @@ -0,0 +1,368 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * This file exercises the event mechanism whereby more than one task is + * blocked waiting for the same event. + * + * The demo creates five tasks - four 'event' tasks, and a controlling task. + * The event tasks have various different priorities and all block on reading + * the same queue. The controlling task writes data to the queue, then checks + * to see which of the event tasks read the data from the queue. The + * controlling task has the lowest priority of all the tasks so is guaranteed + * to always get preempted immediately upon writing to the queue. + * + * By selectively suspending and resuming the event tasks the controlling task + * can check that the highest priority task that is blocked on the queue is the + * task that reads the posted data from the queue. + * + * Two of the event tasks share the same priority. When neither of these tasks + * are suspended they should alternate - one reading one message from the queue, + * the other the next message, etc. + */ + +/* Standard includes. */ +#include +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "mevents.h" +#include "print.h" + +/* Demo specific constants. */ +#define evtSTACK_SIZE ( ( unsigned portBASE_TYPE ) configMINIMAL_STACK_SIZE ) +#define evtNUM_TASKS ( 4 ) +#define evtQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 3 ) +#define evtNO_DELAY 0 + +/* Just indexes used to uniquely identify the tasks. Note that two tasks are + * 'highest' priority. */ +#define evtHIGHEST_PRIORITY_INDEX_2 3 +#define evtHIGHEST_PRIORITY_INDEX_1 2 +#define evtMEDIUM_PRIORITY_INDEX 1 +#define evtLOWEST_PRIORITY_INDEX 0 + +/* Each event task increments one of these counters each time it reads data + * from the queue. */ +static volatile portBASE_TYPE xTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; + +/* Each time the controlling task posts onto the queue it increments the + * expected count of the task that it expected to read the data from the queue + * (i.e. the task with the highest priority that should be blocked on the queue). + * + * xExpectedTaskCounters are incremented from the controlling task, and + * xTaskCounters are incremented from the individual event tasks - therefore + * comparing xTaskCounters to xExpectedTaskCounters shows whether or not the + * correct task was unblocked by the post. */ +static portBASE_TYPE xExpectedTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; + +/* Handles to the four event tasks. These are required to suspend and resume + * the tasks. */ +static TaskHandle_t xCreatedTasks[ evtNUM_TASKS ]; + +/* The single queue onto which the controlling task posts, and the four event + * tasks block. */ +static QueueHandle_t xQueue; + +/* Flag used to indicate whether or not an error has occurred at any time. + * An error is either the queue being full when not expected, or an unexpected + * task reading data from the queue. */ +static portBASE_TYPE xHealthStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +/* Function that implements the event task. This is created four times. */ +static void prvMultiEventTask( void * pvParameters ); + +/* Function that implements the controlling task. */ +static void prvEventControllerTask( void * pvParameters ); + +/* This is a utility function that posts data to the queue, then compares + * xExpectedTaskCounters with xTaskCounters to ensure everything worked as + * expected. + * + * The event tasks all have higher priorities the controlling task. Therefore + * the controlling task will always get preempted between writhing to the queue + * and checking the task counters. + * + * @param xExpectedTask The index to the task that the controlling task thinks + * should be the highest priority task waiting for data, and + * therefore the task that will unblock. + * + * @param xIncrement The number of items that should be written to the queue. + */ +static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, + portBASE_TYPE xIncrement ); + +/* This is just incremented each cycle of the controlling tasks function so + * the main application can ensure the test is still running. */ +static portBASE_TYPE xCheckVariable = 0; + +/*-----------------------------------------------------------*/ + +void vStartMultiEventTasks( void ) +{ + /* Create the queue to be used for all the communications. */ + xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); + + /* Start the controlling task. This has the idle priority to ensure it is + * always preempted by the event tasks. */ + xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* Start the four event tasks. Note that two have priority 3, one + * priority 2 and the other priority 1. */ + xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) ); + xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) ); + xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) ); + xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) ); +} +/*-----------------------------------------------------------*/ + +static void prvMultiEventTask( void * pvParameters ) +{ + portBASE_TYPE * pxCounter; + unsigned portBASE_TYPE uxDummy; + const char * const pcTaskStartMsg = "Multi event task started.\r\n"; + + /* The variable this task will increment is passed in as a parameter. */ + pxCounter = ( portBASE_TYPE * ) pvParameters; + + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ; ; ) + { + /* Block on the queue. */ + if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) ) + { + /* We unblocked by reading the queue - so simply increment + * the counter specific to this task instance. */ + ( *pxCounter )++; + } + else + { + xHealthStatus = pdFAIL; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvEventControllerTask( void * pvParameters ) +{ + const char * const pcTaskStartMsg = "Multi event controller task started.\r\n"; + portBASE_TYPE xDummy = 0; + + /* Just to stop warnings. */ + ( void ) pvParameters; + + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ; ; ) + { + /* All tasks are blocked on the queue. When a message is posted one of + * the two tasks that share the highest priority should unblock to read + * the queue. The next message written should unblock the other task with + * the same high priority, and so on in order. No other task should + * unblock to read data as they have lower priorities. */ + + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* For the rest of these tests we don't need the second 'highest' + * priority task - so it is suspended. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); + + + + /* Now suspend the other highest priority task. The medium priority + * task will then be the task with the highest priority that remains + * blocked on the queue. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + + /* This time, when we post onto the queue we will expect the medium + * priority task to unblock and preempt us. */ + prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); + + /* Now try resuming the highest priority task while the scheduler is + * suspended. The task should start executing as soon as the scheduler + * is resumed - therefore when we post to the queue again, the highest + * priority task should again preempt us. */ + vTaskSuspendAll(); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + xTaskResumeAll(); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* Now we are going to suspend the high and medium priority tasks. The + * low priority task should then preempt us. Again the task suspension is + * done with the whole scheduler suspended just for test purposes. */ + vTaskSuspendAll(); + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + xTaskResumeAll(); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); + + /* Do the same basic test another few times - selectively suspending + * and resuming tasks and each time calling prvCheckTaskCounters() passing + * to the function the number of the task we expected to be unblocked by + * the post. */ + + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + vTaskSuspendAll(); /* Just for test. */ + vTaskSuspendAll(); /* Just for test. */ + vTaskSuspendAll(); /* Just for even more test. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + xTaskResumeAll(); + xTaskResumeAll(); + xTaskResumeAll(); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); + + vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); + + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* Now a slight change, first suspend all tasks. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + + /* Now when we resume the low priority task and write to the queue 3 + * times. We expect the low priority task to service the queue three + * times. */ + vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH ); + + /* Again suspend all tasks (only the low priority task is not suspended + * already). */ + vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + + /* This time we are going to suspend the scheduler, resume the low + * priority task, then resume the high priority task. In this state we + * will write to the queue three times. When the scheduler is resumed + * we expect the high priority task to service all three messages. */ + vTaskSuspendAll(); + { + vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + + for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ ) + { + if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) + { + xHealthStatus = pdFAIL; + } + } + + /* The queue should not have been serviced yet!. The scheduler + * is still suspended. */ + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + xHealthStatus = pdFAIL; + } + } + xTaskResumeAll(); + + /* We should have been preempted by resuming the scheduler - so by the + * time we are running again we expect the high priority task to have + * removed three items from the queue. */ + xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH; + + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + xHealthStatus = pdFAIL; + } + + /* The medium priority and second high priority tasks are still + * suspended. Make sure to resume them before starting again. */ + vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); + + /* Just keep incrementing to show the task is still executing. */ + xCheckVariable++; + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, + portBASE_TYPE xIncrement ) +{ + portBASE_TYPE xDummy = 0; + + /* Write to the queue the requested number of times. The data written is + * not important. */ + for( xDummy = 0; xDummy < xIncrement; xDummy++ ) + { + if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) + { + /* Did not expect to ever find the queue full. */ + xHealthStatus = pdFAIL; + } + } + + /* All the tasks blocked on the queue have a priority higher than the + * controlling task. Writing to the queue will therefore have caused this + * task to be preempted. By the time this line executes the event task will + * have executed and incremented its counter. Increment the expected counter + * to the same value. */ + ( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement; + + /* Check the actual counts and expected counts really are the same. */ + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + /* The counters were not the same. This means a task we did not expect + * to unblock actually did unblock. */ + xHealthStatus = pdFAIL; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreMultiEventTasksStillRunning( void ) +{ + static portBASE_TYPE xPreviousCheckVariable = 0; + + /* Called externally to periodically check that this test is still + * operational. */ + + if( xPreviousCheckVariable == xCheckVariable ) + { + xHealthStatus = pdFAIL; + } + + xPreviousCheckVariable = xCheckVariable; + + return xHealthStatus; +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/flash.c b/SOFTWARE-FreeRTOS/Common/Full/flash.c new file mode 100644 index 0000000..3f4d83d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/flash.c @@ -0,0 +1,126 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/** + * Creates eight tasks, each of which flash an LED at a different rate. The first + * LED flashes every 125ms, the second every 250ms, the third every 375ms, etc. + * + * The LED flash tasks provide instant visual feedback. They show that the scheduler + * is still operational. + * + * The PC port uses the standard parallel port for outputs, the Flashlite 186 port + * uses IO port F. + * + * \page flashC flash.c + * \ingroup DemoFiles + *
+ */ + +/* + * Changes from V2.0.0 + * + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + + + + Changes from V2.1.1 + + + + The stack size now uses configMINIMAL_STACK_SIZE. + + String constants made file scope to decrease stack depth on 8051 port. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash.h" +#include "print.h" + +#define ledSTACK_SIZE configMINIMAL_STACK_SIZE + +/* Structure used to pass parameters to the LED tasks. */ +typedef struct LED_PARAMETERS +{ + unsigned portBASE_TYPE uxLED; /*< The output the task should use. */ + TickType_t xFlashRate; /*< The rate at which the LED should flash. */ +} xLEDParameters; + +/* The task that is created eight times - each time with a different xLEDParameters + * structure passed in as the parameter. */ +static void vLEDFlashTask( void * pvParameters ); + +/* String to print if USE_STDIO is defined. */ +const char * const pcTaskStartMsg = "LED flash task started.\r\n"; + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ) +{ + unsigned portBASE_TYPE uxLEDTask; + xLEDParameters * pxLEDParameters; + const unsigned portBASE_TYPE uxNumOfLEDs = 8; + const TickType_t xFlashRate = 125; + + /* Create the eight tasks. */ + for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask ) + { + /* Create and complete the structure used to pass parameters to the next + * created task. */ + pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) ); + pxLEDParameters->uxLED = uxLEDTask; + pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( TickType_t ) uxLEDTask ) ); + pxLEDParameters->xFlashRate /= portTICK_PERIOD_MS; + + /* Spawn the task. */ + xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( TaskHandle_t * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void vLEDFlashTask( void * pvParameters ) +{ + xLEDParameters * pxParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + pxParameters = ( xLEDParameters * ) pvParameters; + + for( ; ; ) + { + /* Delay for half the flash period then turn the LED on. */ + vTaskDelay( pxParameters->xFlashRate / ( TickType_t ) 2 ); + vParTestToggleLED( pxParameters->uxLED ); + + /* Delay for half the flash period then turn the LED off. */ + vTaskDelay( pxParameters->xFlashRate / ( TickType_t ) 2 ); + vParTestToggleLED( pxParameters->uxLED ); + } +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/flop.c b/SOFTWARE-FreeRTOS/Common/Full/flop.c new file mode 100644 index 0000000..2731f3f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/flop.c @@ -0,0 +1,329 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Changes from V1.2.3 + * + + The created tasks now include calls to tskYIELD(), allowing them to be used + + with the cooperative scheduler. + */ + +/** + * Creates eight tasks, each of which loops continuously performing an (emulated) + * floating point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + * + * \page FlopC flop.c + * \ingroup DemoFiles + *
+ */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "print.h" + +/* Demo program include files. */ +#include "flop.h" + +#define mathSTACK_SIZE ( ( unsigned short ) 512 ) +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. + * Each of the four is created twice. */ +static void vCompetingMathTask1( void * pvParameters ); +static void vCompetingMathTask2( void * pvParameters ); +static void vCompetingMathTask3( void * pvParameters ); +static void vCompetingMathTask4( void * pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a + * task gets a calculation wrong it will + * stop incrementing its check variable. */ +static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask1( void * pvParameters ) +{ + portDOUBLE d1, d2, d3, d4; + volatile unsigned short * pusTaskCheckVariable; + const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222; + const char * const pcTaskStartMsg = "Math task 1 started.\r\n"; + const char * const pcTaskFailMsg = "Math task 1 failed.\r\n"; + short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ; ; ) + { + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + d4 = ( d1 + d2 ) * d3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + * increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask2( void * pvParameters ) +{ + portDOUBLE d1, d2, d3, d4; + volatile unsigned short * pusTaskCheckVariable; + const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001; + const char * const pcTaskStartMsg = "Math task 2 started.\r\n"; + const char * const pcTaskFailMsg = "Math task 2 failed.\r\n"; + short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ; ; ) + { + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + d4 = ( d1 / d2 ) * d3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + * increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know + * this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask3( void * pvParameters ) +{ + portDOUBLE * pdArray, dTotal1, dTotal2, dDifference; + volatile unsigned short * pusTaskCheckVariable; + const unsigned short usArraySize = 250; + unsigned short usPosition; + const char * const pcTaskStartMsg = "Math task 3 started.\r\n"; + const char * const pcTaskFailMsg = "Math task 3 failed.\r\n"; + short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + * array. Then run through the array adding up all the values. If the two totals + * do not match, stop the check variable from incrementing. */ + for( ; ; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5; + dTotal1 += ( portDOUBLE ) usPosition + 5.5; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + dTotal2 += pdArray[ usPosition ]; + } + + dDifference = dTotal1 - dTotal2; + + if( fabs( dDifference ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask4( void * pvParameters ) +{ + portDOUBLE * pdArray, dTotal1, dTotal2, dDifference; + volatile unsigned short * pusTaskCheckVariable; + const unsigned short usArraySize = 250; + unsigned short usPosition; + const char * const pcTaskStartMsg = "Math task 4 started.\r\n"; + const char * const pcTaskFailMsg = "Math task 4 failed.\r\n"; + short sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + * array. Then run through the array adding up all the values. If the two totals + * do not match, stop the check variable from incrementing. */ + for( ; ; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123; + dTotal1 += ( portDOUBLE ) usPosition * 12.123; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + dTotal2 += pdArray[ usPosition ]; + } + + dDifference = dTotal1 - dTotal2; + + if( fabs( dDifference ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented + * since the last call. */ + static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; + portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + * are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/integer.c b/SOFTWARE-FreeRTOS/Common/Full/integer.c new file mode 100644 index 0000000..d2047da --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/integer.c @@ -0,0 +1,325 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Changes from V1.2.3 + * + + The created tasks now include calls to tskYIELD(), allowing them to be used + + with the cooperative scheduler. + */ + +/** + * This does the same as flop. c, but uses variables of type long instead of + * type double. + * + * As with flop. c, the tasks created in this file are a good test of the + * scheduler context switch mechanism. The processor has to access 32bit + * variables in two or four chunks (depending on the processor). The low + * priority of these tasks means there is a high probability that a context + * switch will occur mid calculation. See the flop. c documentation for + * more information. + * + * \page IntegerC integer.c + * \ingroup DemoFiles + *
+ */ + +/* + * Changes from V1.2.1 + * + + The constants used in the calculations are larger to ensure the + + optimiser does not truncate them to 16 bits. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "print.h" + +/* Demo program include files. */ +#include "integer.h" + +#define intgSTACK_SIZE ( ( unsigned short ) 256 ) +#define intgNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different calculation on four byte + * variables. Each of the four is created twice. */ +static void vCompeteingIntMathTask1( void * pvParameters ); +static void vCompeteingIntMathTask2( void * pvParameters ); +static void vCompeteingIntMathTask3( void * pvParameters ); +static void vCompeteingIntMathTask4( void * pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +* task gets a calculation wrong it will stop incrementing its check variable. */ +static volatile unsigned short usTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; +/*-----------------------------------------------------------*/ + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask1( void * pvParameters ) +{ + long l1, l2, l3, l4; + short sError = pdFALSE; + volatile unsigned short * pusTaskCheckVariable; + const long lAnswer = ( ( long ) 74565L + ( long ) 1234567L ) * ( long ) -918L; + const char * const pcTaskStartMsg = "Integer math task 1 started.\r\n"; + const char * const pcTaskFailMsg = "Integer math task 1 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ; ; ) + { + l1 = ( long ) 74565L; + l2 = ( long ) 1234567L; + l3 = ( long ) -918L; + + l4 = ( l1 + l2 ) * l3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + * increment of the check variable. */ + if( l4 != lAnswer ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask2( void * pvParameters ) +{ + long l1, l2, l3, l4; + short sError = pdFALSE; + volatile unsigned short * pusTaskCheckVariable; + const long lAnswer = ( ( long ) -389000L / ( long ) 329999L ) * ( long ) -89L; + const char * const pcTaskStartMsg = "Integer math task 2 started.\r\n"; + const char * const pcTaskFailMsg = "Integer math task 2 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ; ; ) + { + l1 = -389000L; + l2 = 329999L; + l3 = -89L; + + l4 = ( l1 / l2 ) * l3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + * increment of the check variable. */ + if( l4 != lAnswer ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask3( void * pvParameters ) +{ + long * plArray, lTotal1, lTotal2; + short sError = pdFALSE; + volatile unsigned short * pusTaskCheckVariable; + const unsigned short usArraySize = ( unsigned short ) 250; + unsigned short usPosition; + const char * const pcTaskStartMsg = "Integer math task 3 started.\r\n"; + const char * const pcTaskFailMsg = "Integer math task 3 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Create the array we are going to use for our check calculation. */ + plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) ); + + /* Keep filling the array, keeping a running total of the values placed in the + * array. Then run through the array adding up all the values. If the two totals + * do not match, stop the check variable from incrementing. */ + for( ; ; ) + { + lTotal1 = ( long ) 0; + lTotal2 = ( long ) 0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + plArray[ usPosition ] = ( long ) usPosition + ( long ) 5; + lTotal1 += ( long ) usPosition + ( long ) 5; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + lTotal2 += plArray[ usPosition ]; + } + + if( lTotal1 != lTotal2 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask4( void * pvParameters ) +{ + long * plArray, lTotal1, lTotal2; + short sError = pdFALSE; + volatile unsigned short * pusTaskCheckVariable; + const unsigned short usArraySize = 250; + unsigned short usPosition; + const char * const pcTaskStartMsg = "Integer math task 4 started.\r\n"; + const char * const pcTaskFailMsg = "Integer math task 4 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( unsigned short * ) pvParameters; + + /* Create the array we are going to use for our check calculation. */ + plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) ); + + /* Keep filling the array, keeping a running total of the values placed in the + * array. Then run through the array adding up all the values. If the two totals + * do not match, stop the check variable from incrementing. */ + for( ; ; ) + { + lTotal1 = ( long ) 0; + lTotal2 = ( long ) 0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + plArray[ usPosition ] = ( long ) usPosition * ( long ) 12; + lTotal1 += ( long ) usPosition * ( long ) 12; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + lTotal2 += plArray[ usPosition ]; + } + + if( lTotal1 != lTotal2 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented + * since the last call. */ + static unsigned short usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned short ) 0 }; + portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + * are still incrementing. */ + for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/print.c b/SOFTWARE-FreeRTOS/Common/Full/print.c new file mode 100644 index 0000000..86d4418 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/print.c @@ -0,0 +1,103 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * Manages a queue of strings that are waiting to be displayed. This is used to + * ensure mutual exclusion of console output. + * + * A task wishing to display a message will call vPrintDisplayMessage (), with a + * pointer to the string as the parameter. The pointer is posted onto the + * xPrintQueue queue. + * + * The task spawned in main. c blocks on xPrintQueue. When a message becomes + * available it calls pcPrintGetNextMessage () to obtain a pointer to the next + * string, then uses the functions defined in the portable layer FileIO. c to + * display the message. + * + * NOTE: + * Using console IO can disrupt real time performance - depending on the port. + * Standard C IO routines are not designed for real time applications. While + * standard IO is useful for demonstration and debugging an alternative method + * should be used if you actually require console IO as part of your application. + * + * \page PrintC print.c + * \ingroup DemoFiles + *
+ */ + +/* + * Changes from V2.0.0 + * + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo program include files. */ +#include "print.h" + +static QueueHandle_t xPrintQueue; + +/*-----------------------------------------------------------*/ + +void vPrintInitialise( void ) +{ + const unsigned portBASE_TYPE uxQueueSize = 20; + + /* Create the queue on which errors will be reported. */ + xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( char * ) ); +} +/*-----------------------------------------------------------*/ + +void vPrintDisplayMessage( const char * const * ppcMessageToSend ) +{ + #ifdef USE_STDIO + xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( TickType_t ) 0 ); + #else + /* Stop warnings. */ + ( void ) ppcMessageToSend; + #endif +} +/*-----------------------------------------------------------*/ + +const char * pcPrintGetNextMessage( TickType_t xPrintRate ) +{ + char * pcMessage; + + if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS ) + { + return pcMessage; + } + else + { + return NULL; + } +} diff --git a/SOFTWARE-FreeRTOS/Common/Full/semtest.c b/SOFTWARE-FreeRTOS/Common/Full/semtest.c new file mode 100644 index 0000000..a267760 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Full/semtest.c @@ -0,0 +1,285 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * Creates two sets of two tasks. The tasks within a set share a variable, access + * to which is guarded by a semaphore. + * + * Each task starts by attempting to obtain the semaphore. On obtaining a + * semaphore a task checks to ensure that the guarded variable has an expected + * value. It then clears the variable to zero before counting it back up to the + * expected value in increments of 1. After each increment the variable is checked + * to ensure it contains the value to which it was just set. When the starting + * value is again reached the task releases the semaphore giving the other task in + * the set a chance to do exactly the same thing. The starting value is high + * enough to ensure that a tick is likely to occur during the incrementing loop. + * + * An error is flagged if at any time during the process a shared variable is + * found to have a value other than that expected. Such an occurrence would + * suggest an error in the mutual exclusion mechanism by which access to the + * variable is restricted. + * + * The first set of two tasks poll their semaphore. The second set use blocking + * calls. + * + * \page SemTestC semtest.c + * \ingroup DemoFiles + *
+ */ + +/* + * Changes from V1.2.0: + * + + The tasks that operate at the idle priority now use a lower expected + + count than those running at a higher priority. This prevents the low + + priority tasks from signaling an error because they have not been + + scheduled enough time for each of them to count the shared variable to + + the high value. + + + + Changes from V2.0.0 + + + + Delay periods are now specified using variables and constants of + + TickType_t rather than unsigned long. + + + + Changes from V2.1.1 + + + + The stack size now uses configMINIMAL_STACK_SIZE. + + String constants made file scope to decrease stack depth on 8051 port. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "semtest.h" +#include "print.h" + +/* The value to which the shared variables are counted. */ +#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xfff ) +#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xff ) + +#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE + +#define semtstNUM_TASKS ( 4 ) + +#define semtstDELAY_FACTOR ( ( TickType_t ) 10 ) + +/* The task function as described at the top of the file. */ +static void prvSemaphoreTest( void * pvParameters ); + +/* Structure used to pass parameters to each task. */ +typedef struct SEMAPHORE_PARAMETERS +{ + SemaphoreHandle_t xSemaphore; + volatile unsigned long * pulSharedVariable; + TickType_t xBlockTime; +} xSemaphoreParameters; + +/* Variables used to check that all the tasks are still running without errors. */ +static volatile short sCheckVariables[ semtstNUM_TASKS ] = { 0 }; +static volatile short sNextCheckVariable = 0; + +/* Strings to print if USE_STDIO is defined. */ +const char * const pcPollingSemaphoreTaskError = "Guarded shared variable in unexpected state.\r\n"; +const char * const pcSemaphoreTaskStart = "Guarded shared variable task started.\r\n"; + +/*-----------------------------------------------------------*/ + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ) +{ + xSemaphoreParameters * pxFirstSemaphoreParameters, * pxSecondSemaphoreParameters; + const TickType_t xBlockTime = ( TickType_t ) 100; + + /* Create the structure used to pass parameters to the first two tasks. */ + pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxFirstSemaphoreParameters != NULL ) + { + /* Create the semaphore used by the first two tasks. */ + vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore ); + + if( pxFirstSemaphoreParameters->xSemaphore != NULL ) + { + /* Create the variable which is to be shared by the first two tasks. */ + pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) ); + + /* Initialise the share variable to the value the tasks expect. */ + *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; + + /* The first two tasks do not block on semaphore calls. */ + pxFirstSemaphoreParameters->xBlockTime = ( TickType_t ) 0; + + /* Spawn the first two tasks. As they poll they operate at the idle priority. */ + xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL ); + xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL ); + } + } + + /* Do exactly the same to create the second set of tasks, only this time + * provide a block time for the semaphore calls. */ + pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxSecondSemaphoreParameters != NULL ) + { + vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore ); + + if( pxSecondSemaphoreParameters->xSemaphore != NULL ) + { + pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) ); + *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; + pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_PERIOD_MS; + + xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL ); + xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSemaphoreTest( void * pvParameters ) +{ + xSemaphoreParameters * pxParameters; + volatile unsigned long * pulSharedVariable, ulExpectedValue; + unsigned long ulCounter; + short sError = pdFALSE, sCheckVariableToUse; + + /* See which check variable to use. sNextCheckVariable is not semaphore + * protected! */ + portENTER_CRITICAL(); + sCheckVariableToUse = sNextCheckVariable; + sNextCheckVariable++; + portEXIT_CRITICAL(); + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcSemaphoreTaskStart ); + + /* A structure is passed in as the parameter. This contains the shared + * variable being guarded. */ + pxParameters = ( xSemaphoreParameters * ) pvParameters; + pulSharedVariable = pxParameters->pulSharedVariable; + + /* If we are blocking we use a much higher count to ensure loads of context + * switches occur during the count. */ + if( pxParameters->xBlockTime > ( TickType_t ) 0 ) + { + ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; + } + else + { + ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; + } + + for( ; ; ) + { + /* Try to obtain the semaphore. */ + if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) + { + /* We have the semaphore and so expect any other tasks using the + * shared variable to have left it in the state we expect to find + * it. */ + if( *pulSharedVariable != ulExpectedValue ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + sError = pdTRUE; + } + + /* Clear the variable, then count it back up to the expected value + * before releasing the semaphore. Would expect a context switch or + * two during this time. */ + for( ulCounter = ( unsigned long ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) + { + *pulSharedVariable = ulCounter; + + if( *pulSharedVariable != ulCounter ) + { + if( sError == pdFALSE ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + } + + sError = pdTRUE; + } + } + + /* Release the semaphore, and if no errors have occurred increment the check + * variable. */ + if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + if( sCheckVariableToUse < semtstNUM_TASKS ) + { + ( sCheckVariables[ sCheckVariableToUse ] )++; + } + } + + /* If we have a block time then we are running at a priority higher + * than the idle priority. This task takes a long time to complete + * a cycle (deliberately so to test the guarding) so will be starving + * out lower priority tasks. Block for some time to allow give lower + * priority tasks some processor time. */ + vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); + } + else + { + if( pxParameters->xBlockTime == ( TickType_t ) 0 ) + { + /* We have not got the semaphore yet, so no point using the + * processor. We are not blocking when attempting to obtain the + * semaphore. */ + taskYIELD(); + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreSemaphoreTasksStillRunning( void ) +{ + static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; + portBASE_TYPE xTask, xReturn = pdTRUE; + + for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) + { + if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) + { + xReturn = pdFALSE; + } + + sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/AbortDelay.c b/SOFTWARE-FreeRTOS/Common/Minimal/AbortDelay.c new file mode 100644 index 0000000..55f0ba6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/AbortDelay.c @@ -0,0 +1,799 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This file contains some test scenarios that ensure tasks respond correctly + * to xTaskAbortDelay() calls. It also ensures tasks return the correct state + * of eBlocked when blocked indefinitely in both the case where a task is + * blocked on an object and when a task is blocked on a notification. + */ + +/* Standard includes. */ +#include "limits.h" + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" +#include "event_groups.h" +#include "stream_buffer.h" + +/* Demo includes. */ +#include "AbortDelay.h" + +/* This file can only be used if the functionality it tests is included in the + * build. Remove the whole file if this is not the case. */ +#if ( INCLUDE_xTaskAbortDelay == 1 ) + + #if ( INCLUDE_xTaskGetHandle != 1 ) + #error This test file uses the xTaskGetHandle() API function so INCLUDE_xTaskGetHandle must be set to 1 in FreeRTOSConfig.h. + #endif + +/* Task priorities. Allow these to be overridden. */ + #ifndef abtCONTROLLING_PRIORITY + #define abtCONTROLLING_PRIORITY ( configMAX_PRIORITIES - 3 ) + #endif + + #ifndef abtBLOCKING_PRIORITY + #define abtBLOCKING_PRIORITY ( configMAX_PRIORITIES - 2 ) + #endif + +/* The tests that are performed. */ + #define abtNOTIFY_WAIT_ABORTS 0 + #define abtNOTIFY_TAKE_ABORTS 1 + #define abtDELAY_ABORTS 2 + #define abtDELAY_UNTIL_ABORTS 3 + #define abtSEMAPHORE_TAKE_ABORTS 4 + #define abtEVENT_GROUP_ABORTS 5 + #define abtQUEUE_SEND_ABORTS 6 + #define abtSTREAM_BUFFER_RECEIVE 7 + #define abtMAX_TESTS 8 + +/*-----------------------------------------------------------*/ + +/* + * The two test tasks. The controlling task specifies which test to executed. + * More information is provided in the comments within the tasks. + */ + static void prvControllingTask( void * pvParameters ); + static void prvBlockingTask( void * pvParameters ); + +/* + * Test functions called by the blocking task. Each function follows the same + * pattern, but the way the task blocks is different in each case. + * + * In each function three blocking calls are made. The first and third + * blocking call is expected to time out, while the middle blocking call is + * expected to be aborted by the controlling task half way through the block + * time. + */ + static void prvTestAbortingTaskNotifyWait( void ); + static void prvTestAbortingTaskNotifyTake( void ); + static void prvTestAbortingTaskDelay( void ); + static void prvTestAbortingTaskDelayUntil( void ); + static void prvTestAbortingSemaphoreTake( void ); + static void prvTestAbortingEventGroupWait( void ); + static void prvTestAbortingQueueSend( void ); + static void prvTestAbortingStreamBufferReceive( void ); + +/* + * Performs a few tests to cover code paths not otherwise covered by the continuous + * tests. + */ + static void prvPerformSingleTaskTests( void ); + +/* + * Checks the amount of time a task spent in the Blocked state is within the + * expected bounds. + */ + static void prvCheckExpectedTimeIsWithinAnAcceptableMargin( TickType_t xStartTime, + TickType_t xExpectedBlockTime ); + +/*-----------------------------------------------------------*/ + +/* Used to ensure that tasks are still executing without error. */ + static volatile BaseType_t xControllingCycles = 0, xBlockingCycles = 0; + static volatile BaseType_t xErrorOccurred = pdFALSE; + +/* Each task needs to know the other tasks handle so they can send signals to + * each other. The handle is obtained from the task's name. */ + static const char * pcControllingTaskName = "AbtCtrl", * pcBlockingTaskName = "AbtBlk"; + +/* The maximum amount of time a task will block for. */ + const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 100 ); + const TickType_t xHalfMaxBlockTime = pdMS_TO_TICKS( 50 ); + +/* The actual block time is dependent on the priority of other tasks in the + * system so the actual block time might be greater than that expected, but it + * should be within an acceptable upper bound. */ + const TickType_t xAllowableMargin = pdMS_TO_TICKS( 7 ); + +/*-----------------------------------------------------------*/ + + void vCreateAbortDelayTasks( void ) + { + /* Create the two test tasks described above. */ + xTaskCreate( prvControllingTask, pcControllingTaskName, configMINIMAL_STACK_SIZE, NULL, abtCONTROLLING_PRIORITY, NULL ); + xTaskCreate( prvBlockingTask, pcBlockingTaskName, configMINIMAL_STACK_SIZE, NULL, abtBLOCKING_PRIORITY, NULL ); + } +/*-----------------------------------------------------------*/ + + static void prvControllingTask( void * pvParameters ) + { + TaskHandle_t xBlockingTask; + uint32_t ulTestToPerform = abtNOTIFY_WAIT_ABORTS; + TickType_t xTimeAtStart; + const TickType_t xStartMargin = 2UL; + + /* Just to remove compiler warnings. */ + ( void ) pvParameters; + + xBlockingTask = xTaskGetHandle( pcBlockingTaskName ); + configASSERT( xBlockingTask ); + + for( ; ; ) + { + /* Tell the secondary task to perform the next test. */ + xTimeAtStart = xTaskGetTickCount(); + xTaskNotify( xBlockingTask, ulTestToPerform, eSetValueWithOverwrite ); + + /* The secondary task has a higher priority, so will now be in the + * Blocked state to wait for a maximum of xMaxBlockTime. It expects that + * period to complete with a timeout. It will then block for + * xMaxBlockTimeAgain, but this time it expects to the block time to abort + * half way through. Block until it is time to send the abort to the + * secondary task. xStartMargin is used because this task takes timing + * from the beginning of the test, whereas the blocking task takes timing + * from the entry into the Blocked state - and as the tasks run at + * different priorities, there may be some discrepancy. Also, temporarily + * raise the priority of the controlling task to that of the blocking + * task to minimise discrepancies. */ + vTaskPrioritySet( NULL, abtBLOCKING_PRIORITY ); + vTaskDelay( xMaxBlockTime + xHalfMaxBlockTime + xStartMargin ); + + if( xTaskAbortDelay( xBlockingTask ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + /* Reset the priority to the normal controlling priority. */ + vTaskPrioritySet( NULL, abtCONTROLLING_PRIORITY ); + + /* Now wait to be notified that the secondary task has completed its + * test. */ + ulTaskNotifyTake( pdTRUE, portMAX_DELAY ); + + /* Did the entire test run for the expected time, which is two full + * block times plus the half block time caused by calling + * xTaskAbortDelay()? */ + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, ( xMaxBlockTime + xMaxBlockTime + xHalfMaxBlockTime ) ); + + /* Move onto the next test. */ + ulTestToPerform++; + + if( ulTestToPerform >= abtMAX_TESTS ) + { + ulTestToPerform = 0; + } + + /* To indicate this task is still executing. */ + xControllingCycles++; + } + } +/*-----------------------------------------------------------*/ + + static void prvBlockingTask( void * pvParameters ) + { + TaskHandle_t xControllingTask; + uint32_t ulNotificationValue; + const uint32_t ulMax = 0xffffffffUL; + + /* Just to remove compiler warnings. */ + ( void ) pvParameters; + + /* Start by performing a few tests to cover code not exercised in the loops + * below. */ + prvPerformSingleTaskTests(); + + xControllingTask = xTaskGetHandle( pcControllingTaskName ); + configASSERT( xControllingTask ); + + for( ; ; ) + { + /* Wait to be notified of the test that is to be performed next. */ + xTaskNotifyWait( 0, ulMax, &ulNotificationValue, portMAX_DELAY ); + + switch( ulNotificationValue ) + { + case abtNOTIFY_WAIT_ABORTS: + prvTestAbortingTaskNotifyWait(); + break; + + case abtNOTIFY_TAKE_ABORTS: + prvTestAbortingTaskNotifyTake(); + break; + + case abtDELAY_ABORTS: + prvTestAbortingTaskDelay(); + break; + + case abtDELAY_UNTIL_ABORTS: + prvTestAbortingTaskDelayUntil(); + break; + + case abtSEMAPHORE_TAKE_ABORTS: + prvTestAbortingSemaphoreTake(); + break; + + case abtEVENT_GROUP_ABORTS: + prvTestAbortingEventGroupWait(); + break; + + case abtQUEUE_SEND_ABORTS: + prvTestAbortingQueueSend(); + break; + + case abtSTREAM_BUFFER_RECEIVE: + prvTestAbortingStreamBufferReceive(); + break; + + default: + /* Should not get here. */ + break; + } + + /* Let the primary task know the test is complete. */ + xTaskNotifyGive( xControllingTask ); + + /* To indicate this task is still executing. */ + xBlockingCycles++; + } + } +/*-----------------------------------------------------------*/ + + static void prvPerformSingleTaskTests( void ) + { + TaskHandle_t xThisTask; + BaseType_t xReturned; + + /* Try unblocking this task using both the task and ISR versions of the API - + * both should return false as this task is not blocked. */ + xThisTask = xTaskGetCurrentTaskHandle(); + + xReturned = xTaskAbortDelay( xThisTask ); + + if( xReturned != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + } +/*-----------------------------------------------------------*/ + + static void prvTestAbortingTaskDelayUntil( void ) + { + TickType_t xTimeAtStart, xLastBlockTime; + BaseType_t xReturned; + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* Take a copy of the time as it is updated in the call to + * xTaskDelayUntil() but its original value is needed to determine the actual + * time spend in the Blocked state. */ + xLastBlockTime = xTimeAtStart; + + /* This first delay should just time out. */ + xReturned = xTaskDelayUntil( &xLastBlockTime, xMaxBlockTime ); + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + configASSERT( xReturned == pdTRUE ); + + /* Remove compiler warning about value being set but not used in the case + * configASSERT() is not defined. */ + ( void ) xReturned; + + /* This second delay should be aborted by the primary task half way + * through. Again take a copy of the time as it is updated in the call to + * vTaskDelayUntil() buts its original value is needed to determine the amount + * of time actually spent in the Blocked state. This uses vTaskDelayUntil() + * in place of xTaskDelayUntil() for test coverage. */ + xTimeAtStart = xTaskGetTickCount(); + xLastBlockTime = xTimeAtStart; + vTaskDelayUntil( &xLastBlockTime, xMaxBlockTime ); + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime ); + + /* As with the other tests, the third block period should not time out. */ + xTimeAtStart = xTaskGetTickCount(); + xLastBlockTime = xTimeAtStart; + xReturned = xTaskDelayUntil( &xLastBlockTime, xMaxBlockTime ); + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + configASSERT( xReturned == pdTRUE ); + + /* Remove compiler warning about value being set but not used in the case + * configASSERT() is not defined. */ + ( void ) xReturned; + } +/*-----------------------------------------------------------*/ + + static void prvTestAbortingTaskDelay( void ) + { + TickType_t xTimeAtStart; + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This first delay should just time out. */ + vTaskDelay( xMaxBlockTime ); + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This second delay should be aborted by the primary task half way + * through. */ + vTaskDelay( xMaxBlockTime ); + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This third delay should just time out again. */ + vTaskDelay( xMaxBlockTime ); + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + } +/*-----------------------------------------------------------*/ + + static void prvTestAbortingTaskNotifyTake( void ) + { + TickType_t xTimeAtStart; + uint32_t ulReturn; + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This first delay should just time out. */ + ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime ); + + if( ulReturn != 0 ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This second delay should be aborted by the primary task half way + * through. */ + ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime ); + + if( ulReturn != 0 ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This third delay should just time out again. */ + ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime ); + + if( ulReturn != 0 ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + } +/*-----------------------------------------------------------*/ + + static void prvTestAbortingEventGroupWait( void ) + { + TickType_t xTimeAtStart; + EventGroupHandle_t xEventGroup; + EventBits_t xBitsToWaitFor = ( EventBits_t ) 0x01, xReturn; + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + static StaticEventGroup_t xEventGroupBuffer; + + /* Create the event group. Statically allocated memory is used so the + * creation cannot fail. */ + xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer ); + } + #else + { + xEventGroup = xEventGroupCreate(); + configASSERT( xEventGroup ); + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This first delay should just time out. */ + xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime ); + + if( xReturn != 0x00 ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This second delay should be aborted by the primary task half way + * through. */ + xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime ); + + if( xReturn != 0x00 ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This third delay should just time out again. */ + xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime ); + + if( xReturn != 0x00 ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Not really necessary in this case, but for completeness. */ + vEventGroupDelete( xEventGroup ); + } +/*-----------------------------------------------------------*/ + + static void prvTestAbortingStreamBufferReceive( void ) + { + TickType_t xTimeAtStart; + StreamBufferHandle_t xStreamBuffer; + size_t xReturn; + const size_t xTriggerLevelBytes = ( size_t ) 1; + uint8_t uxRxData; + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Defines the memory that will actually hold the streams within the + * stream buffer. */ + static uint8_t ucStorageBuffer[ sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) + 1 ]; + + /* The variable used to hold the stream buffer structure. */ + StaticStreamBuffer_t xStreamBufferStruct; + + + xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ), + xTriggerLevelBytes, + ucStorageBuffer, + &xStreamBufferStruct ); + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xStreamBuffer = xStreamBufferCreate( sizeof( uint8_t ), xTriggerLevelBytes ); + configASSERT( xStreamBuffer ); + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This first delay should just time out. */ + xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime ); + + if( xReturn != 0x00 ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This second delay should be aborted by the primary task half way + * through xMaxBlockTime. */ + xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime ); + + if( xReturn != 0x00 ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This third delay should just time out again. */ + xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime ); + + if( xReturn != 0x00 ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Not really necessary in this case, but for completeness. */ + vStreamBufferDelete( xStreamBuffer ); + } +/*-----------------------------------------------------------*/ + + static void prvTestAbortingQueueSend( void ) + { + TickType_t xTimeAtStart; + BaseType_t xReturn; + const UBaseType_t xQueueLength = ( UBaseType_t ) 1; + QueueHandle_t xQueue; + uint8_t ucItemToQueue; + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + static StaticQueue_t xQueueBuffer; + static uint8_t ucQueueStorage[ sizeof( uint8_t ) ]; + + /* Create the queue. Statically allocated memory is used so the + * creation cannot fail. */ + xQueue = xQueueCreateStatic( xQueueLength, sizeof( uint8_t ), ucQueueStorage, &xQueueBuffer ); + } + #else + { + xQueue = xQueueCreate( xQueueLength, sizeof( uint8_t ) ); + configASSERT( xQueue ); + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + + /* This function tests aborting when in the blocked state waiting to send, + * so the queue must be full. There is only one space in the queue. */ + xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime ); + + if( xReturn != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This first delay should just time out. */ + xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime ); + + if( xReturn != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This second delay should be aborted by the primary task half way + * through. */ + xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime ); + + if( xReturn != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This third delay should just time out again. */ + xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime ); + + if( xReturn != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Not really necessary in this case, but for completeness. */ + vQueueDelete( xQueue ); + } +/*-----------------------------------------------------------*/ + + static void prvTestAbortingSemaphoreTake( void ) + { + TickType_t xTimeAtStart; + BaseType_t xReturn; + SemaphoreHandle_t xSemaphore; + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + static StaticSemaphore_t xSemaphoreBuffer; + + /* Create the semaphore. Statically allocated memory is used so the + * creation cannot fail. */ + xSemaphore = xSemaphoreCreateBinaryStatic( &xSemaphoreBuffer ); + } + #else + { + xSemaphore = xSemaphoreCreateBinary(); + } + #endif + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This first delay should just time out. */ + xReturn = xSemaphoreTake( xSemaphore, xMaxBlockTime ); + + if( xReturn != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This second delay should be aborted by the primary task half way + * through xMaxBlockTime. */ + xReturn = xSemaphoreTake( xSemaphore, portMAX_DELAY ); + + if( xReturn != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This third delay should just time out again. */ + xReturn = xSemaphoreTake( xSemaphore, xMaxBlockTime ); + + if( xReturn != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Not really necessary in this case, but for completeness. */ + vSemaphoreDelete( xSemaphore ); + } +/*-----------------------------------------------------------*/ + + static void prvTestAbortingTaskNotifyWait( void ) + { + TickType_t xTimeAtStart; + BaseType_t xReturn; + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This first delay should just time out. */ + xReturn = xTaskNotifyWait( 0, 0, NULL, xMaxBlockTime ); + + if( xReturn != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This second delay should be aborted by the primary task half way + * through xMaxBlockTime. */ + xReturn = xTaskNotifyWait( 0, 0, NULL, portMAX_DELAY ); + + if( xReturn != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime ); + + /* Note the time before the delay so the length of the delay is known. */ + xTimeAtStart = xTaskGetTickCount(); + + /* This third delay should just time out again. */ + xReturn = xTaskNotifyWait( 0, 0, NULL, xMaxBlockTime ); + + if( xReturn != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime ); + } +/*-----------------------------------------------------------*/ + + static void prvCheckExpectedTimeIsWithinAnAcceptableMargin( TickType_t xStartTime, + TickType_t xExpectedBlockTime ) + { + TickType_t xTimeNow, xActualBlockTime; + + xTimeNow = xTaskGetTickCount(); + xActualBlockTime = xTimeNow - xStartTime; + + /* The actual block time should not be less than the expected block time. */ + if( xActualBlockTime < xExpectedBlockTime ) + { + xErrorOccurred = __LINE__; + } + + /* The actual block time can be greater than the expected block time, as it + * depends on the priority of the other tasks, but it should be within an + * acceptable margin. */ + if( xActualBlockTime > ( xExpectedBlockTime + xAllowableMargin ) ) + { + xErrorOccurred = __LINE__; + } + } +/*-----------------------------------------------------------*/ + + BaseType_t xAreAbortDelayTestTasksStillRunning( void ) + { + static BaseType_t xLastControllingCycleCount = 0, xLastBlockingCycleCount = 0; + BaseType_t xReturn = pdPASS; + + /* Have both tasks performed at least one cycle since this function was + * last called? */ + if( xControllingCycles == xLastControllingCycleCount ) + { + xReturn = pdFAIL; + } + + if( xBlockingCycles == xLastBlockingCycleCount ) + { + xReturn = pdFAIL; + } + + if( xErrorOccurred != pdFALSE ) + { + xReturn = pdFAIL; + } + + xLastBlockingCycleCount = xBlockingCycles; + xLastControllingCycleCount = xControllingCycles; + + return xReturn; + } + +#endif /* INCLUDE_xTaskAbortDelay == 1 */ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/BlockQ.c b/SOFTWARE-FreeRTOS/Common/Minimal/BlockQ.c new file mode 100644 index 0000000..e8f8ef4 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/BlockQ.c @@ -0,0 +1,306 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "BlockQ.h" + +#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE +#define blckqNUM_TASK_SETS ( 3 ) + +#define blckqSHORT_DELAY ( 5 ) +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This example cannot be used if dynamic allocation is not allowed. +#endif + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + QueueHandle_t xQueue; /*< The queue to be used by the task. */ + TickType_t xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile short * psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that + * it is the expected number. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and + * found to be the expected value. + * These are used to check that the tasks are still running. */ +static volatile short sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These + * are used to check that the tasks are still running. */ +static volatile short sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartBlockingQueueTasks( UBaseType_t uxPriority ) +{ + xBlockingQueueParameters * pxQueueParameters1, * pxQueueParameters2; + xBlockingQueueParameters * pxQueueParameters3, * pxQueueParameters4; + xBlockingQueueParameters * pxQueueParameters5, * pxQueueParameters6; + const UBaseType_t uxQueueSize1 = 1, uxQueueSize5 = 5; + const TickType_t xBlockTime = pdMS_TO_TICKS( ( TickType_t ) 1000 ); + const TickType_t xDontBlock = ( TickType_t ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + * Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( UBaseType_t ) sizeof( uint16_t ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + * is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + * wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + * it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + * spawned. */ + xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + * the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( UBaseType_t ) sizeof( uint16_t ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueConsumer, "QConsB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueProducer, "QProdB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + * the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( UBaseType_t ) sizeof( uint16_t ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters ) +{ + uint16_t usValue = 0; + xBlockingQueueParameters * pxQueueParameters; + short sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ; ; ) + { + if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + * used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + * consumer will expect the numbers to follow in numerical order. */ + ++usValue; + + #if ( configNUMBER_OF_CORES > 1 ) + { + if( pxQueueParameters->xBlockTime == 0 ) + { + vTaskDelay( blckqSHORT_DELAY ); + } + } + #elif configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters ) +{ + uint16_t usData, usExpectedValue = 0; + xBlockingQueueParameters * pxQueueParameters; + short sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ; ; ) + { + if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + * variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + * round. */ + ++usExpectedValue; + } + + #if ( configNUMBER_OF_CORES > 1 ) + { + if( pxQueueParameters->xBlockTime == 0 ) + { + vTaskDelay( blckqSHORT_DELAY ); + } + } + #elif configUSE_PREEMPTION == 0 + { + if( pxQueueParameters->xBlockTime == 0 ) + { + taskYIELD(); + } + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreBlockingQueuesStillRunning( void ) +{ + static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 }; + static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 }; + BaseType_t xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + * bits and we are only reading them. We also only care to see if they have + * changed or not. + * + * Loop through each check variable to and return pdFALSE if any are found not + * to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/EventGroupsDemo.c b/SOFTWARE-FreeRTOS/Common/Minimal/EventGroupsDemo.c new file mode 100644 index 0000000..4806e74 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/EventGroupsDemo.c @@ -0,0 +1,1058 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + +/* + * This file contains fairly comprehensive checks on the behaviour of event + * groups. It is not intended to be a user friendly demonstration of the + * event groups API. + * + * NOTE: The tests implemented in this file are informal 'sanity' tests + * only and are not part of the module tests that make use of the + * mtCOVERAGE_TEST_MARKER macro within the event groups implementation. + */ + + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "event_groups.h" + +/* Demo app includes. */ +#include "EventGroupsDemo.h" + +#if ( INCLUDE_eTaskGetState != 1 ) + #error INCLUDE_eTaskGetState must be set to 1 in FreeRTOSConfig.h to use this demo file. +#endif + +/* Priorities used by the tasks. */ +#define ebSET_BIT_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define ebWAIT_BIT_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* Generic bit definitions. */ +#define ebBIT_0 ( 0x01 ) +#define ebBIT_1 ( 0x02 ) +#define ebBIT_2 ( 0x04 ) +#define ebBIT_3 ( 0x08 ) +#define ebBIT_4 ( 0x10 ) +#define ebBIT_5 ( 0x20 ) +#define ebBIT_6 ( 0x40 ) +#define ebBIT_7 ( 0x80 ) + +/* Combinations of bits used in the demo. */ +#define ebCOMBINED_BITS ( ebBIT_1 | ebBIT_5 | ebBIT_7 ) +#define ebALL_BITS ( ebBIT_0 | ebBIT_1 | ebBIT_2 | ebBIT_3 | ebBIT_4 | ebBIT_5 | ebBIT_6 | ebBIT_7 ) + +/* Associate a bit to each task. These bits are used to identify all the tasks + * that synchronise with the xEventGroupSync() function. */ +#define ebSET_BIT_TASK_SYNC_BIT ebBIT_0 +#define ebWAIT_BIT_TASK_SYNC_BIT ebBIT_1 +#define ebRENDEZVOUS_TASK_1_SYNC_BIT ebBIT_2 +#define ebRENDEZVOUS_TASK_2_SYNC_BIT ebBIT_3 +#define ebALL_SYNC_BITS ( ebSET_BIT_TASK_SYNC_BIT | ebWAIT_BIT_TASK_SYNC_BIT | ebRENDEZVOUS_TASK_1_SYNC_BIT | ebRENDEZVOUS_TASK_2_SYNC_BIT ) + +/* A block time of zero simply means "don't block". */ +#define ebDONT_BLOCK ( 0 ) + +/* A 5ms delay. */ +#define ebSHORT_DELAY pdMS_TO_TICKS( ( TickType_t ) 5 ) + +/* Used in the selective bits test which checks no, one or both tasks blocked on + * event bits in a group are unblocked as appropriate as different bits get set. */ +#define ebSELECTIVE_BITS_1 0x03 +#define ebSELECTIVE_BITS_2 0x05 + +#ifndef ebRENDEZVOUS_TEST_TASK_STACK_SIZE + #define ebRENDEZVOUS_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE +#endif + +#ifndef ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE + #define ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE +#endif + +/*-----------------------------------------------------------*/ + +/* + * NOTE: The tests implemented in this function are informal 'sanity' tests + * only and are not part of the module tests that make use of the + * mtCOVERAGE_TEST_MARKER macro within the event groups implementation. + * + * The master test task. This task: + * + * 1) Calls prvSelectiveBitsTestMasterFunction() to test the behaviour when two + * tasks are blocked on different bits in an event group. The counterpart of + * this test is implemented by the prvSelectiveBitsTestSlaveFunction() + * function (which is called by the two tasks that block on the event group). + * + * 2) Calls prvBitCombinationTestMasterFunction() to test the behaviour when + * just one task is blocked on various combinations of bits within an event + * group. The counterpart of this test is implemented within the 'test + * slave' task. + * + * 3) Calls prvPerformTaskSyncTests() to test task synchronisation behaviour. + */ +static void prvTestMasterTask( void * pvParameters ); + +/* + * A helper task that enables the 'test master' task to perform several + * behavioural tests. See the comments above the prvTestMasterTask() prototype + * above. + */ +static void prvTestSlaveTask( void * pvParameters ); + +/* + * The part of the test that is performed between the 'test master' task and the + * 'test slave' task to test the behaviour when the slave blocks on various + * event bit combinations. + */ +static BaseType_t prvBitCombinationTestMasterFunction( BaseType_t xError, + TaskHandle_t xTestSlaveTaskHandle ); + +/* + * The part of the test that uses all the tasks to test the task synchronisation + * behaviour. + */ +static BaseType_t prvPerformTaskSyncTests( BaseType_t xError, + TaskHandle_t xTestSlaveTaskHandle ); + +/* + * Two instances of prvSyncTask() are created. They start by calling + * prvSelectiveBitsTestSlaveFunction() to act as slaves when the test master is + * executing the prvSelectiveBitsTestMasterFunction() function. They then loop + * to test the task synchronisation (rendezvous) behaviour. + */ +static void prvSyncTask( void * pvParameters ); + +/* + * Functions used in a test that blocks two tasks on various different bits + * within an event group - then sets each bit in turn and checks that the + * correct tasks unblock at the correct times. + */ +static BaseType_t prvSelectiveBitsTestMasterFunction( void ); +static void prvSelectiveBitsTestSlaveFunction( void ); + +/*-----------------------------------------------------------*/ + +/* Variables that are incremented by the tasks on each cycle provided no errors + * have been found. Used to detect an error or stall in the test cycling. */ +static volatile uint32_t ulTestMasterCycles = 0, ulTestSlaveCycles = 0, ulISRCycles = 0; + +/* The event group used by all the task based tests. */ +static EventGroupHandle_t xEventGroup = NULL; + +/* The event group used by the interrupt based tests. */ +static EventGroupHandle_t xISREventGroup = NULL; + +/* Handles to the tasks that only take part in the synchronisation calls. */ +static TaskHandle_t xSyncTask1 = NULL, xSyncTask2 = NULL; + +/*-----------------------------------------------------------*/ + +void vStartEventGroupTasks( void ) +{ + TaskHandle_t xTestSlaveTaskHandle; + + /* + * This file contains fairly comprehensive checks on the behaviour of event + * groups. It is not intended to be a user friendly demonstration of the + * event groups API. + * + * NOTE: The tests implemented in this file are informal 'sanity' tests + * only and are not part of the module tests that make use of the + * mtCOVERAGE_TEST_MARKER macro within the event groups implementation. + * + * Create the test tasks as described at the top of this file. + */ + xTaskCreate( prvTestSlaveTask, "WaitO", ebRENDEZVOUS_TEST_TASK_STACK_SIZE, NULL, ebWAIT_BIT_TASK_PRIORITY, &xTestSlaveTaskHandle ); + xTaskCreate( prvTestMasterTask, "SetB", ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE, ( void * ) xTestSlaveTaskHandle, ebSET_BIT_TASK_PRIORITY, NULL ); + xTaskCreate( prvSyncTask, "Rndv", ebRENDEZVOUS_TEST_TASK_STACK_SIZE, ( void * ) ebRENDEZVOUS_TASK_1_SYNC_BIT, ebWAIT_BIT_TASK_PRIORITY, &xSyncTask1 ); + xTaskCreate( prvSyncTask, "Rndv", ebRENDEZVOUS_TEST_TASK_STACK_SIZE, ( void * ) ebRENDEZVOUS_TASK_2_SYNC_BIT, ebWAIT_BIT_TASK_PRIORITY, &xSyncTask2 ); + + /* If the last task was created then the others will have been too. */ + configASSERT( xSyncTask2 ); + + /* Create the event group used by the ISR tests. The event group used by + * the tasks is created by the tasks themselves. */ + xISREventGroup = xEventGroupCreate(); + configASSERT( xISREventGroup ); +} +/*-----------------------------------------------------------*/ + +static void prvTestMasterTask( void * pvParameters ) +{ + BaseType_t xError; + +/* The handle to the slave task is passed in as the task parameter. */ + TaskHandle_t xTestSlaveTaskHandle = ( TaskHandle_t ) pvParameters; + + /* Avoid compiler warnings. */ + ( void ) pvParameters; + + /* Create the event group used by the tasks ready for the initial tests. */ + xEventGroup = xEventGroupCreate(); + configASSERT( xEventGroup ); + + /* Perform the tests that block two tasks on different combinations of bits, + * then set each bit in turn and check the correct tasks unblock at the correct + * times. */ + xError = prvSelectiveBitsTestMasterFunction(); + + for( ; ; ) + { + /* Recreate the event group ready for the next cycle. */ + xEventGroup = xEventGroupCreate(); + configASSERT( xEventGroup ); + + /* Perform the tests that check the behaviour when a single task is + * blocked on various combinations of event bits. */ + xError = prvBitCombinationTestMasterFunction( xError, xTestSlaveTaskHandle ); + + /* Perform the task synchronisation tests. */ + xError = prvPerformTaskSyncTests( xError, xTestSlaveTaskHandle ); + + /* Delete the event group. */ + vEventGroupDelete( xEventGroup ); + + /* Now all the other tasks should have completed and suspended + * themselves ready for the next go around the loop. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask1 ) != eSuspended ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask2 ) != eSuspended ) + { + xError = pdTRUE; + } + + /* Only increment the cycle variable if no errors have been detected. */ + if( xError == pdFALSE ) + { + ulTestMasterCycles++; + } + + configASSERT( xError == pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSyncTask( void * pvParameters ) +{ + EventBits_t uxSynchronisationBit, uxReturned; + + /* A few tests that check the behaviour when two tasks are blocked on + * various different bits within an event group are performed before this task + * enters its infinite loop to carry out its main demo function. */ + prvSelectiveBitsTestSlaveFunction(); + + /* The bit to use to indicate this task is at the synchronisation point is + * passed in as the task parameter. */ + uxSynchronisationBit = ( EventBits_t ) pvParameters; + + for( ; ; ) + { + /* Now this task takes part in a task synchronisation - sometimes known + * as a 'rendezvous'. Its execution pattern is controlled by the 'test + * master' task, which is responsible for taking this task out of the + * Suspended state when it is time to test the synchronisation behaviour. + * See: http://www.freertos.org/xEventGroupSync.html. */ + vTaskSuspend( NULL ); + + /* Set the bit that indicates this task is at the synchronisation + * point. The first time this is done the 'test master' task has a lower + * priority than this task so this task will get to the sync point before + * the set bits task - test this by calling xEventGroupSync() with a zero + * block time before calling again with a max delay - the first call should + * return before the rendezvous completes, the second only after the + * rendezvous is complete. */ + uxReturned = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */ + uxSynchronisationBit, /* The bit to set in the event group to indicate this task is at the sync point. */ + ebALL_SYNC_BITS, /* The bits to wait for - these bits are set by the other tasks taking part in the sync. */ + ebDONT_BLOCK ); /* The maximum time to wait for the sync condition to be met before giving up. */ + + /* No block time was specified, so as per the comments above, the + * rendezvous is not expected to have completed yet. */ + configASSERT( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS ); + + uxReturned = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */ + uxSynchronisationBit, /* The bit to set in the event group to indicate this task is at the sync point. */ + ebALL_SYNC_BITS, /* The bits to wait for - these bits are set by the other tasks taking part in the sync. */ + portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met before giving up. */ + + /* A max delay was used, so this task should only exit the above + * function call when the sync condition is met. Check this is the + * case. */ + configASSERT( ( uxReturned & ebALL_SYNC_BITS ) == ebALL_SYNC_BITS ); + + /* Remove compiler warning if configASSERT() is not defined. */ + ( void ) uxReturned; + + /* Wait until the 'test master' task unsuspends this task again. */ + vTaskSuspend( NULL ); + + /* Set the bit that indicates this task is at the synchronisation + * point again. This time the 'test master' task has a higher priority + * than this task so will get to the sync point before this task. */ + uxReturned = xEventGroupSync( xEventGroup, uxSynchronisationBit, ebALL_SYNC_BITS, portMAX_DELAY ); + + /* Again a max delay was used, so this task should only exit the above + * function call when the sync condition is met. Check this is the + * case. */ + configASSERT( ( uxReturned & ebALL_SYNC_BITS ) == ebALL_SYNC_BITS ); + + /* Block on the event group again. This time the event group is going + * to be deleted while this task is blocked on it so it is expected that 0 + * be returned. */ + uxReturned = xEventGroupWaitBits( xEventGroup, ebALL_SYNC_BITS, pdFALSE, pdTRUE, portMAX_DELAY ); + configASSERT( uxReturned == 0 ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTestSlaveTask( void * pvParameters ) +{ + EventBits_t uxReturned; + BaseType_t xError = pdFALSE; + + /* Avoid compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + /********************************************************************** + * Part 1: This section is the counterpart to the + * prvBitCombinationTestMasterFunction() function which is called by the + * test master task. + *********************************************************************** + * + * This task is controller by the 'test master' task (which is + * implemented by prvTestMasterTask()). Suspend until resumed by the + * 'test master' task. */ + vTaskSuspend( NULL ); + + /* Wait indefinitely for one of the bits in ebCOMBINED_BITS to get + * set. Clear the bit on exit. */ + uxReturned = xEventGroupWaitBits( xEventGroup, /* The event group that contains the event bits being queried. */ + ebBIT_1, /* The bit to wait for. */ + pdTRUE, /* Clear the bit on exit. */ + pdTRUE, /* Wait for all the bits (only one in this case anyway). */ + portMAX_DELAY ); /* Block indefinitely to wait for the condition to be met. */ + + /* The 'test master' task set all the bits defined by ebCOMBINED_BITS, + * only one of which was being waited for by this task. The return value + * shows the state of the event bits when the task was unblocked, however + * because the task was waiting for ebBIT_1 and 'clear on exit' was set to + * the current state of the event bits will have ebBIT_1 clear. */ + if( uxReturned != ebCOMBINED_BITS ) + { + xError = pdTRUE; + } + + /* Now call xEventGroupWaitBits() again, this time waiting for all the + * bits in ebCOMBINED_BITS to be set. This call should block until the + * 'test master' task sets ebBIT_1 - which was the bit cleared in the call + * to xEventGroupWaitBits() above. */ + uxReturned = xEventGroupWaitBits( xEventGroup, + ebCOMBINED_BITS, /* The bits being waited on. */ + pdFALSE, /* Don't clear the bits on exit. */ + pdTRUE, /* All the bits must be set to unblock. */ + portMAX_DELAY ); + + /* Were all the bits set? */ + if( ( uxReturned & ebCOMBINED_BITS ) != ebCOMBINED_BITS ) + { + xError = pdTRUE; + } + + /* Suspend again to wait for the 'test master' task. */ + vTaskSuspend( NULL ); + + /* Now call xEventGroupWaitBits() again, again waiting for all the bits + * in ebCOMBINED_BITS to be set, but this time clearing the bits when the + * task is unblocked. */ + uxReturned = xEventGroupWaitBits( xEventGroup, + ebCOMBINED_BITS, /* The bits being waited on. */ + pdTRUE, /* Clear the bits on exit. */ + pdTRUE, /* All the bits must be set to unblock. */ + portMAX_DELAY ); + + /* The 'test master' task set all the bits in the event group, so that + * is the value that should have been returned. The bits defined by + * ebCOMBINED_BITS will have been clear again in the current value though + * as 'clear on exit' was set to pdTRUE. */ + if( uxReturned != ebALL_BITS ) + { + xError = pdTRUE; + } + + /********************************************************************** + * Part 2: This section is the counterpart to the + * prvPerformTaskSyncTests() function which is called by the + * test master task. + *********************************************************************** + * + * + * Once again wait for the 'test master' task to unsuspend this task + * when it is time for the next test. */ + vTaskSuspend( NULL ); + + /* Now perform a synchronisation with all the other tasks. At this point + * the 'test master' task has the lowest priority so will get to the sync + * point after all the other synchronising tasks. */ + uxReturned = xEventGroupSync( xEventGroup, /* The event group used for the sync. */ + ebWAIT_BIT_TASK_SYNC_BIT, /* The bit in the event group used to indicate this task is at the sync point. */ + ebALL_SYNC_BITS, /* The bits to wait for. These bits are set by the other tasks taking part in the sync. */ + portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met before giving up. */ + + /* A sync with a max delay should only exit when all the synchronisation + * bits are set... */ + if( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS ) + { + xError = pdTRUE; + } + + /* ...but now the synchronisation bits should be clear again. Read back + * the current value of the bits within the event group to check that is + * the case. Setting the bits to zero will return the bits previous value + * then leave all the bits clear. */ + if( xEventGroupSetBits( xEventGroup, 0x00 ) != 0 ) + { + xError = pdTRUE; + } + + /* Check the bits are indeed 0 now by simply reading then. */ + if( xEventGroupGetBits( xEventGroup ) != 0 ) + { + xError = pdTRUE; + } + + if( xError == pdFALSE ) + { + /* This task is still cycling without finding an error. */ + ulTestSlaveCycles++; + } + + vTaskSuspend( NULL ); + + /* This time sync when the 'test master' task has the highest priority + * at the point where it sets its sync bit - so this time the 'test master' + * task will get to the sync point before this task. */ + uxReturned = xEventGroupSync( xEventGroup, ebWAIT_BIT_TASK_SYNC_BIT, ebALL_SYNC_BITS, portMAX_DELAY ); + + /* A sync with a max delay should only exit when all the synchronisation + * bits are set... */ + if( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS ) + { + xError = pdTRUE; + } + + /* ...but now the sync bits should be clear again. */ + if( xEventGroupSetBits( xEventGroup, 0x00 ) != 0 ) + { + xError = pdTRUE; + } + + /* Block on the event group again. This time the event group is going + * to be deleted while this task is blocked on it, so it is expected that 0 + * will be returned. */ + uxReturned = xEventGroupWaitBits( xEventGroup, ebALL_SYNC_BITS, pdFALSE, pdTRUE, portMAX_DELAY ); + + if( uxReturned != 0 ) + { + xError = pdTRUE; + } + + if( xError == pdFALSE ) + { + /* This task is still cycling without finding an error. */ + ulTestSlaveCycles++; + } + + configASSERT( xError == pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvPerformTaskSyncTests( BaseType_t xError, + TaskHandle_t xTestSlaveTaskHandle ) +{ + EventBits_t uxBits; + + /* The three tasks that take part in the synchronisation (rendezvous) are + * expected to be in the suspended state at the start of the test. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask1 ) != eSuspended ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask2 ) != eSuspended ) + { + xError = pdTRUE; + } + + /* Try a synch with no other tasks involved. First set all the bits other + * than this task's bit. */ + xEventGroupSetBits( xEventGroup, ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) ); + + /* Then wait on just one bit - the bit that is being set. */ + uxBits = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */ + ebSET_BIT_TASK_SYNC_BIT, /* The bit set by this task when it reaches the sync point. */ + ebSET_BIT_TASK_SYNC_BIT, /* The bits to wait for - in this case it is just waiting for itself. */ + portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met. */ + + /* A sync with a max delay should only exit when all the synchronise + * bits are set...check that is the case. In this case there is only one + * sync bit anyway. */ + if( ( uxBits & ebSET_BIT_TASK_SYNC_BIT ) != ebSET_BIT_TASK_SYNC_BIT ) + { + xError = pdTRUE; + } + + /* ...but now the sync bits should be clear again, leaving all the other + * bits set (as only one bit was being waited for). */ + if( xEventGroupGetBits( xEventGroup ) != ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) ) + { + xError = pdTRUE; + } + + /* Clear all the bits to zero again. */ + xEventGroupClearBits( xEventGroup, ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) ); + + if( xEventGroupGetBits( xEventGroup ) != 0 ) + { + xError = pdTRUE; + } + + /* Unsuspend the other tasks then check they have executed up to the + * synchronisation point. */ + vTaskResume( xTestSlaveTaskHandle ); + vTaskResume( xSyncTask1 ); + vTaskResume( xSyncTask2 ); + + if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask1 ) != eBlocked ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask2 ) != eBlocked ) + { + xError = pdTRUE; + } + + /* Set this task's sync bit. */ + uxBits = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */ + ebSET_BIT_TASK_SYNC_BIT, /* The bit set by this task when it reaches the sync point. */ + ebALL_SYNC_BITS, /* The bits to wait for - these bits are set by the other tasks that take part in the sync. */ + portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met. */ + + /* A sync with a max delay should only exit when all the synchronise + * bits are set...check that is the case. */ + if( ( uxBits & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS ) + { + xError = pdTRUE; + } + + /* ...but now the sync bits should be clear again. */ + if( xEventGroupGetBits( xEventGroup ) != 0 ) + { + xError = pdTRUE; + } + + /* The other tasks should now all be suspended again, ready for the next + * synchronisation. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask1 ) != eSuspended ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask2 ) != eSuspended ) + { + xError = pdTRUE; + } + + /* Sync again - but this time set the last necessary bit as the + * highest priority task, rather than the lowest priority task. Unsuspend + * the other tasks then check they have executed up to the synchronisation + * point. */ + vTaskResume( xTestSlaveTaskHandle ); + vTaskResume( xSyncTask1 ); + vTaskResume( xSyncTask2 ); + + if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask1 ) != eBlocked ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask2 ) != eBlocked ) + { + xError = pdTRUE; + } + + /* Raise the priority of this task above that of the other tasks. */ + vTaskPrioritySet( NULL, ebWAIT_BIT_TASK_PRIORITY + 1 ); + + /* Set this task's sync bit. */ + uxBits = xEventGroupSync( xEventGroup, ebSET_BIT_TASK_SYNC_BIT, ebALL_SYNC_BITS, portMAX_DELAY ); + + /* A sync with a max delay should only exit when all the synchronisation + * bits are set... */ + if( ( uxBits & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS ) + { + xError = pdTRUE; + } + + /* ...but now the sync bits should be clear again. */ + if( xEventGroupGetBits( xEventGroup ) != 0 ) + { + xError = pdTRUE; + } + + /* The other tasks should now all be in the ready state again, but not + * executed yet as this task still has a higher relative priority. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eReady ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask1 ) != eReady ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask2 ) != eReady ) + { + xError = pdTRUE; + } + + /* Reset the priority of this task back to its original value. */ + vTaskPrioritySet( NULL, ebSET_BIT_TASK_PRIORITY ); + + /* Now all the other tasks should have reblocked on the event bits + * to test the behaviour when the event bits are deleted. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask1 ) != eBlocked ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask2 ) != eBlocked ) + { + xError = pdTRUE; + } + + return xError; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvBitCombinationTestMasterFunction( BaseType_t xError, + TaskHandle_t xTestSlaveTaskHandle ) +{ + EventBits_t uxBits; + + /* Resume the other task. It will block, pending a single bit from + * within ebCOMBINED_BITS. */ + vTaskResume( xTestSlaveTaskHandle ); + + /* Ensure the other task is blocked on the task. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked ) + { + xError = pdTRUE; + } + + /* Set all the bits in ebCOMBINED_BITS - the 'test slave' task is only + * blocked waiting for one of them. */ + xEventGroupSetBits( xEventGroup, ebCOMBINED_BITS ); + + /* The 'test slave' task should now have executed, clearing ebBIT_1 (the + * bit it was blocked on), then re-entered the Blocked state to wait for + * all the other bits in ebCOMBINED_BITS to be set again. First check + * ebBIT_1 is clear. */ + uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK ); + + if( uxBits != ( ebCOMBINED_BITS & ~ebBIT_1 ) ) + { + xError = pdTRUE; + } + + /* Ensure the other task is still in the blocked state. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked ) + { + xError = pdTRUE; + } + + /* Set all the bits other than ebBIT_1 - which is the bit that must be + * set before the other task unblocks. */ + xEventGroupSetBits( xEventGroup, ebALL_BITS & ~ebBIT_1 ); + + /* Ensure all the expected bits are still set. */ + uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK ); + + if( uxBits != ( ebALL_BITS & ~ebBIT_1 ) ) + { + xError = pdTRUE; + } + + /* Ensure the other task is still in the blocked state. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked ) + { + xError = pdTRUE; + } + + /* Now also set ebBIT_1, which should unblock the other task, which will + * then suspend itself. */ + xEventGroupSetBits( xEventGroup, ebBIT_1 ); + + /* Ensure the other task is suspended. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended ) + { + xError = pdTRUE; + } + + /* The other task should not have cleared the bits - so all the bits + * should still be set. */ + if( xEventGroupSetBits( xEventGroup, 0x00 ) != ebALL_BITS ) + { + xError = pdTRUE; + } + + /* Clear ebBIT_1 again. */ + if( xEventGroupClearBits( xEventGroup, ebBIT_1 ) != ebALL_BITS ) + { + xError = pdTRUE; + } + + /* Resume the other task - which will wait on all the ebCOMBINED_BITS + * again - this time clearing the bits when it is unblocked. */ + vTaskResume( xTestSlaveTaskHandle ); + + /* Ensure the other task is blocked once again. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked ) + { + xError = pdTRUE; + } + + /* Set the bit the other task is waiting for. */ + xEventGroupSetBits( xEventGroup, ebBIT_1 ); + + /* Ensure the other task is suspended once again. */ + if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended ) + { + xError = pdTRUE; + } + + /* The other task should have cleared the bits in ebCOMBINED_BITS. + * Clear the remaining bits. */ + uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK ); + + if( uxBits != ( ebALL_BITS & ~ebCOMBINED_BITS ) ) + { + xError = pdTRUE; + } + + /* Clear all bits ready for the sync with the other three tasks. The + * value returned is the value prior to the bits being cleared. */ + if( xEventGroupClearBits( xEventGroup, ebALL_BITS ) != ( ebALL_BITS & ~ebCOMBINED_BITS ) ) + { + xError = pdTRUE; + } + + /* The bits should be clear now. */ + if( xEventGroupGetBits( xEventGroup ) != 0x00 ) + { + xError = pdTRUE; + } + + return xError; +} +/*-----------------------------------------------------------*/ + +static void prvSelectiveBitsTestSlaveFunction( void ) +{ + EventBits_t uxPendBits, uxReturned; + + /* Used in a test that blocks two tasks on various different bits within an + * event group - then sets each bit in turn and checks that the correct tasks + * unblock at the correct times. + * + * This function is called by two different tasks - each of which will use a + * different bit. Check the task handle to see which task the function was + * called by. */ + if( xTaskGetCurrentTaskHandle() == xSyncTask1 ) + { + uxPendBits = ebSELECTIVE_BITS_1; + } + else + { + uxPendBits = ebSELECTIVE_BITS_2; + } + + for( ; ; ) + { + /* Wait until it is time to perform the next cycle of the test. The + * task is unsuspended by the tests implemented in the + * prvSelectiveBitsTestMasterFunction() function. */ + vTaskSuspend( NULL ); + uxReturned = xEventGroupWaitBits( xEventGroup, uxPendBits, pdTRUE, pdFALSE, portMAX_DELAY ); + + if( uxReturned == ( EventBits_t ) 0 ) + { + break; + } + } +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvSelectiveBitsTestMasterFunction( void ) +{ + BaseType_t xError = pdFALSE; + EventBits_t uxBit; + + /* Used in a test that blocks two tasks on various different bits within an + * event group - then sets each bit in turn and checks that the correct tasks + * unblock at the correct times. The two other tasks (xSyncTask1 and + * xSyncTask2) call prvSelectiveBitsTestSlaveFunction() to perform their parts in + * this test. + * + * Both other tasks should start in the suspended state. */ + if( eTaskGetState( xSyncTask1 ) != eSuspended ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask2 ) != eSuspended ) + { + xError = pdTRUE; + } + + /* Test each bit in the byte individually. */ + for( uxBit = 0x01; uxBit < 0x100; uxBit <<= 1 ) + { + /* Resume both tasks. */ + vTaskResume( xSyncTask1 ); + vTaskResume( xSyncTask2 ); + + /* Now both tasks should be blocked on the event group. */ + if( eTaskGetState( xSyncTask1 ) != eBlocked ) + { + xError = pdTRUE; + } + + if( eTaskGetState( xSyncTask2 ) != eBlocked ) + { + xError = pdTRUE; + } + + /* Set one bit. */ + xEventGroupSetBits( xEventGroup, uxBit ); + + /* Is the bit set in the first set of selective bits? If so the first + * sync task should have unblocked and returned to the suspended state. */ + if( ( uxBit & ebSELECTIVE_BITS_1 ) == 0 ) + { + /* Task should not have unblocked. */ + if( eTaskGetState( xSyncTask1 ) != eBlocked ) + { + xError = pdTRUE; + } + } + else + { + /* Task should have unblocked and returned to the suspended state. */ + if( eTaskGetState( xSyncTask1 ) != eSuspended ) + { + xError = pdTRUE; + } + } + + /* Same checks for the second sync task. */ + if( ( uxBit & ebSELECTIVE_BITS_2 ) == 0 ) + { + /* Task should not have unblocked. */ + if( eTaskGetState( xSyncTask2 ) != eBlocked ) + { + xError = pdTRUE; + } + } + else + { + /* Task should have unblocked and returned to the suspended state. */ + if( eTaskGetState( xSyncTask2 ) != eSuspended ) + { + xError = pdTRUE; + } + } + } + + /* Ensure both tasks are blocked on the event group again, then delete the + * event group so the other tasks leave this portion of the test. */ + vTaskResume( xSyncTask1 ); + vTaskResume( xSyncTask2 ); + + /* Deleting the event group is the signal that the two other tasks should + * leave the prvSelectiveBitsTestSlaveFunction() function and continue to the main + * part of their functionality. */ + vEventGroupDelete( xEventGroup ); + + return xError; +} +/*-----------------------------------------------------------*/ + +void vPeriodicEventGroupsProcessing( void ) +{ + static BaseType_t xCallCount = 0, xISRTestError = pdFALSE; + const BaseType_t xSetBitCount = 100, xGetBitsCount = 200, xClearBitsCount = 300; + const EventBits_t uxBitsToSet = 0x12U; + EventBits_t uxReturned; + BaseType_t xMessagePosted; + + /* Called periodically from the tick hook to exercise the "FromISR" + * functions. */ + + /* Check the even group tasks were actually created. */ + configASSERT( xISREventGroup ); + + xCallCount++; + + if( xCallCount == xSetBitCount ) + { + /* All the event bits should start clear. */ + uxReturned = xEventGroupGetBitsFromISR( xISREventGroup ); + + if( uxReturned != 0x00 ) + { + xISRTestError = pdTRUE; + } + else + { + /* Set the bits. This is called from the tick hook so it is not + * necessary to use the last parameter to ensure a context switch + * occurs immediately. */ + xMessagePosted = xEventGroupSetBitsFromISR( xISREventGroup, uxBitsToSet, NULL ); + + if( xMessagePosted != pdPASS ) + { + xISRTestError = pdTRUE; + } + } + } + else if( xCallCount == xGetBitsCount ) + { + /* Check the bits were set as expected. */ + uxReturned = xEventGroupGetBitsFromISR( xISREventGroup ); + + if( uxReturned != uxBitsToSet ) + { + xISRTestError = pdTRUE; + } + } + else if( xCallCount == xClearBitsCount ) + { + /* Clear the bits again. */ + uxReturned = ( EventBits_t ) xEventGroupClearBitsFromISR( xISREventGroup, uxBitsToSet ); + + /* Check the message was posted. */ + if( uxReturned != pdPASS ) + { + xISRTestError = pdTRUE; + } + + /* Go back to the start. */ + xCallCount = 0; + + /* If no errors have been detected then increment the count of test + * cycles. */ + if( xISRTestError == pdFALSE ) + { + ulISRCycles++; + } + } + else + { + /* Nothing else to do. */ + } +} + +/*-----------------------------------------------------------*/ +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreEventGroupTasksStillRunning( void ) +{ + static uint32_t ulPreviousWaitBitCycles = 0, ulPreviousSetBitCycles = 0, ulPreviousISRCycles = 0; + BaseType_t xStatus = pdPASS; + + /* Check the tasks are still cycling without finding any errors. */ + if( ulPreviousSetBitCycles == ulTestMasterCycles ) + { + xStatus = pdFAIL; + } + + ulPreviousSetBitCycles = ulTestMasterCycles; + + if( ulPreviousWaitBitCycles == ulTestSlaveCycles ) + { + xStatus = pdFAIL; + } + + ulPreviousWaitBitCycles = ulTestSlaveCycles; + + if( ulPreviousISRCycles == ulISRCycles ) + { + xStatus = pdFAIL; + } + + ulPreviousISRCycles = ulISRCycles; + + return xStatus; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/GenQTest.c b/SOFTWARE-FreeRTOS/Common/Minimal/GenQTest.c new file mode 100644 index 0000000..aac016f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/GenQTest.c @@ -0,0 +1,1039 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Tests the extra queue functionality introduced in FreeRTOS.org V4.5.0 - + * including xQueueSendToFront(), xQueueSendToBack(), xQueuePeek() and + * mutex behaviour. + * + * See the comments above the prvSendFrontAndBackTest() and + * prvLowPriorityMutexTask() prototypes below for more information. + */ + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "GenQTest.h" + +#define genqQUEUE_LENGTH ( 5 ) +#define intsemNO_BLOCK ( 0 ) +#define genqSHORT_BLOCK ( pdMS_TO_TICKS( 2 ) ) + +#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY ) +#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +#ifndef genqMUTEX_TEST_TASK_STACK_SIZE + #define genqMUTEX_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE +#endif + +#ifndef genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE + #define genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE +#endif +/*-----------------------------------------------------------*/ + +/* + * Tests the behaviour of the xQueueSendToFront() and xQueueSendToBack() + * macros by using both to fill a queue, then reading from the queue to + * check the resultant queue order is as expected. Queue data is also + * peeked. + */ +static void prvSendFrontAndBackTest( void * pvParameters ); + +/* + * The following three tasks are used to demonstrate the mutex behaviour. + * Each task is given a different priority to demonstrate the priority + * inheritance mechanism. + * + * The low priority task obtains a mutex. After this a high priority task + * attempts to obtain the same mutex, causing its priority to be inherited + * by the low priority task. The task with the inherited high priority then + * resumes a medium priority task to ensure it is not blocked by the medium + * priority task while it holds the inherited high priority. Once the mutex + * is returned the task with the inherited priority returns to its original + * low priority, and is therefore immediately preempted by first the high + * priority task and then the medium priority task before it can continue. + */ +static void prvLowPriorityMutexTask( void * pvParameters ); +static void prvMediumPriorityMutexTask( void * pvParameters ); +static void prvHighPriorityMutexTask( void * pvParameters ); + +/* + * Tests the behaviour when a low priority task inherits the priority of a + * higher priority task when taking two mutexes, and returns the mutexes in + * first the same order as the two mutexes were obtained, and second the + * opposite order as the two mutexes were obtained. + */ +static void prvTakeTwoMutexesReturnInSameOrder( SemaphoreHandle_t xMutex, + SemaphoreHandle_t xLocalMutex ); +static void prvTakeTwoMutexesReturnInDifferentOrder( SemaphoreHandle_t xMutex, + SemaphoreHandle_t xLocalMutex ); + +#if ( INCLUDE_xTaskAbortDelay == 1 ) + + #if ( configUSE_PREEMPTION == 0 ) + #error The additional tests included when INCLUDE_xTaskAbortDelay is 1 expect preemption to be used. + #endif + +/* Tests the behaviour when a low priority task inherits the priority of a + * high priority task only for the high priority task to timeout before + * obtaining the mutex. */ + static void prvHighPriorityTimeout( SemaphoreHandle_t xMutex ); +#endif + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be + * detected in any of the tasks. */ +static volatile BaseType_t xErrorDetected = pdFALSE; + +/* Counters that are incremented on each cycle of a test. This is used to + * detect a stalled task - a test that is no longer running. */ +static volatile uint32_t ulLoopCounter = 0; +static volatile uint32_t ulLoopCounter2 = 0; + +/* The variable that is guarded by the mutex in the mutex demo tasks. */ +static volatile uint32_t ulGuardedVariable = 0; + +/* Handles used in the mutex test to suspend and resume the high and medium + * priority mutex test tasks. */ +static TaskHandle_t xHighPriorityMutexTask, xMediumPriorityMutexTask; + +/* If INCLUDE_xTaskAbortDelay is 1 additional tests are performed, requiring an + * additional task. */ +#if ( INCLUDE_xTaskAbortDelay == 1 ) + static TaskHandle_t xSecondMediumPriorityMutexTask; +#endif + +/* Lets the high priority semaphore task know that its wait for the semaphore + * was aborted, in which case not being able to obtain the semaphore is not to be + * considered an error. */ +static volatile BaseType_t xBlockWasAborted = pdFALSE; + +/*-----------------------------------------------------------*/ + +void vStartGenericQueueTasks( UBaseType_t uxPriority ) +{ + QueueHandle_t xQueue; + SemaphoreHandle_t xMutex; + + /* Create the queue that we are going to use for the + * prvSendFrontAndBackTest demo. */ + xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* vQueueAddToRegistry() adds the queue to the queue registry, if one + * is in use. The queue registry is provided as a means for kernel aware + * debuggers to locate queues and has no purpose if a kernel aware debugger + * is not being used. The call to vQueueAddToRegistry() will be removed + * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + * defined to be less than 1. */ + vQueueAddToRegistry( xQueue, "Gen_Queue_Test" ); + + /* Create the demo task and pass it the queue just created. We are + * passing the queue handle by value so it does not matter that it is + * declared on the stack here. */ + xTaskCreate( prvSendFrontAndBackTest, "GenQ", genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL ); + } + + /* Create the mutex used by the prvMutexTest task. */ + xMutex = xSemaphoreCreateMutex(); + + if( xMutex != NULL ) + { + /* vQueueAddToRegistry() adds the mutex to the registry, if one is + * in use. The registry is provided as a means for kernel aware + * debuggers to locate mutexes and has no purpose if a kernel aware + * debugger is not being used. The call to vQueueAddToRegistry() will be + * removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not + * defined or is defined to be less than 1. */ + vQueueAddToRegistry( ( QueueHandle_t ) xMutex, "Gen_Queue_Mutex" ); + + /* Create the mutex demo tasks and pass it the mutex just created. We + * are passing the mutex handle by value so it does not matter that it is + * declared on the stack here. */ + xTaskCreate( prvLowPriorityMutexTask, "MuLow", genqMUTEX_TEST_TASK_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL ); + xTaskCreate( prvMediumPriorityMutexTask, "MuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask ); + xTaskCreate( prvHighPriorityMutexTask, "MuHigh", genqMUTEX_TEST_TASK_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask ); + + /* If INCLUDE_xTaskAbortDelay is set then additional tests are performed, + * requiring two instances of prvHighPriorityMutexTask(). */ + #if ( INCLUDE_xTaskAbortDelay == 1 ) + { + xTaskCreate( prvHighPriorityMutexTask, "MuHigh2", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_MEDIUM_PRIORITY, &xSecondMediumPriorityMutexTask ); + } + #endif /* INCLUDE_xTaskAbortDelay */ + } +} +/*-----------------------------------------------------------*/ + +static void prvSendFrontAndBackTest( void * pvParameters ) +{ + uint32_t ulData, ulData2, ulLoopCounterSnapshot; + QueueHandle_t xQueue; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const char * const * ppcMessageToSend ); + + const char * const pcTaskStartMsg = "Queue SendToFront/SendToBack/Peek test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + xQueue = ( QueueHandle_t ) pvParameters; + + for( ; ; ) + { + /* The queue is empty, so sending an item to the back of the queue + * should have the same effect as sending it to the front of the queue. + * + * First send to the front and check everything is as expected. */ + ulLoopCounterSnapshot = ulLoopCounter; + xQueueSendToFront( xQueue, ( void * ) &ulLoopCounterSnapshot, intsemNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueReceive( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* The data we sent to the queue should equal the data we just received + * from the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + /* Then do the same, sending the data to the back, checking everything + * is as expected. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + ulLoopCounterSnapshot = ulLoopCounter; + xQueueSendToBack( xQueue, ( void * ) &ulLoopCounterSnapshot, intsemNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueReceive( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* The data sent to the queue should equal the data just received from + * the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Place 2, 3, 4 into the queue, adding items to the back of the queue. */ + for( ulData = 2; ulData < 5; ulData++ ) + { + xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK ); + } + + /* Now the order in the queue should be 2, 3, 4, with 2 being the first + * thing to be read out. Now add 1 then 0 to the front of the queue. */ + if( uxQueueMessagesWaiting( xQueue ) != 3 ) + { + xErrorDetected = pdTRUE; + } + + ulData = 1; + xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ); + ulData = 0; + xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ); + + /* Now the queue should be full, and when we read the data out we + * should receive 0, 1, 2, 3, 4. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ ) + { + /* Try peeking the data first. */ + if( xQueuePeek( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + + /* Now try receiving the data for real. The value should be the + * same. Clobber the value first so we know we really received it. */ + ulData2 = ~ulData2; + + if( xQueueReceive( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + /* The queue should now be empty again. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + /* Our queue is empty once more, add 10, 11 to the back. */ + ulData = 10; + + if( xQueueSend( xQueue, &ulData, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + ulData = 11; + + if( xQueueSend( xQueue, &ulData, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 2 ) + { + xErrorDetected = pdTRUE; + } + + /* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the + * front. */ + for( ulData = 9; ulData >= 7; ulData-- ) + { + if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } + + /* Now check that the queue is full, and that receiving data provides + * the expected sequence of 7, 8, 9, 10, 11. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ ) + { + if( xQueueReceive( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* Increment the loop counter to indicate these tasks are still + * executing. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskAbortDelay == 1 ) + + static void prvHighPriorityTimeout( SemaphoreHandle_t xMutex ) + { + static UBaseType_t uxLoopCount = 0; + + /* The tests in this function are very similar, the slight variations + * are for code coverage purposes. */ + + /* Take the mutex. It should be available now. Check before and after + * taking that the holder is reported correctly. */ + if( xSemaphoreGetMutexHolder( xMutex ) != NULL ) + { + xErrorDetected = pdTRUE; + } + + if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( xSemaphoreGetMutexHolder( xMutex ) != xTaskGetCurrentTaskHandle() ) + { + xErrorDetected = pdTRUE; + } + + /* This task's priority should be as per that assigned when the task was + * created. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the high priority task. This will attempt to take the + * mutex, and block when it finds it cannot obtain it. */ + vTaskResume( xHighPriorityMutexTask ); + + /* This task should now have inherited the priority of the high priority + * task as by now the high priority task will have attempted to obtain the + * mutex. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Unblock a second medium priority task. It too will attempt to take + * the mutex and enter the Blocked state - it won't run yet though as this + * task has inherited a priority above it. */ + vTaskResume( xSecondMediumPriorityMutexTask ); + + /* This task should still have the priority of the high priority task as + * that had already been inherited as is the highest priority of the three + * tasks using the mutex. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* On some loops, block for a short while to provide additional + * code coverage. Blocking here will allow the medium priority task to + * execute and so also block on the mutex so when the high priority task + * causes this task to disinherit the high priority it is inherited down to + * the priority of the medium priority task. When there is no delay the + * medium priority task will not run until after the disinheritance, so + * this task will disinherit back to its base priority, then only up to the + * medium priority after the medium priority has executed. */ + vTaskDelay( uxLoopCount & ( UBaseType_t ) 0x07 ); + + /* Now force the high priority task to unblock. It will fail to obtain + * the mutex and go back to the suspended state - allowing this task to + * execute again. xBlockWasAborted is set to pdTRUE so the higher priority + * task knows that its failure to obtain the semaphore is not an error. */ + xBlockWasAborted = pdTRUE; + + if( xTaskAbortDelay( xHighPriorityMutexTask ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* This task has inherited the priority of xHighPriorityMutexTask so + * could still be running even though xHighPriorityMutexTask is no longer + * blocked. Delay for a short while to ensure xHighPriorityMutexTask gets + * a chance to run - indicated by this task changing priority. It should + * disinherit the high priority task, but then inherit the priority of the + * medium priority task that is waiting for the same mutex. */ + while( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY ) + { + /* If this task gets stuck here then the check variables will stop + * incrementing and the check task will detect the error. */ + vTaskDelay( genqSHORT_BLOCK ); + } + + /* Now force the medium priority task to unblock. xBlockWasAborted is + * set to pdTRUE so the medium priority task knows that its failure to + * obtain the semaphore is not an error. */ + xBlockWasAborted = pdTRUE; + + if( xTaskAbortDelay( xSecondMediumPriorityMutexTask ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* This time no other tasks are waiting for the mutex, so this task + * should return to its base priority. This might not happen straight + * away as it is running at the same priority as the task it just + * unblocked. */ + while( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + /* If this task gets stuck here then the check variables will stop + * incrementing and the check task will detect the error. */ + vTaskDelay( genqSHORT_BLOCK ); + } + + /* Give the semaphore back ready for the next test. Check the mutex + * holder before and after using the "FromISR" version for code coverage. */ + if( xSemaphoreGetMutexHolderFromISR( xMutex ) != xTaskGetCurrentTaskHandle() ) + { + xErrorDetected = pdTRUE; + } + + xSemaphoreGive( xMutex ); + + if( xSemaphoreGetMutexHolderFromISR( xMutex ) != NULL ) + { + xErrorDetected = pdTRUE; + } + + configASSERT( xErrorDetected == pdFALSE ); + + /* Now do the same again, but this time unsuspend the tasks in the + * opposite order. This takes a different path though the code because + * when the high priority task has its block aborted there is already + * another task in the list of tasks waiting for the mutex, and the + * low priority task drops down to that priority, rather than dropping + * down to its base priority before inheriting the priority of the medium + * priority task. */ + if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* This time unsuspend the medium priority task first. This will + * attempt to take the mutex, and block when it finds it cannot obtain it. */ + vTaskResume( xSecondMediumPriorityMutexTask ); + + /* This time this task should now have inherited the priority of the + * medium task. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* This time the high priority task in unsuspended second. */ + vTaskResume( xHighPriorityMutexTask ); + + /* The high priority task should already have run, causing this task to + * inherit a priority for the second time. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* This time, when the high priority task has its delay aborted and it + * fails to obtain the mutex this task will immediately have its priority + * lowered down to that of the highest priority task waiting on the mutex, + * which is the medium priority task. */ + xBlockWasAborted = pdTRUE; + + if( xTaskAbortDelay( xHighPriorityMutexTask ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + while( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY ) + { + /* If this task gets stuck here then the check variables will stop + * incrementing and the check task will detect the error. */ + vTaskDelay( genqSHORT_BLOCK ); + } + + /* And finally, when the medium priority task also have its delay + * aborted there are no other tasks waiting for the mutex so this task + * returns to its base priority. */ + xBlockWasAborted = pdTRUE; + + if( xTaskAbortDelay( xSecondMediumPriorityMutexTask ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + while( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + /* If this task gets stuck here then the check variables will stop + * incrementing and the check task will detect the error. */ + vTaskDelay( genqSHORT_BLOCK ); + } + + /* Give the semaphore back ready for the next test. */ + xSemaphoreGive( xMutex ); + + configASSERT( xErrorDetected == pdFALSE ); + + /* uxLoopCount is used to add a variable delay, and in-so-doing provide + * additional code coverage. */ + uxLoopCount++; + } + +#endif /* INCLUDE_xTaskAbortDelay == 1 */ +/*-----------------------------------------------------------*/ + +static void prvTakeTwoMutexesReturnInDifferentOrder( SemaphoreHandle_t xMutex, + SemaphoreHandle_t xLocalMutex ) +{ + /* Take the mutex. It should be available now. */ + if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* Set the guarded variable to a known start value. */ + ulGuardedVariable = 0; + + /* This task's priority should be as per that assigned when the task was + * created. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the high priority task. This will attempt to take the + * mutex, and block when it finds it cannot obtain it. */ + vTaskResume( xHighPriorityMutexTask ); + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Ensure the task is reporting its priority as blocked and not + * suspended (as it would have done in versions up to V7.5.3). */ + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xHighPriorityMutexTask ) == eBlocked ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* This task should now have inherited the priority of the high priority + * task as by now the high priority task will have attempted to obtain the + * mutex. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Attempt to set the priority of this task to the test priority - + * between the idle priority and the medium/high test priorities, but the + * actual priority should remain at the high priority. */ + vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY ); + + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the medium priority task. This should not run as the + * inherited priority of this task is above that of the medium priority + * task. */ + vTaskResume( xMediumPriorityMutexTask ); + + /* If the medium priority task did run then it will have incremented the + * guarded variable. */ + if( ulGuardedVariable != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* Take the local mutex too, so two mutexes are now held. */ + if( xSemaphoreTake( xLocalMutex, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* When the semaphore is given back the priority of this task should not + * yet be disinherited because the local mutex is still held. This is a + * simplification to allow FreeRTOS to be integrated with middleware that + * attempts to hold multiple mutexes without bloating the code with complex + * algorithms. It is possible that the high priority mutex task will + * execute as it shares a priority with this task. */ + if( xSemaphoreGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* The guarded variable is only incremented by the medium priority task, + * which still should not have executed as this task should remain at the + * higher priority, ensure this is the case. */ + if( ulGuardedVariable != 0 ) + { + xErrorDetected = pdTRUE; + } + + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now also give back the local mutex, taking the held count back to 0. + * This time the priority of this task should be disinherited back to the + * priority to which it was set while the mutex was held. This means + * the medium priority task should execute and increment the guarded + * variable. When this task next runs both the high and medium priority + * tasks will have been suspended again. */ + if( xSemaphoreGive( xLocalMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the guarded variable did indeed increment... */ + if( ulGuardedVariable != 1 ) + { + xErrorDetected = pdTRUE; + } + + /* ... and that the priority of this task has been disinherited to + * genqMUTEX_TEST_PRIORITY. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Set the priority of this task back to its original value, ready for + * the next loop around this test. */ + vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +static void prvTakeTwoMutexesReturnInSameOrder( SemaphoreHandle_t xMutex, + SemaphoreHandle_t xLocalMutex ) +{ + /* Take the mutex. It should be available now. */ + if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* Set the guarded variable to a known start value. */ + ulGuardedVariable = 0; + + /* This task's priority should be as per that assigned when the task was + * created. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the high priority task. This will attempt to take the + * mutex, and block when it finds it cannot obtain it. */ + vTaskResume( xHighPriorityMutexTask ); + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Ensure the task is reporting its priority as blocked and not + * suspended (as it would have done in versions up to V7.5.3). */ + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xHighPriorityMutexTask ) == eBlocked ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* This task should now have inherited the priority of the high priority + * task as by now the high priority task will have attempted to obtain the + * mutex. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the medium priority task. This should not run as the + * inherited priority of this task is above that of the medium priority + * task. */ + vTaskResume( xMediumPriorityMutexTask ); + + /* If the medium priority task did run then it will have incremented the + * guarded variable. */ + if( ulGuardedVariable != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* Take the local mutex too, so two mutexes are now held. */ + if( xSemaphoreTake( xLocalMutex, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* When the local semaphore is given back the priority of this task should + * not yet be disinherited because the shared mutex is still held. This is a + * simplification to allow FreeRTOS to be integrated with middleware that + * attempts to hold multiple mutexes without bloating the code with complex + * algorithms. It is possible that the high priority mutex task will + * execute as it shares a priority with this task. */ + if( xSemaphoreGive( xLocalMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* The guarded variable is only incremented by the medium priority task, + * which still should not have executed as this task should remain at the + * higher priority, ensure this is the case. */ + if( ulGuardedVariable != 0 ) + { + xErrorDetected = pdTRUE; + } + + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now also give back the shared mutex, taking the held count back to 0. + * This time the priority of this task should be disinherited back to the + * priority at which it was created. This means the medium priority task + * should execute and increment the guarded variable. When this task next runs + * both the high and medium priority tasks will have been suspended again. */ + if( xSemaphoreGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the guarded variable did indeed increment... */ + if( ulGuardedVariable != 1 ) + { + xErrorDetected = pdTRUE; + } + + /* ... and that the priority of this task has been disinherited to + * genqMUTEX_LOW_PRIORITY. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + xErrorDetected = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +static void prvLowPriorityMutexTask( void * pvParameters ) +{ + SemaphoreHandle_t xMutex = ( SemaphoreHandle_t ) pvParameters, xLocalMutex; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const char * const * ppcMessageToSend ); + + const char * const pcTaskStartMsg = "Mutex with priority inheritance test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + /* The local mutex is used to check the 'mutex held' count. */ + xLocalMutex = xSemaphoreCreateMutex(); + configASSERT( xLocalMutex ); + + for( ; ; ) + { + /* The first tests exercise the priority inheritance when two mutexes + * are taken then returned in a different order to which they were + * taken. */ + prvTakeTwoMutexesReturnInDifferentOrder( xMutex, xLocalMutex ); + + /* Just to show this task is still running. */ + ulLoopCounter2++; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* The second tests exercise the priority inheritance when two mutexes + * are taken then returned in the same order in which they were taken. */ + prvTakeTwoMutexesReturnInSameOrder( xMutex, xLocalMutex ); + + /* Just to show this task is still running. */ + ulLoopCounter2++; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + { + /* Tests the behaviour when a low priority task inherits the + * priority of a high priority task only for the high priority task to + * timeout before obtaining the mutex. */ + prvHighPriorityTimeout( xMutex ); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +static void prvMediumPriorityMutexTask( void * pvParameters ) +{ + ( void ) pvParameters; + + for( ; ; ) + { + /* The medium priority task starts by suspending itself. The low + * priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is increment the guarded + * variable, this is so the low priority task knows that it has + * executed. */ + ulGuardedVariable++; + } +} +/*-----------------------------------------------------------*/ + +static void prvHighPriorityMutexTask( void * pvParameters ) +{ + SemaphoreHandle_t xMutex = ( SemaphoreHandle_t ) pvParameters; + + for( ; ; ) + { + /* The high priority task starts by suspending itself. The low + * priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is attempt to obtain the + * mutex. It should find the mutex is not available so a block time is + * specified. */ + if( xSemaphoreTake( xMutex, portMAX_DELAY ) != pdPASS ) + { + /* This task would expect to obtain the mutex unless its wait for + * the mutex was aborted. */ + if( xBlockWasAborted == pdFALSE ) + { + xErrorDetected = pdTRUE; + } + else + { + xBlockWasAborted = pdFALSE; + } + } + else + { + /* When the mutex is eventually obtained it is just given back before + * returning to suspend ready for the next cycle. */ + if( xSemaphoreGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } + } +} +/*-----------------------------------------------------------*/ + + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreGenericQueueTasksStillRunning( void ) +{ + static uint32_t ulLastLoopCounter = 0, ulLastLoopCounter2 = 0; + + /* If the demo task is still running then we expect the loop counters to + * have incremented since this function was last called. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xErrorDetected = pdTRUE; + } + + if( ulLastLoopCounter2 == ulLoopCounter2 ) + { + xErrorDetected = pdTRUE; + } + + ulLastLoopCounter = ulLoopCounter; + ulLastLoopCounter2 = ulLoopCounter2; + + /* Errors detected in the task itself will have latched xErrorDetected + * to true. */ + + return ( BaseType_t ) !xErrorDetected; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/IntQueue.c b/SOFTWARE-FreeRTOS/Common/Minimal/IntQueue.c new file mode 100644 index 0000000..990427c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/IntQueue.c @@ -0,0 +1,741 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This file defines one of the more complex set of demo/test tasks. They are + * designed to stress test the queue implementation though pseudo simultaneous + * multiple reads and multiple writes from both tasks of varying priority and + * interrupts. The interrupts are prioritised such to ensure that nesting + * occurs (for those ports that support it). + * + * The test ensures that, while being accessed from three tasks and two + * interrupts, all the data sent to the queues is also received from + * the same queue, and that no duplicate items are either sent or received. + * The tests also ensure that a low priority task is never able to successfully + * read from or write to a queue when a task of higher priority is attempting + * the same operation. + */ + +/* Standard includes. */ +#include + +/* SafeRTOS includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo app includes. */ +#include "IntQueue.h" +#include "IntQueueTimer.h" + +#if ( INCLUDE_eTaskGetState != 1 ) + #error INCLUDE_eTaskGetState must be set to 1 in FreeRTOSConfig.h to use this demo file. +#endif + +/* Priorities used by test tasks. */ +#ifndef intqHIGHER_PRIORITY + #define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 2 ) +#endif +#define intqLOWER_PRIORITY ( tskIDLE_PRIORITY ) + +/* The number of values to send/receive before checking that all values were + * processed as expected. */ +#define intqNUM_VALUES_TO_LOG ( 200 ) +#define intqSHORT_DELAY ( 140 ) + +/* The value by which the value being sent to or received from a queue should + * increment past intqNUM_VALUES_TO_LOG before we check that all values have been + * sent/received correctly. This is done to ensure that all tasks and interrupts + * accessing the queue have completed their accesses with the + * intqNUM_VALUES_TO_LOG range. */ +#define intqVALUE_OVERRUN ( 50 ) + +/* The delay used by the polling task. A short delay is used for code + * coverage. */ +#define intqONE_TICK_DELAY ( 1 ) + +/* Each task and interrupt is given a unique identifier. This value is used to + * identify which task sent or received each value. The identifier is also used + * to distinguish between two tasks that are running the same task function. */ +#define intqHIGH_PRIORITY_TASK1 ( ( UBaseType_t ) 1 ) +#define intqHIGH_PRIORITY_TASK2 ( ( UBaseType_t ) 2 ) +#define intqLOW_PRIORITY_TASK ( ( UBaseType_t ) 3 ) +#define intqFIRST_INTERRUPT ( ( UBaseType_t ) 4 ) +#define intqSECOND_INTERRUPT ( ( UBaseType_t ) 5 ) +#define intqQUEUE_LENGTH ( ( UBaseType_t ) 10 ) + +/* At least intqMIN_ACCEPTABLE_TASK_COUNT values should be sent to/received + * from each queue by each task, otherwise an error is detected. */ +#define intqMIN_ACCEPTABLE_TASK_COUNT ( 5 ) + +/* Send the next value to the queue that is normally empty. This is called + * from within the interrupts. */ +#define timerNORMALLY_EMPTY_TX() \ + if( xQueueIsQueueFullFromISR( xNormallyEmptyQueue ) != pdTRUE ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); \ + { \ + uxValueForNormallyEmptyQueue++; \ + if( xQueueSendFromISR( xNormallyEmptyQueue, ( void * ) &uxValueForNormallyEmptyQueue, &xHigherPriorityTaskWoken ) != pdPASS ) \ + { \ + uxValueForNormallyEmptyQueue--; \ + } \ + } \ + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); \ + } \ + + +/* Send the next value to the queue that is normally full. This is called + * from within the interrupts. */ +#define timerNORMALLY_FULL_TX() \ + if( xQueueIsQueueFullFromISR( xNormallyFullQueue ) != pdTRUE ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); \ + { \ + uxValueForNormallyFullQueue++; \ + if( xQueueSendFromISR( xNormallyFullQueue, ( void * ) &uxValueForNormallyFullQueue, &xHigherPriorityTaskWoken ) != pdPASS ) \ + { \ + uxValueForNormallyFullQueue--; \ + } \ + } \ + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); \ + } \ + + +/* Receive a value from the normally empty queue. This is called from within + * an interrupt. */ +#define timerNORMALLY_EMPTY_RX() \ + if( xQueueReceiveFromISR( xNormallyEmptyQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) != pdPASS ) \ + { \ + prvQueueAccessLogError( __LINE__ ); \ + } \ + else \ + { \ + prvRecordValue_NormallyEmpty( uxRxedValue, intqSECOND_INTERRUPT ); \ + } + +/* Receive a value from the normally full queue. This is called from within + * an interrupt. */ +#define timerNORMALLY_FULL_RX() \ + if( xQueueReceiveFromISR( xNormallyFullQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) == pdPASS ) \ + { \ + prvRecordValue_NormallyFull( uxRxedValue, intqSECOND_INTERRUPT ); \ + } \ + + +/*-----------------------------------------------------------*/ + +/* The two queues used by the test. */ +static QueueHandle_t xNormallyEmptyQueue, xNormallyFullQueue; + +/* Variables used to detect a stall in one of the tasks. */ +static volatile UBaseType_t uxHighPriorityLoops1 = 0, uxHighPriorityLoops2 = 0, uxLowPriorityLoops1 = 0, uxLowPriorityLoops2 = 0; + +/* Any unexpected behaviour sets xErrorStatus to fail and log the line that + * caused the error in xErrorLine. */ +static BaseType_t xErrorStatus = pdPASS; +static volatile UBaseType_t xErrorLine = ( UBaseType_t ) 0; + +/* Used for sequencing between tasks. */ +static BaseType_t xWasSuspended = pdFALSE; + +/* The values that are sent to the queues. An incremented value is sent each + * time to each queue. */ +static volatile UBaseType_t uxValueForNormallyEmptyQueue = 0, uxValueForNormallyFullQueue = 0; + +/* A handle to some of the tasks is required so they can be suspended/resumed. */ +TaskHandle_t xHighPriorityNormallyEmptyTask1, xHighPriorityNormallyEmptyTask2, xHighPriorityNormallyFullTask1, xHighPriorityNormallyFullTask2; + +/* When a value is received in a queue the value is ticked off in the array + * the array position of the value is set to a the identifier of the task or + * interrupt that accessed the queue. This way missing or duplicate values can be + * detected. */ +static uint8_t ucNormallyEmptyReceivedValues[ intqNUM_VALUES_TO_LOG ] = { 0 }; +static uint8_t ucNormallyFullReceivedValues[ intqNUM_VALUES_TO_LOG ] = { 0 }; + +/* The test tasks themselves. */ +static void prvLowerPriorityNormallyEmptyTask( void * pvParameters ); +static void prvLowerPriorityNormallyFullTask( void * pvParameters ); +static void prvHigherPriorityNormallyEmptyTask( void * pvParameters ); +static void prv1stHigherPriorityNormallyFullTask( void * pvParameters ); +static void prv2ndHigherPriorityNormallyFullTask( void * pvParameters ); + +/* Used to mark the positions within the ucNormallyEmptyReceivedValues and + * ucNormallyFullReceivedValues arrays, while checking for duplicates. */ +static void prvRecordValue_NormallyEmpty( UBaseType_t uxValue, + UBaseType_t uxSource ); +static void prvRecordValue_NormallyFull( UBaseType_t uxValue, + UBaseType_t uxSource ); + +/* Logs the line on which an error occurred. */ +static void prvQueueAccessLogError( UBaseType_t uxLine ); + +/*-----------------------------------------------------------*/ + +void vStartInterruptQueueTasks( void ) +{ + /* Start the test tasks. */ + xTaskCreate( prvHigherPriorityNormallyEmptyTask, "H1QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask1 ); + xTaskCreate( prvHigherPriorityNormallyEmptyTask, "H2QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask2 ); + xTaskCreate( prvLowerPriorityNormallyEmptyTask, "L1QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL ); + xTaskCreate( prv1stHigherPriorityNormallyFullTask, "H1QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask1 ); + xTaskCreate( prv2ndHigherPriorityNormallyFullTask, "H2QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask2 ); + xTaskCreate( prvLowerPriorityNormallyFullTask, "L2QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL ); + + /* Create the queues that are accessed by multiple tasks and multiple + * interrupts. */ + xNormallyFullQueue = xQueueCreate( intqQUEUE_LENGTH, ( UBaseType_t ) sizeof( UBaseType_t ) ); + xNormallyEmptyQueue = xQueueCreate( intqQUEUE_LENGTH, ( UBaseType_t ) sizeof( UBaseType_t ) ); + + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + * in use. The queue registry is provided as a means for kernel aware + * debuggers to locate queues and has no purpose if a kernel aware debugger + * is not being used. The call to vQueueAddToRegistry() will be removed + * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + * defined to be less than 1. */ + vQueueAddToRegistry( xNormallyFullQueue, "NormallyFull" ); + vQueueAddToRegistry( xNormallyEmptyQueue, "NormallyEmpty" ); +} +/*-----------------------------------------------------------*/ + +static void prvRecordValue_NormallyFull( UBaseType_t uxValue, + UBaseType_t uxSource ) +{ + if( uxValue < intqNUM_VALUES_TO_LOG ) + { + /* We don't expect to receive the same value twice, so if the value + * has already been marked as received an error has occurred. */ + if( ucNormallyFullReceivedValues[ uxValue ] != 0x00 ) + { + prvQueueAccessLogError( __LINE__ ); + } + + /* Log that this value has been received. */ + ucNormallyFullReceivedValues[ uxValue ] = ( uint8_t ) uxSource; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecordValue_NormallyEmpty( UBaseType_t uxValue, + UBaseType_t uxSource ) +{ + if( uxValue < intqNUM_VALUES_TO_LOG ) + { + /* We don't expect to receive the same value twice, so if the value + * has already been marked as received an error has occurred. */ + if( ucNormallyEmptyReceivedValues[ uxValue ] != 0x00 ) + { + prvQueueAccessLogError( __LINE__ ); + } + + /* Log that this value has been received. */ + ucNormallyEmptyReceivedValues[ uxValue ] = ( uint8_t ) uxSource; + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueAccessLogError( UBaseType_t uxLine ) +{ + /* Latch the line number that caused the error. */ + xErrorLine = uxLine; + xErrorStatus = pdFAIL; +} +/*-----------------------------------------------------------*/ + +static void prvHigherPriorityNormallyEmptyTask( void * pvParameters ) +{ + UBaseType_t uxRxed, ux, uxTask1, uxTask2, uxInterrupts, uxErrorCount1 = 0, uxErrorCount2 = 0; + + /* The timer should not be started until after the scheduler has started. + * More than one task is running this code so we check the parameter value + * to determine which task should start the timer. */ + if( ( UBaseType_t ) pvParameters == intqHIGH_PRIORITY_TASK1 ) + { + vInitialiseTimerForIntQueueTest(); + } + + for( ; ; ) + { + /* Block waiting to receive a value from the normally empty queue. + * Interrupts will write to the queue so we should receive a value. */ + if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqSHORT_DELAY ) != pdPASS ) + { + prvQueueAccessLogError( __LINE__ ); + } + else + { + /* Note which value was received so we can check all expected + * values are received and no values are duplicated. */ + prvRecordValue_NormallyEmpty( uxRxed, ( UBaseType_t ) pvParameters ); + } + + /* Ensure the other task running this code gets a chance to execute. */ + taskYIELD(); + + if( ( UBaseType_t ) pvParameters == intqHIGH_PRIORITY_TASK1 ) + { + /* Have we received all the expected values? */ + if( uxValueForNormallyEmptyQueue > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) ) + { + vTaskSuspend( xHighPriorityNormallyEmptyTask2 ); + + uxTask1 = 0; + uxTask2 = 0; + uxInterrupts = 0; + + /* Loop through the array, checking that both tasks have + * placed values into the array, and that no values are missing. + * Start at 1 as we expect position 0 to be unused. */ + for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ ) + { + if( ucNormallyEmptyReceivedValues[ ux ] == 0 ) + { + /* A value is missing. */ + prvQueueAccessLogError( __LINE__ ); + } + else + { + if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK1 ) + { + /* Value was placed into the array by task 1. */ + uxTask1++; + } + else if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK2 ) + { + /* Value was placed into the array by task 2. */ + uxTask2++; + } + else if( ucNormallyEmptyReceivedValues[ ux ] == intqSECOND_INTERRUPT ) + { + uxInterrupts++; + } + } + } + + if( uxTask1 < intqMIN_ACCEPTABLE_TASK_COUNT ) + { + /* Only task 2 seemed to log any values. */ + uxErrorCount1++; + + if( uxErrorCount1 > 2 ) + { + prvQueueAccessLogError( __LINE__ ); + } + } + else + { + uxErrorCount1 = 0; + } + + if( uxTask2 < intqMIN_ACCEPTABLE_TASK_COUNT ) + { + /* Only task 1 seemed to log any values. */ + uxErrorCount2++; + + if( uxErrorCount2 > 2 ) + { + prvQueueAccessLogError( __LINE__ ); + } + } + else + { + uxErrorCount2 = 0; + } + + if( uxInterrupts == 0 ) + { + prvQueueAccessLogError( __LINE__ ); + } + + /* Clear the array again, ready to start a new cycle. */ + memset( ucNormallyEmptyReceivedValues, 0x00, sizeof( ucNormallyEmptyReceivedValues ) ); + + uxHighPriorityLoops1++; + portENTER_CRITICAL(); + { + uxValueForNormallyEmptyQueue = 0; + } + portEXIT_CRITICAL(); + + /* Suspend ourselves, allowing the lower priority task to + * actually receive something from the queue. Until now it + * will have been prevented from doing so by the higher + * priority tasks. The lower priority task will resume us + * if it receives something. We will then resume the other + * higher priority task. */ + vTaskSuspend( NULL ); + vTaskResume( xHighPriorityNormallyEmptyTask2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvLowerPriorityNormallyEmptyTask( void * pvParameters ) +{ + UBaseType_t uxValue, uxRxed; + + /* The parameters are not being used so avoid compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqONE_TICK_DELAY ) != errQUEUE_EMPTY ) + { + /* A value should only be obtained when the high priority task is + * suspended. */ + if( eTaskGetState( xHighPriorityNormallyEmptyTask1 ) != eSuspended ) + { + prvQueueAccessLogError( __LINE__ ); + } + + prvRecordValue_NormallyEmpty( uxRxed, intqLOW_PRIORITY_TASK ); + + /* Wake the higher priority task again. */ + vTaskResume( xHighPriorityNormallyEmptyTask1 ); + uxLowPriorityLoops1++; + } + else + { + /* Raise our priority while we send so we can preempt the higher + * priority task, and ensure we get the Tx value into the queue. */ + vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 ); + + portENTER_CRITICAL(); + { + uxValueForNormallyEmptyQueue++; + uxValue = uxValueForNormallyEmptyQueue; + } + portEXIT_CRITICAL(); + + if( xQueueSend( xNormallyEmptyQueue, &uxValue, portMAX_DELAY ) != pdPASS ) + { + prvQueueAccessLogError( __LINE__ ); + } + + vTaskPrioritySet( NULL, intqLOWER_PRIORITY ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prv1stHigherPriorityNormallyFullTask( void * pvParameters ) +{ + UBaseType_t uxValueToTx, ux, uxInterrupts; + + /* The parameters are not being used so avoid compiler warnings. */ + ( void ) pvParameters; + + /* Make sure the queue starts full or near full. >> 1 as there are two + * high priority tasks. */ + for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ ) + { + portENTER_CRITICAL(); + { + uxValueForNormallyFullQueue++; + uxValueToTx = uxValueForNormallyFullQueue; + } + portEXIT_CRITICAL(); + + xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ); + } + + for( ; ; ) + { + portENTER_CRITICAL(); + { + uxValueForNormallyFullQueue++; + uxValueToTx = uxValueForNormallyFullQueue; + } + portEXIT_CRITICAL(); + + if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS ) + { + /* intqHIGH_PRIORITY_TASK2 is never suspended so we would not + * expect it to ever time out. */ + prvQueueAccessLogError( __LINE__ ); + } + + /* Allow the other task running this code to run. */ + taskYIELD(); + + /* Have all the expected values been sent to the queue? */ + if( uxValueToTx > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) ) + { + /* Make sure the other high priority task completes its send of + * any values below intqNUM_VALUE_TO_LOG. */ + vTaskDelay( intqSHORT_DELAY ); + + vTaskSuspend( xHighPriorityNormallyFullTask2 ); + + if( xWasSuspended == pdTRUE ) + { + /* We would have expected the other high priority task to have + * set this back to false by now. */ + prvQueueAccessLogError( __LINE__ ); + } + + /* Set the suspended flag so an error is not logged if the other + * task recognises a time out when it is unsuspended. */ + xWasSuspended = pdTRUE; + + /* Check interrupts are also sending. */ + uxInterrupts = 0U; + + /* Start at 1 as we expect position 0 to be unused. */ + for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ ) + { + if( ucNormallyFullReceivedValues[ ux ] == 0 ) + { + /* A value was missing. */ + prvQueueAccessLogError( __LINE__ ); + } + else if( ucNormallyFullReceivedValues[ ux ] == intqSECOND_INTERRUPT ) + { + uxInterrupts++; + } + } + + if( uxInterrupts == 0 ) + { + /* No writes from interrupts were found. Are interrupts + * actually running? */ + prvQueueAccessLogError( __LINE__ ); + } + + /* Reset the array ready for the next cycle. */ + memset( ucNormallyFullReceivedValues, 0x00, sizeof( ucNormallyFullReceivedValues ) ); + + uxHighPriorityLoops2++; + portENTER_CRITICAL(); + { + uxValueForNormallyFullQueue = 0; + } + portEXIT_CRITICAL(); + + /* Suspend ourselves, allowing the lower priority task to + * actually receive something from the queue. Until now it + * will have been prevented from doing so by the higher + * priority tasks. The lower priority task will resume us + * if it receives something. We will then resume the other + * higher priority task. */ + vTaskSuspend( NULL ); + vTaskResume( xHighPriorityNormallyFullTask2 ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prv2ndHigherPriorityNormallyFullTask( void * pvParameters ) +{ + UBaseType_t uxValueToTx, ux; + + /* The parameters are not being used so avoid compiler warnings. */ + ( void ) pvParameters; + + /* Make sure the queue starts full or near full. >> 1 as there are two + * high priority tasks. */ + for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ ) + { + portENTER_CRITICAL(); + { + uxValueForNormallyFullQueue++; + uxValueToTx = uxValueForNormallyFullQueue; + } + portEXIT_CRITICAL(); + + xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ); + } + + for( ; ; ) + { + portENTER_CRITICAL(); + { + uxValueForNormallyFullQueue++; + uxValueToTx = uxValueForNormallyFullQueue; + } + portEXIT_CRITICAL(); + + if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS ) + { + if( xWasSuspended != pdTRUE ) + { + /* It is ok to time out if the task has been suspended. */ + prvQueueAccessLogError( __LINE__ ); + } + } + + xWasSuspended = pdFALSE; + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void prvLowerPriorityNormallyFullTask( void * pvParameters ) +{ + UBaseType_t uxValue, uxTxed = 9999; + + /* The parameters are not being used so avoid compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + if( xQueueSend( xNormallyFullQueue, &uxTxed, intqONE_TICK_DELAY ) != errQUEUE_FULL ) + { + /* Should only succeed when the higher priority task is suspended */ + if( eTaskGetState( xHighPriorityNormallyFullTask1 ) != eSuspended ) + { + prvQueueAccessLogError( __LINE__ ); + } + + vTaskResume( xHighPriorityNormallyFullTask1 ); + uxLowPriorityLoops2++; + } + else + { + /* Raise our priority while we receive so we can preempt the higher + * priority task, and ensure we get the value from the queue. */ + vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 ); + + if( xQueueReceive( xNormallyFullQueue, &uxValue, portMAX_DELAY ) != pdPASS ) + { + prvQueueAccessLogError( __LINE__ ); + } + else + { + prvRecordValue_NormallyFull( uxValue, intqLOW_PRIORITY_TASK ); + } + + vTaskPrioritySet( NULL, intqLOWER_PRIORITY ); + } + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xFirstTimerHandler( void ) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + UBaseType_t uxRxedValue; + static UBaseType_t uxNextOperation = 0; + + /* Called from a timer interrupt. Perform various read and write + * accesses on the queues. */ + + uxNextOperation++; + + if( uxNextOperation & ( UBaseType_t ) 0x01 ) + { + timerNORMALLY_EMPTY_TX(); + timerNORMALLY_EMPTY_TX(); + timerNORMALLY_EMPTY_TX(); + } + else + { + timerNORMALLY_FULL_RX(); + timerNORMALLY_FULL_RX(); + timerNORMALLY_FULL_RX(); + } + + return xHigherPriorityTaskWoken; +} +/*-----------------------------------------------------------*/ + +BaseType_t xSecondTimerHandler( void ) +{ + UBaseType_t uxRxedValue; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + static UBaseType_t uxNextOperation = 0; + + /* Called from a timer interrupt. Perform various read and write + * accesses on the queues. */ + + uxNextOperation++; + + if( uxNextOperation & ( UBaseType_t ) 0x01 ) + { + timerNORMALLY_EMPTY_TX(); + timerNORMALLY_EMPTY_TX(); + + timerNORMALLY_EMPTY_RX(); + timerNORMALLY_EMPTY_RX(); + } + else + { + timerNORMALLY_FULL_RX(); + timerNORMALLY_FULL_TX(); + timerNORMALLY_FULL_TX(); + timerNORMALLY_FULL_TX(); + } + + return xHigherPriorityTaskWoken; +} +/*-----------------------------------------------------------*/ + + +BaseType_t xAreIntQueueTasksStillRunning( void ) +{ + static UBaseType_t uxLastHighPriorityLoops1 = 0, uxLastHighPriorityLoops2 = 0, uxLastLowPriorityLoops1 = 0, uxLastLowPriorityLoops2 = 0; + + /* xErrorStatus can be set outside of this function. This function just + * checks that all the tasks are still cycling. */ + + if( uxHighPriorityLoops1 == uxLastHighPriorityLoops1 ) + { + /* The high priority 1 task has stalled. */ + prvQueueAccessLogError( __LINE__ ); + } + + uxLastHighPriorityLoops1 = uxHighPriorityLoops1; + + if( uxHighPriorityLoops2 == uxLastHighPriorityLoops2 ) + { + /* The high priority 2 task has stalled. */ + prvQueueAccessLogError( __LINE__ ); + } + + uxLastHighPriorityLoops2 = uxHighPriorityLoops2; + + if( uxLowPriorityLoops1 == uxLastLowPriorityLoops1 ) + { + /* The low priority 1 task has stalled. */ + prvQueueAccessLogError( __LINE__ ); + } + + uxLastLowPriorityLoops1 = uxLowPriorityLoops1; + + if( uxLowPriorityLoops2 == uxLastLowPriorityLoops2 ) + { + /* The low priority 2 task has stalled. */ + prvQueueAccessLogError( __LINE__ ); + } + + uxLastLowPriorityLoops2 = uxLowPriorityLoops2; + + return xErrorStatus; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/IntSemTest.c b/SOFTWARE-FreeRTOS/Common/Minimal/IntSemTest.c new file mode 100644 index 0000000..e4be9b8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/IntSemTest.c @@ -0,0 +1,537 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Demonstrates and tests mutexes being used from an interrupt. + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "IntSemTest.h" + +/*-----------------------------------------------------------*/ + +/* The priorities of the test tasks. */ +#define intsemMASTER_PRIORITY ( tskIDLE_PRIORITY ) +#define intsemSLAVE_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which the tick hook will give the mutex. */ +#define intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ( 100 ) + +/* A block time of 0 means 'don't block'. */ +#define intsemNO_BLOCK 0 + +/* The maximum count value for the counting semaphore given from an + * interrupt. */ +#define intsemMAX_COUNT 3 + +/*-----------------------------------------------------------*/ + +/* + * The master is a task that receives a mutex that is given from an interrupt - + * although generally mutexes should not be used given in interrupts (and + * definitely never taken in an interrupt) there are some circumstances when it + * may be desirable. + * + * The slave task is just used by the master task to force priority inheritance + * on a mutex that is shared between the master and the slave - which is a + * separate mutex to that given by the interrupt. + */ +static void vInterruptMutexSlaveTask( void * pvParameters ); +static void vInterruptMutexMasterTask( void * pvParameters ); + +/* + * A test whereby the master takes the shared and interrupt mutexes in that + * order, then gives them back in the same order, ensuring the priority + * inheritance is behaving as expected at each step. + */ +static void prvTakeAndGiveInTheSameOrder( void ); + +/* + * A test whereby the master takes the shared and interrupt mutexes in that + * order, then gives them back in the opposite order to which they were taken, + * ensuring the priority inheritance is behaving as expected at each step. + */ +static void prvTakeAndGiveInTheOppositeOrder( void ); + +/* + * A simple task that interacts with an interrupt using a counting semaphore, + * primarily for code coverage purposes. + */ +static void vInterruptCountingSemaphoreTask( void * pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be + * detected in any of the tasks. */ +static volatile BaseType_t xErrorDetected = pdFALSE; + +/* Counters that are incremented on each cycle of a test. This is used to + * detect a stalled task - a test that is no longer running. */ +static volatile uint32_t ulMasterLoops = 0, ulCountingSemaphoreLoops = 0; + +/* Handles of the test tasks that must be accessed from other test tasks. */ +static TaskHandle_t xSlaveHandle; + +/* A mutex which is given from an interrupt - although generally mutexes should + * not be used given in interrupts (and definitely never taken in an interrupt) + * there are some circumstances when it may be desirable. */ +static SemaphoreHandle_t xISRMutex = NULL; + +/* A counting semaphore which is given from an interrupt. */ +static SemaphoreHandle_t xISRCountingSemaphore = NULL; + +/* A mutex which is shared between the master and slave tasks - the master + * does both sharing of this mutex with the slave and receiving a mutex from the + * interrupt. */ +static SemaphoreHandle_t xMasterSlaveMutex = NULL; + +/* Flag that allows the master task to control when the interrupt gives or does + * not give the mutex. There is no mutual exclusion on this variable, but this is + * only test code and it should be fine in the 32=bit test environment. */ +static BaseType_t xOkToGiveMutex = pdFALSE, xOkToGiveCountingSemaphore = pdFALSE; + +/* Used to coordinate timing between tasks and the interrupt. */ +const TickType_t xInterruptGivePeriod = pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ); + +/*-----------------------------------------------------------*/ + +void vStartInterruptSemaphoreTasks( void ) +{ + /* Create the semaphores that are given from an interrupt. */ + xISRMutex = xSemaphoreCreateMutex(); + configASSERT( xISRMutex ); + xISRCountingSemaphore = xSemaphoreCreateCounting( intsemMAX_COUNT, 0 ); + configASSERT( xISRCountingSemaphore ); + + /* Create the mutex that is shared between the master and slave tasks (the + * master receives a mutex from an interrupt and shares a mutex with the + * slave. */ + xMasterSlaveMutex = xSemaphoreCreateMutex(); + configASSERT( xMasterSlaveMutex ); + + /* Create the tasks that share mutexes between then and with interrupts. */ + xTaskCreate( vInterruptMutexSlaveTask, "IntMuS", configMINIMAL_STACK_SIZE, NULL, intsemSLAVE_PRIORITY, &xSlaveHandle ); + xTaskCreate( vInterruptMutexMasterTask, "IntMuM", configMINIMAL_STACK_SIZE, NULL, intsemMASTER_PRIORITY, NULL ); + + /* Create the task that blocks on the counting semaphore. */ + xTaskCreate( vInterruptCountingSemaphoreTask, "IntCnt", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vInterruptMutexMasterTask( void * pvParameters ) +{ + /* Just to avoid compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + prvTakeAndGiveInTheSameOrder(); + + /* Ensure not to starve out other tests. */ + ulMasterLoops++; + vTaskDelay( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ); + + prvTakeAndGiveInTheOppositeOrder(); + + /* Ensure not to starve out other tests. */ + ulMasterLoops++; + vTaskDelay( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTakeAndGiveInTheSameOrder( void ) +{ + /* Ensure the slave is suspended, and that this task is running at the + * lower priority as expected as the start conditions. */ + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + /* Take the semaphore that is shared with the slave. */ + if( xSemaphoreTake( xMasterSlaveMutex, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + + /* This task now has the mutex. Unsuspend the slave so it too + * attempts to take the mutex. */ + vTaskResume( xSlaveHandle ); + + /* The slave has the higher priority so should now have executed and + * blocked on the semaphore. */ + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xSlaveHandle ) == eBlocked ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* This task should now have inherited the priority of the slave + * task. */ + if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + /* Now wait a little longer than the time between ISR gives to also + * obtain the ISR mutex. */ + xOkToGiveMutex = pdTRUE; + + if( xSemaphoreTake( xISRMutex, ( xInterruptGivePeriod * 2 ) ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + + xOkToGiveMutex = pdFALSE; + + /* Attempting to take again immediately should fail as the mutex is + * already held. */ + if( xSemaphoreTake( xISRMutex, intsemNO_BLOCK ) != pdFAIL ) + { + xErrorDetected = __LINE__; + } + + /* Should still be at the priority of the slave task. */ + if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + /* Give back the ISR semaphore to ensure the priority is not + * disinherited as the shared mutex (which the higher priority task is + * attempting to obtain) is still held. */ + if( xSemaphoreGive( xISRMutex ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + + if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + /* Finally give back the shared mutex. This time the higher priority + * task should run before this task runs again - so this task should have + * disinherited the priority and the higher priority task should be in the + * suspended state again. */ + if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + + if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Reset the mutex ready for the next round. */ + xQueueReset( xISRMutex ); +} +/*-----------------------------------------------------------*/ + +static void prvTakeAndGiveInTheOppositeOrder( void ) +{ + /* Ensure the slave is suspended, and that this task is running at the + * lower priority as expected as the start conditions. */ + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + /* Take the semaphore that is shared with the slave. */ + if( xSemaphoreTake( xMasterSlaveMutex, intsemNO_BLOCK ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + + /* This task now has the mutex. Unsuspend the slave so it too + * attempts to take the mutex. */ + vTaskResume( xSlaveHandle ); + + /* The slave has the higher priority so should now have executed and + * blocked on the semaphore. */ + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xSlaveHandle ) == eBlocked ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* This task should now have inherited the priority of the slave + * task. */ + if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + /* Now wait a little longer than the time between ISR gives to also + * obtain the ISR mutex. */ + xOkToGiveMutex = pdTRUE; + + if( xSemaphoreTake( xISRMutex, ( xInterruptGivePeriod * 2 ) ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + + xOkToGiveMutex = pdFALSE; + + /* Attempting to take again immediately should fail as the mutex is + * already held. */ + if( xSemaphoreTake( xISRMutex, intsemNO_BLOCK ) != pdFAIL ) + { + xErrorDetected = __LINE__; + } + + /* Should still be at the priority of the slave task. */ + if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + /* Give back the shared semaphore to ensure the priority is not disinherited + * as the ISR mutex is still held. The higher priority slave task should run + * before this task runs again. */ + if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + + /* Should still be at the priority of the slave task as this task still + * holds one semaphore (this is a simplification in the priority inheritance + * mechanism. */ + if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + /* Give back the ISR semaphore, which should result in the priority being + * disinherited as it was the last mutex held. */ + if( xSemaphoreGive( xISRMutex ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + + if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY ) + { + xErrorDetected = __LINE__; + } + + /* Reset the mutex ready for the next round. */ + xQueueReset( xISRMutex ); +} +/*-----------------------------------------------------------*/ + +static void vInterruptMutexSlaveTask( void * pvParameters ) +{ + /* Just to avoid compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* This task starts by suspending itself so when it executes can be + * controlled by the master task. */ + vTaskSuspend( NULL ); + + /* This task will execute when the master task already holds the mutex. + * Attempting to take the mutex will place this task in the Blocked + * state. */ + if( xSemaphoreTake( xMasterSlaveMutex, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + + if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS ) + { + xErrorDetected = __LINE__; + } + } +} +/*-----------------------------------------------------------*/ + +static void vInterruptCountingSemaphoreTask( void * pvParameters ) +{ + BaseType_t xCount; + const TickType_t xDelay = pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) * ( intsemMAX_COUNT + 1 ); + + ( void ) pvParameters; + + for( ; ; ) + { + /* Expect to start with the counting semaphore empty. */ + if( uxQueueMessagesWaiting( ( QueueHandle_t ) xISRCountingSemaphore ) != 0 ) + { + xErrorDetected = __LINE__; + } + + /* Wait until it is expected that the interrupt will have filled the + * counting semaphore. */ + xOkToGiveCountingSemaphore = pdTRUE; + vTaskDelay( xDelay ); + xOkToGiveCountingSemaphore = pdFALSE; + + /* Now it is expected that the counting semaphore is full. */ + if( uxQueueMessagesWaiting( ( QueueHandle_t ) xISRCountingSemaphore ) != intsemMAX_COUNT ) + { + xErrorDetected = __LINE__; + } + + if( uxQueueSpacesAvailable( ( QueueHandle_t ) xISRCountingSemaphore ) != 0 ) + { + xErrorDetected = __LINE__; + } + + ulCountingSemaphoreLoops++; + + /* Expect to be able to take the counting semaphore intsemMAX_COUNT + * times. A block time of 0 is used as the semaphore should already be + * there. */ + xCount = 0; + + while( xSemaphoreTake( xISRCountingSemaphore, 0 ) == pdPASS ) + { + xCount++; + } + + if( xCount != intsemMAX_COUNT ) + { + xErrorDetected = __LINE__; + } + + /* Now raise the priority of this task so it runs immediately that the + * semaphore is given from the interrupt. */ + vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 ); + + /* Block to wait for the semaphore to be given from the interrupt. */ + xOkToGiveCountingSemaphore = pdTRUE; + xSemaphoreTake( xISRCountingSemaphore, portMAX_DELAY ); + xSemaphoreTake( xISRCountingSemaphore, portMAX_DELAY ); + xOkToGiveCountingSemaphore = pdFALSE; + + /* Reset the priority so as not to disturb other tests too much. */ + vTaskPrioritySet( NULL, tskIDLE_PRIORITY ); + + ulCountingSemaphoreLoops++; + } +} +/*-----------------------------------------------------------*/ + +void vInterruptSemaphorePeriodicTest( void ) +{ + static TickType_t xLastGiveTime = 0; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + TickType_t xTimeNow; + + /* No mutual exclusion on xOkToGiveMutex, but this is only test code (and + * only executed on a 32-bit architecture) so ignore that in this case. */ + xTimeNow = xTaskGetTickCountFromISR(); + + if( ( ( TickType_t ) ( xTimeNow - xLastGiveTime ) ) >= pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) ) + { + configASSERT( xISRMutex ); + + if( xOkToGiveMutex != pdFALSE ) + { + /* Null is used as the second parameter in this give, and non-NULL + * in the other gives for code coverage reasons. */ + xSemaphoreGiveFromISR( xISRMutex, NULL ); + + /* Second give attempt should fail. */ + configASSERT( xSemaphoreGiveFromISR( xISRMutex, &xHigherPriorityTaskWoken ) == pdFAIL ); + } + + if( xOkToGiveCountingSemaphore != pdFALSE ) + { + xSemaphoreGiveFromISR( xISRCountingSemaphore, &xHigherPriorityTaskWoken ); + } + + xLastGiveTime = xTimeNow; + } + + /* Remove compiler warnings about the value being set but not used. */ + ( void ) xHigherPriorityTaskWoken; +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreInterruptSemaphoreTasksStillRunning( void ) +{ + static uint32_t ulLastMasterLoopCounter = 0, ulLastCountingSemaphoreLoops = 0; + BaseType_t xReturn; + + /* If the demo tasks are running then it is expected that the loop counters + * will have changed since this function was last called. */ + if( ulLastMasterLoopCounter == ulMasterLoops ) + { + xErrorDetected = __LINE__; + } + + ulLastMasterLoopCounter = ulMasterLoops; + + if( ulLastCountingSemaphoreLoops == ulCountingSemaphoreLoops ) + { + xErrorDetected = __LINE__; + } + + ulLastCountingSemaphoreLoops = ulCountingSemaphoreLoops++; + + if( xErrorDetected != pdFALSE ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/MessageBufferAMP.c b/SOFTWARE-FreeRTOS/Common/Minimal/MessageBufferAMP.c new file mode 100644 index 0000000..7159adb --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/MessageBufferAMP.c @@ -0,0 +1,328 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * An example that mimics a message buffer being used to pass data from one core + * to another. The core that sends the data is referred to as core A. The core + * that receives the data is referred to as core B. The task implemented by + * prvCoreATask() runs on core A. Two instances of the task implemented by + * prvCoreBTasks() run on core B. prvCoreATask() sends messages via message + * buffers to both instances of prvCoreBTasks(), one message buffer per channel. + * A third message buffer is used to pass the handle of the message buffer + * written to by core A to an interrupt service routine that is triggered by + * core A but executes on core B. + * + * The example relies on the FreeRTOS provided default implementation of + * sbSEND_COMPLETED() being overridden by an implementation in FreeRTOSConfig.h + * that writes the handle of the message buffer that contains data into the + * control message buffer, then generates an interrupt in core B. The necessary + * implementation is provided in this file and can be enabled by adding the + * following to FreeRTOSConfig.h: + * + * #define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer ) + * + * Core to core communication via message buffer requires the message buffers + * to be at an address known to both cores within shared memory. + * + * Note that, while this example uses three message buffers, the same + * functionality can be implemented using a single message buffer by using the + * same design pattern described on the link below for queues, but using message + * buffers instead. It is actually simpler with a message buffer as variable + * length data can be written into the message buffer directly: + * https://www.FreeRTOS.org/Pend-on-multiple-rtos-objects.html#alternative_design_pattern + */ + +/* Standard includes. */ +#include "stdio.h" +#include "string.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "message_buffer.h" + +/* Demo app includes. */ +#include "MessageBufferAMP.h" + +/* Enough for 3 4 byte pointers, including the additional 4 bytes per message + * overhead of message buffers. */ +#define mbaCONTROL_MESSAGE_BUFFER_SIZE ( 24 ) + +/* Enough four 4 8 byte strings, plus the additional 4 bytes per message + * overhead of message buffers. */ +#define mbaTASK_MESSAGE_BUFFER_SIZE ( 60 ) + +/* The number of instances of prvCoreBTasks that are created. */ +#define mbaNUMBER_OF_CORE_B_TASKS 2 + +/* A block time of 0 simply means, don't block. */ +#define mbaDONT_BLOCK 0 + +/* Macro that mimics an interrupt service routine executing by simply calling + * the routine inline. */ +#define mbaGENERATE_CORE_B_INTERRUPT() prvCoreBInterruptHandler() + +/*-----------------------------------------------------------*/ + +/* + * Implementation of the task that, on a real dual core device, would run on + * core A and send message to tasks running on core B. + */ +static void prvCoreATask( void * pvParameters ); + +/* + * Implementation of the task that, on a real dual core device, would run on + * core B and receive message from core A. The demo creates two instances of + * this task. + */ +static void prvCoreBTasks( void * pvParameters ); + +/* + * The function that, on a real dual core device, would handle inter-core + * interrupts, but in this case is just called inline. + */ +static void prvCoreBInterruptHandler( void ); + +/*-----------------------------------------------------------*/ + +/* The message buffers used to pass data from core A to core B. */ +static MessageBufferHandle_t xCoreBMessageBuffers[ mbaNUMBER_OF_CORE_B_TASKS ]; + +/* The control message buffer. This is used to pass the handle of the message + * message buffer that holds application data into the core to core interrupt + * service routine. */ +static MessageBufferHandle_t xControlMessageBuffer; + +/* Counters used to indicate to the check that the tasks are still executing. */ +static uint32_t ulCycleCounters[ mbaNUMBER_OF_CORE_B_TASKS ]; + +/* Set to pdFALSE if any errors are detected. Used to inform the check task + * that something might be wrong. */ +BaseType_t xDemoStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +void vStartMessageBufferAMPTasks( configSTACK_DEPTH_TYPE xStackSize ) +{ + BaseType_t x; + + xControlMessageBuffer = xMessageBufferCreate( mbaCONTROL_MESSAGE_BUFFER_SIZE ); + + xTaskCreate( prvCoreATask, /* The function that implements the task. */ + "AMPCoreA", /* Human readable name for the task. */ + xStackSize, /* Stack size (in words!). */ + NULL, /* Task parameter is not used. */ + tskIDLE_PRIORITY, /* The priority at which the task is created. */ + NULL ); /* No use for the task handle. */ + + for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ ) + { + xCoreBMessageBuffers[ x ] = xMessageBufferCreate( mbaTASK_MESSAGE_BUFFER_SIZE ); + configASSERT( xCoreBMessageBuffers[ x ] ); + + /* Pass the loop counter into the created task using the task's + * parameter. The task then uses the value as an index into the + * ulCycleCounters and xCoreBMessageBuffers arrays. */ + xTaskCreate( prvCoreBTasks, + "AMPCoreB1", + xStackSize, + ( void * ) x, + tskIDLE_PRIORITY + 1, + NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCoreATask( void * pvParameters ) +{ + BaseType_t x; + uint32_t ulNextValue = 0; + const TickType_t xDelay = pdMS_TO_TICKS( 250 ); + char cString[ 15 ]; /* At least large enough to hold "4294967295\0" (0xffffffff). */ + + /* Remove warning about unused parameters. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Create the next string to send. The value is incremented on each + * loop iteration, and the length of the string changes as the number of + * digits in the value increases. */ + sprintf( cString, "%lu", ( unsigned long ) ulNextValue ); + + /* Send the value from this (pseudo) Core A to the tasks on the (pseudo) + * Core B via the message buffers. This will result in sbSEND_COMPLETED() + * being executed, which in turn will write the handle of the message + * buffer written to into xControlMessageBuffer then generate an interrupt + * in core B. */ + for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ ) + { + xMessageBufferSend( /* The message buffer to write to. */ + xCoreBMessageBuffers[ x ], + /* The source of the data to send. */ + ( void * ) cString, + /* The length of the data to send. */ + strlen( cString ), + /* The block time, should the buffer be full. */ + mbaDONT_BLOCK ); + } + + /* Delay before repeating with a different and potentially different + * length string. */ + vTaskDelay( xDelay ); + ulNextValue++; + } +} +/*-----------------------------------------------------------*/ + +static void prvCoreBTasks( void * pvParameters ) +{ + BaseType_t x; + size_t xReceivedBytes; + uint32_t ulNextValue = 0; + char cExpectedString[ 15 ]; /* At least large enough to hold "4294967295\0" (0xffffffff). */ + char cReceivedString[ 15 ]; + + /* The index into the xCoreBMessageBuffers and ulLoopCounter arrays is + * passed into this task using the task's parameter. */ + x = ( BaseType_t ) pvParameters; + configASSERT( x < mbaNUMBER_OF_CORE_B_TASKS ); + + for( ; ; ) + { + /* Create the string that is expected to be received this time round. */ + sprintf( cExpectedString, "%lu", ( unsigned long ) ulNextValue ); + + /* Wait to receive the next message from core A. */ + memset( cReceivedString, 0x00, sizeof( cReceivedString ) ); + xReceivedBytes = xMessageBufferReceive( /* The message buffer to receive from. */ + xCoreBMessageBuffers[ x ], + /* Location to store received data. */ + cReceivedString, + /* Maximum number of bytes to receive. */ + sizeof( cReceivedString ), + /* Ticks to wait if buffer is empty. */ + portMAX_DELAY ); + + /* Check the number of bytes received was as expected. */ + configASSERT( xReceivedBytes == strlen( cExpectedString ) ); + ( void ) xReceivedBytes; /* Incase configASSERT() is not defined. */ + + /* If the received string matches that expected then increment the loop + * counter so the check task knows this task is still running. */ + if( strcmp( cReceivedString, cExpectedString ) == 0 ) + { + ( ulCycleCounters[ x ] )++; + } + else + { + xDemoStatus = pdFAIL; + } + + /* Expect the next string in sequence the next time around. */ + ulNextValue++; + } +} +/*-----------------------------------------------------------*/ + +/* Called by the re-implementation of sbSEND_COMPLETED(), which can be defined + * as follows in FreeRTOSConfig.h: + #define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer ) + */ +void vGenerateCoreBInterrupt( void * xUpdatedMessageBuffer ) +{ + MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer; + + /* If sbSEND_COMPLETED() has been implemented as above, then this function + * is called from within xMessageBufferSend(). As this function also calls + * xMessageBufferSend() itself it is necessary to guard against a recursive + * call. If the message buffer just updated is the message buffer written to + * by this function, then this is a recursive call, and the function can just + * exit without taking further action. */ + if( xUpdatedBuffer != xControlMessageBuffer ) + { + /* Use xControlMessageBuffer to pass the handle of the message buffer + * written to by core A to the interrupt handler about to be generated in + * core B. */ + xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK ); + + /* This is where the interrupt would be generated. In this case it is + * not a genuine interrupt handler that executes, just a standard function + * call. */ + mbaGENERATE_CORE_B_INTERRUPT(); + } +} +/*-----------------------------------------------------------*/ + +/* Handler for the interrupts that are triggered on core A but execute on core + * B. */ +static void prvCoreBInterruptHandler( void ) +{ + MessageBufferHandle_t xUpdatedMessageBuffer; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* xControlMessageBuffer contains the handle of the message buffer that + * contains data. */ + if( xMessageBufferReceive( xControlMessageBuffer, + &xUpdatedMessageBuffer, + sizeof( xUpdatedMessageBuffer ), + mbaDONT_BLOCK ) == sizeof( xUpdatedMessageBuffer ) ) + { + /* Call the API function that sends a notification to any task that is + * blocked on the xUpdatedMessageBuffer message buffer waiting for data to + * arrive. */ + xMessageBufferSendCompletedFromISR( xUpdatedMessageBuffer, &xHigherPriorityTaskWoken ); + } + + /* Normal FreeRTOS yield from interrupt semantics, where + * xHigherPriorityTaskWoken is initialized to pdFALSE and will then get set to + * pdTRUE if the interrupt safe API unblocks a task that has a priority above + * that of the currently executing task. */ + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xAreMessageBufferAMPTasksStillRunning( void ) +{ + static uint32_t ulLastCycleCounters[ mbaNUMBER_OF_CORE_B_TASKS ] = { 0 }; + BaseType_t x; + + /* Called by the check task to determine the health status of the tasks + * implemented in this demo. */ + for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ ) + { + if( ulLastCycleCounters[ x ] == ulCycleCounters[ x ] ) + { + xDemoStatus = pdFAIL; + } + else + { + ulLastCycleCounters[ x ] = ulCycleCounters[ x ]; + } + } + + return xDemoStatus; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/MessageBufferDemo.c b/SOFTWARE-FreeRTOS/Common/Minimal/MessageBufferDemo.c new file mode 100644 index 0000000..d436727 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/MessageBufferDemo.c @@ -0,0 +1,971 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include "stdio.h" +#include "string.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "message_buffer.h" + +/* Demo app includes. */ +#include "MessageBufferDemo.h" + +/* The number of bytes of storage in the message buffers used in this test. */ +#define mbMESSAGE_BUFFER_LENGTH_BYTES ( ( size_t ) 50 ) + +/* The number of additional bytes used to store the length of each message. */ +#define mbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) ) + +/* Start and end ASCII characters used in messages sent to the buffers. */ +#define mbASCII_SPACE 32 +#define mbASCII_TILDA 126 + +/* Defines the number of tasks to create in this test and demo. */ +#define mbNUMBER_OF_ECHO_CLIENTS ( 2 ) +#define mbNUMBER_OF_SENDER_TASKS ( 2 ) + +/* Priority of the test tasks. The send and receive go from low to high + * priority tasks, and from high to low priority tasks. */ +#define mbLOWER_PRIORITY ( tskIDLE_PRIORITY ) +#define mbHIGHER_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* Block times used when sending and receiving from the message buffers. */ +#define mbRX_TX_BLOCK_TIME pdMS_TO_TICKS( 175UL ) + +/* A block time of 0 means "don't block". */ +#define mbDONT_BLOCK ( 0 ) + +/*-----------------------------------------------------------*/ + +/* + * Performs various tests that do not require multiple tasks to interact. + */ +static void prvSingleTaskTests( MessageBufferHandle_t xMessageBuffer ); + +/* + * Tests sending and receiving various lengths of messages via a message buffer. + * The echo client sends the messages to the echo server, which then sends the + * message back to the echo client which, checks it receives exactly what it + * sent. + */ +static void prvEchoClient( void * pvParameters ); +static void prvEchoServer( void * pvParameters ); + +/* + * Tasks that send and receive to a message buffer at a low priority and without + * blocking, so the send and receive functions interleave in time as the tasks + * are switched in and out. + */ +static void prvNonBlockingReceiverTask( void * pvParameters ); +static void prvNonBlockingSenderTask( void * pvParameters ); + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/* This file tests both statically and dynamically allocated message buffers. + * Allocate the structures and buffers to be used by the statically allocated + * objects, which get used in the echo tests. */ + static void prvReceiverTask( void * pvParameters ); + static void prvSenderTask( void * pvParameters ); + + static StaticMessageBuffer_t xStaticMessageBuffers[ mbNUMBER_OF_ECHO_CLIENTS ]; + static uint8_t ucBufferStorage[ mbNUMBER_OF_SENDER_TASKS ][ mbMESSAGE_BUFFER_LENGTH_BYTES + 1 ]; + static uint32_t ulSenderLoopCounters[ mbNUMBER_OF_SENDER_TASKS ] = { 0 }; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + + +#if ( configRUN_ADDITIONAL_TESTS == 1 ) + #define mbCOHERENCE_TEST_BUFFER_SIZE 20 + #define mbCOHERENCE_TEST_BYTES_WRITTEN 5 + #define mbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) ) + #define mbEXPECTED_FREE_BYTES_AFTER_WRITING_STRING ( mbCOHERENCE_TEST_BUFFER_SIZE - ( mbCOHERENCE_TEST_BYTES_WRITTEN + mbBYTES_TO_STORE_MESSAGE_LENGTH ) ) + + static void prvSpaceAvailableCoherenceActor( void * pvParameters ); + static void prvSpaceAvailableCoherenceTester( void * pvParameters ); + static MessageBufferHandle_t xCoherenceTestMessageBuffer = NULL; + + static uint32_t ulSizeCoherencyTestCycles = 0UL; +#endif /* if ( configRUN_ADDITIONAL_TESTS == 1 ) */ + +/*-----------------------------------------------------------*/ + +/* The buffers used by the echo client and server tasks. */ +typedef struct ECHO_MESSAGE_BUFFERS +{ + /* Handles to the data structures that describe the message buffers. */ + MessageBufferHandle_t xEchoClientBuffer; + MessageBufferHandle_t xEchoServerBuffer; +} EchoMessageBuffers_t; +static uint32_t ulEchoLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 }; + +/* The non-blocking tasks monitor their operation, and if no errors have been + * found, increment ulNonBlockingRxCounter. xAreMessageBufferTasksStillRunning() + * then checks ulNonBlockingRxCounter and only returns pdPASS if + * ulNonBlockingRxCounter is still incrementing. */ +static uint32_t ulNonBlockingRxCounter = 0; + +/* A message that is longer than the buffer, parts of which are written to the + * message buffer to test writing different lengths at different offsets. */ +static const char * pc55ByteString = "One two three four five six seven eight nine ten eleven"; + +/* Remember the required stack size so tasks can be created at run time (after + * initialisation time. */ +static configSTACK_DEPTH_TYPE xBlockingStackSize = 0; + +/*-----------------------------------------------------------*/ + +void vStartMessageBufferTasks( configSTACK_DEPTH_TYPE xStackSize ) +{ + MessageBufferHandle_t xMessageBuffer; + + #ifndef configMESSAGE_BUFFER_BLOCK_TASK_STACK_SIZE + xBlockingStackSize = ( xStackSize + ( xStackSize >> 1U ) ); + #else + xBlockingStackSize = configMESSAGE_BUFFER_BLOCK_TASK_STACK_SIZE; + #endif + + /* The echo servers sets up the message buffers before creating the echo + * client tasks. One set of tasks has the server as the higher priority, and + * the other has the client as the higher priority. */ + xTaskCreate( prvEchoServer, "1EchoServer", xBlockingStackSize, NULL, mbHIGHER_PRIORITY, NULL ); + xTaskCreate( prvEchoServer, "2EchoServer", xBlockingStackSize, NULL, mbLOWER_PRIORITY, NULL ); + + /* The non blocking tasks run continuously and will interleave with each + * other, so must be created at the lowest priority. The message buffer they + * use is created and passed in using the task's parameter. */ + xMessageBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES ); + xTaskCreate( prvNonBlockingReceiverTask, "NonBlkRx", xStackSize, ( void * ) xMessageBuffer, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvNonBlockingSenderTask, "NonBlkTx", xStackSize, ( void * ) xMessageBuffer, tskIDLE_PRIORITY, NULL ); + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* The sender tasks set up the message buffers before creating the + * receiver tasks. Priorities must be 0 and 1 as the priority is used to + * index into the xStaticMessageBuffers and ucBufferStorage arrays. */ + xTaskCreate( prvSenderTask, "1Sender", xBlockingStackSize, NULL, mbHIGHER_PRIORITY, NULL ); + xTaskCreate( prvSenderTask, "2Sender", xBlockingStackSize, NULL, mbLOWER_PRIORITY, NULL ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + #if ( configRUN_ADDITIONAL_TESTS == 1 ) + { + xCoherenceTestMessageBuffer = xMessageBufferCreate( mbCOHERENCE_TEST_BUFFER_SIZE ); + configASSERT( xCoherenceTestMessageBuffer ); + + xTaskCreate( prvSpaceAvailableCoherenceActor, "mbsanity1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvSpaceAvailableCoherenceTester, "mbsanity2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + } + #endif +} +/*-----------------------------------------------------------*/ + +static void prvSingleTaskTests( MessageBufferHandle_t xMessageBuffer ) +{ + size_t xReturned, xItem, xExpectedSpace, xNextLength; + const size_t xMax6ByteMessages = mbMESSAGE_BUFFER_LENGTH_BYTES / ( 6 + mbBYTES_TO_STORE_MESSAGE_LENGTH ); + const size_t x6ByteLength = 6, x17ByteLength = 17; + uint8_t * pucFullBuffer, * pucData, * pucReadData; + TickType_t xTimeBeforeCall, xTimeAfterCall; + const TickType_t xBlockTime = pdMS_TO_TICKS( 25 ), xAllowableMargin = pdMS_TO_TICKS( 3 ); + UBaseType_t uxOriginalPriority; + + /* Remove warning in case configASSERT() is not defined. */ + ( void ) xAllowableMargin; + + /* To minimise stack and heap usage a full size buffer is allocated from + * the heap, then buffers which hold smaller amounts of data are overlayed + * with the larger buffer - just make sure not to use both at once!. */ + pucFullBuffer = pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES ); + configASSERT( pucFullBuffer ); + + pucData = pucFullBuffer; + pucReadData = pucData + x17ByteLength; + + /* Nothing has been added or removed yet, so expect the free space to be + * exactly as created and the length of the next message to be 0. */ + xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer ); + configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES ); + configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE ); + xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer ); + configASSERT( xNextLength == 0 ); + /* In case configASSERT() is not define. */ + ( void ) xExpectedSpace; + ( void ) xNextLength; + + /* Try sending more bytes than possible, first using the FromISR version, then + * with an infinite block time to ensure this task does not lock up. */ + xReturned = xMessageBufferSendFromISR( xMessageBuffer, ( void * ) pucData, mbMESSAGE_BUFFER_LENGTH_BYTES + sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ), NULL ); + configASSERT( xReturned == ( size_t ) 0 ); + /* In case configASSERT() is not defined. */ + ( void ) xReturned; + xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, mbMESSAGE_BUFFER_LENGTH_BYTES + sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ), portMAX_DELAY ); + configASSERT( xReturned == ( size_t ) 0 ); + /* In case configASSERT() is not defined. */ + ( void ) xReturned; + + /* The buffer is 50 bytes long. When an item is added to the buffer an + * additional 4 bytes are added to hold the item's size. That means adding + * 6 bytes to the buffer will actually add 10 bytes to the buffer. Therefore, + * with a 50 byte buffer, a maximum of 5 6 bytes items can be added before the + * buffer is completely full. NOTE: The numbers in this paragraph assume + * sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) == 4. */ + for( xItem = 0; xItem < xMax6ByteMessages; xItem++ ) + { + configASSERT( xMessageBufferIsFull( xMessageBuffer ) == pdFALSE ); + + /* Generate recognizable data to write to the buffer. This is just + * ascii characters that shows which loop iteration the data was written + * in. The 'FromISR' version is used to give it some exercise as a block + * time is not used. That requires the call to be in a critical section + * so this code can also run on FreeRTOS ports that do not support + * interrupt nesting (and so don't have interrupt safe critical + * sections).*/ + memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength ); + taskENTER_CRITICAL(); + { + xReturned = xMessageBufferSendFromISR( xMessageBuffer, ( void * ) pucData, x6ByteLength, NULL ); + } + taskEXIT_CRITICAL(); + configASSERT( xReturned == x6ByteLength ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* The space in the buffer will have reduced by the amount of user data + * written into the buffer and the amount of space used to store the length + * of the data written into the buffer. */ + xExpectedSpace -= ( x6ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH ); + xReturned = xMessageBufferSpaceAvailable( xMessageBuffer ); + configASSERT( xReturned == xExpectedSpace ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Only 6 byte messages are written. */ + xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer ); + configASSERT( xNextLength == x6ByteLength ); + ( void ) xNextLength; /* In case configASSERT() is not defined. */ + } + + /* Now the buffer should be full, and attempting to add anything will should + * fail. */ + configASSERT( xMessageBufferIsFull( xMessageBuffer ) == pdTRUE ); + xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), mbDONT_BLOCK ); + configASSERT( xReturned == 0 ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Adding with a timeout should also fail after the appropriate time. The + * priority is temporarily boosted in this part of the test to keep the + * allowable margin to a minimum. */ + uxOriginalPriority = uxTaskPriorityGet( NULL ); + vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 ); + xTimeBeforeCall = xTaskGetTickCount(); + xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), xBlockTime ); + xTimeAfterCall = xTaskGetTickCount(); + vTaskPrioritySet( NULL, uxOriginalPriority ); + configASSERT( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) >= xBlockTime ); + configASSERT( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) < ( xBlockTime + xAllowableMargin ) ); + configASSERT( xReturned == 0 ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + ( void ) xTimeBeforeCall; + ( void ) xTimeAfterCall; + + /* The buffer is now full of data in the form "000000", "111111", etc. Make + * sure the data is read out as expected. */ + for( xItem = 0; xItem < xMax6ByteMessages; xItem++ ) + { + /* Generate the data that is expected to be read out for this loop + * iteration. */ + memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength ); + + /* Try reading the message into a buffer that is too small. The message + * should remain in the buffer. */ + xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x6ByteLength - 1, mbDONT_BLOCK ); + configASSERT( xReturned == 0 ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Should still be at least one 6 byte message still available. */ + xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer ); + configASSERT( xNextLength == x6ByteLength ); + ( void ) xNextLength; /* In case configASSERT() is not defined. */ + + /* Read the next 6 bytes out. The 'FromISR' version is used to give it + * some exercise as a block time is not used. THa requires the code to be + * in a critical section so this test can be run with FreeRTOS ports that + * do not support interrupt nesting (and therefore don't have interrupt + * safe critical sections). */ + taskENTER_CRITICAL(); + { + xReturned = xMessageBufferReceiveFromISR( xMessageBuffer, ( void * ) pucReadData, x6ByteLength, NULL ); + } + taskEXIT_CRITICAL(); + configASSERT( xReturned == x6ByteLength ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Does the data read out match that expected? */ + configASSERT( memcmp( ( void * ) pucData, ( void * ) pucReadData, x6ByteLength ) == 0 ); + + /* The space in the buffer will have increased by the amount of user + * data read from into the buffer and the amount of space used to store the + * length of the data read into the buffer. */ + xExpectedSpace += ( x6ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH ); + xReturned = xMessageBufferSpaceAvailable( xMessageBuffer ); + configASSERT( xReturned == xExpectedSpace ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + } + + /* The buffer should be empty again. */ + configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE ); + xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer ); + configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES ); + ( void ) xExpectedSpace; /* In case configASSERT() is not defined. */ + xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer ); + configASSERT( xNextLength == 0 ); + ( void ) xNextLength; /* In case configASSERT() is not defined. */ + + + /* Reading with a timeout should also fail after the appropriate time. The + * priority is temporarily boosted in this part of the test to keep the + * allowable margin to a minimum. */ + vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 ); + xTimeBeforeCall = xTaskGetTickCount(); + xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x6ByteLength, xBlockTime ); + xTimeAfterCall = xTaskGetTickCount(); + vTaskPrioritySet( NULL, uxOriginalPriority ); + configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) >= xBlockTime ); + configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) < ( xBlockTime + xAllowableMargin ) ); + configASSERT( xReturned == 0 ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + ( void ) xTimeBeforeCall; + ( void ) xTimeAfterCall; + + + /* In the next loop 17 bytes are written to then read out on each iteration. + * The expected length variable is always used after 17 bytes have been written + * into the buffer - the length of the message is also written, making a total + * of 21 bytes consumed for each 17 byte message. */ + xExpectedSpace = mbMESSAGE_BUFFER_LENGTH_BYTES - ( x17ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH ); + + /* Reading and writing 17 bytes at a time will result in 21 bytes being + * written into the buffer, and as 50 is not divisible by 21, writing multiple + * times will cause the data to wrap in the buffer.*/ + for( xItem = 0; xItem < 100; xItem++ ) + { + /* Generate recognizable data to write to the queue. This is just + * ascii characters that shows which loop iteration the data was written + * in. */ + memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x17ByteLength ); + xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, x17ByteLength, mbDONT_BLOCK ); + configASSERT( xReturned == x17ByteLength ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Only 17 byte messages are written. */ + xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer ); + configASSERT( xNextLength == x17ByteLength ); + ( void ) xNextLength; /* In case configASSERT() is not defined. */ + + /* The space in the buffer will have reduced by the amount of user data + * written into the buffer and the amount of space used to store the length + * of the data written into the buffer. */ + xReturned = xMessageBufferSpaceAvailable( xMessageBuffer ); + configASSERT( xReturned == xExpectedSpace ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Read the 17 bytes out again. */ + xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x17ByteLength, mbDONT_BLOCK ); + configASSERT( xReturned == x17ByteLength ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Does the data read out match that expected? */ + configASSERT( memcmp( ( void * ) pucData, ( void * ) pucReadData, x17ByteLength ) == 0 ); + + /* Don't expect any messages to be available as the data was read out + * again. */ + xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer ); + configASSERT( xNextLength == 0 ); + ( void ) xNextLength; /* In case configASSERT() is not defined. */ + } + + /* The buffer should be empty again. */ + configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE ); + xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer ); + configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES ); + + /* Cannot write within sizeof( size_t ) (assumed to be 4 bytes in this test) + * bytes of the full 50 bytes, as that would not leave space for the four bytes + * taken by the data length. */ + xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES, mbDONT_BLOCK ); + configASSERT( xReturned == 0 ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + #ifndef configMESSAGE_BUFFER_LENGTH_TYPE + { + /* The following will fail if configMESSAGE_BUFFER_LENGTH_TYPE is set + * to a non 32-bit type. */ + xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 1, mbDONT_BLOCK ); + configASSERT( xReturned == 0 ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 2, mbDONT_BLOCK ); + configASSERT( xReturned == 0 ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 3, mbDONT_BLOCK ); + configASSERT( xReturned == 0 ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + } + #endif /* ifndef configMESSAGE_BUFFER_LENGTH_TYPE */ + + /* Don't expect any messages to be available as the above were too large to + * get written. */ + xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer ); + configASSERT( xNextLength == 0 ); + ( void ) xNextLength; /* In case configASSERT() is not defined. */ + + /* Can write mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) bytes though. */ + xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ), mbDONT_BLOCK ); + configASSERT( xReturned == mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer ); + configASSERT( xNextLength == ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) ); + ( void ) xNextLength; /* In case configASSERT() is not defined. */ + xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucFullBuffer, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ), mbDONT_BLOCK ); + configASSERT( xReturned == ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + configASSERT( memcmp( ( const void * ) pucFullBuffer, pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) == 0 ); + + /* Clean up. */ + vPortFree( pucFullBuffer ); + xMessageBufferReset( xMessageBuffer ); +} +/*-----------------------------------------------------------*/ + +static void prvNonBlockingSenderTask( void * pvParameters ) +{ + MessageBufferHandle_t xMessageBuffer; + int32_t iDataToSend = 0; + size_t xStringLength; + const int32_t iMaxValue = 1500; + char cTxString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */ + + /* In this case the message buffer has already been created and is passed + * into the task using the task's parameter. */ + + xMessageBuffer = ( MessageBufferHandle_t ) pvParameters; + + /* Create a string from an incrementing number. The length of the + * string will increase and decrease as the value of the number increases + * then overflows. */ + memset( cTxString, 0x00, sizeof( cTxString ) ); + sprintf( cTxString, "%d", ( int ) iDataToSend ); + xStringLength = strlen( cTxString ); + + for( ; ; ) + { + /* Doesn't block so calls can interleave with the non-blocking + * receives performed by prvNonBlockingReceiverTask(). */ + if( xMessageBufferSend( xMessageBuffer, ( void * ) cTxString, strlen( cTxString ), mbDONT_BLOCK ) == xStringLength ) + { + iDataToSend++; + + if( iDataToSend > iMaxValue ) + { + /* The value sent is reset back to 0 to ensure the string being sent + * does not remain at the same length for too long. */ + iDataToSend = 0; + } + + /* Create the next string. */ + memset( cTxString, 0x00, sizeof( cTxString ) ); + sprintf( cTxString, "%d", ( int ) iDataToSend ); + xStringLength = strlen( cTxString ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvNonBlockingReceiverTask( void * pvParameters ) +{ + MessageBufferHandle_t xMessageBuffer; + BaseType_t xNonBlockingReceiveError = pdFALSE; + int32_t iDataToSend = 0; + size_t xStringLength, xReceiveLength; + const int32_t iMaxValue = 1500; + char cExpectedString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */ + char cRxString[ 12 ]; + + /* In this case the message buffer has already been created and is passed + * into the task using the task's parameter. */ + xMessageBuffer = ( MessageBufferHandle_t ) pvParameters; + + /* Create a string from an incrementing number. The length of the + * string will increase and decrease as the value of the number increases + * then overflows. This should always match the string sent to the buffer by + * the non blocking sender task. */ + memset( cExpectedString, 0x00, sizeof( cExpectedString ) ); + memset( cRxString, 0x00, sizeof( cRxString ) ); + sprintf( cExpectedString, "%d", ( int ) iDataToSend ); + xStringLength = strlen( cExpectedString ); + + for( ; ; ) + { + /* Doesn't block so calls can interleave with the non-blocking + * receives performed by prvNonBlockingReceiverTask(). */ + xReceiveLength = xMessageBufferReceive( xMessageBuffer, ( void * ) cRxString, sizeof( cRxString ), mbDONT_BLOCK ); + + /* Should only ever receive no data is available, or the expected + * length of data is available. */ + if( ( xReceiveLength != 0 ) && ( xReceiveLength != xStringLength ) ) + { + xNonBlockingReceiveError = pdTRUE; + } + + if( xReceiveLength == xStringLength ) + { + /* Ensure the received data was that expected, then generate the + * next expected string. */ + if( strcmp( cRxString, cExpectedString ) != 0 ) + { + xNonBlockingReceiveError = pdTRUE; + } + + iDataToSend++; + + if( iDataToSend > iMaxValue ) + { + /* The value sent is reset back to 0 to ensure the string being sent + * does not remain at the same length for too long. */ + iDataToSend = 0; + } + + memset( cExpectedString, 0x00, sizeof( cExpectedString ) ); + memset( cRxString, 0x00, sizeof( cRxString ) ); + sprintf( cExpectedString, "%d", ( int ) iDataToSend ); + xStringLength = strlen( cExpectedString ); + + if( xNonBlockingReceiveError == pdFALSE ) + { + /* No errors detected so increment the counter that lets the + * check task know this test is still functioning correctly. */ + ulNonBlockingRxCounter++; + } + } + } +} +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + static void prvSenderTask( void * pvParameters ) + { + MessageBufferHandle_t xMessageBuffer, xTempMessageBuffer; + int32_t iDataToSend = 0; + const int32_t iSendsBetweenIncrements = 100; + char cTxString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */ + const TickType_t xTicksToWait = mbRX_TX_BLOCK_TIME, xShortDelay = pdMS_TO_TICKS( 50 ); + StaticMessageBuffer_t xStaticMessageBuffer; + size_t xBytesSent; + + + /* The task's priority is used as an index into the loop counters used to + * indicate this task is still running. */ + UBaseType_t uxIndex = uxTaskPriorityGet( NULL ); + + /* Make sure a change in priority does not inadvertently result in an + * invalid array index. */ + configASSERT( uxIndex < mbNUMBER_OF_ECHO_CLIENTS ); + + /* Avoid compiler warnings about unused parameters. */ + ( void ) pvParameters; + + xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ) / mbNUMBER_OF_SENDER_TASKS, /* The number of bytes in each buffer in the array. */ + &( ucBufferStorage[ uxIndex ][ 0 ] ), /* The address of the buffer to use within the array. */ + &( xStaticMessageBuffers[ uxIndex ] ) ); /* The static message buffer structure to use within the array. */ + + /* Now the message buffer has been created the receiver task can be created. + * If this sender task has the higher priority then the receiver task is + * created at the lower priority - if this sender task has the lower priority + * then the receiver task is created at the higher priority. */ + if( uxTaskPriorityGet( NULL ) == mbLOWER_PRIORITY ) + { + /* Here prvSingleTaskTests() performs various tests on a message buffer + * that was created statically. */ + prvSingleTaskTests( xMessageBuffer ); + xTaskCreate( prvReceiverTask, "MsgReceiver", xBlockingStackSize, ( void * ) xMessageBuffer, mbHIGHER_PRIORITY, NULL ); + } + else + { + xTaskCreate( prvReceiverTask, "MsgReceiver", xBlockingStackSize, ( void * ) xMessageBuffer, mbLOWER_PRIORITY, NULL ); + } + + for( ; ; ) + { + /* Create a string from an incrementing number. The length of the + * string will increase and decrease as the value of the number increases + * then overflows. */ + memset( cTxString, 0x00, sizeof( cTxString ) ); + sprintf( cTxString, "%d", ( int ) iDataToSend ); + + do + { + xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) cTxString, strlen( cTxString ), xTicksToWait ); + } while( xBytesSent == 0 ); /* Buffer may become full when receiver is running at the idle priority. */ + + iDataToSend++; + + if( ( iDataToSend % iSendsBetweenIncrements ) == 0 ) + { + /* Increment a loop counter so a check task can tell this task is + * still running as expected. */ + ulSenderLoopCounters[ uxIndex ]++; + + if( uxTaskPriorityGet( NULL ) == mbHIGHER_PRIORITY ) + { + /* Allow other tasks to run. */ + vTaskDelay( xShortDelay ); + } + + /* This message buffer is just created and deleted to ensure no + * issues when attempting to delete a message buffer that was + * created using statically allocated memory. To save stack space + * the buffer is set to point to the cTxString array - this is + * ok because nothing is actually written to the memory. */ + xTempMessageBuffer = xMessageBufferCreateStatic( sizeof( cTxString ), ( uint8_t * ) cTxString, &xStaticMessageBuffer ); + vMessageBufferDelete( xTempMessageBuffer ); + } + } + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + static void prvReceiverTask( void * pvParameters ) + { + MessageBufferHandle_t const pxMessageBuffer = ( MessageBufferHandle_t ) pvParameters; + char cExpectedString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */ + char cReceivedString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */ + int32_t iExpectedData = 0; + const TickType_t xTicksToWait = pdMS_TO_TICKS( 5UL ); + size_t xReceivedBytes; + + for( ; ; ) + { + /* Generate the next expected string in the cExpectedString buffer. */ + memset( cExpectedString, 0x00, sizeof( cExpectedString ) ); + sprintf( cExpectedString, "%d", ( int ) iExpectedData ); + + /* Receive the next string from the message buffer. */ + memset( cReceivedString, 0x00, sizeof( cReceivedString ) ); + + do + { + xReceivedBytes = xMessageBufferReceive( pxMessageBuffer, ( void * ) cReceivedString, sizeof( cExpectedString ), xTicksToWait ); + } while( xReceivedBytes == 0 ); + + /* Ensure the received string matches the expected string. */ + configASSERT( strcmp( cExpectedString, cReceivedString ) == 0 ); + + iExpectedData++; + } + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvEchoClient( void * pvParameters ) +{ + size_t xSendLength = 0, ux; + char * pcStringToSend, * pcStringReceived, cNextChar = mbASCII_SPACE; + const TickType_t xTicksToWait = pdMS_TO_TICKS( 50 ); + +/* The task's priority is used as an index into the loop counters used to + * indicate this task is still running. */ + UBaseType_t uxIndex = uxTaskPriorityGet( NULL ); + +/* Pointers to the client and server message buffers are passed into this task + * using the task's parameter. */ + EchoMessageBuffers_t * pxMessageBuffers = ( EchoMessageBuffers_t * ) pvParameters; + + /* Prevent compiler warnings. */ + ( void ) pvParameters; + + /* Create the buffer into which strings to send to the server will be + * created, and the buffer into which strings echoed back from the server will + * be copied. */ + pcStringToSend = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES ); + pcStringReceived = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES ); + + configASSERT( pcStringToSend ); + configASSERT( pcStringReceived ); + + for( ; ; ) + { + /* Generate the length of the next string to send. */ + xSendLength++; + + /* The message buffer is being used to hold variable length data, so + * each data item requires sizeof( size_t ) bytes to hold the data's + * length, hence the sizeof() in the if() condition below. */ + if( xSendLength > ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) ) + { + /* Back to a string length of 1. */ + xSendLength = sizeof( char ); + + /* Maintain a count of the number of times this code executes so a + * check task can determine if this task is still functioning as + * expected or not. As there are two client tasks, and the priorities + * used are 0 and 1, the task's priority is used as an index into the + * loop count array. */ + ulEchoLoopCounters[ uxIndex ]++; + } + + memset( pcStringToSend, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES ); + + for( ux = 0; ux < xSendLength; ux++ ) + { + pcStringToSend[ ux ] = cNextChar; + + cNextChar++; + + if( cNextChar > mbASCII_TILDA ) + { + cNextChar = mbASCII_SPACE; + } + } + + /* Send the generated string to the buffer. */ + do + { + ux = xMessageBufferSend( pxMessageBuffers->xEchoClientBuffer, ( void * ) pcStringToSend, xSendLength, xTicksToWait ); + + if( ux == 0 ) + { + mtCOVERAGE_TEST_MARKER(); + } + } while( ux == 0 ); + + /* Wait for the string to be echoed back. */ + memset( pcStringReceived, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES ); + xMessageBufferReceive( pxMessageBuffers->xEchoServerBuffer, ( void * ) pcStringReceived, xSendLength, portMAX_DELAY ); + + configASSERT( strcmp( pcStringToSend, pcStringReceived ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +static void prvEchoServer( void * pvParameters ) +{ + MessageBufferHandle_t xTempMessageBuffer; + size_t xReceivedLength; + char * pcReceivedString; + EchoMessageBuffers_t xMessageBuffers; + TickType_t xTimeOnEntering; + const TickType_t xTicksToBlock = pdMS_TO_TICKS( 250UL ); + + /* Prevent compiler warnings about unused parameters. */ + ( void ) pvParameters; + + /* Create the message buffer used to send data from the client to the server, + * and the message buffer used to echo the data from the server back to the + * client. */ + xMessageBuffers.xEchoClientBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES ); + xMessageBuffers.xEchoServerBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES ); + configASSERT( xMessageBuffers.xEchoClientBuffer ); + configASSERT( xMessageBuffers.xEchoServerBuffer ); + + /* Create the buffer into which received strings will be copied. */ + pcReceivedString = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES ); + configASSERT( pcReceivedString ); + + /* Don't expect to receive anything yet! */ + xTimeOnEntering = xTaskGetTickCount(); + xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, xTicksToBlock ); + configASSERT( ( ( TickType_t ) ( xTaskGetTickCount() - xTimeOnEntering ) ) >= xTicksToBlock ); + configASSERT( xReceivedLength == 0 ); + ( void ) xTimeOnEntering; /* In case configASSERT() is not defined. */ + + /* Now the message buffers have been created the echo client task can be + * created. If this server task has the higher priority then the client task + * is created at the lower priority - if this server task has the lower + * priority then the client task is created at the higher priority. */ + if( uxTaskPriorityGet( NULL ) == mbLOWER_PRIORITY ) + { + xTaskCreate( prvEchoClient, "EchoClient", configMINIMAL_STACK_SIZE, ( void * ) &xMessageBuffers, mbHIGHER_PRIORITY, NULL ); + } + else + { + /* Here prvSingleTaskTests() performs various tests on a message buffer + * that was created dynamically. */ + prvSingleTaskTests( xMessageBuffers.xEchoClientBuffer ); + xTaskCreate( prvEchoClient, "EchoClient", configMINIMAL_STACK_SIZE, ( void * ) &xMessageBuffers, mbLOWER_PRIORITY, NULL ); + } + + for( ; ; ) + { + memset( pcReceivedString, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES ); + + /* Has any data been sent by the client? */ + xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, portMAX_DELAY ); + + /* Should always receive data as max delay was used. */ + configASSERT( xReceivedLength > 0 ); + + /* Echo the received data back to the client. */ + xMessageBufferSend( xMessageBuffers.xEchoServerBuffer, ( void * ) pcReceivedString, xReceivedLength, portMAX_DELAY ); + + /* This message buffer is just created and deleted to ensure no memory + * leaks. */ + xTempMessageBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES ); + vMessageBufferDelete( xTempMessageBuffer ); + } +} +/*-----------------------------------------------------------*/ + +/* Tests within configRUN_ADDITIONAL_TESTS blocks only execute on larger + * platforms or have been added to pre-existing files that are already in use + * by other test projects without ensuring they don't cause those pre-existing + * projects to run out of program or data memory. */ +#if ( configRUN_ADDITIONAL_TESTS == 1 ) + + static void prvSpaceAvailableCoherenceActor( void * pvParameters ) + { + static char * cTxString = "12345"; + char cRxString[ mbCOHERENCE_TEST_BYTES_WRITTEN + 1 ]; /* +1 for NULL terminator. */ + + ( void ) pvParameters; + + for( ; ; ) + { + /* Add bytes to the buffer so the other task should see + * mbEXPECTED_FREE_BYTES_AFTER_WRITING_STRING bytes free. */ + xMessageBufferSend( xCoherenceTestMessageBuffer, ( void * ) cTxString, strlen( cTxString ), 0 ); + configASSERT( xMessageBufferSpacesAvailable( xCoherenceTestMessageBuffer ) == mbEXPECTED_FREE_BYTES_AFTER_WRITING_STRING ); + + /* Read out message again so the other task should read the full + * mbCOHERENCE_TEST_BUFFER_SIZE bytes free again. */ + memset( ( void * ) cRxString, 0x00, sizeof( cRxString ) ); + xMessageBufferReceive( xCoherenceTestMessageBuffer, ( void * ) cRxString, mbCOHERENCE_TEST_BYTES_WRITTEN, 0 ); + configASSERT( strcmp( cTxString, cRxString ) == 0 ); + } + } + /*-----------------------------------------------------------*/ + + static void prvSpaceAvailableCoherenceTester( void * pvParameters ) + { + size_t xSpaceAvailable; + BaseType_t xErrorFound = pdFALSE; + + ( void ) pvParameters; + + for( ; ; ) + { + /* This message buffer is only ever empty or contains 5 bytes. So all + * queries of its free space should result in one of the two values tested + * below. */ + xSpaceAvailable = xMessageBufferSpacesAvailable( xCoherenceTestMessageBuffer ); + + if( ( xSpaceAvailable == mbCOHERENCE_TEST_BUFFER_SIZE ) || + ( xSpaceAvailable == mbEXPECTED_FREE_BYTES_AFTER_WRITING_STRING ) ) + { + /* Only continue to increment the variable that shows this task + * is still executing if no errors have been found. */ + if( xErrorFound == pdFALSE ) + { + ulSizeCoherencyTestCycles++; + } + } + else + { + xErrorFound = pdTRUE; + } + + configASSERT( xErrorFound == pdFALSE ); + } + } + +#endif /* configRUN_ADDITIONAL_TESTS == 1 */ +/*-----------------------------------------------------------*/ + +BaseType_t xAreMessageBufferTasksStillRunning( void ) +{ + static uint32_t ulLastEchoLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 }; + static uint32_t ulLastNonBlockingRxCounter = 0; + BaseType_t xReturn = pdPASS, x; + + for( x = 0; x < mbNUMBER_OF_ECHO_CLIENTS; x++ ) + { + if( ulLastEchoLoopCounters[ x ] == ulEchoLoopCounters[ x ] ) + { + xReturn = pdFAIL; + } + else + { + ulLastEchoLoopCounters[ x ] = ulEchoLoopCounters[ x ]; + } + } + + if( ulNonBlockingRxCounter == ulLastNonBlockingRxCounter ) + { + xReturn = pdFAIL; + } + else + { + ulLastNonBlockingRxCounter = ulNonBlockingRxCounter; + } + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + static uint32_t ulLastSenderLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 }; + + for( x = 0; x < mbNUMBER_OF_SENDER_TASKS; x++ ) + { + if( ulLastSenderLoopCounters[ x ] == ulSenderLoopCounters[ x ] ) + { + xReturn = pdFAIL; + } + else + { + ulLastSenderLoopCounters[ x ] = ulSenderLoopCounters[ x ]; + } + } + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + #if ( configRUN_ADDITIONAL_TESTS == 1 ) + { + static uint32_t ullastSizeCoherencyTestCycles = 0UL; + + if( ullastSizeCoherencyTestCycles == ulSizeCoherencyTestCycles ) + { + xReturn = pdFAIL; + } + else + { + ullastSizeCoherencyTestCycles = ulSizeCoherencyTestCycles; + } + } + #endif /* if ( configRUN_ADDITIONAL_TESTS == 1 ) */ + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/PollQ.c b/SOFTWARE-FreeRTOS/Common/Minimal/PollQ.c new file mode 100644 index 0000000..e49cd06 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/PollQ.c @@ -0,0 +1,222 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This version of PollQ. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + */ + +/* + * Changes from V2.0.0 + * + + Delay periods are now specified using variables and constants of + + TickType_t rather than uint32_t. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "PollQ.h" + +#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE +#define pollqQUEUE_SIZE ( 10 ) +#define pollqPRODUCER_DELAY ( pdMS_TO_TICKS( ( TickType_t ) 200 ) ) +#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( TickType_t ) ( 20 / portTICK_PERIOD_MS ) ) +#define pollqNO_DELAY ( ( TickType_t ) 0 ) +#define pollqVALUES_TO_PRODUCE ( ( BaseType_t ) 3 ) +#define pollqINITIAL_VALUE ( ( BaseType_t ) 0 ) + +/* The task that posts the incrementing number onto the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters ); + +/* The task that empties the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters ); + +/* Variables that are used to check that the tasks are still running with no + * errors. */ +static volatile BaseType_t xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE; + +/*-----------------------------------------------------------*/ + +void vStartPolledQueueTasks( UBaseType_t uxPriority ) +{ + static QueueHandle_t xPolledQueue; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( UBaseType_t ) sizeof( uint16_t ) ); + + if( xPolledQueue != NULL ) + { + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + * in use. The queue registry is provided as a means for kernel aware + * debuggers to locate queues and has no purpose if a kernel aware debugger + * is not being used. The call to vQueueAddToRegistry() will be removed + * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + * defined to be less than 1. */ + vQueueAddToRegistry( xPolledQueue, "Poll_Test_Queue" ); + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( TaskHandle_t * ) NULL ); + xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( TaskHandle_t * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueProducer, pvParameters ) +{ + uint16_t usValue = ( uint16_t ) 0; + BaseType_t xError = pdFALSE, xLoop; + + for( ; ; ) + { + for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueSend( *( ( QueueHandle_t * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS ) + { + /* We should never find the queue full so if we get here there + * has been an error. */ + xError = pdTRUE; + } + else + { + if( xError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + * check variable. */ + portENTER_CRITICAL(); + xPollingProducerCount++; + portEXIT_CRITICAL(); + } + + /* Update the value we are going to post next time around. */ + usValue++; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + * empties the queue. */ + vTaskDelay( pollqPRODUCER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters ) +{ + uint16_t usData, usExpectedValue = ( uint16_t ) 0; + BaseType_t xError = pdFALSE; + + for( ; ; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *( ( QueueHandle_t * ) pvParameters ) ) ) + { + if( xQueueReceive( *( ( QueueHandle_t * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + * occurred. */ + xError = pdTRUE; + + /* Catch-up to the value we received so our next expected + * value should again be correct. */ + usExpectedValue = usData; + } + else + { + if( xError == pdFALSE ) + { + /* Only increment the check variable if no errors have + * occurred. */ + portENTER_CRITICAL(); + xPollingConsumerCount++; + portEXIT_CRITICAL(); + } + } + + /* Next time round we would expect the number to be one higher. */ + usExpectedValue++; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + * items in the queue. */ + vTaskDelay( pollqCONSUMER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +BaseType_t xArePollingQueuesStillRunning( void ) +{ + BaseType_t xReturn; + + /* Check both the consumer and producer poll count to check they have both + * been changed since out last trip round. We do not need a critical section + * around the check variables as this is called from a higher priority than + * the other tasks that access the same variables. */ + if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) || + ( xPollingProducerCount == pollqINITIAL_VALUE ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Set the check variables back down so we know if they have been + * incremented the next time around. */ + xPollingConsumerCount = pollqINITIAL_VALUE; + xPollingProducerCount = pollqINITIAL_VALUE; + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/QPeek.c b/SOFTWARE-FreeRTOS/Common/Minimal/QPeek.c new file mode 100644 index 0000000..ba33723 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/QPeek.c @@ -0,0 +1,440 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Tests the behaviour when data is peeked from a queue when there are + * multiple tasks blocked on the queue. + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "QPeek.h" + +#define qpeekQUEUE_LENGTH ( 5 ) +#define qpeekNO_BLOCK ( 0 ) +#define qpeekSHORT_DELAY ( 10 ) + +#define qpeekLOW_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define qpeekMEDIUM_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define qpeekHIGH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define qpeekHIGHEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/*-----------------------------------------------------------*/ + +/* + * The following three tasks are used to demonstrate the peeking behaviour. + * Each task is given a different priority to demonstrate the order in which + * tasks are woken as data is peeked from a queue. + */ +static void prvLowPriorityPeekTask( void * pvParameters ); +static void prvMediumPriorityPeekTask( void * pvParameters ); +static void prvHighPriorityPeekTask( void * pvParameters ); +static void prvHighestPriorityPeekTask( void * pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be + * detected in any of the tasks. */ +static volatile BaseType_t xErrorDetected = pdFALSE; + +/* Counter that is incremented on each cycle of a test. This is used to + * detect a stalled task - a test that is no longer running. */ +static volatile uint32_t ulLoopCounter = 0; + +/* Handles to the test tasks. */ +TaskHandle_t xMediumPriorityTask, xHighPriorityTask, xHighestPriorityTask; +/*-----------------------------------------------------------*/ + +void vStartQueuePeekTasks( void ) +{ + QueueHandle_t xQueue; + + /* Create the queue that we are going to use for the test/demo. */ + xQueue = xQueueCreate( qpeekQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + * in use. The queue registry is provided as a means for kernel aware + * debuggers to locate queues and has no purpose if a kernel aware debugger + * is not being used. The call to vQueueAddToRegistry() will be removed + * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + * defined to be less than 1. */ + vQueueAddToRegistry( xQueue, "QPeek_Test_Queue" ); + + /* Create the demo tasks and pass it the queue just created. We are + * passing the queue handle by value so it does not matter that it is declared + * on the stack here. */ + xTaskCreate( prvLowPriorityPeekTask, "PeekL", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekLOW_PRIORITY, NULL ); + xTaskCreate( prvMediumPriorityPeekTask, "PeekM", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekMEDIUM_PRIORITY, &xMediumPriorityTask ); + xTaskCreate( prvHighPriorityPeekTask, "PeekH1", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGH_PRIORITY, &xHighPriorityTask ); + xTaskCreate( prvHighestPriorityPeekTask, "PeekH2", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGHEST_PRIORITY, &xHighestPriorityTask ); + } +} +/*-----------------------------------------------------------*/ + +static void prvHighestPriorityPeekTask( void * pvParameters ) +{ + QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters; + uint32_t ulValue; + + #ifdef USE_STDIO + { + void vPrintDisplayMessage( const char * const * ppcMessageToSend ); + + const char * const pcTaskStartMsg = "Queue peek test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + } + #endif + + for( ; ; ) + { + /* Try peeking from the queue. The queue should be empty so we will + * block, allowing the high priority task to execute. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we reach here the high and medium priority tasks should still + * be blocked on the queue. We unblocked because the low priority task + * wrote a value to the queue, which we should have peeked. Peeking the + * data (rather than receiving it) will leave the data on the queue, so + * the high priority task should then have also been unblocked, but not + * yet executed. */ + if( ulValue != 0x11223344 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* Now we are going to actually receive the data, so when the high + * priority task runs it will find the queue empty and return to the + * blocked state. */ + ulValue = 0; + + if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We expected to receive the value. */ + xErrorDetected = pdTRUE; + } + + if( ulValue != 0x11223344 ) + { + /* We did not receive the expected value - which should have been + * the same value as was peeked. */ + xErrorDetected = pdTRUE; + } + + /* Now we will block again as the queue is once more empty. The low + * priority task can then execute again. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we get here the low priority task should have again written to the + * queue. */ + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* We only peeked the data, so suspending ourselves now should enable + * the high priority task to also peek the data. The high priority task + * will have been unblocked when we peeked the data as we left the data + * in the queue. */ + vTaskSuspend( NULL ); + + /* This time we are going to do the same as the above test, but the + * high priority task is going to receive the data, rather than peek it. + * This means that the medium priority task should never peek the value. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulValue != 0xaabbaabb ) + { + xErrorDetected = pdTRUE; + } + + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvHighPriorityPeekTask( void * pvParameters ) +{ + QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters; + uint32_t ulValue; + + for( ; ; ) + { + /* Try peeking from the queue. The queue should be empty so we will + * block, allowing the medium priority task to execute. Both the high + * and highest priority tasks will then be blocked on the queue. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we get here the highest priority task should have peeked the data + * (unblocking this task) then suspended (allowing this task to also peek + * the data). */ + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* We only peeked the data, so suspending ourselves now should enable + * the medium priority task to also peek the data. The medium priority task + * will have been unblocked when we peeked the data as we left the data + * in the queue. */ + vTaskSuspend( NULL ); + + /* This time we are going actually receive the value, so the medium + * priority task will never peek the data - we removed it from the queue. */ + if( xQueueReceive( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulValue != 0xaabbaabb ) + { + xErrorDetected = pdTRUE; + } + + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvMediumPriorityPeekTask( void * pvParameters ) +{ + QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters; + uint32_t ulValue; + + for( ; ; ) + { + /* Try peeking from the queue. The queue should be empty so we will + * block, allowing the low priority task to execute. The highest, high + * and medium priority tasks will then all be blocked on the queue. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we get here the high priority task should have peeked the data + * (unblocking this task) then suspended (allowing this task to also peek + * the data). */ + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* Just so we know the test is still running. */ + ulLoopCounter++; + + /* Now we can suspend ourselves so the low priority task can execute + * again. */ + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvLowPriorityPeekTask( void * pvParameters ) +{ + QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters; + uint32_t ulValue; + + for( ; ; ) + { + /* Write some data to the queue. This should unblock the highest + * priority task that is waiting to peek data from the queue. */ + ulValue = 0x11223344; + + if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We were expecting the queue to be empty so we should not of + * had a problem writing to the queue. */ + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* By the time we get here the data should have been removed from + * the queue. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* Write another value to the queue, again waking the highest priority + * task that is blocked on the queue. */ + ulValue = 0x01234567; + + if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We were expecting the queue to be empty so we should not of + * had a problem writing to the queue. */ + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* All the other tasks should now have successfully peeked the data. + * The data is still in the queue so we should be able to receive it. */ + ulValue = 0; + + if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We expected to receive the data. */ + xErrorDetected = pdTRUE; + } + + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + /* Lets just delay a while as this is an intensive test as we don't + * want to starve other tests of processing time. */ + vTaskDelay( qpeekSHORT_DELAY ); + + /* Unsuspend the other tasks so we can repeat the test - this time + * however not all the other tasks will peek the data as the high + * priority task is actually going to remove it from the queue. Send + * to front is used just to be different. As the queue is empty it + * makes no difference to the result. */ + vTaskResume( xMediumPriorityTask ); + vTaskResume( xHighPriorityTask ); + vTaskResume( xHighestPriorityTask ); + + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + ulValue = 0xaabbaabb; + + if( xQueueSendToFront( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We were expecting the queue to be empty so we should not of + * had a problem writing to the queue. */ + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* This time we should find that the queue is empty. The high priority + * task actually removed the data rather than just peeking it. */ + if( xQueuePeek( xQueue, &ulValue, qpeekNO_BLOCK ) != errQUEUE_EMPTY ) + { + /* We expected to receive the data. */ + xErrorDetected = pdTRUE; + } + + /* Unsuspend the highest and high priority tasks so we can go back + * and repeat the whole thing. The medium priority task should not be + * suspended as it was not able to peek the data in this last case. */ + vTaskResume( xHighPriorityTask ); + vTaskResume( xHighestPriorityTask ); + + /* Lets just delay a while as this is an intensive test as we don't + * want to starve other tests of processing time. */ + vTaskDelay( qpeekSHORT_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreQueuePeekTasksStillRunning( void ) +{ + static uint32_t ulLastLoopCounter = 0; + + /* If the demo task is still running then we expect the loopcounter to + * have incremented since this function was last called. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xErrorDetected = pdTRUE; + } + + ulLastLoopCounter = ulLoopCounter; + + /* Errors detected in the task itself will have latched xErrorDetected + * to true. */ + + return ( BaseType_t ) !xErrorDetected; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/QueueOverwrite.c b/SOFTWARE-FreeRTOS/Common/Minimal/QueueOverwrite.c new file mode 100644 index 0000000..7bbb02a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/QueueOverwrite.c @@ -0,0 +1,235 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Basic task to demonstrate the xQueueOverwrite() function. See the comments + * in the function itself. + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "QueueOverwrite.h" + +/* A block time of 0 just means "don't block". */ +#define qoDONT_BLOCK 0 + +/* Number of times to overwrite the value in the queue. */ +#define qoLOOPS 5 + +/* The task that uses the queue. */ +static void prvQueueOverwriteTask( void * pvParameters ); + +/* Variable that is incremented on each loop of prvQueueOverwriteTask() provided + * prvQueueOverwriteTask() has not found any errors. */ +static uint32_t ulLoopCounter = 0; + +/* Set to pdFALSE if an error is discovered by the + * vQueueOverwritePeriodicISRDemo() function. */ +static BaseType_t xISRTestStatus = pdPASS; + +/* The queue that is accessed from the ISR. The queue accessed by the task is + * created inside the task itself. */ +static QueueHandle_t xISRQueue = NULL; + +/*-----------------------------------------------------------*/ + +void vStartQueueOverwriteTask( UBaseType_t uxPriority ) +{ + const UBaseType_t uxQueueLength = 1; + + /* Create the queue used by the ISR. xQueueOverwriteFromISR() should only + * be used on queues that have a length of 1. */ + xISRQueue = xQueueCreate( uxQueueLength, ( UBaseType_t ) sizeof( uint32_t ) ); + + /* Create the test task. The queue used by the test task is created inside + * the task itself. */ + xTaskCreate( prvQueueOverwriteTask, "QOver", configMINIMAL_STACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueOverwriteTask( void * pvParameters ) +{ + QueueHandle_t xTaskQueue; + const UBaseType_t uxQueueLength = 1; + uint32_t ulValue, ulStatus = pdPASS, x; + + /* The parameter is not used. */ + ( void ) pvParameters; + + /* Create the queue. xQueueOverwrite() should only be used on queues that + * have a length of 1. */ + xTaskQueue = xQueueCreate( uxQueueLength, ( UBaseType_t ) sizeof( uint32_t ) ); + configASSERT( xTaskQueue ); + + for( ; ; ) + { + /* The queue is empty. Writing to the queue then reading from the queue + * should return the item written. */ + ulValue = 10; + xQueueOverwrite( xTaskQueue, &ulValue ); + + ulValue = 0; + xQueueReceive( xTaskQueue, &ulValue, qoDONT_BLOCK ); + + if( ulValue != 10 ) + { + ulStatus = pdFAIL; + } + + /* Now try writing to the queue several times. Each time the value + * in the queue should get overwritten. */ + for( x = 0; x < qoLOOPS; x++ ) + { + /* Write to the queue. */ + xQueueOverwrite( xTaskQueue, &x ); + + /* Check the value in the queue is that written, even though the + * queue was not necessarily empty. */ + xQueuePeek( xTaskQueue, &ulValue, qoDONT_BLOCK ); + + if( ulValue != x ) + { + ulStatus = pdFAIL; + } + + /* There should always be one item in the queue. */ + if( uxQueueMessagesWaiting( xTaskQueue ) != uxQueueLength ) + { + ulStatus = pdFAIL; + } + } + + /* Empty the queue again. */ + xQueueReceive( xTaskQueue, &ulValue, qoDONT_BLOCK ); + + if( uxQueueMessagesWaiting( xTaskQueue ) != 0 ) + { + ulStatus = pdFAIL; + } + + if( ulStatus != pdFAIL ) + { + /* Increment a counter to show this task is still running without + * error. */ + ulLoopCounter++; + } + + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsQueueOverwriteTaskStillRunning( void ) +{ + BaseType_t xReturn; + + if( xISRTestStatus != pdPASS ) + { + xReturn = pdFAIL; + } + else if( ulLoopCounter > 0 ) + { + xReturn = pdPASS; + } + else + { + /* The task has either stalled of discovered an error. */ + xReturn = pdFAIL; + } + + ulLoopCounter = 0; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vQueueOverwritePeriodicISRDemo( void ) +{ + static uint32_t ulCallCount = 0; + const uint32_t ulTx1 = 10UL, ulTx2 = 20UL, ulNumberOfSwitchCases = 3UL; + uint32_t ulRx; + + /* This function should be called from an interrupt, such as the tick hook + * function vApplicationTickHook(). */ + + configASSERT( xISRQueue ); + + switch( ulCallCount ) + { + case 0: + + /* The queue is empty. Write ulTx1 to the queue. In this demo the + * last parameter is not used because there are no tasks blocked on + * this queue. */ + xQueueOverwriteFromISR( xISRQueue, &ulTx1, NULL ); + + /* Peek the queue to check it holds the expected value. */ + xQueuePeekFromISR( xISRQueue, &ulRx ); + + if( ulRx != ulTx1 ) + { + xISRTestStatus = pdFAIL; + } + + break; + + case 1: + + /* The queue already holds ulTx1. Overwrite the value in the queue + * with ulTx2. */ + xQueueOverwriteFromISR( xISRQueue, &ulTx2, NULL ); + break; + + case 2: + + /* Read from the queue to empty the queue again. The value read + * should be ulTx2. */ + xQueueReceiveFromISR( xISRQueue, &ulRx, NULL ); + + if( ulRx != ulTx2 ) + { + xISRTestStatus = pdFAIL; + } + + break; + } + + /* Run the next case in the switch statement above next time this function + * is called. */ + ulCallCount++; + + if( ulCallCount >= ulNumberOfSwitchCases ) + { + /* Go back to the start. */ + ulCallCount = 0; + } +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/QueueSet.c b/SOFTWARE-FreeRTOS/Common/Minimal/QueueSet.c new file mode 100644 index 0000000..9bdfb73 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/QueueSet.c @@ -0,0 +1,1160 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Tests the use of queue sets. + * + * A receive task creates a number of queues and adds them to a queue set before + * blocking on the queue set receive. A transmit task and (optionally) an + * interrupt repeatedly unblocks the receive task by sending messages to the + * queues in a pseudo random order. The receive task removes the messages from + * the queues and flags an error if the received message does not match that + * expected. The task sends values in the range 0 to + * queuesetINITIAL_ISR_TX_VALUE, and the ISR sends value in the range + * queuesetINITIAL_ISR_TX_VALUE to ULONG_MAX. + */ + + +/* Standard includes. */ +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "QueueSet.h" + + +#if ( configUSE_QUEUE_SETS == 1 ) /* Remove the tests if queue sets are not defined. */ + + +/* The number of queues that are created and added to the queue set. */ + #define queuesetNUM_QUEUES_IN_SET 3 + +/* The length of each created queue. */ + #define queuesetQUEUE_LENGTH 3 + +/* Block times used in this demo. A block time or 0 means "don't block". */ + #define queuesetSHORT_DELAY 200 + #define queuesetDONT_BLOCK 0 + +/* Messages are sent in incrementing order from both a task and an interrupt. + * The task sends values in the range 0 to 0xfffe, and the interrupt sends values + * in the range of 0xffff to ULONG_MAX. */ + #define queuesetINITIAL_ISR_TX_VALUE 0xffffUL + +/* The priorities used in this demo. */ + #define queuesetLOW_PRIORITY ( tskIDLE_PRIORITY ) + #define queuesetMEDIUM_PRIORITY ( queuesetLOW_PRIORITY + 1 ) + +/* For test purposes the priority of the sending task is changed after every + * queuesetPRIORITY_CHANGE_LOOPS number of values are sent to a queue. */ + #define queuesetPRIORITY_CHANGE_LOOPS ( ( queuesetNUM_QUEUES_IN_SET * queuesetQUEUE_LENGTH ) * 2 ) + +/* The ISR sends to the queue every queuesetISR_TX_PERIOD ticks. */ + #define queuesetISR_TX_PERIOD ( 100UL ) + +/* A delay inserted when the Tx task changes its priority to be above the idle + * task priority to ensure the idle priority tasks get some CPU time before the + * next iteration of the queue set Tx task. */ + #define queuesetTX_LOOP_DELAY pdMS_TO_TICKS( ( TickType_t ) 200 ) + +/* The allowable maximum deviation between a received value and the expected + * received value. A deviation will occur when data is received from a queue + * inside an ISR in between a task receiving from a queue and the task checking + * the received value. */ + #define queuesetALLOWABLE_RX_DEVIATION 3 + +/* Ignore values that are at the boundaries of allowable values to make the + * testing of limits easier (don't have to deal with wrapping values). */ + #define queuesetIGNORED_BOUNDARY ( queuesetALLOWABLE_RX_DEVIATION * 2 ) + + typedef enum + { + eEqualPriority = 0, /* Tx and Rx tasks have the same priority. */ + eTxHigherPriority, /* The priority of the Tx task is above that of the Rx task. */ + eTxLowerPriority /* The priority of the Tx task is below that of the Rx task. */ + } eRelativePriorities; + +/* + * The task that periodically sends to the queue set. + */ + static void prvQueueSetSendingTask( void * pvParameters ); + +/* + * The task that reads from the queue set. + */ + static void prvQueueSetReceivingTask( void * pvParameters ); + +/* + * Check the value received from a queue is the expected value. Some values + * originate from the send task, some values originate from the ISR, with the + * range of the value being used to distinguish between the two message + * sources. + */ + static void prvCheckReceivedValue( uint32_t ulReceived ); + +/* + * For purposes of test coverage, functions that read from and write to a + * queue set from an ISR respectively. + */ + static void prvReceiveFromQueueInSetFromISR( void ); + static void prvSendToQueueInSetFromISR( void ); + +/* + * Create the queues and add them to a queue set before resuming the Tx + * task. + */ + static void prvSetupTest( void ); + +/* + * Checks a value received from a queue falls within the range of expected + * values. + */ + static BaseType_t prvCheckReceivedValueWithinExpectedRange( uint32_t ulReceived, + uint32_t ulExpectedReceived ); + +/* + * Increase test coverage by occasionally change the priorities of the two tasks + * relative to each other. + */ + static void prvChangeRelativePriorities( void ); + +/* + * Queue overwrites can only be performed on queues of length of one, requiring + * a special test function so a queue of length 1 can temporarily be added to a + * set. + */ + static void prvTestQueueOverwriteWithQueueSet( void ); + +/* + * Test the case where two queues within a set are written to with + * xQueueOverwrite(). + */ + static void prvTestQueueOverwriteOnTwoQueuesInQueueSet( void ); + static void prvTestQueueOverwriteFromISROnTwoQueuesInQueueSet( void ); + +/* + * Local pseudo random number seed and return functions. Used to avoid calls + * to the standard library. + */ + static size_t prvRand( void ); + static void prvSRand( size_t uxSeed ); + +/*-----------------------------------------------------------*/ + +/* The queues that are added to the set. */ + static QueueHandle_t xQueues[ queuesetNUM_QUEUES_IN_SET ] = { 0 }; + +/* Counts how many times each queue in the set is used to ensure all the + * queues are used. */ + static uint32_t ulQueueUsedCounter[ queuesetNUM_QUEUES_IN_SET ] = { 0 }; + +/* The handle of the queue set to which the queues are added. */ + static QueueSetHandle_t xQueueSet; + +/* If the prvQueueSetReceivingTask() task has not detected any errors then + * it increments ulCycleCounter on each iteration. + * xAreQueueSetTasksStillRunning() returns pdPASS if the value of + * ulCycleCounter has changed between consecutive calls, and pdFALSE if + * ulCycleCounter has stopped incrementing (indicating an error condition). */ + static volatile uint32_t ulCycleCounter = 0UL; + +/* Set to pdFAIL if an error is detected by any queue set task. + * ulCycleCounter will only be incremented if xQueueSetTasksStatus equals pdPASS. */ + static volatile BaseType_t xQueueSetTasksStatus = pdPASS; + +/* Just a flag to let the function that writes to a queue from an ISR know that + * the queues are setup and can be used. */ + static volatile BaseType_t xSetupComplete = pdFALSE; + +/* The value sent to the queue from the ISR is file scope so the + * xAreQueueSetTasksStillRunning() function can check it is incrementing as + * expected. */ + static volatile uint32_t ulISRTxValue = queuesetINITIAL_ISR_TX_VALUE; + +/* Used by the pseudo random number generator. */ + static size_t uxNextRand = 0; + +/* The task handles are stored so their priorities can be changed. */ + TaskHandle_t xQueueSetSendingTask, xQueueSetReceivingTask; + +/*-----------------------------------------------------------*/ + + void vStartQueueSetTasks( void ) + { + /* Create the tasks. */ + xTaskCreate( prvQueueSetSendingTask, "SetTx", configMINIMAL_STACK_SIZE, NULL, queuesetMEDIUM_PRIORITY, &xQueueSetSendingTask ); + + if( xQueueSetSendingTask != NULL ) + { + xTaskCreate( prvQueueSetReceivingTask, "SetRx", configMINIMAL_STACK_SIZE, ( void * ) xQueueSetSendingTask, queuesetMEDIUM_PRIORITY, &xQueueSetReceivingTask ); + + /* It is important that the sending task does not attempt to write to a + * queue before the queue has been created. It is therefore placed into + * the suspended state before the scheduler has started. It is resumed by + * the receiving task after the receiving task has created the queues and + * added the queues to the queue set. */ + vTaskSuspend( xQueueSetSendingTask ); + } + } +/*-----------------------------------------------------------*/ + + BaseType_t xAreQueueSetTasksStillRunning( void ) + { + static uint32_t ulLastCycleCounter, ulLastISRTxValue = 0; + static uint32_t ulLastQueueUsedCounter[ queuesetNUM_QUEUES_IN_SET ] = { 0 }; + BaseType_t xReturn = pdPASS, x; + + if( ulLastCycleCounter == ulCycleCounter ) + { + /* The cycle counter is no longer being incremented. Either one of the + * tasks is stalled or an error has been detected. */ + xReturn = pdFAIL; + } + + ulLastCycleCounter = ulCycleCounter; + + /* Ensure that all the queues in the set have been used. This ensures the + * test is working as intended and guards against the rand() in the Tx task + * missing some values. */ + for( x = 0; x < queuesetNUM_QUEUES_IN_SET; x++ ) + { + if( ulLastQueueUsedCounter[ x ] == ulQueueUsedCounter[ x ] ) + { + xReturn = pdFAIL; + } + + ulLastQueueUsedCounter[ x ] = ulQueueUsedCounter[ x ]; + } + + /* Check the global status flag. */ + if( xQueueSetTasksStatus != pdPASS ) + { + xReturn = pdFAIL; + } + + /* Check that the ISR is still sending values to the queues too. */ + if( ulISRTxValue == ulLastISRTxValue ) + { + xReturn = pdFAIL; + } + else + { + ulLastISRTxValue = ulISRTxValue; + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + static void prvQueueSetSendingTask( void * pvParameters ) + { + uint32_t ulTaskTxValue = 0; + size_t uxQueueToWriteTo; + QueueHandle_t xQueueInUse; + + /* Remove compiler warning about the unused parameter. */ + ( void ) pvParameters; + + /* Seed mini pseudo random number generator. */ + prvSRand( ( size_t ) &ulTaskTxValue ); + + for( ; ; ) + { + /* Generate the index for the queue to which a value is to be sent. */ + uxQueueToWriteTo = prvRand() % queuesetNUM_QUEUES_IN_SET; + xQueueInUse = xQueues[ uxQueueToWriteTo ]; + + /* Note which index is being written to to ensure all the queues are + * used. */ + ( ulQueueUsedCounter[ uxQueueToWriteTo ] )++; + + /* Send to the queue to unblock the task that is waiting for data to + * arrive on a queue within the queue set to which this queue belongs. */ + if( xQueueSendToBack( xQueueInUse, &ulTaskTxValue, portMAX_DELAY ) != pdPASS ) + { + /* The send should always pass as an infinite block time was + * used. */ + xQueueSetTasksStatus = pdFAIL; + } + + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + ulTaskTxValue++; + + /* If the Tx value has reached the range used by the ISR then set it + * back to 0. */ + if( ulTaskTxValue == queuesetINITIAL_ISR_TX_VALUE ) + { + ulTaskTxValue = 0; + } + + /* Increase test coverage by occasionally change the priorities of the + * two tasks relative to each other. */ + prvChangeRelativePriorities(); + } + } +/*-----------------------------------------------------------*/ + + static void prvChangeRelativePriorities( void ) + { + static UBaseType_t ulLoops = 0; + static eRelativePriorities ePriorities = eEqualPriority; + + /* Occasionally change the task priority relative to the priority of + * the receiving task. */ + ulLoops++; + + if( ulLoops >= queuesetPRIORITY_CHANGE_LOOPS ) + { + ulLoops = 0; + + switch( ePriorities ) + { + case eEqualPriority: + + /* Both tasks are running with medium priority. Now lower the + * priority of the receiving task so the Tx task has the higher + * relative priority. */ + vTaskPrioritySet( xQueueSetReceivingTask, queuesetLOW_PRIORITY ); + ePriorities = eTxHigherPriority; + break; + + case eTxHigherPriority: + + /* The Tx task is running with a higher priority than the Rx + * task. Switch the priorities around so the Rx task has the + * higher relative priority. */ + vTaskPrioritySet( xQueueSetReceivingTask, queuesetMEDIUM_PRIORITY ); + vTaskPrioritySet( xQueueSetSendingTask, queuesetLOW_PRIORITY ); + ePriorities = eTxLowerPriority; + break; + + case eTxLowerPriority: + + /* The Tx task is running with a lower priority than the Rx + * task. Make the priorities equal again. */ + vTaskPrioritySet( xQueueSetSendingTask, queuesetMEDIUM_PRIORITY ); + ePriorities = eEqualPriority; + + /* When both tasks are using a non-idle priority the queue set + * tasks will starve idle priority tasks of execution time - so + * relax a bit before the next iteration to minimise the impact. */ + vTaskDelay( queuesetTX_LOOP_DELAY ); + + break; + } + } + } +/*-----------------------------------------------------------*/ + + static void prvQueueSetReceivingTask( void * pvParameters ) + { + uint32_t ulReceived; + QueueHandle_t xActivatedQueue; + TickType_t xBlockTime; + + /* Remove compiler warnings. */ + ( void ) pvParameters; + + /* Create the queues and add them to the queue set before resuming the Tx + * task. */ + prvSetupTest(); + + for( ; ; ) + { + /* For test coverage reasons, the block time is dependent on the + * priority of this task - which changes during the test. When the task + * is at the idle priority it polls the queue set. */ + if( uxTaskPriorityGet( NULL ) == tskIDLE_PRIORITY ) + { + xBlockTime = 0; + } + else + { + xBlockTime = portMAX_DELAY; + } + + /* Wait for a message to arrive on one of the queues in the set. */ + xActivatedQueue = xQueueSelectFromSet( xQueueSet, portMAX_DELAY ); + + if( xActivatedQueue == NULL ) + { + if( xBlockTime != 0 ) + { + /* This should not happen as an infinite delay was used. */ + xQueueSetTasksStatus = pdFAIL; + } + } + else + { + /* Reading from the queue should pass with a zero block time as + * this task will only run when something has been posted to a task + * in the queue set. */ + if( xQueueReceive( xActivatedQueue, &ulReceived, queuesetDONT_BLOCK ) != pdPASS ) + { + xQueueSetTasksStatus = pdFAIL; + } + + /* Ensure the value received was the value expected. This function + * manipulates file scope data and is also called from an ISR, hence + * the critical section. */ + taskENTER_CRITICAL(); + { + prvCheckReceivedValue( ulReceived ); + } + taskEXIT_CRITICAL(); + + if( xQueueSetTasksStatus == pdPASS ) + { + ulCycleCounter++; + } + } + } + } +/*-----------------------------------------------------------*/ + + void vQueueSetAccessQueueSetFromISR( void ) + { + static uint32_t ulCallCount = 0; + + /* xSetupComplete is set to pdTRUE when the queues have been created and + * are available for use. */ + if( xSetupComplete == pdTRUE ) + { + /* It is intended that this function is called from the tick hook + * function, so each call is one tick period apart. */ + ulCallCount++; + + if( ulCallCount > queuesetISR_TX_PERIOD ) + { + ulCallCount = 0; + + /* First attempt to read from the queue set. */ + prvReceiveFromQueueInSetFromISR(); + + /* Then write to the queue set. */ + prvSendToQueueInSetFromISR(); + } + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckReceivedValue( uint32_t ulReceived ) + { + static uint32_t ulExpectedReceivedFromTask = 0, ulExpectedReceivedFromISR = queuesetINITIAL_ISR_TX_VALUE; + + /* Values are received in tasks and interrupts. It is likely that the + * receiving task will sometimes get preempted by the receiving interrupt + * between reading a value from the queue and calling this function. When + * that happens, if the receiving interrupt calls this function the values + * will get passed into this function slightly out of order. For that + * reason the value passed in is tested against a small range of expected + * values, rather than a single absolute value. To make the range testing + * easier values in the range limits are ignored. */ + + /* If the received value is equal to or greater than + * queuesetINITIAL_ISR_TX_VALUE then it was sent by an ISR. */ + if( ulReceived >= queuesetINITIAL_ISR_TX_VALUE ) + { + /* The value was sent from the ISR. */ + if( ( ulReceived - queuesetINITIAL_ISR_TX_VALUE ) < queuesetIGNORED_BOUNDARY ) + { + /* The value received is at the lower limit of the expected range. + * Don't test it and expect to receive one higher next time. */ + } + else if( ( ULONG_MAX - ulReceived ) <= queuesetIGNORED_BOUNDARY ) + { + /* The value received is at the higher limit of the expected range. + * Don't test it and expect to wrap soon. */ + } + else + { + /* Check the value against its expected value range. */ + if( prvCheckReceivedValueWithinExpectedRange( ulReceived, ulExpectedReceivedFromISR ) != pdPASS ) + { + xQueueSetTasksStatus = pdFAIL; + } + } + + configASSERT( xQueueSetTasksStatus ); + + /* It is expected to receive an incrementing number. */ + ulExpectedReceivedFromISR++; + + if( ulExpectedReceivedFromISR == 0 ) + { + ulExpectedReceivedFromISR = queuesetINITIAL_ISR_TX_VALUE; + } + } + else + { + /* The value was sent from the Tx task. */ + if( ulReceived < queuesetIGNORED_BOUNDARY ) + { + /* The value received is at the lower limit of the expected range. + * Don't test it, and expect to receive one higher next time. */ + } + else if( ( ( queuesetINITIAL_ISR_TX_VALUE - 1 ) - ulReceived ) <= queuesetIGNORED_BOUNDARY ) + { + /* The value received is at the higher limit of the expected range. + * Don't test it and expect to wrap soon. */ + } + else + { + /* Check the value against its expected value range. */ + if( prvCheckReceivedValueWithinExpectedRange( ulReceived, ulExpectedReceivedFromTask ) != pdPASS ) + { + xQueueSetTasksStatus = pdFAIL; + } + } + + configASSERT( xQueueSetTasksStatus ); + + /* It is expected to receive an incrementing number. */ + ulExpectedReceivedFromTask++; + + if( ulExpectedReceivedFromTask >= queuesetINITIAL_ISR_TX_VALUE ) + { + ulExpectedReceivedFromTask = 0; + } + } + } +/*-----------------------------------------------------------*/ + + static BaseType_t prvCheckReceivedValueWithinExpectedRange( uint32_t ulReceived, + uint32_t ulExpectedReceived ) + { + BaseType_t xReturn = pdPASS; + + if( ulReceived > ulExpectedReceived ) + { + configASSERT( ( ulReceived - ulExpectedReceived ) <= queuesetALLOWABLE_RX_DEVIATION ); + + if( ( ulReceived - ulExpectedReceived ) > queuesetALLOWABLE_RX_DEVIATION ) + { + xReturn = pdFALSE; + } + } + else + { + configASSERT( ( ulExpectedReceived - ulReceived ) <= queuesetALLOWABLE_RX_DEVIATION ); + + if( ( ulExpectedReceived - ulReceived ) > queuesetALLOWABLE_RX_DEVIATION ) + { + xReturn = pdFALSE; + } + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + static void prvReceiveFromQueueInSetFromISR( void ) + { + QueueSetMemberHandle_t xActivatedQueue; + uint32_t ulReceived; + + /* See if any of the queues in the set contain data. */ + xActivatedQueue = xQueueSelectFromSetFromISR( xQueueSet ); + + if( xActivatedQueue != NULL ) + { + /* Reading from the queue for test purposes only. */ + if( xQueueReceiveFromISR( xActivatedQueue, &ulReceived, NULL ) != pdPASS ) + { + /* Data should have been available as the handle was returned from + * xQueueSelectFromSetFromISR(). */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Ensure the value received was the value expected. */ + prvCheckReceivedValue( ulReceived ); + } + } +/*-----------------------------------------------------------*/ + + static void prvSendToQueueInSetFromISR( void ) + { + static BaseType_t xQueueToWriteTo = 0; + uint32_t ulTxValueSnapshot = ulISRTxValue; + + if( xQueueSendFromISR( xQueues[ xQueueToWriteTo ], ( void * ) &ulTxValueSnapshot, NULL ) == pdPASS ) + { + ulISRTxValue++; + + /* If the Tx value has wrapped then set it back to its initial value. */ + if( ulISRTxValue == 0UL ) + { + ulISRTxValue = queuesetINITIAL_ISR_TX_VALUE; + } + + /* Use a different queue next time. */ + xQueueToWriteTo++; + + if( xQueueToWriteTo >= queuesetNUM_QUEUES_IN_SET ) + { + xQueueToWriteTo = 0; + } + } + } +/*-----------------------------------------------------------*/ + + static void prvTestQueueOverwriteWithQueueSet( void ) + { + uint32_t ulValueToSend = 0, ulValueReceived = 0; + QueueHandle_t xQueueHandle = NULL, xReceivedHandle = NULL; + const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1; + + /* Create a queue that has a length of one - a requirement in order to call + * xQueueOverwrite. This will get deleted again when this test completes. */ + xQueueHandle = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle ); + + if( xQueueHandle != NULL ) + { + xQueueAddToSet( xQueueHandle, xQueueSet ); + + /* Add an item to the queue then ensure the queue set correctly + * indicates that one item is available, and that item is indeed the + * queue written to. */ + xQueueOverwrite( xQueueHandle, ( void * ) &ulValueToSend ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* Expected one item in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + * held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Now overwrite the value in the queue and ensure the queue set state + * doesn't change as the number of items in the queues within the set have + * not changed. */ + ulValueToSend++; + xQueueOverwrite( xQueueHandle, ( void * ) &ulValueToSend ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* Still expected one item in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + * held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Also ensure the value received from the queue is the overwritten + * value, not the value originally written. */ + xQueueReceive( xQueueHandle, &ulValueReceived, queuesetDONT_BLOCK ); + + if( ulValueReceived != ulValueToSend ) + { + /* Unexpected value received from the queue. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Should be anything in the queue set now. */ + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 ) + { + xQueueSetTasksStatus = pdFAIL; + } + + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + + if( xReceivedHandle != NULL ) + { + xQueueSetTasksStatus = pdFAIL; + } + + /* Clean up. */ + xQueueRemoveFromSet( xQueueHandle, xQueueSet ); + vQueueDelete( xQueueHandle ); + } + } +/*-----------------------------------------------------------*/ + + static void prvTestQueueOverwriteOnTwoQueuesInQueueSet( void ) + { + uint32_t ulValueToSend1 = 1, ulValueToSend2 = 2UL, ulValueReceived = 0; + QueueHandle_t xQueueHandle1 = NULL, xQueueHandle2 = NULL, xReceivedHandle = NULL; + const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1; + + /* Create two queues that have a length of one - a requirement in order to call + * xQueueOverwrite. These will get deleted again when this test completes. */ + xQueueHandle1 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle1 ); + xQueueHandle2 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle2 ); + + if( ( xQueueHandle1 != NULL ) && ( xQueueHandle2 != NULL ) ) + { + /* Add both queues to the queue set. */ + xQueueAddToSet( xQueueHandle1, xQueueSet ); + xQueueAddToSet( xQueueHandle2, xQueueSet ); + + /* Add an item using the first queue. */ + xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend1 ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* Expected one item in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + * held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Next add an item to the second queue. */ + xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend2 ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* The head of the queue set should not have changed though. */ + xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + * held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Now overwrite the value in the queue and ensure the queue set state + * doesn't change as the number of items in the queues within the set have + * not changed. NOTE: after this queue 1 should hold ulValueToSend2 and queue + * 2 should hold the value ulValueToSend1. */ + xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend2 ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend1 ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Repeat the above to ensure the queue set state doesn't change. */ + xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend2 ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend1 ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Now when reading from the queue set we expect the handle to the first + * queue to be received first, and for that queue to hold ulValueToSend2 as the + * originally written value was overwritten. Likewise the second handle received + * from the set should be that of the second queue, and that queue should hold + * ulValueToSend1 as the originally written value was overwritten. */ + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle1 first so expected that handle to be read from + * the set first. */ + xQueueSetTasksStatus = pdFAIL; + } + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* One value was read from the set, so now only expect a single value + * in the set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK ); + + if( ulValueReceived != ulValueToSend2 ) + { + /* Unexpected value received from the queue. ulValueToSend1 was written + * first, but then overwritten with ulValueToSend2; */ + xQueueSetTasksStatus = pdFAIL; + } + + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle2 ) + { + /* xQueueHandle1 has already been removed from the set so expect only + * xQueueHandle2 to be left. */ + xQueueSetTasksStatus = pdFAIL; + } + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 ) + { + /* The last value was read from the set so don't expect any more. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK ); + + if( ulValueReceived != ulValueToSend1 ) + { + /* Unexpected value received from the queue. ulValueToSend2 was written + * first, but then overwritten with ulValueToSend1. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Should be anything in the queue set now. */ + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + + if( xReceivedHandle != NULL ) + { + xQueueSetTasksStatus = pdFAIL; + } + + /* Clean up. */ + xQueueRemoveFromSet( xQueueHandle1, xQueueSet ); + xQueueRemoveFromSet( xQueueHandle2, xQueueSet ); + vQueueDelete( xQueueHandle1 ); + vQueueDelete( xQueueHandle2 ); + } + } +/*-----------------------------------------------------------*/ + + static void prvTestQueueOverwriteFromISROnTwoQueuesInQueueSet( void ) + { + uint32_t ulValueToSend1 = 1, ulValueToSend2 = 2UL, ulValueReceived = 0; + QueueHandle_t xQueueHandle1 = NULL, xQueueHandle2 = NULL, xReceivedHandle = NULL; + const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1; + + /* Create two queues that have a length of one - a requirement in order to call + * xQueueOverwrite. These will get deleted again when this test completes. */ + xQueueHandle1 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle1 ); + xQueueHandle2 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle2 ); + + if( ( xQueueHandle1 != NULL ) && ( xQueueHandle2 != NULL ) ) + { + /* Add both queues to the queue set. */ + xQueueAddToSet( xQueueHandle1, xQueueSet ); + xQueueAddToSet( xQueueHandle2, xQueueSet ); + + /* Add an item using the first queue using the 'FromISR' version of the + * overwrite function. */ + xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend1, NULL ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* Expected one item in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + * held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Next add an item to the second queue using the 'FromISR' version of the + * overwrite function. */ + xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend2, NULL ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* The head of the queue set should not have changed though. */ + xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + * held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Now overwrite the value in the queue and ensure the queue set state + * doesn't change as the number of items in the queues within the set have + * not changed. NOTE: after this queue 1 should hold ulValueToSend2 and queue + * 2 should hold the value ulValueToSend1. */ + xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend2, NULL ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend1, NULL ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Repeat the above to ensure the queue set state doesn't change. */ + xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend2, NULL ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend1, NULL ); + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Now when reading from the queue set we expect the handle to the first + * queue to be received first, and for that queue to hold ulValueToSend2 as the + * originally written value was overwritten. Likewise the second handle received + * from the set should be that of the second queue, and that queue should hold + * ulValueToSend1 as the originally written value was overwritten. */ + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle1 first so expected that handle to be read from + * the set first. */ + xQueueSetTasksStatus = pdFAIL; + } + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* One value was read from the set, so now only expect a single value + * in the set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK ); + + if( ulValueReceived != ulValueToSend2 ) + { + /* Unexpected value received from the queue. ulValueToSend1 was written + * first, but then overwritten with ulValueToSend2; */ + xQueueSetTasksStatus = pdFAIL; + } + + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + + if( xReceivedHandle != xQueueHandle2 ) + { + /* xQueueHandle1 has already been removed from the set so expect only + * xQueueHandle2 to be left. */ + xQueueSetTasksStatus = pdFAIL; + } + + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 ) + { + /* The last value was read from the set so don't expect any more. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK ); + + if( ulValueReceived != ulValueToSend1 ) + { + /* Unexpected value received from the queue. ulValueToSend2 was written + * first, but then overwritten with ulValueToSend1. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Should be anything in the queue set now. */ + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + + if( xReceivedHandle != NULL ) + { + xQueueSetTasksStatus = pdFAIL; + } + + /* Clean up. */ + xQueueRemoveFromSet( xQueueHandle1, xQueueSet ); + xQueueRemoveFromSet( xQueueHandle2, xQueueSet ); + vQueueDelete( xQueueHandle1 ); + vQueueDelete( xQueueHandle2 ); + } + } +/*-----------------------------------------------------------*/ + + static void prvSetupTest( void ) + { + BaseType_t x; + uint32_t ulValueToSend = 0; + + /* Ensure the queues are created and the queue set configured before the + * sending task is unsuspended. + * + * First Create the queue set such that it will be able to hold a message for + * every space in every queue in the set. */ + xQueueSet = xQueueCreateSet( queuesetNUM_QUEUES_IN_SET * queuesetQUEUE_LENGTH ); + + for( x = 0; x < queuesetNUM_QUEUES_IN_SET; x++ ) + { + /* Create the queue and add it to the set. The queue is just holding + * uint32_t value. */ + xQueues[ x ] = xQueueCreate( queuesetQUEUE_LENGTH, sizeof( uint32_t ) ); + configASSERT( xQueues[ x ] ); + + if( xQueueAddToSet( xQueues[ x ], xQueueSet ) != pdPASS ) + { + xQueueSetTasksStatus = pdFAIL; + } + else + { + /* The queue has now been added to the queue set and cannot be added to + * another. */ + if( xQueueAddToSet( xQueues[ x ], xQueueSet ) != pdFAIL ) + { + xQueueSetTasksStatus = pdFAIL; + } + } + } + + /* Attempt to remove a queue from a queue set it does not belong + * to (NULL being passed as the queue set in this case). */ + if( xQueueRemoveFromSet( xQueues[ 0 ], NULL ) != pdFAIL ) + { + /* It is not possible to successfully remove a queue from a queue + * set it does not belong to. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Attempt to remove a queue from the queue set it does belong to. */ + if( xQueueRemoveFromSet( xQueues[ 0 ], xQueueSet ) != pdPASS ) + { + /* It should be possible to remove the queue from the queue set it + * does belong to. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Add an item to the queue before attempting to add it back into the + * set. */ + xQueueSend( xQueues[ 0 ], ( void * ) &ulValueToSend, 0 ); + + if( xQueueAddToSet( xQueues[ 0 ], xQueueSet ) != pdFAIL ) + { + /* Should not be able to add a non-empty queue to a set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Remove the item from the queue before adding the queue back into the + * set so the dynamic tests can begin. */ + xQueueReceive( xQueues[ 0 ], &ulValueToSend, 0 ); + + if( xQueueAddToSet( xQueues[ 0 ], xQueueSet ) != pdPASS ) + { + /* If the queue was successfully removed from the queue set then it + * should be possible to add it back in again. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* The task that sends to the queues is not running yet, so attempting to + * read from the queue set should fail. */ + if( xQueueSelectFromSet( xQueueSet, queuesetSHORT_DELAY ) != NULL ) + { + xQueueSetTasksStatus = pdFAIL; + } + + /* Testing the behaviour of queue sets when a queue overwrite operation is + * performed on a set member requires a special test as overwrites can only + * be performed on queues that have a length of 1. */ + prvTestQueueOverwriteWithQueueSet(); + + /* Test the case where two queues within a set are written to with + * xQueueOverwrite(). */ + prvTestQueueOverwriteOnTwoQueuesInQueueSet(); + prvTestQueueOverwriteFromISROnTwoQueuesInQueueSet(); + + /* In case any of the above have already indicated a failure. */ + configASSERT( xQueueSetTasksStatus != pdFAIL ); + + /* Resume the task that writes to the queues. */ + vTaskResume( xQueueSetSendingTask ); + + /* Let the ISR access the queues also. */ + xSetupComplete = pdTRUE; + } +/*-----------------------------------------------------------*/ + + static size_t prvRand( void ) + { + uxNextRand = ( uxNextRand * ( size_t ) 1103515245 ) + ( size_t ) 12345; + return ( uxNextRand / ( size_t ) 65536 ) % ( size_t ) 32768; + } +/*-----------------------------------------------------------*/ + + static void prvSRand( size_t uxSeed ) + { + uxNextRand = uxSeed; + } + +#endif /* ( configUSE_QUEUE_SETS == 1 ) */ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/QueueSetPolling.c b/SOFTWARE-FreeRTOS/Common/Minimal/QueueSetPolling.c new file mode 100644 index 0000000..cfed766 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/QueueSetPolling.c @@ -0,0 +1,182 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Tests the use of queue sets. + * + * A receive task creates a number of queues and adds them to a queue set before + * blocking on the queue set receive. A transmit task and (optionally) an + * interrupt repeatedly unblocks the receive task by sending messages to the + * queues in a pseudo random order. The receive task removes the messages from + * the queues and flags an error if the received message does not match that + * expected. The task sends values in the range 0 to + * queuesetINITIAL_ISR_TX_VALUE, and the ISR sends value in the range + * queuesetINITIAL_ISR_TX_VALUE to ULONG_MAX. + */ + + +/* Standard includes. */ +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "QueueSetPolling.h" + +#if ( configUSE_QUEUE_SETS == 1 ) /* Remove tests if queue sets are not defined. */ + +/* The length of each created queue. */ + #define setpollQUEUE_LENGTH 10 + +/* Block times used in this demo. A block time or 0 means "don't block". */ + #define setpollDONT_BLOCK 0 + +/* The ISR sends to the queue every setpollISR_TX_PERIOD ticks. */ + #define queuesetISR_TX_PERIOD ( 50UL ) + +/* + * The task that reads from the queue set. + */ + static void prvQueueSetReceivingTask( void * pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue that is added to the set. */ + static QueueHandle_t xQueue = NULL; + +/* The handle of the queue set to which the queue is added. */ + static QueueSetHandle_t xQueueSet = NULL; + +/* Set to pdFAIL if an error is detected by any queue set task. + * ulCycleCounter will only be incremented if xQueueSetTasksStatus equals pdPASS. */ + static volatile BaseType_t xQueueSetPollStatus = pdPASS; + +/* Counter used to ensure the task is still running. */ + static uint32_t ulCycleCounter = 0; + +/*-----------------------------------------------------------*/ + + void vStartQueueSetPollingTask( void ) + { + /* Create the queue that is added to the set, the set, and add the queue to + * the set. */ + xQueue = xQueueCreate( setpollQUEUE_LENGTH, sizeof( uint32_t ) ); + xQueueSet = xQueueCreateSet( setpollQUEUE_LENGTH ); + + if( ( xQueue != NULL ) && ( xQueueSet != NULL ) ) + { + xQueueAddToSet( xQueue, xQueueSet ); + + /* Create the task. */ + xTaskCreate( prvQueueSetReceivingTask, "SetPoll", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + } + } +/*-----------------------------------------------------------*/ + + static void prvQueueSetReceivingTask( void * pvParameters ) + { + uint32_t ulReceived, ulExpected = 0; + QueueHandle_t xActivatedQueue; + + /* Remove compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Is a message waiting? A block time is not used to ensure the queue + * set is polled while it is being written to from an interrupt. */ + xActivatedQueue = xQueueSelectFromSet( xQueueSet, setpollDONT_BLOCK ); + + if( xActivatedQueue != NULL ) + { + /* Reading from the queue should pass with a zero block time as + * this task will only run when something has been posted to a task + * in the queue set. */ + if( xQueueReceive( xActivatedQueue, &ulReceived, setpollDONT_BLOCK ) != pdPASS ) + { + xQueueSetPollStatus = pdFAIL; + } + + if( ulReceived == ulExpected ) + { + ulExpected++; + } + else + { + xQueueSetPollStatus = pdFAIL; + } + + if( xQueueSetPollStatus == pdPASS ) + { + ulCycleCounter++; + } + } + } + } +/*-----------------------------------------------------------*/ + + void vQueueSetPollingInterruptAccess( void ) + { + static uint32_t ulCallCount = 0, ulValueToSend = 0; + + /* It is intended that this function is called from the tick hook + * function, so each call is one tick period apart. */ + ulCallCount++; + + if( ulCallCount > queuesetISR_TX_PERIOD ) + { + ulCallCount = 0; + + if( xQueueSendFromISR( xQueue, ( void * ) &ulValueToSend, NULL ) == pdPASS ) + { + /* Send the next value next time. */ + ulValueToSend++; + } + } + } +/*-----------------------------------------------------------*/ + + BaseType_t xAreQueueSetPollTasksStillRunning( void ) + { + static uint32_t ulLastCycleCounter = 0; + + if( ulLastCycleCounter == ulCycleCounter ) + { + xQueueSetPollStatus = pdFAIL; + } + + ulLastCycleCounter = ulCycleCounter; + + return xQueueSetPollStatus; + } +/*-----------------------------------------------------------*/ + + +#endif /* ( configUSE_QUEUE_SETS == 1 ) */ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/StaticAllocation.c b/SOFTWARE-FreeRTOS/Common/Minimal/StaticAllocation.c new file mode 100644 index 0000000..0cc08d9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/StaticAllocation.c @@ -0,0 +1,1113 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Demonstrates how to create FreeRTOS objects using pre-allocated memory, + * rather than the normal dynamically allocated memory, and tests objects being + * created and deleted with both statically allocated memory and dynamically + * allocated memory. + * + * See http://www.FreeRTOS.org/Static_Vs_Dynamic_Memory_Allocation.html + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" +#include "event_groups.h" +#include "timers.h" + +/* Demo program include files. */ +#include "StaticAllocation.h" + +/* Exclude the entire file if configSUPPORT_STATIC_ALLOCATION is 0. */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/* The priority at which the task that performs the tests is created. */ + #define staticTASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* The length of the queue, in items, not bytes, used in the queue static + * allocation tests. */ + #define staticQUEUE_LENGTH_IN_ITEMS ( 5 ) + +/* A block time of 0 simply means "don't block". */ + #define staticDONT_BLOCK ( ( TickType_t ) 0 ) + +/* Binary semaphores have a maximum count of 1. */ + #define staticBINARY_SEMAPHORE_MAX_COUNT ( 1 ) + +/* The size of the stack used by the task that runs the tests. */ + #define staticCREATOR_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) + +/* The number of times the software timer will execute before stopping itself. */ + #define staticMAX_TIMER_CALLBACK_EXECUTIONS ( 5 ) + + +/*-----------------------------------------------------------*/ + +/* + * The task that repeatedly creates and deletes statically allocated tasks, and + * other RTOS objects. + */ + static void prvStaticallyAllocatedCreator( void * pvParameters ); + +/* + * The callback function used by the software timer that is repeatedly created + * and deleted using both static and dynamically allocated memory. + */ + static void prvTimerCallback( TimerHandle_t xExpiredTimer ); + +/* + * A task that is created and deleted multiple times, using both statically and + * dynamically allocated stack and TCB. + */ + static void prvStaticallyAllocatedTask( void * pvParameters ); + +/* + * A function that demonstrates and tests the API functions that create and + * delete tasks using both statically and dynamically allocated TCBs and stacks. + */ + static void prvCreateAndDeleteStaticallyAllocatedTasks( void ); + +/* + * A function that demonstrates and tests the API functions that create and + * delete event groups using both statically and dynamically allocated RAM. + */ + static void prvCreateAndDeleteStaticallyAllocatedEventGroups( void ); + +/* + * A function that demonstrates and tests the API functions that create and + * delete queues using both statically and dynamically allocated RAM. + */ + static void prvCreateAndDeleteStaticallyAllocatedQueues( void ); + +/* + * A function that demonstrates and tests the API functions that create and + * delete binary semaphores using both statically and dynamically allocated RAM. + */ + static void prvCreateAndDeleteStaticallyAllocatedBinarySemaphores( void ); + +/* + * A function that demonstrates and tests the API functions that create and + * delete software timers using both statically and dynamically allocated RAM. + */ + static void prvCreateAndDeleteStaticallyAllocatedTimers( void ); + +/* + * A function that demonstrates and tests the API functions that create and + * delete mutexes using both statically and dynamically allocated RAM. + */ + static void prvCreateAndDeleteStaticallyAllocatedMutexes( void ); + +/* + * A function that demonstrates and tests the API functions that create and + * delete counting semaphores using both statically and dynamically allocated + * RAM. + */ + static void prvCreateAndDeleteStaticallyAllocatedCountingSemaphores( void ); + +/* + * A function that demonstrates and tests the API functions that create and + * delete recursive mutexes using both statically and dynamically allocated RAM. + */ + static void prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes( void ); + +/* + * Utility function to create pseudo random numbers. + */ + static UBaseType_t prvRand( void ); + +/* + * The task that creates and deletes other tasks has to delay occasionally to + * ensure lower priority tasks are not starved of processing time. A pseudo + * random delay time is used just to add a little bit of randomisation into the + * execution pattern. prvGetNextDelayTime() generates the pseudo random delay. + */ + static TickType_t prvGetNextDelayTime( void ); + +/* + * Checks the basic operation of a queue after it has been created. + */ + static void prvSanityCheckCreatedQueue( QueueHandle_t xQueue ); + +/* + * Checks the basic operation of a recursive mutex after it has been created. + */ + static void prvSanityCheckCreatedRecursiveMutex( SemaphoreHandle_t xSemaphore ); + +/* + * Checks the basic operation of a binary semaphore after it has been created. + */ + static void prvSanityCheckCreatedSemaphore( SemaphoreHandle_t xSemaphore, + UBaseType_t uxMaxCount ); + +/* + * Checks the basic operation of an event group after it has been created. + */ + static void prvSanityCheckCreatedEventGroup( EventGroupHandle_t xEventGroup ); + +/*-----------------------------------------------------------*/ + +/* StaticTask_t is a publicly accessible structure that has the same size and + * alignment requirements as the real TCB structure. It is provided as a mechanism + * for applications to know the size of the TCB (which is dependent on the + * architecture and configuration file settings) without breaking the strict data + * hiding policy by exposing the real TCB. This StaticTask_t variable is passed + * into the xTaskCreateStatic() function that creates the + * prvStaticallyAllocatedCreator() task, and will hold the TCB of the created + * tasks. */ + static StaticTask_t xCreatorTaskTCBBuffer; + +/* This is the stack that will be used by the prvStaticallyAllocatedCreator() + * task, which is itself created using statically allocated buffers (so without any + * dynamic memory allocation). */ + static StackType_t uxCreatorTaskStackBuffer[ staticCREATOR_TASK_STACK_SIZE ]; + +/* Used by the pseudo random number generating function. */ + static uint32_t ulNextRand = 0; + +/* Used so a check task can ensure this test is still executing, and not + * stalled. */ + static volatile UBaseType_t uxCycleCounter = 0; + +/* A variable that gets set to pdTRUE if an error is detected. */ + static volatile BaseType_t xErrorOccurred = pdFALSE; + +/*-----------------------------------------------------------*/ + + void vStartStaticallyAllocatedTasks( void ) + { + /* Create a single task, which then repeatedly creates and deletes the other + * RTOS objects using both statically and dynamically allocated RAM. */ + xTaskCreateStatic( prvStaticallyAllocatedCreator, /* The function that implements the task being created. */ + "StatCreate", /* Text name for the task - not used by the RTOS, its just to assist debugging. */ + staticCREATOR_TASK_STACK_SIZE, /* Size of the buffer passed in as the stack - in words, not bytes! */ + NULL, /* Parameter passed into the task - not used in this case. */ + staticTASK_PRIORITY, /* Priority of the task. */ + &( uxCreatorTaskStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */ + &xCreatorTaskTCBBuffer ); /* The variable that will hold the task's TCB. */ + } +/*-----------------------------------------------------------*/ + + static void prvStaticallyAllocatedCreator( void * pvParameters ) + { + /* Avoid compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Loop, running functions that create and delete the various RTOS + * objects that can be optionally created using either static or dynamic + * memory allocation. */ + prvCreateAndDeleteStaticallyAllocatedTasks(); + prvCreateAndDeleteStaticallyAllocatedQueues(); + + /* Delay to ensure lower priority tasks get CPU time, and increment the + * cycle counter so a 'check' task can determine that this task is still + * executing. */ + vTaskDelay( prvGetNextDelayTime() ); + uxCycleCounter++; + + prvCreateAndDeleteStaticallyAllocatedBinarySemaphores(); + prvCreateAndDeleteStaticallyAllocatedCountingSemaphores(); + + vTaskDelay( prvGetNextDelayTime() ); + uxCycleCounter++; + + prvCreateAndDeleteStaticallyAllocatedMutexes(); + prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes(); + + vTaskDelay( prvGetNextDelayTime() ); + uxCycleCounter++; + + prvCreateAndDeleteStaticallyAllocatedEventGroups(); + prvCreateAndDeleteStaticallyAllocatedTimers(); + } + } +/*-----------------------------------------------------------*/ + + static void prvCreateAndDeleteStaticallyAllocatedCountingSemaphores( void ) + { + SemaphoreHandle_t xSemaphore; + const UBaseType_t uxMaxCount = ( UBaseType_t ) 10; + +/* StaticSemaphore_t is a publicly accessible structure that has the same size + * and alignment requirements as the real semaphore structure. It is provided as a + * mechanism for applications to know the size of the semaphore (which is dependent + * on the architecture and configuration file settings) without breaking the strict + * data hiding policy by exposing the real semaphore internals. This + * StaticSemaphore_t variable is passed into the xSemaphoreCreateCountingStatic() + * function calls within this function. NOTE: In most usage scenarios now it is + * faster and more memory efficient to use a direct to task notification instead of + * a counting semaphore. http://www.freertos.org/RTOS-task-notifications.html */ + StaticSemaphore_t xSemaphoreBuffer; + + /* Create the semaphore. xSemaphoreCreateCountingStatic() has one more + * parameter than the usual xSemaphoreCreateCounting() function. The parameter + * is a pointer to the pre-allocated StaticSemaphore_t structure, which will + * hold information on the semaphore in an anonymous way. If the pointer is + * passed as NULL then the structure will be allocated dynamically, just as + * when xSemaphoreCreateCounting() is called. */ + xSemaphore = xSemaphoreCreateCountingStatic( uxMaxCount, 0, &xSemaphoreBuffer ); + + /* The semaphore handle should equal the static semaphore structure passed + * into the xSemaphoreCreateBinaryStatic() function. */ + configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer ); + + /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */ + prvSanityCheckCreatedSemaphore( xSemaphore, uxMaxCount ); + + /* Delete the semaphore again so the buffers can be reused. */ + vSemaphoreDelete( xSemaphore ); + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Now do the same but using dynamically allocated buffers to ensure the + * delete functions are working correctly in both the static and dynamic + * allocation cases. */ + xSemaphore = xSemaphoreCreateCounting( uxMaxCount, 0 ); + configASSERT( xSemaphore != NULL ); + prvSanityCheckCreatedSemaphore( xSemaphore, uxMaxCount ); + vSemaphoreDelete( xSemaphore ); + } + #endif + } +/*-----------------------------------------------------------*/ + + static void prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes( void ) + { + SemaphoreHandle_t xSemaphore; + +/* StaticSemaphore_t is a publicly accessible structure that has the same size + * and alignment requirements as the real semaphore structure. It is provided as a + * mechanism for applications to know the size of the semaphore (which is dependent + * on the architecture and configuration file settings) without breaking the strict + * data hiding policy by exposing the real semaphore internals. This + * StaticSemaphore_t variable is passed into the + * xSemaphoreCreateRecursiveMutexStatic() function calls within this function. */ + StaticSemaphore_t xSemaphoreBuffer; + + /* Create the semaphore. xSemaphoreCreateRecursiveMutexStatic() has one + * more parameter than the usual xSemaphoreCreateRecursiveMutex() function. + * The parameter is a pointer to the pre-allocated StaticSemaphore_t structure, + * which will hold information on the semaphore in an anonymous way. If the + * pointer is passed as NULL then the structure will be allocated dynamically, + * just as when xSemaphoreCreateRecursiveMutex() is called. */ + xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xSemaphoreBuffer ); + + /* The semaphore handle should equal the static semaphore structure passed + * into the xSemaphoreCreateBinaryStatic() function. */ + configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer ); + + /* Ensure the semaphore passes a few sanity checks as a valid + * recursive semaphore. */ + prvSanityCheckCreatedRecursiveMutex( xSemaphore ); + + /* Delete the semaphore again so the buffers can be reused. */ + vSemaphoreDelete( xSemaphore ); + + /* Now do the same using dynamically allocated buffers to ensure the delete + * functions are working correctly in both the static and dynamic memory + * allocation cases. */ + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + xSemaphore = xSemaphoreCreateRecursiveMutex(); + configASSERT( xSemaphore != NULL ); + prvSanityCheckCreatedRecursiveMutex( xSemaphore ); + vSemaphoreDelete( xSemaphore ); + } + #endif + } +/*-----------------------------------------------------------*/ + + static void prvCreateAndDeleteStaticallyAllocatedQueues( void ) + { + QueueHandle_t xQueue; + +/* StaticQueue_t is a publicly accessible structure that has the same size and + * alignment requirements as the real queue structure. It is provided as a + * mechanism for applications to know the size of the queue (which is dependent on + * the architecture and configuration file settings) without breaking the strict + * data hiding policy by exposing the real queue internals. This StaticQueue_t + * variable is passed into the xQueueCreateStatic() function calls within this + * function. */ + static StaticQueue_t xStaticQueue; + +/* The queue storage area must be large enough to hold the maximum number of + * items it is possible for the queue to hold at any one time, which equals the + * queue length (in items, not bytes) multiplied by the size of each item. In this + * case the queue will hold staticQUEUE_LENGTH_IN_ITEMS 64-bit items. See + * http://www.freertos.org/Embedded-RTOS-Queues.html */ + static uint8_t ucQueueStorageArea[ staticQUEUE_LENGTH_IN_ITEMS * sizeof( uint64_t ) ]; + + /* Create the queue. xQueueCreateStatic() has two more parameters than the + * usual xQueueCreate() function. The first new parameter is a pointer to the + * pre-allocated queue storage area. The second new parameter is a pointer to + * the StaticQueue_t structure that will hold the queue state information in + * an anonymous way. If the two pointers are passed as NULL then the data + * will be allocated dynamically as if xQueueCreate() had been called. */ + xQueue = xQueueCreateStatic( staticQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */ + sizeof( uint64_t ), /* The size of each item. */ + ucQueueStorageArea, /* The buffer used to hold items within the queue. */ + &xStaticQueue ); /* The static queue structure that will hold the state of the queue. */ + + /* The queue handle should equal the static queue structure passed into the + * xQueueCreateStatic() function. */ + configASSERT( xQueue == ( QueueHandle_t ) &xStaticQueue ); + + /* Ensure the queue passes a few sanity checks as a valid queue. */ + prvSanityCheckCreatedQueue( xQueue ); + + /* Delete the queue again so the buffers can be reused. */ + vQueueDelete( xQueue ); + + /* Now do the same using a dynamically allocated queue to ensure the delete + * function is working correctly in both the static and dynamic memory + * allocation cases. */ + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + xQueue = xQueueCreate( staticQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */ + sizeof( uint64_t ) ); /* The size of each item. */ + + /* The queue handle should equal the static queue structure passed into the + * xQueueCreateStatic() function. */ + configASSERT( xQueue != NULL ); + + /* Ensure the queue passes a few sanity checks as a valid queue. */ + prvSanityCheckCreatedQueue( xQueue ); + + /* Delete the queue again so the buffers can be reused. */ + vQueueDelete( xQueue ); + } + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + } +/*-----------------------------------------------------------*/ + + static void prvCreateAndDeleteStaticallyAllocatedMutexes( void ) + { + SemaphoreHandle_t xSemaphore; + BaseType_t xReturned; + +/* StaticSemaphore_t is a publicly accessible structure that has the same size + * and alignment requirements as the real semaphore structure. It is provided as a + * mechanism for applications to know the size of the semaphore (which is dependent + * on the architecture and configuration file settings) without breaking the strict + * data hiding policy by exposing the real semaphore internals. This + * StaticSemaphore_t variable is passed into the xSemaphoreCreateMutexStatic() + * function calls within this function. */ + StaticSemaphore_t xSemaphoreBuffer; + + /* Create the semaphore. xSemaphoreCreateMutexStatic() has one more + * parameter than the usual xSemaphoreCreateMutex() function. The parameter + * is a pointer to the pre-allocated StaticSemaphore_t structure, which will + * hold information on the semaphore in an anonymous way. If the pointer is + * passed as NULL then the structure will be allocated dynamically, just as + * when xSemaphoreCreateMutex() is called. */ + xSemaphore = xSemaphoreCreateMutexStatic( &xSemaphoreBuffer ); + + /* The semaphore handle should equal the static semaphore structure passed + * into the xSemaphoreCreateMutexStatic() function. */ + configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer ); + + /* Take the mutex so the mutex is in the state expected by the + * prvSanityCheckCreatedSemaphore() function. */ + xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */ + prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT ); + + /* Delete the semaphore again so the buffers can be reused. */ + vSemaphoreDelete( xSemaphore ); + + /* Now do the same using a dynamically allocated mutex to ensure the delete + * function is working correctly in both the static and dynamic allocation + * cases. */ + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + xSemaphore = xSemaphoreCreateMutex(); + + /* The semaphore handle should equal the static semaphore structure + * passed into the xSemaphoreCreateMutexStatic() function. */ + configASSERT( xSemaphore != NULL ); + + /* Take the mutex so the mutex is in the state expected by the + * prvSanityCheckCreatedSemaphore() function. */ + xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */ + prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT ); + + /* Delete the semaphore again so the buffers can be reused. */ + vSemaphoreDelete( xSemaphore ); + } + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + } +/*-----------------------------------------------------------*/ + + static void prvCreateAndDeleteStaticallyAllocatedBinarySemaphores( void ) + { + SemaphoreHandle_t xSemaphore; + +/* StaticSemaphore_t is a publicly accessible structure that has the same size +* and alignment requirements as the real semaphore structure. It is provided as a +* mechanism for applications to know the size of the semaphore (which is dependent +* on the architecture and configuration file settings) without breaking the strict +* data hiding policy by exposing the real semaphore internals. This +* StaticSemaphore_t variable is passed into the xSemaphoreCreateBinaryStatic() +* function calls within this function. NOTE: In most usage scenarios now it is +* faster and more memory efficient to use a direct to task notification instead of +* a binary semaphore. http://www.freertos.org/RTOS-task-notifications.html */ + StaticSemaphore_t xSemaphoreBuffer; + + /* Create the semaphore. xSemaphoreCreateBinaryStatic() has one more + * parameter than the usual xSemaphoreCreateBinary() function. The parameter + * is a pointer to the pre-allocated StaticSemaphore_t structure, which will + * hold information on the semaphore in an anonymous way. If the pointer is + * passed as NULL then the structure will be allocated dynamically, just as + * when xSemaphoreCreateBinary() is called. */ + xSemaphore = xSemaphoreCreateBinaryStatic( &xSemaphoreBuffer ); + + /* The semaphore handle should equal the static semaphore structure passed + * into the xSemaphoreCreateBinaryStatic() function. */ + configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer ); + + /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */ + prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT ); + + /* Delete the semaphore again so the buffers can be reused. */ + vSemaphoreDelete( xSemaphore ); + + /* Now do the same using a dynamically allocated semaphore to check the + * delete function is working correctly in both the static and dynamic + * allocation cases. */ + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + xSemaphore = xSemaphoreCreateBinary(); + configASSERT( xSemaphore != NULL ); + prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT ); + vSemaphoreDelete( xSemaphore ); + } + #endif + + /* There isn't a static version of the old and deprecated + * vSemaphoreCreateBinary() macro (because its deprecated!), but check it is + * still functioning correctly. */ + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + vSemaphoreCreateBinary( xSemaphore ); + + /* The macro starts with the binary semaphore available, but the test + * function expects it to be unavailable. */ + if( xSemaphoreTake( xSemaphore, staticDONT_BLOCK ) == pdFAIL ) + { + xErrorOccurred = __LINE__; + } + + prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT ); + vSemaphoreDelete( xSemaphore ); + } + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + } +/*-----------------------------------------------------------*/ + + static void prvTimerCallback( TimerHandle_t xExpiredTimer ) + { + UBaseType_t * puxVariableToIncrement; + BaseType_t xReturned; + + /* The timer callback just demonstrates it is executing by incrementing a + * variable - the address of which is passed into the timer as its ID. Obtain + * the address of the variable to increment. */ + puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer ); + + /* Increment the variable to show the timer callback has executed. */ + ( *puxVariableToIncrement )++; + + /* If this callback has executed the required number of times, stop the + * timer. */ + if( *puxVariableToIncrement == staticMAX_TIMER_CALLBACK_EXECUTIONS ) + { + /* This is called from a timer callback so must not block. See + * http://www.FreeRTOS.org/FreeRTOS-timers-xTimerStop.html */ + xReturned = xTimerStop( xExpiredTimer, staticDONT_BLOCK ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + } + } +/*-----------------------------------------------------------*/ + + static void prvCreateAndDeleteStaticallyAllocatedTimers( void ) + { + TimerHandle_t xTimer; + UBaseType_t uxVariableToIncrement; + const TickType_t xTimerPeriod = pdMS_TO_TICKS( 20 ); + BaseType_t xReturned; + +/* StaticTimer_t is a publicly accessible structure that has the same size + * and alignment requirements as the real timer structure. It is provided as a + * mechanism for applications to know the size of the timer structure (which is + * dependent on the architecture and configuration file settings) without breaking + * the strict data hiding policy by exposing the real timer internals. This + * StaticTimer_t variable is passed into the xTimerCreateStatic() function calls + * within this function. */ + StaticTimer_t xTimerBuffer; + + /* Create the software time. xTimerCreateStatic() has an extra parameter + * than the normal xTimerCreate() API function. The parameter is a pointer to + * the StaticTimer_t structure that will hold the software timer structure. If + * the parameter is passed as NULL then the structure will be allocated + * dynamically, just as if xTimerCreate() had been called. */ + xTimer = xTimerCreateStatic( "T1", /* Text name for the task. Helps debugging only. Not used by FreeRTOS. */ + xTimerPeriod, /* The period of the timer in ticks. */ + pdTRUE, /* This is an auto-reload timer. */ + ( void * ) &uxVariableToIncrement, /* The variable incremented by the test is passed into the timer callback using the timer ID. */ + prvTimerCallback, /* The function to execute when the timer expires. */ + &xTimerBuffer ); /* The buffer that will hold the software timer structure. */ + + /* The timer handle should equal the static timer structure passed into the + * xTimerCreateStatic() function. */ + configASSERT( xTimer == ( TimerHandle_t ) &xTimerBuffer ); + + /* Set the variable to 0, wait for a few timer periods to expire, then check + * the timer callback has incremented the variable to the expected value. */ + uxVariableToIncrement = 0; + + /* This is a low priority so a block time should not be needed. */ + xReturned = xTimerStart( xTimer, staticDONT_BLOCK ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + vTaskDelay( xTimerPeriod * staticMAX_TIMER_CALLBACK_EXECUTIONS ); + + /* By now the timer should have expired staticMAX_TIMER_CALLBACK_EXECUTIONS + * times, and then stopped itself. */ + if( uxVariableToIncrement != staticMAX_TIMER_CALLBACK_EXECUTIONS ) + { + xErrorOccurred = __LINE__; + } + + /* Finished with the timer, delete it. */ + xReturned = xTimerDelete( xTimer, staticDONT_BLOCK ); + + /* Again, as this is a low priority task it is expected that the timer + * command will have been sent even without a block time being used. */ + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + /* Just to show the check task that this task is still executing. */ + uxCycleCounter++; + + /* Now do the same using a dynamically allocated software timer to ensure + * the delete function is working correctly in both the static and dynamic + * allocation cases. */ + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + xTimer = xTimerCreate( "T1", /* Text name for the task. Helps debugging only. Not used by FreeRTOS. */ + xTimerPeriod, /* The period of the timer in ticks. */ + pdTRUE, /* This is an auto-reload timer. */ + ( void * ) &uxVariableToIncrement, /* The variable incremented by the test is passed into the timer callback using the timer ID. */ + prvTimerCallback ); /* The function to execute when the timer expires. */ + + configASSERT( xTimer != NULL ); + + uxVariableToIncrement = 0; + xReturned = xTimerStart( xTimer, staticDONT_BLOCK ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + vTaskDelay( xTimerPeriod * staticMAX_TIMER_CALLBACK_EXECUTIONS ); + + if( uxVariableToIncrement != staticMAX_TIMER_CALLBACK_EXECUTIONS ) + { + xErrorOccurred = __LINE__; + } + + xReturned = xTimerDelete( xTimer, staticDONT_BLOCK ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + } + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + } +/*-----------------------------------------------------------*/ + + static void prvCreateAndDeleteStaticallyAllocatedEventGroups( void ) + { + EventGroupHandle_t xEventGroup; + +/* StaticEventGroup_t is a publicly accessible structure that has the same size + * and alignment requirements as the real event group structure. It is provided as + * a mechanism for applications to know the size of the event group (which is + * dependent on the architecture and configuration file settings) without breaking + * the strict data hiding policy by exposing the real event group internals. This + * StaticEventGroup_t variable is passed into the xSemaphoreCreateEventGroupStatic() + * function calls within this function. */ + StaticEventGroup_t xEventGroupBuffer; + + /* Create the event group. xEventGroupCreateStatic() has an extra parameter + * than the normal xEventGroupCreate() API function. The parameter is a + * pointer to the StaticEventGroup_t structure that will hold the event group + * structure. */ + xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer ); + + /* The event group handle should equal the static event group structure + * passed into the xEventGroupCreateStatic() function. */ + configASSERT( xEventGroup == ( EventGroupHandle_t ) &xEventGroupBuffer ); + + /* Ensure the event group passes a few sanity checks as a valid event + * group. */ + prvSanityCheckCreatedEventGroup( xEventGroup ); + + /* Delete the event group again so the buffers can be reused. */ + vEventGroupDelete( xEventGroup ); + + /* Now do the same using a dynamically allocated event group to ensure the + * delete function is working correctly in both the static and dynamic + * allocation cases. */ + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + xEventGroup = xEventGroupCreate(); + configASSERT( xEventGroup != NULL ); + prvSanityCheckCreatedEventGroup( xEventGroup ); + vEventGroupDelete( xEventGroup ); + } + #endif + } +/*-----------------------------------------------------------*/ + + static void prvCreateAndDeleteStaticallyAllocatedTasks( void ) + { + TaskHandle_t xCreatedTask; + +/* The variable that will hold the TCB of tasks created by this function. See + * the comments above the declaration of the xCreatorTaskTCBBuffer variable for + * more information. NOTE: This is not static so relies on the tasks that use it + * being deleted before this function returns and deallocates its stack. That will + * only be the case if configUSE_PREEMPTION is set to 1. */ + StaticTask_t xTCBBuffer; + +/* This buffer that will be used as the stack of tasks created by this function. + * See the comments above the declaration of the uxCreatorTaskStackBuffer[] array + * above for more information. */ + static StackType_t uxStackBuffer[ configMINIMAL_STACK_SIZE ]; + + /* Create the task. xTaskCreateStatic() has two more parameters than + * the usual xTaskCreate() function. The first new parameter is a pointer to + * the pre-allocated stack. The second new parameter is a pointer to the + * StaticTask_t structure that will hold the task's TCB. If both pointers are + * passed as NULL then the respective object will be allocated dynamically as + * if xTaskCreate() had been called. */ + xCreatedTask = xTaskCreateStatic( + prvStaticallyAllocatedTask, /* Function that implements the task. */ + "Static", /* Human readable name for the task. */ + configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */ + NULL, /* Parameter to pass into the task. */ + uxTaskPriorityGet( NULL ) + 1, /* The priority of the task. */ + &( uxStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */ + &xTCBBuffer ); /* The variable that will hold that task's TCB. */ + + /* Check the task was created correctly, then delete the task. */ + if( xCreatedTask == NULL ) + { + xErrorOccurred = __LINE__; + } + else if( eTaskGetState( xCreatedTask ) != eSuspended ) + { + /* The created task had a higher priority so should have executed and + * suspended itself by now. */ + xErrorOccurred = __LINE__; + } + else + { + vTaskDelete( xCreatedTask ); + } + + /* Now do the same using a dynamically allocated task to ensure the delete + * function is working correctly in both the static and dynamic allocation + * cases. */ + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + BaseType_t xReturned; + + xReturned = xTaskCreate( + prvStaticallyAllocatedTask, /* Function that implements the task - the same function is used but is actually dynamically allocated this time. */ + "Static", /* Human readable name for the task. */ + configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */ + NULL, /* Parameter to pass into the task. */ + uxTaskPriorityGet( NULL ) + 1, /* The priority of the task. */ + &xCreatedTask ); /* Handle of the task being created. */ + + if( eTaskGetState( xCreatedTask ) != eSuspended ) + { + xErrorOccurred = __LINE__; + } + + configASSERT( xReturned == pdPASS ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + vTaskDelete( xCreatedTask ); + } + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + } +/*-----------------------------------------------------------*/ + + static void prvStaticallyAllocatedTask( void * pvParameters ) + { + ( void ) pvParameters; + + /* The created task just suspends itself to wait to get deleted. The task + * that creates this task checks this task is in the expected Suspended state + * before deleting it. */ + vTaskSuspend( NULL ); + } +/*-----------------------------------------------------------*/ + + static UBaseType_t prvRand( void ) + { + const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL; + + /* Utility function to generate a pseudo random number. */ + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + return( ( ulNextRand >> 16UL ) & 0x7fffUL ); + } +/*-----------------------------------------------------------*/ + + static TickType_t prvGetNextDelayTime( void ) + { + TickType_t xNextDelay; + const TickType_t xMaxDelay = pdMS_TO_TICKS( ( TickType_t ) 150 ); + const TickType_t xMinDelay = pdMS_TO_TICKS( ( TickType_t ) 75 ); + const TickType_t xTinyDelay = pdMS_TO_TICKS( ( TickType_t ) 2 ); + + /* Generate the next delay time. This is kept within a narrow band so as + * not to disturb the timing of other tests - but does add in some pseudo + * randomisation into the tests. */ + do + { + xNextDelay = prvRand() % xMaxDelay; + + /* Just in case this loop is executed lots of times. */ + vTaskDelay( xTinyDelay ); + } while( xNextDelay < xMinDelay ); + + return xNextDelay; + } +/*-----------------------------------------------------------*/ + + static void prvSanityCheckCreatedEventGroup( EventGroupHandle_t xEventGroup ) + { + EventBits_t xEventBits; + const EventBits_t xFirstTestBits = ( EventBits_t ) 0xaa, xSecondTestBits = ( EventBits_t ) 0x55; + + /* The event group should not have any bits set yet. */ + xEventBits = xEventGroupGetBits( xEventGroup ); + + if( xEventBits != ( EventBits_t ) 0 ) + { + xErrorOccurred = __LINE__; + } + + /* Some some bits, then read them back to check they are as expected. */ + xEventGroupSetBits( xEventGroup, xFirstTestBits ); + + xEventBits = xEventGroupGetBits( xEventGroup ); + + if( xEventBits != xFirstTestBits ) + { + xErrorOccurred = __LINE__; + } + + xEventGroupSetBits( xEventGroup, xSecondTestBits ); + + xEventBits = xEventGroupGetBits( xEventGroup ); + + if( xEventBits != ( xFirstTestBits | xSecondTestBits ) ) + { + xErrorOccurred = __LINE__; + } + + /* Finally try clearing some bits too and check that operation proceeds as + * expected. */ + xEventGroupClearBits( xEventGroup, xFirstTestBits ); + + xEventBits = xEventGroupGetBits( xEventGroup ); + + if( xEventBits != xSecondTestBits ) + { + xErrorOccurred = __LINE__; + } + } +/*-----------------------------------------------------------*/ + + static void prvSanityCheckCreatedSemaphore( SemaphoreHandle_t xSemaphore, + UBaseType_t uxMaxCount ) + { + BaseType_t xReturned; + UBaseType_t x; + const TickType_t xShortBlockTime = pdMS_TO_TICKS( 10 ); + TickType_t xTickCount; + + /* The binary semaphore should start 'empty', so a call to xSemaphoreTake() + * should fail. */ + xTickCount = xTaskGetTickCount(); + xReturned = xSemaphoreTake( xSemaphore, xShortBlockTime ); + + if( ( ( TickType_t ) ( xTaskGetTickCount() - xTickCount ) ) < xShortBlockTime ) + { + /* Did not block on the semaphore as long as expected. */ + xErrorOccurred = __LINE__; + } + + if( xReturned != pdFAIL ) + { + xErrorOccurred = __LINE__; + } + + /* Should be possible to 'give' the semaphore up to a maximum of uxMaxCount + * times. */ + for( x = 0; x < uxMaxCount; x++ ) + { + xReturned = xSemaphoreGive( xSemaphore ); + + if( xReturned == pdFAIL ) + { + xErrorOccurred = __LINE__; + } + } + + /* Giving the semaphore again should fail, as it is 'full'. */ + xReturned = xSemaphoreGive( xSemaphore ); + + if( xReturned != pdFAIL ) + { + xErrorOccurred = __LINE__; + } + + configASSERT( uxSemaphoreGetCount( xSemaphore ) == uxMaxCount ); + + /* Should now be possible to 'take' the semaphore up to a maximum of + * uxMaxCount times without blocking. */ + for( x = 0; x < uxMaxCount; x++ ) + { + xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK ); + + if( xReturned == pdFAIL ) + { + xErrorOccurred = __LINE__; + } + } + + /* Back to the starting condition, where the semaphore should not be + * available. */ + xTickCount = xTaskGetTickCount(); + xReturned = xSemaphoreTake( xSemaphore, xShortBlockTime ); + + if( ( ( TickType_t ) ( xTaskGetTickCount() - xTickCount ) ) < xShortBlockTime ) + { + /* Did not block on the semaphore as long as expected. */ + xErrorOccurred = __LINE__; + } + + if( xReturned != pdFAIL ) + { + xErrorOccurred = __LINE__; + } + + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); + } +/*-----------------------------------------------------------*/ + + static void prvSanityCheckCreatedQueue( QueueHandle_t xQueue ) + { + uint64_t ull, ullRead; + BaseType_t xReturned, xLoop; + + /* This test is done twice to ensure the queue storage area wraps. */ + for( xLoop = 0; xLoop < 2; xLoop++ ) + { + /* A very basic test that the queue can be written to and read from as + * expected. First the queue should be empty. */ + xReturned = xQueueReceive( xQueue, &ull, staticDONT_BLOCK ); + + if( xReturned != errQUEUE_EMPTY ) + { + xErrorOccurred = __LINE__; + } + + /* Now it should be possible to write to the queue staticQUEUE_LENGTH_IN_ITEMS + * times. */ + for( ull = 0; ull < staticQUEUE_LENGTH_IN_ITEMS; ull++ ) + { + xReturned = xQueueSend( xQueue, &ull, staticDONT_BLOCK ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + } + + /* Should not now be possible to write to the queue again. */ + xReturned = xQueueSend( xQueue, &ull, staticDONT_BLOCK ); + + if( xReturned != errQUEUE_FULL ) + { + xErrorOccurred = __LINE__; + } + + /* Now read back from the queue to ensure the data read back matches that + * written. */ + for( ull = 0; ull < staticQUEUE_LENGTH_IN_ITEMS; ull++ ) + { + xReturned = xQueueReceive( xQueue, &ullRead, staticDONT_BLOCK ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + if( ullRead != ull ) + { + xErrorOccurred = __LINE__; + } + } + + /* The queue should be empty again. */ + xReturned = xQueueReceive( xQueue, &ull, staticDONT_BLOCK ); + + if( xReturned != errQUEUE_EMPTY ) + { + xErrorOccurred = __LINE__; + } + } + } +/*-----------------------------------------------------------*/ + + static void prvSanityCheckCreatedRecursiveMutex( SemaphoreHandle_t xSemaphore ) + { + const BaseType_t xLoops = 5; + BaseType_t x, xReturned; + + /* A very basic test that the recursive semaphore behaved like a recursive + * semaphore. First the semaphore should not be able to be given, as it has not + * yet been taken. */ + xReturned = xSemaphoreGiveRecursive( xSemaphore ); + + if( xReturned != pdFAIL ) + { + xErrorOccurred = __LINE__; + } + + /* Now it should be possible to take the mutex a number of times. */ + for( x = 0; x < xLoops; x++ ) + { + xReturned = xSemaphoreTakeRecursive( xSemaphore, staticDONT_BLOCK ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + } + + /* Should be possible to give the semaphore the same number of times as it + * was given in the loop above. */ + for( x = 0; x < xLoops; x++ ) + { + xReturned = xSemaphoreGiveRecursive( xSemaphore ); + + if( xReturned != pdPASS ) + { + xErrorOccurred = __LINE__; + } + } + + /* No more gives should be possible though. */ + xReturned = xSemaphoreGiveRecursive( xSemaphore ); + + if( xReturned != pdFAIL ) + { + xErrorOccurred = __LINE__; + } + } +/*-----------------------------------------------------------*/ + + BaseType_t xAreStaticAllocationTasksStillRunning( void ) + { + static UBaseType_t uxLastCycleCounter = 0; + BaseType_t xReturn; + + if( uxCycleCounter == uxLastCycleCounter ) + { + xErrorOccurred = __LINE__; + } + else + { + uxLastCycleCounter = uxCycleCounter; + } + + if( xErrorOccurred != pdFALSE ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdPASS; + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + +/* Exclude the entire file if configSUPPORT_STATIC_ALLOCATION is 0. */ +#endif /* configSUPPORT_STATIC_ALLOCATION == 1 */ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/StreamBufferDemo.c b/SOFTWARE-FreeRTOS/Common/Minimal/StreamBufferDemo.c new file mode 100644 index 0000000..17214f1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/StreamBufferDemo.c @@ -0,0 +1,1247 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include "stdio.h" +#include "string.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "stream_buffer.h" + +/* Demo app includes. */ +#include "StreamBufferDemo.h" + +/* The number of bytes of storage in the stream buffers used in this test. */ +#define sbSTREAM_BUFFER_LENGTH_BYTES ( ( size_t ) 30 ) + +/* Stream buffer length one. */ +#define sbSTREAM_BUFFER_LENGTH_ONE ( ( size_t ) 1 ) + +/* Start and end ASCII characters used in data sent to the buffers. */ +#define sbASCII_SPACE 32 +#define sbASCII_TILDA 126 + +/* Defines the number of tasks to create in this test and demo. */ +#define sbNUMBER_OF_ECHO_CLIENTS ( 2 ) +#define sbNUMBER_OF_SENDER_TASKS ( 2 ) + +/* Priority of the test tasks. The send and receive go from low to high + * priority tasks, and from high to low priority tasks. */ +#define sbLOWER_PRIORITY ( tskIDLE_PRIORITY ) +#define sbHIGHER_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* Block times used when sending and receiving from the stream buffers. */ +#define sbRX_TX_BLOCK_TIME pdMS_TO_TICKS( 125UL ) + +/* A block time of 0 means "don't block". */ +#define sbDONT_BLOCK ( 0 ) + +/* The trigger level sets the number of bytes that must be present in the + * stream buffer before a task that is blocked on the stream buffer is moved out of + * the Blocked state so it can read the bytes. */ +#define sbTRIGGER_LEVEL_1 ( 1 ) + +/* The size of the stack allocated to the tasks that run as part of this demo/ + * test. The stack size is over generous in most cases. */ +#ifndef configSTREAM_BUFFER_SENDER_TASK_STACK_SIZE + #define sbSTACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) ) +#else + #define sbSTACK_SIZE configSTREAM_BUFFER_SENDER_TASK_STACK_SIZE +#endif + +#ifndef configSTREAM_BUFFER_SMALLER_TASK_STACK_SIZE + #define sbSMALLER_STACK_SIZE sbSTACK_SIZE +#else + #define sbSMALLER_STACK_SIZE configSTREAM_BUFFER_SMALLER_TASK_STACK_SIZE +#endif + +/*-----------------------------------------------------------*/ + +/* + * Performs various tests that do not require multiple tasks to interact. + */ +static void prvSingleTaskTests( StreamBufferHandle_t xStreamBuffer ); + +/* + * Tests sending and receiving various lengths of data via a stream buffer. + * The echo client sends the data to the echo server, which then sends the + * data back to the echo client, which checks it receives exactly what it + * sent. + */ +static void prvEchoClient( void * pvParameters ); +static void prvEchoServer( void * pvParameters ); + +/* + * Tasks that send and receive to a stream buffer at a low priority and without + * blocking, so the send and receive functions interleave in time as the tasks + * are switched in and out. + */ +static void prvNonBlockingReceiverTask( void * pvParameters ); +static void prvNonBlockingSenderTask( void * pvParameters ); + +/* Performs an assert() like check in a way that won't get removed when + * performing a code coverage analysis. */ +static void prvCheckExpectedState( BaseType_t xState ); + +/* + * A task that creates a stream buffer with a specific trigger level, then + * receives a string from an interrupt (the RTOS tick hook) byte by byte to + * check it is only unblocked when the specified trigger level is reached. + */ +static void prvInterruptTriggerLevelTest( void * pvParameters ); + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/* This file tests both statically and dynamically allocated stream buffers. + * Allocate the structures and buffers to be used by the statically allocated + * objects, which get used in the echo tests. */ + static void prvReceiverTask( void * pvParameters ); + static void prvSenderTask( void * pvParameters ); + + static StaticStreamBuffer_t xStaticStreamBuffers[ sbNUMBER_OF_ECHO_CLIENTS ]; + static uint32_t ulSenderLoopCounters[ sbNUMBER_OF_SENDER_TASKS ] = { 0 }; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/* The +1 is to make the test logic easier as the function that calculates the + * free space will return one less than the actual free space - adding a 1 to the + * actual length makes it appear to the tests as if the free space is returned as + * it might logically be expected. Returning 1 less than the actual free space is + * fine as it can never result in an overrun. */ +static uint8_t ucBufferStorage[ sbNUMBER_OF_SENDER_TASKS ][ sbSTREAM_BUFFER_LENGTH_BYTES + 1 ]; + +/*-----------------------------------------------------------*/ + +/* The buffers used by the echo client and server tasks. */ +typedef struct ECHO_STREAM_BUFFERS +{ + /* Handles to the data structures that describe the stream buffers. */ + StreamBufferHandle_t xEchoClientBuffer; + StreamBufferHandle_t xEchoServerBuffer; +} EchoStreamBuffers_t; +static volatile uint32_t ulEchoLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 }; + +/* The non-blocking tasks monitor their operation, and if no errors have been + * found, increment ulNonBlockingRxCounter. xAreStreamBufferTasksStillRunning() + * then checks ulNonBlockingRxCounter and only returns pdPASS if + * ulNonBlockingRxCounter is still incrementing. */ +static volatile uint32_t ulNonBlockingRxCounter = 0; + +/* The task that receives characters from the tick interrupt in order to test + * different trigger levels monitors its own behaviour. If it has not detected any + * error then it increments ulInterruptTriggerCounter to indicate to the check task + * that it is still operating correctly. */ +static volatile uint32_t ulInterruptTriggerCounter = 0UL; + +/* The stream buffer used from the tick interrupt. This sends one byte at a time + * to a test task to test the trigger level operation. The variable is set to NULL + * in between test runs. */ +static volatile StreamBufferHandle_t xInterruptStreamBuffer = NULL; + +/* The data sent from the tick interrupt to the task that tests the trigger + * level functionality. */ +static const char * pcDataSentFromInterrupt = "0123456789"; + +/* Data that is longer than the buffer that is sent to the buffers as a stream + * of bytes. Parts of which are written to the stream buffer to test writing + * different lengths at different offsets, to many bytes, part streams, streams + * that wrap, etc.. Two messages are defined to ensure left over data is not + * accidentally read out of the buffer. */ +static const char * pc55ByteString = "One two three four five six seven eight nine ten eleven"; +static const char * pc54ByteString = "01234567891abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQ"; + +/* Used to log the status of the tests contained within this file for reporting + * to a monitoring task ('check' task). */ +static BaseType_t xErrorStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +void vStartStreamBufferTasks( void ) +{ + StreamBufferHandle_t xStreamBuffer; + + /* The echo servers sets up the stream buffers before creating the echo + * client tasks. One set of tasks has the server as the higher priority, and + * the other has the client as the higher priority. */ + xTaskCreate( prvEchoServer, "1StrEchoServer", sbSMALLER_STACK_SIZE, NULL, sbHIGHER_PRIORITY, NULL ); + xTaskCreate( prvEchoServer, "2StrEchoServer", sbSMALLER_STACK_SIZE, NULL, sbLOWER_PRIORITY, NULL ); + + /* The non blocking tasks run continuously and will interleave with each + * other, so must be created at the lowest priority. The stream buffer they + * use is created and passed in using the task's parameter. */ + xStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 ); + xTaskCreate( prvNonBlockingReceiverTask, "StrNonBlkRx", configMINIMAL_STACK_SIZE, ( void * ) xStreamBuffer, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvNonBlockingSenderTask, "StrNonBlkTx", configMINIMAL_STACK_SIZE, ( void * ) xStreamBuffer, tskIDLE_PRIORITY, NULL ); + + /* The task that receives bytes from an interrupt to test that it unblocks + * at a specific trigger level must run at a high priority to minimise the risk + * of it receiving more characters before it can execute again after being + * unblocked. */ + xTaskCreate( prvInterruptTriggerLevelTest, "StrTrig", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* The sender tasks set up the stream buffers before creating the + * receiver tasks. Priorities must be 0 and 1 as the priority is used to + * index into the xStaticStreamBuffers and ucBufferStorage arrays. */ + xTaskCreate( prvSenderTask, "Str1Sender", sbSMALLER_STACK_SIZE, NULL, sbHIGHER_PRIORITY, NULL ); + xTaskCreate( prvSenderTask, "Str2Sender", sbSMALLER_STACK_SIZE, NULL, sbLOWER_PRIORITY, NULL ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ +} +/*-----------------------------------------------------------*/ + +static void prvCheckExpectedState( BaseType_t xState ) +{ + configASSERT( xState ); + + if( xState == pdFAIL ) + { + xErrorStatus = pdFAIL; + } +} +/*-----------------------------------------------------------*/ + +static void prvSingleTaskTests( StreamBufferHandle_t xStreamBuffer ) +{ + size_t xReturned, xItem, xExpected, xExpectedSpaces, xExpectedBytes; + const size_t xMax6ByteMessages = sbSTREAM_BUFFER_LENGTH_BYTES / 6; + const size_t xTrueSize = ( sizeof( ucBufferStorage ) / sbNUMBER_OF_SENDER_TASKS ); + const size_t x6ByteLength = 6, x17ByteLength = 17, xFullBufferSize = sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2; + uint8_t * pucFullBuffer, * pucData, * pucReadData; + TickType_t xTimeBeforeCall, xTimeAfterCall; + const TickType_t xBlockTime = pdMS_TO_TICKS( 15 ), xAllowableMargin = pdMS_TO_TICKS( 3 ), xMinimalBlockTime = 2; + UBaseType_t uxOriginalPriority; + + /* Remove warning in case configASSERT() is not defined. */ + ( void ) xAllowableMargin; + + /* To minimise stack and heap usage a full size buffer is allocated from the + * heap, then buffers which hold smaller amounts of data are overlayed with the + * larger buffer - just make sure not to use both at once! */ + pucFullBuffer = pvPortMalloc( xFullBufferSize ); + configASSERT( pucFullBuffer ); + + pucData = pucFullBuffer; + pucReadData = pucData + x17ByteLength; + + /* Nothing has been added or removed yet, so expect the free space to be + * exactly as created. Head and tail are both at 0. */ + xExpectedSpaces = sbSTREAM_BUFFER_LENGTH_BYTES; + xExpectedBytes = 0; + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedSpaces ); + xExpected = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedBytes ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + + /* Add a single item - number of bytes available should go up by one and spaces + * available down by one. Head is in front of tail. */ + xExpectedSpaces--; + xExpectedBytes++; + xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 ); + prvCheckExpectedState( xReturned == sizeof( *pucData ) ); + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedSpaces ); + xExpected = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedBytes ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + + /* Now fill the buffer by adding another 29 bytes. Head is 30 tail is at 0. */ + xExpectedSpaces -= 29; + xExpectedBytes += 29; + xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, ( sbSTREAM_BUFFER_LENGTH_BYTES - 1 ), ( TickType_t ) 0 ); + prvCheckExpectedState( xReturned == ( sbSTREAM_BUFFER_LENGTH_BYTES - 1 ) ); + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedSpaces ); + xExpected = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedBytes ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE ); + + /* Should not be able to add another byte now. */ + xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 ); + prvCheckExpectedState( xReturned == ( size_t ) 0 ); + + /* Remove a byte so the tail pointer moves off 0. Head pointer remains at the + * end of the buffer. */ + xExpectedSpaces += 1; + xExpectedBytes -= 1; + xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 ); + prvCheckExpectedState( xReturned == sizeof( *pucData ) ); + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedSpaces ); + xExpected = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedBytes ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + + /* Should be able to add another byte to fill the buffer again now. */ + xExpectedSpaces -= 1; + xExpectedBytes += 1; + xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 ); + prvCheckExpectedState( xReturned == sizeof( *pucData ) ); + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedSpaces ); + xExpected = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedBytes ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE ); + + /* Now the head pointer is behind the tail pointer. Read another 29 bytes so + * the tail pointer moves to the end of the buffer. */ + xExpectedSpaces += 29; + xExpectedBytes -= 29; + xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, ( size_t ) 29, ( TickType_t ) 0 ); + prvCheckExpectedState( xReturned == ( size_t ) 29 ); + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedSpaces ); + xExpected = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedBytes ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + + /* Read out one more byte to wrap the tail back around to the start, to get back + * to where we started. */ + xExpectedSpaces += 1; + xExpectedBytes -= 1; + xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 ); + prvCheckExpectedState( xReturned == sizeof( *pucData ) ); + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedSpaces ); + xExpected = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedBytes ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + + /* Try filling the message buffer in one write, blocking indefinitely. Expect to + * have written one byte less. */ + xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, xTrueSize, portMAX_DELAY ); + xExpectedSpaces = ( size_t ) 0; + prvCheckExpectedState( xReturned == ( xTrueSize - ( size_t ) 1 ) ); + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == xExpectedSpaces ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE ); + + /* Empty the buffer again ready for the rest of the tests. Again block + * indefinitely to ensure reading more than there can possible be won't lock this + * task up, so expect to actually receive one byte less than requested. */ + xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, xTrueSize, portMAX_DELAY ); + prvCheckExpectedState( xReturned == ( xTrueSize - ( size_t ) 1 ) ); + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == sbSTREAM_BUFFER_LENGTH_BYTES ); + xExpected = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == ( size_t ) 0 ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + + + /* The buffer is 30 bytes long. 6 5 byte messages should fit before the + * buffer is completely full. */ + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + + for( xItem = 0; xItem < xMax6ByteMessages; xItem++ ) + { + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + + /* Generate recognizable data to write to the buffer. This is just + * ascii characters that shows which loop iteration the data was written + * in. The 'FromISR' version is used to give it some exercise as a block + * time is not used, so the call must be inside a critical section so it + * runs with ports that don't support interrupt nesting (and therefore + * don't have interrupt safe critical sections). */ + memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength ); + taskENTER_CRITICAL(); + { + xReturned = xStreamBufferSendFromISR( xStreamBuffer, ( void * ) pucData, x6ByteLength, NULL ); + } + taskEXIT_CRITICAL(); + prvCheckExpectedState( xReturned == x6ByteLength ); + + /* The space in the buffer will have reduced by the amount of user data + * written into the buffer. */ + xExpected -= x6ByteLength; + xReturned = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xReturned == xExpected ); + xReturned = xStreamBufferBytesAvailable( xStreamBuffer ); + /* +1 as it is zero indexed. */ + prvCheckExpectedState( xReturned == ( ( xItem + 1 ) * x6ByteLength ) ); + } + + /* Now the buffer should be full, and attempting to add anything should fail. */ + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE ); + xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), sbDONT_BLOCK ); + prvCheckExpectedState( xReturned == 0 ); + + /* Adding with a timeout should also fail after the appropriate time. The + * priority is temporarily boosted in this part of the test to keep the + * allowable margin to a minimum. */ + uxOriginalPriority = uxTaskPriorityGet( NULL ); + vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 ); + xTimeBeforeCall = xTaskGetTickCount(); + xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), xBlockTime ); + xTimeAfterCall = xTaskGetTickCount(); + vTaskPrioritySet( NULL, uxOriginalPriority ); + prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) >= xBlockTime ); + prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) < ( xBlockTime + xAllowableMargin ) ); + prvCheckExpectedState( xReturned == 0 ); + + /* The buffer is now full of data in the form "000000", "111111", etc. Make + * sure the data is read out as expected. */ + for( xItem = 0; xItem < xMax6ByteMessages; xItem++ ) + { + /* Generate the data that is expected to be read out for this loop + * iteration. */ + memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength ); + + /* Read the next 6 bytes out. The 'FromISR' version is used to give it + * some exercise as a block time is not used, so a it must be called from + * a critical section so this will work on ports that don't support + * interrupt nesting (so don't have interrupt safe critical sections). */ + taskENTER_CRITICAL(); + { + xReturned = xStreamBufferReceiveFromISR( xStreamBuffer, ( void * ) pucReadData, x6ByteLength, NULL ); + } + taskEXIT_CRITICAL(); + prvCheckExpectedState( xReturned == x6ByteLength ); + + /* Does the data read out match that expected? */ + prvCheckExpectedState( memcmp( ( void * ) pucData, ( void * ) pucReadData, x6ByteLength ) == 0 ); + + /* The space in the buffer will have increased by the amount of user + * data removed from the buffer. */ + xExpected += x6ByteLength; + xReturned = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xReturned == xExpected ); + xReturned = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xReturned == ( sbSTREAM_BUFFER_LENGTH_BYTES - xExpected ) ); + } + + /* The buffer should be empty again. */ + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE ); + xExpected = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xExpected == sbSTREAM_BUFFER_LENGTH_BYTES ); + + /* Reading with a timeout should also fail after the appropriate time. The + * priority is temporarily boosted in this part of the test to keep the + * allowable margin to a minimum. */ + vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 ); + xTimeBeforeCall = xTaskGetTickCount(); + xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucReadData, x6ByteLength, xBlockTime ); + xTimeAfterCall = xTaskGetTickCount(); + vTaskPrioritySet( NULL, uxOriginalPriority ); + prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) >= xBlockTime ); + prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) < ( xBlockTime + xAllowableMargin ) ); + prvCheckExpectedState( xReturned == 0 ); + + + /* In the next loop 17 bytes are written to then read out on each + * iteration. As 30 is not divisible by 17 the data will wrap around. */ + xExpected = sbSTREAM_BUFFER_LENGTH_BYTES - x17ByteLength; + + for( xItem = 0; xItem < 100; xItem++ ) + { + /* Generate recognizable data to write to the queue. This is just + * ascii characters that shows which loop iteration the data was written + * in. */ + memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x17ByteLength ); + xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, x17ByteLength, sbDONT_BLOCK ); + prvCheckExpectedState( xReturned == x17ByteLength ); + + /* The space in the buffer will have reduced by the amount of user data + * written into the buffer. */ + xReturned = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xReturned == xExpected ); + xReturned = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xReturned == x17ByteLength ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE ); + + /* Read the 17 bytes out again. */ + xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucReadData, x17ByteLength, sbDONT_BLOCK ); + prvCheckExpectedState( xReturned == x17ByteLength ); + + /* Does the data read out match that expected? */ + prvCheckExpectedState( memcmp( ( void * ) pucData, ( void * ) pucReadData, x17ByteLength ) == 0 ); + + /* Full buffer space available again. */ + xReturned = xStreamBufferSpacesAvailable( xStreamBuffer ); + prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES ); + xReturned = xStreamBufferBytesAvailable( xStreamBuffer ); + prvCheckExpectedState( xReturned == 0 ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE ); + } + + /* Fill the buffer with one message, check it is full, then read it back + * again and check the correct data is received. */ + xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES, sbDONT_BLOCK ); + xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES, sbDONT_BLOCK ); + prvCheckExpectedState( memcmp( pc55ByteString, pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 ); + + /* Fill the buffer one bytes at a time. */ + for( xItem = 0; xItem < sbSTREAM_BUFFER_LENGTH_BYTES; xItem++ ) + { + /* Block time is only for test coverage, the task should never actually + * block here. */ + xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc54ByteString[ xItem ] ), sizeof( char ), sbRX_TX_BLOCK_TIME ); + } + + /* The buffer should now be full. */ + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE ); + + /* Read the message out in one go, even though it was written in individual + * bytes. Try reading much more data than is actually available to ensure only + * the available bytes are returned (otherwise this read will write outside of + * the memory allocated anyway!). */ + xReturned = xStreamBufferReceive( xStreamBuffer, pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, sbRX_TX_BLOCK_TIME ); + prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES ); + prvCheckExpectedState( memcmp( ( const void * ) pc54ByteString, ( const void * ) pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 ); + + /* Now do the opposite, write in one go and read out in single bytes. */ + xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES, sbRX_TX_BLOCK_TIME ); + prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferBytesAvailable( xStreamBuffer ) == sbSTREAM_BUFFER_LENGTH_BYTES ); + prvCheckExpectedState( xStreamBufferSpacesAvailable( xStreamBuffer ) == 0 ); + + /* Read from the buffer one byte at a time. */ + for( xItem = 0; xItem < sbSTREAM_BUFFER_LENGTH_BYTES; xItem++ ) + { + /* Block time is only for test coverage, the task should never actually + * block here. */ + xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, sizeof( char ), sbRX_TX_BLOCK_TIME ); + prvCheckExpectedState( pc55ByteString[ xItem ] == pucFullBuffer[ 0 ] ); + } + + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + + /* Try writing more bytes than there is space. */ + vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 ); + xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, xMinimalBlockTime ); + vTaskPrioritySet( NULL, uxOriginalPriority ); + prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE ); + + /* No space now though. */ + xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, xMinimalBlockTime ); + prvCheckExpectedState( xReturned == 0 ); + + /* Ensure data was written as expected even when there was an attempt to + * write more than was available. This also tries to read more bytes than are + * available. */ + xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, xFullBufferSize, xMinimalBlockTime ); + prvCheckExpectedState( memcmp( ( const void * ) pucFullBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 ); + prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE ); + prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE ); + + /* Clean up with data in the buffer to ensure the tests that follow don't + * see the data (the data should be discarded). */ + ( void ) xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES / ( size_t ) 2, sbDONT_BLOCK ); + vPortFree( pucFullBuffer ); + xStreamBufferReset( xStreamBuffer ); +} +/*-----------------------------------------------------------*/ + +static void prvNonBlockingSenderTask( void * pvParameters ) +{ + StreamBufferHandle_t xStreamBuffer; + size_t xNextChar = 0, xBytesToSend, xBytesActuallySent; + const size_t xStringLength = strlen( pc54ByteString ); + + /* In this case the stream buffer has already been created and is passed + * into the task using the task's parameter. */ + xStreamBuffer = ( StreamBufferHandle_t ) pvParameters; + + /* Keep sending the string to the stream buffer as many bytes as possible in + * each go. Doesn't block so calls can interleave with the non-blocking + * receives performed by prvNonBlockingReceiverTask(). */ + for( ; ; ) + { + /* The whole string cannot be sent at once, so xNextChar is an index to + * the position within the string that has been sent so far. How many + * bytes are there left to send before the end of the string? */ + xBytesToSend = xStringLength - xNextChar; + + /* Attempt to send right up to the end of the string. */ + xBytesActuallySent = xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc54ByteString[ xNextChar ] ), xBytesToSend, sbDONT_BLOCK ); + prvCheckExpectedState( xBytesActuallySent <= xBytesToSend ); + + /* Move the index up the string to the next character to be sent, + * wrapping if the end of the string has been reached. */ + xNextChar += xBytesActuallySent; + prvCheckExpectedState( xNextChar <= xStringLength ); + + if( xNextChar == xStringLength ) + { + xNextChar = 0; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvNonBlockingReceiverTask( void * pvParameters ) +{ + StreamBufferHandle_t xStreamBuffer; + size_t xNextChar = 0, xReceiveLength, xBytesToTest, xStartIndex; + const size_t xStringLength = strlen( pc54ByteString ); + char cRxString[ 12 ]; /* Holds received characters. */ + BaseType_t xNonBlockingReceiveError = pdFALSE; + + /* In this case the stream buffer has already been created and is passed + * into the task using the task's parameter. */ + xStreamBuffer = ( StreamBufferHandle_t ) pvParameters; + + /* Expects to receive the pc54ByteString over and over again. Sends and + * receives are not blocking so will interleave. */ + for( ; ; ) + { + /* Attempt to receive as many bytes as possible, up to the limit of the + * Rx buffer size. */ + xReceiveLength = xStreamBufferReceive( xStreamBuffer, ( void * ) cRxString, sizeof( cRxString ), sbDONT_BLOCK ); + + if( xReceiveLength > 0 ) + { + /* xNextChar is the index into pc54ByteString that has been received + * already. If xReceiveLength bytes are added to that, will it go off + * the end of the string? If so, then first test up to the end of the + * string, then go back to the start of pc54ByteString to test the + * remains of the received data. */ + xBytesToTest = xReceiveLength; + + if( ( xNextChar + xBytesToTest ) > xStringLength ) + { + /* Cap to test the received data to the end of the string. */ + xBytesToTest = xStringLength - xNextChar; + + if( memcmp( ( const void * ) &( pc54ByteString[ xNextChar ] ), ( const void * ) cRxString, xBytesToTest ) != 0 ) + { + xNonBlockingReceiveError = pdTRUE; + } + + /* Then move back to the start of the string to test the + * remaining received bytes. */ + xNextChar = 0; + xStartIndex = xBytesToTest; + xBytesToTest = xReceiveLength - xBytesToTest; + } + else + { + /* The string didn't wrap in the buffer, so start comparing from + * the start of the received data. */ + xStartIndex = 0; + } + + /* Test the received bytes are as expected, then move the index + * along the string to the next expected char to receive. */ + if( memcmp( ( const void * ) &( pc54ByteString[ xNextChar ] ), ( const void * ) &( cRxString[ xStartIndex ] ), xBytesToTest ) != 0 ) + { + xNonBlockingReceiveError = pdTRUE; + } + + if( xNonBlockingReceiveError == pdFALSE ) + { + /* No errors detected so increment the counter that lets the + * check task know this test is still functioning correctly. */ + ulNonBlockingRxCounter++; + } + + xNextChar += xBytesToTest; + + if( xNextChar >= xStringLength ) + { + xNextChar = 0; + } + } + } +} +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + static void prvSenderTask( void * pvParameters ) + { + StreamBufferHandle_t xStreamBuffer, xTempStreamBuffer; + static uint8_t ucTempBuffer[ 10 ]; /* Just used to exercise stream buffer creating and deletion. */ + const TickType_t xTicksToWait = sbRX_TX_BLOCK_TIME, xShortDelay = pdMS_TO_TICKS( 50 ); + StaticStreamBuffer_t xStaticStreamBuffer; + size_t xNextChar = 0, xBytesToSend, xBytesActuallySent; + const size_t xStringLength = strlen( pc55ByteString ); + + /* The task's priority is used as an index into the loop counters used to + * indicate this task is still running. */ + UBaseType_t uxIndex = uxTaskPriorityGet( NULL ); + + /* Make sure a change in priority does not inadvertently result in an + * invalid array index. */ + prvCheckExpectedState( uxIndex < sbNUMBER_OF_ECHO_CLIENTS ); + + /* Avoid compiler warnings about unused parameters. */ + ( void ) pvParameters; + + xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ) / sbNUMBER_OF_SENDER_TASKS, /* The number of bytes in each buffer in the array. */ + sbTRIGGER_LEVEL_1, /* The number of bytes to be in the buffer before a task blocked to wait for data is unblocked. */ + &( ucBufferStorage[ uxIndex ][ 0 ] ), /* The address of the buffer to use within the array. */ + &( xStaticStreamBuffers[ uxIndex ] ) ); /* The static stream buffer structure to use within the array. */ + + /* Now the stream buffer has been created the receiver task can be + * created. If this sender task has the higher priority then the receiver + * task is created at the lower priority - if this sender task has the + * lower priority then the receiver task is created at the higher + * priority. */ + if( uxTaskPriorityGet( NULL ) == sbLOWER_PRIORITY ) + { + /* Here prvSingleTaskTests() performs various tests on a stream buffer + * that was created statically. */ + prvSingleTaskTests( xStreamBuffer ); + xTaskCreate( prvReceiverTask, "StrReceiver", sbSMALLER_STACK_SIZE, ( void * ) xStreamBuffer, sbHIGHER_PRIORITY, NULL ); + } + else + { + xTaskCreate( prvReceiverTask, "StrReceiver", sbSMALLER_STACK_SIZE, ( void * ) xStreamBuffer, sbLOWER_PRIORITY, NULL ); + } + + for( ; ; ) + { + /* The whole string cannot be sent at once, so xNextChar is an index + * to the position within the string that has been sent so far. How + * many bytes are there left to send before the end of the string? */ + xBytesToSend = xStringLength - xNextChar; + + /* Attempt to send right up to the end of the string. */ + xBytesActuallySent = xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc55ByteString[ xNextChar ] ), xBytesToSend, xTicksToWait ); + prvCheckExpectedState( xBytesActuallySent <= xBytesToSend ); + + /* Move the index up the string to the next character to be sent, + * wrapping if the end of the string has been reached. */ + xNextChar += xBytesActuallySent; + prvCheckExpectedState( xNextChar <= xStringLength ); + + if( xNextChar == xStringLength ) + { + xNextChar = 0; + } + + /* Increment a loop counter so a check task can tell this task is + * still running as expected. */ + ulSenderLoopCounters[ uxIndex ]++; + + if( uxTaskPriorityGet( NULL ) == sbHIGHER_PRIORITY ) + { + /* Allow other tasks to run. */ + vTaskDelay( xShortDelay ); + } + + /* This stream buffer is just created and deleted to ensure no + * issues when attempting to delete a stream buffer that was + * created using statically allocated memory. To save stack space + * the buffer is set to point to the pc55ByteString, which is a const + * string, but no data is written into the buffer so any valid address + * will do. */ + xTempStreamBuffer = xStreamBufferCreateStatic( sizeof( ucTempBuffer ), sbTRIGGER_LEVEL_1, ucTempBuffer, &xStaticStreamBuffer ); + xStreamBufferReset( xTempStreamBuffer ); + vStreamBufferDelete( xTempStreamBuffer ); + } + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + static void prvReceiverTask( void * pvParameters ) + { + StreamBufferHandle_t const pxStreamBuffer = ( StreamBufferHandle_t ) pvParameters; + char cRxString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */ + const TickType_t xTicksToWait = pdMS_TO_TICKS( 5UL ); + const size_t xStringLength = strlen( pc55ByteString ); + size_t xNextChar = 0, xReceivedLength, xBytesToReceive; + + for( ; ; ) + { + /* Attempt to receive the number of bytes to the end of the string, + * or the number of byte that can be placed into the rx buffer, + * whichever is smallest. */ + xBytesToReceive = configMIN( ( xStringLength - xNextChar ), sizeof( cRxString ) ); + + do + { + xReceivedLength = xStreamBufferReceive( pxStreamBuffer, ( void * ) cRxString, xBytesToReceive, xTicksToWait ); + } while( xReceivedLength == 0 ); + + /* Ensure the received string matches the expected string. */ + prvCheckExpectedState( memcmp( ( void * ) cRxString, ( const void * ) &( pc55ByteString[ xNextChar ] ), xReceivedLength ) == 0 ); + + /* Move the index into the string up to the end of the bytes + * received so far - wrapping if the end of the string has been + * reached. */ + xNextChar += xReceivedLength; + + if( xNextChar >= xStringLength ) + { + xNextChar = 0; + } + } + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvEchoClient( void * pvParameters ) +{ + size_t xSendLength = 0, ux; + char * pcStringToSend, * pcStringReceived, cNextChar = sbASCII_SPACE; + const TickType_t xTicksToWait = pdMS_TO_TICKS( 50 ); + StreamBufferHandle_t xTempStreamBuffer; + +/* The task's priority is used as an index into the loop counters used to + * indicate this task is still running. */ + UBaseType_t uxIndex = uxTaskPriorityGet( NULL ); + +/* Pointers to the client and server stream buffers are passed into this task + * using the task's parameter. */ + EchoStreamBuffers_t * pxStreamBuffers = ( EchoStreamBuffers_t * ) pvParameters; + + /* Prevent compiler warnings. */ + ( void ) pvParameters; + + /* Create the buffer into which strings to send to the server will be + * created, and the buffer into which strings echoed back from the server will + * be copied. */ + pcStringToSend = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES ); + pcStringReceived = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES ); + + configASSERT( pcStringToSend ); + configASSERT( pcStringReceived ); + + for( ; ; ) + { + /* Generate the length of the next string to send. */ + xSendLength++; + + /* The stream buffer is being used to hold variable length data, so + * each data item requires sizeof( size_t ) bytes to hold the data's + * length, hence the sizeof() in the if() condition below. */ + if( xSendLength > ( sbSTREAM_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) ) + { + /* Back to a string length of 1. */ + xSendLength = sizeof( char ); + } + + memset( pcStringToSend, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES ); + + for( ux = 0; ux < xSendLength; ux++ ) + { + pcStringToSend[ ux ] = cNextChar; + + cNextChar++; + + if( cNextChar > sbASCII_TILDA ) + { + cNextChar = sbASCII_SPACE; + } + } + + /* Send the generated string to the buffer. */ + do + { + ux = xStreamBufferSend( pxStreamBuffers->xEchoClientBuffer, ( void * ) pcStringToSend, xSendLength, xTicksToWait ); + } while( ux == 0 ); + + /* Wait for the string to be echoed back. */ + memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES ); + xStreamBufferReceive( pxStreamBuffers->xEchoServerBuffer, ( void * ) pcStringReceived, xSendLength, portMAX_DELAY ); + + prvCheckExpectedState( strcmp( pcStringToSend, pcStringReceived ) == 0 ); + + /* Maintain a count of the number of times this code executes so a + * check task can determine if this task is still functioning as + * expected or not. As there are two client tasks, and the priorities + * used are 0 and 1, the task's priority is used as an index into the + * loop count array. */ + ulEchoLoopCounters[ uxIndex ]++; + + /* This stream buffer is just created and deleted to ensure no memory + * leaks. */ + xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 ); + vStreamBufferDelete( xTempStreamBuffer ); + + /* The following are tests for a stream buffer of size one. */ + /* Create a buffer of size one. */ + xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_ONE, sbTRIGGER_LEVEL_1 ); + /* Ensure that the buffer was created successfully. */ + configASSERT( xTempStreamBuffer ); + + /* Send one byte to the buffer. */ + ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK ); + /* Ensure that the byte was sent successfully. */ + configASSERT( ux == 1 ); + /* Try sending another byte to the buffer. */ + ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK ); + /* Make sure that send failed as the buffer is full. */ + configASSERT( ux == 0 ); + + /* Receive one byte from the buffer. */ + memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES ); + ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK ); + /* Ensure that the receive was successful. */ + configASSERT( ux == 1 ); + /* Ensure that the correct data was received. */ + configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] ); + /* Try receiving another byte from the buffer. */ + ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK ); + /* Ensure that the receive failed as the buffer is empty. */ + configASSERT( ux == 0 ); + + /* Try sending two bytes to the buffer. Since the size of the + * buffer is one, we must not be able to send more than one. */ + ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 2, sbDONT_BLOCK ); + /* Ensure that only one byte was sent. */ + configASSERT( ux == 1 ); + + /* Try receiving two bytes from the buffer. Since the size of the + * buffer is one, we must not be able to get more than one. */ + memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES ); + ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 2, sbDONT_BLOCK ); + /* Ensure that only one byte was received. */ + configASSERT( ux == 1 ); + /* Ensure that the correct data was received. */ + configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] ); + + /* Delete the buffer. */ + vStreamBufferDelete( xTempStreamBuffer ); + } +} +/*-----------------------------------------------------------*/ + +static void prvEchoServer( void * pvParameters ) +{ + size_t xReceivedLength; + char * pcReceivedString; + EchoStreamBuffers_t xStreamBuffers; + TickType_t xTimeOnEntering; + const TickType_t xTicksToBlock = pdMS_TO_TICKS( 350UL ); + + /* Prevent compiler warnings about unused parameters. */ + ( void ) pvParameters; + + /* Create the stream buffer used to send data from the client to the server, + * and the stream buffer used to echo the data from the server back to the + * client. */ + xStreamBuffers.xEchoClientBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 ); + xStreamBuffers.xEchoServerBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 ); + configASSERT( xStreamBuffers.xEchoClientBuffer ); + configASSERT( xStreamBuffers.xEchoServerBuffer ); + + /* Create the buffer into which received strings will be copied. */ + pcReceivedString = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES ); + configASSERT( pcReceivedString ); + + /* Don't expect to receive anything yet! */ + xTimeOnEntering = xTaskGetTickCount(); + xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, xTicksToBlock ); + prvCheckExpectedState( ( ( TickType_t ) ( xTaskGetTickCount() - xTimeOnEntering ) ) >= xTicksToBlock ); + prvCheckExpectedState( xReceivedLength == 0 ); + + /* Now the stream buffers have been created the echo client task can be + * created. If this server task has the higher priority then the client task + * is created at the lower priority - if this server task has the lower + * priority then the client task is created at the higher priority. */ + if( uxTaskPriorityGet( NULL ) == sbLOWER_PRIORITY ) + { + xTaskCreate( prvEchoClient, "EchoClient", sbSMALLER_STACK_SIZE, ( void * ) &xStreamBuffers, sbHIGHER_PRIORITY, NULL ); + } + else + { + /* Here prvSingleTaskTests() performs various tests on a stream buffer + * that was created dynamically. */ + prvSingleTaskTests( xStreamBuffers.xEchoClientBuffer ); + xTaskCreate( prvEchoClient, "EchoClient", sbSMALLER_STACK_SIZE, ( void * ) &xStreamBuffers, sbLOWER_PRIORITY, NULL ); + } + + for( ; ; ) + { + memset( pcReceivedString, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES ); + + /* Has any data been sent by the client? */ + xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, portMAX_DELAY ); + + /* Should always receive data as max delay was used. */ + prvCheckExpectedState( xReceivedLength > 0 ); + + /* Echo the received data back to the client. */ + xStreamBufferSend( xStreamBuffers.xEchoServerBuffer, ( void * ) pcReceivedString, xReceivedLength, portMAX_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +void vPeriodicStreamBufferProcessing( void ) +{ + static size_t xNextChar = 0; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* Called from the tick interrupt hook. If the global stream buffer + * variable is not NULL then the prvInterruptTriggerTest() task expects a byte + * to be sent to the stream buffer on each tick interrupt. */ + if( xInterruptStreamBuffer != NULL ) + { + /* One character from the pcDataSentFromInterrupt string is sent on each + * interrupt. The task blocked on the stream buffer should not be + * unblocked until the defined trigger level is hit. */ + xStreamBufferSendFromISR( xInterruptStreamBuffer, ( const void * ) &( pcDataSentFromInterrupt[ xNextChar ] ), sizeof( char ), &xHigherPriorityTaskWoken ); + + if( xNextChar < strlen( pcDataSentFromInterrupt ) ) + { + xNextChar++; + } + } + else + { + /* Start at the beginning of the string being sent again. */ + xNextChar = 0; + } +} +/*-----------------------------------------------------------*/ + +static void prvInterruptTriggerLevelTest( void * pvParameters ) +{ + StreamBufferHandle_t xStreamBuffer; + size_t xTriggerLevel = 1, xBytesReceived; + const size_t xStreamBufferSizeBytes = ( size_t ) 9, xMaxTriggerLevel = ( size_t ) 7, xMinTriggerLevel = ( size_t ) 2; + const TickType_t xReadBlockTime = 5, xCycleBlockTime = pdMS_TO_TICKS( 100 ); + uint8_t ucRxData[ 9 ]; + BaseType_t xErrorDetected = pdFALSE; + + #ifndef configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN + const size_t xAllowableMargin = ( size_t ) 0; + #else + const size_t xAllowableMargin = ( size_t ) configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN; + #endif + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ; ; ) + { + for( xTriggerLevel = xMinTriggerLevel; xTriggerLevel < xMaxTriggerLevel; xTriggerLevel++ ) + { + /* This test is very time sensitive so delay at the beginning to ensure + * the rest of the system is up and running before starting. Delay between + * each loop to ensure the interrupt that sends to the stream buffer + * detects it needs to start sending from the start of the string again.. */ + vTaskDelay( xCycleBlockTime ); + + /* Create the stream buffer that will be used from inside the tick + * interrupt. */ + memset( ucRxData, 0x00, sizeof( ucRxData ) ); + xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel ); + configASSERT( xStreamBuffer ); + + /* Now the stream buffer has been created it can be assigned to the + * file scope variable, which will allow the tick interrupt to start + * using it. */ + taskENTER_CRITICAL(); + { + xInterruptStreamBuffer = xStreamBuffer; + } + taskEXIT_CRITICAL(); + + xBytesReceived = xStreamBufferReceive( xStreamBuffer, ( void * ) ucRxData, sizeof( ucRxData ), xReadBlockTime ); + + /* Set the file scope variable back to NULL so the interrupt doesn't + * try to use it again. */ + taskENTER_CRITICAL(); + { + xInterruptStreamBuffer = NULL; + } + taskEXIT_CRITICAL(); + + /* Now check the number of bytes received equals the trigger level, + * except in the case that the read timed out before the trigger level + * was reached. */ + if( xTriggerLevel > xReadBlockTime ) + { + /* Trigger level was greater than the block time so expect to + * time out having received xReadBlockTime bytes. */ + if( xBytesReceived > xReadBlockTime ) + { + /* Received more bytes than expected. That could happen if + * this task unblocked at the right time, but an interrupt + * added another byte to the stream buffer before this task was + * able to run. */ + if( ( xBytesReceived - xReadBlockTime ) > xAllowableMargin ) + { + xErrorDetected = pdTRUE; + } + } + else if( xReadBlockTime != xBytesReceived ) + { + /* It is possible the interrupt placed an item in the stream + * buffer before this task called xStreamBufferReceive(), but + * if that is the case then xBytesReceived will only every be + * 0 as the interrupt will only have executed once. */ + if( xBytesReceived != 1 ) + { + xErrorDetected = pdTRUE; + } + } + } + else if( xTriggerLevel < xReadBlockTime ) + { + /* Trigger level was less than the block time so we expect to + * have received the trigger level number of bytes - could be more + * though depending on other activity between the task being + * unblocked and the task reading the number of bytes received. It + * could also be less if the interrupt already put something in the + * stream buffer before this task attempted to read it - in which + * case the task would have returned the available bytes immediately + * without ever blocking - in that case the bytes received will + * only ever be 1 as the interrupt would not have executed more + * than one in that time unless this task has too low a priority. */ + if( xBytesReceived < xTriggerLevel ) + { + if( xBytesReceived != 1 ) + { + xErrorDetected = pdTRUE; + } + } + else if( ( xBytesReceived - xTriggerLevel ) > xAllowableMargin ) + { + xErrorDetected = pdTRUE; + } + } + else + { + /* The trigger level equalled the block time, so expect to + * receive no greater than the block time. It could also be less + * if the interrupt already put something in the stream buffer + * before this task attempted to read it - in which case the task + * would have returned the available bytes immediately without ever + * blocking - in that case the bytes received would only ever be 1 + * because the interrupt is not going to execute twice in that time + * unless this task is running a too low a priority. */ + if( xBytesReceived < xReadBlockTime ) + { + if( xBytesReceived != 1 ) + { + xErrorDetected = pdTRUE; + } + } + else if( ( xBytesReceived - xReadBlockTime ) > xAllowableMargin ) + { + xErrorDetected = pdTRUE; + } + } + + if( xBytesReceived > sizeof( ucRxData ) ) + { + xErrorDetected = pdTRUE; + } + else if( memcmp( ( void * ) ucRxData, ( const void * ) pcDataSentFromInterrupt, xBytesReceived ) != 0 ) + { + /* Received data didn't match that expected. */ + xErrorDetected = pdTRUE; + } + + if( xErrorDetected == pdFALSE ) + { + /* Increment the cycle counter so the 'check' task knows this test + * is still running without error. */ + ulInterruptTriggerCounter++; + } + + /* Tidy up ready for the next loop. */ + vStreamBufferDelete( xStreamBuffer ); + } + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xAreStreamBufferTasksStillRunning( void ) +{ + static uint32_t ulLastEchoLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 }; + static uint32_t ulLastNonBlockingRxCounter = 0; + static uint32_t ulLastInterruptTriggerCounter = 0; + BaseType_t x; + + for( x = 0; x < sbNUMBER_OF_ECHO_CLIENTS; x++ ) + { + if( ulLastEchoLoopCounters[ x ] == ulEchoLoopCounters[ x ] ) + { + xErrorStatus = pdFAIL; + } + else + { + ulLastEchoLoopCounters[ x ] = ulEchoLoopCounters[ x ]; + } + } + + if( ulNonBlockingRxCounter == ulLastNonBlockingRxCounter ) + { + xErrorStatus = pdFAIL; + } + else + { + ulLastNonBlockingRxCounter = ulNonBlockingRxCounter; + } + + if( ulLastInterruptTriggerCounter == ulInterruptTriggerCounter ) + { + xErrorStatus = pdFAIL; + } + else + { + ulLastInterruptTriggerCounter = ulInterruptTriggerCounter; + } + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + static uint32_t ulLastSenderLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 }; + + for( x = 0; x < sbNUMBER_OF_SENDER_TASKS; x++ ) + { + if( ulLastSenderLoopCounters[ x ] == ulSenderLoopCounters[ x ] ) + { + xErrorStatus = pdFAIL; + } + else + { + ulLastSenderLoopCounters[ x ] = ulSenderLoopCounters[ x ]; + } + } + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + return xErrorStatus; +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/StreamBufferInterrupt.c b/SOFTWARE-FreeRTOS/Common/Minimal/StreamBufferInterrupt.c new file mode 100644 index 0000000..b974ffe --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/StreamBufferInterrupt.c @@ -0,0 +1,228 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A simple example that shows a stream buffer being used to pass data from an + * interrupt to a task. + * + * There are two strings, pcStringToSend and pcStringToReceive, where + * pcStringToReceive is a substring of pcStringToSend. The interrupt sends + * a few bytes of pcStringToSend to a stream buffer ever few times that it + * executes. A task reads the bytes from the stream buffer, looking for the + * substring, and flagging an error if the received data is invalid. + */ + +/* Standard includes. */ +#include "stdio.h" +#include "string.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "stream_buffer.h" + +/* Demo app includes. */ +#include "StreamBufferInterrupt.h" + +#define sbiSTREAM_BUFFER_LENGTH_BYTES ( ( size_t ) 100 ) +#define sbiSTREAM_BUFFER_TRIGGER_LEVEL_10 ( ( BaseType_t ) 10 ) + +/*-----------------------------------------------------------*/ + +/* Implements the task that receives a stream of bytes from the interrupt. */ +static void prvReceivingTask( void * pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The stream buffer that is used to send data from an interrupt to the task. */ +static StreamBufferHandle_t xStreamBuffer = NULL; + +/* The string that is sent from the interrupt to the task four bytes at a + * time. Must be multiple of 4 bytes long as the ISR sends 4 bytes at a time*/ +static const char * pcStringToSend = "_____Hello FreeRTOS_____"; + +/* The string to task is looking for, which must be a substring of + * pcStringToSend. */ +static const char * pcStringToReceive = "Hello FreeRTOS"; + +/* Set to pdFAIL if anything unexpected happens. */ +static BaseType_t xDemoStatus = pdPASS; + +/* Incremented each time pcStringToReceive is correctly received, provided no + * errors have occurred. Used so the check task can check this task is still + * running as expected. */ +static uint32_t ulCycleCount = 0; + +/*-----------------------------------------------------------*/ + +void vStartStreamBufferInterruptDemo( void ) +{ + /* Create the stream buffer that sends data from the interrupt to the + * task, and create the task. */ + xStreamBuffer = xStreamBufferCreate( /* The buffer length in bytes. */ + sbiSTREAM_BUFFER_LENGTH_BYTES, + /* The stream buffer's trigger level. */ + sbiSTREAM_BUFFER_TRIGGER_LEVEL_10 ); + + xTaskCreate( prvReceivingTask, /* The function that implements the task. */ + "StrIntRx", /* Human readable name for the task. */ + configMINIMAL_STACK_SIZE, /* Stack size (in words!). */ + NULL, /* Task parameter is not used. */ + tskIDLE_PRIORITY + 2, /* The priority at which the task is created. */ + NULL ); /* No use for the task handle. */ +} +/*-----------------------------------------------------------*/ + +static void prvReceivingTask( void * pvParameters ) +{ + char cRxBuffer[ 20 ]; + BaseType_t xNextByte = 0; + + /* Remove warning about unused parameters. */ + ( void ) pvParameters; + + /* Make sure the string will fit in the Rx buffer, including the NULL + * terminator. */ + configASSERT( sizeof( cRxBuffer ) > strlen( pcStringToReceive ) ); + + /* Make sure the stream buffer has been created. */ + configASSERT( xStreamBuffer != NULL ); + + /* Start with the Rx buffer in a known state. */ + memset( cRxBuffer, 0x00, sizeof( cRxBuffer ) ); + + for( ; ; ) + { + /* Keep receiving characters until the end of the string is received. + * Note: An infinite block time is used to simplify the example. Infinite + * block times are not recommended in production code as they do not allow + * for error recovery. */ + xStreamBufferReceive( /* The stream buffer data is being received from. */ + xStreamBuffer, + /* Where to place received data. */ + ( void * ) &( cRxBuffer[ xNextByte ] ), + /* The number of bytes to receive. */ + sizeof( char ), + + /* The time to wait for the next data if the buffer + * is empty. */ + portMAX_DELAY ); + + /* If xNextByte is 0 then this task is looking for the start of the + * string, which is 'H'. */ + if( xNextByte == 0 ) + { + if( cRxBuffer[ xNextByte ] == 'H' ) + { + /* The start of the string has been found. Now receive + * characters until the end of the string is found. */ + xNextByte++; + } + } + else + { + /* Receiving characters while looking for the end of the string, + * which is an 'S'. */ + if( cRxBuffer[ xNextByte ] == 'S' ) + { + /* The string has now been received. Check its validity. */ + if( strcmp( cRxBuffer, pcStringToReceive ) != 0 ) + { + xDemoStatus = pdFAIL; + } + + /* Return to start looking for the beginning of the string + * again. */ + memset( cRxBuffer, 0x00, sizeof( cRxBuffer ) ); + xNextByte = 0; + + /* Increment the cycle count as an indication to the check task + * that this demo is still running. */ + if( xDemoStatus == pdPASS ) + { + ulCycleCount++; + } + } + else + { + /* Receive the next character the next time around, while + * continuing to look for the end of the string. */ + xNextByte++; + + configASSERT( ( size_t ) xNextByte < sizeof( cRxBuffer ) ); + } + } + } +} +/*-----------------------------------------------------------*/ + +void vBasicStreamBufferSendFromISR( void ) +{ + static size_t xNextByteToSend = 0; + const BaseType_t xCallsBetweenSends = 100, xBytesToSend = 4; + static BaseType_t xCallCount = 0; + + /* Is it time to write to the stream buffer again? */ + xCallCount++; + + if( xCallCount > xCallsBetweenSends ) + { + xCallCount = 0; + + /* Send the next four bytes to the stream buffer. */ + xStreamBufferSendFromISR( xStreamBuffer, + ( const void * ) ( pcStringToSend + xNextByteToSend ), + xBytesToSend, + NULL ); + + /* Send the next four bytes the next time around, wrapping to the start + * of the string if necessary. */ + xNextByteToSend += xBytesToSend; + + if( xNextByteToSend >= strlen( pcStringToSend ) ) + { + xNextByteToSend = 0; + } + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsInterruptStreamBufferDemoStillRunning( void ) +{ + uint32_t ulLastCycleCount = 0; + + /* Check the demo is still running. */ + if( ulLastCycleCount == ulCycleCount ) + { + xDemoStatus = pdFAIL; + } + else + { + ulLastCycleCount = ulCycleCount; + } + + return xDemoStatus; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/TaskNotify.c b/SOFTWARE-FreeRTOS/Common/Minimal/TaskNotify.c new file mode 100644 index 0000000..b87c9d6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/TaskNotify.c @@ -0,0 +1,720 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Tests the behaviour of direct task notifications. + */ + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" + +/* Demo program include files. */ +#include "TaskNotify.h" + +/* Allow parameters to be overridden on a demo by demo basis. */ +#ifndef notifyNOTIFIED_TASK_STACK_SIZE + #define notifyNOTIFIED_TASK_STACK_SIZE configMINIMAL_STACK_SIZE +#endif + +#define notifyTASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* Constants used in tests when setting/clearing bits. */ +#define notifyUINT32_MAX ( ( uint32_t ) 0xffffffff ) +#define notifyUINT32_HIGH_BYTE ( ( uint32_t ) 0xff000000 ) +#define notifyUINT32_LOW_BYTE ( ( uint32_t ) 0x000000ff ) + +#define notifySUSPENDED_TEST_TIMER_PERIOD pdMS_TO_TICKS( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Implementation of the task that gets notified. + */ +static void prvNotifiedTask( void * pvParameters ); + +/* + * Performs a few initial tests that can be done prior to creating the second + * task. + */ +static void prvSingleTaskTests( void ); + +/* + * Software timer callback function from which xTaskNotify() is called. + */ +static void prvNotifyingTimer( TimerHandle_t xTimer ); + +/* + * Utility function to create pseudo random numbers. + */ +static UBaseType_t prvRand( void ); + +/* + * Callback for a timer that is used during preliminary testing. The timer + * tests the behaviour when 1: a task waiting for a notification is suspended + * and then resumed without ever receiving a notification, and 2: when a task + * waiting for a notification receives a notification while it is suspended. + */ +static void prvSuspendedTaskTimerTestCallback( TimerHandle_t xExpiredTimer ); + +/*-----------------------------------------------------------*/ + +/* Used to latch errors during the test's execution. */ +static BaseType_t xErrorStatus = pdPASS; + +/* Used to ensure the task has not stalled. */ +static volatile uint32_t ulNotifyCycleCount = 0; + +/* The handle of the task that receives the notifications. */ +static TaskHandle_t xTaskToNotify = NULL; + +/* Used to count the notifications sent to the task from a software timer and + * the number of notifications received by the task from the software timer. The + * two should stay synchronised. */ +static uint32_t ulTimerNotificationsReceived = 0UL, ulTimerNotificationsSent = 0UL; + +/* The timer used to notify the task. */ +static TimerHandle_t xTimer = NULL; + +/* Used by the pseudo random number generating function. */ +static size_t uxNextRand = 0; + +/*-----------------------------------------------------------*/ + +void vStartTaskNotifyTask( void ) +{ + /* Create the task that performs some tests by itself, then loops around + * being notified by both a software timer and an interrupt. */ + xTaskCreate( prvNotifiedTask, /* Function that implements the task. */ + "Notified", /* Text name for the task - for debugging only - not used by the kernel. */ + notifyNOTIFIED_TASK_STACK_SIZE, /* Task's stack size in words, not bytes!. */ + NULL, /* Task parameter, not used in this case. */ + notifyTASK_PRIORITY, /* Task priority, 0 is the lowest. */ + &xTaskToNotify ); /* Used to pass a handle to the task out is needed, otherwise set to NULL. */ + + /* Pseudo seed the random number generator. */ + uxNextRand = ( size_t ) prvRand; +} +/*-----------------------------------------------------------*/ + +static void prvSingleTaskTests( void ) +{ + const TickType_t xTicksToWait = pdMS_TO_TICKS( 100UL ); + BaseType_t xReturned; + uint32_t ulNotifiedValue, ulLoop, ulNotifyingValue, ulPreviousValue, ulExpectedValue; + TickType_t xTimeOnEntering; + const uint32_t ulFirstNotifiedConst = 100001UL, ulSecondNotifiedValueConst = 5555UL, ulMaxLoops = 5UL; + const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL; + TimerHandle_t xSingleTaskTimer; + + + /* ------------------------------------------------------------------------ + * Check blocking when there are no notifications. */ + xTimeOnEntering = xTaskGetTickCount(); + xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Should have blocked for the entire block time. */ + if( ( xTaskGetTickCount() - xTimeOnEntering ) < xTicksToWait ) + { + xErrorStatus = pdFAIL; + } + + configASSERT( xReturned == pdFAIL ); + configASSERT( ulNotifiedValue == 0UL ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + + + + /* ------------------------------------------------------------------------ + * Check no blocking when notifications are pending. First notify itself - + * this would not be a normal thing to do and is done here for test purposes + * only. */ + xReturned = xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue ); + + /* Even through the 'without overwrite' action was used the update should + * have been successful. */ + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* No bits should have been pending previously. */ + configASSERT( ulPreviousValue == 0 ); + ( void ) ulPreviousValue; + + /* The task should now have a notification pending, and so not time out. */ + xTimeOnEntering = xTaskGetTickCount(); + xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait ); + + if( ( xTaskGetTickCount() - xTimeOnEntering ) >= xTicksToWait ) + { + xErrorStatus = pdFAIL; + } + + /* The task should have been notified, and the notified value should + * be equal to ulFirstNotifiedConst. */ + configASSERT( xReturned == pdPASS ); + configASSERT( ulNotifiedValue == ulFirstNotifiedConst ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + + /* Incremented to show the task is still running. */ + ulNotifyCycleCount++; + + + + /*------------------------------------------------------------------------- + * Check the non-overwriting functionality. The notification is done twice + * using two different notification values. The action says don't overwrite so + * only the first notification should pass and the value read back should also + * be that used with the first notification. */ + xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + xReturned = xTaskNotify( xTaskToNotify, ulSecondNotifiedValueConst, eSetValueWithoutOverwrite ); + configASSERT( xReturned == pdFAIL ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Waiting for the notification should now return immediately so a block + * time of zero is used. */ + xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 ); + + configASSERT( xReturned == pdPASS ); + configASSERT( ulNotifiedValue == ulFirstNotifiedConst ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + + + + /*------------------------------------------------------------------------- + * Do the same again, only this time use the overwriting version. This time + * both notifications should pass, and the value written the second time should + * overwrite the value written the first time, and so be the value that is read + * back. */ + xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithOverwrite ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + xReturned = xTaskNotify( xTaskToNotify, ulSecondNotifiedValueConst, eSetValueWithOverwrite ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst ); + ( void ) ulNotifiedValue; + + + + /*------------------------------------------------------------------------- + * Check notifications with no action pass without updating the value. Even + * though ulFirstNotifiedConst is used as the value the value read back should + * remain at ulSecondNotifiedConst. */ + xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eNoAction ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 ); + configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst ); + ( void ) ulNotifiedValue; /* In case configASSERT() is not defined. */ + + /*------------------------------------------------------------------------- + * Check incrementing values. Send ulMaxLoop increment notifications, then + * ensure the received value is as expected - which should be + * ulSecondNotificationValueConst plus how ever many times to loop iterated. */ + for( ulLoop = 0; ulLoop < ulMaxLoops; ulLoop++ ) + { + xReturned = xTaskNotify( xTaskToNotify, 0, eIncrement ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + } + + xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdPASS ); + configASSERT( ulNotifiedValue == ( ulSecondNotifiedValueConst + ulMaxLoops ) ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + + /* Should not be any notifications pending now. */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdFAIL ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + + + + /*------------------------------------------------------------------------- + * Check all bits can be set by notifying the task with one additional bit set + * on each notification, and exiting the loop when all the bits are found to be + * set. As there are 32-bits the loop should execute 32 times before all the + * bits are found to be set. */ + ulNotifyingValue = 0x01; + ulLoop = 0; + + /* Start with all bits clear. */ + xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 ); + + do + { + /* Set the next bit in the task's notified value. */ + xTaskNotify( xTaskToNotify, ulNotifyingValue, eSetBits ); + + /* Wait for the notified value - which of course will already be + * available. Don't clear the bits on entry or exit as this loop is exited + * when all the bits are set. */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + ulLoop++; + + /* Use the next bit on the next iteration around this loop. */ + ulNotifyingValue <<= 1UL; + } while( ulNotifiedValue != notifyUINT32_MAX ); + + /* As a 32-bit value was used the loop should have executed 32 times before + * all the bits were set. */ + configASSERT( ulLoop == 32 ); + + + + /*------------------------------------------------------------------------- + * Check bits are cleared on entry but not on exit when a notification fails + * to arrive before timing out - both with and without a timeout value. Wait + * for the notification again - but this time it is not given by anything and + * should return pdFAIL. The parameters are set to clear bit zero on entry and + * bit one on exit. As no notification was received only the bit cleared on + * entry should actually get cleared. */ + xReturned = xTaskNotifyWait( ulBit0, ulBit1, &ulNotifiedValue, xTicksToWait ); + configASSERT( xReturned == pdFAIL ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Notify the task with no action so as not to update the bits even though + * notifyUINT32_MAX is used as the notification value. */ + xTaskNotify( xTaskToNotify, notifyUINT32_MAX, eNoAction ); + + /* Reading back the value should should find bit 0 is clear, as this was + * cleared on entry, but bit 1 is not clear as it will not have been cleared on + * exit as no notification was received. */ + xReturned = xTaskNotifyWait( 0x00UL, 0x00UL, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdPASS ); + configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + + + /*------------------------------------------------------------------------- + * Now try clearing the bit on exit. For that to happen a notification must be + * received, so the task is notified first. */ + xTaskNotify( xTaskToNotify, 0, eNoAction ); + xTaskNotifyWait( 0x00, ulBit1, &ulNotifiedValue, 0 ); + + /* However as the bit is cleared on exit, after the returned notification + * value is set, the returned notification value should not have the bit + * cleared... */ + configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) ); + + /* ...but reading the value back again should find that the bit was indeed + * cleared internally. The returned value should be pdFAIL however as nothing + * has notified the task in the mean time. */ + xReturned = xTaskNotifyWait( 0x00, 0x00, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdFAIL ); + configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + + + /*------------------------------------------------------------------------- + * Now try querying the previous value while notifying a task. */ + xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue ); + configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) ); + + /* Clear all bits. */ + xTaskNotifyWait( 0x00, notifyUINT32_MAX, &ulNotifiedValue, 0 ); + xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue ); + configASSERT( ulPreviousValue == 0 ); + + ulExpectedValue = 0; + + for( ulLoop = 0x01; ulLoop < 0x80UL; ulLoop <<= 1UL ) + { + /* Set the next bit up, and expect to receive the last bits set (so + * the previous value will not yet have the bit being set this time + * around). */ + xTaskNotifyAndQuery( xTaskToNotify, ulLoop, eSetBits, &ulPreviousValue ); + configASSERT( ulExpectedValue == ulPreviousValue ); + ulExpectedValue |= ulLoop; + } + + /* ------------------------------------------------------------------------ + * Clear the previous notifications. */ + xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 ); + + /* The task should not have any notifications pending, so an attempt to clear + * the notification state should fail. */ + configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE ); + + /* Get the task to notify itself. This is not a normal thing to do, and is + * only done here for test purposes. */ + xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue ); + + /* Now the notification state should be eNotified, so it should now be + * possible to clear the notification state. */ + configASSERT( xTaskNotifyStateClear( NULL ) == pdTRUE ); + configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE ); + + + + /* ------------------------------------------------------------------------ + * Clear bits in the notification value. */ + + /* Get the task to set all bits its own notification value. This is not a + * normal thing to do, and is only done here for test purposes. */ + xTaskNotify( xTaskToNotify, notifyUINT32_MAX, eSetBits ); + + /* Now clear the top bytes - the returned value from the first call should + * indicate that previously all bits were set. */ + configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_HIGH_BYTE ) == notifyUINT32_MAX ); + + /* Next clear the bottom bytes - the returned value this time should indicate + * that the top byte was clear (before the bottom byte was cleared. */ + configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_LOW_BYTE ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE ) ); + + /* Next clear all bytes - the returned value should indicate that previously the + * high and low bytes were clear. */ + configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_MAX ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE & ~notifyUINT32_LOW_BYTE ) ); + + /* Now all bits should be clear. */ + configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_MAX ) == 0 ); + configASSERT( ulTaskNotifyValueClear( xTaskToNotify, 0UL ) == 0 ); + configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_MAX ) == 0 ); + + /* Now the notification state should be eNotified, so it should now be + * possible to clear the notification state. */ + configASSERT( xTaskNotifyStateClear( NULL ) == pdTRUE ); + configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE ); + + + + /* ------------------------------------------------------------------------ + * Create a timer that will try notifying this task while it is suspended. */ + xSingleTaskTimer = xTimerCreate( "SingleNotify", notifySUSPENDED_TEST_TIMER_PERIOD, pdFALSE, NULL, prvSuspendedTaskTimerTestCallback ); + configASSERT( xSingleTaskTimer ); + + /* Incremented to show the task is still running. */ + ulNotifyCycleCount++; + + /* Ensure no notifications are pending. */ + xTaskNotifyWait( notifyUINT32_MAX, 0, NULL, 0 ); + + /* Raise the task's priority so it can suspend itself before the timer + * expires. */ + vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 ); + + /* Start the timer that will try notifying this task while it is + * suspended, then wait for a notification. The first time the callback + * executes the timer will suspend the task, then resume the task, without + * ever sending a notification to the task. */ + ulNotifiedValue = 0; + xTimerStart( xSingleTaskTimer, portMAX_DELAY ); + + /* Check a notification is not received. */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, portMAX_DELAY ); + configASSERT( xReturned == pdFALSE ); + configASSERT( ulNotifiedValue == 0 ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + + /* Incremented to show the task is still running. */ + ulNotifyCycleCount++; + + /* Start the timer that will try notifying this task while it is + * suspended, then wait for a notification. The second time the callback + * executes the timer will suspend the task, notify the task, then resume the + * task (previously it was suspended and resumed without being notified). */ + xTimerStart( xSingleTaskTimer, portMAX_DELAY ); + + /* Check a notification is received. */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, portMAX_DELAY ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* In case configASSERT() is not defined. */ + configASSERT( ulNotifiedValue != 0 ); + + /* Return the task to its proper priority and delete the timer as it is + * not used again. */ + vTaskPrioritySet( NULL, notifyTASK_PRIORITY ); + xTimerDelete( xSingleTaskTimer, portMAX_DELAY ); + + /* Incremented to show the task is still running. */ + ulNotifyCycleCount++; + + /* Leave all bits cleared. */ + xTaskNotifyWait( notifyUINT32_MAX, 0, NULL, 0 ); +} +/*-----------------------------------------------------------*/ + +static void prvSuspendedTaskTimerTestCallback( TimerHandle_t xExpiredTimer ) +{ + static uint32_t ulCallCount = 0; + + /* Remove compiler warnings about unused parameters. */ + ( void ) xExpiredTimer; + + /* Callback for a timer that is used during preliminary testing. The timer + * tests the behaviour when 1: a task waiting for a notification is suspended + * and then resumed without ever receiving a notification, and 2: when a task + * waiting for a notification receives a notification while it is suspended. */ + + if( ulCallCount == 0 ) + { + vTaskSuspend( xTaskToNotify ); + configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended ); + vTaskResume( xTaskToNotify ); + } + else + { + vTaskSuspend( xTaskToNotify ); + + /* Sending a notification while the task is suspended should pass, but + * not cause the task to resume. ulCallCount is just used as a convenient + * non-zero value. */ + xTaskNotify( xTaskToNotify, ulCallCount, eSetValueWithOverwrite ); + + /* Make sure giving the notification didn't resume the task. */ + configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended ); + + vTaskResume( xTaskToNotify ); + } + + ulCallCount++; +} +/*-----------------------------------------------------------*/ + +static void prvNotifyingTimer( TimerHandle_t xNotUsed ) +{ + ( void ) xNotUsed; + + xTaskNotifyGive( xTaskToNotify ); + + /* This value is also incremented from an interrupt. */ + taskENTER_CRITICAL(); + { + ulTimerNotificationsSent++; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvNotifiedTask( void * pvParameters ) +{ + const TickType_t xMaxPeriod = pdMS_TO_TICKS( 90 ), xMinPeriod = pdMS_TO_TICKS( 10 ), xDontBlock = 0; + TickType_t xPeriod; + const uint32_t ulCyclesToRaisePriority = 50UL; + + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + /* Run a few tests that can be done from a single task before entering the + * main loop. */ + prvSingleTaskTests(); + + /* Create the software timer that is used to send notifications to this + * task. Notifications are also received from an interrupt. */ + xTimer = xTimerCreate( "Notifier", xMaxPeriod, pdFALSE, NULL, prvNotifyingTimer ); + + for( ; ; ) + { + /* Start the timer again with a different period. Sometimes the period + * will be higher than the task's block time, sometimes it will be lower + * than the task's block time. */ + xPeriod = prvRand() % xMaxPeriod; + + if( xPeriod < xMinPeriod ) + { + xPeriod = xMinPeriod; + } + + /* Change the timer period and start the timer. */ + xTimerChangePeriod( xTimer, xPeriod, portMAX_DELAY ); + + /* Block waiting for the notification again with a different period. + * Sometimes the period will be higher than the task's block time, + * sometimes it will be lower than the task's block time. */ + xPeriod = prvRand() % xMaxPeriod; + + if( xPeriod < xMinPeriod ) + { + xPeriod = xMinPeriod; + } + + /* Block to wait for a notification but without clearing the + * notification count, so only add one to the count of received + * notifications as any other notifications will remain pending. */ + if( ulTaskNotifyTake( pdFALSE, xPeriod ) != 0 ) + { + ulTimerNotificationsReceived++; + } + + /* Take a notification without clearing again, but this time without a + * block time specified. */ + if( ulTaskNotifyTake( pdFALSE, xDontBlock ) != 0 ) + { + ulTimerNotificationsReceived++; + } + + /* Wait for the next notification from the timer, clearing all + * notifications if one is received, so this time adding the total number + * of notifications that were pending as none will be left pending after + * the function call. */ + ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, xPeriod ); + + /* Occasionally raise the priority of the task being notified to test + * the path where the task is notified from an ISR and becomes the highest + * priority ready state task, but the pxHigherPriorityTaskWoken parameter + * is NULL (which it is in the tick hook that sends notifications to this + * task). */ + if( ( ulNotifyCycleCount % ulCyclesToRaisePriority ) == 0 ) + { + vTaskPrioritySet( xTaskToNotify, configMAX_PRIORITIES - 1 ); + + /* Wait for the next notification again, clearing all notifications + * if one is received, but this time blocking indefinitely. */ + ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, portMAX_DELAY ); + + /* Reset the priority. */ + vTaskPrioritySet( xTaskToNotify, notifyTASK_PRIORITY ); + } + else + { + /* Wait for the next notification again, clearing all notifications + * if one is received, but this time blocking indefinitely. */ + ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, portMAX_DELAY ); + } + + /* Incremented to show the task is still running. */ + ulNotifyCycleCount++; + } +} +/*-----------------------------------------------------------*/ + +void xNotifyTaskFromISR( void ) +{ + static BaseType_t xCallCount = 0, xAPIToUse = 0; + const BaseType_t xCallInterval = pdMS_TO_TICKS( 50 ); + uint32_t ulPreviousValue; + const uint32_t ulUnexpectedValue = 0xff; + + /* Check the task notification demo tasks were actually created. */ + configASSERT( xTaskToNotify ); + + /* The task performs some tests before starting the timer that gives the + * notification from this interrupt. If the timer has not been created yet + * then the initial tests have not yet completed and the notification should + * not be sent. */ + if( xTimer != NULL ) + { + xCallCount++; + + if( xCallCount >= xCallInterval ) + { + /* It is time to 'give' the notification again. */ + xCallCount = 0; + + /* Test using both vTaskNotifyGiveFromISR(), xTaskNotifyFromISR() + * and xTaskNotifyAndQueryFromISR(). */ + switch( xAPIToUse ) + { + case 0: + vTaskNotifyGiveFromISR( xTaskToNotify, NULL ); + xAPIToUse++; + break; + + case 1: + xTaskNotifyFromISR( xTaskToNotify, 0, eIncrement, NULL ); + xAPIToUse++; + break; + + case 2: + ulPreviousValue = ulUnexpectedValue; + xTaskNotifyAndQueryFromISR( xTaskToNotify, 0, eIncrement, &ulPreviousValue, NULL ); + configASSERT( ulPreviousValue != ulUnexpectedValue ); + xAPIToUse = 0; + break; + + default: /* Should never get here!. */ + break; + } + + ulTimerNotificationsSent++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check the created tasks are still running and have not + * detected any errors. */ +BaseType_t xAreTaskNotificationTasksStillRunning( void ) +{ + static uint32_t ulLastNotifyCycleCount = 0; + const uint32_t ulMaxSendReceiveDeviation = 5UL; + + /* Check the cycle count is still incrementing to ensure the task is still + * actually running. */ + if( ulLastNotifyCycleCount == ulNotifyCycleCount ) + { + xErrorStatus = pdFAIL; + } + else + { + ulLastNotifyCycleCount = ulNotifyCycleCount; + } + + /* Check the count of 'takes' from the software timer is keeping track with + * the amount of 'gives'. */ + if( ulTimerNotificationsSent > ulTimerNotificationsReceived ) + { + if( ( ulTimerNotificationsSent - ulTimerNotificationsReceived ) > ulMaxSendReceiveDeviation ) + { + xErrorStatus = pdFAIL; + } + } + + return xErrorStatus; +} +/*-----------------------------------------------------------*/ + +static UBaseType_t prvRand( void ) +{ + const size_t uxMultiplier = ( size_t ) 0x015a4e35, uxIncrement = ( size_t ) 1; + + /* Utility function to generate a pseudo random number. */ + uxNextRand = ( uxMultiplier * uxNextRand ) + uxIncrement; + return( ( uxNextRand >> 16 ) & ( ( size_t ) 0x7fff ) ); +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/TaskNotifyArray.c b/SOFTWARE-FreeRTOS/Common/Minimal/TaskNotifyArray.c new file mode 100644 index 0000000..1a136fa --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/TaskNotifyArray.c @@ -0,0 +1,1218 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Tests the behaviour of arrays of task notifications per task. The tests in this + * file are additive to those implemented in FreeRTOS/Demo/Common/Minimal/TaskNotify.c. + */ + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" + +/* Demo program include files. */ +#include "TaskNotifyArray.h" + +#if ( configTASK_NOTIFICATION_ARRAY_ENTRIES < 3 ) + #error This file tests direct to task notification arrays and needs configTASK_NOTIFICATION_ARRAY_ENTRIES to be at least 3. +#endif + +/* Allow parameters to be overridden on a demo by demo basis. */ +#ifndef notifyNOTIFY_ARRAY_TASK_STACK_SIZE + #define notifyNOTIFY_ARRAY_TASK_STACK_SIZE configMINIMAL_STACK_SIZE +#endif + +#define notifyTASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* Constants used in tests when setting/clearing bits. */ +#define notifyUINT32_MAX ( ( uint32_t ) 0xffffffff ) +#define notifyUINT32_HIGH_BYTE ( ( uint32_t ) 0xff000000 ) +#define notifyUINT32_LOW_BYTE ( ( uint32_t ) 0x000000ff ) + +/*-----------------------------------------------------------*/ + +/* + * Implementation of the task that runs the tests - the task runs some tests + * itself, and others where notifications are sent from a software timer or + * an interrupt (specifically the tick hook function). + */ +static void prvNotifiedTask( void * pvParameters ); + +/* + * Performs the tests that don't require notifications to be sent from a + * remote source. + */ +static void prvSingleTaskTests( void ); + +/* + * Uses a software timer to send notifications to the task while the task is + * suspended. + */ +static void prvTestNotifyTaskWhileSuspended( void ); + +/* + * Uses a software timer to send notifications to the index within the array of + * task notifications on which the task is blocked. The task should unblock and + * the state of all the other task notifications within the array should remain + * unchanged. + */ +static void prvBlockOnTheNotifiedIndexed( void ); + +/* + * As per prvBlockOnTheNotifiedIndexed(), but this time the notification comes from + * the tick hook function, so from an interrupt rather than from a software timer. + */ +static void prvBlockOnNotificationsComingFromInterrupts( void ); + +/* + * As per prvBlockOnTheNotifiedIndexed(), except this time the notification is + * sent to an index within the task notification array on which the task is not + * blocked, so this time the task should not unblock and the state of all the + * task notifications other than the one to which the notification was actually + * sent should remain unchanged. + */ +static void prvBlockOnANonNotifiedIndexed( void ); + +/* + * Callback of the software timer used to send notifications for the + * prvBlockOnTheNotifiedIndexed() and prvBlockOnANonNotifiedIndexed() tests. + */ +static void prvNotifyingTimerCallback( TimerHandle_t xTimer ); + +/* + * Callback for a timer that is used by the prvTestNotifyTaskWhileSuspended() + * test. + */ +static void prvSuspendedTaskTimerTestCallback( TimerHandle_t xExpiredTimer ); + +/* + * Utility function to create pseudo random numbers. + */ +static UBaseType_t prvRand( void ); + + +/*-----------------------------------------------------------*/ + +/* Counters used to check the task has not stalled. ulFineCycleCount is + * incremented within each test. ulCourseCycleCounter is incremented one every + * loop of all the tests to ensure each test is actually executing. The check task + * calls xAreTaskNotificationArrayTasksStillRunning() (implemented within this + * file) to check both counters are changing. */ +static volatile uint32_t ulFineCycleCount = 0, ulCourseCycleCounter = 0; + +/* The handle of the task that runs the tests and receives the notifications + * from the software timers and interrupts. */ +static TaskHandle_t xTaskToNotify = NULL; + +/* The software timers used to send notifications to the main test task. */ +static TimerHandle_t xIncrementingIndexTimer = NULL; +static TimerHandle_t xNotifyWhileSuspendedTimer = NULL; + +/* Used by the pseudo random number generating function. */ +static size_t uxNextRand = 0; + +/* Used to communicate when to send a task notification to the tick hook tests. */ +static volatile BaseType_t xSendNotificationFromISR = pdFALSE; + +/*-----------------------------------------------------------*/ + +void vStartTaskNotifyArrayTask( void ) +{ + const TickType_t xIncrementingIndexTimerPeriod = pdMS_TO_TICKS( 100 ); + const TickType_t xSuspendTimerPeriod = pdMS_TO_TICKS( 50 ); + + /* Create the software timers used for these tests. The timer callbacks send + * notifications to this task. */ + xNotifyWhileSuspendedTimer = xTimerCreate( "SingleNotify", xSuspendTimerPeriod, pdFALSE, NULL, prvSuspendedTaskTimerTestCallback ); + xIncrementingIndexTimer = xTimerCreate( "Notifier", xIncrementingIndexTimerPeriod, pdFALSE, NULL, prvNotifyingTimerCallback ); + configASSERT( xNotifyWhileSuspendedTimer ); + configASSERT( xIncrementingIndexTimer ); + + /* Create the task that performs some tests by itself, then loops around + * being notified by both a software timer and an interrupt. */ + xTaskCreate( prvNotifiedTask, /* Function that implements the task. */ + "ArrayNotified", /* Text name for the task - for debugging only - not used by the kernel. */ + notifyNOTIFY_ARRAY_TASK_STACK_SIZE, /* Task's stack size in words, not bytes!. */ + NULL, /* Task parameter, not used in this case. */ + notifyTASK_PRIORITY, /* Task priority, 0 is the lowest. */ + &xTaskToNotify ); /* Used to pass a handle to the task out if needed, otherwise set to NULL. */ + + /* Pseudo seed the random number generator. */ + uxNextRand = ( size_t ) prvRand; +} +/*-----------------------------------------------------------*/ + +static void prvNotifiedTask( void * pvParameters ) +{ + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + /* Loop through each set of test functions in turn. See the comments above + * the respective function prototypes above for more details. */ + for( ; ; ) + { + prvSingleTaskTests(); + prvTestNotifyTaskWhileSuspended(); + prvBlockOnTheNotifiedIndexed(); + prvBlockOnANonNotifiedIndexed(); + prvBlockOnNotificationsComingFromInterrupts(); + ulCourseCycleCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvSingleTaskTests( void ) +{ + const TickType_t xTicksToWait = pdMS_TO_TICKS( 100UL ); + BaseType_t xReturned; + uint32_t ulNotifiedValue, ulLoop, ulNotifyingValue, ulPreviousValue, ulExpectedValue; + TickType_t xTimeOnEntering, xTimeNow, xTimeDifference; + const uint32_t ulFirstNotifiedConst = 100001UL, ulSecondNotifiedValueConst = 5555UL, ulMaxLoops = 5UL; + const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL; + UBaseType_t uxIndexToTest, uxOtherIndexes; + + + /* ------------------------------------------------------------------------ + * Check blocking when there are no notifications. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* Send notifications to the task notification in each index of the + * task notification array other than the one on which this task will + * block. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + if( uxOtherIndexes != uxIndexToTest ) + { + xTaskNotifyIndexed( xTaskToNotify, uxOtherIndexes, 0, eNoAction ); + } + } + + xTimeOnEntering = xTaskGetTickCount(); + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* Should have blocked for the entire block time. */ + xTimeNow = xTaskGetTickCount(); + xTimeDifference = xTimeNow - xTimeOnEntering; + configASSERT( xTimeDifference >= xTicksToWait ); + configASSERT( xReturned == pdFAIL ); + configASSERT( ulNotifiedValue == 0UL ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + + /* Clear all the other notifications within the array of task + * notifications again ready for the next round. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + if( uxOtherIndexes != uxIndexToTest ) + { + xReturned = xTaskNotifyStateClearIndexed( xTaskToNotify, uxOtherIndexes ); + + /* The notification state was set above so expect it to still be + * set. */ + configASSERT( xReturned == pdTRUE ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + } + } + + /* ------------------------------------------------------------------------ + * Check no blocking when notifications are pending. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* First notify the task notification at index uxIndexToTest within this + * task's own array of task notifications - this would not be a normal + * thing to do and is done here for test purposes only. */ + xReturned = xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue ); + + /* Even through the 'without overwrite' action was used the update should + * have been successful. */ + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* No bits should have been pending previously. */ + configASSERT( ulPreviousValue == 0 ); + ( void ) ulPreviousValue; + + /* The task should now have a notification pending in the task + * notification at index uxIndexToTest within the task notification array, + * and so not time out. */ + xTimeOnEntering = xTaskGetTickCount(); + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait ); + xTimeNow = xTaskGetTickCount(); + xTimeDifference = xTimeNow - xTimeOnEntering; + configASSERT( xTimeDifference < xTicksToWait ); + + /* The task should have been notified, and the notified value should + * be equal to ulFirstNotifiedConst. */ + configASSERT( xReturned == pdPASS ); + configASSERT( ulNotifiedValue == ulFirstNotifiedConst ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + } + + /*------------------------------------------------------------------------- + * Check the non-overwriting functionality. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* Send notifications to all indexes with the array of task + * notifications other than the one on which this task will block. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + if( uxOtherIndexes != uxIndexToTest ) + { + xReturned = xTaskNotifyIndexed( xTaskToNotify, uxOtherIndexes, ulFirstNotifiedConst, eSetValueWithOverwrite ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + } + + /* The notification is performed twice using two different notification + * values. The action says don't overwrite so only the first notification + * should pass and the value read back should also be that used with the + * first notification. The notification is sent to the task notification at + * index uxIndexToTest within the array of task notifications. */ + xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithoutOverwrite ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulSecondNotifiedValueConst, eSetValueWithoutOverwrite ); + configASSERT( xReturned == pdFAIL ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* Waiting for the notification should now return immediately so a block + * time of zero is used. */ + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, 0 ); + + configASSERT( xReturned == pdPASS ); + configASSERT( ulNotifiedValue == ulFirstNotifiedConst ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + + /* Clear all the other task notifications within the array of task + * notifications again ready for the next round. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + if( uxOtherIndexes != uxIndexToTest ) + { + xReturned = xTaskNotifyStateClearIndexed( xTaskToNotify, uxOtherIndexes ); + configASSERT( xReturned == pdTRUE ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + ulNotifiedValue = ulTaskNotifyValueClearIndexed( xTaskToNotify, uxOtherIndexes, notifyUINT32_MAX ); + + /* The notification value was set to ulFirstNotifiedConst in all + * the other indexes, so expect it to still have that value. */ + configASSERT( ulNotifiedValue == ulFirstNotifiedConst ); + ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + } + } + + /*------------------------------------------------------------------------- + * Do the same again, only this time use the overwriting version. This time + * both notifications should pass, and the value written the second time should + * overwrite the value written the first time, and so be the value that is read + * back. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + if( uxOtherIndexes != uxIndexToTest ) + { + xTaskNotifyIndexed( xTaskToNotify, uxOtherIndexes, ulFirstNotifiedConst, eSetValueWithOverwrite ); + } + } + + xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithOverwrite ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulSecondNotifiedValueConst, eSetValueWithOverwrite ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, notifyUINT32_MAX, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst ); + ( void ) ulNotifiedValue; + + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + if( uxOtherIndexes != uxIndexToTest ) + { + xReturned = xTaskNotifyStateClearIndexed( xTaskToNotify, uxOtherIndexes ); + configASSERT( xReturned == pdTRUE ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + ulNotifiedValue = ulTaskNotifyValueClearIndexed( xTaskToNotify, uxOtherIndexes, notifyUINT32_MAX ); + configASSERT( ulNotifiedValue == ulFirstNotifiedConst ); + ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + } + } + + /*------------------------------------------------------------------------- + * For each task notification within the array of task notifications, check + * notifications with no action pass without updating the value. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* First set the notification values of the task notification at index + * uxIndexToTest of the array of task notification to + * ulSecondNotifiedValueConst. */ + xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulSecondNotifiedValueConst, eSetValueWithOverwrite ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* Even though ulFirstNotifiedConst is used as the value next, the value + * read back should remain at ulSecondNotifiedConst as the action is set + * to eNoAction. */ + xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eNoAction ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* All task notifications in the array of task notifications up to and + * including index uxIndexToTest should still contain the same value. */ + for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ ) + { + /* First zero is bits to clear on entry, the second is bits to clear on + * exist, the last 0 is the block time. */ + xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 ); + configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst ); + ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + + /* All array indexes in the array of task notifications after index + * uxIndexToTest should still contain 0 as they have not been set in this + * loop yet. This time use ulTaskNotifyValueClearIndexed() instead of + * xTaskNotifyWaitIndexed(), just for test coverage. */ + for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + /* This time 0 is the bits to clear parameter - so clearing no bits. */ + ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 ); + configASSERT( ulNotifiedValue == 0 ); + ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + } + + /*------------------------------------------------------------------------- + * Check incrementing values. For each task notification in the array of task + * notifications in turn, send ulMaxLoop increment notifications, then ensure + * the received value is as expected - which should be + * ulSecondNotificationValueConst plus how ever many times to loop iterated. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + for( ulLoop = 0; ulLoop < ulMaxLoops; ulLoop++ ) + { + /* Increment the value of the task notification at index + * uxIndexToTest within the array of task notifications. */ + xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, 0, eIncrement ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + + /* All array indexes up to and including uxIndexToTest should still + * contain the updated value. */ + for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ ) + { + /* First zero is bits to clear on entry, the second is bits to clear on + * exist, the last 0 is the block time. */ + xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 ); + configASSERT( ulNotifiedValue == ( ulSecondNotifiedValueConst + ulMaxLoops ) ); + ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + + /* Should not be any notifications pending now. */ + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdFAIL ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + + /* All notifications values in the array of task notifications after + * index uxIndexToTest should still contain the un-incremented + * ulSecondNotifiedValueConst as they have not been set in this loop yet. + * This time use ulTaskNotifyValueClearIndexed() instead of xTaskNotifyWaitIndexed(), + * just for test coverage. */ + for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + /* This time 0 is the bits to clear parameter - so clearing no bits. */ + ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 ); + configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst ); + ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + } + + /* Clear all bits ready for next test. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* Start with all bits clear. */ + ulTaskNotifyValueClearIndexed( NULL, uxIndexToTest, notifyUINT32_MAX ); + } + + /*------------------------------------------------------------------------- + * For each task notification in the array of task notifications in turn, check + * all bits in the notification's value can be set by notifying the task with + * one additional bit set on each notification, and exiting the loop when all + * the bits are found to be set. As there are 32-bits the loop should execute + * 32 times before all the bits are found to be set. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + ulNotifyingValue = 0x01; + ulLoop = 0; + + do + { + /* Set the next bit in the value of the task notification at index + * uxIndexToTest within the array of task notifications. */ + xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulNotifyingValue, eSetBits ); + + /* Wait for the notified value - which of course will already be + * available. Don't clear the bits on entry or exit as this loop is + * exited when all the bits are set. */ + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + ulLoop++; + + /* Use the next bit on the next iteration around this loop. */ + ulNotifyingValue <<= 1UL; + } while( ulNotifiedValue != notifyUINT32_MAX ); + + /* As a 32-bit value was used the loop should have executed 32 times before + * all the bits were set. */ + configASSERT( ulLoop == 32 ); + + /* The value of each task notification within the array of task + * notifications up to and including index uxIndexToTest should still have + * all bits set. */ + for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ ) + { + /* First zero is bits to clear on entry, the second is bits to clear on + * exist, the last 0 is the block time. */ + xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 ); + configASSERT( ulNotifiedValue == notifyUINT32_MAX ); + ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + + /* The value of each task notification within the array of task + * notifications after index uxIndexToTest should still contain 0 as they + * have not been set in this loop yet. This time use ulTaskNotifyValueClearIndexed() + * instead of xTaskNotifyWaitIndexed(), just for test coverage. */ + for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + /* This time 0 is the bits to clear parameter - so clearing no bits. */ + ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 ); + configASSERT( ulNotifiedValue == 0 ); + ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + } + + /*------------------------------------------------------------------------- + * For each task notification within the array of task notifications in turn, + * check bits are cleared on entry but not on exit when a notification fails + * to arrive before timing out - both with and without a timeout value. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* Wait for the notification - but this time it is not given by anything + * and should return pdFAIL. The parameters are set to clear bit zero on + * entry and bit one on exit. As no notification was received only the bit + * cleared on entry should actually get cleared. */ + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, ulBit0, ulBit1, &ulNotifiedValue, xTicksToWait ); + configASSERT( xReturned == pdFAIL ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* Send a notification with no action to the task notification at index + * uxIndexToTest within the array of task notifications. This should not + * update the bits even though notifyUINT32_MAX is used as the notification + * value. */ + xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX, eNoAction ); + + /* All array indexes up to and including uxIndexToTest within the array + * of task notifications should have the modified value. */ + for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ ) + { + /* Reading back the value should find bit 0 is clear, as this was cleared + * on entry, but bit 1 is not clear as it will not have been cleared on exit + * as no notification was received. */ + xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0x00UL, 0x00UL, &ulNotifiedValue, 0 ); + + if( uxOtherIndexes == uxIndexToTest ) + { + /* This is the index being used this time round the loop and its + * notification state was set immediately above. */ + configASSERT( xReturned == pdPASS ); + } + else + { + /* Nothing should have set this index's notification state again. */ + configASSERT( xReturned == pdFAIL ); + } + + configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + + /* All array indexes after uxIndexToTest should still contain notifyUINT32_MAX + * left over from the previous test. This time use xTaskNotifyValueClear() + * instead of xTaskNotifyWaitIndexed(), just for test coverage. */ + for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + /* This time 0 is the bits to clear parameter - so clearing no bits. */ + ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 ); + configASSERT( ulNotifiedValue == notifyUINT32_MAX ); + ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + } + + /*------------------------------------------------------------------------- + * Now try clearing the bit on exit. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* The task is notified first using the task notification at index + * uxIndexToTest within the array of task notifications. */ + xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, 0, eNoAction ); + xTaskNotifyWaitIndexed( uxIndexToTest, 0x00, ulBit1, &ulNotifiedValue, 0 ); + + /* However as the bit is cleared on exit, after the returned notification + * value is set, the returned notification value should not have the bit + * cleared... */ + configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) ); + + /* ...but reading the value back again should find that the bit was indeed + * cleared internally. The returned value should be pdFAIL however as nothing + * has notified the task in the mean time. */ + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0x00, 0x00, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdFAIL ); + configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* No other indexes should have a notification pending. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + if( uxOtherIndexes != uxIndexToTest ) + { + xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0x00UL, 0x00UL, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdFAIL ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + } + } + + /*------------------------------------------------------------------------- + * For each task notification within the array of task notifications, try + * querying the previous value while notifying a task. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, 0x00, eSetBits, &ulPreviousValue ); + configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) ); + + /* Clear all bits. */ + xTaskNotifyWaitIndexed( uxIndexToTest, 0x00, notifyUINT32_MAX, &ulNotifiedValue, 0 ); + xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, 0x00, eSetBits, &ulPreviousValue ); + configASSERT( ulPreviousValue == 0 ); + + ulExpectedValue = 0; + + for( ulLoop = 0x01; ulLoop < 0x80UL; ulLoop <<= 1UL ) + { + /* Set the next bit up, and expect to receive the last bits set (so + * the previous value will not yet have the bit being set this time + * around). */ + xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, ulLoop, eSetBits, &ulPreviousValue ); + configASSERT( ulExpectedValue == ulPreviousValue ); + ulExpectedValue |= ulLoop; + } + } + + /* ---------------------------------------------------------------------- */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* Clear the previous notifications. */ + xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, 0 ); + } + + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* No task notification within the array of task notifications should + * have any notification pending, so an attempt to clear the notification + * state should fail. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + configASSERT( xTaskNotifyStateClearIndexed( NULL, uxOtherIndexes ) == pdFALSE ); + } + + /* Get the task to notify itself using the task notification at index + * uxIndexToTest within the array of task notifications. This is not a + * normal thing to do, and is only done here for test purposes. */ + xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue ); + + /* Now the notification state should be eNotified, so it should now be + * possible to clear the notification state. Other indexes should still + * not have a notification pending - likewise uxIndexToTest should not have + * a notification pending once it has been cleared. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + if( uxOtherIndexes == uxIndexToTest ) + { + configASSERT( xTaskNotifyStateClearIndexed( NULL, uxOtherIndexes ) == pdTRUE ); + } + + configASSERT( xTaskNotifyStateClearIndexed( NULL, uxOtherIndexes ) == pdFALSE ); + } + } + + /* ------------------------------------------------------------------------ + * For each task notification within the array of task notifications, clear + * bits in the notification value. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* Get the task to set all bits in its task notification at index + * uxIndexToTest within its array of task notifications. This is not a + * normal thing to do, and is only done here for test purposes. */ + xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX, eSetBits ); + + /* Now clear the top bytes - the returned value from the first call + * should indicate that previously all bits were set. */ + configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_HIGH_BYTE ) == notifyUINT32_MAX ); + + /* Next clear the bottom bytes - the returned value this time should + * indicate that the top byte was clear (before the bottom byte was + * cleared. */ + configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_LOW_BYTE ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE ) ); + + /* Next clear all bytes - the returned value should indicate that previously the + * high and low bytes were clear. */ + configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE & ~notifyUINT32_LOW_BYTE ) ); + + /* Now all bits should be clear. */ + configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX ) == 0 ); + configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, 0UL ) == 0 ); + configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX ) == 0 ); + + /* Now the notification state should be eNotified, so it should now be + * possible to clear the notification state. */ + configASSERT( xTaskNotifyStateClearIndexed( NULL, uxIndexToTest ) == pdTRUE ); + configASSERT( xTaskNotifyStateClearIndexed( NULL, uxIndexToTest ) == pdFALSE ); + } + + /* Incremented to show the task is still running. */ + ulFineCycleCount++; + + /* Leave all bits cleared. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, NULL, 0 ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSuspendedTaskTimerTestCallback( TimerHandle_t xExpiredTimer ) +{ + static uint32_t ulCallCount = 0; + static UBaseType_t uxIndexToNotify = 0; + + /* Remove compiler warnings about unused parameters. */ + ( void ) xExpiredTimer; + + /* Callback for a timer that is used to send notifications to a task while + * it is suspended. The timer tests the behaviour when 1: a task waiting for a + * notification is suspended and then resumed without ever receiving a + * notification, and 2: when a task waiting for a notification receives a + * notification while it is suspended. Run one of two tests on every other + * invocation of this callback. The notification is sent to the task + * notification at index uxIndexToNotify. */ + if( ( ulCallCount & 0x01 ) == 0 ) + { + vTaskSuspend( xTaskToNotify ); + configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended ); + vTaskResume( xTaskToNotify ); + } + else + { + vTaskSuspend( xTaskToNotify ); + + /* Sending a notification while the task is suspended should pass, but + * not cause the task to resume. */ + xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, 1, eSetValueWithOverwrite ); + + /* Use the next task notification within the array of task notifications + * the next time around. */ + uxIndexToNotify++; + + if( uxIndexToNotify >= configTASK_NOTIFICATION_ARRAY_ENTRIES ) + { + uxIndexToNotify = 0; + } + + /* Make sure giving the notification didn't resume the task. */ + configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended ); + + vTaskResume( xTaskToNotify ); + } + + ulCallCount++; +} +/*-----------------------------------------------------------*/ + +static void prvNotifyingTimerCallback( TimerHandle_t xNotUsed ) +{ + static BaseType_t uxIndexToNotify = 0; + + ( void ) xNotUsed; + + /* "Give" the task notification (which increments the target task + * notification value) at index uxIndexToNotify within the array of task + * notifications. */ + xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ); + + /* Use the next task notification within the array of task notifications the + * next time around. */ + uxIndexToNotify++; + + if( uxIndexToNotify >= configTASK_NOTIFICATION_ARRAY_ENTRIES ) + { + uxIndexToNotify = 0; + } +} +/*-----------------------------------------------------------*/ + +static void prvTestNotifyTaskWhileSuspended( void ) +{ + UBaseType_t uxIndexToTest, uxOtherIndexes; + BaseType_t xReturned; + uint32_t ulNotifiedValue; + + /* Raise the task's priority so it can suspend itself before the timer + * expires. */ + vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 ); + + /* Perform the test on each task notification within the array or task + * notifications. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + /* Ensure no notifications within the array of task notifications are + * pending. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, NULL, 0 ); + configASSERT( xReturned == pdFALSE ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + + /* Start the timer that will try notifying this task while it is + * suspended, then wait for a notification. The first time the callback + * executes the timer will suspend the task, then resume the task, without + * ever sending a notification to the task. */ + ulNotifiedValue = 0; + xTimerStart( xNotifyWhileSuspendedTimer, portMAX_DELAY ); + + /* Check a notification is not received on the task notification at + * index uxIndexToTest within the array of task notifications. */ + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, portMAX_DELAY ); + configASSERT( xReturned == pdFALSE ); + configASSERT( ulNotifiedValue == 0 ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* Check none of the task notifications within the array of task + * notifications as been notified. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdFALSE ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + } + + /* Start the timer that will try notifying this task while it is + * suspended, then wait for a notification at index uxIndexToTest within + * the array of task notifications. The second time the callback executes + * the timer will suspend the task, notify the task, then resume the task + * (previously it was suspended and resumed without being notified). */ + xTimerStart( xNotifyWhileSuspendedTimer, portMAX_DELAY ); + + /* Check a notification is only received in the index within the array + * of task notifications under test. */ + xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, portMAX_DELAY ); + configASSERT( xReturned == pdPASS ); + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + configASSERT( ulNotifiedValue != 0 ); + + /* Check a notification is not received in any index within the array + * of task notifications at and below the index being tested have a notification + * value, and that indexes above the index being tested to not have + * notification values. */ + for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ ) + { + xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 ); + configASSERT( xReturned == pdFALSE ); + + if( uxOtherIndexes <= uxIndexToTest ) + { + configASSERT( ulNotifiedValue == 1 ); + } + else + { + configASSERT( ulNotifiedValue == 0 ); + } + + ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */ + ( void ) ulNotifiedValue; + } + } + + /* Return the task to its proper priority */ + vTaskPrioritySet( NULL, notifyTASK_PRIORITY ); + + /* Incremented to show the task is still running. */ + ulFineCycleCount++; + + /* Leave all bits cleared. */ + for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ ) + { + xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, NULL, 0 ); + } +} +/* ------------------------------------------------------------------------ */ + +static void prvBlockOnTheNotifiedIndexed( void ) +{ + const TickType_t xTimerPeriod = pdMS_TO_TICKS( 100 ), xMargin = pdMS_TO_TICKS( 50 ), xDontBlock = 0; + UBaseType_t uxIndex, uxIndexToNotify; + uint32_t ulReceivedValue; + BaseType_t xReturned; + + /* Set the value of each notification in the array of task notifications to + * the value of its index position plus 1 so everything starts in a known + * state, then clear the notification state ready for the next test. Plus 1 is + * used because the index under test will use 0. */ + for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ ) + { + xTaskNotifyIndexed( xTaskToNotify, uxIndex, uxIndex + 1, eSetValueWithOverwrite ); + xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndex ); + } + + /* Perform the test on each task notification within the array of task + * notifications. */ + for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ ) + { + /* Set the notification value of the index being tested to 0 so the + * notification value increment/decrement functions can be tested. */ + xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, 0, eSetValueWithOverwrite ); + xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndexToNotify ); + + /* Start the software timer then wait for it to notify this task. Block + * on the notification index we expect to receive the notification on. The + * margin is to ensure the task blocks longer than the timer period. */ + xTimerStart( xIncrementingIndexTimer, portMAX_DELAY ); + ulReceivedValue = ulTaskNotifyTakeIndexed( uxIndexToNotify, pdFALSE, xTimerPeriod + xMargin ); + + /* The notification value was initially zero, and should have been + * incremented by the software timer, so now one. It will also have been + * decremented again by the call to ulTaskNotifyTakeIndexed() so gone back + * to 0. */ + configASSERT( ulReceivedValue == 1UL ); + ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* No other notification indexes should have changed, and therefore should + * still have their value set to their index plus 1 within the array of + * notifications. */ + for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ ) + { + if( uxIndex != uxIndexToNotify ) + { + xReturned = xTaskNotifyWaitIndexed( uxIndex, 0, 0, &ulReceivedValue, xDontBlock ); + configASSERT( xReturned == pdFALSE ); + configASSERT( ulReceivedValue == ( uxIndex + 1 ) ); + ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + ( void ) xReturned; + } + } + + /* Reset the notification value for the index just tested back to the + * index value plus 1 ready for the next iteration around this loop. */ + xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, uxIndexToNotify + 1, eSetValueWithOverwrite ); + xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndexToNotify ); + + /* Incremented to show the task is still running. */ + ulFineCycleCount++; + } +} +/* ------------------------------------------------------------------------ */ + +static void prvBlockOnANonNotifiedIndexed( void ) +{ + const TickType_t xTimerPeriod = pdMS_TO_TICKS( 100 ), xMargin = pdMS_TO_TICKS( 50 ), xDontBlock = 0; + UBaseType_t uxIndex, uxIndexToNotify; + uint32_t ulReceivedValue; + BaseType_t xReturned; + TickType_t xTimeBeforeBlocking, xTimeNow, xTimeDifference; + + /* Set all notify values within the array of tasks notifications to zero + * ready for the next test. */ + for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ ) + { + ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToNotify, notifyUINT32_MAX ); + } + + /* Perform the test for each notification within the array of task + * notifications. */ + for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ ) + { + /* Start the software timer then wait for it to notify this task. Block + * on a notification index that we do not expect to receive the notification + * on. The margin is to ensure the task blocks longer than the timer period. */ + xTimerStart( xIncrementingIndexTimer, portMAX_DELAY ); + xTimeBeforeBlocking = xTaskGetTickCount(); + + if( uxIndexToNotify == ( configTASK_NOTIFICATION_ARRAY_ENTRIES - 1 ) ) + { + /* configTASK_NOTIFICATION_ARRAY_ENTRIES - 1 is to be notified, so + * block on index 0. */ + uxIndex = 0; + } + else + { + /* The next index to get notified will be uxIndexToNotify, so block + * on uxIndexToNotify + 1 */ + uxIndex = uxIndexToNotify + 1; + } + + xReturned = xTaskNotifyWaitIndexed( uxIndex, 0, 0, &ulReceivedValue, xTimerPeriod + xMargin ); + + /* The notification will have been sent to task notification at index + * uxIndexToNotify in this task by the timer callback after xTimerPeriodTicks. + * The notification should not have woken this task, so xReturned should + * be false and at least xTimerPeriod + xMargin ticks should have passed. */ + configASSERT( xReturned == pdFALSE ); + xTimeNow = xTaskGetTickCount(); + xTimeDifference = xTimeNow - xTimeBeforeBlocking; + configASSERT( xTimeDifference >= ( xTimerPeriod + xMargin ) ); + ( void ) xReturned; /* Remove compiler warnings if configASSERT() is not defined. */ + ( void ) xTimeBeforeBlocking; + ( void ) xTimeDifference; + + /* Only the notification at index position uxIndexToNotify should be + * set. Calling this function will clear it again. */ + for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ ) + { + xReturned = xTaskNotifyWaitIndexed( uxIndex, 0, 0, &ulReceivedValue, xDontBlock ); + + if( uxIndex == uxIndexToNotify ) + { + /* Expect the notification state to be set and the notification + * value to have been incremented. */ + configASSERT( xReturned == pdTRUE ); + configASSERT( ulReceivedValue == 1 ); + + /* Set the notification value for this array index back to 0. */ + ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndex, notifyUINT32_MAX ); + } + else + { + /* Expect the notification state to be clear and the notification + * value to remain at zer0. */ + configASSERT( xReturned == pdFALSE ); + configASSERT( ulReceivedValue == 0 ); + } + } + + /* Incremented to show the task is still running. */ + ulFineCycleCount++; + } +} +/* ------------------------------------------------------------------------ */ + +static void prvBlockOnNotificationsComingFromInterrupts( void ) +{ + UBaseType_t uxIndex, uxIndexToNotify; + uint32_t ulReceivedValue; + BaseType_t xReturned; + const TickType_t xDontBlock = 0; + + /* Set the value of each notification within the array of task notifications + * to zero so the task can block on xTaskNotifyTake(). */ + for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ ) + { + xTaskNotifyIndexed( xTaskToNotify, uxIndex, 0, eSetValueWithOverwrite ); + xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndex ); + } + + /* Perform the test on each task notification within the array of task + * notifications. */ + for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ ) + { + /* Tell the interrupt to send the next notification. */ + taskENTER_CRITICAL(); + { + /* Don't expect to find xSendNotificationFromISR set at this time as + * the interrupt should have cleared it back to pdFALSE last time it + * executed. */ + configASSERT( xSendNotificationFromISR == pdFALSE ); + xSendNotificationFromISR = pdTRUE; + } + taskEXIT_CRITICAL(); + + /* Wait for a notification on the task notification at index + * uxIndexToNotify within the array of task notifications. */ + ulReceivedValue = ulTaskNotifyTakeIndexed( uxIndexToNotify, pdTRUE, portMAX_DELAY ); + + /* Interrupt should have reset xSendNotificationFromISR after it sent + * the notification. */ + configASSERT( xSendNotificationFromISR == pdFALSE ); + + /* The notification value was initially zero, and should have been + * incremented by the interrupt, so now one. */ + configASSERT( ulReceivedValue == 1UL ); + ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + + /* No other notification indexes should have changed, and therefore should + * still have their value set to 0. The value in array index uxIndexToNotify + * should also have been decremented back to zero by the call to + * ulTaskNotifyTakeIndexed(). */ + for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ ) + { + xReturned = xTaskNotifyWaitIndexed( uxIndexToNotify, 0, 0, &ulReceivedValue, xDontBlock ); + configASSERT( xReturned == pdFALSE ); + configASSERT( ulReceivedValue == 0 ); + ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */ + ( void ) xReturned; + } + + /* Incremented to show the task is still running. */ + ulFineCycleCount++; + } +} +/*-----------------------------------------------------------*/ + +void xNotifyArrayTaskFromISR( void ) +{ + static BaseType_t xAPIToUse = 0; + uint32_t ulPreviousValue; + const uint32_t ulUnexpectedValue = 0xff; + static UBaseType_t uxIndexToNotify = 0; + + /* Check the task notification demo task was actually created. */ + configASSERT( xTaskToNotify ); + + /* The task sets xSendNotificationFromISR to pdTRUE each time it wants this + * interrupt (this function runs in the RTOS tick hook) to send the next + * notification. */ + if( xSendNotificationFromISR == pdTRUE ) + { + xSendNotificationFromISR = pdFALSE; + + /* Test using both vTaskNotifyGiveFromISR(), xTaskNotifyFromISR() + * and xTaskNotifyAndQueryFromISR(). The notification is set to the task + * notification at index uxIndexToNotify within the array of task + * notifications. */ + switch( xAPIToUse ) + { + case 0: + vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, NULL ); + xAPIToUse++; + break; + + case 1: + xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, 0, eIncrement, NULL ); + xAPIToUse++; + break; + + case 2: + ulPreviousValue = ulUnexpectedValue; + xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, 0, eIncrement, &ulPreviousValue, NULL ); + configASSERT( ulPreviousValue == 0 ); + xAPIToUse = 0; + break; + + default: /* Should never get here!. */ + break; + } + + /* Use the next index in the array of task notifications the next time + * around. */ + uxIndexToNotify++; + + if( uxIndexToNotify >= configTASK_NOTIFICATION_ARRAY_ENTRIES ) + { + uxIndexToNotify = 0; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check the created tasks are still running and have not + * detected any errors. */ +BaseType_t xAreTaskNotificationArrayTasksStillRunning( void ) +{ + static uint32_t ulLastFineCycleCount = 0, ulLastCourseCycleCount = 0, ulCallCount = 0; + const uint32_t ulCallsBetweenCourseCycleCountChecks = 3UL; + static BaseType_t xErrorStatus = pdPASS; + + /* Check the cycle count is still incrementing to ensure the task is still + * actually running. The fine counter is incremented within individual test + * functions. The course counter is incremented one each time all the test + * functions have been executed to ensure all the tests are running. */ + if( ulLastFineCycleCount == ulFineCycleCount ) + { + xErrorStatus = pdFAIL; + } + else + { + ulLastFineCycleCount = ulFineCycleCount; + } + + ulCallCount++; + + if( ulCallCount >= ulCallsBetweenCourseCycleCountChecks ) + { + ulCallCount = 0; + + if( ulLastCourseCycleCount == ulCourseCycleCounter ) + { + xErrorStatus = pdFAIL; + } + else + { + ulLastCourseCycleCount = ulCourseCycleCounter; + } + } + + return xErrorStatus; +} +/*-----------------------------------------------------------*/ + +static UBaseType_t prvRand( void ) +{ + const size_t uxMultiplier = ( size_t ) 0x015a4e35, uxIncrement = ( size_t ) 1; + + /* Utility function to generate a pseudo random number. */ + uxNextRand = ( uxMultiplier * uxNextRand ) + uxIncrement; + return( ( uxNextRand >> 16 ) & ( ( size_t ) 0x7fff ) ); +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/TimerDemo.c b/SOFTWARE-FreeRTOS/Common/Minimal/TimerDemo.c new file mode 100644 index 0000000..be3002a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/TimerDemo.c @@ -0,0 +1,1224 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Tests the behaviour of timers. Some timers are created before the scheduler + * is started, and some after. + */ + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" + +/* Demo program include files. */ +#include "TimerDemo.h" + +#if ( configTIMER_TASK_PRIORITY < 1 ) + #error configTIMER_TASK_PRIORITY must be set to at least 1 for this test/demo to function correctly. +#endif + +#define tmrdemoDONT_BLOCK ( ( TickType_t ) 0 ) +#define tmrdemoONE_SHOT_TIMER_PERIOD ( xBasePeriod * ( TickType_t ) 3 ) +#define tmrdemoNUM_TIMER_RESETS ( ( uint8_t ) 10 ) + +#ifndef tmrTIMER_TEST_TASK_STACK_SIZE + #define tmrTIMER_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE +#endif + +/*-----------------------------------------------------------*/ + +/* The callback functions used by the timers. These each increment a counter + * to indicate which timer has expired. The auto-reload timers that are used by + * the test task (as opposed to being used from an ISR) all share the same + * prvAutoReloadTimerCallback() callback function, and use the ID of the + * pxExpiredTimer parameter passed into that function to know which counter to + * increment. The other timers all have their own unique callback function and + * simply increment their counters without using the callback function parameter. */ +static void prvAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer ); +static void prvOneShotTimerCallback( TimerHandle_t pxExpiredTimer ); +static void prvTimerTestTask( void * pvParameters ); +static void prvISRAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer ); +static void prvISROneShotTimerCallback( TimerHandle_t pxExpiredTimer ); + +/* The test functions used by the timer test task. These manipulate the auto + * reload and one-shot timers in various ways, then delay, then inspect the timers + * to ensure they have behaved as expected. */ +static void prvTest1_CreateTimersWithoutSchedulerRunning( void ); +static void prvTest2_CheckTaskAndTimersInitialState( void ); +static void prvTest3_CheckAutoReloadExpireRates( void ); +static void prvTest4_CheckAutoReloadTimersCanBeStopped( void ); +static void prvTest5_CheckBasicOneShotTimerBehaviour( void ); +static void prvTest6_CheckAutoReloadResetBehaviour( void ); +static void prvTest7_CheckBacklogBehaviour( void ); +static void prvResetStartConditionsForNextIteration( void ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdFAIL should any unexpected behaviour be + * detected in any of the demo tests. */ +static volatile BaseType_t xTestStatus = pdPASS; + +/* Flag indicating whether the testing includes the backlog demo. The backlog + * demo can be disruptive to other demos because the timer backlog is created by + * calling xTaskCatchUpTicks(). */ +static uint8_t ucIsBacklogDemoEnabled = ( uint8_t ) pdFALSE; + +/* Counter that is incremented on each cycle of a test. This is used to + * detect a stalled task - a test that is no longer running. */ +static volatile uint32_t ulLoopCounter = 0; + +/* A set of auto-reload timers - each of which use the same callback function. + * The callback function uses the timer ID to index into, and then increment, a + * counter in the ucAutoReloadTimerCounters[] array. The callback function stops + * xAutoReloadTimers[0] during its callback if ucIsStopNeededInTimerZeroCallback is + * pdTRUE. The auto-reload timers referenced from xAutoReloadTimers[] are used by + * the prvTimerTestTask task. */ +static TimerHandle_t xAutoReloadTimers[ configTIMER_QUEUE_LENGTH + 1 ] = { 0 }; +static uint8_t ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH + 1 ] = { 0 }; +static uint8_t ucIsStopNeededInTimerZeroCallback = ( uint8_t ) pdFALSE; + +/* The one-shot timer is configured to use a callback function that increments + * ucOneShotTimerCounter each time it gets called. */ +static TimerHandle_t xOneShotTimer = NULL; +static uint8_t ucOneShotTimerCounter = ( uint8_t ) 0; + +/* The ISR reload timer is controlled from the tick hook to exercise the timer + * API functions that can be used from an ISR. It is configured to increment + * ucISRReloadTimerCounter each time its callback function is executed. */ +static TimerHandle_t xISRAutoReloadTimer = NULL; +static uint8_t ucISRAutoReloadTimerCounter = ( uint8_t ) 0; + +/* The ISR one-shot timer is controlled from the tick hook to exercise the timer + * API functions that can be used from an ISR. It is configured to increment + * ucISRReloadTimerCounter each time its callback function is executed. */ +static TimerHandle_t xISROneShotTimer = NULL; +static uint8_t ucISROneShotTimerCounter = ( uint8_t ) 0; + +/* The period of all the timers are a multiple of the base period. The base + * period is configured by the parameter to vStartTimerDemoTask(). */ +static TickType_t xBasePeriod = 0; + +/*-----------------------------------------------------------*/ + +void vStartTimerDemoTask( TickType_t xBasePeriodIn ) +{ + /* Start with the timer and counter arrays clear - this is only necessary + * where the compiler does not clear them automatically on start up. */ + memset( ucAutoReloadTimerCounters, 0x00, sizeof( ucAutoReloadTimerCounters ) ); + memset( xAutoReloadTimers, 0x00, sizeof( xAutoReloadTimers ) ); + + /* Store the period from which all the timer periods will be generated from + * (multiples of). */ + xBasePeriod = xBasePeriodIn; + + /* Create a set of timers for use by this demo/test. */ + prvTest1_CreateTimersWithoutSchedulerRunning(); + + /* Create the task that will control and monitor the timers. This is + * created at a lower priority than the timer service task to ensure, as + * far as it is concerned, commands on timers are acted on immediately + * (sending a command to the timer service task will unblock the timer service + * task, which will then preempt this task). */ + if( xTestStatus != pdFAIL ) + { + xTaskCreate( prvTimerTestTask, "Tmr Tst", tmrTIMER_TEST_TASK_STACK_SIZE, NULL, configTIMER_TASK_PRIORITY - 1, NULL ); + } +} +/*-----------------------------------------------------------*/ + +void vTimerDemoIncludeBacklogTests( BaseType_t includeBacklogTests ) +{ + ucIsBacklogDemoEnabled = ( uint8_t ) includeBacklogTests; +} +/*-----------------------------------------------------------*/ + +static void prvTimerTestTask( void * pvParameters ) +{ + ( void ) pvParameters; + + /* Create a one-shot timer for use later on in this test. For test purposes it + * is created as an auto-reload timer then converted to a one-shot timer. */ + xOneShotTimer = xTimerCreate( "Oneshot Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */ + tmrdemoONE_SHOT_TIMER_PERIOD, /* The period for the timer. */ + pdFALSE, /* Autoreload is false, so created as a one-shot timer. */ + ( void * ) 0, /* The timer identifier. Initialise to 0, then increment each time it is called. */ + prvOneShotTimerCallback ); /* The callback to be called when the timer expires. */ + + if( xOneShotTimer == NULL ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Purely for test coverage purposes - change and query the reload mode to + * auto-reload then back to one-shot. */ + + /* Change timer to auto-reload. */ + vTimerSetReloadMode( xOneShotTimer, pdTRUE ); + + /* Timer should now be auto-reload. */ + configASSERT( uxTimerGetReloadMode( xOneShotTimer ) == pdTRUE ); + + /* Change timer to one-shot, which is what is needed for this test. */ + vTimerSetReloadMode( xOneShotTimer, pdFALSE ); + + /* Check change to one-shot was successful. */ + configASSERT( uxTimerGetReloadMode( xOneShotTimer ) == pdFALSE ); + + /* Ensure all the timers are in their expected initial state. This + * depends on the timer service task having a higher priority than this task. */ + prvTest2_CheckTaskAndTimersInitialState(); + + for( ; ; ) + { + /* Check the auto-reload timers expire at the expected/correct rates. */ + prvTest3_CheckAutoReloadExpireRates(); + + /* Check the auto-reload timers can be stopped correctly, and correctly + * report their state. */ + prvTest4_CheckAutoReloadTimersCanBeStopped(); + + /* Check the one-shot timer only calls its callback once after it has been + * started, and that it reports its state correctly. */ + prvTest5_CheckBasicOneShotTimerBehaviour(); + + /* Check timer reset behaviour. */ + prvTest6_CheckAutoReloadResetBehaviour(); + + /* Check timer behaviour when the timer task gets behind in its work. */ + if( ucIsBacklogDemoEnabled == ( uint8_t ) pdTRUE ) + { + prvTest7_CheckBacklogBehaviour(); + } + + /* Start the timers again to restart all the tests over again. */ + prvResetStartConditionsForNextIteration(); + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the created task is still running and has not + * detected any errors. */ +BaseType_t xAreTimerDemoTasksStillRunning( TickType_t xCycleFrequency ) +{ + static uint32_t ulLastLoopCounter = 0UL; + TickType_t xMaxBlockTimeUsedByTheseTests, xLoopCounterIncrementTimeMax; + static TickType_t xIterationsWithoutCounterIncrement = ( TickType_t ) 0, xLastCycleFrequency; + + if( xLastCycleFrequency != xCycleFrequency ) + { + /* The cycle frequency has probably become much faster due to an error + * elsewhere. Start counting Iterations again. */ + xIterationsWithoutCounterIncrement = ( TickType_t ) 0; + xLastCycleFrequency = xCycleFrequency; + } + + /* Calculate the maximum number of times that it is permissible for this + * function to be called without ulLoopCounter being incremented. This is + * necessary because the tests in this file block for extended periods, and the + * block period might be longer than the time between calls to this function. */ + xMaxBlockTimeUsedByTheseTests = ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod; + xLoopCounterIncrementTimeMax = ( xMaxBlockTimeUsedByTheseTests / xCycleFrequency ) + 1; + + /* If the demo task is still running then the loop counter is expected to + * have incremented every xLoopCounterIncrementTimeMax calls. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xIterationsWithoutCounterIncrement++; + + if( xIterationsWithoutCounterIncrement > xLoopCounterIncrementTimeMax ) + { + /* The tests appear to be no longer running (stalled). */ + xTestStatus = pdFAIL; + } + } + else + { + /* ulLoopCounter changed, so the count of times this function was called + * without a change can be reset to zero. */ + xIterationsWithoutCounterIncrement = ( TickType_t ) 0; + } + + ulLastLoopCounter = ulLoopCounter; + + /* Errors detected in the task itself will have latched xTestStatus + * to pdFAIL. */ + + return xTestStatus; +} +/*-----------------------------------------------------------*/ + +static void prvTest1_CreateTimersWithoutSchedulerRunning( void ) +{ + TickType_t xTimer; + + for( xTimer = 0; xTimer < configTIMER_QUEUE_LENGTH; xTimer++ ) + { + /* As the timer queue is not yet full, it should be possible to both + * create and start a timer. These timers are being started before the + * scheduler has been started, so their block times should get set to zero + * within the timer API itself. */ + xAutoReloadTimers[ xTimer ] = xTimerCreate( "FR Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */ + ( ( xTimer + ( TickType_t ) 1 ) * xBasePeriod ), /* The period for the timer. The plus 1 ensures a period of zero is not specified. */ + pdTRUE, /* Auto-reload is set to true. */ + ( void * ) xTimer, /* An identifier for the timer as all the auto-reload timers use the same callback. */ + prvAutoReloadTimerCallback ); /* The callback to be called when the timer expires. */ + + if( xAutoReloadTimers[ xTimer ] == NULL ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + else + { + configASSERT( strcmp( pcTimerGetName( xAutoReloadTimers[ xTimer ] ), "FR Timer" ) == 0 ); + + /* The scheduler has not yet started, so the block period of + * portMAX_DELAY should just get set to zero in xTimerStart(). Also, + * the timer queue is not yet full so xTimerStart() should return + * pdPASS. */ + if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) != pdPASS ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + } + + /* The timers queue should now be full, so it should be possible to create + * another timer, but not possible to start it (the timer queue will not get + * drained until the scheduler has been started. */ + xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] = xTimerCreate( "FR Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */ + ( configTIMER_QUEUE_LENGTH * xBasePeriod ), /* The period for the timer. */ + pdTRUE, /* Auto-reload is set to true. */ + ( void * ) xTimer, /* An identifier for the timer as all the auto-reload timers use the same callback. */ + prvAutoReloadTimerCallback ); /* The callback executed when the timer expires. */ + + if( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] == NULL ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + else + { + if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) == pdPASS ) + { + /* This time it would not be expected that the timer could be + * started at this point. */ + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + /* Create the timers that are used from the tick interrupt to test the timer + * API functions that can be called from an ISR. */ + xISRAutoReloadTimer = xTimerCreate( "ISR AR", /* The text name given to the timer. */ + 0xffff, /* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */ + pdTRUE, /* This is an auto-reload timer. */ + ( void * ) NULL, /* The identifier is not required. */ + prvISRAutoReloadTimerCallback ); /* The callback that is executed when the timer expires. */ + + xISROneShotTimer = xTimerCreate( "ISR OS", /* The text name given to the timer. */ + 0xffff, /* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */ + pdFALSE, /* This is a one-shot timer. */ + ( void * ) NULL, /* The identifier is not required. */ + prvISROneShotTimerCallback ); /* The callback that is executed when the timer expires. */ + + if( ( xISRAutoReloadTimer == NULL ) || ( xISROneShotTimer == NULL ) ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTest2_CheckTaskAndTimersInitialState( void ) +{ + uint8_t ucTimer; + + /* Ensure all the timers are in their expected initial state. This depends + * on the timer service task having a higher priority than this task. + * + * auto-reload timers 0 to ( configTIMER_QUEUE_LENGTH - 1 ) should now be active, + * and auto-reload timer configTIMER_QUEUE_LENGTH should not yet be active (it + * could not be started prior to the scheduler being started when it was + * created). */ + for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTest3_CheckAutoReloadExpireRates( void ) +{ + uint8_t ucMaxAllowableValue, ucMinAllowableValue, ucTimer; + TickType_t xBlockPeriod, xTimerPeriod, xExpectedNumber; + UBaseType_t uxOriginalPriority; + + /* Check the auto-reload timers expire at the expected rates. Do this at a + * high priority for maximum accuracy. This is ok as most of the time is spent + * in the Blocked state. */ + uxOriginalPriority = uxTaskPriorityGet( NULL ); + vTaskPrioritySet( NULL, ( configMAX_PRIORITIES - 1 ) ); + + /* Delaying for configTIMER_QUEUE_LENGTH * xBasePeriod ticks should allow + * all the auto-reload timers to expire at least once. */ + xBlockPeriod = ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod; + vTaskDelay( xBlockPeriod ); + + /* Check that all the auto-reload timers have called their callback + * function the expected number of times. */ + for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + /* The expected number of expires is equal to the block period divided + * by the timer period. */ + xTimerPeriod = ( ( ( TickType_t ) ucTimer + ( TickType_t ) 1 ) * xBasePeriod ); + xExpectedNumber = xBlockPeriod / xTimerPeriod; + + ucMaxAllowableValue = ( ( uint8_t ) xExpectedNumber ); + ucMinAllowableValue = ( uint8_t ) ( ( uint8_t ) xExpectedNumber - ( uint8_t ) 1 ); /* Weird casting to try and please all compilers. */ + + if( ( ucAutoReloadTimerCounters[ ucTimer ] < ucMinAllowableValue ) || + ( ucAutoReloadTimerCounters[ ucTimer ] > ucMaxAllowableValue ) + ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + /* Return to the original priority. */ + vTaskPrioritySet( NULL, uxOriginalPriority ); + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so the + * check task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvTest4_CheckAutoReloadTimersCanBeStopped( void ) +{ + uint8_t ucTimer; + + /* Check the auto-reload timers can be stopped correctly, and correctly + * report their state. */ + + /* Stop all the active timers. */ + for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + /* The timer has not been stopped yet! */ + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Now stop the timer. This will appear to happen immediately to + * this task because this task is running at a priority below the + * timer service task. */ + xTimerStop( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK ); + + /* The timer should now be inactive. */ + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + taskENTER_CRITICAL(); + { + /* The timer in array position configTIMER_QUEUE_LENGTH should not + * be active. The critical section is used to ensure the timer does + * not call its callback between the next line running and the array + * being cleared back to zero, as that would mask an error condition. */ + if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH ] != ( uint8_t ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Clear the timer callback count. */ + memset( ( void * ) ucAutoReloadTimerCounters, 0, sizeof( ucAutoReloadTimerCounters ) ); + } + taskEXIT_CRITICAL(); + + /* The timers are now all inactive, so this time, after delaying, none + * of the callback counters should have incremented. */ + vTaskDelay( ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod ); + + for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + if( ucAutoReloadTimerCounters[ ucTimer ] != ( uint8_t ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so + * the check task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvTest5_CheckBasicOneShotTimerBehaviour( void ) +{ + /* Check the one-shot timer only calls its callback once after it has been + * started, and that it reports its state correctly. */ + + /* The one-shot timer should not be active yet. */ + if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucOneShotTimerCounter != ( uint8_t ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Start the one-shot timer and check that it reports its state correctly. */ + xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK ); + + if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Delay for three times as long as the one-shot timer period, then check + * to ensure it has only called its callback once, and is now not in the + * active state. */ + vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD * ( TickType_t ) 3 ); + + if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucOneShotTimerCounter != ( uint8_t ) 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + else + { + /* Reset the one-shot timer callback count. */ + ucOneShotTimerCounter = ( uint8_t ) 0; + } + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so the + * check task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvTest6_CheckAutoReloadResetBehaviour( void ) +{ + uint8_t ucTimer; + + /* Check timer reset behaviour. */ + + /* Restart the one-shot timer and check it reports its status correctly. */ + xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK ); + + if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Restart one of the auto-reload timers and check that it reports its + * status correctly. */ + xTimerStart( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK ); + + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + for( ucTimer = 0; ucTimer < tmrdemoNUM_TIMER_RESETS; ucTimer++ ) + { + /* Delay for half as long as the one-shot timer period, then reset it. + * It should never expire while this is done, so its callback count should + * never increment. */ + vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD / 2 ); + + /* Check both running timers are still active, but have not called their + * callback functions. */ + if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucOneShotTimerCounter != ( uint8_t ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] != ( uint8_t ) 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Reset both running timers. */ + xTimerReset( xOneShotTimer, tmrdemoDONT_BLOCK ); + xTimerReset( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK ); + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so + * the check task knows this task is still running. */ + ulLoopCounter++; + } + } + + /* Finally delay long enough for both running timers to expire. */ + vTaskDelay( ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod ); + + /* The timers were not reset during the above delay period so should now + * both have called their callback functions. */ + if( ucOneShotTimerCounter != ( uint8_t ) 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] == 0 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* The one-shot timer should no longer be active, while the auto-reload + * timer should still be active. */ + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( xTimerIsTimerActive( xOneShotTimer ) == pdTRUE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Stop the auto-reload timer again. */ + xTimerStop( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK ); + + if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Clear the timer callback counts, ready for another iteration of these + * tests. */ + ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] = ( uint8_t ) 0; + ucOneShotTimerCounter = ( uint8_t ) 0; + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so the check + * task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvTest7_CheckBacklogBehaviour( void ) +{ + UBaseType_t uxOriginalPriority; + + /* Use the first auto-reload timer to test stopping a timer from a + * backlogged callback. */ + + /* The timer has not been started yet! */ + if( xTimerIsTimerActive( xAutoReloadTimers[ 0 ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Prompt the callback function to stop the timer. */ + ucIsStopNeededInTimerZeroCallback = ( uint8_t ) pdTRUE; + + /* Now start the timer. This will appear to happen immediately to + * this task because this task is running at a priority below the timer + * service task. Use a timer period of one tick so the call to + * xTaskCatchUpTicks() below has minimal impact on other tests that might + * be running. */ +#define tmrdemoBACKLOG_TIMER_PERIOD ( ( TickType_t ) 1 ) + xTimerChangePeriod( xAutoReloadTimers[ 0 ], tmrdemoBACKLOG_TIMER_PERIOD, tmrdemoDONT_BLOCK ); + + /* The timer should now be active. */ + if( xTimerIsTimerActive( xAutoReloadTimers[ 0 ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Arrange for the callback to execute late enough that it will execute + * twice, back-to-back. The timer must handle the stop request properly + * in spite of the backlog of callbacks. */ +#define tmrdemoEXPECTED_BACKLOG_EXPIRES ( ( TickType_t ) 2 ) + xTaskCatchUpTicks( tmrdemoBACKLOG_TIMER_PERIOD * tmrdemoEXPECTED_BACKLOG_EXPIRES ); + + /* The timer should now be inactive. */ + if( xTimerIsTimerActive( xAutoReloadTimers[ 0 ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Restore the standard timer period, and leave the timer inactive. */ + xTimerChangePeriod( xAutoReloadTimers[ 0 ], xBasePeriod, tmrdemoDONT_BLOCK ); + xTimerStop( xAutoReloadTimers[ 0 ], tmrdemoDONT_BLOCK ); + + /* Clear the reload count for the timer used in this test. */ + ucAutoReloadTimerCounters[ 0 ] = ( uint8_t ) 0; + + + /* Verify a one-shot timer is marked as inactive if the timer task processes + * the start or reset request after the expiration time has passed. */ + + /* The timer has not been started yet! */ + if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Use the timer period specific to backlogged timers because it reduces + * the impact on other tests that might be running when xTaskCatchUpTicks() + * creates the backlog, below. */ + xTimerChangePeriod( xOneShotTimer, tmrdemoBACKLOG_TIMER_PERIOD, tmrdemoDONT_BLOCK ); + + /* Temporarily give this task maximum priority so it can cause the timer + * task to delay its processing of the reset request below. */ + uxOriginalPriority = uxTaskPriorityGet( NULL ); + vTaskPrioritySet( NULL, ( configMAX_PRIORITIES - 1 ) ); + + /* Reset the timer. The timer service won't process this request right + * away as noted above. */ + xTimerReset( xOneShotTimer, tmrdemoDONT_BLOCK ); + + /* Cause the timer period to elapse without giving an opportunity for the + * timer service task to process the reset request. */ + xTaskCatchUpTicks( tmrdemoBACKLOG_TIMER_PERIOD ); + + /* Return this task to its original priority. The timer service task will + * process the reset request immediately. The timer task must handle the reset + * request as if it were processed at the time of the request even though in + * this test the processing occurs after the intended expiration time. */ + vTaskPrioritySet( NULL, uxOriginalPriority ); + + /* The timer should now be inactive. */ + if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Restore the standard timer period, and leave the timer inactive. */ + xTimerChangePeriod( xOneShotTimer, tmrdemoONE_SHOT_TIMER_PERIOD, tmrdemoDONT_BLOCK ); + xTimerStop( xOneShotTimer, tmrdemoDONT_BLOCK ); + + /* Clear the counter for the timer used in this test. */ + ucOneShotTimerCounter = ( uint8_t ) 0; + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so the check + * task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvResetStartConditionsForNextIteration( void ) +{ + uint8_t ucTimer; + + /* Start the timers again to start all the tests over again. */ + + /* Start the timers again. */ + for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ ) + { + /* The timer has not been started yet! */ + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Now start the timer. This will appear to happen immediately to + * this task because this task is running at a priority below the timer + * service task. */ + xTimerStart( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK ); + + /* The timer should now be active. */ + if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + + if( xTestStatus == pdPASS ) + { + /* No errors have been reported so increment the loop counter so the + * check task knows this task is still running. */ + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +void vTimerPeriodicISRTests( void ) +{ + static TickType_t uxTick = ( TickType_t ) -1; + + #if ( configTIMER_TASK_PRIORITY != ( configMAX_PRIORITIES - 1 ) ) + + /* The timer service task is not the highest priority task, so it cannot + * be assumed that timings will be exact. Timers should never call their + * callback before their expiry time, but a margin is permissible for calling + * their callback after their expiry time. If exact timing is required then + * configTIMER_TASK_PRIORITY must be set to ensure the timer service task + * is the highest priority task in the system. + * + * This function is called from the tick hook. The tick hook is called + * even when the scheduler is suspended. Therefore it is possible that the + * uxTick count maintained in this function is temporarily ahead of the tick + * count maintained by the kernel. When this is the case a message posted from + * this function will assume a time stamp in advance of the real time stamp, + * which can result in a timer being processed before this function expects it + * to. For example, if the kernel's tick count was 100, and uxTick was 102, + * then this function will not expect the timer to have expired until the + * kernel's tick count is (102 + xBasePeriod), whereas in reality the timer + * will expire when the kernel's tick count is (100 + xBasePeriod). For this + * reason xMargin is used as an allowable margin for premature timer expires + * as well as late timer expires. */ + #ifdef _WINDOWS_ + /* Windows is not real real time. */ + const TickType_t xMargin = 20; + #else + const TickType_t xMargin = 6; + #endif /* _WINDOWS_ */ + #else + #ifdef _WINDOWS_ + /* Windows is not real real time. */ + const TickType_t xMargin = 20; + #else + const TickType_t xMargin = 4; + #endif /* _WINDOWS_ */ + #endif /* if ( configTIMER_TASK_PRIORITY != ( configMAX_PRIORITIES - 1 ) ) */ + + + uxTick++; + + if( uxTick == 0 ) + { + /* The timers will have been created, but not started. Start them now + * by setting their period. */ + ucISRAutoReloadTimerCounter = 0; + ucISROneShotTimerCounter = 0; + + /* It is possible that the timer task has not yet made room in the + * timer queue. If the timers cannot be started then reset uxTick so + * another attempt is made later. */ + uxTick = ( TickType_t ) -1; + + /* Try starting first timer. */ + if( xTimerChangePeriodFromISR( xISRAutoReloadTimer, xBasePeriod, NULL ) == pdPASS ) + { + /* First timer was started, try starting the second timer. */ + if( xTimerChangePeriodFromISR( xISROneShotTimer, xBasePeriod, NULL ) == pdPASS ) + { + /* Both timers were started, so set the uxTick back to its + * proper value. */ + uxTick = 0; + } + else + { + /* Second timer could not be started, so stop the first one + * again. */ + xTimerStopFromISR( xISRAutoReloadTimer, NULL ); + } + } + } + else if( uxTick == ( xBasePeriod - xMargin ) ) + { + /* Neither timer should have expired yet. */ + if( ( ucISRAutoReloadTimerCounter != 0 ) || ( ucISROneShotTimerCounter != 0 ) ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( xBasePeriod + xMargin ) ) + { + /* Both timers should now have expired once. The auto-reload timer will + * still be active, but the one-shot timer should now have stopped. */ + if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( ( 2 * xBasePeriod ) - xMargin ) ) + { + /* The auto-reload timer will still be active, but the one-shot timer + * should now have stopped - however, at this time neither of the timers + * should have expired again since the last test. */ + if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( ( 2 * xBasePeriod ) + xMargin ) ) + { + /* The auto-reload timer will still be active, but the one-shot timer + * should now have stopped. At this time the auto-reload timer should have + * expired again, but the one-shot timer count should not have changed. */ + if( ucISRAutoReloadTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( ( 2 * xBasePeriod ) + ( xBasePeriod >> ( TickType_t ) 2U ) ) ) + { + /* The auto-reload timer will still be active, but the one-shot timer + * should now have stopped. Again though, at this time, neither timer call + * back should have been called since the last test. */ + if( ucISRAutoReloadTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( 3 * xBasePeriod ) ) + { + /* Start the one-shot timer again. */ + xTimerStartFromISR( xISROneShotTimer, NULL ); + } + else if( uxTick == ( ( 3 * xBasePeriod ) + xMargin ) ) + { + /* The auto-reload timer and one-shot timer will be active. At + * this time the auto-reload timer should have expired again, but the one + * shot timer count should not have changed yet. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Now stop the auto-reload timer. The one-shot timer was started + * a few ticks ago. */ + xTimerStopFromISR( xISRAutoReloadTimer, NULL ); + } + else if( uxTick == ( 4 * ( xBasePeriod - xMargin ) ) ) + { + /* The auto-reload timer is now stopped, and the one-shot timer is + * active, but at this time neither timer should have expired since the + * last test. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 1 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( ( 4 * xBasePeriod ) + xMargin ) ) + { + /* The auto-reload timer is now stopped, and the one-shot timer is + * active. The one-shot timer should have expired again, but the auto + * reload timer should not have executed its callback. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( 8 * xBasePeriod ) ) + { + /* The auto-reload timer is now stopped, and the one-shot timer has + * already expired and then stopped itself. Both callback counters should + * not have incremented since the last test. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + /* Now reset the one-shot timer. */ + xTimerResetFromISR( xISROneShotTimer, NULL ); + } + else if( uxTick == ( ( 9 * xBasePeriod ) - xMargin ) ) + { + /* Only the one-shot timer should be running, but it should not have + * expired since the last test. Check the callback counters have not + * incremented, then reset the one-shot timer again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + xTimerResetFromISR( xISROneShotTimer, NULL ); + } + else if( uxTick == ( ( 10 * xBasePeriod ) - ( 2 * xMargin ) ) ) + { + /* Only the one-shot timer should be running, but it should not have + * expired since the last test. Check the callback counters have not + * incremented, then reset the one-shot timer again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + xTimerResetFromISR( xISROneShotTimer, NULL ); + } + else if( uxTick == ( ( 11 * xBasePeriod ) - ( 3 * xMargin ) ) ) + { + /* Only the one-shot timer should be running, but it should not have + * expired since the last test. Check the callback counters have not + * incremented, then reset the one-shot timer once again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 2 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + xTimerResetFromISR( xISROneShotTimer, NULL ); + } + else if( uxTick == ( ( 12 * xBasePeriod ) - ( 2 * xMargin ) ) ) + { + /* Only the one-shot timer should have been running and this time it + * should have expired. Check its callback count has been incremented. + * The auto-reload timer is still not running so should still have the same + * count value. This time the one-shot timer is not reset so should not + * restart from its expiry period again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + } + else if( uxTick == ( 15 * xBasePeriod ) ) + { + /* Neither timer should be running now. Check neither callback count + * has incremented, then go back to the start to run these tests all + * over again. */ + if( ucISRAutoReloadTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + if( ucISROneShotTimerCounter != 3 ) + { + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } + + uxTick = ( TickType_t ) -1; + } +} +/*-----------------------------------------------------------*/ + +/*** Timer callback functions are defined below here. ***/ + +static void prvAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer ) +{ + size_t uxTimerID; + + uxTimerID = ( size_t ) pvTimerGetTimerID( pxExpiredTimer ); + + if( uxTimerID <= ( configTIMER_QUEUE_LENGTH + 1 ) ) + { + ( ucAutoReloadTimerCounters[ uxTimerID ] )++; + + /* Stop timer ID 0 if requested. */ + if( ( uxTimerID == ( size_t ) 0 ) && ( ucIsStopNeededInTimerZeroCallback == ( uint8_t ) pdTRUE ) ) + { + xTimerStop( pxExpiredTimer, tmrdemoDONT_BLOCK ); + ucIsStopNeededInTimerZeroCallback = ( uint8_t ) pdFALSE; + } + } + else + { + /* The timer ID appears to be unexpected (invalid). */ + xTestStatus = pdFAIL; + configASSERT( xTestStatus ); + } +} +/*-----------------------------------------------------------*/ + +static void prvOneShotTimerCallback( TimerHandle_t pxExpiredTimer ) +{ +/* A count is kept of the number of times this callback function is executed. + * The count is stored as the timer's ID. This is only done to test the + * vTimerSetTimerID() function. */ + static size_t uxCallCount = 0; + size_t uxLastCallCount; + + /* Obtain the timer's ID, which should be a count of the number of times + * this callback function has been executed. */ + uxLastCallCount = ( size_t ) pvTimerGetTimerID( pxExpiredTimer ); + configASSERT( uxLastCallCount == uxCallCount ); + + /* Increment the call count, then save it back as the timer's ID. This is + * only done to test the vTimerSetTimerID() API function. */ + uxLastCallCount++; + vTimerSetTimerID( pxExpiredTimer, ( void * ) uxLastCallCount ); + uxCallCount++; + + ucOneShotTimerCounter++; +} +/*-----------------------------------------------------------*/ + +static void prvISRAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer ) +{ + /* The parameter is not used in this case as only one timer uses this + * callback function. */ + ( void ) pxExpiredTimer; + + ucISRAutoReloadTimerCounter++; +} +/*-----------------------------------------------------------*/ + +static void prvISROneShotTimerCallback( TimerHandle_t pxExpiredTimer ) +{ + /* The parameter is not used in this case as only one timer uses this + * callback function. */ + ( void ) pxExpiredTimer; + + ucISROneShotTimerCounter++; +} +/*-----------------------------------------------------------*/ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/blocktim.c b/SOFTWARE-FreeRTOS/Common/Minimal/blocktim.c new file mode 100644 index 0000000..e7a0385 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/blocktim.c @@ -0,0 +1,597 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This file contains some test scenarios that ensure tasks do not exit queue + * send or receive functions prematurely. A description of the tests is + * included within the code. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "blocktim.h" + +/* Task priorities and stack sizes. Allow these to be overridden. */ +#ifndef bktPRIMARY_PRIORITY + #define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#endif + +#ifndef bktSECONDARY_PRIORITY + #define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#endif + +#ifndef bktBLOCK_TIME_TASK_STACK_SIZE + #define bktBLOCK_TIME_TASK_STACK_SIZE configMINIMAL_STACK_SIZE +#endif + +/* Task behaviour. */ +#define bktQUEUE_LENGTH ( 5 ) +#define bktSHORT_WAIT pdMS_TO_TICKS( ( TickType_t ) 20 ) +#define bktPRIMARY_BLOCK_TIME ( 10 ) +#define bktALLOWABLE_MARGIN ( 15 ) +#define bktTIME_TO_BLOCK ( 175 ) +#define bktDONT_BLOCK ( ( TickType_t ) 0 ) +#define bktRUN_INDICATOR ( ( UBaseType_t ) 0x55 ) + +/* In case the demo does not have software timers enabled, as this file uses + * the configTIMER_TASK_PRIORITY setting. */ +#ifndef configTIMER_TASK_PRIORITY + #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#endif + +/*-----------------------------------------------------------*/ + +/* + * The two test tasks. Their behaviour is commented within the functions. + */ +static void vPrimaryBlockTimeTestTask( void * pvParameters ); +static void vSecondaryBlockTimeTestTask( void * pvParameters ); + +/* + * Very basic tests to verify the block times are as expected. + */ +static void prvBasicDelayTests( void ); + +/*-----------------------------------------------------------*/ + +/* The queue on which the tasks block. */ +static QueueHandle_t xTestQueue; + +/* Handle to the secondary task is required by the primary task for calls + * to vTaskSuspend/Resume(). */ +static TaskHandle_t xSecondary; + +/* Used to ensure that tasks are still executing without error. */ +static volatile BaseType_t xPrimaryCycles = 0, xSecondaryCycles = 0; +static volatile BaseType_t xErrorOccurred = pdFALSE; + +/* Provides a simple mechanism for the primary task to know when the + * secondary task has executed. */ +static volatile UBaseType_t xRunIndicator; + +/*-----------------------------------------------------------*/ + +void vCreateBlockTimeTasks( void ) +{ + /* Create the queue on which the two tasks block. */ + xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( BaseType_t ) ); + + if( xTestQueue != NULL ) + { + /* vQueueAddToRegistry() adds the queue to the queue registry, if one + * is in use. The queue registry is provided as a means for kernel aware + * debuggers to locate queues and has no purpose if a kernel aware + * debugger is not being used. The call to vQueueAddToRegistry() will be + * removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not + * defined or is defined to be less than 1. */ + vQueueAddToRegistry( xTestQueue, "Block_Time_Queue" ); + + /* Create the two test tasks. */ + xTaskCreate( vPrimaryBlockTimeTestTask, "BTest1", bktBLOCK_TIME_TASK_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL ); + xTaskCreate( vSecondaryBlockTimeTestTask, "BTest2", bktBLOCK_TIME_TASK_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary ); + } +} +/*-----------------------------------------------------------*/ + +static void vPrimaryBlockTimeTestTask( void * pvParameters ) +{ + BaseType_t xItem, xData; + TickType_t xTimeWhenBlocking; + TickType_t xTimeToBlock, xBlockedTime; + + ( void ) pvParameters; + + for( ; ; ) + { + /********************************************************************* + * Test 0 + * + * Basic vTaskDelay() and vTaskDelayUntil() tests. */ + prvBasicDelayTests(); + + /********************************************************************* + * Test 1 + * + * Simple block time wakeup test on queue receives. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is empty. Attempt to read from the queue using a block + * time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = ( TickType_t ) ( bktPRIMARY_BLOCK_TIME << xItem ); + + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + * anything on the queue. */ + if( xQueueReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY ) + { + xErrorOccurred = __LINE__; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = __LINE__; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + * although we would not necessarily run as soon as we were + * unblocked so a margin is allowed. */ + xErrorOccurred = __LINE__; + } + } + + /********************************************************************* + * Test 2 + * + * Simple block time wakeup test on queue sends. + * + * First fill the queue. It should be empty so all sends should pass. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is full. Attempt to write to the queue using a block + * time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = ( TickType_t ) ( bktPRIMARY_BLOCK_TIME << xItem ); + + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + * anything on the queue. */ + if( xQueueSend( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL ) + { + xErrorOccurred = __LINE__; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = __LINE__; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + * although we would not necessarily run as soon as we were + * unblocked so a margin is allowed. */ + xErrorOccurred = __LINE__; + } + } + + /********************************************************************* + * Test 3 + * + * Wake the other task, it will block attempting to post to the queue. + * When we read from the queue the other task will wake, but before it + * can run we will post to the queue again. When the other task runs it + * will find the queue still full, even though it was woken. It should + * recognise that its block time has not expired and return to block for + * the remains of its block time. + * + * Wake the other task so it blocks attempting to post to the already + * full queue. */ + xRunIndicator = 0; + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + /* The other task has not yet executed. */ + vTaskDelay( bktSHORT_WAIT ); + } + + /* Make sure the other task is blocked on the queue. */ + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we make space on the queue the other task should wake + * but not execute as this task has higher priority. */ + if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + /* Now fill the queue again before the other task gets a chance to + * execute. If the other task had executed we would find the queue + * full ourselves, and the other task have set xRunIndicator. */ + if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = __LINE__; + } + + /* Raise the priority of the other task so it executes and blocks + * on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + * queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + * queue function. */ + xErrorOccurred = __LINE__; + } + + /* Set the priority back down. */ + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblocks it will check that it + * unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + /********************************************************************* + * Test 4 + * + * As per test 3 - but with the send and receive the other way around. + * The other task blocks attempting to read from the queue. + * + * Empty the queue. We should find that it is full. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + } + + /* Wake the other task so it blocks attempting to read from the + * already empty queue. */ + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we place an item on the queue the other task should + * wake but not execute as this task has higher priority. */ + if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + /* Now empty the queue again before the other task gets a chance to + * execute. If the other task had executed we would find the queue + * empty ourselves, and the other task would be suspended. */ + if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = __LINE__; + } + + /* Raise the priority of the other task so it executes and blocks + * on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + * queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + * queue function. */ + xErrorOccurred = __LINE__; + } + + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblocks it will check that it + * unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + + vTaskDelay( bktSHORT_WAIT ); + + xPrimaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void vSecondaryBlockTimeTestTask( void * pvParameters ) +{ + TickType_t xTimeWhenBlocking, xBlockedTime; + BaseType_t xData; + + ( void ) pvParameters; + + for( ; ; ) + { + /********************************************************************* + * Test 0, 1 and 2 + * + * This task does not participate in these tests. */ + vTaskSuspend( NULL ); + + /********************************************************************* + * Test 3 + * + * The first thing we do is attempt to read from the queue. It should be + * full so we block. Note the time before we block so we can check the + * wake time is as per that expected. */ + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not sent anything to + * the queue. */ + xData = 0; + xRunIndicator = bktRUN_INDICATOR; + + if( xQueueSend( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL ) + { + xErrorOccurred = __LINE__; + } + + /* How long were we inside the send function? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = __LINE__; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + * either. A margin is permitted as we would not necessarily run as + * soon as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = __LINE__; + } + + /* Suspend ready for test 3. */ + xRunIndicator = bktRUN_INDICATOR; + vTaskSuspend( NULL ); + + /********************************************************************* + * Test 4 + * + * As per test three, but with the send and receive reversed. */ + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not received + * anything on the queue. */ + xRunIndicator = bktRUN_INDICATOR; + + if( xQueueReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY ) + { + xErrorOccurred = __LINE__; + } + + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = __LINE__; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + * either. A margin is permitted as we would not necessarily run as soon + * as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = __LINE__; + } + + xRunIndicator = bktRUN_INDICATOR; + + xSecondaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void prvBasicDelayTests( void ) +{ + TickType_t xPreTime, xPostTime, x, xLastUnblockTime, xExpectedUnblockTime; + const TickType_t xPeriod = 75, xCycles = 5, xAllowableMargin = ( bktALLOWABLE_MARGIN >> 1 ), xHalfPeriod = xPeriod / ( TickType_t ) 2; + BaseType_t xDidBlock; + + /* Temporarily increase priority so the timing is more accurate, but not so + * high as to disrupt the timer tests. */ + vTaskPrioritySet( NULL, configTIMER_TASK_PRIORITY - 1 ); + + /* Crude check to too see that vTaskDelay() blocks for the expected + * period. */ + xPreTime = xTaskGetTickCount(); + vTaskDelay( bktTIME_TO_BLOCK ); + xPostTime = xTaskGetTickCount(); + + /* The priority is higher, so the allowable margin is halved when compared + * to the other tests in this file. */ + if( ( xPostTime - xPreTime ) > ( bktTIME_TO_BLOCK + xAllowableMargin ) ) + { + xErrorOccurred = __LINE__; + } + + /* Now crude tests to check the vTaskDelayUntil() functionality. */ + xPostTime = xTaskGetTickCount(); + xLastUnblockTime = xPostTime; + + for( x = 0; x < xCycles; x++ ) + { + /* Calculate the next expected unblock time from the time taken before + * this loop was entered. */ + xExpectedUnblockTime = xPostTime + ( x * xPeriod ); + + vTaskDelayUntil( &xLastUnblockTime, xPeriod ); + + if( ( xTaskGetTickCount() - xExpectedUnblockTime ) > ( bktTIME_TO_BLOCK + xAllowableMargin ) ) + { + xErrorOccurred = __LINE__; + } + + xPrimaryCycles++; + } + + /* Crude tests for return value of xTaskDelayUntil(). First a standard block + * should return that the task does block. */ + xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod ); + + if( xDidBlock != pdTRUE ) + { + xErrorOccurred = __LINE__; + } + + /* Now delay a few ticks so repeating the above block period will not block for + * the full amount of time, but will still block. */ + vTaskDelay( xHalfPeriod ); + xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod ); + + if( xDidBlock != pdTRUE ) + { + xErrorOccurred = __LINE__; + } + + /* This time block for longer than xPeriod before calling xTaskDelayUntil() so + * the call to xTaskDelayUntil() should not block. */ + vTaskDelay( xPeriod ); + xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod ); + + if( xDidBlock != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + /* Catch up. */ + xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod ); + + if( xDidBlock != pdTRUE ) + { + xErrorOccurred = __LINE__; + } + + /* Again block for slightly longer than a period so ensure the time is in the + * past next time xTaskDelayUntil() gets called. */ + vTaskDelay( xPeriod + xAllowableMargin ); + xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod ); + + if( xDidBlock != pdFALSE ) + { + xErrorOccurred = __LINE__; + } + + /* Reset to the original task priority ready for the other tests. */ + vTaskPrioritySet( NULL, bktPRIMARY_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xAreBlockTimeTestTasksStillRunning( void ) +{ + static BaseType_t xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0; + BaseType_t xReturn = pdPASS; + + /* Have both tasks performed at least one cycle since this function was + * last called? */ + if( xPrimaryCycles == xLastPrimaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xSecondaryCycles == xLastSecondaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xErrorOccurred != pdFALSE ) + { + xReturn = pdFAIL; + } + + xLastSecondaryCycleCount = xSecondaryCycles; + xLastPrimaryCycleCount = xPrimaryCycles; + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/comtest.c b/SOFTWARE-FreeRTOS/Common/Minimal/comtest.c new file mode 100644 index 0000000..8611d04 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/comtest.c @@ -0,0 +1,265 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * This version of comtest. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * Creates two tasks that operate on an interrupt driven serial port. A + * loopback connector should be used so that everything that is transmitted is + * also received. The serial port does not use any flow control. On a + * standard 9way 'D' connector pins two and three should be connected together. + * + * The first task posts a sequence of characters to the Tx queue, toggling an + * LED on each successful post. At the end of the sequence it sleeps for a + * pseudo-random period before resending the same sequence. + * + * The UART Tx end interrupt is enabled whenever data is available in the Tx + * queue. The Tx end ISR removes a single character from the Tx queue and + * passes it to the UART for transmission. + * + * The second task blocks on the Rx queue waiting for a character to become + * available. When the UART Rx end interrupt receives a character it places + * it in the Rx queue, waking the second task. The second task checks that the + * characters removed from the Rx queue form the same sequence as those posted + * to the Tx queue, and toggles an LED for each correct character. + * + * The receiving task is spawned with a higher priority than the transmitting + * task. The receiver will therefore wake every time a character is + * transmitted so neither the Tx or Rx queue should ever hold more than a few + * characters. + * + */ + +/* Scheduler include files. */ +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "serial.h" +#include "comtest.h" +#include "partest.h" + +#define comSTACK_SIZE configMINIMAL_STACK_SIZE +#define comTX_LED_OFFSET ( 0 ) +#define comRX_LED_OFFSET ( 1 ) +#define comTOTAL_PERMISSIBLE_ERRORS ( 2 ) + +/* The Tx task will transmit the sequence of characters at a pseudo random + * interval. This is the maximum and minimum block time between sends. */ +#define comTX_MAX_BLOCK_TIME ( ( TickType_t ) 0x96 ) +#define comTX_MIN_BLOCK_TIME ( ( TickType_t ) 0x32 ) +#define comOFFSET_TIME ( ( TickType_t ) 3 ) + +/* We should find that each character can be queued for Tx immediately and we + * don't have to block to send. */ +#define comNO_BLOCK ( ( TickType_t ) 0 ) + +/* The Rx task will block on the Rx queue for a long period. */ +#define comRX_BLOCK_TIME ( ( TickType_t ) 0xffff ) + +/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */ +#define comFIRST_BYTE ( 'A' ) +#define comLAST_BYTE ( 'X' ) + +#define comBUFFER_LEN ( ( UBaseType_t ) ( comLAST_BYTE - comFIRST_BYTE ) + ( UBaseType_t ) 1 ) +#define comINITIAL_RX_COUNT_VALUE ( 0 ) + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort = NULL; + +/* The transmit task as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters ); + +/* The receive task as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters ); + +/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will + * toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED + * ( uxBaseLED + comTX_LED_OFFSET ). */ +static UBaseType_t uxBaseLED = 0; + +/* Check variable used to ensure no error have occurred. The Rx task will + * increment this variable after every successfully received sequence. If at any + * time the sequence is incorrect the the variable will stop being incremented. */ +static volatile UBaseType_t uxRxLoops = comINITIAL_RX_COUNT_VALUE; + +/*-----------------------------------------------------------*/ + +void vAltStartComTestTasks( UBaseType_t uxPriority, + uint32_t ulBaudRate, + UBaseType_t uxLED ) +{ + /* Initialise the com port then spawn the Rx and Tx tasks. */ + uxBaseLED = uxLED; + xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN ); + + /* The Tx task is spawned with a lower priority than the Rx task. */ + xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( TaskHandle_t * ) NULL ); + xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vComTxTask, pvParameters ) +{ + char cByteToSend; + TickType_t xTimeToWait; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Simply transmit a sequence of characters from comFIRST_BYTE to + * comLAST_BYTE. */ + for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ ) + { + if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS ) + { + vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET ); + } + } + + /* Turn the LED off while we are not doing anything. */ + vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE ); + + /* We have posted all the characters in the string - wait before + * re-sending. Wait a pseudo-random time as this will provide a better + * test. */ + xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME; + + /* Make sure we don't wait too long... */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* ...but we do want to wait. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + vTaskDelay( xTimeToWait ); + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vComRxTask, pvParameters ) +{ + signed char cExpectedByte, cByteRxed; + BaseType_t xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* We expect to receive the characters from comFIRST_BYTE to + * comLAST_BYTE in an incrementing order. Loop to receive each byte. */ + for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ ) + { + /* Block on the queue that contains received bytes until a byte is + * available. */ + if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) ) + { + /* Was this the byte we were expecting? If so, toggle the LED, + * otherwise we are out on sync and should break out of the loop + * until the expected character sequence is about to restart. */ + if( cByteRxed == cExpectedByte ) + { + vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET ); + } + else + { + xResyncRequired = pdTRUE; + break; /*lint !e960 Non-switch break allowed. */ + } + } + } + + /* Turn the LED off while we are not doing anything. */ + vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE ); + + /* Did we break out of the loop because the characters were received in + * an unexpected order? If so wait here until the character sequence is + * about to restart. */ + if( xResyncRequired == pdTRUE ) + { + while( cByteRxed != comLAST_BYTE ) + { + /* Block until the next char is available. */ + xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ); + } + + /* Note that an error occurred which caused us to have to resync. + * We use this to stop incrementing the loop counter so + * sAreComTestTasksStillRunning() will return false - indicating an + * error. */ + xErrorOccurred++; + + /* We have now resynced with the Tx task and can continue. */ + xResyncRequired = pdFALSE; + } + else + { + if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS ) + { + /* Increment the count of successful loops. As error + * occurring (i.e. an unexpected character being received) will + * prevent this counter being incremented for the rest of the + * execution. Don't worry about mutual exclusion on this + * variable - it doesn't really matter as we just want it + * to change. */ + uxRxLoops++; + } + } + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +BaseType_t xAreComTestTasksStillRunning( void ) +{ + BaseType_t xReturn; + + /* If the count of successful reception loops has not changed than at + * some time an error occurred (i.e. a character was received out of sequence) + * and we will return false. */ + if( uxRxLoops == comINITIAL_RX_COUNT_VALUE ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Reset the count of successful Rx loops. When this function is called + * again we expect this to have been incremented. */ + uxRxLoops = comINITIAL_RX_COUNT_VALUE; + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/comtest_strings.c b/SOFTWARE-FreeRTOS/Common/Minimal/comtest_strings.c new file mode 100644 index 0000000..b6c0425 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/comtest_strings.c @@ -0,0 +1,316 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Creates a task and a timer that operate on an interrupt driven serial port. + * This demo assumes that the characters transmitted on a port will also be + * received on the same port. Therefore, the UART must either be connected to + * an echo server, or the uart connector must have a loopback connector fitted. + * See http://www.serialporttool.com/CommEcho.htm for a suitable echo server + * for Windows hosts. + * + * The timer sends a string to the UART, toggles an LED, then resets itself by + * changing its own period. The period is calculated as a pseudo random number + * between comTX_MAX_BLOCK_TIME and comTX_MIN_BLOCK_TIME. + * + * The task blocks on an Rx queue waiting for a character to become available. + * Received characters are checked to ensure they match those transmitted by the + * Tx timer. An error is latched if characters are missing, incorrect, or + * arrive too slowly. + * + * How characters are actually transmitted and received is port specific. Demos + * that include this test/demo file will provide example drivers. The Tx timer + * executes in the context of the timer service (daemon) task, and must + * therefore never attempt to block. + * + */ + +/* Scheduler include files. */ +#include +#include +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" + +#ifndef configUSE_TIMERS + #error This demo uses timers. configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h. +#endif + +#if configUSE_TIMERS != 1 + #error This demo uses timers. configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h. +#endif + + +/* Demo program include files. */ +#include "serial.h" +#include "comtest_strings.h" +#include "partest.h" + +/* The size of the stack given to the Rx task. */ +#define comSTACK_SIZE configMINIMAL_STACK_SIZE + +/* See the comment above the declaration of the uxBaseLED variable. */ +#define comTX_LED_OFFSET ( 0 ) +#define comRX_LED_OFFSET ( 1 ) + +/* The Tx timer transmits the sequence of characters at a pseudo random + * interval that is capped between comTX_MAX_BLOCK_TIME and + * comTX_MIN_BLOCK_TIME. */ +#define comTX_MAX_BLOCK_TIME ( ( TickType_t ) 0x96 ) +#define comTX_MIN_BLOCK_TIME ( ( TickType_t ) 0x32 ) +#define comOFFSET_TIME ( ( TickType_t ) 3 ) + +/* States for the simple state machine implemented in the Rx task. */ +#define comtstWAITING_START_OF_STRING 0 +#define comtstWAITING_END_OF_STRING 1 + +/* A short delay in ticks - this delay is used to allow the Rx queue to fill up + * a bit so more than one character can be processed at a time. This is relative + * to comTX_MIN_BLOCK_TIME to ensure it is never longer than the shortest gap + * between transmissions. It could be worked out more scientifically from the + * baud rate being used. */ +#define comSHORT_DELAY ( comTX_MIN_BLOCK_TIME >> ( TickType_t ) 2 ) + +/* The string that is transmitted and received. */ +#define comTRANSACTED_STRING "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ1234567890" + +/* A block time of 0 simply means "don't block". */ +#define comtstDONT_BLOCK ( TickType_t ) 0 + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort = NULL; + +/* The callback function allocated to the transmit timer, as described in the + * comments at the top of this file. */ +static void prvComTxTimerCallback( TimerHandle_t xTimer ); + +/* The receive task as described in the comments at the top of this file. */ +static void vComRxTask( void * pvParameters ); + +/* The Rx task will toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task + * will toggle LED ( uxBaseLED + comTX_LED_OFFSET ). */ +static UBaseType_t uxBaseLED = 0; + +/* The Rx task toggles uxRxLoops on each successful iteration of its defined + * function - provided no errors have ever been latched. If this variable stops + * incrementing, then an error has occurred. */ +static volatile UBaseType_t uxRxLoops = 0UL; + +/* The timer used to periodically transmit the string. This is the timer that + * has prvComTxTimerCallback allocated to it as its callback function. */ +static TimerHandle_t xTxTimer = NULL; + +/* The string length is held at file scope so the Tx timer does not need to + * calculate it each time it executes. */ +static size_t xStringLength = 0U; + +/*-----------------------------------------------------------*/ + +void vStartComTestStringsTasks( UBaseType_t uxPriority, + uint32_t ulBaudRate, + UBaseType_t uxLED ) +{ + /* Store values that are used at run time. */ + uxBaseLED = uxLED; + + /* Calculate the string length here, rather than each time the Tx timer + * executes. */ + xStringLength = strlen( comTRANSACTED_STRING ); + + /* Include the null terminator in the string length as this is used to + * detect the end of the string in the Rx task. */ + xStringLength++; + + /* Initialise the com port, then spawn the Rx task and create the Tx + * timer. */ + xSerialPortInitMinimal( ulBaudRate, ( xStringLength * 2U ) ); + + /* Create the Rx task and the Tx timer. The timer is started from the + * Rx task. */ + xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL ); + xTxTimer = xTimerCreate( "TxTimer", comTX_MIN_BLOCK_TIME, pdFALSE, NULL, prvComTxTimerCallback ); + configASSERT( xTxTimer ); +} +/*-----------------------------------------------------------*/ + +static void prvComTxTimerCallback( TimerHandle_t xTimer ) +{ + TickType_t xTimeToWait; + + /* The parameter is not used in this case. */ + ( void ) xTimer; + + /* Send the string. How this is actually performed depends on the + * sample driver provided with this demo. However - as this is a timer, + * it executes in the context of the timer task and therefore must not + * block. */ + vSerialPutString( xPort, comTRANSACTED_STRING, xStringLength ); + + /* Toggle an LED to give a visible indication that another transmission + * has been performed. */ + vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET ); + + /* Wait a pseudo random time before sending the string again. */ + xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME; + + /* Ensure the time to wait is not greater than comTX_MAX_BLOCK_TIME. */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* Ensure the time to wait is not less than comTX_MIN_BLOCK_TIME. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + /* Reset the timer to run again xTimeToWait ticks from now. This function + * is called from the context of the timer task, so the block time must not + * be anything other than zero. */ + xTimerChangePeriod( xTxTimer, xTimeToWait, comtstDONT_BLOCK ); +} +/*-----------------------------------------------------------*/ + +static void vComRxTask( void * pvParameters ) +{ + BaseType_t xState = comtstWAITING_START_OF_STRING, xErrorOccurred = pdFALSE; + char * pcExpectedByte, cRxedChar; + const xComPortHandle xPort = NULL; + + /* The parameter is not used in this example. */ + ( void ) pvParameters; + + /* Start the Tx timer. This only needs to be started once, as it will + * reset itself thereafter. */ + xTimerStart( xTxTimer, portMAX_DELAY ); + + /* The first expected Rx character is the first in the string that is + * transmitted. */ + pcExpectedByte = comTRANSACTED_STRING; + + for( ; ; ) + { + /* Wait for the next character. */ + if( xSerialGetChar( xPort, &cRxedChar, ( comTX_MAX_BLOCK_TIME * 2 ) ) == pdFALSE ) + { + /* A character definitely should have been received by now. As a + * character was not received an error must have occurred (which might + * just be that the loopback connector is not fitted). */ + xErrorOccurred = pdTRUE; + } + + switch( xState ) + { + case comtstWAITING_START_OF_STRING: + + if( cRxedChar == *pcExpectedByte ) + { + /* The received character was the first character of the + * string. Move to the next state to check each character + * as it comes in until the entire string has been received. */ + xState = comtstWAITING_END_OF_STRING; + pcExpectedByte++; + + /* Block for a short period. This just allows the Rx queue + * to contain more than one character, and therefore prevent + * thrashing reads to the queue, and repetitive context + * switches as each character is received. */ + vTaskDelay( comSHORT_DELAY ); + } + + break; + + case comtstWAITING_END_OF_STRING: + + if( cRxedChar == *pcExpectedByte ) + { + /* The received character was the expected character. Was + * it the last character in the string - i.e. the null + * terminator? */ + if( cRxedChar == 0x00 ) + { + /* The entire string has been received. If no errors + * have been latched, then increment the loop counter to + * show this task is still healthy. */ + if( xErrorOccurred == pdFALSE ) + { + uxRxLoops++; + + /* Toggle an LED to give a visible sign that a + * complete string has been received. */ + vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET ); + } + + /* Go back to wait for the start of the next string. */ + pcExpectedByte = comTRANSACTED_STRING; + xState = comtstWAITING_START_OF_STRING; + } + else + { + /* Wait for the next character in the string. */ + pcExpectedByte++; + } + } + else + { + /* The character received was not that expected. */ + xErrorOccurred = pdTRUE; + } + + break; + + default: + + /* Should not get here. Stop the Rx loop counter from + * incrementing to latch the error. */ + xErrorOccurred = pdTRUE; + break; + } + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xAreComTestTasksStillRunning( void ) +{ + BaseType_t xReturn; + + /* If the count of successful reception loops has not changed than at + * some time an error occurred (i.e. a character was received out of sequence) + * and false is returned. */ + if( uxRxLoops == 0UL ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Reset the count of successful Rx loops. When this function is called + * again it should have been incremented again. */ + uxRxLoops = 0UL; + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/countsem.c b/SOFTWARE-FreeRTOS/Common/Minimal/countsem.c new file mode 100644 index 0000000..791b4b4 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/countsem.c @@ -0,0 +1,290 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Simple demonstration of the usage of counting semaphore. + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "countsem.h" + +/* The maximum count value that the semaphore used for the demo can hold. */ +#define countMAX_COUNT_VALUE ( 200 ) + +/* Constants used to indicate whether or not the semaphore should have been + * created with its maximum count value, or its minimum count value. These + * numbers are used to ensure that the pointers passed in as the task parameters + * are valid. */ +#define countSTART_AT_MAX_COUNT ( 0xaa ) +#define countSTART_AT_ZERO ( 0x55 ) + +/* Two tasks are created for the test. One uses a semaphore created with its + * count value set to the maximum, and one with the count value set to zero. */ +#define countNUM_TEST_TASKS ( 2 ) +#define countDONT_BLOCK ( 0 ) + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be + * detected in any of the tasks. */ +static volatile BaseType_t xErrorDetected = pdFALSE; + +/*-----------------------------------------------------------*/ + +/* + * The demo task. This simply counts the semaphore up to its maximum value, + * the counts it back down again. The result of each semaphore 'give' and + * 'take' is inspected, with an error being flagged if it is found not to be + * the expected result. + */ +static void prvCountingSemaphoreTask( void * pvParameters ); + +/* + * Utility function to increment the semaphore count value up from zero to + * countMAX_COUNT_VALUE. + */ +static void prvIncrementSemaphoreCount( SemaphoreHandle_t xSemaphore, + volatile UBaseType_t * puxLoopCounter ); + +/* + * Utility function to decrement the semaphore count value up from + * countMAX_COUNT_VALUE to zero. + */ +static void prvDecrementSemaphoreCount( SemaphoreHandle_t xSemaphore, + volatile UBaseType_t * puxLoopCounter ); + +/*-----------------------------------------------------------*/ + +/* The structure that is passed into the task as the task parameter. */ +typedef struct COUNT_SEM_STRUCT +{ + /* The semaphore to be used for the demo. */ + SemaphoreHandle_t xSemaphore; + + /* Set to countSTART_AT_MAX_COUNT if the semaphore should be created with + * its count value set to its max count value, or countSTART_AT_ZERO if it + * should have been created with its count value set to 0. */ + UBaseType_t uxExpectedStartCount; + + /* Incremented on each cycle of the demo task. Used to detect a stalled + * task. */ + volatile UBaseType_t uxLoopCounter; +} xCountSemStruct; + +/* Two structures are defined, one is passed to each test task. */ +static xCountSemStruct xParameters[ countNUM_TEST_TASKS ]; + +/*-----------------------------------------------------------*/ + +void vStartCountingSemaphoreTasks( void ) +{ + /* Create the semaphores that we are going to use for the test/demo. The + * first should be created such that it starts at its maximum count value, + * the second should be created such that it starts with a count value of zero. */ + xParameters[ 0 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, countMAX_COUNT_VALUE ); + xParameters[ 0 ].uxExpectedStartCount = countSTART_AT_MAX_COUNT; + xParameters[ 0 ].uxLoopCounter = 0; + + xParameters[ 1 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, 0 ); + xParameters[ 1 ].uxExpectedStartCount = 0; + xParameters[ 1 ].uxLoopCounter = 0; + + /* Were the semaphores created? */ + if( ( xParameters[ 0 ].xSemaphore != NULL ) || ( xParameters[ 1 ].xSemaphore != NULL ) ) + { + /* vQueueAddToRegistry() adds the semaphore to the registry, if one is + * in use. The registry is provided as a means for kernel aware + * debuggers to locate semaphores and has no purpose if a kernel aware + * debugger is not being used. The call to vQueueAddToRegistry() will be + * removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not + * defined or is defined to be less than 1. */ + vQueueAddToRegistry( ( QueueHandle_t ) xParameters[ 0 ].xSemaphore, "Counting_Sem_1" ); + vQueueAddToRegistry( ( QueueHandle_t ) xParameters[ 1 ].xSemaphore, "Counting_Sem_2" ); + + /* Create the demo tasks, passing in the semaphore to use as the parameter. */ + xTaskCreate( prvCountingSemaphoreTask, "CNT1", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 0 ] ), tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvCountingSemaphoreTask, "CNT2", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 1 ] ), tskIDLE_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvDecrementSemaphoreCount( SemaphoreHandle_t xSemaphore, + volatile UBaseType_t * puxLoopCounter ) +{ + UBaseType_t ux; + + /* If the semaphore count is at its maximum then we should not be able to + * 'give' the semaphore. */ + if( xSemaphoreGive( xSemaphore ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* We should be able to 'take' the semaphore countMAX_COUNT_VALUE times. */ + for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ ) + { + configASSERT( uxSemaphoreGetCount( xSemaphore ) == ( countMAX_COUNT_VALUE - ux ) ); + + if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) != pdPASS ) + { + /* We expected to be able to take the semaphore. */ + xErrorDetected = pdTRUE; + } + + ( *puxLoopCounter )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the semaphore count is zero then we should not be able to 'take' + * the semaphore. */ + configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); + + if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +static void prvIncrementSemaphoreCount( SemaphoreHandle_t xSemaphore, + volatile UBaseType_t * puxLoopCounter ) +{ + UBaseType_t ux; + + /* If the semaphore count is zero then we should not be able to 'take' + * the semaphore. */ + if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* We should be able to 'give' the semaphore countMAX_COUNT_VALUE times. */ + for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ ) + { + configASSERT( uxSemaphoreGetCount( xSemaphore ) == ux ); + + if( xSemaphoreGive( xSemaphore ) != pdPASS ) + { + /* We expected to be able to take the semaphore. */ + xErrorDetected = pdTRUE; + } + + ( *puxLoopCounter )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the semaphore count is at its maximum then we should not be able to + * 'give' the semaphore. */ + if( xSemaphoreGive( xSemaphore ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +static void prvCountingSemaphoreTask( void * pvParameters ) +{ + xCountSemStruct * pxParameter; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const char * const * ppcMessageToSend ); + + const char * const pcTaskStartMsg = "Counting semaphore demo started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + /* The semaphore to be used was passed as the parameter. */ + pxParameter = ( xCountSemStruct * ) pvParameters; + + /* Did we expect to find the semaphore already at its max count value, or + * at zero? */ + if( pxParameter->uxExpectedStartCount == countSTART_AT_MAX_COUNT ) + { + prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) ); + } + + /* Now we expect the semaphore count to be 0, so this time there is an + * error if we can take the semaphore. */ + if( xSemaphoreTake( pxParameter->xSemaphore, 0 ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } + + for( ; ; ) + { + prvIncrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) ); + prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xAreCountingSemaphoreTasksStillRunning( void ) +{ + static UBaseType_t uxLastCount0 = 0, uxLastCount1 = 0; + BaseType_t xReturn = pdPASS; + + /* Return fail if any 'give' or 'take' did not result in the expected + * behaviour. */ + if( xErrorDetected != pdFALSE ) + { + xReturn = pdFAIL; + } + + /* Return fail if either task is not still incrementing its loop counter. */ + if( uxLastCount0 == xParameters[ 0 ].uxLoopCounter ) + { + xReturn = pdFAIL; + } + else + { + uxLastCount0 = xParameters[ 0 ].uxLoopCounter; + } + + if( uxLastCount1 == xParameters[ 1 ].uxLoopCounter ) + { + xReturn = pdFAIL; + } + else + { + uxLastCount1 = xParameters[ 1 ].uxLoopCounter; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/crflash.c b/SOFTWARE-FreeRTOS/Common/Minimal/crflash.c new file mode 100644 index 0000000..1ce0e16 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/crflash.c @@ -0,0 +1,218 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This demo application file demonstrates the use of queues to pass data + * between co-routines. + * + * N represents the number of 'fixed delay' co-routines that are created and + * is set during initialisation. + * + * N 'fixed delay' co-routines are created that just block for a fixed + * period then post the number of an LED onto a queue. Each such co-routine + * uses a different block period. A single 'flash' co-routine is also created + * that blocks on the same queue, waiting for the number of the next LED it + * should flash. Upon receiving a number it simply toggle the instructed LED + * then blocks on the queue once more. In this manner each LED from LED 0 to + * LED N-1 is caused to flash at a different rate. + * + * The 'fixed delay' co-routines are created with co-routine priority 0. The + * flash co-routine is created with co-routine priority 1. This means that + * the queue should never contain more than a single item. This is because + * posting to the queue will unblock the 'flash' co-routine, and as this has + * a priority greater than the tasks posting to the queue it is guaranteed to + * have emptied the queue and blocked once again before the queue can contain + * any more date. An error is indicated if an attempt to post data to the + * queue fails - indicating that the queue is already full. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "queue.h" + +/* Demo application includes. */ +#include "partest.h" +#include "crflash.h" + +/* The queue should only need to be of length 1. See the description at the + * top of the file. */ +#define crfQUEUE_LENGTH 1 + +#define crfFIXED_DELAY_PRIORITY 0 +#define crfFLASH_PRIORITY 1 + +/* Only one flash co-routine is created so the index is not significant. */ +#define crfFLASH_INDEX 0 + +/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be + * created. */ +#define crfMAX_FLASH_TASKS 8 + +/* We don't want to block when posting to the queue. */ +#define crfPOSTING_BLOCK_TIME 0 + +#if ( configUSE_CO_ROUTINES == 1 ) + +/* + * The 'fixed delay' co-routine as described at the top of the file. + */ + static void prvFixedDelayCoRoutine( CoRoutineHandle_t xHandle, + UBaseType_t uxIndex ); + +/* + * The 'flash' co-routine as described at the top of the file. + */ + static void prvFlashCoRoutine( CoRoutineHandle_t xHandle, + UBaseType_t uxIndex ); + +/* The queue used to pass data between the 'fixed delay' co-routines and the + * 'flash' co-routine. */ + static QueueHandle_t xFlashQueue; + +/* This will be set to pdFALSE if we detect an error. */ + static BaseType_t xCoRoutineFlashStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +/* + * See the header file for details. + */ + void vStartFlashCoRoutines( UBaseType_t uxNumberToCreate ) + { + UBaseType_t uxIndex; + + if( uxNumberToCreate > crfMAX_FLASH_TASKS ) + { + uxNumberToCreate = crfMAX_FLASH_TASKS; + } + + /* Create the queue used to pass data between the co-routines. */ + xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( UBaseType_t ) ); + + if( xFlashQueue ) + { + /* Create uxNumberToCreate 'fixed delay' co-routines. */ + for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ ) + { + xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex ); + } + + /* Create the 'flash' co-routine. */ + xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX ); + } + } +/*-----------------------------------------------------------*/ + + static void prvFixedDelayCoRoutine( CoRoutineHandle_t xHandle, + UBaseType_t uxIndex ) + { +/* Even though this is a co-routine the xResult variable does not need to be + * static as we do not need it to maintain its state between blocks. */ + BaseType_t xResult; + +/* The uxIndex parameter of the co-routine function is used as an index into + * the xFlashRates array to obtain the delay period to use. */ + static const TickType_t xFlashRates[ crfMAX_FLASH_TASKS ] = + { + 150 / portTICK_PERIOD_MS, + 200 / portTICK_PERIOD_MS, + 250 / portTICK_PERIOD_MS, + 300 / portTICK_PERIOD_MS, + 350 / portTICK_PERIOD_MS, + 400 / portTICK_PERIOD_MS, + 450 / portTICK_PERIOD_MS, + 500 / portTICK_PERIOD_MS + }; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for( ; ; ) + { + /* Post our uxIndex value onto the queue. This is used as the LED to + * flash. */ + crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult ); + + if( xResult != pdPASS ) + { + /* For the reasons stated at the top of the file we should always + * find that we can post to the queue. If we could not then an error + * has occurred. */ + xCoRoutineFlashStatus = pdFAIL; + } + + crDELAY( xHandle, xFlashRates[ uxIndex ] ); + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); + } +/*-----------------------------------------------------------*/ + + static void prvFlashCoRoutine( CoRoutineHandle_t xHandle, + UBaseType_t uxIndex ) + { +/* Even though this is a co-routine the variable do not need to be + * static as we do not need it to maintain their state between blocks. */ + BaseType_t xResult; + UBaseType_t uxLEDToFlash; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + ( void ) uxIndex; + + for( ; ; ) + { + /* Block to wait for the number of the LED to flash. */ + crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + + if( xResult != pdPASS ) + { + /* We would not expect to wake unless we received something. */ + xCoRoutineFlashStatus = pdFAIL; + } + else + { + /* We received the number of an LED to flash - flash it! */ + vParTestToggleLED( uxLEDToFlash ); + } + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); + } +/*-----------------------------------------------------------*/ + + BaseType_t xAreFlashCoRoutinesStillRunning( void ) + { + /* Return pdPASS or pdFAIL depending on whether an error has been detected + * or not. */ + return xCoRoutineFlashStatus; + } + +#endif /* if ( configUSE_CO_ROUTINES == 1 ) */ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/crhook.c b/SOFTWARE-FreeRTOS/Common/Minimal/crhook.c new file mode 100644 index 0000000..cb8d464 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/crhook.c @@ -0,0 +1,236 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This demo file demonstrates how to send data between an ISR and a + * co-routine. A tick hook function is used to periodically pass data between + * the RTOS tick and a set of 'hook' co-routines. + * + * hookNUM_HOOK_CO_ROUTINES co-routines are created. Each co-routine blocks + * to wait for a character to be received on a queue from the tick ISR, checks + * to ensure the character received was that expected, then sends the number + * back to the tick ISR on a different queue. + * + * The tick ISR checks the numbers received back from the 'hook' co-routines + * matches the number previously sent. + * + * If at any time a queue function returns unexpectedly, or an incorrect value + * is received either by the tick hook or a co-routine then an error is + * latched. + * + * This demo relies on each 'hook' co-routine to execute between each + * hookTICK_CALLS_BEFORE_POST tick interrupts. This and the heavy use of + * queues from within an interrupt may result in an error being detected on + * slower targets simply due to timing. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "queue.h" + +/* Demo application includes. */ +#include "crhook.h" + +/* The number of 'hook' co-routines that are to be created. */ +#define hookNUM_HOOK_CO_ROUTINES ( 4 ) + +/* The number of times the tick hook should be called before a character is + * posted to the 'hook' co-routines. */ +#define hookTICK_CALLS_BEFORE_POST ( 500 ) + +/* There should never be more than one item in any queue at any time. */ +#define hookHOOK_QUEUE_LENGTH ( 1 ) + +/* Don't block when initially posting to the queue. */ +#define hookNO_BLOCK_TIME ( 0 ) + +/* The priority relative to other co-routines (rather than tasks) that the + * 'hook' co-routines should take. */ +#define mainHOOK_CR_PRIORITY ( 1 ) +/*-----------------------------------------------------------*/ +#if ( configUSE_CO_ROUTINES == 1 ) + +/* + * The co-routine function itself. + */ + static void prvHookCoRoutine( CoRoutineHandle_t xHandle, + UBaseType_t uxIndex ); + + +/* + * The tick hook function. This receives a number from each 'hook' co-routine + * then sends a number to each co-routine. An error is flagged if a send or + * receive fails, or an unexpected number is received. + */ + void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +/* Queues used to send data FROM a co-routine TO the tick hook function. + * The hook functions received (Rx's) on these queues. One queue per + * 'hook' co-routine. */ + static QueueHandle_t xHookRxQueues[ hookNUM_HOOK_CO_ROUTINES ]; + +/* Queues used to send data FROM the tick hook TO a co-routine function. + * The hood function transmits (Tx's) on these queues. One queue per + * 'hook' co-routine. */ + static QueueHandle_t xHookTxQueues[ hookNUM_HOOK_CO_ROUTINES ]; + +/* Set to true if an error is detected at any time. */ + static BaseType_t xCoRoutineErrorDetected = pdFALSE; + +/*-----------------------------------------------------------*/ + + void vStartHookCoRoutines( void ) + { + UBaseType_t uxIndex, uxValueToPost = 0; + + for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ ) + { + /* Create a queue to transmit to and receive from each 'hook' + * co-routine. */ + xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( UBaseType_t ) ); + xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( UBaseType_t ) ); + + /* To start things off the tick hook function expects the queue it + * uses to receive data to contain a value. */ + xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME ); + + /* Create the 'hook' co-routine itself. */ + xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex ); + } + } +/*-----------------------------------------------------------*/ + + static UBaseType_t uxCallCounter = 0, uxNumberToPost = 0; + void vApplicationTickHook( void ) + { + UBaseType_t uxReceivedNumber; + BaseType_t xIndex, xCoRoutineWoken; + + /* Is it time to talk to the 'hook' co-routines again? */ + uxCallCounter++; + + if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST ) + { + uxCallCounter = 0; + + for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) + { + xCoRoutineWoken = pdFALSE; + + if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS ) + { + /* There is no reason why we would not expect the queue to + * contain a value. */ + xCoRoutineErrorDetected = pdTRUE; + } + else + { + /* Each queue used to receive data from the 'hook' co-routines + * should contain the number we last posted to the same co-routine. */ + if( uxReceivedNumber != uxNumberToPost ) + { + xCoRoutineErrorDetected = pdTRUE; + } + + /* Nothing should be blocked waiting to post to the queue. */ + if( xCoRoutineWoken != pdFALSE ) + { + xCoRoutineErrorDetected = pdTRUE; + } + } + } + + /* Start the next cycle by posting the next number onto each Tx queue. */ + uxNumberToPost++; + + for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) + { + if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE ) + { + /* Posting to the queue should have woken the co-routine that + * was blocked on the queue. */ + xCoRoutineErrorDetected = pdTRUE; + } + } + } + } +/*-----------------------------------------------------------*/ + + static void prvHookCoRoutine( CoRoutineHandle_t xHandle, + UBaseType_t uxIndex ) + { + static UBaseType_t uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ]; + BaseType_t xResult; + + /* Each co-routine MUST start with a call to crSTART(); */ + crSTART( xHandle ); + + for( ; ; ) + { + /* Wait to receive a value from the tick hook. */ + xResult = pdFAIL; + crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult ); + + /* There is no reason why we should not have received something on + * the queue. */ + if( xResult != pdPASS ) + { + xCoRoutineErrorDetected = pdTRUE; + } + + /* Send the same number back to the idle hook so it can verify it. */ + xResult = pdFAIL; + crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult ); + + if( xResult != pdPASS ) + { + /* There is no reason why we should not have been able to post to + * the queue. */ + xCoRoutineErrorDetected = pdTRUE; + } + } + + /* Each co-routine MUST end with a call to crEND(). */ + crEND(); + } +/*-----------------------------------------------------------*/ + + BaseType_t xAreHookCoRoutinesStillRunning( void ) + { + if( xCoRoutineErrorDetected ) + { + return pdFALSE; + } + else + { + return pdTRUE; + } + } + +#endif /* if ( configUSE_CO_ROUTINES == 1 ) */ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/death.c b/SOFTWARE-FreeRTOS/Common/Minimal/death.c new file mode 100644 index 0000000..1b195d1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/death.c @@ -0,0 +1,200 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * Create a single persistent task which periodically dynamically creates another + * two tasks. The original task is called the creator task, the two tasks it + * creates are called suicidal tasks. + * + * One of the created suicidal tasks kill one other suicidal task before killing + * itself - leaving just the original task remaining. + * + * The creator task must be spawned after all of the other demo application tasks + * as it keeps a check on the number of tasks under the scheduler control. The + * number of tasks it expects to see running should never be greater than the + * number of tasks that were in existence when the creator task was spawned, plus + * one set of four suicidal tasks. If this number is exceeded an error is flagged. + * + * \page DeathC death.c + * \ingroup DemoFiles + *
+ */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "death.h" + +#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 60 ) + +/* The task originally created which is responsible for periodically dynamically + * creating another four tasks. */ +static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters ); + +/* The task function of the dynamically created tasks. */ +static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters ); + +/* A variable which is incremented every time the dynamic tasks are created. This + * is used to check that the task is still running. */ +static volatile uint16_t usCreationCount = 0; + +/* Used to store the number of tasks that were originally running so the creator + * task can tell if any of the suicidal tasks have failed to die. + */ +static volatile UBaseType_t uxTasksRunningAtStart = 0; + +/* When a task deletes itself, it stack and TCB are cleaned up by the Idle task. + * Under heavy load the idle task might not get much processing time, so it would + * be legitimate for several tasks to remain undeleted for a short period. There + * may also be a few other unexpected tasks if, for example, the tasks that test + * static allocation are also being used. */ +static const UBaseType_t uxMaxNumberOfExtraTasksRunning = 3; + +/* Used to store a handle to the task that should be killed by a suicidal task, + * before it kills itself. */ +TaskHandle_t xCreatedTask; + +/*-----------------------------------------------------------*/ + +void vCreateSuicidalTasks( UBaseType_t uxPriority ) +{ + xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) NULL, uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vSuicidalTask, pvParameters ) +{ + volatile long l1, l2; + TaskHandle_t xTaskToKill; + const TickType_t xDelay = pdMS_TO_TICKS( ( TickType_t ) 200 ); + + /* Test deletion of a task's secure context, if any. */ + portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE ); + + if( pvParameters != NULL ) + { + /* This task is periodically created four times. Two created tasks are + * passed a handle to the other task so it can kill it before killing itself. + * The other task is passed in null. */ + xTaskToKill = *( TaskHandle_t * ) pvParameters; + } + else + { + xTaskToKill = NULL; + } + + for( ; ; ) + { + /* Do something random just to use some stack and registers. */ + l1 = 2; + l2 = 89; + l2 *= l1; + vTaskDelay( xDelay ); + + if( xTaskToKill != NULL ) + { + /* Make sure the other task has a go before we delete it. */ + vTaskDelay( ( TickType_t ) 0 ); + + /* Kill the other task that was created by vCreateTasks(). */ + vTaskDelete( xTaskToKill ); + + /* Kill ourselves. */ + vTaskDelete( NULL ); + } + } +} /*lint !e818 !e550 Function prototype must be as per standard for task functions. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCreateTasks, pvParameters ) +{ + const TickType_t xDelay = pdMS_TO_TICKS( ( TickType_t ) 1000 ); + UBaseType_t uxPriority; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Delay at the start to ensure tasks created by other demos have been + * created before storing the current number of tasks. */ + vTaskDelay( xDelay ); + uxTasksRunningAtStart = ( UBaseType_t ) uxTaskGetNumberOfTasks(); + + uxPriority = uxTaskPriorityGet( NULL ); + + for( ; ; ) + { + /* Just loop round, delaying then creating the four suicidal tasks. */ + vTaskDelay( xDelay ); + + xCreatedTask = NULL; + + xTaskCreate( vSuicidalTask, "SUICID1", configMINIMAL_STACK_SIZE, NULL, uxPriority, &xCreatedTask ); + xTaskCreate( vSuicidalTask, "SUICID2", configMINIMAL_STACK_SIZE, &xCreatedTask, uxPriority, NULL ); + + ++usCreationCount; + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the creator task is still running and that there + * are not any more than four extra tasks. */ +BaseType_t xIsCreateTaskStillRunning( void ) +{ + static uint16_t usLastCreationCount = 0xfff; + BaseType_t xReturn = pdTRUE; + static UBaseType_t uxTasksRunningNow; + + if( usLastCreationCount == usCreationCount ) + { + xReturn = pdFALSE; + } + else + { + usLastCreationCount = usCreationCount; + } + + uxTasksRunningNow = ( UBaseType_t ) uxTaskGetNumberOfTasks(); + + if( uxTasksRunningNow < uxTasksRunningAtStart ) + { + xReturn = pdFALSE; + } + else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) + { + xReturn = pdFALSE; + } + else + { + /* Everything is okay. */ + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/dynamic.c b/SOFTWARE-FreeRTOS/Common/Minimal/dynamic.c new file mode 100644 index 0000000..0016855 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/dynamic.c @@ -0,0 +1,488 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The first test creates three tasks - two counter tasks (one continuous count + * and one limited count) and one controller. A "count" variable is shared + * between all three tasks. The two counter tasks should never be in a "ready" + * state at the same time. The controller task runs at the same priority as + * the continuous count task, and at a lower priority than the limited count + * task. + * + * One counter task loops indefinitely, incrementing the shared count variable + * on each iteration. To ensure it has exclusive access to the variable it + * raises its priority above that of the controller task before each + * increment, lowering it again to its original priority before starting the + * next iteration. + * + * The other counter task increments the shared count variable on each + * iteration of its loop until the count has reached a limit of 0xff - at + * which point it suspends itself. It will not start a new loop until the + * controller task has made it "ready" again by calling vTaskResume(). + * This second counter task operates at a higher priority than controller + * task so does not need to worry about mutual exclusion of the counter + * variable. + * + * The controller task is in two sections. The first section controls and + * monitors the continuous count task. When this section is operational the + * limited count task is suspended. Likewise, the second section controls + * and monitors the limited count task. When this section is operational the + * continuous count task is suspended. + * + * In the first section the controller task first takes a copy of the shared + * count variable. To ensure mutual exclusion on the count variable it + * suspends the continuous count task, resuming it again when the copy has been + * taken. The controller task then sleeps for a fixed period - during which + * the continuous count task will execute and increment the shared variable. + * When the controller task wakes it checks that the continuous count task + * has executed by comparing the copy of the shared variable with its current + * value. This time, to ensure mutual exclusion, the scheduler itself is + * suspended with a call to vTaskSuspendAll (). This is for demonstration + * purposes only and is not a recommended technique due to its inefficiency. + * + * After a fixed number of iterations the controller task suspends the + * continuous count task, and moves on to its second section. + * + * At the start of the second section the shared variable is cleared to zero. + * The limited count task is then woken from its suspension by a call to + * vTaskResume (). As this counter task operates at a higher priority than + * the controller task the controller task should not run again until the + * shared variable has been counted up to the limited value causing the counter + * task to suspend itself. The next line after vTaskResume () is therefore + * a check on the shared variable to ensure everything is as expected. + * + * + * The second test consists of a couple of very simple tasks that post onto a + * queue while the scheduler is suspended. This test was added to test parts + * of the scheduler not exercised by the first test. + * + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "dynamic.h" + +/* Function that implements the "limited count" task as described above. */ +static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters ); + +/* Function that implements the "continuous count" task as described above. */ +static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters ); + +/* Function that implements the controller task as described above. */ +static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters ); + +static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters ); +static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters ); + +/* Demo task specific constants. */ +#ifndef priSUSPENDED_RX_TASK_STACK_SIZE + #define priSUSPENDED_RX_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE ) +#endif +#define priSTACK_SIZE ( configMINIMAL_STACK_SIZE ) +#define priSLEEP_TIME pdMS_TO_TICKS( 128 ) +#define priLOOPS ( 5 ) +#define priMAX_COUNT ( ( uint32_t ) 0xff ) +#define priNO_BLOCK ( ( TickType_t ) 0 ) +#define priSUSPENDED_QUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* Handles to the two counter tasks. These could be passed in as parameters + * to the controller task to prevent them having to be file scope. */ +static TaskHandle_t xContinuousIncrementHandle, xLimitedIncrementHandle; + +/* The shared counter variable. This is passed in as a parameter to the two + * counter variables for demonstration purposes. */ +static uint32_t ulCounter; + +/* Variables used to check that the tasks are still operating without error. + * Each complete iteration of the controller task increments this variable + * provided no errors have been found. The variable maintaining the same value + * is therefore indication of an error. */ +static volatile uint16_t usCheckVariable = ( uint16_t ) 0; +static volatile BaseType_t xSuspendedQueueSendError = pdFALSE; +static volatile BaseType_t xSuspendedQueueReceiveError = pdFALSE; + +/* Queue used by the second test. */ +QueueHandle_t xSuspendedTestQueue; + +/* The value the queue receive task expects to receive next. This is file + * scope so xAreDynamicPriorityTasksStillRunning() can ensure it is still + * incrementing. */ +static uint32_t ulExpectedValue = ( uint32_t ) 0; + +/*-----------------------------------------------------------*/ + +/* + * Start the three tasks as described at the top of the file. + * Note that the limited count task is given a higher priority. + */ +void vStartDynamicPriorityTasks( void ) +{ + xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xSuspendedTestQueue != NULL ) + { + /* vQueueAddToRegistry() adds the queue to the queue registry, if one is + * in use. The queue registry is provided as a means for kernel aware + * debuggers to locate queues and has no purpose if a kernel aware debugger + * is not being used. The call to vQueueAddToRegistry() will be removed + * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + * defined to be less than 1. */ + vQueueAddToRegistry( xSuspendedTestQueue, "Suspended_Test_Queue" ); + + xTaskCreate( vContinuousIncrementTask, "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle ); + xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); + xTaskCreate( vCounterControlTask, "C_CTRL", priSUSPENDED_RX_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RX", priSUSPENDED_RX_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +/* + * Just loops around incrementing the shared variable until the limit has been + * reached. Once the limit has been reached it suspends itself. + */ +static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters ) +{ + volatile uint32_t * pulCounter; + + /* Take a pointer to the shared variable from the parameters passed into + * the task. */ + pulCounter = ( volatile uint32_t * ) pvParameters; + + /* This will run before the control task, so the first thing it does is + * suspend - the control task will resume it when ready. */ + vTaskSuspend( NULL ); + + for( ; ; ) + { + /* Just count up to a value then suspend. */ + ( *pulCounter )++; + + if( *pulCounter >= priMAX_COUNT ) + { + vTaskSuspend( NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Just keep counting the shared variable up. The control task will suspend + * this task when it wants. + */ +static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters ) +{ + volatile uint32_t * pulCounter; + UBaseType_t uxOurPriority; + + /* Take a pointer to the shared variable from the parameters passed into + * the task. */ + pulCounter = ( volatile uint32_t * ) pvParameters; + + /* Query our priority so we can raise it when exclusive access to the + * shared variable is required. */ + uxOurPriority = uxTaskPriorityGet( NULL ); + + for( ; ; ) + { + /* Raise the priority above the controller task to ensure a context + * switch does not occur while the variable is being accessed. */ + vTaskPrioritySet( NULL, uxOurPriority + 1 ); + { + configASSERT( ( uxTaskPriorityGet( NULL ) == ( uxOurPriority + 1 ) ) ); + ( *pulCounter )++; + } + vTaskPrioritySet( NULL, uxOurPriority ); + + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + configASSERT( ( uxTaskPriorityGet( NULL ) == uxOurPriority ) ); + } +} +/*-----------------------------------------------------------*/ + +/* + * Controller task as described above. + */ +static portTASK_FUNCTION( vCounterControlTask, pvParameters ) +{ + uint32_t ulLastCounter; + short sLoops; + short sError = pdFALSE; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Start with the counter at zero. */ + ulCounter = ( uint32_t ) 0; + + /* First section : */ + + /* Check the continuous count task is running. */ + for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) + { + /* Suspend the continuous count task so we can take a mirror of the + * shared variable without risk of corruption. This is not really + * needed as the other task raises its priority above this task's + * priority. */ + vTaskSuspend( xContinuousIncrementHandle ); + { + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + ulLastCounter = ulCounter; + } + vTaskResume( xContinuousIncrementHandle ); + + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + #if ( INCLUDE_eTaskGetState == 1 ) + { + #if ( configNUMBER_OF_CORES > 1 ) + { + eTaskState eState = eTaskGetState( xContinuousIncrementHandle ); + configASSERT( ( eState == eReady ) || ( eState == eRunning ) ); + } + #else + { + configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eReady ); + } + #endif + } + #endif /* INCLUDE_eTaskGetState */ + + /* Now delay to ensure the other task has processor time. */ + vTaskDelay( priSLEEP_TIME ); + + /* Check the shared variable again. This time to ensure mutual + * exclusion the whole scheduler will be locked. This is just for + * demo purposes! */ + vTaskSuspendAll(); + { + if( ulLastCounter == ulCounter ) + { + /* The shared variable has not changed. There is a problem + * with the continuous count task so flag an error. */ + sError = pdTRUE; + } + } + xTaskResumeAll(); + } + + /* Second section: */ + + /* Suspend the continuous counter task so it stops accessing the shared + * variable. */ + vTaskSuspend( xContinuousIncrementHandle ); + + /* Reset the variable. */ + ulCounter = ( uint32_t ) 0; + + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Resume the limited count task which has a higher priority than us. + * We should therefore not return from this call until the limited count + * task has suspended itself with a known value in the counter variable. */ + vTaskResume( xLimitedIncrementHandle ); + + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + /* This task should not run again until xLimitedIncrementHandle has + * suspended itself. */ + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Does the counter variable have the expected value? */ + if( ulCounter != priMAX_COUNT ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If no errors have occurred then increment the check variable. */ + portENTER_CRITICAL(); + usCheckVariable++; + portEXIT_CRITICAL(); + } + + /* Resume the continuous count task and do it all again. */ + vTaskResume( xContinuousIncrementHandle ); + + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters ) +{ + static uint32_t ulValueToSend = ( uint32_t ) 0; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ; ; ) + { + vTaskSuspendAll(); + { + /* We must not block while the scheduler is suspended! */ + if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) + { + xSuspendedQueueSendError = pdTRUE; + } + } + xTaskResumeAll(); + + vTaskDelay( priSLEEP_TIME ); + + ++ulValueToSend; + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters ) +{ + uint32_t ulReceivedValue; + BaseType_t xGotValue; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ; ; ) + { + do + { + /* Suspending the scheduler here is fairly pointless and + * undesirable for a normal application. It is done here purely + * to test the scheduler. The inner xTaskResumeAll() should + * never return pdTRUE as the scheduler is still locked by the + * outer call. */ + vTaskSuspendAll(); + { + vTaskSuspendAll(); + { + xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); + } + + if( xTaskResumeAll() != pdFALSE ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + } + xTaskResumeAll(); + + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } while( xGotValue == pdFALSE ); + + if( ulReceivedValue != ulExpectedValue ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + + if( xSuspendedQueueReceiveError != pdTRUE ) + { + /* Only increment the variable if an error has not occurred. This + * allows xAreDynamicPriorityTasksStillRunning() to check for stalled + * tasks as well as explicit errors. */ + ++ulExpectedValue; + } + } +} +/*-----------------------------------------------------------*/ + +/* Called to check that all the created tasks are still running without error. */ +BaseType_t xAreDynamicPriorityTasksStillRunning( void ) +{ +/* Keep a history of the check variables so we know if it has been incremented + * since the last call. */ + static uint16_t usLastTaskCheck = ( uint16_t ) 0; + static uint32_t ulLastExpectedValue = ( uint32_t ) 0U; + BaseType_t xReturn = pdTRUE; + + /* Check the tasks are still running by ensuring the check variable + * is still incrementing. */ + + if( usCheckVariable == usLastTaskCheck ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( ulExpectedValue == ulLastExpectedValue ) + { + /* The value being received by the queue receive task has not + * incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( xSuspendedQueueSendError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xSuspendedQueueReceiveError == pdTRUE ) + { + xReturn = pdFALSE; + } + + usLastTaskCheck = usCheckVariable; + ulLastExpectedValue = ulExpectedValue; + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/flash.c b/SOFTWARE-FreeRTOS/Common/Minimal/flash.c new file mode 100644 index 0000000..01aa0c2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/flash.c @@ -0,0 +1,117 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * This version of flash .c is for use on systems that have limited stack space + * and no display facilities. The complete version can be found in the + * Demo/Common/Full directory. + * + * Three tasks are created, each of which flash an LED at a different rate. The first + * LED flashes every 200ms, the second every 400ms, the third every 600ms. + * + * The LED flash tasks provide instant visual feedback. They show that the scheduler + * is still operational. + * + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash.h" + +#define ledSTACK_SIZE configMINIMAL_STACK_SIZE +#define ledNUMBER_OF_LEDS ( 3 ) +#define ledFLASH_RATE_BASE ( ( TickType_t ) 333 ) + +/* Variable used by the created tasks to calculate the LED number to use, and + * the rate at which they should flash the LED. */ +static volatile UBaseType_t uxFlashTaskNumber = 0; + +/* The task that is created three times. */ +static portTASK_FUNCTION_PROTO( vLEDFlashTask, pvParameters ); + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTasks( UBaseType_t uxPriority ) +{ + BaseType_t xLEDTask; + + /* Create the three tasks. */ + for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask ) + { + /* Spawn the task. */ + xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vLEDFlashTask, pvParameters ) +{ + TickType_t xFlashRate, xLastFlashTime; + UBaseType_t uxLED; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Calculate the LED and flash rate. */ + portENTER_CRITICAL(); + { + /* See which of the eight LED's we should use. */ + uxLED = uxFlashTaskNumber; + + /* Update so the next task uses the next LED. */ + uxFlashTaskNumber++; + } + portEXIT_CRITICAL(); + + xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( TickType_t ) uxLED ); + xFlashRate /= portTICK_PERIOD_MS; + + /* We will turn the LED on and off again in the delay period, so each + * delay is only half the total period. */ + xFlashRate /= ( TickType_t ) 2; + + /* We need to initialise xLastFlashTime prior to the first call to + * vTaskDelayUntil(). */ + xLastFlashTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Delay for half the flash period then turn the LED on. */ + vTaskDelayUntil( &xLastFlashTime, xFlashRate ); + vParTestToggleLED( uxLED ); + + /* Delay for half the flash period then turn the LED off. */ + vTaskDelayUntil( &xLastFlashTime, xFlashRate ); + vParTestToggleLED( uxLED ); + } +} /*lint !e715 !e818 !e830 Function definition must be standard for task creation. */ diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/flash_timer.c b/SOFTWARE-FreeRTOS/Common/Minimal/flash_timer.c new file mode 100644 index 0000000..7dfb61d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/flash_timer.c @@ -0,0 +1,95 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * Repeatedly toggles one or more LEDs using software timers - one timer per + * LED. + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "timers.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash_timer.h" + +/* The toggle rates are all a multple of ledFLASH_RATE_BASE. */ +#define ledFLASH_RATE_BASE ( ( ( TickType_t ) 333 ) / portTICK_PERIOD_MS ) + +/* A block time of zero simple means "don't block". */ +#define ledDONT_BLOCK ( ( TickType_t ) 0 ) + +/*-----------------------------------------------------------*/ + +/* + * The callback function used by each LED flashing timer. All the timers use + * this function, and the timer ID is used within the function to determine + * which timer has actually expired. + */ +static void prvLEDTimerCallback( TimerHandle_t xTimer ); + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTimers( UBaseType_t uxNumberOfLEDs ) +{ + UBaseType_t uxLEDTimer; + TimerHandle_t xTimer; + + /* Create and start the requested number of timers. */ + for( uxLEDTimer = 0; uxLEDTimer < uxNumberOfLEDs; ++uxLEDTimer ) + { + /* Create the timer. */ + xTimer = xTimerCreate( "Flasher", /* A text name, purely to help debugging. */ + ledFLASH_RATE_BASE * ( uxLEDTimer + 1 ), /* The timer period, which is a multiple of ledFLASH_RATE_BASE. */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) uxLEDTimer, /* The ID is used to identify the timer within the timer callback function, as each timer uses the same callback. */ + prvLEDTimerCallback /* Each timer uses the same callback. */ + ); + + /* If the timer was created successfully, attempt to start it. If the + * scheduler has not yet been started then the timer command queue must + * be long enough to hold each command sent to it until such time that the + * scheduler is started. The timer command queue length is set by + * configTIMER_QUEUE_LENGTH in FreeRTOSConfig.h. */ + if( xTimer != NULL ) + { + xTimerStart( xTimer, ledDONT_BLOCK ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvLEDTimerCallback( TimerHandle_t xTimer ) +{ + BaseType_t xTimerID; + + /* The timer ID is used to identify the timer that has actually expired as + * each timer uses the same callback. The ID is then also used as the number + * of the LED that is to be toggled. */ + xTimerID = ( BaseType_t ) pvTimerGetTimerID( xTimer ); + vParTestToggleLED( xTimerID ); +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/flop.c b/SOFTWARE-FreeRTOS/Common/Minimal/flop.c new file mode 100644 index 0000000..5188c68 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/flop.c @@ -0,0 +1,346 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Creates eight tasks, each of which loops continuously performing a floating + * point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle + * priority means that these tasks will get pre-empted any time another task is + * ready to run or a time slice occurs. More often than not the pre-emption + * will occur mid calculation, creating a good test of the schedulers context + * switch mechanism - a calculation producing an unexpected result could be a + * symptom of a corruption in the context of a task. + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "flop.h" + +#ifndef mathSTACK_SIZE + #define mathSTACK_SIZE configMINIMAL_STACK_SIZE +#endif + +#define mathNUMBER_OF_TASKS ( 4 ) + +/* Four tasks, each of which performs a different floating point calculation. + * Each of the four is created twice. */ +static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a + * task gets a calculation wrong it will stop setting its check variable. */ +static uint16_t usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( UBaseType_t uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) +{ + volatile portDOUBLE d1, d2, d3, d4; + volatile uint16_t * pusTaskCheckVariable; + volatile portDOUBLE dAnswer; + short sError = pdFALSE; + + /* Some ports require that tasks that use a hardware floating point unit + * tell the kernel that they require a floating point context before any + * floating point instructions are executed. */ + portTASK_USES_FLOATING_POINT(); + + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + dAnswer = ( d1 + d2 ) * d3; + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ; ; ) + { + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + d4 = ( d1 + d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + * increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct then set set the check + * variable. The check variable will get set to pdFALSE each time + * xAreMathsTaskStillRunning() is executed. */ + ( *pusTaskCheckVariable ) = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) +{ + volatile portDOUBLE d1, d2, d3, d4; + volatile uint16_t * pusTaskCheckVariable; + volatile portDOUBLE dAnswer; + short sError = pdFALSE; + + /* Some ports require that tasks that use a hardware floating point unit + * tell the kernel that they require a floating point context before any + * floating point instructions are executed. */ + portTASK_USES_FLOATING_POINT(); + + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + dAnswer = ( d1 / d2 ) * d3; + + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ; ; ) + { + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + d4 = ( d1 / d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + * increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct then set set the check + * variable. The check variable will get set to pdFALSE each time + * xAreMathsTaskStillRunning() is executed. */ + ( *pusTaskCheckVariable ) = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) +{ + volatile portDOUBLE * pdArray, dTotal1, dTotal2, dDifference; + volatile uint16_t * pusTaskCheckVariable; + const size_t xArraySize = 10; + size_t xPosition; + short sError = pdFALSE; + + /* Some ports require that tasks that use a hardware floating point unit + * tell the kernel that they require a floating point context before any + * floating point instructions are executed. */ + portTASK_USES_FLOATING_POINT(); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + * array. Then run through the array adding up all the values. If the two totals + * do not match, stop the check variable from incrementing. */ + for( ; ; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5; + dTotal1 += ( portDOUBLE ) xPosition + 5.5; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct then set set the check + * variable. The check variable will get set to pdFALSE each time + * xAreMathsTaskStillRunning() is executed. */ + ( *pusTaskCheckVariable ) = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) +{ + volatile portDOUBLE * pdArray, dTotal1, dTotal2, dDifference; + volatile uint16_t * pusTaskCheckVariable; + const size_t xArraySize = 10; + size_t xPosition; + short sError = pdFALSE; + + /* Some ports require that tasks that use a hardware floating point unit + * tell the kernel that they require a floating point context before any + * floating point instructions are executed. */ + portTASK_USES_FLOATING_POINT(); + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + * array. Then run through the array adding up all the values. If the two totals + * do not match, stop the check variable from incrementing. */ + for( ; ; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123; + dTotal1 += ( portDOUBLE ) xPosition * 12.123; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct then set set the check + * variable. The check variable will get set to pdFALSE each time + * xAreMathsTaskStillRunning() is executed. */ + ( *pusTaskCheckVariable ) = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreMathsTaskStillRunning( void ) +{ + BaseType_t xReturn = pdPASS, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + * have been set to pdPASS. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] != pdTRUE ) + { + /* The check has not been set so the associated task has either + * stalled or detected an error. */ + xReturn = pdFAIL; + } + else + { + /* Reset the variable so it can be checked again the next time this + * function is executed. */ + usTaskCheck[ xTask ] = pdFALSE; + } + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/integer.c b/SOFTWARE-FreeRTOS/Common/Minimal/integer.c new file mode 100644 index 0000000..cc0bdef --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/integer.c @@ -0,0 +1,161 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Creates one or more tasks that repeatedly perform a set of integer + * calculations. The result of each run-time calculation is compared to the + * known expected result - with a mismatch being indicative of an error in the + * context switch mechanism. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "integer.h" + +/* The constants used in the calculation. */ +#define intgCONST1 ( ( long ) 123 ) +#define intgCONST2 ( ( long ) 234567 ) +#define intgCONST3 ( ( long ) -3 ) +#define intgCONST4 ( ( long ) 7 ) +#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) + +#define intgSTACK_SIZE configMINIMAL_STACK_SIZE + +/* As this is the minimal version, we will only create one task. */ +#define intgNUMBER_OF_TASKS ( 1 ) + +/* The task function. Repeatedly performs a 32 bit calculation, checking the + * result against the expected result. If the result is incorrect then the + * context switch must have caused some corruption. */ +static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters ); + +/* Variables that are set to true within the calculation task to indicate + * that the task is still executing. The check task sets the variable back to + * false, flagging an error if the variable is still false the next time it + * is called. */ +static BaseType_t xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( BaseType_t ) pdFALSE }; + +/*-----------------------------------------------------------*/ + +void vStartIntegerMathTasks( UBaseType_t uxPriority ) +{ + short sTask; + + for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) + { + xTaskCreate( vCompeteingIntMathTask, "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( TaskHandle_t * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters ) +{ +/* These variables are all effectively set to constants so they are volatile to + * ensure the compiler does not just get rid of them. */ + volatile long lValue; + short sError = pdFALSE; + volatile BaseType_t * pxTaskHasExecuted; + + /* Set a pointer to the variable we are going to set to true each + * iteration. This is also a good test of the parameter passing mechanism + * within each port. */ + pxTaskHasExecuted = ( volatile BaseType_t * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ; ; ) + { + /* Perform the calculation. This will store partial value in + * registers, resulting in a good test of the context switch mechanism. */ + lValue = intgCONST1; + lValue += intgCONST2; + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + + /* Finish off the calculation. */ + lValue *= intgCONST3; + lValue /= intgCONST4; + + /* If the calculation is found to be incorrect we stop setting the + * TaskHasExecuted variable so the check task can see an error has + * occurred. */ + if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */ + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* We have not encountered any errors, so set the flag that show + * we are still executing. This will be periodically cleared by + * the check task. */ + portENTER_CRITICAL(); + *pxTaskHasExecuted = pdTRUE; + portEXIT_CRITICAL(); + } + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreIntegerMathsTaskStillRunning( void ) +{ + BaseType_t xReturn = pdTRUE; + short sTask; + + /* Check the maths tasks are still running by ensuring their check variables + * are still being set to true. */ + for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) + { + if( xTaskCheck[ sTask ] == pdFALSE ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + /* Reset the check variable so we can tell if it has been set by + * the next time around. */ + xTaskCheck[ sTask ] = pdFALSE; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/readme.txt b/SOFTWARE-FreeRTOS/Common/Minimal/readme.txt new file mode 100644 index 0000000..9e5ee6c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/readme.txt @@ -0,0 +1,2 @@ +This directory contains the implementation of the "common demo tasks". These +are test tasks and demo tasks that are used by nearly all the demo applications. \ No newline at end of file diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/recmutex.c b/SOFTWARE-FreeRTOS/Common/Minimal/recmutex.c new file mode 100644 index 0000000..39bf9a4 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/recmutex.c @@ -0,0 +1,411 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The tasks defined on this page demonstrate the use of recursive mutexes. + * + * For recursive mutex functionality the created mutex should be created using + * xSemaphoreCreateRecursiveMutex(), then be manipulated + * using the xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() API + * functions. + * + * This demo creates three tasks all of which access the same recursive mutex: + * + * prvRecursiveMutexControllingTask() has the highest priority so executes + * first and grabs the mutex. It then performs some recursive accesses - + * between each of which it sleeps for a short period to let the lower + * priority tasks execute. When it has completed its demo functionality + * it gives the mutex back before suspending itself. + * + * prvRecursiveMutexBlockingTask() attempts to access the mutex by performing + * a blocking 'take'. The blocking task has a lower priority than the + * controlling task so by the time it executes the mutex has already been + * taken by the controlling task, causing the blocking task to block. It + * does not unblock until the controlling task has given the mutex back, + * and it does not actually run until the controlling task has suspended + * itself (due to the relative priorities). When it eventually does obtain + * the mutex all it does is give the mutex back prior to also suspending + * itself. At this point both the controlling task and the blocking task are + * suspended. + * + * prvRecursiveMutexPollingTask() runs at the idle priority. It spins round + * a tight loop attempting to obtain the mutex with a non-blocking call. As + * the lowest priority task it will not successfully obtain the mutex until + * both the controlling and blocking tasks are suspended. Once it eventually + * does obtain the mutex it first unsuspends both the controlling task and + * blocking task prior to giving the mutex back - resulting in the polling + * task temporarily inheriting the controlling tasks priority. + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "recmutex.h" + +/* Priorities assigned to the three tasks. recmuCONTROLLING_TASK_PRIORITY can + * be overridden by a definition in FreeRTOSConfig.h. */ +#ifndef recmuCONTROLLING_TASK_PRIORITY + #define recmuCONTROLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#endif +#define recmuBLOCKING_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define recmuPOLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 ) + +/* The recursive call depth. */ +#define recmuMAX_COUNT ( 10 ) + +/* Misc. */ +#define recmuSHORT_DELAY ( pdMS_TO_TICKS( 20 ) ) +#define recmuNO_DELAY ( ( TickType_t ) 0 ) +#define recmu15ms_DELAY ( pdMS_TO_TICKS( 15 ) ) + +#ifndef recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE + #define recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE +#endif + +/* The three tasks as described at the top of this file. */ +static void prvRecursiveMutexControllingTask( void * pvParameters ); +static void prvRecursiveMutexBlockingTask( void * pvParameters ); +static void prvRecursiveMutexPollingTask( void * pvParameters ); + +/* The mutex used by the demo. */ +static SemaphoreHandle_t xMutex; + +/* Variables used to detect and latch errors. */ +static volatile BaseType_t xErrorOccurred = pdFALSE, xControllingIsSuspended = pdFALSE, xBlockingIsSuspended = pdFALSE; +static volatile UBaseType_t uxControllingCycles = 0, uxBlockingCycles = 0, uxPollingCycles = 0; + +/* Handles of the two higher priority tasks, required so they can be resumed + * (unsuspended). */ +static TaskHandle_t xControllingTaskHandle, xBlockingTaskHandle; + +/*-----------------------------------------------------------*/ + +void vStartRecursiveMutexTasks( void ) +{ + /* Just creates the mutex and the three tasks. */ + + xMutex = xSemaphoreCreateRecursiveMutex(); + + if( xMutex != NULL ) + { + /* vQueueAddToRegistry() adds the mutex to the registry, if one is + * in use. The registry is provided as a means for kernel aware + * debuggers to locate mutex and has no purpose if a kernel aware debugger + * is not being used. The call to vQueueAddToRegistry() will be removed + * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is + * defined to be less than 1. */ + vQueueAddToRegistry( ( QueueHandle_t ) xMutex, "Recursive_Mutex" ); + + xTaskCreate( prvRecursiveMutexControllingTask, "Rec1", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuCONTROLLING_TASK_PRIORITY, &xControllingTaskHandle ); + xTaskCreate( prvRecursiveMutexBlockingTask, "Rec2", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuBLOCKING_TASK_PRIORITY, &xBlockingTaskHandle ); + xTaskCreate( prvRecursiveMutexPollingTask, "Rec3", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuPOLLING_TASK_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexControllingTask( void * pvParameters ) +{ + UBaseType_t ux; + + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Should not be able to 'give' the mutex, as we have not yet 'taken' + * it. The first time through, the mutex will not have been used yet, + * subsequent times through, at this point the mutex will be held by the + * polling task. */ + if( xSemaphoreGiveRecursive( xMutex ) == pdPASS ) + { + xErrorOccurred = __LINE__; + } + + for( ux = 0; ux < recmuMAX_COUNT; ux++ ) + { + /* We should now be able to take the mutex as many times as + * we like. + * + * The first time through the mutex will be immediately available, on + * subsequent times through the mutex will be held by the polling task + * at this point and this Take will cause the polling task to inherit + * the priority of this task. In this case the block time must be + * long enough to ensure the polling task will execute again before the + * block time expires. If the block time does expire then the error + * flag will be set here. */ + if( xSemaphoreTakeRecursive( xMutex, recmu15ms_DELAY ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + /* Ensure the other task attempting to access the mutex (and the + * other demo tasks) are able to execute to ensure they either block + * (where a block time is specified) or return an error (where no + * block time is specified) as the mutex is held by this task. */ + vTaskDelay( recmuSHORT_DELAY ); + } + + /* For each time we took the mutex, give it back. */ + for( ux = 0; ux < recmuMAX_COUNT; ux++ ) + { + /* Ensure the other task attempting to access the mutex (and the + * other demo tasks) are able to execute. */ + vTaskDelay( recmuSHORT_DELAY ); + + /* We should now be able to give the mutex as many times as we + * took it. When the mutex is available again the Blocking task + * should be unblocked but not run because it has a lower priority + * than this task. The polling task should also not run at this point + * as it too has a lower priority than this task. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + } + + /* Having given it back the same number of times as it was taken, we + * should no longer be the mutex owner, so the next give should fail. */ + if( xSemaphoreGiveRecursive( xMutex ) == pdPASS ) + { + xErrorOccurred = __LINE__; + } + + /* Keep count of the number of cycles this task has performed so a + * stall can be detected. */ + uxControllingCycles++; + + /* Suspend ourselves so the blocking task can execute. */ + xControllingIsSuspended = pdTRUE; + vTaskSuspend( NULL ); + xControllingIsSuspended = pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexBlockingTask( void * pvParameters ) +{ + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* This task will run while the controlling task is blocked, and the + * controlling task will block only once it has the mutex - therefore + * this call should block until the controlling task has given up the + * mutex, and not actually execute past this call until the controlling + * task is suspended. portMAX_DELAY - 1 is used instead of portMAX_DELAY + * to ensure the task's state is reported as Blocked and not Suspended in + * a later call to configASSERT() (within the polling task). */ + if( xSemaphoreTakeRecursive( xMutex, ( portMAX_DELAY - 1 ) ) == pdPASS ) + { + if( xControllingIsSuspended != pdTRUE ) + { + /* Did not expect to execute until the controlling task was + * suspended. */ + xErrorOccurred = __LINE__; + } + else + { + /* Give the mutex back before suspending ourselves to allow + * the polling task to obtain the mutex. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + xBlockingIsSuspended = pdTRUE; + vTaskSuspend( NULL ); + xBlockingIsSuspended = pdFALSE; + } + } + else + { + /* We should not leave the xSemaphoreTakeRecursive() function + * until the mutex was obtained. */ + xErrorOccurred = __LINE__; + } + + /* The controlling and blocking tasks should be in lock step. */ + if( uxControllingCycles != ( UBaseType_t ) ( uxBlockingCycles + 1 ) ) + { + xErrorOccurred = __LINE__; + } + + /* Keep count of the number of cycles this task has performed so a + * stall can be detected. */ + uxBlockingCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexPollingTask( void * pvParameters ) +{ + /* Just to remove compiler warning. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Keep attempting to obtain the mutex. It should only be obtained when + * the blocking task has suspended itself, which in turn should only + * happen when the controlling task is also suspended. */ + if( xSemaphoreTakeRecursive( xMutex, recmuNO_DELAY ) == pdPASS ) + { + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xControllingTaskHandle ) == eSuspended ); + configASSERT( eTaskGetState( xBlockingTaskHandle ) == eSuspended ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Is the blocking task suspended? */ + if( ( xBlockingIsSuspended != pdTRUE ) || ( xControllingIsSuspended != pdTRUE ) ) + { + xErrorOccurred = __LINE__; + } + else + { + /* Keep count of the number of cycles this task has performed + * so a stall can be detected. */ + uxPollingCycles++; + + /* We can resume the other tasks here even though they have a + * higher priority than the polling task. When they execute they + * will attempt to obtain the mutex but fail because the polling + * task is still the mutex holder. The polling task (this task) + * will then inherit the higher priority. The Blocking task will + * block indefinitely when it attempts to obtain the mutex, the + * Controlling task will only block for a fixed period and an + * error will be latched if the polling task has not returned the + * mutex by the time this fixed period has expired. */ + vTaskResume( xBlockingTaskHandle ); + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + vTaskResume( xControllingTaskHandle ); + #if ( configUSE_PREEMPTION == 0 ) + taskYIELD(); + #endif + + /* The other two tasks should now have executed and no longer + * be suspended. */ + if( ( xBlockingIsSuspended == pdTRUE ) || ( xControllingIsSuspended == pdTRUE ) ) + { + xErrorOccurred = __LINE__; + } + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + { + /* Check priority inherited. */ + configASSERT( uxTaskPriorityGet( NULL ) == recmuCONTROLLING_TASK_PRIORITY ); + } + #endif /* INCLUDE_uxTaskPriorityGet */ + + #if ( INCLUDE_eTaskGetState == 1 ) + { + configASSERT( eTaskGetState( xControllingTaskHandle ) == eBlocked ); + configASSERT( eTaskGetState( xBlockingTaskHandle ) == eBlocked ); + } + #endif /* INCLUDE_eTaskGetState */ + + /* Release the mutex, disinheriting the higher priority again. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = __LINE__; + } + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + { + /* Check priority disinherited. */ + configASSERT( uxTaskPriorityGet( NULL ) == recmuPOLLING_TASK_PRIORITY ); + } + #endif /* INCLUDE_uxTaskPriorityGet */ + } + } + + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreRecursiveMutexTasksStillRunning( void ) +{ + BaseType_t xReturn; + static UBaseType_t uxLastControllingCycles = 0, uxLastBlockingCycles = 0, uxLastPollingCycles = 0; + + /* Is the controlling task still cycling? */ + if( uxLastControllingCycles == uxControllingCycles ) + { + xErrorOccurred = __LINE__; + } + else + { + uxLastControllingCycles = uxControllingCycles; + } + + /* Is the blocking task still cycling? */ + if( uxLastBlockingCycles == uxBlockingCycles ) + { + xErrorOccurred = __LINE__; + } + else + { + uxLastBlockingCycles = uxBlockingCycles; + } + + /* Is the polling task still cycling? */ + if( uxLastPollingCycles == uxPollingCycles ) + { + xErrorOccurred = __LINE__; + } + else + { + uxLastPollingCycles = uxPollingCycles; + } + + if( xErrorOccurred != pdFALSE ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdPASS; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/semtest.c b/SOFTWARE-FreeRTOS/Common/Minimal/semtest.c new file mode 100644 index 0000000..29d2850 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/semtest.c @@ -0,0 +1,271 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Creates two sets of two tasks. The tasks within a set share a variable, access + * to which is guarded by a semaphore. + * + * Each task starts by attempting to obtain the semaphore. On obtaining a + * semaphore a task checks to ensure that the guarded variable has an expected + * value. It then clears the variable to zero before counting it back up to the + * expected value in increments of 1. After each increment the variable is checked + * to ensure it contains the value to which it was just set. When the starting + * value is again reached the task releases the semaphore giving the other task in + * the set a chance to do exactly the same thing. The starting value is high + * enough to ensure that a tick is likely to occur during the incrementing loop. + * + * An error is flagged if at any time during the process a shared variable is + * found to have a value other than that expected. Such an occurrence would + * suggest an error in the mutual exclusion mechanism by which access to the + * variable is restricted. + * + * The first set of two tasks poll their semaphore. The second set use blocking + * calls. + * + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "semtest.h" + +/* The value to which the shared variables are counted. */ +#define semtstBLOCKING_EXPECTED_VALUE ( ( uint32_t ) 0xfff ) +#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( uint32_t ) 0xff ) + +#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE + +#define semtstNUM_TASKS ( 4 ) + +#define semtstDELAY_FACTOR ( ( TickType_t ) 10 ) + +/* The task function as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters ); + +/* Structure used to pass parameters to each task. */ +typedef struct SEMAPHORE_PARAMETERS +{ + SemaphoreHandle_t xSemaphore; + volatile uint32_t * pulSharedVariable; + TickType_t xBlockTime; +} xSemaphoreParameters; + +/* Variables used to check that all the tasks are still running without errors. */ +static volatile short sCheckVariables[ semtstNUM_TASKS ] = { 0 }; +static volatile short sNextCheckVariable = 0; + +/*-----------------------------------------------------------*/ + +void vStartSemaphoreTasks( UBaseType_t uxPriority ) +{ + xSemaphoreParameters * pxFirstSemaphoreParameters, * pxSecondSemaphoreParameters; + const TickType_t xBlockTime = ( TickType_t ) 100; + + /* Create the structure used to pass parameters to the first two tasks. */ + pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxFirstSemaphoreParameters != NULL ) + { + /* Create the semaphore used by the first two tasks. */ + pxFirstSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary(); + + if( pxFirstSemaphoreParameters->xSemaphore != NULL ) + { + xSemaphoreGive( pxFirstSemaphoreParameters->xSemaphore ); + + /* Create the variable which is to be shared by the first two tasks. */ + pxFirstSemaphoreParameters->pulSharedVariable = ( uint32_t * ) pvPortMalloc( sizeof( uint32_t ) ); + + /* Initialise the share variable to the value the tasks expect. */ + *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; + + /* The first two tasks do not block on semaphore calls. */ + pxFirstSemaphoreParameters->xBlockTime = ( TickType_t ) 0; + + /* Spawn the first two tasks. As they poll they operate at the idle priority. */ + xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL ); + xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL ); + + /* vQueueAddToRegistry() adds the semaphore to the registry, if one + * is in use. The registry is provided as a means for kernel aware + * debuggers to locate semaphores and has no purpose if a kernel aware + * debugger is not being used. The call to vQueueAddToRegistry() will + * be removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not + * defined or is defined to be less than 1. */ + vQueueAddToRegistry( ( QueueHandle_t ) pxFirstSemaphoreParameters->xSemaphore, "Counting_Sem_1" ); + } + } + + /* Do exactly the same to create the second set of tasks, only this time + * provide a block time for the semaphore calls. */ + pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxSecondSemaphoreParameters != NULL ) + { + pxSecondSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary(); + + if( pxSecondSemaphoreParameters->xSemaphore != NULL ) + { + xSemaphoreGive( pxSecondSemaphoreParameters->xSemaphore ); + + pxSecondSemaphoreParameters->pulSharedVariable = ( uint32_t * ) pvPortMalloc( sizeof( uint32_t ) ); + *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; + pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_PERIOD_MS; + + xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL ); + xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL ); + + /* vQueueAddToRegistry() adds the semaphore to the registry, if one + * is in use. The registry is provided as a means for kernel aware + * debuggers to locate semaphores and has no purpose if a kernel aware + * debugger is not being used. The call to vQueueAddToRegistry() will + * be removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not + * defined or is defined to be less than 1. */ + vQueueAddToRegistry( ( QueueHandle_t ) pxSecondSemaphoreParameters->xSemaphore, "Counting_Sem_2" ); + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( prvSemaphoreTest, pvParameters ) +{ + xSemaphoreParameters * pxParameters; + volatile uint32_t * pulSharedVariable, ulExpectedValue; + uint32_t ulCounter; + short sError = pdFALSE, sCheckVariableToUse; + + /* See which check variable to use. sNextCheckVariable is not semaphore + * protected! */ + portENTER_CRITICAL(); + sCheckVariableToUse = sNextCheckVariable; + sNextCheckVariable++; + portEXIT_CRITICAL(); + + /* A structure is passed in as the parameter. This contains the shared + * variable being guarded. */ + pxParameters = ( xSemaphoreParameters * ) pvParameters; + pulSharedVariable = pxParameters->pulSharedVariable; + + /* If we are blocking we use a much higher count to ensure loads of context + * switches occur during the count. */ + if( pxParameters->xBlockTime > ( TickType_t ) 0 ) + { + ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; + } + else + { + ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; + } + + for( ; ; ) + { + /* Try to obtain the semaphore. */ + if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) + { + /* We have the semaphore and so expect any other tasks using the + * shared variable to have left it in the state we expect to find + * it. */ + if( *pulSharedVariable != ulExpectedValue ) + { + sError = pdTRUE; + } + + /* Clear the variable, then count it back up to the expected value + * before releasing the semaphore. Would expect a context switch or + * two during this time. */ + for( ulCounter = ( uint32_t ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) + { + *pulSharedVariable = ulCounter; + + if( *pulSharedVariable != ulCounter ) + { + sError = pdTRUE; + } + } + + /* Release the semaphore, and if no errors have occurred increment the check + * variable. */ + if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + if( sCheckVariableToUse < semtstNUM_TASKS ) + { + ( sCheckVariables[ sCheckVariableToUse ] )++; + } + } + + /* If we have a block time then we are running at a priority higher + * than the idle priority. This task takes a long time to complete + * a cycle (deliberately so to test the guarding) so will be starving + * out lower priority tasks. Block for some time to allow give lower + * priority tasks some processor time. */ + if( pxParameters->xBlockTime != ( TickType_t ) 0 ) + { + vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); + } + } + else + { + if( pxParameters->xBlockTime == ( TickType_t ) 0 ) + { + /* We have not got the semaphore yet, so no point using the + * processor. We are not blocking when attempting to obtain the + * semaphore. */ + taskYIELD(); + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreSemaphoreTasksStillRunning( void ) +{ + static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; + BaseType_t xTask, xReturn = pdTRUE; + + for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) + { + if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) + { + xReturn = pdFALSE; + } + + sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/Minimal/sp_flop.c b/SOFTWARE-FreeRTOS/Common/Minimal/sp_flop.c new file mode 100644 index 0000000..997c377 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/Minimal/sp_flop.c @@ -0,0 +1,324 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Creates eight tasks, each of which loops continuously performing a floating + * point calculation - using single precision variables. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "flop.h" + +#define mathSTACK_SIZE configMINIMAL_STACK_SIZE +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. + * Each of the four is created twice. */ +static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a + * task gets a calculation wrong it will + * stop incrementing its check variable. */ +static volatile uint16_t usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( UBaseType_t uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) +{ + volatile float f1, f2, f3, f4; + volatile uint16_t * pusTaskCheckVariable; + volatile float fAnswer; + short sError = pdFALSE; + + f1 = 123.4567F; + f2 = 2345.6789F; + f3 = -918.222F; + + fAnswer = ( f1 + f2 ) * f3; + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( uint16_t * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ; ; ) + { + f1 = 123.4567F; + f2 = 2345.6789F; + f3 = -918.222F; + + f4 = ( f1 + f2 ) * f3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + * increment of the check variable. */ + if( fabs( f4 - fAnswer ) > 0.001F ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) +{ + volatile float f1, f2, f3, f4; + volatile uint16_t * pusTaskCheckVariable; + volatile float fAnswer; + short sError = pdFALSE; + + f1 = -389.38F; + f2 = 32498.2F; + f3 = -2.0001F; + + fAnswer = ( f1 / f2 ) * f3; + + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( uint16_t * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ; ; ) + { + f1 = -389.38F; + f2 = 32498.2F; + f3 = -2.0001F; + + f4 = ( f1 / f2 ) * f3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + * increment of the check variable. */ + if( fabs( f4 - fAnswer ) > 0.001F ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know + * this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) +{ + volatile float * pfArray, fTotal1, fTotal2, fDifference, fPosition; + volatile uint16_t * pusTaskCheckVariable; + const size_t xArraySize = 10; + size_t xPosition; + short sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( uint16_t * ) pvParameters; + + pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + * array. Then run through the array adding up all the values. If the two totals + * do not match, stop the check variable from incrementing. */ + for( ; ; ) + { + fTotal1 = 0.0F; + fTotal2 = 0.0F; + fPosition = 0.0F; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pfArray[ xPosition ] = fPosition + 5.5F; + fTotal1 += fPosition + 5.5F; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + fTotal2 += pfArray[ xPosition ]; + } + + fDifference = fTotal1 - fTotal2; + + if( fabs( fDifference ) > 0.001F ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) +{ + volatile float * pfArray, fTotal1, fTotal2, fDifference, fPosition; + volatile uint16_t * pusTaskCheckVariable; + const size_t xArraySize = 10; + size_t xPosition; + short sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + * as the parameter. */ + pusTaskCheckVariable = ( uint16_t * ) pvParameters; + + pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + * array. Then run through the array adding up all the values. If the two totals + * do not match, stop the check variable from incrementing. */ + for( ; ; ) + { + fTotal1 = 0.0F; + fTotal2 = 0.0F; + fPosition = 0.0F; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pfArray[ xPosition ] = fPosition * 12.123F; + fTotal1 += fPosition * 12.123F; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + fTotal2 += pfArray[ xPosition ]; + } + + fDifference = fTotal1 - fTotal2; + + if( fabs( fDifference ) > 0.001F ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + * variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +BaseType_t xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented + * since the last call. */ + static uint16_t usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 }; + BaseType_t xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + * are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} diff --git a/SOFTWARE-FreeRTOS/Common/ReadMe.txt b/SOFTWARE-FreeRTOS/Common/ReadMe.txt new file mode 100644 index 0000000..769b122 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ReadMe.txt @@ -0,0 +1,14 @@ +Contains the files that are not specific to any one demo, but are instead used +by all the demo applications. + +Most of the directories are now obsolete, and only maintained for backward +compatibility. The directories in active use are: + ++ Minimal - this contains the implementation of what are referred to as the +"Standard Demo Tasks". These are used by all the demo applications. Their only +purpose is to demonstrate the FreeRTOS API and test the FreeRTOS features. The +directory is called 'Minimal' as it contains a minimal implementation of files +contained in the 'Full' directory - but the 'Full' directory is no longer used. + ++ include - contains header files for the C source files located in the Minimal +directory. \ No newline at end of file diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/AT91SAM9XE128.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/AT91SAM9XE128.h new file mode 100644 index 0000000..e548551 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/AT91SAM9XE128.h @@ -0,0 +1,4042 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the disclaimer below in the documentation and/or +// other materials provided with the distribution. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM9XE128.h +// Object : AT91SAM9XE128 definitions +// Generated : AT91 SW Application Group 02/13/2008 (18:26:05) +// +// CVS Reference : /AT91SAM9XE128.pl/1.3/Wed Jan 30 13:58:28 2008// +// CVS Reference : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008// +// CVS Reference : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007// +// CVS Reference : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007// +// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004// +// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004// +// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004// +// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005// +// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:53:02 2006// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006// +// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005// +// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005// +// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005// +// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM9XE128_H +#define AT91SAM9XE128_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG Reserved0[2560]; // + AT91_REG ECC_CR; // ECC reset register + AT91_REG ECC_MR; // ECC Page size register + AT91_REG ECC_SR; // ECC Status register + AT91_REG ECC_PR; // ECC Parity register + AT91_REG ECC_NPR; // ECC Parity N register + AT91_REG Reserved1[58]; // + AT91_REG ECC_VR; // ECC Version register + AT91_REG Reserved2[64]; // + AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register + AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register + AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register + AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register + AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register + AT91_REG Reserved3[118]; // + AT91_REG SMC_SETUP0; // Setup Register for CS 0 + AT91_REG SMC_PULSE0; // Pulse Register for CS 0 + AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 + AT91_REG SMC_CTRL0; // Control Register for CS 0 + AT91_REG SMC_SETUP1; // Setup Register for CS 1 + AT91_REG SMC_PULSE1; // Pulse Register for CS 1 + AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 + AT91_REG SMC_CTRL1; // Control Register for CS 1 + AT91_REG SMC_SETUP2; // Setup Register for CS 2 + AT91_REG SMC_PULSE2; // Pulse Register for CS 2 + AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 + AT91_REG SMC_CTRL2; // Control Register for CS 2 + AT91_REG SMC_SETUP3; // Setup Register for CS 3 + AT91_REG SMC_PULSE3; // Pulse Register for CS 3 + AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 + AT91_REG SMC_CTRL3; // Control Register for CS 3 + AT91_REG SMC_SETUP4; // Setup Register for CS 4 + AT91_REG SMC_PULSE4; // Pulse Register for CS 4 + AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 + AT91_REG SMC_CTRL4; // Control Register for CS 4 + AT91_REG SMC_SETUP5; // Setup Register for CS 5 + AT91_REG SMC_PULSE5; // Pulse Register for CS 5 + AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 + AT91_REG SMC_CTRL5; // Control Register for CS 5 + AT91_REG SMC_SETUP6; // Setup Register for CS 6 + AT91_REG SMC_PULSE6; // Pulse Register for CS 6 + AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 + AT91_REG SMC_CTRL6; // Control Register for CS 6 + AT91_REG SMC_SETUP7; // Setup Register for CS 7 + AT91_REG SMC_PULSE7; // Pulse Register for CS 7 + AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 + AT91_REG SMC_CTRL7; // Control Register for CS 7 + AT91_REG Reserved4[96]; // + AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) + AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) + AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) + AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi) + AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) + AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) + AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) + AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) + AT91_REG Reserved5[8]; // + AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) + AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) + AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) + AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi) + AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) + AT91_REG Reserved6[11]; // + AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) + AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) + AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) + AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) + AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) + AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) + AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs + AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs + AT91_REG MATRIX_PRAS4; // PRAS4 : ebi + AT91_REG MATRIX_PRBS4; // PRBS4 : ebi + AT91_REG Reserved7[22]; // + AT91_REG MATRIX_MRCR; // Master Remp Control Register + AT91_REG Reserved8[6]; // + AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register + AT91_REG Reserved9[3]; // + AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register + AT91_REG Reserved10[51]; // + AT91_REG CCFG_MATRIXVERSION; // Version Register + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved11[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved12[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved13[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved14[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved15[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved16[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved18[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved19[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved20[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved21[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved22[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved23[213]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved24[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved25[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved26[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved27[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved28[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved29[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved30[85]; // + AT91_REG PIOC_PER; // PIO Enable Register + AT91_REG PIOC_PDR; // PIO Disable Register + AT91_REG PIOC_PSR; // PIO Status Register + AT91_REG Reserved31[1]; // + AT91_REG PIOC_OER; // Output Enable Register + AT91_REG PIOC_ODR; // Output Disable Registerr + AT91_REG PIOC_OSR; // Output Status Register + AT91_REG Reserved32[1]; // + AT91_REG PIOC_IFER; // Input Filter Enable Register + AT91_REG PIOC_IFDR; // Input Filter Disable Register + AT91_REG PIOC_IFSR; // Input Filter Status Register + AT91_REG Reserved33[1]; // + AT91_REG PIOC_SODR; // Set Output Data Register + AT91_REG PIOC_CODR; // Clear Output Data Register + AT91_REG PIOC_ODSR; // Output Data Status Register + AT91_REG PIOC_PDSR; // Pin Data Status Register + AT91_REG PIOC_IER; // Interrupt Enable Register + AT91_REG PIOC_IDR; // Interrupt Disable Register + AT91_REG PIOC_IMR; // Interrupt Mask Register + AT91_REG PIOC_ISR; // Interrupt Status Register + AT91_REG PIOC_MDER; // Multi-driver Enable Register + AT91_REG PIOC_MDDR; // Multi-driver Disable Register + AT91_REG PIOC_MDSR; // Multi-driver Status Register + AT91_REG Reserved34[1]; // + AT91_REG PIOC_PPUDR; // Pull-up Disable Register + AT91_REG PIOC_PPUER; // Pull-up Enable Register + AT91_REG PIOC_PPUSR; // Pull-up Status Register + AT91_REG Reserved35[1]; // + AT91_REG PIOC_ASR; // Select A Register + AT91_REG PIOC_BSR; // Select B Register + AT91_REG PIOC_ABSR; // AB Select Status Register + AT91_REG Reserved36[9]; // + AT91_REG PIOC_OWER; // Output Write Enable Register + AT91_REG PIOC_OWDR; // Output Write Disable Register + AT91_REG PIOC_OWSR; // Output Write Status Register + AT91_REG Reserved37[85]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved38[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved39[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG PMC_PLLAR; // PLL A Register + AT91_REG PMC_PLLBR; // PLL B Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved40[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved41[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved42[1]; // + AT91_REG SHDWC_SHCR; // Shut Down Control Register + AT91_REG SHDWC_SHMR; // Shut Down Mode Register + AT91_REG SHDWC_SHSR; // Shut Down Status Register + AT91_REG Reserved43[1]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved44[1]; // + AT91_REG SYS_GPBR[4]; // General Purpose Register +} AT91S_SYS, *AT91PS_SYS; +#else +#define SYS_GPBR (AT91_CAST(AT91_REG *) 0x00003D50) // (SYS_GPBR) General Purpose Register + +#endif +// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- +#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR External Bus Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EBI { + AT91_REG EBI_DUMMY; // Dummy register - Do not use +} AT91S_EBI, *AT91PS_EBI; +#else +#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Error Correction Code controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ECC { + AT91_REG ECC_CR; // ECC reset register + AT91_REG ECC_MR; // ECC Page size register + AT91_REG ECC_SR; // ECC Status register + AT91_REG ECC_PR; // ECC Parity register + AT91_REG ECC_NPR; // ECC Parity N register + AT91_REG Reserved0[58]; // + AT91_REG ECC_VR; // ECC Version register +} AT91S_ECC, *AT91PS_ECC; +#else +#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register +#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register +#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register +#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register +#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register +#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register + +#endif +// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- +#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity +// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- +#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size +// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- +#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error +#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error +#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR +// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- +#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error +#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit +// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- +#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N +// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- +#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR SDRAM Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SDRAMC { + AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register + AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register + AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register + AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register + AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register +} AT91S_SDRAMC, *AT91PS_SDRAMC; +#else +#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register +#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register +#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register +#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register +#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register +#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register +#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register +#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register +#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register +#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register + +#endif +// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- +#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode +#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode +#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access +#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access +#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access +#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh +#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register +#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode +// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- +#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter +// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- +#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits +#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits +#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits +#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits +#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits +#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits +#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits +#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits +#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits +#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks +#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks +#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks +#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency +#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles +#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles +#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width +#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus +#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus +#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles +#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles +#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles +#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles +#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles +#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles +#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15 +// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- +#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit +#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle +#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle +// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- +#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations +#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features +#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH +#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN +#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN +#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM) +#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM) +#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM) +#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled +#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately +#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer +#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer +// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status +// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- +// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- +#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type +#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode +#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Static Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SMC { + AT91_REG SMC_SETUP0; // Setup Register for CS 0 + AT91_REG SMC_PULSE0; // Pulse Register for CS 0 + AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 + AT91_REG SMC_CTRL0; // Control Register for CS 0 + AT91_REG SMC_SETUP1; // Setup Register for CS 1 + AT91_REG SMC_PULSE1; // Pulse Register for CS 1 + AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 + AT91_REG SMC_CTRL1; // Control Register for CS 1 + AT91_REG SMC_SETUP2; // Setup Register for CS 2 + AT91_REG SMC_PULSE2; // Pulse Register for CS 2 + AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 + AT91_REG SMC_CTRL2; // Control Register for CS 2 + AT91_REG SMC_SETUP3; // Setup Register for CS 3 + AT91_REG SMC_PULSE3; // Pulse Register for CS 3 + AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 + AT91_REG SMC_CTRL3; // Control Register for CS 3 + AT91_REG SMC_SETUP4; // Setup Register for CS 4 + AT91_REG SMC_PULSE4; // Pulse Register for CS 4 + AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 + AT91_REG SMC_CTRL4; // Control Register for CS 4 + AT91_REG SMC_SETUP5; // Setup Register for CS 5 + AT91_REG SMC_PULSE5; // Pulse Register for CS 5 + AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 + AT91_REG SMC_CTRL5; // Control Register for CS 5 + AT91_REG SMC_SETUP6; // Setup Register for CS 6 + AT91_REG SMC_PULSE6; // Pulse Register for CS 6 + AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 + AT91_REG SMC_CTRL6; // Control Register for CS 6 + AT91_REG SMC_SETUP7; // Setup Register for CS 7 + AT91_REG SMC_PULSE7; // Pulse Register for CS 7 + AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 + AT91_REG SMC_CTRL7; // Control Register for CS 7 +} AT91S_SMC, *AT91PS_SMC; +#else +#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0 +#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0 +#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0 +#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0 +#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1 +#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1 +#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1 +#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1 +#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2 +#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2 +#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2 +#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2 +#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3 +#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3 +#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3 +#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3 +#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4 +#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4 +#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4 +#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4 +#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5 +#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5 +#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5 +#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5 +#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6 +#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6 +#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6 +#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6 +#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7 +#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7 +#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7 +#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7 + +#endif +// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- +#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length +#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access +#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length +#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access +// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- +#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length +#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access +#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length +#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access +// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- +#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length +#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length +// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- +#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode +#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode +#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode +#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled. +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode. +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode. +#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type +#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. +#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. +#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width +#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits. +#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits. +#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits. +#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time. +#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled. +#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled. +#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size +#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes. +#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes. +#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes. +#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes. +// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR AHB Matrix Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MATRIX { + AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) + AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) + AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) + AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi) + AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) + AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) + AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) + AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) + AT91_REG Reserved0[8]; // + AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) + AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) + AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) + AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi) + AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) + AT91_REG Reserved1[11]; // + AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) + AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) + AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) + AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) + AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) + AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) + AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs + AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs + AT91_REG MATRIX_PRAS4; // PRAS4 : ebi + AT91_REG MATRIX_PRBS4; // PRBS4 : ebi + AT91_REG Reserved2[22]; // + AT91_REG MATRIX_MRCR; // Master Remp Control Register + AT91_REG Reserved3[6]; // + AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register + AT91_REG Reserved4[3]; // + AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register + AT91_REG Reserved5[51]; // + AT91_REG MATRIX_VERSION; // Version Register +} AT91S_MATRIX, *AT91PS_MATRIX; +#else +#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k) +#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom) +#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs) +#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi) +#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge) +#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox) +#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k) +#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog) +#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k) +#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom) +#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs) +#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi) +#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge) +#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0) +#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0) +#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1) +#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1) +#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2) +#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2) +#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs +#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs +#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi +#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi +#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register +#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register +#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register +#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register + +#endif +// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- +#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst +#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type +#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. +#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. +#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. +#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master +// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master +// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master +// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- +#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority +#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority +#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority +#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority +#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority +#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority +#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority +#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority +// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- +#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority +// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- +// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- +// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- +// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- +// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- +// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- +// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- +// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- +// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- +#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master +#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master +// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- +#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment +#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment +#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. +#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment +#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. +#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. +#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment +#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC +#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. +#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration +// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- +#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB +#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled +#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled +#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine +#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled +#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled +#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset +#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled +#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled +#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Chip Configuration Registers +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CCFG { + AT91_REG Reserved0[3]; // + AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register + AT91_REG Reserved1[55]; // + AT91_REG CCFG_MATRIXVERSION; // Version Register +} AT91S_CCFG, *AT91PS_CCFG; +#else +#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register +#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register + +#endif +// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- +#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment +#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment +#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. +#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment +#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. +#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. +#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment +#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC +#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. +#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration +#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // EFC Flash Mode Register + AT91_REG EFC_FCR; // EFC Flash Command Register + AT91_REG EFC_FSR; // EFC Flash Status Register + AT91_REG EFC_FRR; // EFC Flash Result Register + AT91_REG EFC_FVR; // EFC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; +#else +#define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register +#define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register +#define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register +#define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register +#define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000010) // (EFC_FVR) EFC Flash Version Register + +#endif +// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- +#define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable +#define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State. +#define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State +#define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State +#define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States +#define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States +// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- +#define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command +#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor +#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page +#define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock +#define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page +#define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock +#define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All +#define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane +#define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages +#define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit +#define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit +#define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit +#define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit +#define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit +#define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit +#define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument +#define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key +// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- +#define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status +#define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status +#define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status +// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- +#define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG CKGR_PLLAR; // PLL A Register + AT91_REG CKGR_PLLBR; // PLL B Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register +#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- +#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected +#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0 +#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed +#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter +#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range +#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier +#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) +// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected +#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0 +#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed +#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter +#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range +#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG PMC_PLLAR; // PLL A Register + AT91_REG PMC_PLLBR; // PLL B Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved2[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock +#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- +// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected +#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division +#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same +#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock +#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Shut Down Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SHDWC { + AT91_REG SHDWC_SHCR; // Shut Down Control Register + AT91_REG SHDWC_SHMR; // Shut Down Mode Register + AT91_REG SHDWC_SHSR; // Shut Down Status Register +} AT91S_SHDWC, *AT91PS_SHDWC; +#else +#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register +#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register +#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register + +#endif +// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- +#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset +#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password +// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- +#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection +#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input. +#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level. +#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level. +#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change. +#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0 +#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection +#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input. +#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level. +#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level. +#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change. +#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1 +#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable +#define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable +// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- +#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status +#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status +#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status +#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up +#define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Multimedia Card Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MCI { + AT91_REG MCI_CR; // MCI Control Register + AT91_REG MCI_MR; // MCI Mode Register + AT91_REG MCI_DTOR; // MCI Data Timeout Register + AT91_REG MCI_SDCR; // MCI SD Card Register + AT91_REG MCI_ARGR; // MCI Argument Register + AT91_REG MCI_CMDR; // MCI Command Register + AT91_REG MCI_BLKR; // MCI Block Register + AT91_REG Reserved0[1]; // + AT91_REG MCI_RSPR[4]; // MCI Response Register + AT91_REG MCI_RDR; // MCI Receive Data Register + AT91_REG MCI_TDR; // MCI Transmit Data Register + AT91_REG Reserved1[2]; // + AT91_REG MCI_SR; // MCI Status Register + AT91_REG MCI_IER; // MCI Interrupt Enable Register + AT91_REG MCI_IDR; // MCI Interrupt Disable Register + AT91_REG MCI_IMR; // MCI Interrupt Mask Register + AT91_REG Reserved2[43]; // + AT91_REG MCI_VR; // MCI Version Register + AT91_REG MCI_RPR; // Receive Pointer Register + AT91_REG MCI_RCR; // Receive Counter Register + AT91_REG MCI_TPR; // Transmit Pointer Register + AT91_REG MCI_TCR; // Transmit Counter Register + AT91_REG MCI_RNPR; // Receive Next Pointer Register + AT91_REG MCI_RNCR; // Receive Next Counter Register + AT91_REG MCI_TNPR; // Transmit Next Pointer Register + AT91_REG MCI_TNCR; // Transmit Next Counter Register + AT91_REG MCI_PTCR; // PDC Transfer Control Register + AT91_REG MCI_PTSR; // PDC Transfer Status Register +} AT91S_MCI, *AT91PS_MCI; +#else +#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register +#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register +#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register +#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register +#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register +#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register +#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register +#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register +#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register +#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register +#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register +#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register +#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register +#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register +#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register + +#endif +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable +#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable +#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable +#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable +#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider +#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider +#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable +#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable +#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer +#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value +#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode +#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number +#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier +#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1 +#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16 +#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128 +#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256 +#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024 +#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096 +#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536 +#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576 +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector +#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number +#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type +#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response +#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response +#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response +#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD +#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD +#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD +#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD +#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command +#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response +#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command +#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond +#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD +#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer +#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer +#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer +#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction +#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type +#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type +#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type +#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type +#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type +#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type +#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command +#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command +#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command +#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command +// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- +#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag +#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag +#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag +#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag +#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag +#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag +#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag +#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag +#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A +#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B +#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C +#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D +#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag +#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag +#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag +#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag +#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag +#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag +#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag +#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag +#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag +#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag +#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved1[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode) +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode) +#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode) +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode) +#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode) +#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode) +#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode) +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Host Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UHP { + AT91_REG UHP_HcRevision; // Revision + AT91_REG UHP_HcControl; // Operating modes for the Host Controller + AT91_REG UHP_HcCommandStatus; // Command & status Register + AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register + AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register + AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register + AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area + AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor + AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list + AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register + AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list + AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list + AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor + AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs + AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame + AT91_REG UHP_HcFmNumber; // Frame number + AT91_REG UHP_HcPeriodicStart; // Periodic Start + AT91_REG UHP_HcLSThreshold; // LS Threshold + AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A + AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B + AT91_REG UHP_HcRhStatus; // Root Hub Status register + AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register +} AT91S_UHP, *AT91PS_UHP; +#else +#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision +#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller +#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register +#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register +#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register +#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register +#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area +#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor +#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list +#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register +#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list +#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list +#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor +#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs +#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame +#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number +#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start +#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold +#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A +#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B +#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register +#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Image Sensor Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ISI { + AT91_REG ISI_CR1; // Control Register 1 + AT91_REG ISI_CR2; // Control Register 2 + AT91_REG ISI_SR; // Status Register + AT91_REG ISI_IER; // Interrupt Enable Register + AT91_REG ISI_IDR; // Interrupt Disable Register + AT91_REG ISI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[2]; // + AT91_REG ISI_PSIZE; // Preview Size Register + AT91_REG ISI_PDECF; // Preview Decimation Factor Register + AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register + AT91_REG ISI_CDBA; // Codec Dma Address Register + AT91_REG ISI_Y2RSET0; // Color Space Conversion Register + AT91_REG ISI_Y2RSET1; // Color Space Conversion Register + AT91_REG ISI_R2YSET0; // Color Space Conversion Register + AT91_REG ISI_R2YSET1; // Color Space Conversion Register + AT91_REG ISI_R2YSET2; // Color Space Conversion Register +} AT91S_ISI, *AT91PS_ISI; +#else +#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1 +#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2 +#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register +#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register +#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register +#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register +#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register +#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register +#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register +#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register +#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register +#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register +#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register +#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register +#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register + +#endif +// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- +#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset +#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable. +#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity +#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity +#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation +#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction +#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed +#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask +#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed +#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed +#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed +#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path +#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay +#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay +// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- +#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047] +#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode +#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode +#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits +#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits +#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits +#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode +#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap +#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data +#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047] +#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1) +#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1) +#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i) +#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i) +#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration +#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B +#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R +#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB) +#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB) +// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- +#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame +#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable +#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset +#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error +#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow +#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow +#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty +#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty +#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun +// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- +// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- +// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- +// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- +#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path +#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path +// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- +#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0 +#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1 +#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2 +#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3 +// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- +#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4 +#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset +#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset +#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset +// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- +#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0 +#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1 +#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2 +#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset +// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- +#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3 +#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4 +#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5 +#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset +// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- +#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6 +#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7 +#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8 +#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM9XE128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFFFF) // (SYS) General Purpose Register +// ========== Register definition for EBI peripheral ========== +#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (EBI) Dummy register - Do not use +// ========== Register definition for HECC peripheral ========== +#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFE8FC) // (HECC) ECC Version register +#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (HECC) ECC Parity N register +#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (HECC) ECC Status register +#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (HECC) ECC Parity register +#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (HECC) ECC Page size register +#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (HECC) ECC reset register +// ========== Register definition for SDRAMC peripheral ========== +#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register +#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register +#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register +#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register +#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register +#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register +#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register +#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register +// ========== Register definition for SMC peripheral ========== +#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1 +#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7 +#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6 +#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4 +#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3 +#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5 +#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2 +#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2 +#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0 +#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5 +#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1 +#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0 +#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7 +#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4 +#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3 +#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7 +#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7 +#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1 +#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0 +#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5 +#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1 +#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6 +#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0 +#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4 +#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5 +#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2 +#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3 +#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6 +#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6 +#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4 +#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2 +#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3 +// ========== Register definition for MATRIX peripheral ========== +#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k) +#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (MATRIX) Master Configuration Register 7 (teak_prog) +#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom) +#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge) +#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (MATRIX) Version Register +#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs) +#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA4) // (MATRIX) PRBS4 : ebi +#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX) PRBS0 (ram0) +#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi) +#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (MATRIX) Master Configuration Register 6 (ram16k) +#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (MATRIX) Slave 3 (ebi) Special Function Register +#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k) +#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEE9C) // (MATRIX) PRBS3 : usb_dev_hs +#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEE98) // (MATRIX) PRAS3 : usb_dev_hs +#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX) PRAS0 (ram0) +#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi) +#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEE88) // (MATRIX) PRAS1 (ram1) +#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEE90) // (MATRIX) PRAS2 (ram2) +#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs) +#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox) +#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom) +#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA0) // (MATRIX) PRAS4 : ebi +#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register +#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEE94) // (MATRIX) PRBS2 (ram2) +#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge) +#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0xFFFFEF2C) // (MATRIX) Slave 7 (teak_prog) Special Function Register +#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEE8C) // (MATRIX) PRBS1 (ram1) +// ========== Register definition for CCFG peripheral ========== +#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (CCFG) Version Register +#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for PIOC peripheral ========== +#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register +#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register +#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register +#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register +#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register +#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register +#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr +#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register +#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register +#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register +#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register +#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register +#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register +#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register +#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register +#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register +#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register +#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register +#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register +#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register +#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register +#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register +#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register +#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register +#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register +#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register +#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register +#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register +#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register +// ========== Register definition for EFC peripheral ========== +#define AT91C_EFC_FVR (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (EFC) EFC Flash Version Register +#define AT91C_EFC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (EFC) EFC Flash Command Register +#define AT91C_EFC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (EFC) EFC Flash Mode Register +#define AT91C_EFC_FRR (AT91_CAST(AT91_REG *) 0xFFFFFA0C) // (EFC) EFC Flash Result Register +#define AT91C_EFC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (EFC) EFC Flash Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for SHDWC peripheral ========== +#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register +#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register +#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TC3 peripheral ========== +#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (TC3) Interrupt Enable Register +#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFDC018) // (TC3) Register B +#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (TC3) Register C +#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (TC3) Channel Control Register +#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (TC3) Status Register +#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFDC010) // (TC3) Counter Value +#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFDC014) // (TC3) Register A +#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (TC3) Interrupt Disable Register +#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (TC3) Interrupt Mask Register +// ========== Register definition for TC4 peripheral ========== +#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (TC4) Register C +#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFDC060) // (TC4) Status Register +#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFDC058) // (TC4) Register B +#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFDC064) // (TC4) Interrupt Enable Register +#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFDC050) // (TC4) Counter Value +#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFDC054) // (TC4) Register A +#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFDC068) // (TC4) Interrupt Disable Register +#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (TC4) Interrupt Mask Register +#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFDC040) // (TC4) Channel Control Register +// ========== Register definition for TC5 peripheral ========== +#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFDC098) // (TC5) Register B +#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFDC094) // (TC5) Register A +#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFDC090) // (TC5) Counter Value +#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFDC080) // (TC5) Channel Control Register +#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (TC5) Status Register +#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (TC5) Interrupt Enable Register +#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (TC5) Interrupt Disable Register +#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (TC5) Register C +#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (TC5) Interrupt Mask Register +#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode) +// ========== Register definition for TCB0 peripheral ========== +#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register +#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register +// ========== Register definition for TCB1 peripheral ========== +#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (TCB1) TC Block Control Register +#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (TCB1) TC Block Mode Register +// ========== Register definition for PDC_MCI peripheral ========== +#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register +#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register +#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register +#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register +#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register +#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register +#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register +#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register +#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register +#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register +// ========== Register definition for MCI peripheral ========== +#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register +#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register +#define AT91C_MCI_VR (AT91_CAST(AT91_REG *) 0xFFFA80FC) // (MCI) MCI Version Register +#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register +#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register +#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register +#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register +#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register +#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register +#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register +#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register +#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register +#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD Card Register +#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register +#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register +// ========== Register definition for PDC_TWI0 peripheral ========== +#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register +#define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_TWI0) Receive Pointer Register +#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register +#define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_TWI0) Receive Counter Register +#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register +#define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register +#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register +#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register +#define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register +#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register +// ========== Register definition for TWI0 peripheral ========== +#define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI0) Transmit Holding Register +#define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI0) Interrupt Disable Register +#define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI0) Slave Mode Register +#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI0) Clock Waveform Generator Register +#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI0) Internal Address Register +#define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI0) Receive Holding Register +#define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI0) Interrupt Enable Register +#define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI0) Master Mode Register +#define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI0) Status Register +#define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI0) Interrupt Mask Register +#define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI0) Control Register +// ========== Register definition for PDC_TWI1 peripheral ========== +#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register +#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register +#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register +#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register +#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register +#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register +#define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_TWI1) Receive Pointer Register +#define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_TWI1) Transmit Counter Register +#define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register +#define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_TWI1) Receive Counter Register +// ========== Register definition for TWI1 peripheral ========== +#define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0xFFFD8030) // (TWI1) Receive Holding Register +#define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (TWI1) Interrupt Enable Register +#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0xFFFD8010) // (TWI1) Clock Waveform Generator Register +#define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (TWI1) Master Mode Register +#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0xFFFD800C) // (TWI1) Internal Address Register +#define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0xFFFD8034) // (TWI1) Transmit Holding Register +#define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (TWI1) Interrupt Mask Register +#define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (TWI1) Status Register +#define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (TWI1) Interrupt Disable Register +#define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (TWI1) Control Register +#define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0xFFFD8008) // (TWI1) Slave Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register +// ========== Register definition for PDC_US2 peripheral ========== +#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register +#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register +#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register +#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register +#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register +#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register +#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register +#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register +#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register +#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register +// ========== Register definition for US2 peripheral ========== +#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register +#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register +#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register +#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register +#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register +#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register +#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register +#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register +#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register +#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register +#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register +#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register +#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register +#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register +// ========== Register definition for PDC_US3 peripheral ========== +#define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_US3) Receive Next Pointer Register +#define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_US3) Receive Next Counter Register +#define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_US3) PDC Transfer Status Register +#define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_US3) PDC Transfer Control Register +#define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_US3) Transmit Counter Register +#define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register +#define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_US3) Receive Counter Register +#define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_US3) Transmit Pointer Register +#define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_US3) Transmit Next Counter Register +#define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_US3) Receive Pointer Register +// ========== Register definition for US3 peripheral ========== +#define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (US3) Nb Errors Register +#define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (US3) Receiver Time-out Register +#define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (US3) Interrupt Disable Register +#define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (US3) Mode Register +#define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0xFFFD0040) // (US3) FI_DI_Ratio Register +#define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (US3) Baud Rate Generator Register +#define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (US3) Transmitter Holding Register +#define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (US3) Control Register +#define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0xFFFD004C) // (US3) IRDA_FILTER Register +#define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0xFFFD0008) // (US3) Interrupt Enable Register +#define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (US3) Transmitter Time-guard Register +#define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (US3) Receiver Holding Register +#define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (US3) Interrupt Mask Register +#define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (US3) Channel Status Register +// ========== Register definition for PDC_US4 peripheral ========== +#define AT91C_US4_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_US4) Transmit Next Counter Register +#define AT91C_US4_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_US4) Receive Pointer Register +#define AT91C_US4_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_US4) Receive Next Counter Register +#define AT91C_US4_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_US4) Transmit Pointer Register +#define AT91C_US4_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_US4) PDC Transfer Control Register +#define AT91C_US4_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_US4) Transmit Counter Register +#define AT91C_US4_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_US4) Receive Counter Register +#define AT91C_US4_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_US4) Receive Next Pointer Register +#define AT91C_US4_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register +#define AT91C_US4_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_US4) PDC Transfer Status Register +// ========== Register definition for US4 peripheral ========== +#define AT91C_US4_BRGR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (US4) Baud Rate Generator Register +#define AT91C_US4_THR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (US4) Transmitter Holding Register +#define AT91C_US4_RTOR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (US4) Receiver Time-out Register +#define AT91C_US4_IMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (US4) Interrupt Mask Register +#define AT91C_US4_NER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (US4) Nb Errors Register +#define AT91C_US4_TTGR (AT91_CAST(AT91_REG *) 0xFFFD4028) // (US4) Transmitter Time-guard Register +#define AT91C_US4_FIDI (AT91_CAST(AT91_REG *) 0xFFFD4040) // (US4) FI_DI_Ratio Register +#define AT91C_US4_MR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (US4) Mode Register +#define AT91C_US4_IER (AT91_CAST(AT91_REG *) 0xFFFD4008) // (US4) Interrupt Enable Register +#define AT91C_US4_RHR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (US4) Receiver Holding Register +#define AT91C_US4_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (US4) Control Register +#define AT91C_US4_IF (AT91_CAST(AT91_REG *) 0xFFFD404C) // (US4) IRDA_FILTER Register +#define AT91C_US4_IDR (AT91_CAST(AT91_REG *) 0xFFFD400C) // (US4) Interrupt Disable Register +#define AT91C_US4_CSR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (US4) Channel Status Register +// ========== Register definition for PDC_SSC0 peripheral ========== +#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register +#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register +#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register +#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register +#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register +#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register +#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register +#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register +#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register +#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register +// ========== Register definition for SSC0 peripheral ========== +#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register +#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register +#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register +#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register +#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register +#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register +#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register +#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister +#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register +#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register +#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register +#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register +#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register +#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_ADC) Receive Counter Register +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFE0014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFE003C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (ADC) ADC Control Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFE002C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFE0038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (ADC) ADC Status Register +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFE0024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFE004C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFE0030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFE0044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFE0040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFE0010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFE0048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFE0020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFE0034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFE0028) // (ADC) ADC Interrupt Disable Register +// ========== Register definition for EMACB peripheral ========== +#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFC40C0) // (EMACB) USER Input/Output Register +#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 0xFFFC4074) // (EMACB) Receive Symbol Errors Register +#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 0xFFFC4044) // (EMACB) Single Collision Frame Register +#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 0xFFFC4084) // (EMACB) SQE Test Error Register +#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 0xFFFC4070) // (EMACB) Receive Overrun Errors Register +#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer +#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (EMACB) Interrupt Mask Register +#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 0xFFFC4028) // (EMACB) Interrupt Enable Register +#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (EMACB) Revision Register +#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 0xFFFC4078) // (EMACB) Excessive Length Errors Register +#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 0xFFFC4094) // (EMACB) Hash Address Top[63:32] +#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 0xFFFC406C) // (EMACB) Receive Ressource Error Register +#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 0xFFFC404C) // (EMACB) Frames Received OK Register +#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register +#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (EMACB) Interrupt Status Register +#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (EMACB) Transmit Status Register +#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register +#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 0xFFFC4080) // (EMACB) Undersize Frames Register +#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 0xFFFC40C4) // (EMACB) Wake On LAN Register +#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 0xFFFC408C) // (EMACB) Transmitted Pause Frames Register +#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 0xFFFC4038) // (EMACB) Pause Time Register +#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 0xFFFC4064) // (EMACB) Transmit Underrun Error Register +#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 0xFFFC4034) // (EMACB) PHY Maintenance Register +#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 0xFFFC407C) // (EMACB) Receive Jabbers Register +#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 0xFFFC4068) // (EMACB) Carrier Sense Error Register +#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 0xFFFC4090) // (EMACB) Hash Address Bottom[31:0] +#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 0xFFFC4054) // (EMACB) Alignment Error Register +#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (EMACB) Network Control Register +#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 0xFFFC4040) // (EMACB) Frames Transmitted OK Register +#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFC4060) // (EMACB) Excessive Collision Register +#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 0xFFFC4058) // (EMACB) Deferred Transmission Frame Register +#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFC4050) // (EMACB) Frame Check Sequence Error Register +#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 0xFFFC40B8) // (EMACB) Type ID Checking Register +#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 0xFFFC403C) // (EMACB) Pause Frames received Register +#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 0xFFFC402C) // (EMACB) Interrupt Disable Register +#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (EMACB) Network Status Register +#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 0xFFFC4048) // (EMACB) Multiple Collision Frame Register +#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer +#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (EMACB) Receive Status Register +#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (EMACB) Network Configuration Register +#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFC405C) // (EMACB) Late Collision Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register +// ========== Register definition for UHP peripheral ========== +#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register +#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register +#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register +#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register +#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start +#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register +#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor +#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list +#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision +#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list +#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B +#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list +#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame +#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area +#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold +#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register +#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register +#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number +#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs +#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller +#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor +#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A +// ========== Register definition for HECC peripheral ========== +// ========== Register definition for HISI peripheral ========== +#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC0020) // (HISI) Preview Size Register +#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC0000) // (HISI) Control Register 1 +#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC003C) // (HISI) Color Space Conversion Register +#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC002C) // (HISI) Codec Dma Address Register +#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (HISI) Interrupt Disable Register +#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC0040) // (HISI) Color Space Conversion Register +#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC0034) // (HISI) Color Space Conversion Register +#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC0028) // (HISI) Preview Frame Buffer Address Register +#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC0004) // (HISI) Control Register 2 +#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC0030) // (HISI) Color Space Conversion Register +#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC0024) // (HISI) Preview Decimation Factor Register +#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (HISI) Interrupt Mask Register +#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC000C) // (HISI) Interrupt Enable Register +#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC0038) // (HISI) Color Space Conversion Register +#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC0008) // (HISI) Status Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM9XE128 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave +#define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0 +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave +#define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2 +#define AT91C_PA10_ETX2_0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3 +#define AT91C_PA11_ETX3_0 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger +#define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TWD0 (AT91C_PIO_PA23) // TWI Two-wire Serial Data 0 +#define AT91C_PA23_ETX2_1 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_TWCK0 (AT91C_PIO_PA24) // TWI Two-wire Serial Clock 0 +#define AT91C_PA24_ETX3_1 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input +#define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock +#define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock +#define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock +#define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send +#define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send +#define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave +#define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave +#define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data +#define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data +#define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_TWD1 (AT91C_PIO_PB12) // TWI Two-wire Serial Data 1 +#define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10 +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_TWCK1 (AT91C_PIO_PB13) // TWI Two-wire Serial Clock 1 +#define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock +#define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync +#define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data +#define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data +#define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock +#define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock +#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync +#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready +#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect +#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3 +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready +#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4 +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator +#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5 +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send +#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6 +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send +#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send +#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send +#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0 +#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro +#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31 +#define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1 +#define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data +#define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data +#define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data +#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 +#define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0 +#define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock +#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 +#define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1 +#define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 +#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25] +#define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send +#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 +#define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2 +#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 +#define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0 +#define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7 +#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 +#define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input +#define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6 +#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 +#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3 +#define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2 +#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 +#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal +#define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1 +#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 +#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16] +#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 +#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17] +#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 +#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18] +#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 +#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19] +#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 +#define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2 +#define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 +#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20] +#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 +#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21] +#define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 +#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22] +#define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input +#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 +#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23] +#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24 +#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24] +#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25 +#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25] +#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26 +#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26] +#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27 +#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27] +#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28 +#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28] +#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29 +#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29] +#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 +#define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3 +#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30 +#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30] +#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31 +#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31] +#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 +#define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23] +#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 +#define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24] +#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 +#define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1 +#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 +#define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2 +#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 +#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4 +#define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send +#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 +#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5 +#define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE128 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Controller +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C +#define AT91C_ID_ADC ( 5) // ADC +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_US2 ( 8) // USART 2 +#define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0 +#define AT91C_ID_UDP (10) // USB Device Port +#define AT91C_ID_TWI0 (11) // Two-Wire Interface 0 +#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1 +#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0 +#define AT91C_ID_TC0 (17) // Timer Counter 0 +#define AT91C_ID_TC1 (18) // Timer Counter 1 +#define AT91C_ID_TC2 (19) // Timer Counter 2 +#define AT91C_ID_UHP (20) // USB Host Port +#define AT91C_ID_EMAC (21) // Ethernet Mac +#define AT91C_ID_HISI (22) // Image Sensor Interface +#define AT91C_ID_US3 (23) // USART 3 +#define AT91C_ID_US4 (24) // USART 4 +#define AT91C_ID_TWI1 (25) // Two-Wire Interface 1 +#define AT91C_ID_TC3 (26) // Timer Counter 3 +#define AT91C_ID_TC4 (27) // Timer Counter 4 +#define AT91C_ID_TC5 (28) // Timer Counter 5 +#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2) +#define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM9XE128 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFFD00) // (SYS) Base Address +#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFEA00) // (EBI) Base Address +#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFE800) // (HECC) Base Address +#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address +#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address +#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address +#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFEF10) // (CCFG) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address +#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFA00) // (EFC) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFDC000) // (TC3) Base Address +#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFDC040) // (TC4) Base Address +#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFDC080) // (TC5) Base Address +#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address +#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFDC000) // (TCB1) Base Address +#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address +#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address +#define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_TWI0) Base Address +#define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI0) Base Address +#define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_TWI1) Base Address +#define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0xFFFD8000) // (TWI1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address +#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address +#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address +#define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_US3) Base Address +#define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0xFFFD0000) // (US3) Base Address +#define AT91C_BASE_PDC_US4 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_US4) Base Address +#define AT91C_BASE_US4 (AT91_CAST(AT91PS_USART) 0xFFFD4000) // (US4) Base Address +#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address +#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFE0000) // (ADC) Base Address +#define AT91C_BASE_EMACB (AT91_CAST(AT91PS_EMAC) 0xFFFC4000) // (EMACB) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address +#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address +#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC0000) // (HISI) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE128 +// ***************************************************************************** +// IROM +#define AT91C_IROM (0x00100000) // Internal ROM base address +#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes) +// ISRAM +#define AT91C_ISRAM (0x00300000) // Maximum IRAM Area : 16Kbyte base address +#define AT91C_ISRAM_SIZE (0x00004000) // Maximum IRAM Area : 16Kbyte size in byte (16 Kbytes) +// ISRAM_MIN +#define AT91C_ISRAM_MIN (0x00300000) // Minimun IRAM Area : 16Kbyte base address +#define AT91C_ISRAM_MIN_SIZE (0x00004000) // Minimun IRAM Area : 16Kbyte size in byte (16 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00200000) // Maximum IFLASH Area : 128Kbyte base address +#define AT91C_IFLASH_SIZE (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (512) // Maximum IFLASH Area : 128Kbyte Page Size: 512 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (256) // Maximum IFLASH Area : 128Kbyte Number of Pages: 256 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 8 bytes +// EBI_CS0 +#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address +#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes) +// EBI_CS1 +#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address +#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes) +// EBI_SDRAM +#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address +#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes) +// EBI_SDRAM_16BIT +#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address +#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes) +// EBI_SDRAM_32BIT +#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address +#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes) +// EBI_CS2 +#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address +#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes) +// EBI_CS3 +#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address +#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes) +// EBI_SM +#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address +#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes) +// EBI_CS4 +#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address +#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes) +// EBI_CF0 +#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address +#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes) +// EBI_CS5 +#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address +#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes) +// EBI_CF1 +#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address +#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes) +// EBI_CS6 +#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address +#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes) +// EBI_CS7 +#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address +#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes) + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/flash.icf b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/flash.icf new file mode 100644 index 0000000..c1755de --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/flash.icf @@ -0,0 +1,48 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x21FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x100; +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in ROM_region { readonly }; +place in VEC_region { section .vectors }; +place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sdram.icf b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sdram.icf new file mode 100644 index 0000000..f79413b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sdram.icf @@ -0,0 +1,46 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x100; +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_SDRAM_start__; +export symbol __ICFEDIT_region_SDRAM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__]; +define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in VEC_region { section .vectors }; +place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sram.icf b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sram.icf new file mode 100644 index 0000000..45d75b2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sram.icf @@ -0,0 +1,36 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { section .noinit }; + +place in VEC_region { section .vectors }; +place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/AT91SAM9XE256.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/AT91SAM9XE256.h new file mode 100644 index 0000000..861c849 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/AT91SAM9XE256.h @@ -0,0 +1,4042 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the disclaimer below in the documentation and/or +// other materials provided with the distribution. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM9XE256.h +// Object : AT91SAM9XE256 definitions +// Generated : AT91 SW Application Group 02/13/2008 (18:26:11) +// +// CVS Reference : /AT91SAM9XE256.pl/1.3/Wed Jan 30 13:59:12 2008// +// CVS Reference : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008// +// CVS Reference : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007// +// CVS Reference : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007// +// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004// +// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004// +// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004// +// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005// +// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:53:02 2006// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006// +// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005// +// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005// +// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005// +// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM9XE256_H +#define AT91SAM9XE256_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG Reserved0[2560]; // + AT91_REG ECC_CR; // ECC reset register + AT91_REG ECC_MR; // ECC Page size register + AT91_REG ECC_SR; // ECC Status register + AT91_REG ECC_PR; // ECC Parity register + AT91_REG ECC_NPR; // ECC Parity N register + AT91_REG Reserved1[58]; // + AT91_REG ECC_VR; // ECC Version register + AT91_REG Reserved2[64]; // + AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register + AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register + AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register + AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register + AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register + AT91_REG Reserved3[118]; // + AT91_REG SMC_SETUP0; // Setup Register for CS 0 + AT91_REG SMC_PULSE0; // Pulse Register for CS 0 + AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 + AT91_REG SMC_CTRL0; // Control Register for CS 0 + AT91_REG SMC_SETUP1; // Setup Register for CS 1 + AT91_REG SMC_PULSE1; // Pulse Register for CS 1 + AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 + AT91_REG SMC_CTRL1; // Control Register for CS 1 + AT91_REG SMC_SETUP2; // Setup Register for CS 2 + AT91_REG SMC_PULSE2; // Pulse Register for CS 2 + AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 + AT91_REG SMC_CTRL2; // Control Register for CS 2 + AT91_REG SMC_SETUP3; // Setup Register for CS 3 + AT91_REG SMC_PULSE3; // Pulse Register for CS 3 + AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 + AT91_REG SMC_CTRL3; // Control Register for CS 3 + AT91_REG SMC_SETUP4; // Setup Register for CS 4 + AT91_REG SMC_PULSE4; // Pulse Register for CS 4 + AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 + AT91_REG SMC_CTRL4; // Control Register for CS 4 + AT91_REG SMC_SETUP5; // Setup Register for CS 5 + AT91_REG SMC_PULSE5; // Pulse Register for CS 5 + AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 + AT91_REG SMC_CTRL5; // Control Register for CS 5 + AT91_REG SMC_SETUP6; // Setup Register for CS 6 + AT91_REG SMC_PULSE6; // Pulse Register for CS 6 + AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 + AT91_REG SMC_CTRL6; // Control Register for CS 6 + AT91_REG SMC_SETUP7; // Setup Register for CS 7 + AT91_REG SMC_PULSE7; // Pulse Register for CS 7 + AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 + AT91_REG SMC_CTRL7; // Control Register for CS 7 + AT91_REG Reserved4[96]; // + AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) + AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) + AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) + AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi) + AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) + AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) + AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) + AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) + AT91_REG Reserved5[8]; // + AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) + AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) + AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) + AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi) + AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) + AT91_REG Reserved6[11]; // + AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) + AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) + AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) + AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) + AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) + AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) + AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs + AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs + AT91_REG MATRIX_PRAS4; // PRAS4 : ebi + AT91_REG MATRIX_PRBS4; // PRBS4 : ebi + AT91_REG Reserved7[22]; // + AT91_REG MATRIX_MRCR; // Master Remp Control Register + AT91_REG Reserved8[6]; // + AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register + AT91_REG Reserved9[3]; // + AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register + AT91_REG Reserved10[51]; // + AT91_REG CCFG_MATRIXVERSION; // Version Register + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved11[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved12[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved13[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved14[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved15[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved16[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved18[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved19[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved20[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved21[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved22[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved23[213]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved24[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved25[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved26[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved27[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved28[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved29[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved30[85]; // + AT91_REG PIOC_PER; // PIO Enable Register + AT91_REG PIOC_PDR; // PIO Disable Register + AT91_REG PIOC_PSR; // PIO Status Register + AT91_REG Reserved31[1]; // + AT91_REG PIOC_OER; // Output Enable Register + AT91_REG PIOC_ODR; // Output Disable Registerr + AT91_REG PIOC_OSR; // Output Status Register + AT91_REG Reserved32[1]; // + AT91_REG PIOC_IFER; // Input Filter Enable Register + AT91_REG PIOC_IFDR; // Input Filter Disable Register + AT91_REG PIOC_IFSR; // Input Filter Status Register + AT91_REG Reserved33[1]; // + AT91_REG PIOC_SODR; // Set Output Data Register + AT91_REG PIOC_CODR; // Clear Output Data Register + AT91_REG PIOC_ODSR; // Output Data Status Register + AT91_REG PIOC_PDSR; // Pin Data Status Register + AT91_REG PIOC_IER; // Interrupt Enable Register + AT91_REG PIOC_IDR; // Interrupt Disable Register + AT91_REG PIOC_IMR; // Interrupt Mask Register + AT91_REG PIOC_ISR; // Interrupt Status Register + AT91_REG PIOC_MDER; // Multi-driver Enable Register + AT91_REG PIOC_MDDR; // Multi-driver Disable Register + AT91_REG PIOC_MDSR; // Multi-driver Status Register + AT91_REG Reserved34[1]; // + AT91_REG PIOC_PPUDR; // Pull-up Disable Register + AT91_REG PIOC_PPUER; // Pull-up Enable Register + AT91_REG PIOC_PPUSR; // Pull-up Status Register + AT91_REG Reserved35[1]; // + AT91_REG PIOC_ASR; // Select A Register + AT91_REG PIOC_BSR; // Select B Register + AT91_REG PIOC_ABSR; // AB Select Status Register + AT91_REG Reserved36[9]; // + AT91_REG PIOC_OWER; // Output Write Enable Register + AT91_REG PIOC_OWDR; // Output Write Disable Register + AT91_REG PIOC_OWSR; // Output Write Status Register + AT91_REG Reserved37[85]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved38[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved39[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG PMC_PLLAR; // PLL A Register + AT91_REG PMC_PLLBR; // PLL B Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved40[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved41[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved42[1]; // + AT91_REG SHDWC_SHCR; // Shut Down Control Register + AT91_REG SHDWC_SHMR; // Shut Down Mode Register + AT91_REG SHDWC_SHSR; // Shut Down Status Register + AT91_REG Reserved43[1]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved44[1]; // + AT91_REG SYS_GPBR[4]; // General Purpose Register +} AT91S_SYS, *AT91PS_SYS; +#else +#define SYS_GPBR (AT91_CAST(AT91_REG *) 0x00003D50) // (SYS_GPBR) General Purpose Register + +#endif +// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- +#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR External Bus Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EBI { + AT91_REG EBI_DUMMY; // Dummy register - Do not use +} AT91S_EBI, *AT91PS_EBI; +#else +#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Error Correction Code controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ECC { + AT91_REG ECC_CR; // ECC reset register + AT91_REG ECC_MR; // ECC Page size register + AT91_REG ECC_SR; // ECC Status register + AT91_REG ECC_PR; // ECC Parity register + AT91_REG ECC_NPR; // ECC Parity N register + AT91_REG Reserved0[58]; // + AT91_REG ECC_VR; // ECC Version register +} AT91S_ECC, *AT91PS_ECC; +#else +#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register +#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register +#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register +#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register +#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register +#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register + +#endif +// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- +#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity +// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- +#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size +// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- +#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error +#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error +#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR +// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- +#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error +#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit +// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- +#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N +// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- +#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR SDRAM Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SDRAMC { + AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register + AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register + AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register + AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register + AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register +} AT91S_SDRAMC, *AT91PS_SDRAMC; +#else +#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register +#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register +#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register +#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register +#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register +#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register +#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register +#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register +#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register +#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register + +#endif +// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- +#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode +#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode +#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access +#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access +#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access +#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh +#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register +#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode +// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- +#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter +// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- +#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits +#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits +#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits +#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits +#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits +#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits +#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits +#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits +#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits +#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks +#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks +#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks +#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency +#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles +#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles +#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width +#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus +#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus +#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles +#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles +#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles +#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles +#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles +#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles +#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15 +// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- +#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit +#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle +#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle +// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- +#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations +#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features +#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH +#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN +#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN +#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM) +#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM) +#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM) +#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled +#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately +#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer +#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer +// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status +// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- +// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- +#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type +#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode +#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Static Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SMC { + AT91_REG SMC_SETUP0; // Setup Register for CS 0 + AT91_REG SMC_PULSE0; // Pulse Register for CS 0 + AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 + AT91_REG SMC_CTRL0; // Control Register for CS 0 + AT91_REG SMC_SETUP1; // Setup Register for CS 1 + AT91_REG SMC_PULSE1; // Pulse Register for CS 1 + AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 + AT91_REG SMC_CTRL1; // Control Register for CS 1 + AT91_REG SMC_SETUP2; // Setup Register for CS 2 + AT91_REG SMC_PULSE2; // Pulse Register for CS 2 + AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 + AT91_REG SMC_CTRL2; // Control Register for CS 2 + AT91_REG SMC_SETUP3; // Setup Register for CS 3 + AT91_REG SMC_PULSE3; // Pulse Register for CS 3 + AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 + AT91_REG SMC_CTRL3; // Control Register for CS 3 + AT91_REG SMC_SETUP4; // Setup Register for CS 4 + AT91_REG SMC_PULSE4; // Pulse Register for CS 4 + AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 + AT91_REG SMC_CTRL4; // Control Register for CS 4 + AT91_REG SMC_SETUP5; // Setup Register for CS 5 + AT91_REG SMC_PULSE5; // Pulse Register for CS 5 + AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 + AT91_REG SMC_CTRL5; // Control Register for CS 5 + AT91_REG SMC_SETUP6; // Setup Register for CS 6 + AT91_REG SMC_PULSE6; // Pulse Register for CS 6 + AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 + AT91_REG SMC_CTRL6; // Control Register for CS 6 + AT91_REG SMC_SETUP7; // Setup Register for CS 7 + AT91_REG SMC_PULSE7; // Pulse Register for CS 7 + AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 + AT91_REG SMC_CTRL7; // Control Register for CS 7 +} AT91S_SMC, *AT91PS_SMC; +#else +#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0 +#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0 +#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0 +#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0 +#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1 +#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1 +#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1 +#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1 +#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2 +#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2 +#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2 +#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2 +#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3 +#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3 +#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3 +#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3 +#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4 +#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4 +#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4 +#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4 +#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5 +#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5 +#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5 +#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5 +#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6 +#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6 +#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6 +#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6 +#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7 +#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7 +#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7 +#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7 + +#endif +// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- +#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length +#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access +#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length +#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access +// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- +#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length +#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access +#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length +#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access +// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- +#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length +#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length +// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- +#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode +#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode +#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode +#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled. +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode. +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode. +#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type +#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. +#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. +#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width +#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits. +#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits. +#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits. +#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time. +#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled. +#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled. +#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size +#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes. +#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes. +#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes. +#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes. +// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR AHB Matrix Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MATRIX { + AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) + AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) + AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) + AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi) + AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) + AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) + AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) + AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) + AT91_REG Reserved0[8]; // + AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) + AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) + AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) + AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi) + AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) + AT91_REG Reserved1[11]; // + AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) + AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) + AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) + AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) + AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) + AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) + AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs + AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs + AT91_REG MATRIX_PRAS4; // PRAS4 : ebi + AT91_REG MATRIX_PRBS4; // PRBS4 : ebi + AT91_REG Reserved2[22]; // + AT91_REG MATRIX_MRCR; // Master Remp Control Register + AT91_REG Reserved3[6]; // + AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register + AT91_REG Reserved4[3]; // + AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register + AT91_REG Reserved5[51]; // + AT91_REG MATRIX_VERSION; // Version Register +} AT91S_MATRIX, *AT91PS_MATRIX; +#else +#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k) +#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom) +#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs) +#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi) +#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge) +#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox) +#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k) +#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog) +#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k) +#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom) +#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs) +#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi) +#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge) +#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0) +#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0) +#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1) +#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1) +#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2) +#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2) +#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs +#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs +#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi +#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi +#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register +#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register +#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register +#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register + +#endif +// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- +#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst +#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type +#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. +#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. +#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. +#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master +// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master +// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master +// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- +#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority +#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority +#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority +#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority +#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority +#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority +#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority +#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority +// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- +#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority +// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- +// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- +// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- +// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- +// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- +// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- +// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- +// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- +// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- +#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master +#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master +// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- +#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment +#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment +#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. +#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment +#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. +#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. +#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment +#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC +#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. +#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration +// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- +#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB +#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled +#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled +#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine +#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled +#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled +#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset +#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled +#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled +#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Chip Configuration Registers +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CCFG { + AT91_REG Reserved0[3]; // + AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register + AT91_REG Reserved1[55]; // + AT91_REG CCFG_MATRIXVERSION; // Version Register +} AT91S_CCFG, *AT91PS_CCFG; +#else +#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register +#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register + +#endif +// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- +#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment +#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment +#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. +#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment +#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. +#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. +#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment +#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC +#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. +#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration +#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // EFC Flash Mode Register + AT91_REG EFC_FCR; // EFC Flash Command Register + AT91_REG EFC_FSR; // EFC Flash Status Register + AT91_REG EFC_FRR; // EFC Flash Result Register + AT91_REG EFC_FVR; // EFC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; +#else +#define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register +#define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register +#define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register +#define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register +#define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000010) // (EFC_FVR) EFC Flash Version Register + +#endif +// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- +#define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable +#define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State. +#define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State +#define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State +#define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States +#define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States +// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- +#define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command +#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor +#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page +#define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock +#define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page +#define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock +#define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All +#define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane +#define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages +#define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit +#define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit +#define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit +#define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit +#define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit +#define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit +#define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument +#define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key +// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- +#define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status +#define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status +#define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status +// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- +#define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG CKGR_PLLAR; // PLL A Register + AT91_REG CKGR_PLLBR; // PLL B Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register +#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- +#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected +#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0 +#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed +#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter +#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range +#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier +#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) +// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected +#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0 +#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed +#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter +#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range +#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG PMC_PLLAR; // PLL A Register + AT91_REG PMC_PLLBR; // PLL B Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved2[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock +#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- +// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected +#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division +#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same +#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock +#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Shut Down Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SHDWC { + AT91_REG SHDWC_SHCR; // Shut Down Control Register + AT91_REG SHDWC_SHMR; // Shut Down Mode Register + AT91_REG SHDWC_SHSR; // Shut Down Status Register +} AT91S_SHDWC, *AT91PS_SHDWC; +#else +#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register +#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register +#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register + +#endif +// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- +#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset +#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password +// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- +#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection +#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input. +#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level. +#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level. +#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change. +#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0 +#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection +#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input. +#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level. +#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level. +#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change. +#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1 +#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable +#define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable +// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- +#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status +#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status +#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status +#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up +#define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Multimedia Card Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MCI { + AT91_REG MCI_CR; // MCI Control Register + AT91_REG MCI_MR; // MCI Mode Register + AT91_REG MCI_DTOR; // MCI Data Timeout Register + AT91_REG MCI_SDCR; // MCI SD Card Register + AT91_REG MCI_ARGR; // MCI Argument Register + AT91_REG MCI_CMDR; // MCI Command Register + AT91_REG MCI_BLKR; // MCI Block Register + AT91_REG Reserved0[1]; // + AT91_REG MCI_RSPR[4]; // MCI Response Register + AT91_REG MCI_RDR; // MCI Receive Data Register + AT91_REG MCI_TDR; // MCI Transmit Data Register + AT91_REG Reserved1[2]; // + AT91_REG MCI_SR; // MCI Status Register + AT91_REG MCI_IER; // MCI Interrupt Enable Register + AT91_REG MCI_IDR; // MCI Interrupt Disable Register + AT91_REG MCI_IMR; // MCI Interrupt Mask Register + AT91_REG Reserved2[43]; // + AT91_REG MCI_VR; // MCI Version Register + AT91_REG MCI_RPR; // Receive Pointer Register + AT91_REG MCI_RCR; // Receive Counter Register + AT91_REG MCI_TPR; // Transmit Pointer Register + AT91_REG MCI_TCR; // Transmit Counter Register + AT91_REG MCI_RNPR; // Receive Next Pointer Register + AT91_REG MCI_RNCR; // Receive Next Counter Register + AT91_REG MCI_TNPR; // Transmit Next Pointer Register + AT91_REG MCI_TNCR; // Transmit Next Counter Register + AT91_REG MCI_PTCR; // PDC Transfer Control Register + AT91_REG MCI_PTSR; // PDC Transfer Status Register +} AT91S_MCI, *AT91PS_MCI; +#else +#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register +#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register +#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register +#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register +#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register +#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register +#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register +#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register +#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register +#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register +#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register +#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register +#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register +#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register +#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register + +#endif +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable +#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable +#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable +#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable +#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider +#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider +#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable +#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable +#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer +#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value +#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode +#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number +#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier +#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1 +#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16 +#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128 +#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256 +#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024 +#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096 +#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536 +#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576 +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector +#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number +#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type +#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response +#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response +#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response +#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD +#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD +#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD +#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD +#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command +#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response +#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command +#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond +#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD +#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer +#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer +#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer +#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction +#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type +#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type +#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type +#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type +#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type +#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type +#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command +#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command +#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command +#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command +// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- +#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag +#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag +#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag +#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag +#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag +#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag +#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag +#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag +#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A +#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B +#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C +#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D +#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag +#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag +#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag +#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag +#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag +#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag +#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag +#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag +#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag +#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag +#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved1[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode) +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode) +#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode) +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode) +#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode) +#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode) +#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode) +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Host Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UHP { + AT91_REG UHP_HcRevision; // Revision + AT91_REG UHP_HcControl; // Operating modes for the Host Controller + AT91_REG UHP_HcCommandStatus; // Command & status Register + AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register + AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register + AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register + AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area + AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor + AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list + AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register + AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list + AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list + AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor + AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs + AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame + AT91_REG UHP_HcFmNumber; // Frame number + AT91_REG UHP_HcPeriodicStart; // Periodic Start + AT91_REG UHP_HcLSThreshold; // LS Threshold + AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A + AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B + AT91_REG UHP_HcRhStatus; // Root Hub Status register + AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register +} AT91S_UHP, *AT91PS_UHP; +#else +#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision +#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller +#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register +#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register +#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register +#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register +#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area +#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor +#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list +#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register +#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list +#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list +#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor +#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs +#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame +#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number +#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start +#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold +#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A +#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B +#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register +#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Image Sensor Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ISI { + AT91_REG ISI_CR1; // Control Register 1 + AT91_REG ISI_CR2; // Control Register 2 + AT91_REG ISI_SR; // Status Register + AT91_REG ISI_IER; // Interrupt Enable Register + AT91_REG ISI_IDR; // Interrupt Disable Register + AT91_REG ISI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[2]; // + AT91_REG ISI_PSIZE; // Preview Size Register + AT91_REG ISI_PDECF; // Preview Decimation Factor Register + AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register + AT91_REG ISI_CDBA; // Codec Dma Address Register + AT91_REG ISI_Y2RSET0; // Color Space Conversion Register + AT91_REG ISI_Y2RSET1; // Color Space Conversion Register + AT91_REG ISI_R2YSET0; // Color Space Conversion Register + AT91_REG ISI_R2YSET1; // Color Space Conversion Register + AT91_REG ISI_R2YSET2; // Color Space Conversion Register +} AT91S_ISI, *AT91PS_ISI; +#else +#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1 +#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2 +#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register +#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register +#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register +#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register +#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register +#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register +#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register +#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register +#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register +#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register +#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register +#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register +#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register + +#endif +// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- +#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset +#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable. +#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity +#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity +#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation +#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction +#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed +#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask +#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed +#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed +#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed +#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path +#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay +#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay +// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- +#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047] +#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode +#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode +#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits +#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits +#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits +#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode +#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap +#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data +#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047] +#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1) +#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1) +#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i) +#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i) +#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration +#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B +#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R +#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB) +#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB) +// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- +#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame +#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable +#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset +#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error +#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow +#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow +#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty +#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty +#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun +// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- +// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- +// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- +// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- +#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path +#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path +// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- +#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0 +#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1 +#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2 +#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3 +// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- +#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4 +#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset +#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset +#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset +// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- +#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0 +#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1 +#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2 +#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset +// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- +#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3 +#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4 +#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5 +#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset +// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- +#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6 +#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7 +#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8 +#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM9XE256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFFFF) // (SYS) General Purpose Register +// ========== Register definition for EBI peripheral ========== +#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (EBI) Dummy register - Do not use +// ========== Register definition for HECC peripheral ========== +#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFE8FC) // (HECC) ECC Version register +#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (HECC) ECC Parity N register +#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (HECC) ECC Status register +#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (HECC) ECC Parity register +#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (HECC) ECC Page size register +#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (HECC) ECC reset register +// ========== Register definition for SDRAMC peripheral ========== +#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register +#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register +#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register +#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register +#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register +#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register +#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register +#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register +// ========== Register definition for SMC peripheral ========== +#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1 +#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7 +#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6 +#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4 +#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3 +#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5 +#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2 +#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2 +#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0 +#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5 +#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1 +#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0 +#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7 +#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4 +#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3 +#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7 +#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7 +#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1 +#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0 +#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5 +#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1 +#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6 +#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0 +#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4 +#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5 +#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2 +#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3 +#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6 +#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6 +#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4 +#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2 +#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3 +// ========== Register definition for MATRIX peripheral ========== +#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k) +#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (MATRIX) Master Configuration Register 7 (teak_prog) +#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom) +#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge) +#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (MATRIX) Version Register +#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs) +#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA4) // (MATRIX) PRBS4 : ebi +#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX) PRBS0 (ram0) +#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi) +#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (MATRIX) Master Configuration Register 6 (ram16k) +#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (MATRIX) Slave 3 (ebi) Special Function Register +#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k) +#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEE9C) // (MATRIX) PRBS3 : usb_dev_hs +#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEE98) // (MATRIX) PRAS3 : usb_dev_hs +#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX) PRAS0 (ram0) +#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi) +#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEE88) // (MATRIX) PRAS1 (ram1) +#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEE90) // (MATRIX) PRAS2 (ram2) +#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs) +#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox) +#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom) +#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA0) // (MATRIX) PRAS4 : ebi +#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register +#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEE94) // (MATRIX) PRBS2 (ram2) +#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge) +#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0xFFFFEF2C) // (MATRIX) Slave 7 (teak_prog) Special Function Register +#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEE8C) // (MATRIX) PRBS1 (ram1) +// ========== Register definition for CCFG peripheral ========== +#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (CCFG) Version Register +#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for PIOC peripheral ========== +#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register +#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register +#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register +#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register +#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register +#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register +#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr +#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register +#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register +#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register +#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register +#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register +#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register +#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register +#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register +#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register +#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register +#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register +#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register +#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register +#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register +#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register +#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register +#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register +#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register +#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register +#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register +#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register +#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register +// ========== Register definition for EFC peripheral ========== +#define AT91C_EFC_FVR (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (EFC) EFC Flash Version Register +#define AT91C_EFC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (EFC) EFC Flash Command Register +#define AT91C_EFC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (EFC) EFC Flash Mode Register +#define AT91C_EFC_FRR (AT91_CAST(AT91_REG *) 0xFFFFFA0C) // (EFC) EFC Flash Result Register +#define AT91C_EFC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (EFC) EFC Flash Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for SHDWC peripheral ========== +#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register +#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register +#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TC3 peripheral ========== +#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (TC3) Interrupt Enable Register +#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFDC018) // (TC3) Register B +#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (TC3) Register C +#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (TC3) Channel Control Register +#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (TC3) Status Register +#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFDC010) // (TC3) Counter Value +#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFDC014) // (TC3) Register A +#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (TC3) Interrupt Disable Register +#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (TC3) Interrupt Mask Register +// ========== Register definition for TC4 peripheral ========== +#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (TC4) Register C +#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFDC060) // (TC4) Status Register +#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFDC058) // (TC4) Register B +#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFDC064) // (TC4) Interrupt Enable Register +#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFDC050) // (TC4) Counter Value +#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFDC054) // (TC4) Register A +#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFDC068) // (TC4) Interrupt Disable Register +#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (TC4) Interrupt Mask Register +#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFDC040) // (TC4) Channel Control Register +// ========== Register definition for TC5 peripheral ========== +#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFDC098) // (TC5) Register B +#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFDC094) // (TC5) Register A +#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFDC090) // (TC5) Counter Value +#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFDC080) // (TC5) Channel Control Register +#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (TC5) Status Register +#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (TC5) Interrupt Enable Register +#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (TC5) Interrupt Disable Register +#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (TC5) Register C +#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (TC5) Interrupt Mask Register +#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode) +// ========== Register definition for TCB0 peripheral ========== +#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register +#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register +// ========== Register definition for TCB1 peripheral ========== +#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (TCB1) TC Block Control Register +#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (TCB1) TC Block Mode Register +// ========== Register definition for PDC_MCI peripheral ========== +#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register +#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register +#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register +#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register +#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register +#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register +#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register +#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register +#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register +#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register +// ========== Register definition for MCI peripheral ========== +#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register +#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register +#define AT91C_MCI_VR (AT91_CAST(AT91_REG *) 0xFFFA80FC) // (MCI) MCI Version Register +#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register +#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register +#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register +#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register +#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register +#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register +#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register +#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register +#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register +#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD Card Register +#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register +#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register +// ========== Register definition for PDC_TWI0 peripheral ========== +#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register +#define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_TWI0) Receive Pointer Register +#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register +#define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_TWI0) Receive Counter Register +#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register +#define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register +#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register +#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register +#define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register +#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register +// ========== Register definition for TWI0 peripheral ========== +#define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI0) Transmit Holding Register +#define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI0) Interrupt Disable Register +#define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI0) Slave Mode Register +#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI0) Clock Waveform Generator Register +#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI0) Internal Address Register +#define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI0) Receive Holding Register +#define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI0) Interrupt Enable Register +#define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI0) Master Mode Register +#define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI0) Status Register +#define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI0) Interrupt Mask Register +#define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI0) Control Register +// ========== Register definition for PDC_TWI1 peripheral ========== +#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register +#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register +#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register +#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register +#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register +#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register +#define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_TWI1) Receive Pointer Register +#define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_TWI1) Transmit Counter Register +#define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register +#define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_TWI1) Receive Counter Register +// ========== Register definition for TWI1 peripheral ========== +#define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0xFFFD8030) // (TWI1) Receive Holding Register +#define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (TWI1) Interrupt Enable Register +#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0xFFFD8010) // (TWI1) Clock Waveform Generator Register +#define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (TWI1) Master Mode Register +#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0xFFFD800C) // (TWI1) Internal Address Register +#define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0xFFFD8034) // (TWI1) Transmit Holding Register +#define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (TWI1) Interrupt Mask Register +#define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (TWI1) Status Register +#define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (TWI1) Interrupt Disable Register +#define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (TWI1) Control Register +#define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0xFFFD8008) // (TWI1) Slave Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register +// ========== Register definition for PDC_US2 peripheral ========== +#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register +#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register +#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register +#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register +#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register +#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register +#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register +#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register +#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register +#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register +// ========== Register definition for US2 peripheral ========== +#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register +#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register +#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register +#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register +#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register +#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register +#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register +#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register +#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register +#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register +#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register +#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register +#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register +#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register +// ========== Register definition for PDC_US3 peripheral ========== +#define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_US3) Receive Next Pointer Register +#define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_US3) Receive Next Counter Register +#define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_US3) PDC Transfer Status Register +#define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_US3) PDC Transfer Control Register +#define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_US3) Transmit Counter Register +#define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register +#define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_US3) Receive Counter Register +#define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_US3) Transmit Pointer Register +#define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_US3) Transmit Next Counter Register +#define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_US3) Receive Pointer Register +// ========== Register definition for US3 peripheral ========== +#define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (US3) Nb Errors Register +#define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (US3) Receiver Time-out Register +#define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (US3) Interrupt Disable Register +#define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (US3) Mode Register +#define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0xFFFD0040) // (US3) FI_DI_Ratio Register +#define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (US3) Baud Rate Generator Register +#define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (US3) Transmitter Holding Register +#define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (US3) Control Register +#define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0xFFFD004C) // (US3) IRDA_FILTER Register +#define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0xFFFD0008) // (US3) Interrupt Enable Register +#define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (US3) Transmitter Time-guard Register +#define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (US3) Receiver Holding Register +#define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (US3) Interrupt Mask Register +#define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (US3) Channel Status Register +// ========== Register definition for PDC_US4 peripheral ========== +#define AT91C_US4_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_US4) Transmit Next Counter Register +#define AT91C_US4_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_US4) Receive Pointer Register +#define AT91C_US4_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_US4) Receive Next Counter Register +#define AT91C_US4_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_US4) Transmit Pointer Register +#define AT91C_US4_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_US4) PDC Transfer Control Register +#define AT91C_US4_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_US4) Transmit Counter Register +#define AT91C_US4_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_US4) Receive Counter Register +#define AT91C_US4_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_US4) Receive Next Pointer Register +#define AT91C_US4_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register +#define AT91C_US4_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_US4) PDC Transfer Status Register +// ========== Register definition for US4 peripheral ========== +#define AT91C_US4_BRGR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (US4) Baud Rate Generator Register +#define AT91C_US4_THR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (US4) Transmitter Holding Register +#define AT91C_US4_RTOR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (US4) Receiver Time-out Register +#define AT91C_US4_IMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (US4) Interrupt Mask Register +#define AT91C_US4_NER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (US4) Nb Errors Register +#define AT91C_US4_TTGR (AT91_CAST(AT91_REG *) 0xFFFD4028) // (US4) Transmitter Time-guard Register +#define AT91C_US4_FIDI (AT91_CAST(AT91_REG *) 0xFFFD4040) // (US4) FI_DI_Ratio Register +#define AT91C_US4_MR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (US4) Mode Register +#define AT91C_US4_IER (AT91_CAST(AT91_REG *) 0xFFFD4008) // (US4) Interrupt Enable Register +#define AT91C_US4_RHR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (US4) Receiver Holding Register +#define AT91C_US4_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (US4) Control Register +#define AT91C_US4_IF (AT91_CAST(AT91_REG *) 0xFFFD404C) // (US4) IRDA_FILTER Register +#define AT91C_US4_IDR (AT91_CAST(AT91_REG *) 0xFFFD400C) // (US4) Interrupt Disable Register +#define AT91C_US4_CSR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (US4) Channel Status Register +// ========== Register definition for PDC_SSC0 peripheral ========== +#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register +#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register +#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register +#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register +#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register +#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register +#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register +#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register +#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register +#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register +// ========== Register definition for SSC0 peripheral ========== +#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register +#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register +#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register +#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register +#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register +#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register +#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register +#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister +#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register +#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register +#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register +#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register +#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register +#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_ADC) Receive Counter Register +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFE0014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFE003C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (ADC) ADC Control Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFE002C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFE0038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (ADC) ADC Status Register +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFE0024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFE004C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFE0030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFE0044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFE0040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFE0010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFE0048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFE0020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFE0034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFE0028) // (ADC) ADC Interrupt Disable Register +// ========== Register definition for EMACB peripheral ========== +#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFC40C0) // (EMACB) USER Input/Output Register +#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 0xFFFC4074) // (EMACB) Receive Symbol Errors Register +#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 0xFFFC4044) // (EMACB) Single Collision Frame Register +#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 0xFFFC4084) // (EMACB) SQE Test Error Register +#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 0xFFFC4070) // (EMACB) Receive Overrun Errors Register +#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer +#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (EMACB) Interrupt Mask Register +#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 0xFFFC4028) // (EMACB) Interrupt Enable Register +#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (EMACB) Revision Register +#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 0xFFFC4078) // (EMACB) Excessive Length Errors Register +#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 0xFFFC4094) // (EMACB) Hash Address Top[63:32] +#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 0xFFFC406C) // (EMACB) Receive Ressource Error Register +#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 0xFFFC404C) // (EMACB) Frames Received OK Register +#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register +#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (EMACB) Interrupt Status Register +#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (EMACB) Transmit Status Register +#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register +#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 0xFFFC4080) // (EMACB) Undersize Frames Register +#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 0xFFFC40C4) // (EMACB) Wake On LAN Register +#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 0xFFFC408C) // (EMACB) Transmitted Pause Frames Register +#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 0xFFFC4038) // (EMACB) Pause Time Register +#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 0xFFFC4064) // (EMACB) Transmit Underrun Error Register +#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 0xFFFC4034) // (EMACB) PHY Maintenance Register +#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 0xFFFC407C) // (EMACB) Receive Jabbers Register +#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 0xFFFC4068) // (EMACB) Carrier Sense Error Register +#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 0xFFFC4090) // (EMACB) Hash Address Bottom[31:0] +#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 0xFFFC4054) // (EMACB) Alignment Error Register +#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (EMACB) Network Control Register +#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 0xFFFC4040) // (EMACB) Frames Transmitted OK Register +#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFC4060) // (EMACB) Excessive Collision Register +#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 0xFFFC4058) // (EMACB) Deferred Transmission Frame Register +#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFC4050) // (EMACB) Frame Check Sequence Error Register +#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 0xFFFC40B8) // (EMACB) Type ID Checking Register +#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 0xFFFC403C) // (EMACB) Pause Frames received Register +#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 0xFFFC402C) // (EMACB) Interrupt Disable Register +#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (EMACB) Network Status Register +#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 0xFFFC4048) // (EMACB) Multiple Collision Frame Register +#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer +#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (EMACB) Receive Status Register +#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (EMACB) Network Configuration Register +#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFC405C) // (EMACB) Late Collision Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register +// ========== Register definition for UHP peripheral ========== +#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register +#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register +#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register +#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register +#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start +#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register +#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor +#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list +#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision +#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list +#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B +#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list +#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame +#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area +#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold +#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register +#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register +#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number +#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs +#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller +#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor +#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A +// ========== Register definition for HECC peripheral ========== +// ========== Register definition for HISI peripheral ========== +#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC0020) // (HISI) Preview Size Register +#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC0000) // (HISI) Control Register 1 +#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC003C) // (HISI) Color Space Conversion Register +#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC002C) // (HISI) Codec Dma Address Register +#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (HISI) Interrupt Disable Register +#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC0040) // (HISI) Color Space Conversion Register +#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC0034) // (HISI) Color Space Conversion Register +#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC0028) // (HISI) Preview Frame Buffer Address Register +#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC0004) // (HISI) Control Register 2 +#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC0030) // (HISI) Color Space Conversion Register +#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC0024) // (HISI) Preview Decimation Factor Register +#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (HISI) Interrupt Mask Register +#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC000C) // (HISI) Interrupt Enable Register +#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC0038) // (HISI) Color Space Conversion Register +#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC0008) // (HISI) Status Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM9XE256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave +#define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0 +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave +#define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2 +#define AT91C_PA10_ETX2_0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3 +#define AT91C_PA11_ETX3_0 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger +#define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TWD0 (AT91C_PIO_PA23) // TWI Two-wire Serial Data 0 +#define AT91C_PA23_ETX2_1 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_TWCK0 (AT91C_PIO_PA24) // TWI Two-wire Serial Clock 0 +#define AT91C_PA24_ETX3_1 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input +#define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock +#define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock +#define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock +#define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send +#define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send +#define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave +#define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave +#define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data +#define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data +#define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_TWD1 (AT91C_PIO_PB12) // TWI Two-wire Serial Data 1 +#define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10 +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_TWCK1 (AT91C_PIO_PB13) // TWI Two-wire Serial Clock 1 +#define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock +#define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync +#define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data +#define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data +#define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock +#define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock +#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync +#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready +#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect +#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3 +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready +#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4 +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator +#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5 +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send +#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6 +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send +#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send +#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send +#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0 +#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro +#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31 +#define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1 +#define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data +#define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data +#define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data +#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 +#define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0 +#define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock +#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 +#define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1 +#define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 +#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25] +#define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send +#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 +#define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2 +#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 +#define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0 +#define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7 +#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 +#define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input +#define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6 +#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 +#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3 +#define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2 +#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 +#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal +#define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1 +#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 +#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16] +#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 +#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17] +#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 +#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18] +#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 +#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19] +#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 +#define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2 +#define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 +#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20] +#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 +#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21] +#define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 +#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22] +#define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input +#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 +#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23] +#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24 +#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24] +#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25 +#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25] +#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26 +#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26] +#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27 +#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27] +#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28 +#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28] +#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29 +#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29] +#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 +#define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3 +#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30 +#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30] +#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31 +#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31] +#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 +#define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23] +#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 +#define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24] +#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 +#define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1 +#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 +#define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2 +#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 +#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4 +#define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send +#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 +#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5 +#define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Controller +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C +#define AT91C_ID_ADC ( 5) // ADC +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_US2 ( 8) // USART 2 +#define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0 +#define AT91C_ID_UDP (10) // USB Device Port +#define AT91C_ID_TWI0 (11) // Two-Wire Interface 0 +#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1 +#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0 +#define AT91C_ID_TC0 (17) // Timer Counter 0 +#define AT91C_ID_TC1 (18) // Timer Counter 1 +#define AT91C_ID_TC2 (19) // Timer Counter 2 +#define AT91C_ID_UHP (20) // USB Host Port +#define AT91C_ID_EMAC (21) // Ethernet Mac +#define AT91C_ID_HISI (22) // Image Sensor Interface +#define AT91C_ID_US3 (23) // USART 3 +#define AT91C_ID_US4 (24) // USART 4 +#define AT91C_ID_TWI1 (25) // Two-Wire Interface 1 +#define AT91C_ID_TC3 (26) // Timer Counter 3 +#define AT91C_ID_TC4 (27) // Timer Counter 4 +#define AT91C_ID_TC5 (28) // Timer Counter 5 +#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2) +#define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM9XE256 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFFD00) // (SYS) Base Address +#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFEA00) // (EBI) Base Address +#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFE800) // (HECC) Base Address +#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address +#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address +#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address +#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFEF10) // (CCFG) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address +#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFA00) // (EFC) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFDC000) // (TC3) Base Address +#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFDC040) // (TC4) Base Address +#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFDC080) // (TC5) Base Address +#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address +#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFDC000) // (TCB1) Base Address +#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address +#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address +#define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_TWI0) Base Address +#define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI0) Base Address +#define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_TWI1) Base Address +#define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0xFFFD8000) // (TWI1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address +#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address +#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address +#define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_US3) Base Address +#define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0xFFFD0000) // (US3) Base Address +#define AT91C_BASE_PDC_US4 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_US4) Base Address +#define AT91C_BASE_US4 (AT91_CAST(AT91PS_USART) 0xFFFD4000) // (US4) Base Address +#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address +#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFE0000) // (ADC) Base Address +#define AT91C_BASE_EMACB (AT91_CAST(AT91PS_EMAC) 0xFFFC4000) // (EMACB) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address +#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address +#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC0000) // (HISI) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE256 +// ***************************************************************************** +// IROM +#define AT91C_IROM (0x00100000) // Internal ROM base address +#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes) +// ISRAM +#define AT91C_ISRAM (0x00300000) // Maximum IRAM Area : 32Kbyte base address +#define AT91C_ISRAM_SIZE (0x00008000) // Maximum IRAM Area : 32Kbyte size in byte (32 Kbytes) +// ISRAM_MIN +#define AT91C_ISRAM_MIN (0x00300000) // Minimun IRAM Area : 32Kbyte base address +#define AT91C_ISRAM_MIN_SIZE (0x00008000) // Minimun IRAM Area : 32Kbyte size in byte (32 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00200000) // Maximum IFLASH Area : 256Kbyte base address +#define AT91C_IFLASH_SIZE (0x00040000) // Maximum IFLASH Area : 256Kbyte size in byte (256 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (512) // Maximum IFLASH Area : 256Kbyte Page Size: 512 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Maximum IFLASH Area : 256Kbyte Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (512) // Maximum IFLASH Area : 256Kbyte Number of Pages: 512 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Maximum IFLASH Area : 256Kbyte Number of Lock Bits: 16 bytes +// EBI_CS0 +#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address +#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes) +// EBI_CS1 +#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address +#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes) +// EBI_SDRAM +#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address +#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes) +// EBI_SDRAM_16BIT +#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address +#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes) +// EBI_SDRAM_32BIT +#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address +#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes) +// EBI_CS2 +#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address +#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes) +// EBI_CS3 +#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address +#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes) +// EBI_SM +#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address +#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes) +// EBI_CS4 +#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address +#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes) +// EBI_CF0 +#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address +#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes) +// EBI_CS5 +#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address +#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes) +// EBI_CF1 +#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address +#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes) +// EBI_CS6 +#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address +#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes) +// EBI_CS7 +#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address +#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes) + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/flash.icf b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/flash.icf new file mode 100644 index 0000000..eeb2bcb --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/flash.icf @@ -0,0 +1,48 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x23FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x100; +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in ROM_region { readonly }; +place in VEC_region { section .vectors }; +place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sdram.icf b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sdram.icf new file mode 100644 index 0000000..4753f07 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sdram.icf @@ -0,0 +1,46 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x100; +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_SDRAM_start__; +export symbol __ICFEDIT_region_SDRAM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__]; +define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in VEC_region { section .vectors }; +place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sram.icf b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sram.icf new file mode 100644 index 0000000..2544f86 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sram.icf @@ -0,0 +1,36 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { section .noinit }; + +place in VEC_region { section .vectors }; +place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/AT91SAM9XE512.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/AT91SAM9XE512.h new file mode 100644 index 0000000..54ac781 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/AT91SAM9XE512.h @@ -0,0 +1,4042 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the disclaimer below in the documentation and/or +// other materials provided with the distribution. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM9XE512.h +// Object : AT91SAM9XE512 definitions +// Generated : AT91 SW Application Group 02/13/2008 (18:25:59) +// +// CVS Reference : /AT91SAM9XE512.pl/1.16/Wed Jan 30 14:02:22 2008// +// CVS Reference : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008// +// CVS Reference : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007// +// CVS Reference : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007// +// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004// +// CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004// +// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004// +// CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005// +// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:53:02 2006// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006// +// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005// +// CVS Reference : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005// +// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005// +// CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM9XE512_H +#define AT91SAM9XE512_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG Reserved0[2560]; // + AT91_REG ECC_CR; // ECC reset register + AT91_REG ECC_MR; // ECC Page size register + AT91_REG ECC_SR; // ECC Status register + AT91_REG ECC_PR; // ECC Parity register + AT91_REG ECC_NPR; // ECC Parity N register + AT91_REG Reserved1[58]; // + AT91_REG ECC_VR; // ECC Version register + AT91_REG Reserved2[64]; // + AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register + AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register + AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register + AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register + AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register + AT91_REG Reserved3[118]; // + AT91_REG SMC_SETUP0; // Setup Register for CS 0 + AT91_REG SMC_PULSE0; // Pulse Register for CS 0 + AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 + AT91_REG SMC_CTRL0; // Control Register for CS 0 + AT91_REG SMC_SETUP1; // Setup Register for CS 1 + AT91_REG SMC_PULSE1; // Pulse Register for CS 1 + AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 + AT91_REG SMC_CTRL1; // Control Register for CS 1 + AT91_REG SMC_SETUP2; // Setup Register for CS 2 + AT91_REG SMC_PULSE2; // Pulse Register for CS 2 + AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 + AT91_REG SMC_CTRL2; // Control Register for CS 2 + AT91_REG SMC_SETUP3; // Setup Register for CS 3 + AT91_REG SMC_PULSE3; // Pulse Register for CS 3 + AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 + AT91_REG SMC_CTRL3; // Control Register for CS 3 + AT91_REG SMC_SETUP4; // Setup Register for CS 4 + AT91_REG SMC_PULSE4; // Pulse Register for CS 4 + AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 + AT91_REG SMC_CTRL4; // Control Register for CS 4 + AT91_REG SMC_SETUP5; // Setup Register for CS 5 + AT91_REG SMC_PULSE5; // Pulse Register for CS 5 + AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 + AT91_REG SMC_CTRL5; // Control Register for CS 5 + AT91_REG SMC_SETUP6; // Setup Register for CS 6 + AT91_REG SMC_PULSE6; // Pulse Register for CS 6 + AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 + AT91_REG SMC_CTRL6; // Control Register for CS 6 + AT91_REG SMC_SETUP7; // Setup Register for CS 7 + AT91_REG SMC_PULSE7; // Pulse Register for CS 7 + AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 + AT91_REG SMC_CTRL7; // Control Register for CS 7 + AT91_REG Reserved4[96]; // + AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) + AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) + AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) + AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi) + AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) + AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) + AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) + AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) + AT91_REG Reserved5[8]; // + AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) + AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) + AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) + AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi) + AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) + AT91_REG Reserved6[11]; // + AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) + AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) + AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) + AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) + AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) + AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) + AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs + AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs + AT91_REG MATRIX_PRAS4; // PRAS4 : ebi + AT91_REG MATRIX_PRBS4; // PRBS4 : ebi + AT91_REG Reserved7[22]; // + AT91_REG MATRIX_MRCR; // Master Remp Control Register + AT91_REG Reserved8[6]; // + AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register + AT91_REG Reserved9[3]; // + AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register + AT91_REG Reserved10[51]; // + AT91_REG CCFG_MATRIXVERSION; // Version Register + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved11[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved12[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved13[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved14[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved15[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved16[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved18[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved19[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved20[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved21[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved22[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved23[213]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved24[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved25[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved26[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved27[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved28[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved29[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved30[85]; // + AT91_REG PIOC_PER; // PIO Enable Register + AT91_REG PIOC_PDR; // PIO Disable Register + AT91_REG PIOC_PSR; // PIO Status Register + AT91_REG Reserved31[1]; // + AT91_REG PIOC_OER; // Output Enable Register + AT91_REG PIOC_ODR; // Output Disable Registerr + AT91_REG PIOC_OSR; // Output Status Register + AT91_REG Reserved32[1]; // + AT91_REG PIOC_IFER; // Input Filter Enable Register + AT91_REG PIOC_IFDR; // Input Filter Disable Register + AT91_REG PIOC_IFSR; // Input Filter Status Register + AT91_REG Reserved33[1]; // + AT91_REG PIOC_SODR; // Set Output Data Register + AT91_REG PIOC_CODR; // Clear Output Data Register + AT91_REG PIOC_ODSR; // Output Data Status Register + AT91_REG PIOC_PDSR; // Pin Data Status Register + AT91_REG PIOC_IER; // Interrupt Enable Register + AT91_REG PIOC_IDR; // Interrupt Disable Register + AT91_REG PIOC_IMR; // Interrupt Mask Register + AT91_REG PIOC_ISR; // Interrupt Status Register + AT91_REG PIOC_MDER; // Multi-driver Enable Register + AT91_REG PIOC_MDDR; // Multi-driver Disable Register + AT91_REG PIOC_MDSR; // Multi-driver Status Register + AT91_REG Reserved34[1]; // + AT91_REG PIOC_PPUDR; // Pull-up Disable Register + AT91_REG PIOC_PPUER; // Pull-up Enable Register + AT91_REG PIOC_PPUSR; // Pull-up Status Register + AT91_REG Reserved35[1]; // + AT91_REG PIOC_ASR; // Select A Register + AT91_REG PIOC_BSR; // Select B Register + AT91_REG PIOC_ABSR; // AB Select Status Register + AT91_REG Reserved36[9]; // + AT91_REG PIOC_OWER; // Output Write Enable Register + AT91_REG PIOC_OWDR; // Output Write Disable Register + AT91_REG PIOC_OWSR; // Output Write Status Register + AT91_REG Reserved37[85]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved38[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved39[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG PMC_PLLAR; // PLL A Register + AT91_REG PMC_PLLBR; // PLL B Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved40[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved41[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved42[1]; // + AT91_REG SHDWC_SHCR; // Shut Down Control Register + AT91_REG SHDWC_SHMR; // Shut Down Mode Register + AT91_REG SHDWC_SHSR; // Shut Down Status Register + AT91_REG Reserved43[1]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved44[1]; // + AT91_REG SYS_GPBR[4]; // General Purpose Register +} AT91S_SYS, *AT91PS_SYS; +#else +#define SYS_GPBR (AT91_CAST(AT91_REG *) 0x00003D50) // (SYS_GPBR) General Purpose Register + +#endif +// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- +#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR External Bus Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EBI { + AT91_REG EBI_DUMMY; // Dummy register - Do not use +} AT91S_EBI, *AT91PS_EBI; +#else +#define EBI_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_DUMMY) Dummy register - Do not use + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Error Correction Code controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ECC { + AT91_REG ECC_CR; // ECC reset register + AT91_REG ECC_MR; // ECC Page size register + AT91_REG ECC_SR; // ECC Status register + AT91_REG ECC_PR; // ECC Parity register + AT91_REG ECC_NPR; // ECC Parity N register + AT91_REG Reserved0[58]; // + AT91_REG ECC_VR; // ECC Version register +} AT91S_ECC, *AT91PS_ECC; +#else +#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register +#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register +#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register +#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register +#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register +#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register + +#endif +// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- +#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity +// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- +#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size +// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- +#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error +#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error +#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR +// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- +#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error +#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit +// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- +#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N +// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- +#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR SDRAM Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SDRAMC { + AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register + AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register + AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register + AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register + AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register +} AT91S_SDRAMC, *AT91PS_SDRAMC; +#else +#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register +#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register +#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register +#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register +#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register +#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register +#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register +#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register +#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register +#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register + +#endif +// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- +#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode +#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode +#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access +#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access +#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access +#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh +#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register +#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode +// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- +#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter +// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- +#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits +#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits +#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits +#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits +#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits +#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits +#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits +#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits +#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits +#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks +#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks +#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks +#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency +#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles +#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles +#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width +#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus +#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus +#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles +#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles +#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles +#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles +#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles +#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15 +#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles +#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0 +#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1 +#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2 +#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3 +#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4 +#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5 +#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6 +#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7 +#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8 +#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9 +#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10 +#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11 +#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12 +#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13 +#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14 +#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15 +// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- +#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit +#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle +#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle +// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- +#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations +#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features +#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH +#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN +#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN +#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM) +#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM) +#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM) +#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled +#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately +#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer +#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer +// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status +// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- +// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- +#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type +#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode +#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Static Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SMC { + AT91_REG SMC_SETUP0; // Setup Register for CS 0 + AT91_REG SMC_PULSE0; // Pulse Register for CS 0 + AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 + AT91_REG SMC_CTRL0; // Control Register for CS 0 + AT91_REG SMC_SETUP1; // Setup Register for CS 1 + AT91_REG SMC_PULSE1; // Pulse Register for CS 1 + AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 + AT91_REG SMC_CTRL1; // Control Register for CS 1 + AT91_REG SMC_SETUP2; // Setup Register for CS 2 + AT91_REG SMC_PULSE2; // Pulse Register for CS 2 + AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 + AT91_REG SMC_CTRL2; // Control Register for CS 2 + AT91_REG SMC_SETUP3; // Setup Register for CS 3 + AT91_REG SMC_PULSE3; // Pulse Register for CS 3 + AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 + AT91_REG SMC_CTRL3; // Control Register for CS 3 + AT91_REG SMC_SETUP4; // Setup Register for CS 4 + AT91_REG SMC_PULSE4; // Pulse Register for CS 4 + AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 + AT91_REG SMC_CTRL4; // Control Register for CS 4 + AT91_REG SMC_SETUP5; // Setup Register for CS 5 + AT91_REG SMC_PULSE5; // Pulse Register for CS 5 + AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 + AT91_REG SMC_CTRL5; // Control Register for CS 5 + AT91_REG SMC_SETUP6; // Setup Register for CS 6 + AT91_REG SMC_PULSE6; // Pulse Register for CS 6 + AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 + AT91_REG SMC_CTRL6; // Control Register for CS 6 + AT91_REG SMC_SETUP7; // Setup Register for CS 7 + AT91_REG SMC_PULSE7; // Pulse Register for CS 7 + AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 + AT91_REG SMC_CTRL7; // Control Register for CS 7 +} AT91S_SMC, *AT91PS_SMC; +#else +#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0 +#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0 +#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0 +#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0 +#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1 +#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1 +#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1 +#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1 +#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2 +#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2 +#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2 +#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2 +#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3 +#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3 +#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3 +#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3 +#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4 +#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4 +#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4 +#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4 +#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5 +#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5 +#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5 +#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5 +#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6 +#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6 +#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6 +#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6 +#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7 +#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7 +#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7 +#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7 + +#endif +// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- +#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length +#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access +#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length +#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access +// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- +#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length +#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access +#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length +#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access +// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- +#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length +#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length +// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- +#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode +#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode +#define AT91C_SMC_NWAITM (0x3 << 4) // (SMC) NWAIT Mode +#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 4) // (SMC) External NWAIT disabled. +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 4) // (SMC) External NWAIT enabled in frozen mode. +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 4) // (SMC) External NWAIT enabled in ready mode. +#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type +#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. +#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. +#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width +#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits. +#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits. +#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits. +#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time. +#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled. +#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled. +#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size +#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes. +#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes. +#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes. +#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes. +// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR AHB Matrix Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MATRIX { + AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 (ram96k) + AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 (rom) + AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 (hperiphs) + AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 (ebi) + AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 (bridge) + AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 (mailbox) + AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 (ram16k) + AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 (teak_prog) + AT91_REG Reserved0[8]; // + AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 (ram96k) + AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 (rom) + AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 (hperiphs) + AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 (ebi) + AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 (bridge) + AT91_REG Reserved1[11]; // + AT91_REG MATRIX_PRAS0; // PRAS0 (ram0) + AT91_REG MATRIX_PRBS0; // PRBS0 (ram0) + AT91_REG MATRIX_PRAS1; // PRAS1 (ram1) + AT91_REG MATRIX_PRBS1; // PRBS1 (ram1) + AT91_REG MATRIX_PRAS2; // PRAS2 (ram2) + AT91_REG MATRIX_PRBS2; // PRBS2 (ram2) + AT91_REG MATRIX_PRAS3; // PRAS3 : usb_dev_hs + AT91_REG MATRIX_PRBS3; // PRBS3 : usb_dev_hs + AT91_REG MATRIX_PRAS4; // PRAS4 : ebi + AT91_REG MATRIX_PRBS4; // PRBS4 : ebi + AT91_REG Reserved2[22]; // + AT91_REG MATRIX_MRCR; // Master Remp Control Register + AT91_REG Reserved3[6]; // + AT91_REG MATRIX_EBI; // Slave 3 (ebi) Special Function Register + AT91_REG Reserved4[3]; // + AT91_REG MATRIX_TEAKCFG; // Slave 7 (teak_prog) Special Function Register + AT91_REG Reserved5[51]; // + AT91_REG MATRIX_VERSION; // Version Register +} AT91S_MATRIX, *AT91PS_MATRIX; +#else +#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 (ram96k) +#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 (rom) +#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 (hperiphs) +#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 (ebi) +#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 (bridge) +#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 (mailbox) +#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 (ram16k) +#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 (teak_prog) +#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 (ram96k) +#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 (rom) +#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 (hperiphs) +#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 (ebi) +#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 (bridge) +#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 (ram0) +#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 (ram0) +#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 (ram1) +#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 (ram1) +#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 (ram2) +#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 (ram2) +#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 : usb_dev_hs +#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 : usb_dev_hs +#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 : ebi +#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 : ebi +#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register +#define MATRIX_EBI (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_EBI) Slave 3 (ebi) Special Function Register +#define MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_TEAKCFG) Slave 7 (teak_prog) Special Function Register +#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x000001FC) // (MATRIX_VERSION) Version Register + +#endif +// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- +#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst +#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type +#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. +#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. +#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. +#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master +// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master +// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x4 << 18) // (MATRIX) DMA Master is Default Master +// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- +#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master +#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master +// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- +#define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority +#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority +#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority +#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority +#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority +#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority +#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority +#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority +// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- +#define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority +// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- +// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- +// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- +// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- +// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- +// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- +// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- +// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- +// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- +#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master +#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master +// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- +#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment +#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment +#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. +#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment +#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. +#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. +#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment +#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC +#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. +#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration +// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- +#define AT91C_TEAK_PROGRAM_ACCESS (0x1 << 0) // (MATRIX) TEAK program memory access from AHB +#define AT91C_TEAK_PROGRAM_ACCESS_DISABLED (0x0) // (MATRIX) TEAK program access disabled +#define AT91C_TEAK_PROGRAM_ACCESS_ENABLED (0x1) // (MATRIX) TEAK program access enabled +#define AT91C_TEAK_BOOT (0x1 << 1) // (MATRIX) TEAK program start from boot routine +#define AT91C_TEAK_BOOT_DISABLED (0x0 << 1) // (MATRIX) TEAK program starts from boot routine disabled +#define AT91C_TEAK_BOOT_ENABLED (0x1 << 1) // (MATRIX) TEAK program starts from boot routine enabled +#define AT91C_TEAK_NRESET (0x1 << 2) // (MATRIX) active low TEAK reset +#define AT91C_TEAK_NRESET_ENABLED (0x0 << 2) // (MATRIX) active low TEAK reset enabled +#define AT91C_TEAK_NRESET_DISABLED (0x1 << 2) // (MATRIX) active low TEAK reset disabled +#define AT91C_TEAK_LVECTORP (0x3FFFF << 14) // (MATRIX) boot routine start address + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Chip Configuration Registers +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CCFG { + AT91_REG Reserved0[3]; // + AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register + AT91_REG Reserved1[55]; // + AT91_REG CCFG_MATRIXVERSION; // Version Register +} AT91S_CCFG, *AT91PS_CCFG; +#else +#define CCFG_EBICSA (AT91_CAST(AT91_REG *) 0x0000000C) // (CCFG_EBICSA) EBI Chip Select Assignement Register +#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register + +#endif +// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- +#define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment +#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment +#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. +#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment +#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. +#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. +#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment +#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC +#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. +#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration +#define AT91C_EBI_SUPPLY (0x1 << 16) // (CCFG) EBI supply selection + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // EFC Flash Mode Register + AT91_REG EFC_FCR; // EFC Flash Command Register + AT91_REG EFC_FSR; // EFC Flash Status Register + AT91_REG EFC_FRR; // EFC Flash Result Register + AT91_REG EFC_FVR; // EFC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; +#else +#define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register +#define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register +#define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register +#define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register +#define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000010) // (EFC_FVR) EFC Flash Version Register + +#endif +// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- +#define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable +#define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State. +#define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State +#define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State +#define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States +#define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States +// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- +#define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command +#define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor +#define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page +#define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock +#define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page +#define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock +#define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All +#define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane +#define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages +#define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit +#define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit +#define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit +#define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit +#define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit +#define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit +#define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument +#define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key +// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- +#define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status +#define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status +#define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status +// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- +#define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG CKGR_PLLAR; // PLL A Register + AT91_REG CKGR_PLLBR; // PLL B Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register +#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- +#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected +#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0 +#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed +#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter +#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range +#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier +#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) +// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected +#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0 +#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed +#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter +#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range +#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG PMC_PLLAR; // PLL A Register + AT91_REG PMC_PLLBR; // PLL B Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved2[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock +#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- +// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected +#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division +#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same +#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock +#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Shut Down Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SHDWC { + AT91_REG SHDWC_SHCR; // Shut Down Control Register + AT91_REG SHDWC_SHMR; // Shut Down Mode Register + AT91_REG SHDWC_SHSR; // Shut Down Status Register +} AT91S_SHDWC, *AT91PS_SHDWC; +#else +#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register +#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register +#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register + +#endif +// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- +#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset +#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password +// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- +#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection +#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input. +#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level. +#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level. +#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change. +#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0 +#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection +#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input. +#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level. +#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level. +#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change. +#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1 +#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable +#define AT91C_SHDWC_RTCWKEN (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable +// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- +#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status +#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status +#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status +#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up +#define AT91C_SHDWC_RTCWK (0x1 << 17) // (SHDWC) Real Time Clock wake Up + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Multimedia Card Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MCI { + AT91_REG MCI_CR; // MCI Control Register + AT91_REG MCI_MR; // MCI Mode Register + AT91_REG MCI_DTOR; // MCI Data Timeout Register + AT91_REG MCI_SDCR; // MCI SD Card Register + AT91_REG MCI_ARGR; // MCI Argument Register + AT91_REG MCI_CMDR; // MCI Command Register + AT91_REG MCI_BLKR; // MCI Block Register + AT91_REG Reserved0[1]; // + AT91_REG MCI_RSPR[4]; // MCI Response Register + AT91_REG MCI_RDR; // MCI Receive Data Register + AT91_REG MCI_TDR; // MCI Transmit Data Register + AT91_REG Reserved1[2]; // + AT91_REG MCI_SR; // MCI Status Register + AT91_REG MCI_IER; // MCI Interrupt Enable Register + AT91_REG MCI_IDR; // MCI Interrupt Disable Register + AT91_REG MCI_IMR; // MCI Interrupt Mask Register + AT91_REG Reserved2[43]; // + AT91_REG MCI_VR; // MCI Version Register + AT91_REG MCI_RPR; // Receive Pointer Register + AT91_REG MCI_RCR; // Receive Counter Register + AT91_REG MCI_TPR; // Transmit Pointer Register + AT91_REG MCI_TCR; // Transmit Counter Register + AT91_REG MCI_RNPR; // Receive Next Pointer Register + AT91_REG MCI_RNCR; // Receive Next Counter Register + AT91_REG MCI_TNPR; // Transmit Next Pointer Register + AT91_REG MCI_TNCR; // Transmit Next Counter Register + AT91_REG MCI_PTCR; // PDC Transfer Control Register + AT91_REG MCI_PTSR; // PDC Transfer Status Register +} AT91S_MCI, *AT91PS_MCI; +#else +#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register +#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register +#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register +#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register +#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register +#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register +#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register +#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register +#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register +#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register +#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register +#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register +#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register +#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register +#define MCI_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VR) MCI Version Register + +#endif +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable +#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable +#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable +#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable +#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider +#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider +#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable +#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable +#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer +#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value +#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode +#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number +#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier +#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1 +#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16 +#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128 +#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256 +#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024 +#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096 +#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536 +#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576 +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card Selector +#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SDCard/SDIO Bus Width +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number +#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type +#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response +#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response +#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response +#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD +#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD +#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD +#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD +#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command +#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response +#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command +#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond +#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD +#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer +#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer +#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer +#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction +#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type +#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type +#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type +#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type +#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type +#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type +#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command +#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command +#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command +#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command +// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- +#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag +#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag +#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag +#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag +#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag +#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag +#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag +#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag +#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A +#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B +#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C +#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D +#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag +#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag +#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag +#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag +#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag +#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag +#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag +#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag +#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag +#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag +#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved1[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode) +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode) +#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode) +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode) +#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode) +#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode) +#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode) +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Host Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UHP { + AT91_REG UHP_HcRevision; // Revision + AT91_REG UHP_HcControl; // Operating modes for the Host Controller + AT91_REG UHP_HcCommandStatus; // Command & status Register + AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register + AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register + AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register + AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area + AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor + AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list + AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register + AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list + AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list + AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor + AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs + AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame + AT91_REG UHP_HcFmNumber; // Frame number + AT91_REG UHP_HcPeriodicStart; // Periodic Start + AT91_REG UHP_HcLSThreshold; // LS Threshold + AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A + AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B + AT91_REG UHP_HcRhStatus; // Root Hub Status register + AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register +} AT91S_UHP, *AT91PS_UHP; +#else +#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision +#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller +#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register +#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register +#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register +#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register +#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area +#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor +#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list +#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register +#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list +#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list +#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor +#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs +#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame +#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number +#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start +#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold +#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A +#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B +#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register +#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Image Sensor Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ISI { + AT91_REG ISI_CR1; // Control Register 1 + AT91_REG ISI_CR2; // Control Register 2 + AT91_REG ISI_SR; // Status Register + AT91_REG ISI_IER; // Interrupt Enable Register + AT91_REG ISI_IDR; // Interrupt Disable Register + AT91_REG ISI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[2]; // + AT91_REG ISI_PSIZE; // Preview Size Register + AT91_REG ISI_PDECF; // Preview Decimation Factor Register + AT91_REG ISI_PFBD; // Preview Frame Buffer Address Register + AT91_REG ISI_CDBA; // Codec Dma Address Register + AT91_REG ISI_Y2RSET0; // Color Space Conversion Register + AT91_REG ISI_Y2RSET1; // Color Space Conversion Register + AT91_REG ISI_R2YSET0; // Color Space Conversion Register + AT91_REG ISI_R2YSET1; // Color Space Conversion Register + AT91_REG ISI_R2YSET2; // Color Space Conversion Register +} AT91S_ISI, *AT91PS_ISI; +#else +#define ISI_CR1 (AT91_CAST(AT91_REG *) 0x00000000) // (ISI_CR1) Control Register 1 +#define ISI_CR2 (AT91_CAST(AT91_REG *) 0x00000004) // (ISI_CR2) Control Register 2 +#define ISI_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ISI_SR) Status Register +#define ISI_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (ISI_IER) Interrupt Enable Register +#define ISI_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (ISI_IDR) Interrupt Disable Register +#define ISI_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (ISI_IMR) Interrupt Mask Register +#define ISI_PSIZE (AT91_CAST(AT91_REG *) 0x00000020) // (ISI_PSIZE) Preview Size Register +#define ISI_PDECF (AT91_CAST(AT91_REG *) 0x00000024) // (ISI_PDECF) Preview Decimation Factor Register +#define ISI_PFBD (AT91_CAST(AT91_REG *) 0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register +#define ISI_CDBA (AT91_CAST(AT91_REG *) 0x0000002C) // (ISI_CDBA) Codec Dma Address Register +#define ISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register +#define ISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register +#define ISI_R2YSET0 (AT91_CAST(AT91_REG *) 0x00000038) // (ISI_R2YSET0) Color Space Conversion Register +#define ISI_R2YSET1 (AT91_CAST(AT91_REG *) 0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register +#define ISI_R2YSET2 (AT91_CAST(AT91_REG *) 0x00000040) // (ISI_R2YSET2) Color Space Conversion Register + +#endif +// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- +#define AT91C_ISI_RST (0x1 << 0) // (ISI) Image sensor interface reset +#define AT91C_ISI_DISABLE (0x1 << 1) // (ISI) image sensor disable. +#define AT91C_ISI_HSYNC_POL (0x1 << 2) // (ISI) Horizontal synchronisation polarity +#define AT91C_ISI_PIXCLK_POL (0x1 << 4) // (ISI) Pixel Clock Polarity +#define AT91C_ISI_EMB_SYNC (0x1 << 6) // (ISI) Embedded synchronisation +#define AT91C_ISI_CRC_SYNC (0x1 << 7) // (ISI) CRC correction +#define AT91C_ISI_FULL (0x1 << 12) // (ISI) Full mode is allowed +#define AT91C_ISI_THMASK (0x3 << 13) // (ISI) DMA Burst Mask +#define AT91C_ISI_THMASK_4_8_16_BURST (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed +#define AT91C_ISI_THMASK_8_16_BURST (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed +#define AT91C_ISI_THMASK_16_BURST (0x2 << 13) // (ISI) Only 16 AHB burst are allowed +#define AT91C_ISI_CODEC_ON (0x1 << 15) // (ISI) Enable the codec path +#define AT91C_ISI_SLD (0xFF << 16) // (ISI) Start of Line Delay +#define AT91C_ISI_SFD (0xFF << 24) // (ISI) Start of frame Delay +// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- +#define AT91C_ISI_IM_VSIZE (0x7FF << 0) // (ISI) Vertical size of the Image sensor [0..2047] +#define AT91C_ISI_GS_MODE (0x1 << 11) // (ISI) Grayscale Memory Mode +#define AT91C_ISI_RGB_MODE (0x3 << 12) // (ISI) RGB mode +#define AT91C_ISI_RGB_MODE_RGB_888 (0x0 << 12) // (ISI) RGB 8:8:8 24 bits +#define AT91C_ISI_RGB_MODE_RGB_565 (0x1 << 12) // (ISI) RGB 5:6:5 16 bits +#define AT91C_ISI_RGB_MODE_RGB_555 (0x2 << 12) // (ISI) RGB 5:5:5 16 bits +#define AT91C_ISI_GRAYSCALE (0x1 << 13) // (ISI) Grayscale Mode +#define AT91C_ISI_RGB_SWAP (0x1 << 14) // (ISI) RGB Swap +#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data +#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047] +#define AT91C_ISI_RGB_MODE_YCC_DEF (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1) +#define AT91C_ISI_RGB_MODE_YCC_MOD1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1) +#define AT91C_ISI_RGB_MODE_YCC_MOD2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i) +#define AT91C_ISI_RGB_MODE_YCC_MOD3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i) +#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration +#define AT91C_ISI_RGB_CFG_RGB_DEF (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B +#define AT91C_ISI_RGB_CFG_RGB_MOD1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R +#define AT91C_ISI_RGB_CFG_RGB_MOD2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB) +#define AT91C_ISI_RGB_CFG_RGB_MOD3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB) +// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- +#define AT91C_ISI_SOF (0x1 << 0) // (ISI) Start of Frame +#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface disable +#define AT91C_ISI_SOFTRST (0x1 << 2) // (ISI) Software Reset +#define AT91C_ISI_CRC_ERR (0x1 << 4) // (ISI) CRC synchronisation error +#define AT91C_ISI_FO_C_OVF (0x1 << 5) // (ISI) Fifo Codec Overflow +#define AT91C_ISI_FO_P_OVF (0x1 << 6) // (ISI) Fifo Preview Overflow +#define AT91C_ISI_FO_P_EMP (0x1 << 7) // (ISI) Fifo Preview Empty +#define AT91C_ISI_FO_C_EMP (0x1 << 8) // (ISI) Fifo Codec Empty +#define AT91C_ISI_FR_OVR (0x1 << 9) // (ISI) Frame rate overun +// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- +// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- +// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- +// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- +#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path +#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path +// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- +#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0 +#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1 +#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2 +#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3 +// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- +#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4 +#define AT91C_ISI_Y2R_YOFF (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset +#define AT91C_ISI_Y2R_CROFF (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset +#define AT91C_ISI_Y2R_CBFF (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset +// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- +#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0 +#define AT91C_ISI_R2Y_C1 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1 +#define AT91C_ISI_R2Y_C2 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2 +#define AT91C_ISI_R2Y_ROFF (0x1 << 4) // (ISI) Color Space Conversion Red component offset +// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- +#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3 +#define AT91C_ISI_R2Y_C4 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4 +#define AT91C_ISI_R2Y_C5 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5 +#define AT91C_ISI_R2Y_GOFF (0x1 << 4) // (ISI) Color Space Conversion Green component offset +// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- +#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6 +#define AT91C_ISI_R2Y_C7 (0x7F << 1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7 +#define AT91C_ISI_R2Y_C8 (0x7F << 3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8 +#define AT91C_ISI_R2Y_BOFF (0x1 << 4) // (ISI) Color Space Conversion Blue component offset + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM9XE512 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFFFF) // (SYS) General Purpose Register +// ========== Register definition for EBI peripheral ========== +#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (EBI) Dummy register - Do not use +// ========== Register definition for HECC peripheral ========== +#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFE8FC) // (HECC) ECC Version register +#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFE810) // (HECC) ECC Parity N register +#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFE808) // (HECC) ECC Status register +#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFE80C) // (HECC) ECC Parity register +#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFE804) // (HECC) ECC Page size register +#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFE800) // (HECC) ECC reset register +// ========== Register definition for SDRAMC peripheral ========== +#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register +#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register +#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register +#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register +#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register +#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register +#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register +#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register +// ========== Register definition for SMC peripheral ========== +#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1 +#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7 +#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6 +#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4 +#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3 +#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5 +#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2 +#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2 +#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0 +#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5 +#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1 +#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0 +#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7 +#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4 +#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3 +#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7 +#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7 +#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1 +#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0 +#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5 +#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1 +#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6 +#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0 +#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4 +#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5 +#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2 +#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3 +#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6 +#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6 +#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4 +#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2 +#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3 +// ========== Register definition for MATRIX peripheral ========== +#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register 0 (ram96k) +#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0xFFFFEE1C) // (MATRIX) Master Configuration Register 7 (teak_prog) +#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Slave Configuration Register 1 (rom) +#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Master Configuration Register 4 (bridge) +#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (MATRIX) Version Register +#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Master Configuration Register 2 (hperiphs) +#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA4) // (MATRIX) PRBS4 : ebi +#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX) PRBS0 (ram0) +#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE4C) // (MATRIX) Slave Configuration Register 3 (ebi) +#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0xFFFFEE18) // (MATRIX) Master Configuration Register 6 (ram16k) +#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (MATRIX) Slave 3 (ebi) Special Function Register +#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register 0 (ram96k) +#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0xFFFFEE9C) // (MATRIX) PRBS3 : usb_dev_hs +#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0xFFFFEE98) // (MATRIX) PRAS3 : usb_dev_hs +#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX) PRAS0 (ram0) +#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Master Configuration Register 3 (ebi) +#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0xFFFFEE88) // (MATRIX) PRAS1 (ram1) +#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0xFFFFEE90) // (MATRIX) PRAS2 (ram2) +#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE48) // (MATRIX) Slave Configuration Register 2 (hperiphs) +#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Master Configuration Register 5 (mailbox) +#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Master Configuration Register 1 (rom) +#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0xFFFFEEA0) // (MATRIX) PRAS4 : ebi +#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register +#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0xFFFFEE94) // (MATRIX) PRBS2 (ram2) +#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE50) // (MATRIX) Slave Configuration Register 4 (bridge) +#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 0xFFFFEF2C) // (MATRIX) Slave 7 (teak_prog) Special Function Register +#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0xFFFFEE8C) // (MATRIX) PRBS1 (ram1) +// ========== Register definition for CCFG peripheral ========== +#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0xFFFFEFFC) // (CCFG) Version Register +#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for PIOC peripheral ========== +#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register +#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register +#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register +#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register +#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register +#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register +#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr +#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register +#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register +#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register +#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register +#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register +#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register +#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register +#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register +#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register +#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register +#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register +#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register +#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register +#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register +#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register +#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register +#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register +#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register +#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register +#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register +#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register +#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register +// ========== Register definition for EFC peripheral ========== +#define AT91C_EFC_FVR (AT91_CAST(AT91_REG *) 0xFFFFFA10) // (EFC) EFC Flash Version Register +#define AT91C_EFC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFA04) // (EFC) EFC Flash Command Register +#define AT91C_EFC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFA00) // (EFC) EFC Flash Mode Register +#define AT91C_EFC_FRR (AT91_CAST(AT91_REG *) 0xFFFFFA0C) // (EFC) EFC Flash Result Register +#define AT91C_EFC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFA08) // (EFC) EFC Flash Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for SHDWC peripheral ========== +#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register +#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register +#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TC3 peripheral ========== +#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (TC3) Interrupt Enable Register +#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFDC018) // (TC3) Register B +#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (TC3) Register C +#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (TC3) Channel Control Register +#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (TC3) Status Register +#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFDC010) // (TC3) Counter Value +#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFDC014) // (TC3) Register A +#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (TC3) Interrupt Disable Register +#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (TC3) Interrupt Mask Register +// ========== Register definition for TC4 peripheral ========== +#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (TC4) Register C +#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFDC060) // (TC4) Status Register +#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFDC058) // (TC4) Register B +#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFDC064) // (TC4) Interrupt Enable Register +#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFDC050) // (TC4) Counter Value +#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFDC054) // (TC4) Register A +#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFDC068) // (TC4) Interrupt Disable Register +#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (TC4) Interrupt Mask Register +#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFDC040) // (TC4) Channel Control Register +// ========== Register definition for TC5 peripheral ========== +#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFDC098) // (TC5) Register B +#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFDC094) // (TC5) Register A +#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFDC090) // (TC5) Counter Value +#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFDC080) // (TC5) Channel Control Register +#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (TC5) Status Register +#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (TC5) Interrupt Enable Register +#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (TC5) Interrupt Disable Register +#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (TC5) Register C +#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (TC5) Interrupt Mask Register +#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode) +// ========== Register definition for TCB0 peripheral ========== +#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register +#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register +// ========== Register definition for TCB1 peripheral ========== +#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (TCB1) TC Block Control Register +#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (TCB1) TC Block Mode Register +// ========== Register definition for PDC_MCI peripheral ========== +#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register +#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register +#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register +#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register +#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register +#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register +#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register +#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register +#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register +#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register +// ========== Register definition for MCI peripheral ========== +#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register +#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register +#define AT91C_MCI_VR (AT91_CAST(AT91_REG *) 0xFFFA80FC) // (MCI) MCI Version Register +#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register +#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register +#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register +#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register +#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register +#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register +#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register +#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register +#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register +#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD Card Register +#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register +#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register +// ========== Register definition for PDC_TWI0 peripheral ========== +#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register +#define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_TWI0) Receive Pointer Register +#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register +#define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_TWI0) Receive Counter Register +#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register +#define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register +#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register +#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register +#define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register +#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register +// ========== Register definition for TWI0 peripheral ========== +#define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI0) Transmit Holding Register +#define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI0) Interrupt Disable Register +#define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI0) Slave Mode Register +#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI0) Clock Waveform Generator Register +#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI0) Internal Address Register +#define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI0) Receive Holding Register +#define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI0) Interrupt Enable Register +#define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI0) Master Mode Register +#define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI0) Status Register +#define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI0) Interrupt Mask Register +#define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI0) Control Register +// ========== Register definition for PDC_TWI1 peripheral ========== +#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register +#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register +#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register +#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register +#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register +#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register +#define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_TWI1) Receive Pointer Register +#define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_TWI1) Transmit Counter Register +#define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register +#define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_TWI1) Receive Counter Register +// ========== Register definition for TWI1 peripheral ========== +#define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0xFFFD8030) // (TWI1) Receive Holding Register +#define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (TWI1) Interrupt Enable Register +#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0xFFFD8010) // (TWI1) Clock Waveform Generator Register +#define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (TWI1) Master Mode Register +#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0xFFFD800C) // (TWI1) Internal Address Register +#define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0xFFFD8034) // (TWI1) Transmit Holding Register +#define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (TWI1) Interrupt Mask Register +#define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (TWI1) Status Register +#define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (TWI1) Interrupt Disable Register +#define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (TWI1) Control Register +#define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0xFFFD8008) // (TWI1) Slave Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register +// ========== Register definition for PDC_US2 peripheral ========== +#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register +#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register +#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register +#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register +#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register +#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register +#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register +#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register +#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register +#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register +// ========== Register definition for US2 peripheral ========== +#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register +#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register +#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register +#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register +#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register +#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register +#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register +#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register +#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register +#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register +#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register +#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register +#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register +#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register +// ========== Register definition for PDC_US3 peripheral ========== +#define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_US3) Receive Next Pointer Register +#define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_US3) Receive Next Counter Register +#define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_US3) PDC Transfer Status Register +#define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_US3) PDC Transfer Control Register +#define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_US3) Transmit Counter Register +#define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register +#define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_US3) Receive Counter Register +#define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_US3) Transmit Pointer Register +#define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_US3) Transmit Next Counter Register +#define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_US3) Receive Pointer Register +// ========== Register definition for US3 peripheral ========== +#define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (US3) Nb Errors Register +#define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (US3) Receiver Time-out Register +#define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (US3) Interrupt Disable Register +#define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (US3) Mode Register +#define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0xFFFD0040) // (US3) FI_DI_Ratio Register +#define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (US3) Baud Rate Generator Register +#define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (US3) Transmitter Holding Register +#define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (US3) Control Register +#define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0xFFFD004C) // (US3) IRDA_FILTER Register +#define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0xFFFD0008) // (US3) Interrupt Enable Register +#define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (US3) Transmitter Time-guard Register +#define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (US3) Receiver Holding Register +#define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (US3) Interrupt Mask Register +#define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (US3) Channel Status Register +// ========== Register definition for PDC_US4 peripheral ========== +#define AT91C_US4_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_US4) Transmit Next Counter Register +#define AT91C_US4_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_US4) Receive Pointer Register +#define AT91C_US4_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_US4) Receive Next Counter Register +#define AT91C_US4_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_US4) Transmit Pointer Register +#define AT91C_US4_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_US4) PDC Transfer Control Register +#define AT91C_US4_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_US4) Transmit Counter Register +#define AT91C_US4_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_US4) Receive Counter Register +#define AT91C_US4_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_US4) Receive Next Pointer Register +#define AT91C_US4_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register +#define AT91C_US4_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_US4) PDC Transfer Status Register +// ========== Register definition for US4 peripheral ========== +#define AT91C_US4_BRGR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (US4) Baud Rate Generator Register +#define AT91C_US4_THR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (US4) Transmitter Holding Register +#define AT91C_US4_RTOR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (US4) Receiver Time-out Register +#define AT91C_US4_IMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (US4) Interrupt Mask Register +#define AT91C_US4_NER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (US4) Nb Errors Register +#define AT91C_US4_TTGR (AT91_CAST(AT91_REG *) 0xFFFD4028) // (US4) Transmitter Time-guard Register +#define AT91C_US4_FIDI (AT91_CAST(AT91_REG *) 0xFFFD4040) // (US4) FI_DI_Ratio Register +#define AT91C_US4_MR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (US4) Mode Register +#define AT91C_US4_IER (AT91_CAST(AT91_REG *) 0xFFFD4008) // (US4) Interrupt Enable Register +#define AT91C_US4_RHR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (US4) Receiver Holding Register +#define AT91C_US4_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (US4) Control Register +#define AT91C_US4_IF (AT91_CAST(AT91_REG *) 0xFFFD404C) // (US4) IRDA_FILTER Register +#define AT91C_US4_IDR (AT91_CAST(AT91_REG *) 0xFFFD400C) // (US4) Interrupt Disable Register +#define AT91C_US4_CSR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (US4) Channel Status Register +// ========== Register definition for PDC_SSC0 peripheral ========== +#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register +#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register +#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register +#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register +#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register +#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register +#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register +#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register +#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register +#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register +// ========== Register definition for SSC0 peripheral ========== +#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register +#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register +#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register +#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register +#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register +#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register +#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register +#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister +#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register +#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register +#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register +#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register +#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register +#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_ADC) Receive Counter Register +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFE0014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFE003C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (ADC) ADC Control Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFE002C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFE0038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (ADC) ADC Status Register +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFE0024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFE004C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFE0030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFE0044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFE0040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFE0010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFE0048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFE0020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFE0034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFE0028) // (ADC) ADC Interrupt Disable Register +// ========== Register definition for EMACB peripheral ========== +#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 0xFFFC40C0) // (EMACB) USER Input/Output Register +#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 0xFFFC4074) // (EMACB) Receive Symbol Errors Register +#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 0xFFFC4044) // (EMACB) Single Collision Frame Register +#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 0xFFFC4084) // (EMACB) SQE Test Error Register +#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 0xFFFC4070) // (EMACB) Receive Overrun Errors Register +#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer +#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (EMACB) Interrupt Mask Register +#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 0xFFFC4028) // (EMACB) Interrupt Enable Register +#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (EMACB) Revision Register +#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 0xFFFC4078) // (EMACB) Excessive Length Errors Register +#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 0xFFFC4094) // (EMACB) Hash Address Top[63:32] +#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 0xFFFC406C) // (EMACB) Receive Ressource Error Register +#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 0xFFFC404C) // (EMACB) Frames Received OK Register +#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register +#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (EMACB) Interrupt Status Register +#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (EMACB) Transmit Status Register +#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register +#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 0xFFFC4080) // (EMACB) Undersize Frames Register +#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 0xFFFC40C4) // (EMACB) Wake On LAN Register +#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 0xFFFC408C) // (EMACB) Transmitted Pause Frames Register +#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 0xFFFC4038) // (EMACB) Pause Time Register +#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 0xFFFC4064) // (EMACB) Transmit Underrun Error Register +#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 0xFFFC4034) // (EMACB) PHY Maintenance Register +#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 0xFFFC407C) // (EMACB) Receive Jabbers Register +#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 0xFFFC4068) // (EMACB) Carrier Sense Error Register +#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 0xFFFC4090) // (EMACB) Hash Address Bottom[31:0] +#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 0xFFFC4054) // (EMACB) Alignment Error Register +#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (EMACB) Network Control Register +#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 0xFFFC4040) // (EMACB) Frames Transmitted OK Register +#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 0xFFFC4060) // (EMACB) Excessive Collision Register +#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 0xFFFC4058) // (EMACB) Deferred Transmission Frame Register +#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 0xFFFC4050) // (EMACB) Frame Check Sequence Error Register +#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 0xFFFC40B8) // (EMACB) Type ID Checking Register +#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 0xFFFC403C) // (EMACB) Pause Frames received Register +#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 0xFFFC402C) // (EMACB) Interrupt Disable Register +#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 0xFFFC4008) // (EMACB) Network Status Register +#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 0xFFFC4048) // (EMACB) Multiple Collision Frame Register +#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer +#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (EMACB) Receive Status Register +#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (EMACB) Network Configuration Register +#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 0xFFFC405C) // (EMACB) Late Collision Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register +// ========== Register definition for UHP peripheral ========== +#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register +#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register +#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register +#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register +#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start +#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register +#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor +#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list +#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision +#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list +#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B +#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list +#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame +#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area +#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold +#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register +#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register +#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number +#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs +#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller +#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor +#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A +// ========== Register definition for HECC peripheral ========== +// ========== Register definition for HISI peripheral ========== +#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 0xFFFC0020) // (HISI) Preview Size Register +#define AT91C_HISI_CR1 (AT91_CAST(AT91_REG *) 0xFFFC0000) // (HISI) Control Register 1 +#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 0xFFFC003C) // (HISI) Color Space Conversion Register +#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 0xFFFC002C) // (HISI) Codec Dma Address Register +#define AT91C_HISI_IDR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (HISI) Interrupt Disable Register +#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 0xFFFC0040) // (HISI) Color Space Conversion Register +#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 0xFFFC0034) // (HISI) Color Space Conversion Register +#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 0xFFFC0028) // (HISI) Preview Frame Buffer Address Register +#define AT91C_HISI_CR2 (AT91_CAST(AT91_REG *) 0xFFFC0004) // (HISI) Control Register 2 +#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 0xFFFC0030) // (HISI) Color Space Conversion Register +#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 0xFFFC0024) // (HISI) Preview Decimation Factor Register +#define AT91C_HISI_IMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (HISI) Interrupt Mask Register +#define AT91C_HISI_IER (AT91_CAST(AT91_REG *) 0xFFFC000C) // (HISI) Interrupt Enable Register +#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 0xFFFC0038) // (HISI) Color Space Conversion Register +#define AT91C_HISI_SR (AT91_CAST(AT91_REG *) 0xFFFC0008) // (HISI) Status Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM9XE512 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI 0 Master In Slave +#define AT91C_PA0_MCDB0 (AT91C_PIO_PA0) // Multimedia Card B Data 0 +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI 0 Master Out Slave +#define AT91C_PA1_MCCDB (AT91C_PIO_PA1) // Multimedia Card B Command +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_MCDA2 (AT91C_PIO_PA10) // Multimedia Card A Data 2 +#define AT91C_PA10_ETX2_0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_MCDA3 (AT91C_PIO_PA11) // Multimedia Card A Data 3 +#define AT91C_PA11_ETX3_0 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_ETX0 (AT91C_PIO_PA12) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_ETX1 (AT91C_PIO_PA13) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_ERX0 (AT91C_PIO_PA14) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_ERX1 (AT91C_PIO_PA15) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_ETXEN (AT91C_PIO_PA16) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_ERXDV (AT91C_PIO_PA17) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_ERXER (AT91C_PIO_PA18) // Ethernet MAC Receive Error +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_ETXCK (AT91C_PIO_PA19) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_EMDC (AT91C_PIO_PA20) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_EMDIO (AT91C_PIO_PA21) // Ethernet MAC Management Data Input/Output +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_ADTRG (AT91C_PIO_PA22) // ADC Trigger +#define AT91C_PA22_ETXER (AT91C_PIO_PA22) // Ethernet MAC Transmikt Coding Error +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TWD0 (AT91C_PIO_PA23) // TWI Two-wire Serial Data 0 +#define AT91C_PA23_ETX2_1 (AT91C_PIO_PA23) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_TWCK0 (AT91C_PIO_PA24) // TWI Two-wire Serial Clock 0 +#define AT91C_PA24_ETX3_1 (AT91C_PIO_PA24) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_TCLK0 (AT91C_PIO_PA25) // Timer Counter 0 external clock input +#define AT91C_PA25_ERX2 (AT91C_PIO_PA25) // Ethernet MAC Receive Data 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PA26_ERX3 (AT91C_PIO_PA26) // Ethernet MAC Receive Data 3 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_TIOA1 (AT91C_PIO_PA27) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PA27_ERXCK (AT91C_PIO_PA27) // Ethernet MAC Receive Clock +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_TIOA2 (AT91C_PIO_PA28) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PA28_ECRS (AT91C_PIO_PA28) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_SCK1 (AT91C_PIO_PA29) // USART 1 Serial Clock +#define AT91C_PA29_ECOL (AT91C_PIO_PA29) // Ethernet MAC Collision Detected +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PA3_MCDB3 (AT91C_PIO_PA3) // Multimedia Card B Data 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_SCK2 (AT91C_PIO_PA30) // USART 2 Serial Clock +#define AT91C_PA30_RXD4 (AT91C_PIO_PA30) // USART 4 Receive Data +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_SCK0 (AT91C_PIO_PA31) // USART 0 Serial Clock +#define AT91C_PA31_TXD4 (AT91C_PIO_PA31) // USART 4 Transmit Data +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_RTS2 (AT91C_PIO_PA4) // USART 2 Ready To Send +#define AT91C_PA4_MCDB2 (AT91C_PIO_PA4) // Multimedia Card B Data 2 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_CTS2 (AT91C_PIO_PA5) // USART 2 Clear To Send +#define AT91C_PA5_MCDB1 (AT91C_PIO_PA5) // Multimedia Card B Data 1 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_MCDA0 (AT91C_PIO_PA6) // Multimedia Card A Data 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_MCCDA (AT91C_PIO_PA7) // Multimedia Card A Command +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_MCCK (AT91C_PIO_PA8) // Multimedia Card Clock +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_MCDA1 (AT91C_PIO_PA9) // Multimedia Card A Data 1 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) // SPI 1 Master In Slave +#define AT91C_PB0_TIOA3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) // SPI 1 Master Out Slave +#define AT91C_PB1_TIOB3 (AT91C_PIO_PB1) // Timer Counter 3 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_TXD3 (AT91C_PIO_PB10) // USART 3 Transmit Data +#define AT91C_PB10_ISI_D8 (AT91C_PIO_PB10) // Image Sensor Data 8 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_RXD3 (AT91C_PIO_PB11) // USART 3 Receive Data +#define AT91C_PB11_ISI_D9 (AT91C_PIO_PB11) // Image Sensor Data 9 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_TWD1 (AT91C_PIO_PB12) // TWI Two-wire Serial Data 1 +#define AT91C_PB12_ISI_D10 (AT91C_PIO_PB12) // Image Sensor Data 10 +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_TWCK1 (AT91C_PIO_PB13) // TWI Two-wire Serial Clock 1 +#define AT91C_PB13_ISI_D11 (AT91C_PIO_PB13) // Image Sensor Data 11 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_DRXD (AT91C_PIO_PB14) // DBGU Debug Receive Data +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_DTXD (AT91C_PIO_PB15) // DBGU Debug Transmit Data +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_TK0 (AT91C_PIO_PB16) // SSC0 Transmit Clock +#define AT91C_PB16_TCLK3 (AT91C_PIO_PB16) // Timer Counter 3 external clock input +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_TF0 (AT91C_PIO_PB17) // SSC0 Transmit Frame Sync +#define AT91C_PB17_TCLK4 (AT91C_PIO_PB17) // Timer Counter 4 external clock input +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_TD0 (AT91C_PIO_PB18) // SSC0 Transmit data +#define AT91C_PB18_TIOB4 (AT91C_PIO_PB18) // Timer Counter 4 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_RD0 (AT91C_PIO_PB19) // SSC0 Receive Data +#define AT91C_PB19_TIOB5 (AT91C_PIO_PB19) // Timer Counter 5 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) // SPI 1 Serial Clock +#define AT91C_PB2_TIOA4 (AT91C_PIO_PB2) // Timer Counter 4 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_RK0 (AT91C_PIO_PB20) // SSC0 Receive Clock +#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // Image Sensor Data 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_RF0 (AT91C_PIO_PB21) // SSC0 Receive Frame Sync +#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // Image Sensor Data 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_DSR0 (AT91C_PIO_PB22) // USART 0 Data Set ready +#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // Image Sensor Data 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_DCD0 (AT91C_PIO_PB23) // USART 0 Data Carrier Detect +#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // Image Sensor Data 3 +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_DTR0 (AT91C_PIO_PB24) // USART 0 Data Terminal ready +#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // Image Sensor Data 4 +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_RI0 (AT91C_PIO_PB25) // USART 0 Ring Indicator +#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // Image Sensor Data 5 +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_RTS0 (AT91C_PIO_PB26) // USART 0 Ready To Send +#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // Image Sensor Data 6 +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_CTS0 (AT91C_PIO_PB27) // USART 0 Clear To Send +#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // Image Sensor Data 7 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_RTS1 (AT91C_PIO_PB28) // USART 1 Ready To Send +#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // Image Sensor Data Clock +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_CTS1 (AT91C_PIO_PB29) // USART 1 Clear To Send +#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // Image Sensor Vertical Synchro +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PB3_TIOA5 (AT91C_PIO_PB3) // Timer Counter 5 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK0_0 (AT91C_PIO_PB30) // PMC Programmable Clock Output 0 +#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // Image Sensor Horizontal Synchro +#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31 +#define AT91C_PB31_PCK1_0 (AT91C_PIO_PB31) // PMC Programmable Clock Output 1 +#define AT91C_PB31_ISI_MCK (AT91C_PIO_PB31) // Image Sensor Reference Clock +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_TXD0 (AT91C_PIO_PB4) // USART 0 Transmit Data +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_RXD0 (AT91C_PIO_PB5) // USART 0 Receive Data +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_TXD1 (AT91C_PIO_PB6) // USART 1 Transmit Data +#define AT91C_PB6_TCLK1 (AT91C_PIO_PB6) // Timer Counter 1 external clock input +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_RXD1 (AT91C_PIO_PB7) // USART 1 Receive Data +#define AT91C_PB7_TCLK2 (AT91C_PIO_PB7) // Timer Counter 2 external clock input +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_TXD2 (AT91C_PIO_PB8) // USART 2 Transmit Data +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_RXD2 (AT91C_PIO_PB9) // USART 2 Receive Data +#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 +#define AT91C_PC0_AD0 (AT91C_PIO_PC0) // ADC Analog Input 0 +#define AT91C_PC0_SCK3 (AT91C_PIO_PC0) // USART 3 Serial Clock +#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 +#define AT91C_PC1_AD1 (AT91C_PIO_PC1) // ADC Analog Input 1 +#define AT91C_PC1_PCK0 (AT91C_PIO_PC1) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 +#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) // Address Bus[25] +#define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // USART 3 Clear To Send +#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 +#define AT91C_PC11_NCS2 (AT91C_PIO_PC11) // Chip Select Line 2 +#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 +#define AT91C_PC12_IRQ0 (AT91C_PIO_PC12) // External Interrupt 0 +#define AT91C_PC12_NCS7 (AT91C_PIO_PC12) // Chip Select Line 7 +#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 +#define AT91C_PC13_FIQ (AT91C_PIO_PC13) // AIC Fast Interrupt Input +#define AT91C_PC13_NCS6 (AT91C_PIO_PC13) // Chip Select Line 6 +#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 +#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // Chip Select Line 3 +#define AT91C_PC14_IRQ2 (AT91C_PIO_PC14) // External Interrupt 2 +#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 +#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // External Wait Signal +#define AT91C_PC15_IRQ1 (AT91C_PIO_PC15) // External Interrupt 1 +#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 +#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus[16] +#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 +#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus[17] +#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 +#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus[18] +#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 +#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus[19] +#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 +#define AT91C_PC2_AD2 (AT91C_PIO_PC2) // ADC Analog Input 2 +#define AT91C_PC2_PCK1 (AT91C_PIO_PC2) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 +#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus[20] +#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 +#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus[21] +#define AT91C_PC21_EF100 (AT91C_PIO_PC21) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 +#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus[22] +#define AT91C_PC22_TCLK5 (AT91C_PIO_PC22) // Timer Counter 5 external clock input +#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 +#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus[23] +#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24 +#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus[24] +#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25 +#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus[25] +#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26 +#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus[26] +#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27 +#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus[27] +#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28 +#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus[28] +#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29 +#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus[29] +#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 +#define AT91C_PC3_AD3 (AT91C_PIO_PC3) // ADC Analog Input 3 +#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30 +#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus[30] +#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31 +#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus[31] +#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 +#define AT91C_PC4_A23 (AT91C_PIO_PC4) // Address Bus[23] +#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 +#define AT91C_PC5_A24 (AT91C_PIO_PC5) // Address Bus[24] +#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 +#define AT91C_PC6_TIOB2 (AT91C_PIO_PC6) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // Compact Flash Enable 1 +#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 +#define AT91C_PC7_TIOB1 (AT91C_PIO_PC7) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // Compact Flash Enable 2 +#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 +#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) // Chip Select Line 4 +#define AT91C_PC8_RTS3 (AT91C_PIO_PC8) // USART 3 Ready To Send +#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 +#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) // Chip Select Line 5 +#define AT91C_PC9_TIOB0 (AT91C_PIO_PC9) // Timer Counter 0 Multipurpose Timer I/O Pin B + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE512 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Controller +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C +#define AT91C_ID_ADC ( 5) // ADC +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_US2 ( 8) // USART 2 +#define AT91C_ID_MCI ( 9) // Multimedia Card Interface 0 +#define AT91C_ID_UDP (10) // USB Device Port +#define AT91C_ID_TWI0 (11) // Two-Wire Interface 0 +#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1 +#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0 +#define AT91C_ID_TC0 (17) // Timer Counter 0 +#define AT91C_ID_TC1 (18) // Timer Counter 1 +#define AT91C_ID_TC2 (19) // Timer Counter 2 +#define AT91C_ID_UHP (20) // USB Host Port +#define AT91C_ID_EMAC (21) // Ethernet Mac +#define AT91C_ID_HISI (22) // Image Sensor Interface +#define AT91C_ID_US3 (23) // USART 3 +#define AT91C_ID_US4 (24) // USART 4 +#define AT91C_ID_TWI1 (25) // Two-Wire Interface 1 +#define AT91C_ID_TC3 (26) // Timer Counter 3 +#define AT91C_ID_TC4 (27) // Timer Counter 4 +#define AT91C_ID_TC5 (28) // Timer Counter 5 +#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2) +#define AT91C_ALL_INT (0xFFFE7FFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM9XE512 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFFD00) // (SYS) Base Address +#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFEA00) // (EBI) Base Address +#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFE800) // (HECC) Base Address +#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address +#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address +#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address +#define AT91C_BASE_CCFG (AT91_CAST(AT91PS_CCFG) 0xFFFFEF10) // (CCFG) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address +#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFA00) // (EFC) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFDC000) // (TC3) Base Address +#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFDC040) // (TC4) Base Address +#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFDC080) // (TC5) Base Address +#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address +#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFDC000) // (TCB1) Base Address +#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address +#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address +#define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_TWI0) Base Address +#define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI0) Base Address +#define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_TWI1) Base Address +#define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0xFFFD8000) // (TWI1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address +#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address +#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address +#define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_US3) Base Address +#define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0xFFFD0000) // (US3) Base Address +#define AT91C_BASE_PDC_US4 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_US4) Base Address +#define AT91C_BASE_US4 (AT91_CAST(AT91PS_USART) 0xFFFD4000) // (US4) Base Address +#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address +#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFE0000) // (ADC) Base Address +#define AT91C_BASE_EMACB (AT91_CAST(AT91PS_EMAC) 0xFFFC4000) // (EMACB) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address +#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address +#define AT91C_BASE_HISI (AT91_CAST(AT91PS_ISI) 0xFFFC0000) // (HISI) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE512 +// ***************************************************************************** +// IROM +#define AT91C_IROM (0x00100000) // Internal ROM base address +#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes) +// ISRAM +#define AT91C_ISRAM (0x00300000) // Maximum IRAM Area : 32Kbyte base address +#define AT91C_ISRAM_SIZE (0x00008000) // Maximum IRAM Area : 32Kbyte size in byte (32 Kbytes) +// ISRAM_MIN +#define AT91C_ISRAM_MIN (0x00300000) // Minimun IRAM Area : 32Kbyte base address +#define AT91C_ISRAM_MIN_SIZE (0x00008000) // Minimun IRAM Area : 32Kbyte size in byte (32 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00200000) // Maximum IFLASH Area : 512Kbyte base address +#define AT91C_IFLASH_SIZE (0x00080000) // Maximum IFLASH Area : 512Kbyte size in byte (512 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (512) // Maximum IFLASH Area : 512Kbyte Page Size: 512 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Maximum IFLASH Area : 512Kbyte Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Maximum IFLASH Area : 512Kbyte Number of Pages: 1024 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Maximum IFLASH Area : 512Kbyte Number of Lock Bits: 32 bytes +// EBI_CS0 +#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address +#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes) +// EBI_CS1 +#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address +#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes) +// EBI_SDRAM +#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address +#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes) +// EBI_SDRAM_16BIT +#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address +#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes) +// EBI_SDRAM_32BIT +#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address +#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes) +// EBI_CS2 +#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address +#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes) +// EBI_CS3 +#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address +#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes) +// EBI_SM +#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address +#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes) +// EBI_CS4 +#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address +#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes) +// EBI_CF0 +#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address +#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes) +// EBI_CS5 +#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address +#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes) +// EBI_CF1 +#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address +#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes) +// EBI_CS6 +#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address +#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes) +// EBI_CS7 +#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address +#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes) + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/flash.icf b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/flash.icf new file mode 100644 index 0000000..d1ff040 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/flash.icf @@ -0,0 +1,48 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x200000; +define symbol __ICFEDIT_region_ROM_end__ = 0x27FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x100; +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in ROM_region { readonly }; +place in VEC_region { section .vectors }; +place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sdram.icf b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sdram.icf new file mode 100644 index 0000000..4753f07 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sdram.icf @@ -0,0 +1,46 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x100; +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_SDRAM_start__; +export symbol __ICFEDIT_region_SDRAM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__]; +define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in VEC_region { section .vectors }; +place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sram.icf b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sram.icf new file mode 100644 index 0000000..2544f86 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sram.icf @@ -0,0 +1,36 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x307FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_svcstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_svcstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { section .noinit }; + +place in VEC_region { section .vectors }; +place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP }; + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board.h new file mode 100644 index 0000000..697f61d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board.h @@ -0,0 +1,428 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Definition and functions for using AT91SAM9XE-related features, such +/// has PIO pins, memories, etc. +/// +/// !Usage +/// -# The code for booting the board is provided by board_cstartup.S and +/// board_lowlevel.c. +/// -# For using board PIOs, board characteristics (clock, etc.) and external +/// components, see board.h. +/// -# For manipulating memories (remapping, SDRAM, etc.), see board_memories.h. +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Definition of AT91SAM9XE-EK characteristics, AT91SAM9XE-dependant PIOs and +/// external components interfacing. +/// +/// !Usage +/// -# For operating frequency information, see "SAM9XE-EK - Operating frequencies". +/// -# For using portable PIO definitions, see "SAM9XE-EK - PIO definitions". +/// -# Several USB definitions are included here (see "SAM9XE-EK - USB device"). +/// -# For external components definitions, see "SAM79260-EK - External components". +/// -# For memory-related definitions, see "SAM79260-EK - Memories". +//------------------------------------------------------------------------------ + +#ifndef BOARD_H +#define BOARD_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#if defined(at91sam9xe128) + #include "at91sam9xe128/AT91SAM9XE128.h" +#elif defined(at91sam9xe256) + #include "at91sam9xe256/AT91SAM9XE256.h" +#elif defined(at91sam9xe512) + #include "at91sam9xe512/AT91SAM9XE512.h" +#else + #error Board does not support the specified chip. +#endif + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM9XE-EK - Board Description" +/// This page lists several definition related to the board description. +/// +/// !Definitions +/// - BOARD_NAME + +/// Name of the board. +#define BOARD_NAME "AT91SAM9XE-EK" +/// Board definition. +#define at91sam9xeek +/// Family definition. +#define at91sam9xe +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM9XE-EK - Operating frequencies" +/// This page lists several definition related to the board operating frequency +/// (when using the initialization done by board_lowlevel.c). +/// +/// !Definitions +/// - BOARD_MAINOSC +/// - BOARD_MCK + +/// Frequency of the board main oscillator. +#define BOARD_MAINOSC 18432000 + +/// Master clock frequency (when using board_lowlevel.c). +#define BOARD_MCK ((18432000 * 97 / 9) / 2) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM9XE-EK - USB device" +/// This page lists constants describing several characteristics (controller +/// type, D+ pull-up type, etc.) of the USB device controller of the chip/board. +/// +/// !Constants +/// - BOARD_USB_UDP +/// - BOARD_USB_PULLUP_INTERNAL +/// - BOARD_USB_NUMENDPOINTS +/// - BOARD_USB_ENDPOINTS_MAXPACKETSIZE +/// - BOARD_USB_ENDPOINTS_BANKS +/// - BOARD_USB_BMATTRIBUTES + +/// Chip has a UDP controller. +#define BOARD_USB_UDP + +/// Indicates the D+ pull-up is internal to the USB controller. +#define BOARD_USB_PULLUP_INTERNAL + +/// Number of endpoints in the USB controller. +#define BOARD_USB_NUMENDPOINTS 6 + +/// Returns the maximum packet size of the given endpoint. +#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE(i) ((i >= 4) ? 512 : 64) +#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE_FS 64 + +/// Returns the number of FIFO banks for the given endpoint. +#define BOARD_USB_ENDPOINTS_BANKS(i) (((i == 0) || (i == 3)) ? 1 : 2) + +/// USB attributes configuration descriptor (bus or self powered, remote wakeup) +#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM9XE-EK - PIO definitions" +/// This pages lists all the pio definitions contained in board.h. The constants +/// are named using the following convention: PIN_* for a constant which defines +/// a single Pin instance (but may include several PIOs sharing the same +/// controller), and PINS_* for a list of Pin instances. +/// +/// !DBGU +/// - PINS_DBGU +/// +/// !LEDs +/// - PIN_LED_0 +/// - PIN_LED_1 +/// - PINS_LEDS +/// - LED_POWER +/// - LED_DS1 +/// +/// !Push buttons +/// - PIN_PUSHBUTTON_1 +/// - PIN_PUSHBUTTON_2 +/// - PINS_PUSHBUTTONS +/// - PUSHBUTTON_BP1 +/// - PUSHBUTTON_BP2 +/// +/// !USART0 +/// - PIN_USART0_RXD +/// - PIN_USART0_TXD +/// - PIN_USART0_SCK +/// +/// !SPI0 +/// - PIN_SPI0_MISO +/// - PIN_SPI0_MOSI +/// - PIN_SPI0_SPCK +/// - PINS_SPI0 +/// - PIN_SPI0_NPCS0 +/// - PIN_SPI0_NPCS1 +/// +/// !SSC +/// - PINS_SSC_TX +/// +/// !USB +/// - PIN_USB_VBUS +/// +/// !MCI +/// - PINS_MCI +/// +/// !TWI0 +/// - PINS_TWI0 + +/// List of all DBGU pin definitions. +#define PINS_DBGU {(1<<14) | (1<<15), AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} + +/// LED #0 pin definition. +#define PIN_LED_0 {1 << 9, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/// LED #1 pin definition. +#define PIN_LED_1 {1 << 6, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/// List of all LED definitions. +#define PINS_LEDS PIN_LED_0, PIN_LED_1 +/// Power LED index. +#define LED_POWER 0 +/// DS1 LED index. +#define LED_DS1 1 + +/// Push button #1 pin definition. +#define PIN_PUSHBUTTON_1 {1 << 30, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP} +/// Pusb button #2 pin definition. +#define PIN_PUSHBUTTON_2 {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP} +/// List of all pushbutton pin definitions. +#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 +/// Push button #1 index. +#define PUSHBUTTON_BP1 0 +/// Push button #2 index. +#define PUSHBUTTON_BP2 1 + +/// USART0 TXD pin definition. +#define PIN_USART0_TXD {1 << 4, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/// USART0 RXD pin definition. +#define PIN_USART0_RXD {1 << 5, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/// USART0 RTS pin definition. +#define PIN_USART0_RTS {1 << 26, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/// USART0 CTS pin definition. +#define PIN_USART0_CTS {1 << 27, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/// USART0 SCK pin definition. +#define PIN_USART0_SCK {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// SPI0 MISO pin definition. +#define PIN_SPI0_MISO {1 << 0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP} +/// SPI0 MOSI pin definition. +#define PIN_SPI0_MOSI {1 << 1, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/// SPI0 SPCK pin definition. +#define PIN_SPI0_SPCK {1 << 2, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/// List of SPI0 pin definitions (MISO, MOSI & SPCK). +#define PINS_SPI0 PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK +/// SPI0 chip select 0 pin definition. +#define PIN_SPI0_NPCS0 {AT91C_PA3_SPI0_NPCS0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/// SPI0 chip select 1 pin definition. +#define PIN_SPI0_NPCS1 {AT91C_PC11_SPI0_NPCS1, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} + +/// SSC transmitter pins definition. +#define PINS_SSC_TX {0x00038000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// USB VBus monitoring pin definition. +#define PIN_USB_VBUS {1 << 5, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT} + +/// List of MCI pins definitions. +#define PINS_MCI {0x0000003B, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}, \ + {1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// TWI0 pins definition. +#define PINS_TWI0 {0x01800000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM9XE-EK - External components" +/// This page lists the definitions related to external on-board components +/// located in the board.h file for the AT91SAM9XE-EK. +/// +/// !AT45 Dataflash Card (A) +/// - BOARD_AT45_A_SPI_BASE +/// - BOARD_AT45_A_SPI_ID +/// - BOARD_AT45_A_SPI_PINS +/// - BOARD_AT45_A_SPI +/// - BOARD_AT45_A_NPCS +/// - BOARD_AT45_A_NPCS_PIN +/// +/// !AT45 Dataflash (B) +/// - BOARD_AT45_B_SPI_BASE +/// - BOARD_AT45_B_SPI_ID +/// - BOARD_AT45_B_SPI_PINS +/// - BOARD_AT45_B_SPI +/// - BOARD_AT45_B_NPCS +/// - BOARD_AT45_B_NPCS_PIN +/// +/// !SD Card +/// - BOARD_SD_MCI_BASE +/// - BOARD_SD_MCI_ID +/// - BOARD_SD_PINS +/// - BOARD_SD_SLOT +/// +/// +/// !EMAC +/// - AT91C_BASE_EMAC +/// - BOARD_EMAC_POWER_ALWAYS_ON +/// - BOARD_EMAC_MODE_RMII +/// - BOARD_EMAC_PINS +/// - BOARD_EMAC_PIN_TEST +/// - BOARD_EMAC_PIN_RPTR +/// - BOARD_EMAC_RST_PINS +/// - BOARD_EMAC_RUN_PINS + + +/// Base address of SPI peripheral connected to the dataflash. +#define BOARD_AT45_A_SPI_BASE AT91C_BASE_SPI0 +/// Identifier of SPI peripheral connected to the dataflash. +#define BOARD_AT45_A_SPI_ID AT91C_ID_SPI0 +/// Pins of the SPI peripheral connected to the dataflash. +#define BOARD_AT45_A_SPI_PINS PINS_SPI0 +/// Dataflahs SPI number. +#define BOARD_AT45_A_SPI 0 +/// Chip select connected to the dataflash. +#define BOARD_AT45_A_NPCS 0 +/// Chip select pin connected to the dataflash. +#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS0 + +/// Base address of SPI peripheral connected to the dataflash. +#define BOARD_AT45_B_SPI_BASE AT91C_BASE_SPI0 +/// Identifier of SPI peripheral connected to the dataflash. +#define BOARD_AT45_B_SPI_ID AT91C_ID_SPI0 +/// Pins of the SPI peripheral connected to the dataflash. +#define BOARD_AT45_B_SPI_PINS PINS_SPI0 +/// Dataflahs SPI number. +#define BOARD_AT45_B_SPI 0 +/// Chip select connected to the dataflash. +#define BOARD_AT45_B_NPCS 1 +/// Chip select pin connected to the dataflash. +#define BOARD_AT45_B_NPCS_PIN PIN_SPI0_NPCS1 + +/// Base address of SPI peripheral connected to the serialflash. +#define BOARD_AT26_A_SPI_BASE AT91C_BASE_SPI0 +/// Identifier of SPI peripheral connected to the dataflash. +#define BOARD_AT26_A_SPI_ID AT91C_ID_SPI0 +/// Pins of the SPI peripheral connected to the dataflash. +#define BOARD_AT26_A_SPI_PINS PINS_SPI0 +/// Dataflahs SPI number. +#define BOARD_AT26_A_SPI 0 +/// Chip select connected to the dataflash. +#define BOARD_AT26_A_NPCS 0 +/// Chip select pin connected to the dataflash. +#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS0 + +/// Base address of the MCI peripheral connected to the SD card. +#define BOARD_SD_MCI_BASE AT91C_BASE_MCI +/// Peripheral identifier of the MCI connected to the SD card. +#define BOARD_SD_MCI_ID AT91C_ID_MCI +/// MCI pins that shall be configured to access the SD card. +#define BOARD_SD_PINS PINS_MCI +/// MCI slot to which the SD card is connected to. +#define BOARD_SD_SLOT MCI_SD_SLOTB + +/// Board EMAC base address +#if !defined(AT91C_BASE_EMAC) && defined(AT91C_BASE_EMACB) +#define AT91C_BASE_EMAC AT91C_BASE_EMACB +#endif +/// Board EMAC power control - ALWAYS ON +#define BOARD_EMAC_POWER_ALWAYS_ON +/// Board EMAC work mode - RMII/MII ( 1 / 0 ) +#define BOARD_EMAC_MODE_RMII 1 +/// The PIN list of PIO for EMAC +#define BOARD_EMAC_PINS { ((1<<19)|(1<<13)|(1<<12)|(1<<16)|(1<<15)|(1<<14)\ + |(1<<17)|(1<<18)|(1<<20)|(1<<21)|(1<<7)),\ + AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT},\ + { ((1<<11)|(1<<10)|(1<<26)|(1<<25)|(1<<27)|(1<<22)\ + |(1<<29)|(1<<28)),\ + AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +/// The power up reset latch PIO for PHY +#define BOARD_EMAC_PIN_TEST {(1<<17), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +//#define BOARD_EMAC_PIN_RMII : connected to 3v3 (RMII) +// We force the address +// (1<<14) PHY address 0, (1<<15) PHY address 1 (PIO A, perih A) +// (1<<25) PHY address 2, (1<<26) PHY address 3 (PIO A, perih B) +#define BOARD_EMAC_PINS_PHYAD { ((1<<14)|(1<<15)),\ + AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT},\ + { ((1<<25)|(1<<26)),\ + AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +//#define BOARD_EMAC_PIN_10BT : not connected +#define BOARD_EMAC_PIN_RPTR {(1<<27), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/// The PIN Configure list for EMAC on power up reset +#define BOARD_EMAC_RST_PINS BOARD_EMAC_PINS_PHYAD,\ + BOARD_EMAC_PIN_TEST,\ + BOARD_EMAC_PIN_RPTR +/// The runtime pin configure list for EMAC +#define BOARD_EMAC_RUN_PINS BOARD_EMAC_PINS + +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM9XE-EK - Memories" +/// This page lists definitions related to external on-board memories. +/// +/// !Embedded Flash +/// - BOARD_FLASH_EEFC +/// +/// !SDRAM +/// - BOARD_SDRAM_SIZE +/// - PINS_SDRAM +/// +/// !Nandflash +/// - PINS_NANDFLASH +/// - BOARD_NF_COMMAND_ADDR +/// - BOARD_NF_ADDRESS_ADDR +/// - BOARD_NF_DATA_ADDR +/// - BOARD_NF_CE_PIN +/// - BOARD_NF_RB_PIN + +/// Indicates chip has an Enhanced EFC. +#define BOARD_FLASH_EEFC +/// Address of the IAP function in ROM. +#define BOARD_FLASH_IAP_ADDRESS 0x100008 + +/// Board SDRAM size +#define BOARD_SDRAM_SIZE 0x02000000 +/// List of all SDRAM pins definitions. +#define PINS_SDRAM {0xFFFF0000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} + + +/// Nandflash controller peripheral pins definition. +#define PINS_NANDFLASH BOARD_NF_CE_PIN, BOARD_NF_RB_PIN +/// Nandflash chip enable pin definition. +#define BOARD_NF_CE_PIN {1 << 14, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/// Nandflash ready/busy pin definition. +#define BOARD_NF_RB_PIN {1 << 13, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_PULLUP} +/// Address for transferring command bytes to the nandflash. +#define BOARD_NF_COMMAND_ADDR 0x40400000 +/// Address for transferring address bytes to the nandflash. +#define BOARD_NF_ADDRESS_ADDR 0x40200000 +/// Address for transferring data bytes to the nandflash. +#define BOARD_NF_DATA_ADDR 0x40000000 + +/// Address for transferring command bytes to the norflash. +#define BOARD_NORFLASH_ADDR 0x10000000 +//------------------------------------------------------------------------------ + +#endif //#ifndef BOARD_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_cstartup_iar.s b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_cstartup_iar.s new file mode 100644 index 0000000..5e4e147 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_cstartup_iar.s @@ -0,0 +1,169 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#include "ISR_Support.h" + +/* + IAR startup file for AT91SAM9XE microcontrollers. + */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(2) + SECTION CSTACK:DATA:NOROOT(3) + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#define __ASSEMBLY__ +#include "board.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#define ARM_MODE_ABT 0x17 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 +#define ARM_MODE_SYS 0x1F + +#define I_BIT 0x80 +#define F_BIT 0x40 + +//------------------------------------------------------------------------------ +// Startup routine +//------------------------------------------------------------------------------ + +/* + Exception vectors + */ + SECTION .vectors:CODE:NOROOT(2) + + PUBLIC resetVector + PUBLIC irqHandler + + EXTERN Undefined_Handler + EXTERN vPortYieldProcessor + EXTERN Prefetch_Handler + EXTERN Abort_Handler + EXTERN FIQ_Handler + + ARM + +__iar_init$$done: ; The interrupt vector is not needed + ; until after copy initialization is done + +resetVector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR pc, =resetHandler ; Reset + LDR pc, Undefined_Addr ; Undefined instructions + LDR pc, SWI_Addr ; Software interrupt (SWI/SVC) + LDR pc, Prefetch_Addr ; Prefetch abort + LDR pc, Abort_Addr ; Data abort + B . ; RESERVED + LDR pc, =irqHandler ; IRQ + LDR pc, FIQ_Addr ; FIQ + +Undefined_Addr: DCD Undefined_Handler +SWI_Addr: DCD vPortYieldProcessor +Prefetch_Addr: DCD Prefetch_Handler +Abort_Addr: DCD Abort_Handler +FIQ_Addr: DCD FIQ_Handler + +/* + Handles incoming interrupt requests by branching to the corresponding + handler, as defined in the AIC. Supports interrupt nesting. + */ +irqHandler: + portSAVE_CONTEXT + + /* Write in the IVR to support Protect Mode */ + LDR lr, =AT91C_BASE_AIC + LDR r0, [r14, #AIC_IVR] + STR lr, [r14, #AIC_IVR] + + /* Branch to C portion of the interrupt handler */ + MOV lr, pc + BX r0 + + /* Acknowledge interrupt */ + LDR lr, =AT91C_BASE_AIC + STR lr, [r14, #AIC_EOICR] + + portRESTORE_CONTEXT + +/* + After a reset, execution starts here, the mode is ARM, supervisor + with interrupts disabled. + Initializes the chip and branches to the main() function. + */ + SECTION .cstartup:CODE:NOROOT(2) + + PUBLIC resetHandler + EXTERN LowLevelInit + EXTERN ?main + REQUIRE resetVector + ARM + +resetHandler: + + /* Set pc to actual code location (i.e. not in remap zone) */ + LDR pc, =label + + /* Perform low-level initialization of the chip using LowLevelInit() */ +label: + LDR r0, =LowLevelInit + LDR r4, =SFE(CSTACK) + MOV sp, r4 + MOV lr, pc + BX r0 + + /* Set up the interrupt stack pointer. */ + MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode + LDR sp, =SFE(IRQ_STACK) + + /* Set up the SVC stack pointer. */ + MSR cpsr_c, #ARM_MODE_SVC | F_BIT ; Change the mode + LDR sp, =SFE(CSTACK) + + /* Branch to main() */ + LDR r0, =?main + MOV lr, pc + BX r0 + + /* Loop indefinitely when program is finished */ +loop4: + B loop4 + + END diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_lowlevel.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_lowlevel.c new file mode 100644 index 0000000..711f846 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_lowlevel.c @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "board.h" +#include "board_memories.h" + +//------------------------------------------------------------------------------ +// Local definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM9XE - Oscillator & PLL Parameters" +/// This page lists the parameters which are set for the PLL and main +/// oscillator configuration. +/// +/// !Parameters +/// - BOARD_OSCOUNT +/// - BOARD_CKGR_PLLA +/// - BOARD_PLLACOUNT +/// - BOARD_MULA +/// - BOARD_DIVA +/// - BOARD_CKGR_PLLB +/// - BOARD_PLLBCOUNT +/// - BOARD_MULB +/// - BOARD_DIVB +/// - BOARD_USBDIV +/// - BOARD_PRESCALER + +/// Main oscillator startup time (in number of slow clock ticks). +#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8)) + +/// PLLA frequency range. +#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_2) +/// PLLA startup time (in number of slow clock ticks). +#define BOARD_PLLACOUNT (63 << 8) +/// PLLA MUL value. +#define BOARD_MULA (AT91C_CKGR_MULA & (96 << 16)) +/// PLLA DIV value. +#define BOARD_DIVA (AT91C_CKGR_DIVA & 9) + +/// PLLB frequency range +#define BOARD_CKGR_PLLB AT91C_CKGR_OUTB_1 +/// PLLB startup time (in number of slow clock ticks). +#define BOARD_PLLBCOUNT BOARD_PLLACOUNT +/// PLLB MUL value. +#define BOARD_MULB (124 << 16) +/// PLLB DIV value. +#define BOARD_DIVB 12 + +/// USB PLL divisor value to obtain a 48MHz clock. +#define BOARD_USBDIV AT91C_CKGR_USBDIV_2 +/// Master clock prescaler value. +#define BOARD_PRESCALER AT91C_PMC_MDIV_2 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Local functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Default spurious interrupt handler +//------------------------------------------------------------------------------ +void DefaultSpuriousHandler(void) +{ + while (1); +} + +//------------------------------------------------------------------------------ +/// Default handler for fast interrupt requests. +//------------------------------------------------------------------------------ +void DefaultFiqHandler(void) +{ + while (1); +} + +//------------------------------------------------------------------------------ +/// Default handler for standard interrupt requests. +//------------------------------------------------------------------------------ +void DefaultIrqHandler(void) +{ + while (1); +} + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Performs the low-level initialization of the chip. +//------------------------------------------------------------------------------ +void LowLevelInit(void) +{ + unsigned char i; + + // Set flash wait states + //---------------------- + AT91C_BASE_EFC->EFC_FMR = 6 << 8; + +//#if !defined(sdram) + // Initialize main oscillator + //--------------------------- + AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); + + // Initialize PLLA at 200MHz (198.656) + AT91C_BASE_PMC->PMC_PLLAR = BOARD_CKGR_PLLA + | BOARD_PLLACOUNT + | BOARD_MULA + | BOARD_DIVA; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)); + + // Initialize PLLB for USB usage + AT91C_BASE_PMC->PMC_PLLBR = BOARD_USBDIV + | BOARD_CKGR_PLLB + | BOARD_PLLBCOUNT + | BOARD_MULB + | BOARD_DIVB; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKB)); + + // Wait for the master clock if it was already initialized + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + + // Switch to fast clock + //--------------------- + // Switch to main oscillator + prescaler + AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + + // Switch to PLL + prescaler + AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); +//#endif //#if !defined(sdram) + + // Initialize AIC + //--------------- + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) DefaultFiqHandler; + for (i = 1; i < 31; i++) { + + AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) DefaultIrqHandler; + } + AT91C_BASE_AIC->AIC_SPU = (unsigned int) DefaultSpuriousHandler; + + // Unstack nested interrupts + for (i = 0; i < 8 ; i++) { + + AT91C_BASE_AIC->AIC_EOICR = 0; + } + + // Watchdog initialization + //------------------------ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + // Remap + //------ + BOARD_RemapRam(); + + // Disable RTT and PIT interrupts (potential problem when program A + // configures RTT, then program B wants to use PIT only, interrupts + // from the RTT will still occur since they both use AT91C_ID_SYS) + AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN); + AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.c new file mode 100644 index 0000000..51a5721 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.c @@ -0,0 +1,304 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include + +//------------------------------------------------------------------------------ +// Local macros +//------------------------------------------------------------------------------ + +/// Reads a register value. Useful to add trace information to read accesses. +#define READ(peripheral, register) (peripheral->register) +/// Writes data in a register. Useful to add trace information to write accesses. +#define WRITE(peripheral, register, value) (peripheral->register = value) + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Changes the mapping of the chip so that the remap area mirrors the +/// internal ROM or the EBI CS0 (depending on the BMS input). +//------------------------------------------------------------------------------ +void BOARD_RemapRom(void) +{ + WRITE(AT91C_BASE_MATRIX, MATRIX_MRCR, 0); +} + +//------------------------------------------------------------------------------ +/// Changes the mapping of the chip so that the remap area mirrors the +/// internal RAM. +//------------------------------------------------------------------------------ +void BOARD_RemapRam(void) +{ + WRITE(AT91C_BASE_MATRIX, + MATRIX_MRCR, + (AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D)); +} + +//------------------------------------------------------------------------------ +/// Initialize and configure the external SDRAM. +//------------------------------------------------------------------------------ +void BOARD_ConfigureSdram(void) +{ + volatile unsigned int i; + static const Pin pinsSdram = PINS_SDRAM; + volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM; + + // Enable corresponding PIOs + PIO_Configure(&pinsSdram, 1); + + // Enable EBI chip select for the SDRAM + WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC); + + + // CFG Control Register + WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9 + | AT91C_SDRAMC_NR_13 + | AT91C_SDRAMC_CAS_2 + | AT91C_SDRAMC_NB_4_BANKS + | AT91C_SDRAMC_DBW_32_BITS + | AT91C_SDRAMC_TWR_2 + | AT91C_SDRAMC_TRC_7 + | AT91C_SDRAMC_TRP_2 + | AT91C_SDRAMC_TRCD_2 + | AT91C_SDRAMC_TRAS_5 + | AT91C_SDRAMC_TXSR_8); + + for (i = 0; i < 1000; i++); + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP + pSdram[0] = 0x00000000; + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL + pSdram[0] = 0x00000000; // Perform PRCHG + + for (i = 0; i < 10000; i++); + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR + pSdram[1] = 0x00000001; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR + pSdram[2] = 0x00000002; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR + pSdram[3] = 0x00000003; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR + pSdram[4] = 0x00000004; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR + pSdram[5] = 0x00000005; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR + pSdram[6] = 0x00000006; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR + pSdram[7] = 0x00000007; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR + pSdram[8] = 0x00000008; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation + pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2 + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000); // Set Refresh Timer + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode + pSdram[0] = 0x00000000; // Perform Normal mode +} + +//------------------------------------------------------------------------------ +/// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings). +//------------------------------------------------------------------------------ +void BOARD_ConfigureSdram48MHz(void) +{ + volatile unsigned int i; + static const Pin pinsSdram = PINS_SDRAM; + volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM; + + // Enable corresponding PIOs + PIO_Configure(&pinsSdram, 1); + + // Enable EBI chip select for the SDRAM + WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC); + + + // CFG Control Register + WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9 + | AT91C_SDRAMC_NR_13 + | AT91C_SDRAMC_CAS_2 + | AT91C_SDRAMC_NB_4_BANKS + | AT91C_SDRAMC_DBW_32_BITS + | AT91C_SDRAMC_TWR_1 + | AT91C_SDRAMC_TRC_4 + | AT91C_SDRAMC_TRP_1 + | AT91C_SDRAMC_TRCD_1 + | AT91C_SDRAMC_TRAS_2 + | AT91C_SDRAMC_TXSR_3); + + for (i = 0; i < 1000; i++); + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP + pSdram[0] = 0x00000000; + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL + pSdram[0] = 0x00000000; // Perform PRCHG + + for (i = 0; i < 10000; i++); + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR + pSdram[1] = 0x00000001; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR + pSdram[2] = 0x00000002; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR + pSdram[3] = 0x00000003; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR + pSdram[4] = 0x00000004; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR + pSdram[5] = 0x00000005; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR + pSdram[6] = 0x00000006; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR + pSdram[7] = 0x00000007; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR + pSdram[8] = 0x00000008; // Perform CBR + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation + pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2 + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000); // Set Refresh Timer + + WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode + pSdram[0] = 0x00000000; // Perform Normal mode +} + +//------------------------------------------------------------------------------ +/// Configures the EBI for NandFlash access. Pins must be configured after or +/// before calling this function. +//------------------------------------------------------------------------------ +void BOARD_ConfigureNandFlash(unsigned char busWidth) +{ + // Configure EBI + AT91C_BASE_MATRIX->MATRIX_EBI |= AT91C_MATRIX_CS3A_SM; + + // Configure SMC + AT91C_BASE_SMC->SMC_SETUP3 = 0x00000000; + AT91C_BASE_SMC->SMC_PULSE3 = 0x00030003; + AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005; + AT91C_BASE_SMC->SMC_CTRL3 = 0x00002003; + + if (busWidth == 8) { + + AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS; + } + else if (busWidth == 16) { + + AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS; + } +} + +//------------------------------------------------------------------------------ +/// Configures the EBI for NandFlash access at 48MHz. Pins must be configured +/// after or before calling this function. +//------------------------------------------------------------------------------ +void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth) +{ + // Configure EBI + AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM; + + // Configure SMC + AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001; + AT91C_BASE_SMC->SMC_PULSE3 = 0x04030302; + AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070004; + AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE + | AT91C_SMC_WRITEMODE + | AT91C_SMC_NWAITM_NWAIT_DISABLE + | ((0x1 << 16) & AT91C_SMC_TDF)); + + if (busWidth == 8) { + + AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS; + } + else if (busWidth == 16) { + + AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS; + } +} + +//------------------------------------------------------------------------------ +/// Configures the EBI for NorFlash access at 48MHz. +/// \Param busWidth Bus width +//------------------------------------------------------------------------------ +void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth) +{ + // Configure SMC + AT91C_BASE_SMC->SMC_SETUP0 = 0x00000001; + AT91C_BASE_SMC->SMC_PULSE0 = 0x07070703; + AT91C_BASE_SMC->SMC_CYCLE0 = 0x00070007; + AT91C_BASE_SMC->SMC_CTRL0 = (AT91C_SMC_READMODE + | AT91C_SMC_WRITEMODE + | AT91C_SMC_NWAITM_NWAIT_DISABLE + | ((0x1 << 16) & AT91C_SMC_TDF)); + + if (busWidth == 8) { + + AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS; + } + else if (busWidth == 16) { + + AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS; + } + else if (busWidth == 32) { + + AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS; + } +} + +//------------------------------------------------------------------------------ +/// Set flash wait states in the EFC for 48MHz +//------------------------------------------------------------------------------ +void BOARD_ConfigureFlash48MHz(void) +{ + // Set flash wait states + //---------------------- + AT91C_BASE_EFC->EFC_FMR = 6 << 8; +} diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.h new file mode 100644 index 0000000..8e2a677 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.h @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef BOARD_MEMORIES_H +#define BOARD_MEMORIES_H + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void BOARD_RemapRom(void); + +extern void BOARD_RemapRam(void); + +extern void BOARD_ConfigureSdram(void); + +extern void BOARD_ConfigureSdram48MHz(void); + +extern void BOARD_ConfigureNandFlash(unsigned char busWidth); + +extern void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth); + +extern void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth); + +extern void BOARD_ConfigureFlash48MHz(void); + +#endif //#ifndef BOARD_MEMORIES_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.c new file mode 100644 index 0000000..0cbe25f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.c @@ -0,0 +1,679 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "ac97c.h" +#include +#include +#include +#include +#include + +//------------------------------------------------------------------------------ +// Local constants +//------------------------------------------------------------------------------ + +/// Maximum size of one PDC buffer (in bytes). +#define MAX_PDC_COUNTER 65535 + +//------------------------------------------------------------------------------ +// Local types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// AC97 transfer descriptor. Tracks the status and parameters of a transfer +/// on the AC97 bus. +//------------------------------------------------------------------------------ +typedef struct _Ac97Transfer { + + /// Buffer containing the slots to send. + unsigned char *pBuffer; + /// Total number of samples to send. + volatile unsigned int numSamples; + /// Optional callback function. + Ac97Callback callback; + /// Optional argument to the callback function. + void *pArg; + +} Ac97Transfer; + +//------------------------------------------------------------------------------ +/// AC97 controller driver structure. Monitors the status of transfers on all +/// AC97 channels. +//------------------------------------------------------------------------------ +typedef struct _Ac97c { + + /// List of transfers occuring on each channel. + Ac97Transfer transfers[5]; +} Ac97c; + +//------------------------------------------------------------------------------ +// Local variables +//------------------------------------------------------------------------------ + +/// Global AC97 controller instance. +static Ac97c ac97c; + +//------------------------------------------------------------------------------ +// Local functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the size of one sample (in bytes) on the given channel. +/// \param channel Channel number. +//------------------------------------------------------------------------------ +static unsigned char GetSampleSize(unsigned char channel) +{ + unsigned int size = 0; + + SANITY_CHECK((channel == AC97C_CHANNEL_A) + || (channel == AC97C_CHANNEL_B) + || (channel == AC97C_CHANNEL_CODEC)); + + // Check selected channel + switch (channel) { + case AC97C_CHANNEL_CODEC: return 2; + case AC97C_CHANNEL_A: size = (AT91C_BASE_AC97C->AC97C_CAMR & AT91C_AC97C_SIZE) >> 16; break; + case AC97C_CHANNEL_B: size = (AT91C_BASE_AC97C->AC97C_CBMR & AT91C_AC97C_SIZE) >> 16; break; + } + + // Compute size in bytes given SIZE field + if ((size & 2) != 0) { + + return 2; + } + else { + + return 4; + } +} + +//------------------------------------------------------------------------------ +/// Interrupt service routine for Codec, is invoked by AC97C_Handler. +//------------------------------------------------------------------------------ +static void CodecHandler(void) +{ + unsigned int status; + unsigned int data; + Ac97Transfer *pTransfer = &(ac97c.transfers[AC97C_CODEC_TRANSFER]); + + // Read CODEC status register + status = AT91C_BASE_AC97C->AC97C_COSR; + status &= AT91C_BASE_AC97C->AC97C_COMR; + + // A sample has been transmitted + if (status & AT91C_AC97C_TXRDY) { + + pTransfer->numSamples--; + + // If there are remaining samples, transmit one + if (pTransfer->numSamples > 0) { + + data = *((unsigned int *) pTransfer->pBuffer); + AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY); + AT91C_BASE_AC97C->AC97C_COTHR = data; + + // Check if transfer is read or write + if ((data & AT91C_AC97C_READ) != 0) { + + AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY; + } + else { + + pTransfer->pBuffer += sizeof(unsigned int); + AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY; + } + } + // Transfer finished + else { + + AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT; + AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY); + if (pTransfer->callback) { + + pTransfer->callback(pTransfer->pArg, 0, 0); + } + } + } + + // A sample has been received + if (status & AT91C_AC97C_RXRDY) { + + // Store sample + data = AT91C_BASE_AC97C->AC97C_CORHR; + *((unsigned int *) pTransfer->pBuffer) = data; + + pTransfer->pBuffer += sizeof(unsigned int); + pTransfer->numSamples--; + + // Transfer finished + if (pTransfer->numSamples > 0) { + + data = *((unsigned int *) pTransfer->pBuffer); + AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY); + AT91C_BASE_AC97C->AC97C_COTHR = data; + + // Check if transfer is read or write + if ((data & AT91C_AC97C_READ) != 0) { + + AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY; + } + else { + + pTransfer->pBuffer += sizeof(unsigned int); + AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY; + } + } + else { + + AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT; + AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY); + if (pTransfer->callback) { + + pTransfer->callback(pTransfer->pArg, 0, 0); + } + } + } +} + +//------------------------------------------------------------------------------ +/// Interrupt service routine for channel A, is invoked by AC97C_Handler. +//------------------------------------------------------------------------------ +static void ChannelAHandler(void) +{ + unsigned int status; + Ac97Transfer *pTransmit = &(ac97c.transfers[AC97C_CHANNEL_A_TRANSMIT]); + Ac97Transfer *pReceive = &(ac97c.transfers[AC97C_CHANNEL_A_RECEIVE]); + + // Read channel A status register + status = AT91C_BASE_AC97C->AC97C_CASR; + + // A buffer has been transmitted + if ((status & AT91C_AC97C_ENDTX) != 0) { + + // Update transfer information + if (pTransmit->numSamples > MAX_PDC_COUNTER) { + + pTransmit->numSamples -= MAX_PDC_COUNTER; + } + else { + + pTransmit->numSamples = 0; + } + + // Transmit new buffers if necessary + if (pTransmit->numSamples > MAX_PDC_COUNTER) { + + // Fill next PDC + AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransmit->pBuffer; + if (pTransmit->numSamples > 2 * MAX_PDC_COUNTER) { + + AT91C_BASE_AC97C->AC97C_TNCR = MAX_PDC_COUNTER; + pTransmit->pBuffer += MAX_PDC_COUNTER * GetSampleSize(AC97C_CHANNEL_A); + } + else { + + AT91C_BASE_AC97C->AC97C_TNCR = pTransmit->numSamples - MAX_PDC_COUNTER; + } + } + // Only one buffer remaining + else { + + AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_ENDTX; + AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_TXBUFE; + } + } + + // Transmit completed + if ((status & AT91C_AC97C_TXBUFE) != 0) { + + pTransmit->numSamples = 0; + AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS; + AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_TXBUFE; + if (pTransmit->callback) { + + pTransmit->callback(pTransmit->pArg, 0, 0); + } + } + + // A buffer has been received + if (status & AT91C_AC97C_ENDRX) { + + if (pReceive->numSamples > MAX_PDC_COUNTER) { + + pReceive->numSamples -= MAX_PDC_COUNTER; + } + else { + + pReceive->numSamples = 0; + } + + // Transfer remaining samples + if (pReceive->numSamples > MAX_PDC_COUNTER) { + + AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pReceive->pBuffer; + if (pReceive->numSamples > 2 * MAX_PDC_COUNTER) { + + AT91C_BASE_AC97C->AC97C_RNCR = MAX_PDC_COUNTER; + pReceive->pBuffer += MAX_PDC_COUNTER * GetSampleSize(AC97C_CHANNEL_A); + } + else { + + AT91C_BASE_AC97C->AC97C_RNCR = pReceive->numSamples - MAX_PDC_COUNTER; + } + } + // Only one buffer remaining + else { + + AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_ENDRX); + AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_RXBUFF; + } + } + + // Receive complete + if ((status & AT91C_AC97C_RXBUFF) != 0) { + + pReceive->numSamples = 0; + AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS; + AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_RXBUFF; + if (pReceive->callback) { + + pReceive->callback(pReceive->pArg, 0, 0); + } + } +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// This handler function must be called by the AC97C interrupt service routine. +/// Identifies which event was activated and calls the associated function. +//------------------------------------------------------------------------------ +void AC97C_Handler(void) +{ + unsigned int status; + + // Get the real interrupt source + status = AT91C_BASE_AC97C->AC97C_SR; + status &= AT91C_BASE_AC97C->AC97C_IMR; + + // Check if an event on the codec channel is active + if ((status & AT91C_AC97C_COEVT) != 0) { + + CodecHandler(); + } + // Check if an event on channel A is active + if ((status & AT91C_AC97C_CAEVT) != 0) { + + ChannelAHandler(); + } +} + +//------------------------------------------------------------------------------ +/// Starts a read or write transfer on the given channel +/// \param channel particular channel (AC97C_CHANNEL_A or AC97C_CHANNEL_B). +/// \param pBuffer buffer containing the slots to send. +/// \param numSamples total number of samples to send. +/// \param callback optional callback function. +/// \param pArg optional argument to the callback function. +//------------------------------------------------------------------------------ +unsigned char AC97C_Transfer( + unsigned char channel, + unsigned char *pBuffer, + unsigned int numSamples, + Ac97Callback callback, + void *pArg) +{ + unsigned int size; + unsigned int data; + Ac97Transfer *pTransfer; + + SANITY_CHECK(channel <= 5); + SANITY_CHECK(pBuffer); + SANITY_CHECK(numSamples > 0); + + // Check that no transfer is pending on the channel + pTransfer = &(ac97c.transfers[channel]); + if (pTransfer->numSamples > 0) { + + trace_LOG(trace_WARNING, "-W- AC97C_Transfer: Channel %d is busy\n\r", channel); + return AC97C_ERROR_BUSY; + } + + // Fill transfer information + pTransfer->pBuffer = pBuffer; + pTransfer->numSamples = numSamples; + pTransfer->callback = callback; + pTransfer->pArg = pArg; + + // Transmit or receive over codec channel + if (channel == AC97C_CODEC_TRANSFER) { + + // Send command + data = *((unsigned int *) pTransfer->pBuffer); + AT91C_BASE_AC97C->AC97C_COTHR = data; + + // Check if transfer is read or write + if ((data & AT91C_AC97C_READ) != 0) { + + AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY; + } + else { + + pTransfer->pBuffer += sizeof(unsigned int); + AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY; + } + + // Enable interrupts + AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_COEVT; + } + // Transmit over channel A + else if (channel == AC97C_CHANNEL_A_TRANSMIT) { + + // Disable PDC + AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS; + + // Fill PDC buffers + size = min(pTransfer->numSamples, MAX_PDC_COUNTER); + AT91C_BASE_AC97C->AC97C_TPR = (unsigned int) pTransfer->pBuffer; + AT91C_BASE_AC97C->AC97C_TCR = size; + pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A); + + size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER); + if (size > 0) { + + AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransfer->pBuffer; + AT91C_BASE_AC97C->AC97C_TNCR = size; + pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A); + } + + // Enable interrupts + AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDTX; + AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT; + + // Start transfer + AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTEN; + } + // Receive over channel A + else if (channel == AC97C_CHANNEL_A_RECEIVE) { + + // Disable PDC + AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS; + + // Fill PDC buffers + size = min(pTransfer->numSamples, MAX_PDC_COUNTER); + AT91C_BASE_AC97C->AC97C_RPR = (unsigned int) pTransfer->pBuffer; + AT91C_BASE_AC97C->AC97C_RCR = size; + pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A); + + size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER); + if (size > 0) { + + AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pTransfer->pBuffer; + AT91C_BASE_AC97C->AC97C_RNCR = size; + pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A); + } + + // Enable interrupts + AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDRX; + AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT; + + // Start transfer + AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTEN; + } + + return 0; +} + +//------------------------------------------------------------------------------ +/// Stop read or write transfer on the given channel. +/// \param channel Channel number. +//------------------------------------------------------------------------------ +void AC97C_CancelTransfer(unsigned char channel) +{ + unsigned int size = 0; + Ac97Transfer *pTransfer; + + SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT); + + // Save remaining size + pTransfer = &(ac97c.transfers[channel]); + size = pTransfer->numSamples; + pTransfer->numSamples = 0; + + // Stop PDC + if (channel == AC97C_CHANNEL_A_TRANSMIT) { + + AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS; + size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_TCR; + } + if (channel == AC97C_CHANNEL_A_RECEIVE) { + + AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS; + size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_RCR; + } + + // Invoke callback if provided + if (pTransfer->callback) { + + pTransfer->callback(pTransfer->pArg, AC97C_ERROR_STOPPED, size); + } +} + +//------------------------------------------------------------------------------ +/// Initializes the AC97 controller. +//------------------------------------------------------------------------------ +void AC97C_Configure(void) +{ + unsigned char channel; + + // Enable the AC97 controller peripheral clock + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_AC97C); + + // Enable the peripheral and variable rate adjustment + AT91C_BASE_AC97C->AC97C_MR = AT91C_AC97C_ENA | AT91C_AC97C_VRA; + + // Unassigns all input & output slots + AC97C_AssignInputSlots(0, 0xFFFF); + AC97C_AssignOutputSlots(0, 0xFFFF); + + // Install the AC97C interrupt handler + AT91C_BASE_AC97C->AC97C_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_AC97C, 0, AC97C_Handler); + AIC_EnableIT(AT91C_ID_AC97C); + + // Disable PDC transfers + AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS; + + // Clear channel transfers + for (channel = 0; channel < AC97C_CHANNEL_B_TRANSMIT; channel++) { + + ac97c.transfers[channel].numSamples = 0; + } +} + +//------------------------------------------------------------------------------ +/// Configures the desired channel with the given value. +/// \param channel Channel number. +/// \param cfg Configuration value. +//------------------------------------------------------------------------------ +void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg) +{ + SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B)); + + if (channel == AC97C_CHANNEL_A) { + + AT91C_BASE_AC97C->AC97C_CAMR = cfg; + } + else { + + AT91C_BASE_AC97C->AC97C_CBMR = cfg; + } +} + +//------------------------------------------------------------------------------ +/// Assigns the desired input slots to a particular channel. +/// \param channel Channel number (or 0 to unassign slots). +/// \param slots Bitfield value of slots to assign. +//------------------------------------------------------------------------------ +void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots) +{ + unsigned int value; + unsigned int i; + + SANITY_CHECK(channel <= AC97C_CHANNEL_B); + + // Assign all slots + slots >>= 3; + for (i = 3; i < 15; i++) { + + // Check if slots is selected + if (slots & 1) { + + value = AT91C_BASE_AC97C->AC97C_ICA; + value &= ~(0x07 << ((i - 3) * 3)); + value |= channel << ((i - 3) * 3); + AT91C_BASE_AC97C->AC97C_ICA = value; + } + slots >>= 1; + } +} + +//------------------------------------------------------------------------------ +/// Assigns the desired output slots to a particular channel. +/// \param channel Channel number (or 0 to unassign slots). +/// \param slots Bitfield value of slots to assign. +//------------------------------------------------------------------------------ +void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots) +{ + unsigned int value; + unsigned int i; + + SANITY_CHECK(channel <= AC97C_CHANNEL_B); + + // Assign all slots + slots >>= 3; + for (i = 3; i < 15; i++) { + + // Check if slots is selected + if (slots & 1) { + + value = AT91C_BASE_AC97C->AC97C_OCA; + value &= ~(0x07 << ((i - 3) * 3)); + value |= channel << ((i - 3) * 3); + AT91C_BASE_AC97C->AC97C_OCA = value; + } + slots >>= 1; + } +} + +//------------------------------------------------------------------------------ +/// Returns 1 if no transfer is currently pending on the given channel; +/// otherwise, returns 0. +/// \param channel Channel number. +//------------------------------------------------------------------------------ +unsigned char AC97C_IsFinished(unsigned char channel) +{ + SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT); + + if (ac97c.transfers[channel].numSamples > 0) { + + return 0; + } + else { + + return 1; + } +} + +//------------------------------------------------------------------------------ +/// Convenience function for synchronously sending commands to the codec. +/// \param address Register address. +/// \param data Command data. +//------------------------------------------------------------------------------ +void AC97C_WriteCodec(unsigned char address, unsigned short data) +{ + unsigned int sample; + + sample = (address << 16) | data; + AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0); + while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER)); +} + +//------------------------------------------------------------------------------ +/// Convenience function for receiving data from the AC97 codec. +/// \param address Register address. +//------------------------------------------------------------------------------ +unsigned short AC97C_ReadCodec(unsigned char address) +{ + unsigned int sample; + + sample = AT91C_AC97C_READ | (address << 16); + AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0); + while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER)); + + return sample; +} + +//------------------------------------------------------------------------------ +/// Sets the size in bits of one sample on the given channel. +/// \param channel Channel number. +/// \param size Size of one sample in bits (10, 16, 18 or 24). +//------------------------------------------------------------------------------ +void AC97C_SetChannelSize(unsigned char channel, unsigned char size) +{ + unsigned int bits = 0; + + SANITY_CHECK((size == 10) || (size == 16) || (size == 18) || (size == 24)); + SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B)); + + switch (size) { + + case 10 : bits = AT91C_AC97C_SIZE_10_BITS; break; + case 16 : bits = AT91C_AC97C_SIZE_16_BITS; break; + case 18 : bits = AT91C_AC97C_SIZE_18_BITS; break; + case 20 : bits = AT91C_AC97C_SIZE_20_BITS; break; + } + + if (channel == AC97C_CHANNEL_A) { + + AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_SIZE); + AT91C_BASE_AC97C->AC97C_CAMR |= bits; + } + else { + + AT91C_BASE_AC97C->AC97C_CBMR &= ~(AT91C_AC97C_SIZE); + AT91C_BASE_AC97C->AC97C_CBMR |= bits; + } +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.h new file mode 100644 index 0000000..77a7925 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.h @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +#ifndef AC97C_H +#define AC97C_H + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + +/// The channel is already busy with a transfer. +#define AC97C_ERROR_BUSY 1 +/// The transfer has been stopped by the user. +#define AC97C_ERROR_STOPPED 2 + +/// Codec channel index. +#define AC97C_CHANNEL_CODEC 0 +/// Channel A index. +#define AC97C_CHANNEL_A 1 +/// Channel B index. +#define AC97C_CHANNEL_B 2 + +/// Codec transmit/receive transfer index. +#define AC97C_CODEC_TRANSFER 0 +/// Channel A receive transfer index. +#define AC97C_CHANNEL_A_RECEIVE 1 +/// Channel A transmit transfer index. +#define AC97C_CHANNEL_A_TRANSMIT 2 +/// Channel B receive transfer index. +#define AC97C_CHANNEL_B_RECEIVE 3 +/// Channel B transmit transfer index. +#define AC97C_CHANNEL_B_TRANSMIT 4 + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +/// AC97C transfer callback function. +typedef void (*Ac97Callback)(void *pArg, + unsigned char status, + unsigned int remaining); + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void AC97C_Configure(); + +extern void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg); + +extern void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots); + +extern void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots); + +extern unsigned char AC97C_Transfer( + unsigned char channel, + unsigned char *pBuffer, + unsigned int numSamples, + Ac97Callback callback, + void *pArg); + +extern unsigned char AC97C_IsFinished(unsigned char channel); + +extern void AC97C_WriteCodec(unsigned char address, unsigned short data); + +extern unsigned short AC97C_ReadCodec(unsigned char address); + +extern void AC97C_SetChannelSize(unsigned char channel, unsigned char size); + +extern void AC97C_CancelTransfer(unsigned char channel); + +#endif //#ifndef AC97C_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aes/aes.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aes/aes.c new file mode 100644 index 0000000..82586a2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aes/aes.c @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef trace_LEVEL + #define trace_LEVEL 1 +#endif + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "aes.h" +#include +#include +#include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures the AES peripheral to encrypt/decrypt, start mode (manual, auto, +/// PDC) and operating mode (ECB, CBC, OFB, CFB, CTR). +/// \param cipher Indicates if the peripheral should encrypt or decrypt data. +/// \param smode Start mode. +/// \param opmode Operating mode. +//------------------------------------------------------------------------------ +void AES_Configure( + unsigned char cipher, + unsigned int smode, + unsigned int opmode) +{ + trace_LOG(trace_DEBUG, "-D- AES_Configure()\n\r"); + SANITY_CHECK((cipher & 0xFFFFFFFE) == 0); + SANITY_CHECK((smode & 0xFFFFFCFF) == 0); + SANITY_CHECK((opmode & 0xFFFF8FFF) == 0); + + // Reset the peripheral first + AT91C_BASE_AES->AES_CR = AT91C_AES_SWRST; + + // Configure mode register + AT91C_BASE_AES->AES_MR = cipher | smode | opmode; +} + +//------------------------------------------------------------------------------ +/// Sets the key used by the AES algorithm to cipher the plain text or +/// decipher the encrypted text. +/// \param pKey Pointer to a 16-bytes cipher key. +//------------------------------------------------------------------------------ +void AES_SetKey(const unsigned int *pKey) +{ + trace_LOG(trace_DEBUG, "-D- AES_SetKey()\n\r"); + SANITY_CHECK(pKey); + + AT91C_BASE_AES->AES_KEYWxR[0] = pKey[0]; + AT91C_BASE_AES->AES_KEYWxR[1] = pKey[1]; + AT91C_BASE_AES->AES_KEYWxR[2] = pKey[2]; + AT91C_BASE_AES->AES_KEYWxR[3] = pKey[3]; +} + +//------------------------------------------------------------------------------ +/// Sets the initialization vector that is used to encrypt the plain text or +/// decrypt the cipher text in chained block modes (CBC, CFB, OFB & CTR). +/// \param pVector Pointer to a 16-bytes initialization vector. +//------------------------------------------------------------------------------ +void AES_SetVector(const unsigned int *pVector) +{ + trace_LOG(trace_DEBUG, "-D- AES_SetVector()\n\r"); + SANITY_CHECK(pVector); + + AT91C_BASE_AES->AES_IVxR[0] = pVector[0]; + AT91C_BASE_AES->AES_IVxR[1] = pVector[1]; + AT91C_BASE_AES->AES_IVxR[2] = pVector[2]; + AT91C_BASE_AES->AES_IVxR[3] = pVector[3]; +} + +//------------------------------------------------------------------------------ +/// Sets the input data of the AES algorithm (i.e. plain text in cipher mode, +/// ciphered text in decipher mode). If auto mode is active, the encryption is +/// started automatically after writing the last word. +/// \param pData Pointer to the 16-bytes data to cipher/decipher. +//------------------------------------------------------------------------------ +void AES_SetInputData(const unsigned int *pData) +{ + trace_LOG(trace_DEBUG, "-D- AES_SetInputData()\n\r"); + SANITY_CHECK(pData); + + AT91C_BASE_AES->AES_IDATAxR[0] = pData[0]; + AT91C_BASE_AES->AES_IDATAxR[1] = pData[1]; + AT91C_BASE_AES->AES_IDATAxR[2] = pData[2]; + AT91C_BASE_AES->AES_IDATAxR[3] = pData[3]; +} + +//------------------------------------------------------------------------------ +/// Stores the result of the last AES operation (encrypt/decrypt) in the +/// provided buffer. +/// \param pData Pointer to a 16-bytes buffer. +//------------------------------------------------------------------------------ +void AES_GetOutputData(unsigned int *pData) +{ + trace_LOG(trace_DEBUG, "-D- AES_GetOutputData()\n\r"); + SANITY_CHECK(pData); + + pData[0] = AT91C_BASE_AES->AES_ODATAxR[0]; + pData[1] = AT91C_BASE_AES->AES_ODATAxR[1]; + pData[2] = AT91C_BASE_AES->AES_ODATAxR[2]; + pData[3] = AT91C_BASE_AES->AES_ODATAxR[3]; +} + +//------------------------------------------------------------------------------ +/// Sets the input buffer to use when in PDC mode. +/// \param pInput Pointer to the input buffer. +//------------------------------------------------------------------------------ +void AES_SetInputBuffer(const unsigned int *pInput) +{ + trace_LOG(trace_DEBUG, "-D- AES_SetInputBuffer()\n\r"); + SANITY_CHECK(pInput); + + AT91C_BASE_AES->AES_TPR = (unsigned int) pInput; + AT91C_BASE_AES->AES_TCR = 4; +} + +//------------------------------------------------------------------------------ +/// Sets the output buffer to use when in PDC mode. +/// \param pOutput Pointer to the output buffer. +//------------------------------------------------------------------------------ +void AES_SetOutputBuffer(unsigned int *pOutput) +{ + trace_LOG(trace_DEBUG, "-D- AES_SetOutputBuffer()\n\r"); + SANITY_CHECK(pOutput); + + AT91C_BASE_AES->AES_RPR = (unsigned int) pOutput; + AT91C_BASE_AES->AES_RCR = 4; +} + +//------------------------------------------------------------------------------ +/// Starts the encryption/decryption process when in manual or PDC mode. In +/// manual mode, the key and input data must have been entered using +/// AES_SetKey() and AES_SetInputData(). In PDC mode, the key, input & output +/// buffer must have been set using AES_SetKey(), AES_SetInputBuffer() and +/// AES_SetOutputBuffer(). +//------------------------------------------------------------------------------ +void AES_Start(void) +{ + trace_LOG(trace_DEBUG, "AES_Start()\n\r"); + SANITY_CHECK(((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL) + || ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_PDC)); + + // Manual mode + if ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL) { + + AT91C_BASE_AES->AES_CR = AT91C_AES_START; + } + // PDC + else { + + AT91C_BASE_AES->AES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; + } +} + +//------------------------------------------------------------------------------ +/// Returns the current value of the AES interrupt status register. +//------------------------------------------------------------------------------ +unsigned int AES_GetStatus(void) +{ + trace_LOG(trace_DEBUG, "-D- AES_GetStatus()\n\r"); + + return AT91C_BASE_AES->AES_ISR; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aes/aes.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aes/aes.h new file mode 100644 index 0000000..0f14f44 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aes/aes.h @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef AES_H +#define AES_H + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void AES_Configure( + unsigned char cipher, + unsigned int smode, + unsigned int opmode); + +extern void AES_SetKey(const unsigned int *pKey); + +extern void AES_SetVector(const unsigned int *pVector); + +extern void AES_SetInputData(const unsigned int *pData); + +extern void AES_GetOutputData(unsigned int *pData); + +extern void AES_SetInputBuffer(const unsigned int *pInput); + +extern void AES_SetOutputBuffer(unsigned int *pOutput); + +extern void AES_Start(void); + +extern unsigned int AES_GetStatus(void); + +#endif //#ifndef AES_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aic/aic.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aic/aic.c new file mode 100644 index 0000000..ab6b7b2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aic/aic.c @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "aic.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures the interrupt associated with the given source, using the +/// specified mode and interrupt handler. +/// \param source Interrupt source to configure. +/// \param mode Triggering mode of the interrupt. +/// \param handler Interrupt handler function. +//------------------------------------------------------------------------------ +void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )) +{ + // Disable the interrupt first + AT91C_BASE_AIC->AIC_IDCR = 1 << source; + + // Configure mode and handler + AT91C_BASE_AIC->AIC_SMR[source] = mode; + AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler; + + // Clear interrupt + AT91C_BASE_AIC->AIC_ICCR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Enables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_EnableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IECR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Disables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_DisableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IDCR = 1 << source; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aic/aic.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aic/aic.h new file mode 100644 index 0000000..64d1aef --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/aic/aic.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Methods and definitions for configuring interrupts using the Advanced +/// Interrupt Controller (AIC). +/// +/// !Usage +/// -# Configure an interrupt source using AIC_ConfigureIT +/// -# Enable or disable interrupt generation of a particular source with +/// AIC_EnableIT and AIC_DisableIT. +//------------------------------------------------------------------------------ + +#ifndef AIC_H +#define AIC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL + /// Redefinition of missing constant. + #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE +#endif + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )); + +extern void AIC_EnableIT(unsigned int source); + +extern void AIC_DisableIT(unsigned int source); + +#endif //#ifndef AIC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/can/can.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/can/can.c new file mode 100644 index 0000000..18ab19d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/can/can.c @@ -0,0 +1,1042 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include +#include +#include +#include "can.h" + +//------------------------------------------------------------------------------ +// Local definitions +//------------------------------------------------------------------------------ +// CAN state +#define CAN_DISABLED 0 +#define CAN_HALTED 1 +#define CAN_IDLE 2 +#define CAN_SENDING 3 +#define CAN_RECEIVING 4 + +// MOT: Mailbox Object Type +#define CAN_MOT_DISABLE 0 // Mailbox is disabled +#define CAN_MOT_RECEPT 1 // Reception Mailbox +#define CAN_MOT_RECEPT_OW 2 // Reception mailbox with overwrite +#define CAN_MOT_TRANSMIT 3 // Transmit mailbox +#define CAN_MOT_CONSUMER 4 // Consumer mailbox +#define CAN_MOT_PRODUCER 5 // Producer mailbox + +//------------------------------------------------------------------------------ +// Local variables +//------------------------------------------------------------------------------ +#if defined (PINS_CAN_TRANSCEIVER_TXD) +static const Pin pins_can_transceiver_txd[] = {PINS_CAN_TRANSCEIVER_TXD}; +#endif +#if defined (PINS_CAN_TRANSCEIVER_RXD) +static const Pin pins_can_transceiver_rxd[] = {PINS_CAN_TRANSCEIVER_RXD}; +#endif +static const Pin pin_can_transceiver_rs = PIN_CAN_TRANSCEIVER_RS; +#if defined (PIN_CAN_TRANSCEIVER_RXEN) +static const Pin pin_can_transceiver_rxen = PIN_CAN_TRANSCEIVER_RXEN; +#endif + +static CanTransfer *pCAN0Transfer=NULL; +#ifdef AT91C_BASE_CAN1 +static CanTransfer *pCAN1Transfer=NULL; +#endif + +//------------------------------------------------------------------------------ +// Local functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// CAN Error Detection +/// \param status error type +/// \param can_number can nulber +//------------------------------------------------------------------------------ +static void CAN_ErrorHandling( unsigned int status, unsigned char can_number) +{ + if( (status&AT91C_CAN_ERRA) == AT91C_CAN_ERRA) { + trace_LOG( trace_ERROR, "-E- (CAN) CAN is in active Error Active mode\n\r"); + } + else if( (status&AT91C_CAN_ERRP) == AT91C_CAN_ERRP) { + trace_LOG( trace_ERROR, "-E- (CAN) CAN is in Error Passive mode\n\r"); + } + else if( (status&AT91C_CAN_BOFF) == AT91C_CAN_BOFF) { + trace_LOG( trace_ERROR, "-E- (CAN) CAN is in Buff Off mode\n\r"); + // CAN reset + trace_LOG( trace_ERROR, "-E- (CAN) CAN%d reset\n\r", can_number); + // CAN Controller Disable + if (can_number == 0) { + AT91C_BASE_CAN0->CAN_MR &= ~AT91C_CAN_CANEN; + // CAN Controller Enable + AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_CANEN; + } +#ifdef AT91C_BASE_CAN1 + else if (can_number == 1) { + AT91C_BASE_CAN1->CAN_MR &= ~AT91C_CAN_CANEN; + // CAN Controller Enable + AT91C_BASE_CAN1->CAN_MR |= AT91C_CAN_CANEN; + } +#endif + } + + // Error for Frame dataframe + // CRC error + if( (status&AT91C_CAN_CERR) == AT91C_CAN_CERR) { + trace_LOG( trace_ERROR, "-E- (CAN) CRC Error\n\r"); + } + // Bit-stuffing error + else if( (status&AT91C_CAN_SERR) == AT91C_CAN_SERR) { + trace_LOG( trace_ERROR, "-E- (CAN) Stuffing Error\n\r"); + } + // Bit error + else if( (status&AT91C_CAN_BERR) == AT91C_CAN_BERR) { + trace_LOG( trace_ERROR, "-E- (CAN) Bit Error\n\r"); + } + // Form error + else if( (status&AT91C_CAN_FERR) == AT91C_CAN_FERR) { + trace_LOG( trace_ERROR, "-E- (CAN) Form Error\n\r"); + } + // Acknowledgment error + else if( (status&AT91C_CAN_AERR) == AT91C_CAN_AERR) { + trace_LOG( trace_ERROR, "-E- (CAN) Acknowledgment Error\n\r"); + } + + // Error interrupt handler + // Represent the current status of the CAN bus and are not latched. + // See CAN, par. Error Interrupt Handler + // AT91C_CAN_WARN + // AT91C_CAN_ERRA +} + +//------------------------------------------------------------------------------ +// Generic CAN Interrupt handler +/// \param can_number can nulber +//------------------------------------------------------------------------------ +static void CAN_Handler( unsigned char can_number ) +{ + AT91PS_CAN base_can; + AT91PS_CAN_MB CAN_Mailbox; + + unsigned int status; + unsigned int can_msr; + unsigned int* pCan_mcr; + unsigned int message_mode; + unsigned char numMailbox; + unsigned char state0; + unsigned char state1; + + if( can_number == 0 ) { + base_can = AT91C_BASE_CAN0; + CAN_Mailbox = AT91C_BASE_CAN0_MB0; + state0 = pCAN0Transfer->state; + } +#ifdef AT91C_BASE_CAN1 + else { + base_can = AT91C_BASE_CAN1; + CAN_Mailbox = AT91C_BASE_CAN1_MB0; + state1 = pCAN1Transfer->state; + } +#endif + status = (base_can->CAN_SR) & (base_can->CAN_IMR); + base_can->CAN_IDR = status; + + trace_LOG( trace_DEBUG, "CAN0 status=0x%X\n\r", status); + if(status & AT91C_CAN_WAKEUP) { + if( can_number == 0 ) { + pCAN0Transfer->test_can = AT91C_TEST_OK; + pCAN0Transfer->state = CAN_IDLE; + } +#ifdef AT91C_BASE_CAN1 + else { + pCAN1Transfer->test_can = AT91C_TEST_OK; + pCAN1Transfer->state = CAN_IDLE; + } +#endif + } + // Mailbox event ? + else if ((status&0x0000FFFF) != 0) { + trace_LOG( trace_DEBUG, "Mailbox event\n\r"); + + // Handle Mailbox interrupts + for (numMailbox = 0; numMailbox < NUM_MAILBOX_MAX; numMailbox++) { + + can_msr = *(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x10+(0x20*numMailbox))); + if ((AT91C_CAN_MRDY & can_msr) == AT91C_CAN_MRDY) { + // Mailbox object type + message_mode = ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x00+(0x20*numMailbox))))>>24)&0x7; + trace_LOG( trace_DEBUG, "message_mode 0x%X\n\r", message_mode); + trace_LOG( trace_DEBUG, "numMailbox 0x%X\n\r", numMailbox); + + if( message_mode == 0 ) { + trace_LOG( trace_ERROR, "-E-Error in MOT\n\r"); + } + else if( ( message_mode == CAN_MOT_RECEPT ) + || ( message_mode == CAN_MOT_RECEPT_OW ) + || ( message_mode == CAN_MOT_PRODUCER ) ) { + trace_LOG( trace_DEBUG, "Mailbox is in RECEPTION\n\r"); + trace_LOG( trace_DEBUG, "Length 0x%X\n\r", (can_msr>>16)&0xF); + trace_LOG( trace_DEBUG, "CAN_MB_MID 0x%X\n\r", ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x08+(0x20*numMailbox)))&AT91C_CAN_MIDvA)>>18)); + + trace_LOG( trace_DEBUG, "can_number %d\n\r", can_number); + if( can_number == 0 ) { + //CAN_MB_MDLx + pCAN0Transfer->data_low_reg = + (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox)))); + //CAN_MB_MDHx + pCAN0Transfer->data_high_reg = + (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox)))); + pCAN0Transfer->size = (can_msr>>16)&0xF; + pCAN0Transfer->mailbox_number = numMailbox; + state0 = CAN_IDLE; + } +#ifdef AT91C_BASE_CAN1 + else { + //CAN_MB_MDLx + pCAN1Transfer->data_low_reg = + (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox)))); + //CAN_MB_MDHx + pCAN1Transfer->data_high_reg = + (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox)))); + pCAN1Transfer->size = (can_msr>>16)&0xF; + pCAN1Transfer->mailbox_number = numMailbox; + state1 = CAN_IDLE; + } +#endif + // Message Data has been received + pCan_mcr = (unsigned int*)((unsigned int)CAN_Mailbox+0x1C+(0x20*numMailbox)); + *pCan_mcr = AT91C_CAN_MTCR; + + } + else { + trace_LOG( trace_DEBUG, "Mailbox is in TRANSMIT\n\r"); + trace_LOG( trace_DEBUG, "Length 0x%X\n\r", (can_msr>>16)&0xF); + trace_LOG( trace_DEBUG, "can_number %d\n\r", can_number); + if( can_number == 0 ) { + state0 = CAN_IDLE; + } + else { + state1 = CAN_IDLE; + } + } + } + } + if( can_number == 0 ) { + pCAN0Transfer->state = state0; + } +#ifdef AT91C_BASE_CAN1 + else { + pCAN1Transfer->state = state1; + } +#endif + } + if ((status&0xFFCF0000) != 0) { + CAN_ErrorHandling(status, 0); + } +} + +//------------------------------------------------------------------------------ +/// CAN 0 Interrupt handler +//------------------------------------------------------------------------------ +static void CAN0_Handler(void) +{ + CAN_Handler( 0 ); +} + +//------------------------------------------------------------------------------ +/// CAN 1 Interrupt handler +//------------------------------------------------------------------------------ +#if defined AT91C_BASE_CAN1 +static void CAN1_Handler(void) +{ + CAN_Handler( 1 ); +} +#endif + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configure the corresponding mailbox +/// \param pTransfer can transfer structure +//------------------------------------------------------------------------------ +void CAN_InitMailboxRegisters( CanTransfer *pTransfer ) +{ + AT91PS_CAN base_can; + AT91PS_CAN_MB CAN_Mailbox; + + if( pTransfer->can_number == 0 ) { + base_can = AT91C_BASE_CAN0; + CAN_Mailbox = AT91C_BASE_CAN0_MB0; + } +#ifdef AT91C_BASE_CAN1 + else { + base_can = AT91C_BASE_CAN1; + CAN_Mailbox = AT91C_BASE_CAN1_MB0; + } +#endif + CAN_Mailbox = (AT91PS_CAN_MB)((unsigned int)CAN_Mailbox+(unsigned int)(0x20*pTransfer->mailbox_number)); + + pTransfer->mailbox_in_use |= 1<<(pTransfer->mailbox_number); + // MailBox Control Register + CAN_Mailbox->CAN_MB_MCR = 0x0; + // MailBox Mode Register + CAN_Mailbox->CAN_MB_MMR = 0x00; + // CAN Message Acceptance Mask Register + CAN_Mailbox->CAN_MB_MAM = pTransfer->acceptance_mask_reg; + // MailBox ID Register + // Disable the mailbox before writing to CAN_MIDx registers + if( pTransfer->identifier != 0 ) { + CAN_Mailbox->CAN_MB_MAM |= AT91C_CAN_MIDE; + CAN_Mailbox->CAN_MB_MID = pTransfer->identifier; + } + else { + CAN_Mailbox->CAN_MB_MAM &= ~AT91C_CAN_MIDE; + } + // MailBox Mode Register + CAN_Mailbox->CAN_MB_MMR = pTransfer->mode_reg; + // MailBox Data Low Register + CAN_Mailbox->CAN_MB_MDL = pTransfer->data_low_reg; + // MailBox Data High Register + CAN_Mailbox->CAN_MB_MDH = pTransfer->data_high_reg; + // MailBox Control Register + CAN_Mailbox->CAN_MB_MCR = pTransfer->control_reg; +} + +//------------------------------------------------------------------------------ +/// Reset the MBx +//------------------------------------------------------------------------------ +void CAN_ResetAllMailbox( void ) +{ + unsigned char i; + +#if defined (AT91C_BASE_CAN0_MB0) + CAN_ResetTransfer( pCAN0Transfer ); + for( i=0; i<8; i++ ) { + pCAN0Transfer->can_number = 0; + pCAN0Transfer->mailbox_number = i; + pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS; + pCAN0Transfer->acceptance_mask_reg = 0; + pCAN0Transfer->identifier = 0; + pCAN0Transfer->data_low_reg = 0x00000000; + pCAN0Transfer->data_high_reg = 0x00000000; + pCAN0Transfer->control_reg = 0x00000000; + CAN_InitMailboxRegisters( pCAN0Transfer ); + } +#endif +#if defined (AT91C_BASE_CAN0_MB8) + for( i=0; i<8; i++ ) { + pCAN0Transfer->can_number = 0; + pCAN0Transfer->mailbox_number = i+8; + pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS; + pCAN0Transfer->acceptance_mask_reg = 0; + pCAN0Transfer->identifier = 0; + pCAN0Transfer->data_low_reg = 0x00000000; + pCAN0Transfer->data_high_reg = 0x00000000; + pCAN0Transfer->control_reg = 0x00000000; + CAN_InitMailboxRegisters( pCAN0Transfer ); + } +#endif + +#if defined (AT91C_BASE_CAN1_MB0) + if( pCAN1Transfer != NULL ) { + CAN_ResetTransfer( pCAN1Transfer ); + for( i=0; i<8; i++ ) { + pCAN1Transfer->can_number = 1; + pCAN1Transfer->mailbox_number = i; + pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS; + pCAN1Transfer->acceptance_mask_reg = 0; + pCAN1Transfer->identifier = 0; + pCAN1Transfer->data_low_reg = 0x00000000; + pCAN1Transfer->data_high_reg = 0x00000000; + pCAN1Transfer->control_reg = 0x00000000; + CAN_InitMailboxRegisters( pCAN1Transfer ); + } + } +#endif +#if defined (AT91C_BASE_CAN1_MB8) + if( pCAN1Transfer != NULL ) { + for( i=0; i<8; i++ ) { + pCAN1Transfer->can_number = 1; + pCAN1Transfer->mailbox_number = i+8; + pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS; + pCAN1Transfer->acceptance_mask_reg = 0; + pCAN1Transfer->identifier = 0; + pCAN1Transfer->data_low_reg = 0x00000000; + pCAN1Transfer->data_high_reg = 0x00000000; + pCAN1Transfer->control_reg = 0x00000000; + CAN_InitMailboxRegisters( pCAN1Transfer ); + } + } +#endif + +} + +//------------------------------------------------------------------------------ +/// CAN reset Transfer descriptor +/// \param pTransfer can transfer structure +//------------------------------------------------------------------------------ +void CAN_ResetTransfer( CanTransfer *pTransfer ) +{ + pTransfer->state = CAN_IDLE; + pTransfer->can_number = 0; + pTransfer->mailbox_number = 0; + pTransfer->test_can = 0; + pTransfer->mode_reg = 0; + pTransfer->acceptance_mask_reg = 0; + pTransfer->identifier = 0; + pTransfer->data_low_reg = 0; + pTransfer->data_high_reg = 0; + pTransfer->control_reg = 0; + pTransfer->mailbox_in_use = 0; + pTransfer->size = 0; +} + +//------------------------------------------------------------------------------ +/// Wait for CAN synchronisation +/// \return return 1 for good initialisation, otherwise return 0 +//------------------------------------------------------------------------------ +static unsigned char CAN_Synchronisation( void ) +{ + unsigned int tick=0; + + trace_LOG( trace_INFO, "CAN_Synchronisation\n\r"); + + pCAN0Transfer->test_can = AT91C_TEST_NOK; +#ifdef AT91C_BASE_CAN1 + if( pCAN1Transfer != NULL ) { + pCAN1Transfer->test_can = AT91C_TEST_NOK; + } +#endif + // Enable CAN and Wait for WakeUp Interrupt + AT91C_BASE_CAN0->CAN_IER = AT91C_CAN_WAKEUP; + // CAN Controller Enable + AT91C_BASE_CAN0->CAN_MR = AT91C_CAN_CANEN; + // Enable Autobaud/Listen mode + // dangerous, CAN not answer in this mode + + while( (pCAN0Transfer->test_can != AT91C_TEST_OK) + && (tick < AT91C_CAN_TIMEOUT) ) { + tick++; + } + if (tick == AT91C_CAN_TIMEOUT) { + trace_LOG( trace_ERROR, "-E- CAN0 Initialisations FAILED\n\r"); + return 0; + } else { + trace_LOG( trace_INFO, "-I- CAN0 Initialisations Completed\n\r"); + } + +#if defined AT91C_BASE_CAN1 + if( pCAN1Transfer != NULL ) { + AT91C_BASE_CAN1->CAN_IER = AT91C_CAN_WAKEUP; + // CAN Controller Enable + AT91C_BASE_CAN1->CAN_MR = AT91C_CAN_CANEN; + + tick = 0; + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( ((pCAN1Transfer->test_can != AT91C_TEST_OK)) + && (tick < AT91C_CAN_TIMEOUT) ) { + tick++; + } + + if (tick == AT91C_CAN_TIMEOUT) { + trace_LOG( trace_ERROR, "-E- CAN1 Initialisations FAILED\n\r"); + return 0; + } else { + trace_LOG( trace_INFO, "-I- CAN1 Initialisations Completed\n\r"); + } + } +#endif + return 1; +} + +//------------------------------------------------------------------------------ +/// Write a CAN transfer +/// \param pTransfer can transfer structure +/// \return return CAN_STATUS_SUCCESS if command passed, otherwise +/// return CAN_STATUS_LOCKED +//------------------------------------------------------------------------------ +unsigned char CAN_Write( CanTransfer *pTransfer ) +{ + AT91PS_CAN base_can; + + if (pTransfer->state == CAN_RECEIVING) { + pTransfer->state = CAN_IDLE; + } + + if (pTransfer->state != CAN_IDLE) { + return CAN_STATUS_LOCKED; + } + + trace_LOG( trace_DEBUG, "CAN_Write\n\r"); + pTransfer->state = CAN_SENDING; + if( pTransfer->can_number == 0 ) { + base_can = AT91C_BASE_CAN0; + } +#ifdef AT91C_BASE_CAN1 + else { + base_can = AT91C_BASE_CAN1; + } +#endif + base_can->CAN_TCR = pTransfer->mailbox_in_use; + base_can->CAN_IER = pTransfer->mailbox_in_use; + + return CAN_STATUS_SUCCESS; + +} + + +//------------------------------------------------------------------------------ +/// Read a CAN transfer +/// \param pTransfer can transfer structure +/// \return return CAN_STATUS_SUCCESS if command passed, otherwise +/// return CAN_STATUS_LOCKED +//------------------------------------------------------------------------------ +unsigned char CAN_Read( CanTransfer *pTransfer ) +{ + AT91PS_CAN base_can; + + if (pTransfer->state != CAN_IDLE) { + return CAN_STATUS_LOCKED; + } + + trace_LOG( trace_DEBUG, "CAN_Read\n\r"); + pTransfer->state = CAN_RECEIVING; + + + if( pTransfer->can_number == 0 ) { + base_can = AT91C_BASE_CAN0; + } +#ifdef AT91C_BASE_CAN1 + else { + base_can = AT91C_BASE_CAN1; + } +#endif + // enable interrupt + base_can->CAN_IER = pTransfer->mailbox_in_use; + + return CAN_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Test if CAN is in IDLE state +/// \param pTransfer can transfer structure +/// \return return 0 if CAN is in IDLE, otherwise return 1 +//------------------------------------------------------------------------------ +unsigned char CAN_IsInIdle( CanTransfer *pTransfer ) +{ + return( pTransfer->state != CAN_IDLE ); +} + +//------------------------------------------------------------------------------ +/// Basic CAN test without Interrupt +//------------------------------------------------------------------------------ +void CAN_BasicTestSuiteWithoutInterrupt(void) +{ +#if defined AT91C_BASE_CAN1 + unsigned int status; + unsigned int tick=0; + + trace_LOG( trace_INFO, "Without Interrupt "); + trace_LOG( trace_INFO, "CAN0 Mailbox 0 transmitting to CAN1 Mailbox 0\n\r"); + // Init CAN0 Mailbox 0, transmit + CAN_ResetTransfer( pCAN0Transfer ); + pCAN0Transfer->can_number = 0; + pCAN0Transfer->mailbox_number = 0; + pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR; + pCAN0Transfer->acceptance_mask_reg = 0x00000000; + pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18); + pCAN0Transfer->data_low_reg = 0x11223344; + pCAN0Transfer->data_high_reg = 0x01234567; + pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); + CAN_InitMailboxRegisters( pCAN0Transfer ); + + // Init CAN1 Mailbox 0, receive, + CAN_ResetTransfer( pCAN1Transfer ); + pCAN1Transfer->can_number = 1; + pCAN1Transfer->mailbox_number = 0; + pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX; + pCAN1Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB; + pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18); + pCAN1Transfer->data_low_reg = 0x00000000; + pCAN1Transfer->data_high_reg = 0x00000000; + pCAN1Transfer->control_reg = 0x00000000; + CAN_InitMailboxRegisters( pCAN1Transfer ); + + // Transfer Request for Mailbox 0 + AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB0; + + tick = 0; + do { + // CAN Message Status Register + status = AT91C_BASE_CAN0_MB0->CAN_MB_MSR; + } + while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) ); + + if (tick == AT91C_CAN_TIMEOUT) { + trace_LOG( trace_ERROR, "-E- Test FAILED\n\r"); + } + else { + trace_LOG( trace_DEBUG, "-I- Transfer completed: CAN1 Mailbox 0 MRDY flag has raised\n\r"); + if( AT91C_BASE_CAN0_MB0->CAN_MB_MDL != AT91C_BASE_CAN1_MB0->CAN_MB_MDL ) { + trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r"); + } + else if( AT91C_BASE_CAN0_MB0->CAN_MB_MDH != AT91C_BASE_CAN1_MB0->CAN_MB_MDH ) { + trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r"); + } + else { + trace_LOG( trace_INFO, "Test passed\n\r"); + } + } + + CAN_ResetAllMailbox(); + + trace_LOG( trace_INFO, "Without Interrupt "); + trace_LOG( trace_INFO, "CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r"); + // Init CAN0 Mailbox 1, transmit + CAN_ResetTransfer( pCAN0Transfer ); + pCAN0Transfer->can_number = 0; + pCAN0Transfer->mailbox_number = 1; + pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR; + pCAN0Transfer->acceptance_mask_reg = 0x00000000; + pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18); // ID 9 + pCAN0Transfer->data_low_reg = 0xAABBCCDD; + pCAN0Transfer->data_high_reg = 0xCAFEDECA; + pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code + CAN_InitMailboxRegisters( pCAN0Transfer ); + + // Init CAN0 Mailbox 2, transmit + pCAN0Transfer->can_number = 0; + pCAN0Transfer->mailbox_number = 2; + pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16)); + pCAN0Transfer->acceptance_mask_reg = 0x00000000; + pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18); // ID 10 + pCAN0Transfer->data_low_reg = 0x55667788; + pCAN0Transfer->data_high_reg = 0x99AABBCC; + pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code + CAN_InitMailboxRegisters( pCAN0Transfer ); + + // Init CAN1 Mailbox 15, reception with overwrite + CAN_ResetTransfer( pCAN1Transfer ); + pCAN1Transfer->can_number = 1; + pCAN1Transfer->mailbox_number = 15; + pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RXOVERWRITE; + pCAN1Transfer->acceptance_mask_reg = 0; + pCAN1Transfer->identifier = 0x0; + pCAN1Transfer->data_low_reg = 0x00000000; + pCAN1Transfer->data_high_reg = 0x00000000; + pCAN1Transfer->control_reg = 0x00000000; + CAN_InitMailboxRegisters( pCAN1Transfer ); + + // Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR + AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2; + + // Wait for Last Transmit Mailbox + tick = 0; + do { + status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR; + } + while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) ); + + if (tick == AT91C_CAN_TIMEOUT) { + } + else { + trace_LOG( trace_DEBUG, "-I- Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r"); + if( AT91C_BASE_CAN0_MB1->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) { + trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r"); + } + else if( AT91C_BASE_CAN0_MB1->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) { + trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r"); + } + else { + trace_LOG( trace_INFO, "Test passed\n\r"); + } + } + + CAN_ResetAllMailbox(); + trace_LOG( trace_INFO, "Without Interrupt "); + trace_LOG( trace_INFO, "CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r"); + // Init CAN0 Mailbox 1, transmit + CAN_ResetTransfer( pCAN0Transfer ); + pCAN0Transfer->can_number = 0; + pCAN0Transfer->mailbox_number = 1; + pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR; + pCAN0Transfer->acceptance_mask_reg = 0x00000000; + pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18); // ID 9 + pCAN0Transfer->data_low_reg = 0xAABBCCDD; + pCAN0Transfer->data_high_reg = 0xCAFEDECA; + pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code + CAN_InitMailboxRegisters( pCAN0Transfer ); + + // Init CAN0 Mailbox 2, transmit + pCAN0Transfer->can_number = 0; + pCAN0Transfer->mailbox_number = 2; + pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16)); + pCAN0Transfer->acceptance_mask_reg = 0x00000000; + pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18); // ID 10 + pCAN0Transfer->data_low_reg = 0x55667788; + pCAN0Transfer->data_high_reg = 0x99AABBCC; + pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code + CAN_InitMailboxRegisters( pCAN0Transfer ); + + // Init CAN1 Mailbox 15, reception with overwrite + CAN_ResetTransfer( pCAN1Transfer ); + pCAN1Transfer->can_number = 1; + pCAN1Transfer->mailbox_number = 15; + pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX; + pCAN1Transfer->acceptance_mask_reg = 0; + pCAN1Transfer->identifier = 0x0; + pCAN1Transfer->data_low_reg = 0x00000000; + pCAN1Transfer->data_high_reg = 0x00000000; + pCAN1Transfer->control_reg = 0x00000000; + CAN_InitMailboxRegisters( pCAN1Transfer ); + + // Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR + AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2; + + // Wait for Last Transmit Mailbox + tick = 0; + do { + status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR; + } + while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) ); + + if (tick == AT91C_CAN_TIMEOUT) { + trace_LOG( trace_ERROR, "-E- Test FAILED\n\r"); + } + else { + trace_LOG( trace_DEBUG, "Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r"); + trace_LOG( trace_DEBUG, "MB_MDL: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDL); + trace_LOG( trace_DEBUG, "MB_MDLH: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDH); + if( AT91C_BASE_CAN0_MB2->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) { + trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r"); + } + else if( AT91C_BASE_CAN0_MB2->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) { + trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r"); + } + else { + trace_LOG( trace_INFO, "Test passed\n\r"); + } + } + + CAN_ResetAllMailbox(); + trace_LOG( trace_INFO, "Without Interrupt "); + trace_LOG( trace_INFO, "CAN0 Mailbox 3 asking for CAN1 Mailbox 3 transmission\n\r"); + // Init CAN0 Mailbox 3, consumer mailbox + // Sends a remote frame and waits for an answer + CAN_ResetTransfer( pCAN0Transfer ); + pCAN0Transfer->can_number = 0; + pCAN0Transfer->mailbox_number = 3; + pCAN0Transfer->mode_reg = AT91C_CAN_MOT_CONSUMER | AT91C_CAN_PRIOR; + pCAN0Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB; + pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18); // ID 11 + pCAN0Transfer->data_low_reg = 0x00000000; + pCAN0Transfer->data_high_reg = 0x00000000; + pCAN0Transfer->control_reg = 0x00000000; + CAN_InitMailboxRegisters( pCAN0Transfer ); + + // Init CAN1 Mailbox 3, porducer mailbox + // Waits to receive a Remote Frame before sending its contents + CAN_ResetTransfer( pCAN1Transfer ); + pCAN1Transfer->can_number = 1; + pCAN1Transfer->mailbox_number = 3; + pCAN1Transfer->mode_reg = AT91C_CAN_MOT_PRODUCER | AT91C_CAN_PRIOR; + pCAN1Transfer->acceptance_mask_reg = 0; + pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18); // ID 11 + pCAN1Transfer->data_low_reg = 0xEEDDFF00; + pCAN1Transfer->data_high_reg = 0x34560022; + pCAN1Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); + CAN_InitMailboxRegisters( pCAN1Transfer ); + + // Ask Transmissions on Mailbox 3 --> AT91C_CAN_MRDY raises for Mailbox 3 CAN_MB_SR + AT91C_BASE_CAN1->CAN_TCR = AT91C_CAN_MB3; + AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB3; + + // Wait for Last Transmit Mailbox + tick = 0; + do { + status = AT91C_BASE_CAN0_MB3->CAN_MB_MSR; + } + while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) ); + + if (tick == AT91C_CAN_TIMEOUT) { + trace_LOG( trace_ERROR, "-E- Test FAILED\n\r"); + } + else { + trace_LOG( trace_DEBUG, "-I- Transfer Completed: CAN0 & CAN1 Mailboxes 3 MRDY flags have raised\n\r"); + if( AT91C_BASE_CAN0_MB3->CAN_MB_MDL != AT91C_BASE_CAN1_MB3->CAN_MB_MDL ) { + trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r"); + } + else if( AT91C_BASE_CAN0_MB3->CAN_MB_MDH != AT91C_BASE_CAN1_MB3->CAN_MB_MDH ) { + trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r"); + } + else { + trace_LOG( trace_INFO, "Test passed\n\r"); + } + } +#endif // AT91C_BASE_CAN1 + + return; +} + + +//------------------------------------------------------------------------------ +/// Disable CAN and enter in low power +//------------------------------------------------------------------------------ +void CAN_disable( void ) +{ + // Disable the interrupt on the interrupt controller + AIC_DisableIT(AT91C_ID_CAN0); + // disable all IT + AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF; +#if defined AT91C_BASE_CAN1 + AIC_DisableIT(AT91C_ID_CAN1); + // disable all IT + AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF; +#endif + + // Enable Low Power mode + AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_LPM; + + // Disable CANs Transceivers + // Enter standby mode + PIO_Set(&pin_can_transceiver_rs); +#if defined (PIN_CAN_TRANSCEIVER_RXEN) + // Enable ultra Low Power mode + PIO_Clear(&pin_can_transceiver_rxen); +#endif + + // Disable clock for CAN PIO + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_PIOA); + + // Disable the CAN0 controller peripheral clock + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_CAN0); + +} + +//------------------------------------------------------------------------------ +/// baudrate calcul +/// \param base_CAN CAN base address +/// \param baudrate Baudrate value +/// allowed values: 1000, 800, 500, 250, 125, 50, 25, 10 +/// \return return 1 in success, otherwise return 0 +//------------------------------------------------------------------------------ +unsigned char CAN_BaudRateCalculate( AT91PS_CAN base_CAN, + unsigned int baudrate ) +{ + unsigned int BRP; + unsigned int PROPAG; + unsigned int PHASE1; + unsigned int PHASE2; + unsigned int SJW; + unsigned int t1t2; + + base_CAN->CAN_BR = 0; + + BRP = (BOARD_MCK / (baudrate*1000*16))-1; + //trace_LOG( trace_DEBUG, "BRP = 0x%X\n\r", BRP); + // timing Delay: + // Delay Bus Driver: 50 ns + // Delay Receiver: 30 ns + // Delay Bus Line: 110 ns + if( (16*baudrate*2*(50+30+110)/1000000) >= 1) { + PROPAG = (16*baudrate*2*(50+30+110)/1000000)-1; + } + else { + PROPAG = 0; + } + //trace_LOG( trace_DEBUG, "PROPAG = 0x%X\n\r", PROPAG); + + t1t2 = 15-(PROPAG+1); + //trace_LOG( trace_DEBUG, "t1t2 = 0x%X\n\r", t1t2); + + if( (t1t2 & 0x01) == 0x01 ) { + // ODD + //trace_LOG( trace_DEBUG, "ODD\n\r"); + PHASE1 = ((t1t2-1)/2)-1; + PHASE2 = PHASE1+1; + } + else { + // EVEN + //trace_LOG( trace_DEBUG, "EVEN\n\r"); + PHASE1 = (t1t2/2)-1; + PHASE2 = PHASE1; + } + //trace_LOG( trace_DEBUG, "PHASE1 = 0x%X\n\r", PHASE1); + //trace_LOG( trace_DEBUG, "PHASE2 = 0x%X\n\r", PHASE2); + + if( 1 > (4/(PHASE1+1)) ) { + //trace_LOG( trace_DEBUG, "4*Tcsc\n\r"); + SJW = 3; + } + else { + //trace_LOG( trace_DEBUG, "Tphs1\n\r"); + SJW = PHASE1; + } + //trace_LOG( trace_DEBUG, "SJW = 0x%X\n\r", SJW); + // Verif + if( BRP == 0 ) { + trace_LOG( trace_DEBUG, "BRP = 0 is not authorized\n\r"); + return 0; + } + if( (PROPAG + PHASE1 + PHASE2) != 12 ) { + trace_LOG( trace_DEBUG, "(PROPAG + PHASE1 + PHASE2) != 12\n\r"); + return 0; + } + base_CAN->CAN_BR = (AT91C_CAN_PHASE2 & (PHASE2 << 0)) + + (AT91C_CAN_PHASE1 & (PHASE1 << 4)) + + (AT91C_CAN_PROPAG & (PROPAG << 8)) + + (AT91C_CAN_SYNC & (SJW << 12)) + + (AT91C_CAN_BRP & (BRP << 16)) + + (AT91C_CAN_SMP & (0 << 24)); + return 1; + +} + +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Init of the CAN peripheral +/// \param baudrate Baudrate value +/// allowed values: 1000, 800, 500, 250, 125, 50, 25, 10 +/// \param canTransfer0 CAN0 structure transfer +/// \param canTransfer1 CAN1 structure transfer +/// \return return 1 if CAN has good baudrate and CAN is synchronized, +/// otherwise return 0 +//------------------------------------------------------------------------------ +unsigned char CAN_Init( unsigned int baudrate, + CanTransfer *canTransfer0, + CanTransfer *canTransfer1 ) +{ + unsigned char ret; + + // CAN Transmit Serial Data +#if defined (PINS_CAN_TRANSCEIVER_TXD) + PIO_Configure(pins_can_transceiver_txd, PIO_LISTSIZE(pins_can_transceiver_txd)); +#endif +#if defined (PINS_CAN_TRANSCEIVER_RXD) + // CAN Receive Serial Data + PIO_Configure(pins_can_transceiver_rxd, PIO_LISTSIZE(pins_can_transceiver_rxd)); +#endif + // CAN RS + PIO_Configure(&pin_can_transceiver_rs, PIO_LISTSIZE(pin_can_transceiver_rs)); +#if defined (PIN_CAN_TRANSCEIVER_RXEN) + // CAN RXEN + PIO_Configure(&pin_can_transceiver_rxen, PIO_LISTSIZE(pin_can_transceiver_rxen)); +#endif + + // Enable clock for CAN PIO + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA); + + // Enable the CAN0 controller peripheral clock + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN0); + + // disable all IT + AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF; + + // Enable CANs Transceivers +#if defined (PIN_CAN_TRANSCEIVER_RXEN) + // Disable ultra Low Power mode + PIO_Set(&pin_can_transceiver_rxen); +#endif + // Normal Mode (versus Standby mode) + PIO_Clear(&pin_can_transceiver_rs); + + // Configure the AIC for CAN interrupts + AIC_ConfigureIT(AT91C_ID_CAN0, AT91C_AIC_PRIOR_HIGHEST, CAN0_Handler); + + // Enable the interrupt on the interrupt controller + AIC_EnableIT(AT91C_ID_CAN0); + + if( CAN_BaudRateCalculate(AT91C_BASE_CAN0, baudrate) == 0 ) { + // Baudrate problem + trace_LOG( trace_DEBUG, "Baudrate CAN0 problem\n\r"); + return 0; + } + + pCAN0Transfer = canTransfer0; + +#if defined AT91C_BASE_CAN1 + if( canTransfer1 != NULL ) { + pCAN1Transfer = canTransfer1; + // Enable CAN1 Clocks + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN1); + + // disable all IT + AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF; + + // Configure the AIC for CAN interrupts + AIC_ConfigureIT(AT91C_ID_CAN1, AT91C_AIC_PRIOR_HIGHEST, CAN1_Handler); + + // Enable the interrupt on the interrupt controller + AIC_EnableIT(AT91C_ID_CAN1); + + if( CAN_BaudRateCalculate(AT91C_BASE_CAN1, baudrate) == 0 ) { + // Baudrate problem + trace_LOG( trace_DEBUG, "Baudrate CAN1 problem\n\r"); + return 0; + } + } +#endif + // Reset all mailbox + CAN_ResetAllMailbox(); + + // Enable the interrupt with all error cases + AT91C_BASE_CAN0->CAN_IER = AT91C_CAN_CERR // (CAN) CRC Error + | AT91C_CAN_SERR // (CAN) Stuffing Error + | AT91C_CAN_BERR // (CAN) Bit Error + | AT91C_CAN_FERR // (CAN) Form Error + | AT91C_CAN_AERR; // (CAN) Acknowledgment Error + +#if defined AT91C_BASE_CAN1 + if( canTransfer1 != NULL ) { + AT91C_BASE_CAN1->CAN_IER = AT91C_CAN_CERR // (CAN) CRC Error + | AT91C_CAN_SERR // (CAN) Stuffing Error + | AT91C_CAN_BERR // (CAN) Bit Error + | AT91C_CAN_FERR // (CAN) Form Error + | AT91C_CAN_AERR; // (CAN) Acknowledgment Error + } +#endif + + // Wait for CAN synchronisation + if( CAN_Synchronisation( ) == 1 ) { + ret = 1; + } + else { + ret = 0; + } + + return ret; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/can/can.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/can/can.h new file mode 100644 index 0000000..63a83b3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/can/can.h @@ -0,0 +1,113 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _CAN_H +#define _CAN_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ +#define AT91C_CAN_TIMEOUT 100000 + +#define AT91C_TEST_NOK 0 +#define AT91C_TEST_OK 1 + +#define CAN_STATUS_SUCCESS 0 +#define CAN_STATUS_LOCKED 1 +#define CAN_STATUS_ABORTED 2 +#define CAN_STATUS_RESET 3 + +#if defined (AT91C_BASE_CAN) + #define AT91C_BASE_CAN0 AT91C_BASE_CAN +#endif +#if defined (AT91C_ID_CAN) + #define AT91C_ID_CAN0 AT91C_ID_CAN +#endif +#if defined (AT91C_BASE_CAN_MB0) + #define AT91C_BASE_CAN0_MB0 AT91C_BASE_CAN_MB0 + #define AT91C_BASE_CAN0_MB1 AT91C_BASE_CAN_MB1 + #define AT91C_BASE_CAN0_MB2 AT91C_BASE_CAN_MB2 + #define AT91C_BASE_CAN0_MB3 AT91C_BASE_CAN_MB3 + #define AT91C_BASE_CAN0_MB4 AT91C_BASE_CAN_MB4 + #define AT91C_BASE_CAN0_MB5 AT91C_BASE_CAN_MB5 + #define AT91C_BASE_CAN0_MB6 AT91C_BASE_CAN_MB6 + #define AT91C_BASE_CAN0_MB7 AT91C_BASE_CAN_MB7 +#endif +#if defined (AT91C_BASE_CAN_MB8) + #define AT91C_BASE_CAN0_MB8 AT91C_BASE_CAN_MB8 + #define AT91C_BASE_CAN0_MB9 AT91C_BASE_CAN_MB9 + #define AT91C_BASE_CAN0_MB10 AT91C_BASE_CAN_MB10 + #define AT91C_BASE_CAN0_MB11 AT91C_BASE_CAN_MB11 + #define AT91C_BASE_CAN0_MB12 AT91C_BASE_CAN_MB12 + #define AT91C_BASE_CAN0_MB13 AT91C_BASE_CAN_MB13 + #define AT91C_BASE_CAN0_MB14 AT91C_BASE_CAN_MB14 + #define AT91C_BASE_CAN0_MB15 AT91C_BASE_CAN_MB15 +#endif + +#define NUM_MAILBOX_MAX 16 + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ +typedef struct +{ + volatile unsigned char state; + volatile unsigned char can_number; + volatile unsigned char mailbox_number; + volatile unsigned char test_can; + volatile unsigned int mode_reg; + volatile unsigned int acceptance_mask_reg; + volatile unsigned int identifier; + volatile unsigned int data_low_reg; + volatile unsigned int data_high_reg; + volatile unsigned int control_reg; + volatile unsigned int mailbox_in_use; + volatile int size; +} CanTransfer; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern unsigned char CAN_Init( unsigned int baudrate, + CanTransfer *canTransferRead, + CanTransfer *canTransferWrite ); +extern void CAN_BasicTestSuite(void); +extern void CAN_disable( void ); +extern void CAN_ResetAllMailbox( void ); +extern void CAN_ResetTransfer( CanTransfer *pTransfer ); +extern void CAN_InitMailboxRegisters( CanTransfer *pTransfer ); +extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer ); + +extern unsigned char CAN_Write( CanTransfer *pTransfer ); +extern unsigned char CAN_Read( CanTransfer *pTransfer ); + +extern void CAN_BasicTestSuiteWithoutInterrupt( void ); +extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer ); +#endif // _CAN_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.c new file mode 100644 index 0000000..3cb7af5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.c @@ -0,0 +1,156 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "dbgu.h" +#include +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Initializes the DBGU with the given parameters, and enables both the +/// transmitter and the receiver. +/// \param mode Operating mode to configure (see ). +/// \param baudrate Desired baudrate. +/// \param mck Frequency of the system master clock. +//------------------------------------------------------------------------------ +void DBGU_Configure(unsigned int mode, + unsigned int baudrate, + unsigned int mck) +{ + // Reset & disable receiver and transmitter, disable interrupts + AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTRX | AT91C_US_RSTTX; + AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF; + + // Configure baud rate + AT91C_BASE_DBGU->DBGU_BRGR = mck / (baudrate * 16); + + // Configure mode register + AT91C_BASE_DBGU->DBGU_MR = mode; + + // Disable DMA channel + AT91C_BASE_DBGU->DBGU_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS; + + // Enable receiver and transmitter + AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN; +} + +//------------------------------------------------------------------------------ +/// Outputs a character on the DBGU line. +/// \param c Character to send. +//------------------------------------------------------------------------------ +static void DBGU_PutChar(unsigned char c) +{ + // Wait for the transmitter to be ready + while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0); + + // Send character + AT91C_BASE_DBGU->DBGU_THR = c; + + // Wait for the transfer to complete + while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0); +} + +//------------------------------------------------------------------------------ +/// Reads and returns a character from the DBGU. +//------------------------------------------------------------------------------ +unsigned char DBGU_GetChar() +{ + while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_RXRDY) == 0); + return AT91C_BASE_DBGU->DBGU_RHR; +} + +#ifndef NOFPUT + +#include + +//------------------------------------------------------------------------------ +/// Implementation of fputc using the DBGU as the standard output. Required +/// for printf(). +/// Returns the character written if successful, or -1 if the output stream is +/// not stdout or stderr. +/// \param c Character to write. +/// \param pStream Output stream. +//------------------------------------------------------------------------------ +signed int fputc(signed int c, FILE *pStream) +{ + if ((pStream == stdout) || (pStream == stderr)) { + + DBGU_PutChar(c); + return c; + } + else { + + return EOF; + } +} + +//------------------------------------------------------------------------------ +/// Implementation of fputs using the DBGU as the standard output. Required +/// for printf(). Does NOT currently use the PDC. +/// Returns the number of characters written if successful, or -1 if the output +/// stream is not stdout or stderr. +/// \param pStr String to write. +/// \param pStream Output stream. +//------------------------------------------------------------------------------ +signed int fputs(const char *pStr, FILE *pStream) +{ + signed int num = 0; + + while (*pStr != 0) { + + if (fputc(*pStr, pStream) == -1) { + + return -1; + } + num++; + pStr++; + } + + return num; +} + +#undef putchar + +//------------------------------------------------------------------------------ +/// Outputs a character on the DBGU. Returns the character itself. +/// \param c Character to output. +//------------------------------------------------------------------------------ +signed int putchar(signed int c) +{ + return fputc(c, stdout); +} + +#endif //#ifndef NOFPUT + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.h new file mode 100644 index 0000000..1893016 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// This module provides definitions and functions for using the DBGU. +/// +/// !Usage +/// +/// -# Enable the DBGU pins (see pio.h). +/// -# Configure the DBGU using DBGU_Configure. +/// +/// \note Unless specified, all the functions defined here operate synchronously; +/// i.e. they all wait the data is sent/received before returning. +//------------------------------------------------------------------------------ + +#ifndef DBGU_H +#define DBGU_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page Modes +/// This page lists several common operating modes for the DBGU. +/// !Modes +/// - DBGU_STANDARD + +/// Standard operating mode (asynchronous, 8bit, no parity) +#define DBGU_STANDARD AT91C_US_PAR_NONE +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void DBGU_Configure(unsigned int mode, + unsigned int baudrate, + unsigned int mck); + +extern unsigned char DBGU_GetChar(); + +#endif //#ifndef DBGU_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.c new file mode 100644 index 0000000..cf0fdbe --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.c @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef trace_LEVEL + #define trace_LEVEL trace_INFO +#endif + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "eefc.h" + +#ifdef BOARD_FLASH_EEFC + +#include +#include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Enables the flash ready interrupt source on the EEFC peripheral. +//------------------------------------------------------------------------------ +void EFC_EnableFrdyIt(void) +{ + AT91C_BASE_EFC->EFC_FMR |= AT91C_EFC_FRDY; +} + +//------------------------------------------------------------------------------ +/// Disables the flash ready interrupt source on the EEFC peripheral. +//------------------------------------------------------------------------------ +void EFC_DisableFrdyIt(void) +{ + AT91C_BASE_EFC->EFC_FMR &= ~AT91C_EFC_FRDY; +} + +//------------------------------------------------------------------------------ +/// Translates the given address page and offset values. The resulting +/// values are stored in the provided variables if they are not null. +/// \param address Address to translate. +/// \param pPage First page accessed. +/// \param pOffset Byte offset in first page. +//------------------------------------------------------------------------------ +void EFC_TranslateAddress( + unsigned int address, + unsigned short *pPage, + unsigned short *pOffset) +{ + unsigned short page; + unsigned short offset; + + SANITY_CHECK(address >= AT91C_IFLASH); + SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE)); + + // Calculate page & offset + page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE; + offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE; + trace_LOG(trace_DEBUG, + "-D- Translated 0x%08X to page=%d and offset=%d\n\r", + address, page, offset); + + // Store values + if (pPage) { + + *pPage = page; + } + if (pOffset) { + + *pOffset = offset; + } +} + +//------------------------------------------------------------------------------ +/// Computes the address of a flash access given the page and offset. +/// \param page Page number. +/// \param offset Byte offset inside page. +/// \param pAddress Computed address (optional). +//------------------------------------------------------------------------------ +void EFC_ComputeAddress( + unsigned short page, + unsigned short offset, + unsigned int *pAddress) +{ + unsigned int address; + + SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES); + SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE); + + // Compute address + address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset; + + // Store result + if (pAddress) { + + *pAddress = address; + } +} + +//------------------------------------------------------------------------------ +/// Starts the executing the given command on the EEFC. This function returns +/// as soon as the command is started. It does NOT set the FMCN field automatically. +/// \param command Command to execute. +/// \param argument Command argument (should be 0 if not used). +//------------------------------------------------------------------------------ +void EFC_StartCommand(unsigned char command, unsigned short argument) +{ + // Check command & argument + switch (command) { + + case AT91C_EFC_FCMD_WP: + case AT91C_EFC_FCMD_WPL: + case AT91C_EFC_FCMD_EWP: + case AT91C_EFC_FCMD_EWPL: + case AT91C_EFC_FCMD_EPL: + case AT91C_EFC_FCMD_EPA: + case AT91C_EFC_FCMD_SLB: + case AT91C_EFC_FCMD_CLB: + ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES, + "-F- Embedded flash has only %d pages\n\r", + AT91C_IFLASH_NB_OF_PAGES); + break; + + case AT91C_EFC_FCMD_SFB: + case AT91C_EFC_FCMD_CFB: + ASSERT(argument < EFC_NUM_GPNVMS, "-F- Embedded flash has only %d GPNVMs\n\r", EFC_NUM_GPNVMS); + break; + + case AT91C_EFC_FCMD_GETD: + case AT91C_EFC_FCMD_EA: + case AT91C_EFC_FCMD_GLB: + case AT91C_EFC_FCMD_GFB: + ASSERT(argument == 0, "-F- Argument is meaningless for the given command.\n\r"); + break; + + default: ASSERT(0, "-F- Unknown command %d\n\r", command); + } + + // Start commandEmbedded flash + ASSERT((AT91C_BASE_EFC->EFC_FSR & AT91C_EFC_FRDY) == AT91C_EFC_FRDY, "-F- EEFC is not ready\n\r"); + AT91C_BASE_EFC->EFC_FCR = (0x5A << 24) | (argument << 8) | command; +} + +//------------------------------------------------------------------------------ +/// Performs the given command and wait until its completion (or an error). +/// Returns 0 if successful; otherwise returns an error code. +/// \param command Command to perform. +/// \param argument Optional command argument. +//------------------------------------------------------------------------------ +#ifdef __ICCARM__ +__ramfunc +#else +__attribute__ ((section (".ramfunc"))) +#endif +unsigned char EFC_PerformCommand(unsigned char command, unsigned short argument) +{ + unsigned int status; + +#ifdef BOARD_FLASH_IAP_ADDRESS + // Pointer on IAP function in ROM + static void (*IAP_PerformCommand)(unsigned int); + IAP_PerformCommand = (void (*)(unsigned int)) *((unsigned int *) BOARD_FLASH_IAP_ADDRESS); + + // Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */ + if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) && + (((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) { + + IAP_PerformCommand((0x5A << 24) | (argument << 8) | command); + return (AT91C_BASE_EFC->EFC_FSR & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE)); + } +#endif + + AT91C_BASE_EFC->EFC_FCR = (0x5A << 24) | (argument << 8) | command; + do { + + status = AT91C_BASE_EFC->EFC_FSR; + } + while ((status & AT91C_EFC_FRDY) != AT91C_EFC_FRDY); + + return (status & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE)); +} + +//------------------------------------------------------------------------------ +/// Returns the current status of the EEFC. Keep in mind that this function clears +/// the value of some status bits (LOCKE, PROGE). +//------------------------------------------------------------------------------ +unsigned int EFC_GetStatus(void) +{ + return AT91C_BASE_EFC->EFC_FSR; +} + +//------------------------------------------------------------------------------ +/// Returns the result of the last executed command. +//------------------------------------------------------------------------------ +unsigned int EFC_GetResult(void) { + + return AT91C_BASE_EFC->EFC_FRR; +} + +#endif //#ifdef BOARD_FLASH_EEFC + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.h new file mode 100644 index 0000000..277e4c7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.h @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef EEFC_H +#define EEFC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +#ifdef BOARD_FLASH_EEFC + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + +/// Number of GPNVMs available on each chip. +#if defined(at91sam7l64) || defined(at91sam7l128) + + #define EFC_NUM_GPNVMS 2 + +#elif defined(at91sam9xe128) || defined(at91sam9xe256) || defined(at91sam9xe512) + + #define EFC_NUM_GPNVMS 17 +#endif + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +// Needed when EEFC is integrated in MC. +#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC) +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // EFC Flash Mode Register + AT91_REG EFC_FCR; // EFC Flash Command Register + AT91_REG EFC_FSR; // EFC Flash Status Register + AT91_REG EFC_FRR; // EFC Flash Result Register + AT91_REG EFC_FVR; // EFC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; + +#define AT91C_EFC_FRDY AT91C_MC_FRDY +#define AT91C_EFC_FWS AT91C_MC_FWS +#define AT91C_EFC_FWS_0WS AT91C_MC_FWS_0WS +#define AT91C_EFC_FWS_1WS AT91C_MC_FWS_1WS +#define AT91C_EFC_FWS_2WS AT91C_MC_FWS_2WS +#define AT91C_EFC_FWS_3WS AT91C_MC_FWS_3WS +#define AT91C_EFC_FCMD AT91C_MC_FCMD +#define AT91C_EFC_FCMD_GETD AT91C_MC_FCMD_GETD +#define AT91C_EFC_FCMD_WP AT91C_MC_FCMD_WP +#define AT91C_EFC_FCMD_WPL AT91C_MC_FCMD_WPL +#define AT91C_EFC_FCMD_EWP AT91C_MC_FCMD_EWP +#define AT91C_EFC_FCMD_EWPL AT91C_MC_FCMD_EWPL +#define AT91C_EFC_FCMD_EA AT91C_MC_FCMD_EA +#define AT91C_EFC_FCMD_EPL AT91C_MC_FCMD_EPL +#define AT91C_EFC_FCMD_EPA AT91C_MC_FCMD_EPA +#define AT91C_EFC_FCMD_SLB AT91C_MC_FCMD_SLB +#define AT91C_EFC_FCMD_CLB AT91C_MC_FCMD_CLB +#define AT91C_EFC_FCMD_GLB AT91C_MC_FCMD_GLB +#define AT91C_EFC_FCMD_SFB AT91C_MC_FCMD_SFB +#define AT91C_EFC_FCMD_CFB AT91C_MC_FCMD_CFB +#define AT91C_EFC_FCMD_GFB AT91C_MC_FCMD_GFB +#define AT91C_EFC_FARG AT91C_MC_FARG +#define AT91C_EFC_FKEY AT91C_MC_FKEY +#define AT91C_EFC_FRDY_S AT91C_MC_FRDY_S +#define AT91C_EFC_FCMDE AT91C_MC_FCMDE +#define AT91C_EFC_LOCKE AT91C_MC_LOCKE +#define AT91C_EFC_FVALUE AT91C_MC_FVALUE + +#define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) + +#endif //#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC) + +//------------------------------------------------------------------------------ +// Functions +//------------------------------------------------------------------------------ + +extern void EFC_EnableFrdyIt(void); + +extern void EFC_DisableFrdyIt(void); + +extern void EFC_TranslateAddress( + unsigned int address, + unsigned short *pPage, + unsigned short *pOffset); + +extern void EFC_ComputeAddress( + unsigned short page, + unsigned short offset, + unsigned int *pAddress); + +extern void EFC_StartCommand( + unsigned char command, + unsigned short argument); + +extern unsigned char EFC_PerformCommand( + unsigned char command, + unsigned short argument); + +extern unsigned int EFC_GetStatus(void); + +extern unsigned int EFC_GetResult(void); + +#endif //#ifdef BOARD_FLASH_EEFC +#endif //#ifndef EEFC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/efc/efc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/efc/efc.c new file mode 100644 index 0000000..b4637c8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/efc/efc.c @@ -0,0 +1,387 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef trace_LEVEL + #define trace_LEVEL trace_INFO +#endif + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "efc.h" + +#ifdef BOARD_FLASH_EFC + +#include +#include + +//------------------------------------------------------------------------------ +// Local definitions +//------------------------------------------------------------------------------ + +// Round a number to the nearest integral value (number must have been +// multiplied by 10, e.g. to round 10.3 enter 103). +#define ROUND(n) ((((n) % 10) >= 5) ? (((n) / 10) + 1) : ((n) / 10)) + +// Returns the FMCN field value when manipulating lock bits, given MCK. +#if defined(at91sam7a3) + #define FMCN_BITS(mck) (ROUND((mck) / 100000) << 16) // <- Not correct according to the datasheet but it works +#else + #define FMCN_BITS(mck) (ROUND((mck) / 100000) << 16) +#endif + +// Returns the FMCN field value when manipulating the rest of the flash. +#define FMCN_FLASH(mck) ((((mck) / 2000000) * 3) << 16) + +//------------------------------------------------------------------------------ +// Local functions +//------------------------------------------------------------------------------ + + +/// Master clock frequency, used to infer the value of the FMCN field. +static unsigned int lMck; +/// Calculated value of the FMCN field base on Master clock frequency. +static unsigned int lMckFMCN; + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Sets the system master clock so the FMCN field of the EFC(s) can be +/// programmed properly. +/// \param mck Master clock frequency in Hz. +//------------------------------------------------------------------------------ +void EFC_SetMasterClock(unsigned int mck) +{ + lMck = mck; + lMckFMCN = FMCN_BITS(lMck); +} + +//------------------------------------------------------------------------------ +/// Enables the given interrupt sources on an EFC peripheral. +/// \param pEfc Pointer to an AT91S_EFC structure. +/// \param sources Interrupt sources to enable. +//------------------------------------------------------------------------------ +void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources) +{ + SANITY_CHECK(pEfc); + SANITY_CHECK((sources & ~0x0000000D) == 0); + + pEfc->EFC_FMR |= sources; +} + +//------------------------------------------------------------------------------ +/// Disables the given interrupt sources on an EFC peripheral. +/// \param pEfc Pointer to an AT91S_EFC structure. +/// \param sources Interrupt sources to disable. +//------------------------------------------------------------------------------ +void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources) +{ + SANITY_CHECK(pEfc); + SANITY_CHECK((sources & ~(AT91C_MC_FRDY | AT91C_MC_LOCKE | AT91C_MC_PROGE)) == 0); + + pEfc->EFC_FMR &= ~sources; +} + +//------------------------------------------------------------------------------ +/// Enables or disable the "Erase before programming" feature of an EFC. +/// \param pEfc Pointer to an AT91S_EFC structure. +/// \param enable If 1, the feature is enabled; otherwise it is disabled. +//------------------------------------------------------------------------------ +void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable) +{ + SANITY_CHECK(pEfc); + + if (enable) { + + pEfc->EFC_FMR &= ~AT91C_MC_NEBP; + } + else { + + pEfc->EFC_FMR |= AT91C_MC_NEBP; + } +} + +//------------------------------------------------------------------------------ +/// Translates the given address into EFC, page and offset values. The resulting +/// values are stored in the provided variables if they are not null. +/// \param address Address to translate. +/// \param ppEfc Pointer to target EFC peripheral. +/// \param pPage First page accessed. +/// \param pOffset Byte offset in first page. +//------------------------------------------------------------------------------ +void EFC_TranslateAddress( + unsigned int address, + AT91S_EFC **ppEfc, + unsigned short *pPage, + unsigned short *pOffset) +{ + AT91S_EFC *pEfc; + unsigned short page; + unsigned short offset; + + SANITY_CHECK(address >= AT91C_IFLASH); + SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE)); + +#if defined(AT91C_BASE_EFC0) + if (address >= (AT91C_IFLASH + AT91C_IFLASH_SIZE / 2)) { + + pEfc = AT91C_BASE_EFC1; + page = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) / AT91C_IFLASH_PAGE_SIZE; + offset = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) % AT91C_IFLASH_PAGE_SIZE; + } + else { + + pEfc = AT91C_BASE_EFC0; + page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE; + offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE; + } +#else + pEfc = AT91C_BASE_EFC; + page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE; + offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE; +#endif + trace_LOG(trace_DEBUG, + "-D- Translated 0x%08X to EFC=0x%08X, page=%d and offset=%d\n\r", + address, (unsigned int) pEfc, page, offset); + + // Store values + if (ppEfc) { + + *ppEfc = pEfc; + } + if (pPage) { + + *pPage = page; + } + if (pOffset) { + + *pOffset = offset; + } +} + +//------------------------------------------------------------------------------ +/// Computes the address of a flash access given the EFC, page and offset. +/// \param pEfc Pointer to an AT91S_EFC structure. +/// \param page Page number. +/// \param offset Byte offset inside page. +/// \param pAddress Computed address (optional). +//------------------------------------------------------------------------------ +void EFC_ComputeAddress( + AT91S_EFC *pEfc, + unsigned short page, + unsigned short offset, + unsigned int *pAddress) +{ + unsigned int address; + + SANITY_CHECK(pEfc); +#if defined(AT91C_BASE_EFC1) + SANITY_CHECK(page <= (AT91C_IFLASH_NB_OF_PAGES / 2)); +#else + SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES); +#endif + SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE); + + // Compute address + address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset; +#if defined(AT91C_BASE_EFC1) + if (pEfc == AT91C_BASE_EFC1) { + + address += AT91C_IFLASH_SIZE / 2; + } +#endif + + // Store result + if (pAddress) { + + *pAddress = address; + } +} + +//------------------------------------------------------------------------------ +/// Starts the executing the given command on an EFC. This function returns +/// as soon as the command is started. It does NOT set the FMCN field automatically. +/// \param pEfc Pointer to an AT91S_EFC structure. +/// \param command Command to execute. +/// \param argument Command argument (should be 0 if not used). +//------------------------------------------------------------------------------ +void EFC_StartCommand( + AT91S_EFC *pEfc, + unsigned char command, + unsigned short argument) +{ + SANITY_CHECK(pEfc); + ASSERT(lMck != 0, "-F- Master clock not set.\n\r"); + + // Check command & argument + switch (command) { + + case AT91C_MC_FCMD_PROG_AND_LOCK: + ASSERT(0, "-F- Write and lock command cannot be carried out.\n\r"); + break; + + case AT91C_MC_FCMD_START_PROG: + case AT91C_MC_FCMD_LOCK: + case AT91C_MC_FCMD_UNLOCK: + ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES, + "-F- Maximum number of pages is %d (argument was %d)\n\r", + AT91C_IFLASH_NB_OF_PAGES, + argument); + break; + +#if (EFC_NUM_GPNVMS > 0) + case AT91C_MC_FCMD_SET_GP_NVM: + case AT91C_MC_FCMD_CLR_GP_NVM: + ASSERT(argument < EFC_NUM_GPNVMS, "-F- A maximum of %d GPNVMs are available on the chip.\n\r", EFC_NUM_GPNVMS); + break; +#endif + + case AT91C_MC_FCMD_ERASE_ALL: + +#if !defined(EFC_NO_SECURITY_BIT) + case AT91C_MC_FCMD_SET_SECURITY: +#endif + ASSERT(argument == 0, "-F- Argument is meaningless for the given command\n\r"); + break; + + default: ASSERT(0, "-F- Unknown command %d\n\r", command); + } + + // Set FMCN + switch (command) { + + case AT91C_MC_FCMD_LOCK: + case AT91C_MC_FCMD_UNLOCK: +#if (EFC_NUM_GPNVMS > 0) + case AT91C_MC_FCMD_SET_GP_NVM: + case AT91C_MC_FCMD_CLR_GP_NVM: +#endif +#if !defined(EFC_NO_SECURITY_BIT) + case AT91C_MC_FCMD_SET_SECURITY: +#endif + pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN; + break; + + case AT91C_MC_FCMD_START_PROG: + case AT91C_MC_FCMD_ERASE_ALL: + pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN; + break; + } + + // Start command + ASSERT((pEfc->EFC_FSR & AT91C_MC_FRDY) != 0, "-F- Efc is not ready\n\r"); + pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command; +} + +//------------------------------------------------------------------------------ +/// Performs the given command and wait until its completion (or an error). +/// Returns 0 if successful; otherwise returns an error code. +/// \param pEfc Pointer to an AT91S_EFC structure. +/// \param command Command to perform. +/// \param argument Optional command argument. +//------------------------------------------------------------------------------ +#ifdef __ICCARM__ +__ramfunc +#else +__attribute__ ((section (".ramfunc"))) +#endif +unsigned char EFC_PerformCommand( + AT91S_EFC *pEfc, + unsigned char command, + unsigned short argument) +{ + unsigned int status; + + // Set FMCN + switch (command) { + + case AT91C_MC_FCMD_LOCK: + case AT91C_MC_FCMD_UNLOCK: +#if (EFC_NUM_GPNVMS > 0) + case AT91C_MC_FCMD_SET_GP_NVM: + case AT91C_MC_FCMD_CLR_GP_NVM: +#endif +#if !defined(EFC_NO_SECURITY_BIT) + case AT91C_MC_FCMD_SET_SECURITY: +#endif + pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN; + break; + + case AT91C_MC_FCMD_START_PROG: + case AT91C_MC_FCMD_ERASE_ALL: + pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN; + break; + } + +#ifdef BOARD_FLASH_IAP_ADDRESS + // Pointer on IAP function in ROM + static void (*IAP_PerformCommand)(unsigned int, unsigned int); + unsigned int index = 0; +#ifdef AT91C_BASE_EFC1 + if (pEfc == AT91C_BASE_EFC1) { + + index = 1; + } +#endif + IAP_PerformCommand = (void (*)(unsigned int, unsigned int)) *((unsigned int *) BOARD_FLASH_IAP_ADDRESS); + + // Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */ + if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) && + (((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) { + + IAP_PerformCommand(index, (0x5A << 24) | (argument << 8) | command); + return (pEfc->EFC_FSR & (AT91C_MC_LOCKE | AT91C_MC_PROGE)); + } +#endif + + pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command; + do { + + status = pEfc->EFC_FSR; + } + while ((status & AT91C_MC_FRDY) == 0); + + return (status & (AT91C_MC_PROGE | AT91C_MC_LOCKE)); +} + +//------------------------------------------------------------------------------ +/// Returns the current status of an EFC. Keep in mind that this function clears +/// the value of some status bits (LOCKE, PROGE). +/// \param pEfc Pointer to an AT91S_EFC structure. +//------------------------------------------------------------------------------ +unsigned int EFC_GetStatus(AT91S_EFC *pEfc) +{ + return pEfc->EFC_FSR; +} + +#endif //#ifdef BOARD_FLASH_EFC + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/efc/efc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/efc/efc.h new file mode 100644 index 0000000..6487c66 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/efc/efc.h @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef EFC_H +#define EFC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +#ifdef BOARD_FLASH_EFC + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + +/// Number of GPNVMs available on each chip. +#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \ + || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \ + || defined(at91sam7s256) || defined(at91sam7s512) + + #define EFC_NUM_GPNVMS 2 + +#elif defined(at91sam7se32) || defined(at91sam7se256) || defined(at91sam7se512) \ + || defined(at91sam7x128) || defined(at91sam7x256) || defined(at91sam7x512) \ + || defined(at91sam7xc128) || defined(at91sam7xc256) || defined(at91sam7xc512) \ + + #define EFC_NUM_GPNVMS 3 + +#elif defined(at91sam7a3) + + #define EFC_NUM_GPNVMS 0 +#endif + +// Missing FRDY bit for SAM7A3 +#if defined(at91sam7a3) + #define AT91C_MC_FRDY (AT91C_MC_EOP | AT91C_MC_EOL) +#endif + +// No security bit on SAM7A3 +#if defined(at91sam7a3) + #define EFC_NO_SECURITY_BIT +#endif + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +// For chips which do not define AT91S_EFC +#if !defined(AT91C_BASE_EFC) && !defined(AT91C_BASE_EFC0) +typedef struct _AT91S_EFC { + + AT91_REG EFC_FMR; + AT91_REG EFC_FCR; + AT91_REG EFC_FSR; + +} AT91S_EFC, *AT91PS_EFC; + #define AT91C_BASE_EFC (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) +#endif + +//------------------------------------------------------------------------------ +// Functions +//------------------------------------------------------------------------------ + +extern void EFC_SetMasterClock(unsigned int mck); + +extern void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources); + +extern void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources); + +extern void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable); + +extern void EFC_TranslateAddress( + unsigned int address, + AT91S_EFC **ppEfc, + unsigned short *pPage, + unsigned short *pOffset); + +extern void EFC_ComputeAddress( + AT91S_EFC *pEfc, + unsigned short page, + unsigned short offset, + unsigned int *pAddress); + +extern void EFC_StartCommand( + AT91S_EFC *pEfc, + unsigned char command, + unsigned short argument); + +extern unsigned char EFC_PerformCommand( + AT91S_EFC *pEfc, + unsigned char command, + unsigned short argument); + +extern unsigned int EFC_GetStatus(AT91S_EFC *pEfc); + +#endif //#ifdef BOARD_FLASH_EFC +#endif //#ifndef EFC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/emac/emac.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/emac/emac.c new file mode 100644 index 0000000..bc78725 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/emac/emac.c @@ -0,0 +1,833 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- +#include +#include "emac.h" +#include +#include +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ +/// The buffer addresses written into the descriptors must be aligned so the +/// last few bits are zero. These bits have special meaning for the EMAC +/// peripheral and cannot be used as part of the address. +#define EMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC) +#define EMAC_LENGTH_FRAME ((unsigned int)0x0FFF) /// Length of frame mask + +// receive buffer descriptor bits +#define EMAC_RX_OWNERSHIP_BIT (1UL << 0) +#define EMAC_RX_WRAP_BIT (1UL << 1) +#define EMAC_RX_SOF_BIT (1UL << 14) +#define EMAC_RX_EOF_BIT (1UL << 15) + +// Transmit buffer descriptor bits +#define EMAC_TX_LAST_BUFFER_BIT (1UL << 15) +#define EMAC_TX_WRAP_BIT (1UL << 30) +#define EMAC_TX_USED_BIT (1UL << 31) + +//----------------------------------------------------------------------------- +// Circular buffer management +//----------------------------------------------------------------------------- +// Return count in buffer +#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1)) + +// Return space available, 0..size-1 +// We always leave one free char as a completely full buffer +// has head == tail, which is the same as empty +#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) + +// Return count up to the end of the buffer. +// Carefully avoid accessing head and tail more than once, +// so they can change underneath us without returning inconsistent results +#define CIRC_CNT_TO_END(head,tail,size) \ + ({int end = (size) - (tail); \ + int n = ((head) + end) & ((size)-1); \ + n < end ? n : end;}) + +// Return space available up to the end of the buffer +#define CIRC_SPACE_TO_END(head,tail,size) \ + ({int end = (size) - 1 - (head); \ + int n = (end + (tail)) & ((size)-1); \ + n <= end ? n : end+1;}) + +// Increment head or tail +#define CIRC_INC(headortail,size) \ + headortail++; \ + if(headortail >= size) { \ + headortail = 0; \ + } + +#define CIRC_EMPTY(circ) ((circ)->head == (circ)->tail) +#define CIRC_CLEAR(circ) ((circ)->head = (circ)->tail = 0) + + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ +#ifdef __ICCARM__ // IAR +#pragma pack(4) // IAR +#define __attribute__(...) // IAR +#endif // IAR +/// Describes the type and attribute of Receive Transfer descriptor. +typedef struct _EmacRxTDescriptor { + unsigned int addr; + unsigned int status; +} __attribute__((packed, aligned(8))) EmacRxTDescriptor, *PEmacRxTDescriptor; + +/// Describes the type and attribute of Transmit Transfer descriptor. +typedef struct _EmacTxTDescriptor { + unsigned int addr; + unsigned int status; +} __attribute__((packed, aligned(8))) EmacTxTDescriptor, *PEmacTxTDescriptor; +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +/// Descriptors for RX (required aligned by 8) +typedef struct { + volatile EmacRxTDescriptor td[RX_BUFFERS]; + EMAC_RxCallback rxCb; /// Callback function to be invoked once a frame has been received + unsigned short idx; +} RxTd; + +/// Descriptors for TX (required aligned by 8) +typedef struct { + volatile EmacTxTDescriptor td[TX_BUFFERS]; + EMAC_TxCallback txCb[TX_BUFFERS]; /// Callback function to be invoked once TD has been processed + EMAC_WakeupCallback wakeupCb; /// Callback function to be invoked once several TD have been released + unsigned short wakeupThreshold; /// Number of free TD before wakeupCb is invoked + unsigned short head; /// Circular buffer head pointer incremented by the upper layer (buffer to be sent) + unsigned short tail; /// Circular buffer head pointer incremented by the IT handler (buffer sent) +} TxTd; + +//------------------------------------------------------------------------------ +// Internal variables +//------------------------------------------------------------------------------ +// Receive Transfer Descriptor buffer +#ifdef __ICCARM__ // IAR +#pragma data_alignment=8 // IAR +#endif // IAR +static volatile RxTd rxTd; +// Transmit Transfer Descriptor buffer +#ifdef __ICCARM__ // IAR +#pragma data_alignment=8 // IAR +#endif // IAR +static volatile TxTd txTd; +/// Send Buffer +// Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries. +// Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address shall be set to 0 +#ifdef __ICCARM__ // IAR +#pragma data_alignment=8 // IAR +#endif // IAR +static volatile unsigned char pTxBuffer[TX_BUFFERS * EMAC_TX_UNITSIZE] __attribute__((aligned(8))); + +#ifdef __ICCARM__ // IAR +#pragma data_alignment=8 // IAR +#endif // IAR +/// Receive Buffer +static volatile unsigned char pRxBuffer[RX_BUFFERS * EMAC_RX_UNITSIZE] __attribute__((aligned(8))); +/// Statistics +static volatile EmacStats EmacStatistics; + +//----------------------------------------------------------------------------- +// Internal functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Wait PHY operation complete. +/// Return 1 if the operation completed successfully. +/// May be need to re-implemented to reduce CPU load. +/// \param retry: the retry times, 0 to wait forever until complete. +//----------------------------------------------------------------------------- +static unsigned char EMAC_WaitPhy( unsigned int retry ) +{ + unsigned int retry_count = 0; + + while((AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE) == 0) { + + // Dead LOOP! + if (retry == 0) { + + continue; + } + + // Timeout check + retry_count++; + if(retry_count >= retry) { + + trace_LOG(trace_ERROR, "E: Wait PHY time out\n\r"); + return 0; + } + } + + return 1; +} + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// PHY management functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Set MDC clock according to current board clock. Per 802.3, MDC should be +/// less then 2.5MHz. +/// Return 1 if successfully, 0 if MDC clock not found. +//----------------------------------------------------------------------------- +unsigned char EMAC_SetMdcClock( unsigned int mck ) +{ + int clock_dividor; + + if (mck <= 20000000) { + clock_dividor = AT91C_EMAC_CLK_HCLK_8; /// MDC clock = MCK/8 + } + else if (mck <= 40000000) { + clock_dividor = AT91C_EMAC_CLK_HCLK_16; /// MDC clock = MCK/16 + } + else if (mck <= 80000000) { + clock_dividor = AT91C_EMAC_CLK_HCLK_32; /// MDC clock = MCK/32 + } + else if (mck <= 160000000) { + clock_dividor = AT91C_EMAC_CLK_HCLK_64; /// MDC clock = MCK/64 + } + else { + trace_LOG(trace_ERROR, "E: No valid MDC clock.\n\r"); + return 0; + } + AT91C_BASE_EMAC->EMAC_NCFGR = (AT91C_BASE_EMAC->EMAC_NCFGR & (~AT91C_EMAC_CLK)) + | clock_dividor; + return 1; +} + +//----------------------------------------------------------------------------- +/// Enable MDI with PHY +//----------------------------------------------------------------------------- +void EMAC_EnableMdio( void ) +{ + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; +} + +//----------------------------------------------------------------------------- +/// Enable MDI with PHY +//----------------------------------------------------------------------------- +void EMAC_DisableMdio( void ) +{ + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; +} + +//----------------------------------------------------------------------------- +/// Enable MII mode for EMAC, called once after autonegotiate +//----------------------------------------------------------------------------- +void EMAC_EnableMII( void ) +{ + AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN; +} + +//----------------------------------------------------------------------------- +/// Enable RMII mode for EMAC, called once after autonegotiate +//----------------------------------------------------------------------------- +void EMAC_EnableRMII( void ) +{ + AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN | AT91C_EMAC_RMII; +} + +//----------------------------------------------------------------------------- +/// Read PHY register. +/// Return 1 if successfully, 0 if timeout. +/// \param PhyAddress PHY Address +/// \param Address Register Address +/// \param pValue Pointer to a 32 bit location to store read data +/// \param retry The retry times, 0 to wait forever until complete. +//----------------------------------------------------------------------------- +unsigned char EMAC_ReadPhy(unsigned char PhyAddress, + unsigned char Address, + unsigned int *pValue, + unsigned int retry) +{ + AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30)) + | (AT91C_EMAC_CODE & (2 << 16)) + | (AT91C_EMAC_RW & (2 << 28)) + | (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23)) + | (AT91C_EMAC_REGA & (Address << 18)); + + if ( EMAC_WaitPhy(retry) == 0 ) { + + trace_LOG(trace_ERROR, "TimeOut EMAC_ReadPhy\n\r"); + return 0; + } + *pValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff ); + return 1; +} + +//----------------------------------------------------------------------------- +/// Write PHY register +/// Return 1 if successfully, 0 if timeout. +/// \param PhyAddress PHY Address +/// \param Address Register Address +/// \param Value Data to write ( Actually 16 bit data ) +/// \param retry The retry times, 0 to wait forever until complete. +//----------------------------------------------------------------------------- +unsigned char EMAC_WritePhy(unsigned char PhyAddress, + unsigned char Address, + unsigned int Value, + unsigned int retry) +{ + AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30)) + | (AT91C_EMAC_CODE & (2 << 16)) + | (AT91C_EMAC_RW & (1 << 28)) + | (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23)) + | (AT91C_EMAC_REGA & (Address << 18)) + | (AT91C_EMAC_DATA & Value) ; + if ( EMAC_WaitPhy(retry) == 0 ) { + + trace_LOG(trace_ERROR, "TimeOut EMAC_WritePhy\n\r"); + return 0; + } + return 1; +} + +//----------------------------------------------------------------------------- +/// Setup the EMAC for the link : speed 100M/10M and Full/Half duplex +/// \param speed Link speed, 0 for 10M, 1 for 100M +/// \param fullduplex 1 for Full Duplex mode +//----------------------------------------------------------------------------- +void EMAC_SetLinkSpeed(unsigned char speed, unsigned char fullduplex) +{ + unsigned int ncfgr; + + ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR; + ncfgr &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + if (speed) { + + ncfgr |= AT91C_EMAC_SPD; + } + if (fullduplex) { + + ncfgr |= AT91C_EMAC_FD; + } + AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr; +} + + + +//----------------------------------------------------------------------------- +// EMAC functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// EMAC Interrupt handler +//----------------------------------------------------------------------------- +void EMAC_Handler(void) +{ + volatile EmacTxTDescriptor *pTxTd; + volatile EMAC_TxCallback *pTxCb; + unsigned int isr; + unsigned int rsr; + unsigned int tsr; + unsigned int rxStatusFlag; + unsigned int txStatusFlag; + + //trace_LOG(trace_DEBUG, "EMAC_Handler\n\r"); + isr = AT91C_BASE_EMAC->EMAC_ISR & AT91C_BASE_EMAC->EMAC_IMR; + rsr = AT91C_BASE_EMAC->EMAC_RSR; + tsr = AT91C_BASE_EMAC->EMAC_TSR; + + // RX packet + if ((isr & AT91C_EMAC_RCOMP) || (rsr & AT91C_EMAC_REC)) { + rxStatusFlag = AT91C_EMAC_REC; + + // Frame received + EmacStatistics.rx_packets++; + + // Check OVR + if (rsr & AT91C_EMAC_OVR) { + rxStatusFlag |= AT91C_EMAC_OVR; + EmacStatistics.rx_ovrs++; + } + // Check BNA + if (rsr & AT91C_EMAC_BNA) { + rxStatusFlag |= AT91C_EMAC_BNA; + EmacStatistics.rx_bnas++; + } + // Clear status + AT91C_BASE_EMAC->EMAC_RSR |= rxStatusFlag; + + // Invoke callbacks + if (rxTd.rxCb) { + rxTd.rxCb(rxStatusFlag); + } + } + + // TX packet + if ((isr & AT91C_EMAC_TCOMP) || (tsr & AT91C_EMAC_COMP)) { + + txStatusFlag = AT91C_EMAC_COMP; + EmacStatistics.tx_comp ++; + + // A frame transmitted + // Check RLE + if (tsr & AT91C_EMAC_RLES) { + txStatusFlag |= AT91C_EMAC_RLES; + EmacStatistics.tx_errors++; + } + // Check COL + if (tsr & AT91C_EMAC_COL) { + txStatusFlag |= AT91C_EMAC_COL; + EmacStatistics.collisions++; + } + // Check BEX + if (tsr & AT91C_EMAC_BEX) { + txStatusFlag |= AT91C_EMAC_BEX; + EmacStatistics.tx_exausts++; + } + // Check UND + if (tsr & AT91C_EMAC_UND) { + txStatusFlag |= AT91C_EMAC_UND; + EmacStatistics.tx_underruns++; + } + // Clear status + AT91C_BASE_EMAC->EMAC_TSR |= txStatusFlag; + + // Sanity check: Tx buffers have to be scheduled + ASSERT(!CIRC_EMPTY(&txTd), + "-F- EMAC Tx interrupt received meanwhile no TX buffers has been scheduled\n\r"); + + // Check the buffers + while (CIRC_CNT(txTd.head, txTd.tail, TX_BUFFERS)) { + pTxTd = txTd.td + txTd.tail; + pTxCb = txTd.txCb + txTd.tail; + + // Exit if buffer has not been sent yet + if ((pTxTd->status & EMAC_TX_USED_BIT) == 0) { + break; + } + + // Notify upper layer that packet has been sent + if (*pTxCb) { + (*pTxCb)(txStatusFlag); + } + + CIRC_INC( txTd.tail, TX_BUFFERS ); + } + + // If a wakeup has been scheduled, notify upper layer that it can send + // other packets, send will be successfull. + if( (CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) >= txTd.wakeupThreshold) + && txTd.wakeupCb) { + txTd.wakeupCb(); + } + } +} + +//----------------------------------------------------------------------------- +/// Initialize the EMAC with the emac controller address +/// \param id HW ID for power management +/// \param pTxWakeUpfct Thresold TX Wakeup Callback +/// \param pRxfct RX Wakeup Callback +/// \param pMacAddress Mac Address +/// \param enableCAF enable AT91C_EMAC_CAF if needed by application +/// \param enableNBC AT91C_EMAC_NBC if needed by application +//----------------------------------------------------------------------------- +void EMAC_Init( unsigned char id, const unsigned char *pMacAddress, + unsigned char enableCAF, unsigned char enableNBC ) +{ + int Index; + unsigned int Address; + + // Check parameters + ASSERT(RX_BUFFERS * EMAC_RX_UNITSIZE > EMAC_FRAME_LENTGH_MAX, + "E: RX buffers too small\n\r"); + + trace_LOG(trace_DEBUG, "EMAC_Init\n\r"); + + // Power ON + AT91C_BASE_PMC->PMC_PCER = 1 << id; + + // Disable TX & RX and more + AT91C_BASE_EMAC->EMAC_NCR = 0; + + // disable + AT91C_BASE_EMAC->EMAC_IDR = ~0; + + rxTd.idx = 0; + CIRC_CLEAR(&txTd); + + // Setup the RX descriptors. + for(Index = 0; Index < RX_BUFFERS; Index++) { + + Address = (unsigned int)(&(pRxBuffer[Index * EMAC_RX_UNITSIZE])); + // Remove EMAC_RX_OWNERSHIP_BIT and EMAC_RX_WRAP_BIT + rxTd.td[Index].addr = Address & EMAC_ADDRESS_MASK; + rxTd.td[Index].status = 0; + } + rxTd.td[RX_BUFFERS - 1].addr |= EMAC_RX_WRAP_BIT; + + // Setup the TX descriptors. + for(Index = 0; Index < TX_BUFFERS; Index++) { + + Address = (unsigned int)(&(pTxBuffer[Index * EMAC_TX_UNITSIZE])); + txTd.td[Index].addr = Address; + txTd.td[Index].status = EMAC_TX_USED_BIT; + } + txTd.td[TX_BUFFERS - 1].status = EMAC_TX_USED_BIT | EMAC_TX_WRAP_BIT; + + // Set the MAC address + if( pMacAddress != (unsigned char *)0 ) { + AT91C_BASE_EMAC->EMAC_SA1L = ( ((unsigned int)pMacAddress[3] << 24) + | ((unsigned int)pMacAddress[2] << 16) + | ((unsigned int)pMacAddress[1] << 8 ) + | pMacAddress[0] ); + + AT91C_BASE_EMAC->EMAC_SA1H = ( ((unsigned int)pMacAddress[5] << 8 ) + | pMacAddress[4] ); + } + // Now setup the descriptors + // Receive Buffer Queue Pointer Register + AT91C_BASE_EMAC->EMAC_RBQP = (unsigned int) (rxTd.td); + // Transmit Buffer Queue Pointer Register + AT91C_BASE_EMAC->EMAC_TBQP = (unsigned int) (txTd.td); + + AT91C_BASE_EMAC->EMAC_NCR = AT91C_EMAC_CLRSTAT; + + // Clear all status bits in the receive status register. + AT91C_BASE_EMAC->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); + + // Clear all status bits in the transmit status register + AT91C_BASE_EMAC->EMAC_TSR = ( AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES + | AT91C_EMAC_BEX | AT91C_EMAC_COMP + | AT91C_EMAC_UND ); + + // Clear interrupts + AT91C_BASE_EMAC->EMAC_ISR; + + // Enable the copy of data into the buffers + // ignore broadcasts, and don't copy FCS. + AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_DRFCS | AT91C_EMAC_PAE); + + if( enableCAF == EMAC_CAF_ENABLE ) { + AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_CAF; + } + if( enableNBC == EMAC_NBC_ENABLE ) { + AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_NBC; + } + + // Enable Rx and Tx, plus the stats register. + AT91C_BASE_EMAC->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT); + + // Setup the interrupts for TX (and errors) + AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RXUBR + | AT91C_EMAC_TUNDR + | AT91C_EMAC_RLEX + | AT91C_EMAC_TXERR + | AT91C_EMAC_TCOMP + | AT91C_EMAC_ROVR + | AT91C_EMAC_HRESP; + +} + +//----------------------------------------------------------------------------- +/// Get the statstic information & reset it +/// \param pStats Pointer to EmacStats structure to copy the informations +/// \param reset Reset the statistics after copy it +//----------------------------------------------------------------------------- +void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset) +{ + unsigned int ncrBackup = 0; + + trace_LOG(trace_DEBUG, "EMAC_GetStatistics\n\r"); + + // Sanity check + if (pStats == (EmacStats *) 0) { + return; + } + + ncrBackup = AT91C_BASE_EMAC->EMAC_NCR & (AT91C_EMAC_TE | AT91C_EMAC_RE); + + // Disable TX/RX + AT91C_BASE_EMAC->EMAC_NCR = ncrBackup & ~(AT91C_EMAC_TE | AT91C_EMAC_RE); + + // Copy the informations + memcpy(pStats, (void*)&EmacStatistics, sizeof(EmacStats)); + + // Reset the statistics + if (reset) { + memset((void*)&EmacStatistics, 0x00, sizeof(EmacStats)); + AT91C_BASE_EMAC->EMAC_NCR = ncrBackup | AT91C_EMAC_CLRSTAT; + } + + // restore NCR + AT91C_BASE_EMAC->EMAC_NCR = ncrBackup; +} + +//----------------------------------------------------------------------------- +/// Send a packet with EMAC. +/// If the packet size is larger than transfer buffer size error returned. +/// \param buffer The buffer to be send +/// \param size The size of buffer to be send +/// \param fEMAC_TxCallback Threshold Wakeup callback +/// \param fWakeUpCb TX Wakeup +/// \return OK, Busy or invalid packet +//----------------------------------------------------------------------------- +unsigned char EMAC_Send(void *pBuffer, + unsigned int size, + EMAC_TxCallback fEMAC_TxCallback) +{ + volatile EmacTxTDescriptor *pTxTd; + volatile EMAC_TxCallback *pTxCb; + + //trace_LOG(trace_DEBUG, "EMAC_Send\n\r"); + + // Check parameter + if (size > EMAC_TX_UNITSIZE) { + + trace_LOG(trace_ERROR, "-E- EMAC driver does not split send packets."); + trace_LOG(trace_ERROR, " It can send %d bytes max in one packet (%u bytes requested)\n\r", + EMAC_TX_UNITSIZE, size); + return EMAC_TX_INVALID_PACKET; + } + + // If no free TxTd, buffer can't be sent, schedule the wakeup callback + if( CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) == 0) { + return EMAC_TX_BUFFER_BUSY; + + } + + // Pointers to the current TxTd + pTxTd = txTd.td + txTd.head; + pTxCb = txTd.txCb + txTd.head; + + // Sanity check + ASSERT((pTxTd->status & EMAC_TX_USED_BIT) != 0, + "-F- Buffer is still under EMAC control\n\r"); + + // Setup/Copy data to transmition buffer + if (pBuffer && size) { + // Driver manage the ring buffer + memcpy((void *)pTxTd->addr, pBuffer, size); + } + + // Tx Callback + *pTxCb = fEMAC_TxCallback; + + // Update TD status + // The buffer size defined is length of ethernet frame + // so it's always the last buffer of the frame. + if (txTd.head == TX_BUFFERS-1) { + pTxTd->status = + (size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT | EMAC_TX_WRAP_BIT; + } + else { + pTxTd->status = (size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT; + } + + CIRC_INC(txTd.head, TX_BUFFERS) + + // Tx packets count + EmacStatistics.tx_packets++; + + // Now start to transmit if it is not already done + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART; + + return EMAC_TX_OK; +} + +//----------------------------------------------------------------------------- +/// Receive a packet with EMAC +/// If not enough buffer for the packet, the remaining data is lost but right +/// frame length is returned. +/// \param pFrame Buffer to store the frame +/// \param frameSize Size of the frame +/// \param pRcvSize Received size +/// \return OK, no data, or frame too small +//----------------------------------------------------------------------------- +unsigned char EMAC_Poll(unsigned char *pFrame, + unsigned int frameSize, + unsigned int *pRcvSize) +{ + unsigned short bufferLength; + unsigned int tmpFrameSize=0; + unsigned char *pTmpFrame=0; + unsigned int tmpIdx = rxTd.idx; + volatile EmacRxTDescriptor *pRxTd = rxTd.td + rxTd.idx; + + ASSERT(pFrame, "F: EMAC_Poll\n\r"); + + char isFrame = 0; + // Set the default return value + *pRcvSize = 0; + + // Process received RxTd + while ((pRxTd->addr & EMAC_RX_OWNERSHIP_BIT) == EMAC_RX_OWNERSHIP_BIT) { + + // A start of frame has been received, discard previous fragments + if ((pRxTd->status & EMAC_RX_SOF_BIT) == EMAC_RX_SOF_BIT) { + // Skip previous fragment + while (tmpIdx != rxTd.idx) { + pRxTd = rxTd.td + rxTd.idx; + pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT); + CIRC_INC(rxTd.idx, RX_BUFFERS); + } + // Reset the temporary frame pointer + pTmpFrame = pFrame; + tmpFrameSize = 0; + // Start to gather buffers in a frame + isFrame = 1; + } + + // Increment the pointer + CIRC_INC(tmpIdx, RX_BUFFERS); + + // Copy data in the frame buffer + if (isFrame) { + if (tmpIdx == rxTd.idx) { + trace_LOG(trace_INFO, + "I: no EOF (Invalid of buffers too small)\n\r"); + + do { + + pRxTd = rxTd.td + rxTd.idx; + pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT); + CIRC_INC(rxTd.idx, RX_BUFFERS); + } while(tmpIdx != rxTd.idx); + return EMAC_RX_NO_DATA; + } + // Copy the buffer into the application frame + bufferLength = EMAC_RX_UNITSIZE; + if ((tmpFrameSize + bufferLength) > frameSize) { + bufferLength = frameSize - tmpFrameSize; + } + + memcpy(pTmpFrame, (void*)(pRxTd->addr & EMAC_ADDRESS_MASK), bufferLength); + pTmpFrame += bufferLength; + tmpFrameSize += bufferLength; + + // An end of frame has been received, return the data + if ((pRxTd->status & EMAC_RX_EOF_BIT) == EMAC_RX_EOF_BIT) { + // Frame size from the EMAC + *pRcvSize = (pRxTd->status & EMAC_LENGTH_FRAME); + + // Application frame buffer is too small all data have not been copied + if (tmpFrameSize < *pRcvSize) { + printf("size req %u size allocated %u\n\r", *pRcvSize, frameSize); + + return EMAC_RX_FRAME_SIZE_TOO_SMALL; + } + + trace_LOG(trace_INFO, "packet %d-%u (%u)\n\r", rxTd.idx, tmpIdx, *pRcvSize); + // All data have been copied in the application frame buffer => release TD + while (rxTd.idx != tmpIdx) { + pRxTd = rxTd.td + rxTd.idx; + pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT); + CIRC_INC(rxTd.idx, RX_BUFFERS); + } + EmacStatistics.rx_packets++; + return EMAC_RX_OK; + } + } + + // SOF has not been detected, skip the fragment + else { + pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT); + rxTd.idx = tmpIdx; + } + + // Process the next buffer + pRxTd = rxTd.td + tmpIdx; + } + + //trace_LOG(trace_DEBUG, "E"); + return EMAC_RX_NO_DATA; +} + +//----------------------------------------------------------------------------- +/// Registers pRxCb callback. Callback will be invoked after the next received +/// frame. +/// When EMAC_Poll() returns EMAC_RX_NO_DATA the application task call EMAC_Set_RxCb() +/// to register pRxCb() callback and enters suspend state. The callback is in charge +/// to resume the task once a new frame has been received. The next time EMAC_Poll() +/// is called, it will be successfull. +/// \param pRxCb Pointer to callback function +//----------------------------------------------------------------------------- +void EMAC_Set_RxCb(EMAC_RxCallback pRxCb) +{ + rxTd.rxCb = pRxCb; + AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP; +} + +//----------------------------------------------------------------------------- +/// Remove the RX callback function. +/// This function is usually invoked from the RX callback itself. Once the callback +/// has resumed the application task, there is no need to invoke the callback again. +//----------------------------------------------------------------------------- +void EMAC_Clear_RxCb(void) +{ + AT91C_BASE_EMAC->EMAC_IDR = AT91C_EMAC_RCOMP; + rxTd.rxCb = (EMAC_RxCallback) 0; +} + +//----------------------------------------------------------------------------- +/// Registers TX wakeup callback callback. Callback will be invoked once several +/// transfer descriptors are available. +/// When EMAC_Send() returns EMAC_TX_BUFFER_BUSY (all TD busy) the application +/// task calls EMAC_Set_TxWakeUpCb() to register pTxWakeUpCb() callback and +/// enters suspend state. The callback is in charge to resume the task once +/// several TD have been released. The next time EMAC_Send() will be called, it +/// shall be successfull. +/// \param pTxWakeUpCb Pointer to callback function +/// \param threshold Minimum number of available transfer descriptors before pTxWakeUpCb() is invoked +/// \return 0= success, 1 = threshold exceeds nuber of transfer descriptors +//----------------------------------------------------------------------------- +char EMAC_Set_TxWakeUpCb(EMAC_WakeupCallback pTxWakeUpCb, unsigned short threshold) +{ + if (threshold <= TX_BUFFERS) { + txTd.wakeupCb = pTxWakeUpCb; + txTd.wakeupThreshold = threshold; + return 0; + } + return 1; +} + +//----------------------------------------------------------------------------- +/// Remove the TX wakeup callback function. +/// This function is usually invoked from the TX wakeup callback itself. Once the callback +/// has resumed the application task, there is no need to invoke the callback again. +//----------------------------------------------------------------------------- +void EMAC_Clear_TxWakeUpCb(void) +{ + txTd.wakeupCb = (EMAC_WakeupCallback) 0; +} + + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/emac/emac.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/emac/emac.h new file mode 100644 index 0000000..992c908 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/emac/emac.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +// peripherals/emac/emac.h + +#ifndef EMAC_H +#define EMAC_H + +//----------------------------------------------------------------------------- +/// \dir +/// !Purpose +/// +/// Definition of methods and structures for using EMAC +/// +/// !Usage +/// +/// -# Initialize EMAC with EMAC_Init. +/// -# Setup EMAC with EMAC_SetupTx, EMAC_SetupRx, EMAC_SetupMacAddress +/// and EMAC_SetupStack. +/// -# Drive the EMAC status machine by EMAC_Task. +/// -# EMAC_GetStatus give EMAC status machine current status +/// -# Send a packet to network with EMAC_SendPacket. +/// -# Get a packet from network with EMAC_GetPacket. +/// +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Definitions +//----------------------------------------------------------------------------- +/// Number of buffer for RX, be carreful: MUST be 2^n +#define RX_BUFFERS 16 +/// Number of buffer for TX, be carreful: MUST be 2^n +#define TX_BUFFERS 8 + +/// Buffer Size +#define EMAC_RX_UNITSIZE 128 /// Fixed size for RX buffer +#define EMAC_TX_UNITSIZE 1518 /// Size for ETH frame length + +// The MAC can support frame lengths up to 1536 bytes. +#define EMAC_FRAME_LENTGH_MAX 1536 + + +//----------------------------------------------------------------------------- +// Types +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Describes the statistics of the EMAC. +//----------------------------------------------------------------------------- +typedef struct _EmacStats { + + // TX errors + unsigned int tx_packets; /// Total Number of packets sent + unsigned int tx_comp; /// Packet complete + unsigned int tx_errors; /// TX errors ( Retry Limit Exceed ) + unsigned int collisions; /// Collision + unsigned int tx_exausts; /// Buffer exhausted + unsigned int tx_underruns; /// Under Run, not able to read from memory + // RX errors + unsigned int rx_packets; /// Total Number of packets RX + unsigned int rx_eof; /// No EOF error + unsigned int rx_ovrs; /// Over Run, not able to store to memory + unsigned int rx_bnas; /// Buffer is not available + +} EmacStats, *PEmacStats; + +//----------------------------------------------------------------------------- +// PHY Exported functions +//----------------------------------------------------------------------------- +extern unsigned char EMAC_SetMdcClock( unsigned int mck ); + +extern void EMAC_EnableMdio( void ); + +extern void EMAC_DisableMdio( void ); + +extern void EMAC_EnableMII( void ); + +extern void EMAC_EnableRMII( void ); + +extern unsigned char EMAC_ReadPhy(unsigned char PhyAddress, + unsigned char Address, + unsigned int *pValue, + unsigned int retry); + +extern unsigned char EMAC_WritePhy(unsigned char PhyAddress, + unsigned char Address, + unsigned int Value, + unsigned int retry); + +extern void EMAC_SetLinkSpeed(unsigned char speed, + unsigned char fullduplex); + +//----------------------------------------------------------------------------- +// EMAC Exported functions +//----------------------------------------------------------------------------- +/// Callback used by send function +typedef void (*EMAC_TxCallback)(unsigned int status); +typedef void (*EMAC_RxCallback)(unsigned int status); +typedef void (*EMAC_WakeupCallback)(void); + +extern void EMAC_Init( unsigned char id, const unsigned char *pMacAddress, + unsigned char enableCAF, unsigned char enableNBC ); +#define EMAC_CAF_DISABLE 0 +#define EMAC_CAF_ENABLE 1 +#define EMAC_NBC_DISABLE 0 +#define EMAC_NBC_ENABLE 1 + +extern void EMAC_Handler(void); + +extern unsigned char EMAC_Send(void *pBuffer, + unsigned int size, + EMAC_TxCallback fEMAC_TxCallback); +/// Return for EMAC_Send function +#define EMAC_TX_OK 0 +#define EMAC_TX_BUFFER_BUSY 1 +#define EMAC_TX_INVALID_PACKET 2 + + +extern unsigned char EMAC_Poll(unsigned char *pFrame, + unsigned int frameSize, + unsigned int *pRcvSize); +/// Return for EMAC_Poll function +#define EMAC_RX_OK 0 +#define EMAC_RX_NO_DATA 1 +#define EMAC_RX_FRAME_SIZE_TOO_SMALL 2 + +extern void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset); + +#endif // #ifndef EMAC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.c new file mode 100644 index 0000000..b5a8d69 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.c @@ -0,0 +1,362 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "lcd.h" +#include +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Enables the LCD controller, after waiting for the specified number of +/// frames. +/// \param frames Number of frames before the LCD is enabled. +//------------------------------------------------------------------------------ +void LCD_Enable(unsigned int frames) +{ + ASSERT((frames & 0xFFFFFF80) == 0, + "LCD_Enable: Wrong frames value.\n\r"); + AT91C_BASE_LCDC->LCDC_PWRCON = AT91C_LCDC_PWR | (frames << 1); +} + +//------------------------------------------------------------------------------ +/// Disables the LCD controller, after waiting for the specified number of +/// frames. +/// \param frames Number of frames before the LCD is shut down. +//------------------------------------------------------------------------------ +void LCD_Disable(unsigned int frames) +{ + ASSERT((frames & 0xFFFFFF80) == 0, + "LCD_Disable: Wrong frames value.\n\r"); + AT91C_BASE_LCDC->LCDC_PWRCON = frames << 1; +} + +//------------------------------------------------------------------------------ +/// Enables the DMA of the LCD controller. +//------------------------------------------------------------------------------ +void LCD_EnableDma() +{ + AT91C_BASE_LCDC->LCDC_DMACON = AT91C_LCDC_DMAEN; +} + +//------------------------------------------------------------------------------ +/// Disables the DMA of the LCD controller. +//------------------------------------------------------------------------------ +void LCD_DisableDma() +{ + AT91C_BASE_LCDC->LCDC_DMACON = 0; +} + +//------------------------------------------------------------------------------ +/// Configures the internal clock of the LCD controller given the master clock of +/// the system and the desired pixel clock in MHz. +/// \param masterClock Master clock frequency. +/// \param pixelClock Pixel clock frequency. +//------------------------------------------------------------------------------ +void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock) +{ + AT91C_BASE_LCDC->LCDC_LCDCON1 = ((masterClock / (2 * pixelClock)) - 1) << 12; +} + +//------------------------------------------------------------------------------ +/// Sets the type of display used with the LCD controller. +/// \param displayType Type of display used. +//------------------------------------------------------------------------------ +void LCD_SetDisplayType(unsigned int displayType) +{ + unsigned int value; + + ASSERT((displayType & ~AT91C_LCDC_DISTYPE) == 0, + "LCD_SetDisplayType: Wrong display type value.\n\r"); + + value = AT91C_BASE_LCDC->LCDC_LCDCON2; + value &= ~AT91C_LCDC_DISTYPE; + value |= displayType; + AT91C_BASE_LCDC->LCDC_LCDCON2 = value; +} + +//------------------------------------------------------------------------------ +/// Sets the scan mode used by the LCD (either single scan or double-scan). +/// \param scanMode Scan mode to use. +//------------------------------------------------------------------------------ +void LCD_SetScanMode(unsigned int scanMode) +{ + unsigned int value; + + ASSERT((scanMode & ~AT91C_LCDC_SCANMOD) == 0, + "LCD_SetScanMode: Wrong scan mode value.\n\r"); + + value = AT91C_BASE_LCDC->LCDC_LCDCON2; + value &= ~AT91C_LCDC_SCANMOD; + value |= scanMode; + AT91C_BASE_LCDC->LCDC_LCDCON2 = value; +} + +//------------------------------------------------------------------------------ +/// Sets the number of bits per pixel used by the LCD display. +/// \param bitsPerPixel Number of bits per pixel to use. +//------------------------------------------------------------------------------ +void LCD_SetBitsPerPixel(unsigned int bitsPerPixel) +{ + unsigned int value; + + ASSERT((bitsPerPixel & ~AT91C_LCDC_PIXELSIZE) == 0, + "LCD_SetScanMode: Wrong bitsPerPixel value.\n\r"); + + value = AT91C_BASE_LCDC->LCDC_LCDCON2; + value &= ~AT91C_LCDC_PIXELSIZE; + value |= bitsPerPixel; + AT91C_BASE_LCDC->LCDC_LCDCON2 = value; +} + +//------------------------------------------------------------------------------ +/// Sets the LCDD, LCDVSYNC, LCDHSYNC, LCDDOTCLK and LCDDEN signal polarities. +/// \param lcdd LCDD signal polarity. +/// \param lcdvsync LCDVSYNC signal polarity. +/// \param lcdhsync LCDHSYNC signal polarity. +/// \param lcddotclk LCDDOTCLK signal polarity. +/// \param lcdden LCDDEN signal polarity. +//------------------------------------------------------------------------------ +void LCD_SetPolarities( + unsigned int lcdd, + unsigned int lcdvsync, + unsigned int lcdhsync, + unsigned int lcddotclk, + unsigned int lcdden) +{ + unsigned int value; + + ASSERT((lcdd & ~AT91C_LCDC_INVVD) == 0, + "LCD_SetPolarities: Wrong lcdd value.\n\r"); + ASSERT((lcdvsync & ~AT91C_LCDC_INVFRAME) == 0, + "LCD_SetPolarities: Wrong lcdvsync value.\n\r"); + ASSERT((lcdhsync & ~AT91C_LCDC_INVLINE) == 0, + "LCD_SetPolarities: Wrong lcdhsync value.\n\r"); + ASSERT((lcddotclk & ~AT91C_LCDC_INVCLK) == 0, + "LCD_SetPolarities: Wrong lcddotclk value.\n\r"); + ASSERT((lcdden & ~AT91C_LCDC_INVDVAL) == 0, + "LCD_SetPolarities: Wrong lcdden value.\n\r"); + + value = AT91C_BASE_LCDC->LCDC_LCDCON2; + value &= 0xFFFFE0FF; + value |= lcdd | lcdvsync | lcdhsync | lcddotclk | lcdden; + AT91C_BASE_LCDC->LCDC_LCDCON2 = value; +} + +//------------------------------------------------------------------------------ +/// Sets the LCD clock mode, i.e. always active or active only during display +/// period. +/// \param clockMode Clock mode to use. +//------------------------------------------------------------------------------ +void LCD_SetClockMode(unsigned int clockMode) +{ + unsigned int value; + + ASSERT((clockMode & ~AT91C_LCDC_CLKMOD) == 0, + "LCD_SetScanMode: Wrong scan mode value.\n\r"); + + value = AT91C_BASE_LCDC->LCDC_LCDCON2; + value &= ~AT91C_LCDC_CLKMOD; + value |= clockMode; + AT91C_BASE_LCDC->LCDC_LCDCON2 = value; +} + +//------------------------------------------------------------------------------ +/// Sets the format of the frame buffer memory. +/// \param format Memory ordering format. +//------------------------------------------------------------------------------ +void LCD_SetMemoryFormat(unsigned int format) +{ + unsigned int value; + + ASSERT((format & ~AT91C_LCDC_MEMOR) == 0, + "LCD_SetMemoryFormat: Wrong memory format value.\n\r"); + + value = AT91C_BASE_LCDC->LCDC_LCDCON2; + value &= ~AT91C_LCDC_MEMOR; + value |= format; + AT91C_BASE_LCDC->LCDC_LCDCON2 = value; +} + +//------------------------------------------------------------------------------ +/// Sets the size in pixel of the LCD display. +/// \param width Width in pixel of the LCD display. +/// \param height Height in pixel of the LCD display. +//------------------------------------------------------------------------------ +void LCD_SetSize(unsigned int width, unsigned int height) +{ + ASSERT(((width - 1) & 0xFFFFF800) == 0, + "LCD_SetSize: Wrong width value.\n\r"); + ASSERT(((height - 1) & 0xFFFFF800) == 0, + "LCD_SetSize: Wrong height value.\n\r"); + + AT91C_BASE_LCDC->LCDC_LCDFRCFG = ((width - 1) << 21) | (height - 1); +} + +//------------------------------------------------------------------------------ +/// Sets the vertical timings of the LCD controller. Only meaningful when +/// using a TFT display. +/// \param vfp Number of idle lines at the end of a frame. +/// \param vbp Number of idle lines at the beginning of a frame. +/// \param vpw Vertical synchronization pulse width in number of lines. +/// \param vhdly Delay between LCDVSYNC edge and LCDHSYNC rising edge, in +/// LCDDOTCLK cycles. +//------------------------------------------------------------------------------ +void LCD_SetVerticalTimings( + unsigned int vfp, + unsigned int vbp, + unsigned int vpw, + unsigned int vhdly) +{ + ASSERT((vfp & 0xFFFFFF00) == 0, + "LCD_SetVerticalTimings: Wrong vfp value.\n\r"); + ASSERT((vbp & 0xFFFFFF00) == 0, + "LCD_SetVerticalTimings: Wrong vbp value.\n\r"); + ASSERT(((vpw-1) & 0xFFFFFFC0) == 0, + "LCD_SetVerticalTimings: Wrong vpw value.\n\r"); + ASSERT(((vhdly-1) & 0xFFFFFFF0) == 0, + "LCD_SetVerticalTimings: Wrong vhdly value.\n\r"); + + AT91C_BASE_LCDC->LCDC_TIM1 = vfp + | (vbp << 8) + | ((vpw-1) << 16) + | ((vhdly-1) << 24); +} + +//------------------------------------------------------------------------------ +/// Sets the horizontal timings of the LCD controller. Meaningful for both +/// STN and TFT displays. +/// \param hbp Number of idle LCDDOTCLK cycles at the beginning of a line. +/// \param hpw Width of the LCDHSYNC pulse, in LCDDOTCLK cycles. +/// \param hfp Number of idel LCDDOTCLK cycles at the end of a line. +//------------------------------------------------------------------------------ +void LCD_SetHorizontalTimings( + unsigned int hbp, + unsigned int hpw, + unsigned int hfp) +{ + ASSERT(((hbp-1) & 0xFFFFFF00) == 0, + "LCD_SetHorizontalTimings: Wrong hbp value.\n\r"); + ASSERT(((hpw-1) & 0xFFFFFFC0) == 0, + "LCD_SetHorizontalTimings: Wrong hpw value.\n\r"); + ASSERT(((hfp-1) & 0xFFFFFF00) == 0, + "LCD_SetHorizontalTimings: Wrong hfp value.\n\r"); + + AT91C_BASE_LCDC->LCDC_TIM2 = (hbp-1) | ((hpw-1) << 8) | ((hfp-1) << 24); +} + +//------------------------------------------------------------------------------ +/// Sets the address of the frame buffer in the LCD controller DMA. When using +/// dual-scan mode, this is the upper frame buffer. +/// \param address Frame buffer address. +//------------------------------------------------------------------------------ +void LCD_SetFrameBufferAddress(void *address) +{ + AT91C_BASE_LCDC->LCDC_BA1 = (unsigned int) address; +} + +//------------------------------------------------------------------------------ +/// Sets the size in pixels of a frame (height * width * bpp). +/// \param frameSize Size of frame in pixels. +//------------------------------------------------------------------------------ +void LCD_SetFrameSize(unsigned int frameSize) +{ + ASSERT((frameSize & 0xFF800000) == 0, + "LCD_SetFrameSize: Wrong frameSize value.\n\r"); + + AT91C_BASE_LCDC->LCDC_FRMCFG = frameSize | (AT91C_BASE_LCDC->LCDC_FRMCFG & 0xFF000000); +} + +//------------------------------------------------------------------------------ +/// Sets the DMA controller burst length. +/// \param burstLength Desired burst length. +//------------------------------------------------------------------------------ +void LCD_SetBurstLength(unsigned int burstLength) +{ + ASSERT(((burstLength-1) & 0xFFFFFF80) == 0, + "LCD_SetBurstLength: Wrong burstLength value.\n\r"); + + AT91C_BASE_LCDC->LCDC_FRMCFG &= 0x00FFFFFF; + AT91C_BASE_LCDC->LCDC_FRMCFG |= ((burstLength-1) << 24); + + AT91C_BASE_LCDC->LCDC_FIFO = 2048 - (2 * burstLength + 3); +} + +//------------------------------------------------------------------------------ +/// Sets the prescaler value of the contrast control PWM. +/// \param prescaler Desired prescaler value. +//------------------------------------------------------------------------------ +void LCD_SetContrastPrescaler(unsigned int prescaler) +{ + ASSERT((prescaler & ~AT91C_LCDC_PS) == 0, + "LCD_SetContrastPrescaler: Wrong prescaler value\n\r"); + + AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_PS; + AT91C_BASE_LCDC->LCDC_CTRSTCON |= prescaler; +} + +//------------------------------------------------------------------------------ +/// Sets the polarity of the contrast PWM. +/// \param polarity PWM polarity +//------------------------------------------------------------------------------ +void LCD_SetContrastPolarity(unsigned int polarity) +{ + ASSERT((polarity & ~AT91C_LCDC_POL) == 0, + "LCD_SetContrastPolarity: Wrong polarity value\n\r"); + + AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_POL; + AT91C_BASE_LCDC->LCDC_CTRSTCON |= polarity; +} + +//------------------------------------------------------------------------------ +/// Sets the threshold value of the constrast PWM. +/// \param value PWM threshold value. +//------------------------------------------------------------------------------ +void LCD_SetContrastValue(unsigned int value) +{ + ASSERT((value & ~AT91C_LCDC_CVAL) == 0, + "LCD_SetContrastValue: Wrong value.\n\r"); + + AT91C_BASE_LCDC->LCDC_CTRSTVAL = value; +} + +//------------------------------------------------------------------------------ +/// Enables the contrast PWM generator. +//------------------------------------------------------------------------------ +void LCD_EnableContrast() +{ + AT91C_BASE_LCDC->LCDC_CTRSTCON |= AT91C_LCDC_ENA_PWMGEMENABLED; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.h new file mode 100644 index 0000000..35d6be0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.h @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef LCD_H +#define LCD_H + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void LCD_Enable(unsigned int frames); + +extern void LCD_Disable(unsigned int frames); + +extern void LCD_EnableDma(); + +extern void LCD_DisableDma(); + +extern void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock); + +extern void LCD_SetDisplayType(unsigned int displayType); + +extern void LCD_SetScanMode(unsigned int scanMode); + +extern void LCD_SetBitsPerPixel(unsigned int bitsPerPixel); + +extern void LCD_SetPolarities( + unsigned int lcdd, + unsigned int lcdvsync, + unsigned int lcdhsync, + unsigned int lcddotclk, + unsigned int lcdden); + +extern void LCD_SetClockMode(unsigned int clockMode); + +extern void LCD_SetMemoryFormat(unsigned int format); + +extern void LCD_SetSize(unsigned int width, unsigned int height); + +extern void LCD_SetVerticalTimings( + unsigned int vfp, + unsigned int vbp, + unsigned int vpw, + unsigned int vhdly); + +extern void LCD_SetHorizontalTimings( + unsigned int hbp, + unsigned int hpw, + unsigned int hfp); + +extern void LCD_SetFrameBufferAddress(void *address); + +extern void LCD_SetFrameSize(unsigned int frameSize); + +extern void LCD_SetBurstLength(unsigned int burstLength); + +extern void LCD_SetContrastPrescaler(unsigned int prescaler); + +extern void LCD_SetContrastPolarity(unsigned int polarity); + +extern void LCD_SetContrastValue(unsigned int value); + +extern void LCD_EnableContrast(); + +#endif //#ifndef LCD_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/mci/mci.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/mci/mci.c new file mode 100644 index 0000000..a442a51 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/mci/mci.c @@ -0,0 +1,551 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "mci.h" +#include +#include + +//------------------------------------------------------------------------------ +// Local constants +//------------------------------------------------------------------------------ + +/// Bit mask for status register errors. +#define STATUS_ERRORS (AT91C_MCI_UNRE \ + | AT91C_MCI_OVRE \ + | AT91C_MCI_DTOE \ + | AT91C_MCI_DCRCE \ + | AT91C_MCI_RTOE \ + | AT91C_MCI_RENDE \ + | AT91C_MCI_RCRCE \ + | AT91C_MCI_RDIRE \ + | AT91C_MCI_RINDE) + +/// MCI data timeout configuration with 1048576 MCK cycles between 2 data transfers. +#define DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL) + +#define SDCARD_APP_OP_COND_CMD (41 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO ) +#define MMC_SEND_OP_COND_CMD (1 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD) + + +#define DISABLE 0 // Disable MCI interface +#define ENABLE 1 // Enable MCI interface + + +//------------------------------------------------------------------------------ +// Local macros +//------------------------------------------------------------------------------ + +/// Used to write in PMC registers. +#define WRITE_PMC(pPmc, regName, value) pPmc->regName = (value) + +/// Used to write in MCI registers. +#define WRITE_MCI(pMci, regName, value) pMci->regName = (value) + +/// Used to read from MCI registers. +#define READ_MCI(pMci, regName) (pMci->regName) + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Enable/disable a MCI driver instance. +/// \param pMci Pointer to a MCI driver instance. +/// \param enb 0 for disable MCI and 1 for enable MCI. +//------------------------------------------------------------------------------ +void MCI_Enable(Mci *pMci, unsigned char enb) +{ + AT91S_MCI *pMciHw = pMci->pMciHw; + + SANITY_CHECK(pMci); + SANITY_CHECK(pMci->pMciHw); + + // Set the Control Register: Enable/Disable MCI interface clock + if(enb == DISABLE) { + WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS); + } + else { + WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN); + } +} + +//------------------------------------------------------------------------------ +/// Initializes a MCI driver instance and the underlying peripheral. +/// \param pMci Pointer to a MCI driver instance. +/// \param pMciHw Pointer to a MCI peripheral. +/// \param mciId MCI peripheral identifier. +/// \param mode Slot and type of connected card. +//------------------------------------------------------------------------------ +void MCI_Init( + Mci *pMci, + AT91S_MCI *pMciHw, + unsigned char mciId, + unsigned int mode) +{ + unsigned short clkDiv; + + SANITY_CHECK(pMci); + SANITY_CHECK(pMciHw); + SANITY_CHECK((mode == MCI_MMC_SLOTA) || (mode == MCI_MMC_SLOTB) + || (mode == MCI_SD_SLOTA) || (mode == MCI_SD_SLOTB)); + + // Initialize the MCI driver structure + pMci->pMciHw = pMciHw; + pMci->mciId = mciId; + pMci->semaphore = 1; + pMci->pCommand = 0; + + // Enable the MCI clock + WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << mciId)); + + // Reset the MCI + WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST); + + // Disable the MCI + WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS); + + // Disable all the interrupts + WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF); + + // Set the Data Timeout Register + WRITE_MCI(pMciHw, MCI_DTOR, DTOR_1MEGA_CYCLES); + + // Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58) + clkDiv = (BOARD_MCK / (400000 * 2)) - 1; + WRITE_MCI(pMciHw, MCI_MR, (clkDiv | (AT91C_MCI_PWSDIV & (0x7 << 8)))); + + // Set the SDCard Register + WRITE_MCI(pMciHw, MCI_SDCR, mode); + + // Enable the MCI and the Power Saving + WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN); + + // Disable the MCI peripheral clock. + WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << mciId)); +} + +//------------------------------------------------------------------------------ +/// Close a MCI driver instance and the underlying peripheral. +/// \param pMci Pointer to a MCI driver instance. +/// \param pMciHw Pointer to a MCI peripheral. +/// \param mciId MCI peripheral identifier. +//------------------------------------------------------------------------------ +void MCI_Close(Mci *pMci) +{ + AT91S_MCI *pMciHw = pMci->pMciHw; + + SANITY_CHECK(pMci); + SANITY_CHECK(pMciHw); + + // Initialize the MCI driver structure + pMci->semaphore = 1; + pMci->pCommand = 0; + + // Disable the MCI peripheral clock. + WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << pMci->mciId)); + + // Disable the MCI + WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS); + + // Disable all the interrupts + WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF); +} + +//------------------------------------------------------------------------------ +/// Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is +/// MCK/2 and corresponds to CLKDIV = 0 +/// \param pMci Pointer to the low level MCI driver. +/// \param mciSpeed MCI clock speed in Hz. +//------------------------------------------------------------------------------ +void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed) +{ + AT91S_MCI *pMciHw = pMci->pMciHw; + unsigned int mciMr; + unsigned short clkdiv; + + SANITY_CHECK(pMci); + SANITY_CHECK(pMci->pMciHw); + + // Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58) + mciMr = READ_MCI(pMciHw, MCI_MR) & (~AT91C_MCI_CLKDIV); + + // Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + // divided by (2*(CLKDIV+1)) + if (mciSpeed > 0) { + + clkdiv = (BOARD_MCK / (mciSpeed * 2)); + if (clkdiv > 0) { + + clkdiv -= 1; + } + } + else { + + clkdiv = 0; + } + + WRITE_MCI(pMciHw, MCI_MR, mciMr | clkdiv); +} + +//------------------------------------------------------------------------------ +/// Configure the MCI SDCBUS in the MCI_SDCR register. Only two modes available +/// +/// \param pMci Pointer to the low level MCI driver. +/// \param busWidth MCI bus width mode. +//------------------------------------------------------------------------------ +void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth) +{ + AT91S_MCI *pMciHw = pMci->pMciHw; + unsigned int mciSdcr; + + SANITY_CHECK(pMci); + SANITY_CHECK(pMci->pMciHw); + + mciSdcr = (READ_MCI(pMciHw, MCI_SDCR) & ~(AT91C_MCI_SCDBUS)); + + WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr | busWidth); +} + +//------------------------------------------------------------------------------ +/// Starts a MCI transfer. This is a non blocking function. It will return +/// as soon as the transfer is started. +/// Return 0 if successful; otherwise returns MCI_ERROR_LOCK if the driver is +/// already in use. +/// \param pMci Pointer to an MCI driver instance. +/// \param pCommand Pointer to the command to execute. +//------------------------------------------------------------------------------ +unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pCommand) +{ + AT91PS_MCI pMciHw = pMci->pMciHw; + unsigned int mciIer, mciMr; + + SANITY_CHECK(pMci); + SANITY_CHECK(pMciHw); + SANITY_CHECK(pCommand); + + // Try to acquire the MCI semaphore + if (pMci->semaphore == 0) { + + return MCI_ERROR_LOCK; + } + pMci->semaphore--; + // trace_LOG(trace_DEBUG, "MCI_SendCommand %x %d\n\r", READ_MCI(pMciHw, MCI_SR), pCommand->cmd & 0x3f); + + // Command is now being executed + pMci->pCommand = pCommand; + pCommand->status = MCI_STATUS_PENDING; + + // Enable the MCI clock + WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << pMci->mciId)); + + //Disable MCI clock, for multi-block data transfer + MCI_Enable(pMci, DISABLE); + + // Set PDC data transfer direction + if(pCommand->blockSize > 0) { + if(pCommand->isRead) { + WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN); + } + else { + WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN); + } + } + // Disable transmitter and receiver + WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); + + mciMr = READ_MCI(pMciHw, MCI_MR) & (~(AT91C_MCI_BLKLEN | AT91C_MCI_PDCMODE)); + + // Command with DATA stage + if (pCommand->blockSize > 0) { + // Enable PDC mode and set block size + if(pCommand->conTrans != MCI_CONTINUE_TRANSFER) { + + WRITE_MCI(pMciHw, MCI_MR, mciMr | AT91C_MCI_PDCMODE | (pCommand->blockSize << 16)); + } + + // DATA transfer from card to host + if (pCommand->isRead) { + WRITE_MCI(pMciHw, MCI_RPR, (int) pCommand->pData); + + // If Multiblock command set the BLKR register + /* if (pCommand->nbBlock > 1) { + WRITE_MCI(pMciHw, MCI_BLKR, pCommand->nbBlock | (pCommand->blockSize << 16)); + } + else { + WRITE_MCI(pMciHw, MCI_BLKR, (pCommand->blockSize << 16)); + }*/ + + // Sanity check + if (pCommand->nbBlock == 0) + pCommand->nbBlock = 1; + //////// + if ((pCommand->blockSize & 0x3) != 0) { + WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1); + } + else { + WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4); + } + + WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN); + mciIer = AT91C_MCI_ENDRX | STATUS_ERRORS; + // mciIer = AT91C_MCI_RXBUFF | STATUS_ERRORS; + } + + // DATA transfer from host to card + else { + // Sanity check + if (pCommand->nbBlock == 0) + pCommand->nbBlock = 1; + WRITE_MCI(pMciHw, MCI_TPR, (int) pCommand->pData); + // Update the PDC counter + if ((pCommand->blockSize & 0x3) != 0) { + WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1); + } + else { + WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4); + } + // MCI_BLKE notifies the end of Multiblock command + mciIer = AT91C_MCI_BLKE | STATUS_ERRORS; + } + } + // No data transfer: stop at the end of the command + else { + WRITE_MCI(pMciHw, MCI_MR, mciMr); + mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS; + } + // Enable MCI clock + MCI_Enable(pMci, ENABLE); + + // Send the command + if((pCommand->conTrans != MCI_CONTINUE_TRANSFER) + || (pCommand->blockSize == 0)) { + + WRITE_MCI(pMciHw, MCI_ARGR, pCommand->arg); + WRITE_MCI(pMciHw, MCI_CMDR, pCommand->cmd); + } + + // In case of transmit, the PDC shall be enabled after sending the command + if ((pCommand->blockSize > 0) && !(pCommand->isRead)) { + WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN); + } + + // Ignore data error +// if (pCommand->blockSize == 0) { + { + mciIer &= ~(AT91C_MCI_UNRE | AT91C_MCI_OVRE \ + | AT91C_MCI_DTOE | AT91C_MCI_DCRCE); + } + + // Interrupt enable shall be done after PDC TXTEN and RXTEN + WRITE_MCI(pMciHw, MCI_IER, mciIer); + + return 0; +} + +//------------------------------------------------------------------------------ +/// Check NOTBUSY and DTIP bits of status register on the given MCI driver. +/// Return value, 0 for bus ready, 1 for bus busy +/// \param pMci Pointer to a MCI driver instance. +//------------------------------------------------------------------------------ +unsigned char MCI_CheckBusy(Mci *pMci) +{ + AT91S_MCI *pMciHw = pMci->pMciHw; + unsigned int status; + + // Enable MCI clock + MCI_Enable(pMci, ENABLE); + + status = READ_MCI(pMciHw, MCI_SR); + // trace_LOG(trace_DEBUG, "status %x\n\r",status); + + + if(((status & AT91C_MCI_NOTBUSY)!=0) + && ((status & AT91C_MCI_DTIP)==0)) { + + // Disable MCI clock + MCI_Enable(pMci, DISABLE); + + return 0; + } + else { + return 1; + } +} + +//------------------------------------------------------------------------------ +/// Check BLKE bit of status register on the given MCI driver. +/// \param pMci Pointer to a MCI driver instance. +//------------------------------------------------------------------------------ +unsigned char MCI_CheckBlke(Mci *pMci) +{ + AT91S_MCI *pMciHw = pMci->pMciHw; + unsigned int status; + + status = READ_MCI(pMciHw, MCI_SR); + // trace_LOG(trace_DEBUG, "status %x\n\r",status); + + if((status & AT91C_MCI_BLKE)!=0) { + return 0; + } + else { + return 1; + } +} + +//------------------------------------------------------------------------------ +/// Processes pending events on the given MCI driver. +/// \param pMci Pointer to a MCI driver instance. +//------------------------------------------------------------------------------ +void MCI_Handler(Mci *pMci) +{ + AT91S_MCI *pMciHw = pMci->pMciHw; + MciCmd *pCommand = pMci->pCommand; + unsigned int status; + unsigned char i; + #if defined(at91rm9200) + unsigned int mciCr, mciSdcr, mciMr, mciDtor; + #endif + + SANITY_CHECK(pMci); + SANITY_CHECK(pMciHw); + SANITY_CHECK(pCommand); + + // Read the status register + status = READ_MCI(pMciHw, MCI_SR) & READ_MCI(pMciHw, MCI_IMR); + // trace_LOG(trace_DEBUG, "status %x\n\r", status); + + // Check if an error has occured + if ((status & STATUS_ERRORS) != 0) { + + // Check error code + if ((status & STATUS_ERRORS) == AT91C_MCI_RTOE) { + + pCommand->status = MCI_STATUS_NORESPONSE; + } + // if the command is SEND_OP_COND the CRC error flag is always present + // (cf : R3 response) + else if (((status & STATUS_ERRORS) != AT91C_MCI_RCRCE) + || ((pCommand->cmd != SDCARD_APP_OP_COND_CMD) + && (pCommand->cmd != MMC_SEND_OP_COND_CMD))) { + + pCommand->status = MCI_STATUS_ERROR; + } + } + + // Check if a transfer has been completed + if (((status & AT91C_MCI_CMDRDY) != 0) + || ((status & AT91C_MCI_ENDRX) != 0) + || ((status & AT91C_MCI_RXBUFF) != 0) + || ((status & AT91C_MCI_ENDTX) != 0) + || ((status & AT91C_MCI_BLKE) != 0) + || ((status & AT91C_MCI_RTOE) != 0)) { + + if (((status & AT91C_MCI_ENDRX) != 0) + || ((status & AT91C_MCI_RXBUFF) != 0) + || ((status & AT91C_MCI_ENDTX) != 0)) { + + MCI_Enable(pMci, DISABLE); + } + + /// On AT91RM9200-EK, if stop transmission, software reset MCI. + #if defined(at91rm9200) + if ((pCommand->cmd & AT91C_MCI_TRCMD_STOP) != 0) { + mciMr = READ_MCI(pMciHw, MCI_MR); + mciSdcr = READ_MCI(pMciHw, MCI_SDCR); + mciDtor = READ_MCI(pMciHw, MCI_DTOR); + WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST); + // trace_LOG(trace_DEBUG, "reset MCI\n\r"); + + WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS); + WRITE_MCI(pMciHw, MCI_MR, mciMr); + WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr); + WRITE_MCI(pMciHw, MCI_DTOR, mciDtor); + } + #endif + + // If no error occured, the transfer is successful + if (pCommand->status == MCI_STATUS_PENDING) { + pCommand->status = 0; + } +#if 0 + if ((status & AT91C_MCI_CMDRDY) != 0) + trace_LOG(trace_DEBUG, "."); + if ((status & AT91C_MCI_ENDRX) != 0) + trace_LOG(trace_DEBUG, "<"); + if ((status & AT91C_MCI_ENDTX) != 0) + trace_LOG(trace_DEBUG, "-"); + if ((status & AT91C_MCI_BLKE) != 0) + trace_LOG(trace_DEBUG, ">"); + trace_LOG(trace_DEBUG, "\n\r"); +#endif + // Store the card response in the provided buffer + if (pCommand->pResp) { + + for (i=0; i < pCommand->resSize; i++) { + + pCommand->pResp[i] = READ_MCI(pMciHw, MCI_RSPR[0]); + } + } + + // Disable interrupts + WRITE_MCI(pMciHw, MCI_IDR, READ_MCI(pMciHw, MCI_IMR)); + + // Release the semaphore + pMci->semaphore++; + + // Invoke the callback associated with the current command (if any) + if (pCommand->callback) { + (pCommand->callback)(pCommand->status, pCommand); + } + } +} + +//------------------------------------------------------------------------------ +/// Returns 1 if the given MCI transfer is complete; otherwise returns 0. +/// \param pCommand Pointer to a MciCmd instance. +//------------------------------------------------------------------------------ +unsigned char MCI_IsTxComplete(MciCmd *pCommand) +{ + if (pCommand->status != MCI_STATUS_PENDING) { + if (pCommand->status != 0) + printf("MCI_IsTxComplete %d\n\r", pCommand->status); + return 1; + } + else { + return 0; + } +} diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/mci/mci.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/mci/mci.h new file mode 100644 index 0000000..e112fc6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/mci/mci.h @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef MCI_H +#define MCI_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + +/// Transfer is pending. +#define MCI_STATUS_PENDING 1 +/// Transfer has been aborted because an error occured. +#define MCI_STATUS_ERROR 2 +/// Card did not answer command. +#define MCI_STATUS_NORESPONSE 3 + +/// MCI driver is currently in use. +#define MCI_ERROR_LOCK 1 + +/// MCI configuration with 1-bit data bus on slot A (for MMC cards). +#define MCI_MMC_SLOTA 0 +/// MCI configuration with 1-bit data bus on slot B (for MMC cards). +#define MCI_MMC_SLOTB 1 +/// MCI configuration with 4-bit data bus on slot A (for SD cards). +#define MCI_SD_SLOTA AT91C_MCI_SCDBUS +/// MCI configuration with 4-bit data bus on slot B (for SD cards). +#define MCI_SD_SLOTB (AT91C_MCI_SCDBUS | 1) + +/// Start new data transfer +#define MCI_NEW_TRANSFER 0 +/// Continue data transfer +#define MCI_CONTINUE_TRANSFER 1 + +/// MCI SD Bus Width 1-bit +#define MCI_SDCBUS_1BIT (0 << 7) +/// MCI SD Bus Width 4-bit +#define MCI_SDCBUS_4BIT (1 << 7) + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +/// MCI end-of-transfer callback function. +typedef void (*MciCallback)(unsigned char status, void *pCommand); + +//------------------------------------------------------------------------------ +/// MCI Transfer Request prepared by the application upper layer. This structure +/// is sent to the MCI_SendCommand function to start the transfer. At the end of +/// the transfer, the callback is invoked by the interrupt handler. +//------------------------------------------------------------------------------ +typedef struct _MciCmd { + + /// Command status. + volatile char status; + /// Command code. + unsigned int cmd; + /// Command argument. + unsigned int arg; + /// Data buffer. + unsigned char *pData; + /// Size of data buffer in bytes. + unsigned short blockSize; + /// Number of blocks to be transfered + unsigned short nbBlock; + /// Indicate if continue to transfer data + unsigned char conTrans; + /// Indicates if the command is a read operation. + unsigned char isRead; + /// Response buffer. + unsigned int *pResp; + /// Size of SD card response in bytes. + unsigned char resSize; + /// Optional user-provided callback function. + MciCallback callback; + /// Optional argument to the callback function. + void *pArg; + +} MciCmd; + +//------------------------------------------------------------------------------ +/// MCI driver structure. Holds the internal state of the MCI driver and +/// prevents parallel access to a MCI peripheral. +//------------------------------------------------------------------------------ +typedef struct { + + /// Pointer to a MCI peripheral. + AT91S_MCI *pMciHw; + /// MCI peripheral identifier. + unsigned char mciId; + /// Pointer to currently executing command. + MciCmd *pCommand; + /// Mutex. + volatile char semaphore; + +} Mci; + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void MCI_Init( + Mci *pMci, + AT91PS_MCI pMciHw, + unsigned char mciId, + unsigned int mode); + +extern void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed); + +extern unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pMciCmd); + +extern void MCI_Handler(Mci *pMci); + +extern unsigned char MCI_IsTxComplete(MciCmd *pMciCmd); + +extern unsigned char MCI_CheckBusy(Mci *pMci); + +extern void MCI_Close(Mci *pMci); + +extern void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth); + +#endif //#ifndef MCI_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio.c new file mode 100644 index 0000000..c874d2d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio.c @@ -0,0 +1,336 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pio.h" +#include + +//------------------------------------------------------------------------------ +// Internal definitions +//------------------------------------------------------------------------------ +/// \internal Returns the current value of a register. +#define READ(peripheral, register) (peripheral->register) +/// \internal Modifies the current value of a register. +#define WRITE(peripheral, register, value) (peripheral->register = value) + +//------------------------------------------------------------------------------ +// Internal functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Configures one or more pin(s) of a PIO controller as being controlled by +/// peripheral A. Optionally, the corresponding internal pull-up(s) can be +/// enabled. +/// \param pio Pointer to a PIO controller. +/// \param mask Bitmask of one or more pin(s) to configure. +/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be +/// configured. +//------------------------------------------------------------------------------ +static void PIO_SetPeripheralA(AT91S_PIO *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + // Disable interrupts on the pin(s) + WRITE(pio, PIO_IDR, mask); + + // Enable the pull-up(s) if necessary + if (enablePullUp) { + + WRITE(pio, PIO_PPUER, mask); + } + else { + + WRITE(pio, PIO_PPUDR, mask); + } + + // Configure pin + WRITE(pio, PIO_ASR, mask); + WRITE(pio, PIO_PDR, mask); +} + +//------------------------------------------------------------------------------ +/// Configures one or more pin(s) of a PIO controller as being controlled by +/// peripheral A. Optionally, the corresponding internal pull-up(s) can be +/// enabled. +/// \param pio Pointer to a PIO controller. +/// \param mask Bitmask of one or more pin(s) to configure. +/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be +/// configured. +//------------------------------------------------------------------------------ +static void PIO_SetPeripheralB(AT91S_PIO *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + // Disable interrupts on the pin(s) + WRITE(pio, PIO_IDR, mask); + + // Enable the pull-up(s) if necessary + if (enablePullUp) { + + WRITE(pio, PIO_PPUER, mask); + } + else { + + WRITE(pio, PIO_PPUDR, mask); + } + + // Configure pin + WRITE(pio, PIO_BSR, mask); + WRITE(pio, PIO_PDR, mask); +} + +//------------------------------------------------------------------------------ +/// Configures one or more pin(s) or a PIO controller as inputs. Optionally, +/// the corresponding internal pull-up(s) and glitch filter(s) can be +/// enabled. +/// \param pio Pointer to a PIO controller. +/// \param mask Bitmask indicating which pin(s) to configure as input(s). +/// \param enablePullUp Indicates if the internal pull-up(s) must be enabled. +/// \param enableFilter Indicates if the glitch filter(s) must be enabled. +//------------------------------------------------------------------------------ +static void PIO_SetInput(AT91S_PIO *pio, + unsigned int mask, + unsigned char enablePullUp, + unsigned char enableFilter) +{ + // Disable interrupts + WRITE(pio, PIO_IDR, mask); + + // Enable pull-up(s) if necessary + if (enablePullUp) { + + WRITE(pio, PIO_PPUER, mask); + } + else { + + WRITE(pio, PIO_PPUDR, mask); + } + + // Enable filter(s) if necessary + if (enableFilter) { + + WRITE(pio, PIO_IFER, mask); + } + else { + + WRITE(pio, PIO_IFDR, mask); + } + + // Configure pin as input + WRITE(pio, PIO_ODR, mask); + WRITE(pio, PIO_PER, mask); +} + +//------------------------------------------------------------------------------ +/// Configures one or more pin(s) of a PIO controller as outputs, with the +/// given default value. Optionally, the multi-drive feature can be enabled +/// on the pin(s). +/// \param pio Pointer to a PIO controller. +/// \param mask Bitmask indicating which pin(s) to configure. +/// \param defaultValue Default level on the pin(s). +/// \param enableMultiDrive Indicates if the pin(s) shall be configured as +/// open-drain. +/// \param enablePullUp Indicates if the pin shall have its pull-up activated. +//------------------------------------------------------------------------------ +static void PIO_SetOutput(AT91S_PIO *pio, + unsigned int mask, + unsigned char defaultValue, + unsigned char enableMultiDrive, + unsigned char enablePullUp) +{ + // Disable interrupts + WRITE(pio, PIO_IDR, mask); + + // Enable pull-up(s) if necessary + if (enablePullUp) { + + WRITE(pio, PIO_PPUER, mask); + } + else { + + WRITE(pio, PIO_PPUDR, mask); + } + + // Enable multi-drive if necessary + if (enableMultiDrive) { + + WRITE(pio, PIO_MDER, mask); + } + else { + + WRITE(pio, PIO_MDDR, mask); + } + + // Set default value + if (defaultValue) { + + WRITE(pio, PIO_SODR, mask); + } + else { + + WRITE(pio, PIO_CODR, mask); + } + + // Configure pin(s) as output(s) + WRITE(pio, PIO_OER, mask); + WRITE(pio, PIO_PER, mask); +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Configures a list of Pin instances, which can either hold a single pin or a +/// group of pins, depending on the mask value; all pins are configured by this +/// function. +/// Returns 1 if the configuration has been performed successfully; otherwise 0. +/// \param list Pointer to a list of Pin instances. +/// \param size Size of the Pin list (see ). +//------------------------------------------------------------------------------ +unsigned char PIO_Configure(const Pin *list, unsigned int size) +{ + // Configure pins + while (size > 0) { + + switch (list->type) { + + case PIO_PERIPH_A: + PIO_SetPeripheralA(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_PERIPH_B: + PIO_SetPeripheralB(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_INPUT: + AT91C_BASE_PMC->PMC_PCER = 1 << list->id; + PIO_SetInput(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0, + (list->attribute & PIO_DEGLITCH)? 1 : 0); + break; + + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + PIO_SetOutput(list->pio, + list->mask, + (list->type == PIO_OUTPUT_1), + (list->attribute & PIO_OPENDRAIN) ? 1 : 0, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + default: return 0; + } + + list++; + size--; + } + + return 1; +} + +//------------------------------------------------------------------------------ +/// Sets a high output level on one or more pin(s) (if configured as output(s)). +/// \param pin Pointer to a Pin instance describing one or more pins. +//------------------------------------------------------------------------------ +void PIO_Set(const Pin *pin) +{ + WRITE(pin->pio, PIO_SODR, pin->mask); +} + +//------------------------------------------------------------------------------ +/// Sets a low output level on one or more pin(s) (if configured as output(s)). +/// \param pin Pointer to a Pin instance describing one or more pins. +//------------------------------------------------------------------------------ +void PIO_Clear(const Pin *pin) +{ + WRITE(pin->pio, PIO_CODR, pin->mask); +} + +//------------------------------------------------------------------------------ +/// Returns 1 if one or more PIO of the given Pin instance currently have a high +/// level; otherwise returns 0. +/// \param pin Pointer to a Pin instance describing one or more pins. +//------------------------------------------------------------------------------ +unsigned char PIO_Get(const Pin *pin) +{ + unsigned int reg; + if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) { + + reg = READ(pin->pio, PIO_ODSR); + } + else { + + reg = READ(pin->pio, PIO_PDSR); + } + + if ((reg & pin->mask) == 0) { + + return 0; + } + else { + + return 1; + } +} + + +//------------------------------------------------------------------------------ +/// Returns 1 if one or more PIO of the given Pin data to be driven on the I/O line +/// level; otherwise returns 0. +/// \param pin Pointer to a Pin instance describing one or more pins. +//------------------------------------------------------------------------------ +unsigned char PIO_GetOutputDataStatus(const Pin *pin) +{ + if ((READ(pin->pio, PIO_ODSR) & pin->mask) == 0) { + + return 0; + } + else { + + return 1; + } +} + +//------------------------------------------------------------------------------ +/// Returns the value of ISR for the PIO controller of the pin. +/// Reading this register acknoledges all the ITs. +/// \param pin Pointer to a Pin instance describing one or more pins. +//------------------------------------------------------------------------------ +unsigned int PIO_GetISR(const Pin *pin) +{ + return (READ(pin->pio, PIO_ISR)); +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio.h new file mode 100644 index 0000000..e5721dc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio.h @@ -0,0 +1,169 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Definition of methods and structures for using PIOs in a transparent +/// way. The main purpose is to allow portability between several boards. +/// +/// !Usage +/// +/// -# To configure and use pins, see pio.h. +/// -# To enable and use interrupt generation on PIO status change, see +/// pio_it.h. +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Simple & portable usage of PIO pins. +/// +/// !Usage +/// +/// -# Define a constant pin description array such as the following one: +/// \code +/// const Pin at91board_dbgu[] = { +/// {AT91C_BASE_PIOA, (1 << 30), PIO_PERIPH_A, PIO_DEFAULT}, +/// {AT91C_BASE_PIOA, (1 << 31), PIO_PERIPH_A, PIO_DEFAULT}, +/// }; +/// \endcode +/// Alternatively, constants defined in the piodefs.h header file of the +/// board module can be used: +/// \code +/// const Pin at91board_dbgu[] = {PINS_DBGU}; +/// const Pin at91board_usart[] = {PIN_USART0_RXD, PIN_USART0_TXD}; +/// \endcode +/// It is possible to group multiple pins if they share the same +/// attributes, to save memory. Here is the previous DBGU example +/// rewritten in such a way: +/// \code +/// const Pin at91board_dbgu[] = { +/// {AT91C_BASE_PIOA, 0xC0000000, PIO_PERIPH_A, PIO_DEFAULT} +/// }; +/// \endcode +/// -# For pins configured as inputs, the PIO controller must be enabled +/// in the PMC (*enabled by PIO_Configure at the moment*). +/// -# Configure a pin array by calling PIO_Configure, using +/// the PIO_LISTSIZE macro to calculate the array size if needed. Do not +/// forget to check the return value for any error. +/// -# Set and get the value of a pin using the PIO_Set, PIO_Clear and +/// PIO_Get methods. +//------------------------------------------------------------------------------ + +#ifndef PIO_H +#define PIO_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// \page "Pin types" +/// This page lists the available types for a Pin instance (in its type field). +/// !Types +/// - PIO_PERIPH_A +/// - PIO_PERIPH_B +/// - PIO_INPUT +/// - PIO_OUTPUT_0 +/// - PIO_OUTPUT_1 + +/// The pin is controlled by the associated signal of peripheral A. +#define PIO_PERIPH_A 0 +/// The pin is controlled by the associated signal of peripheral B. +#define PIO_PERIPH_B 1 +/// The pin is an input. +#define PIO_INPUT 2 +/// The pin is an output and has a default level of 0. +#define PIO_OUTPUT_0 3 +/// The pin is an output and has a default level of 1. +#define PIO_OUTPUT_1 4 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "Pin attributes" +/// This page lists the valid values for the attribute field of a Pin instance. +/// !Attributes +/// - PIO_DEFAULT +/// - PIO_PULLUP +/// - PIO_DEGLITCH +/// - PIO_OPENDRAIN + +/// Default pin configuration (no attribute). +#define PIO_DEFAULT (0 << 0) +/// The internal pin pull-up is active. +#define PIO_PULLUP (1 << 0) +/// The internal glitch filter is active. +#define PIO_DEGLITCH (1 << 1) +/// The pin is open-drain. +#define PIO_OPENDRAIN (1 << 2) +//------------------------------------------------------------------------------ + +/// Calculates the size of a Pin instances array. The array must be local (i.e. +/// not a pointer), otherwise the computation will not be correct. +#define PIO_LISTSIZE(list) (sizeof(list) / sizeof(Pin)) + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Describes the type and attribute of one PIO pin or a group of similar pins. +typedef struct { + /// Bitmask indicating which pin(s) to configure. + unsigned int mask; + /// Pointer to the PIO controller which has the pin(s). + AT91S_PIO *pio; + /// Peripheral ID of the PIO controller which has the pin(s). + unsigned char id; + /// Pin type (see "Pin types"). + unsigned char type; + /// Pin attribute (see "Pin attributes"). + unsigned char attribute; +} Pin; +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern unsigned char PIO_Configure(const Pin *list, unsigned int size); +extern void PIO_Set(const Pin *pin ); +extern void PIO_Clear(const Pin *pin); +extern unsigned char PIO_Get(const Pin *pin); +extern unsigned int PIO_GetISR(const Pin *pin); +extern unsigned char PIO_GetOutputDataStatus(const Pin *pin); + +#endif //#ifndef PIO_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.c new file mode 100644 index 0000000..c58220c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.c @@ -0,0 +1,387 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/// Disable traces for this file +#ifndef NOTRACE + #define NOTRACE +#endif + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pio_it.h" +#include "pio.h" +#include +#include +#include +#include + +//------------------------------------------------------------------------------ +// Local definitions +//------------------------------------------------------------------------------ + +/// Returns the current value of a register. +#define READ(peripheral, register) (peripheral->register) +/// Modifies the current value of a register. +#define WRITE(peripheral, register, value) (peripheral->register = value) + +/// Maximum number of interrupt sources that can be defined. +#define MAX_INTERRUPT_SOURCES 7 + +//------------------------------------------------------------------------------ +// Local types +//------------------------------------------------------------------------------ + +/// Describes a PIO interrupt source, including the PIO instance triggering the +/// interrupt and the associated interrupt handler. +typedef struct _InterruptSource { + + /// Interrupt source pin. + const Pin *pPin; + + /// Interrupt handler. + void (*handler)(const Pin *); + +} InterruptSource; + +//------------------------------------------------------------------------------ +// Local variables +//------------------------------------------------------------------------------ + +/// List of interrupt sources. +static InterruptSource pSources[MAX_INTERRUPT_SOURCES]; + +/// Number of currently defined interrupt sources. +static unsigned int numSources; + +//------------------------------------------------------------------------------ +// Local functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Handles all interrupts on the given PIO controller. +/// \param id PIO controller ID. +/// \param pBase PIO controller base address. +//------------------------------------------------------------------------------ +void PioInterruptHandler(unsigned int id, AT91S_PIO *pBase) +{ + unsigned int status; + unsigned int i; + + // Check PIO controller status + status = pBase->PIO_ISR; + status &= pBase->PIO_IMR; + if (status != 0) { + + trace_LOG(trace_DEBUG, "-D- PIO interrupt on PIO controller #%d\n\r", id); + + // Check all sources + i = 0; + while (status != 0) { + + // There cannot be an unconfigured source enabled. + SANITY_CHECK(i < numSources); + + // Source if configured on PIOA + if (pSources[i].pPin->id == id) { + + // Source has PIOs which have changed + if ((status & pSources[i].pPin->mask) != 0) { + + trace_LOG(trace_DEBUG, "-D- Interrupt source #%d triggered\n\r", i); + + pSources[i].handler(pSources[i].pPin); + status &= ~(pSources[i].pPin->mask); + } + } + i++; + } + } +} + +//------------------------------------------------------------------------------ +/// Generic PIO interrupt handler. Single entry point for interrupts coming +/// from any PIO controller (PIO A, B, C ...). Dispatches the interrupt to +/// the user-configured handlers. +//------------------------------------------------------------------------------ +void InterruptHandler() +{ +#if defined(AT91C_ID_PIOA) + // Treat PIOA interrupts + PioInterruptHandler(AT91C_ID_PIOA, AT91C_BASE_PIOA); +#endif + +#if defined(AT91C_ID_PIOB) + // Treat PIOB interrupts + PioInterruptHandler(AT91C_ID_PIOB, AT91C_BASE_PIOB); +#endif + +#if defined(AT91C_ID_PIOC) + // Treat PIOC interrupts + PioInterruptHandler(AT91C_ID_PIOC, AT91C_BASE_PIOC); +#endif + +#if defined(AT91C_ID_PIOD) + // Treat PIOD interrupts + PioInterruptHandler(AT91C_ID_PIOD, AT91C_BASE_PIOD); +#endif + +#if defined(AT91C_ID_PIOE) + // Treat PIOE interrupts + PioInterruptHandler(AT91C_ID_PIOE, AT91C_BASE_PIOE); +#endif + +#if defined(AT91C_ID_PIOABCD) + // Treat PIOABCD interrupts + #if !defined(AT91C_ID_PIOA) + PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOA); + #endif + #if !defined(AT91C_ID_PIOB) + PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOB); + #endif + #if !defined(AT91C_ID_PIOC) + PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOC); + #endif + #if !defined(AT91C_ID_PIOD) + PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOD); + #endif +#endif + +#if defined(AT91C_ID_PIOABCDE) + // Treat PIOABCDE interrupts + #if !defined(AT91C_ID_PIOA) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOA); + #endif + #if !defined(AT91C_ID_PIOB) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOB); + #endif + #if !defined(AT91C_ID_PIOC) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOC); + #endif + #if !defined(AT91C_ID_PIOD) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOD); + #endif + #if !defined(AT91C_ID_PIOE) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOE); + #endif +#endif + +#if defined(AT91C_ID_PIOCDE) + // Treat PIOCDE interrupts + #if !defined(AT91C_ID_PIOC) + PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOC); + #endif + #if !defined(AT91C_ID_PIOD) + PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOD); + #endif + #if !defined(AT91C_ID_PIOE) + PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOE); + #endif +#endif + +} + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Initializes the PIO interrupt management logic. +/// \param priority PIO controller interrupts priority. +//------------------------------------------------------------------------------ +void PIO_InitializeInterrupts(unsigned int priority) +{ + trace_LOG(trace_DEBUG, "-D- PIO_Initialize()\n\r"); + + SANITY_CHECK((priority & ~AT91C_AIC_PRIOR) == 0); + + // Reset sources + numSources = 0; + +#ifdef AT91C_ID_PIOA + // Configure PIO interrupt sources + trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOA\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; + AT91C_BASE_PIOA->PIO_ISR; + AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOA, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOA); +#endif + +#ifdef AT91C_ID_PIOB + trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOB\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB; + AT91C_BASE_PIOB->PIO_ISR; + AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOB, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOB); +#endif + +#ifdef AT91C_ID_PIOC + trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOC\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOC; + AT91C_BASE_PIOC->PIO_ISR; + AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOC, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOC); +#endif + +#ifdef AT91C_ID_PIOD + trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOD\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOD; + AT91C_BASE_PIOC->PIO_ISR; + AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOD, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOD); +#endif + +#ifdef AT91C_ID_PIOE + trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOE\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOE; + AT91C_BASE_PIOC->PIO_ISR; + AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOE, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOE); +#endif + +#if defined(AT91C_ID_PIOABCD) + // Treat PIOABCD interrupts + #if !defined(AT91C_ID_PIOA) \ + && !defined(AT91C_ID_PIOB) \ + && !defined(AT91C_ID_PIOC) \ + && !defined(AT91C_ID_PIOD) + + trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOABCD\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD; + AT91C_BASE_PIOA->PIO_ISR; + AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOABCD, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOABCD); + #endif +#endif + +#if defined(AT91C_ID_PIOABCDE) + // Treat PIOABCDE interrupts + #if !defined(AT91C_ID_PIOA) \ + && !defined(AT91C_ID_PIOB) \ + && !defined(AT91C_ID_PIOC) \ + && !defined(AT91C_ID_PIOD) \ + && !defined(AT91C_ID_PIOE) + + trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOABCDE\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCDE; + AT91C_BASE_PIOA->PIO_ISR; + AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOABCDE, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOABCDE); + #endif +#endif + +#if defined(AT91C_ID_PIOCDE) + // Treat PIOCDE interrupts + #if !defined(AT91C_ID_PIOC) \ + && !defined(AT91C_ID_PIOD) \ + && !defined(AT91C_ID_PIOE) + + trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOC\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOCDE; + AT91C_BASE_PIOC->PIO_ISR; + AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOCDE, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOCDE); + #endif +#endif +} + +//------------------------------------------------------------------------------ +/// Configures an interrupt source. +/// \param pPin Interrupt source. +/// \param handler Desired interrupt handler for the source. +//------------------------------------------------------------------------------ +void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *)) +{ + InterruptSource *pSource; + + trace_LOG(trace_DEBUG, "-D- PIO_ConfigureIt()\n\r"); + + SANITY_CHECK(pPin); + ASSERT(numSources < MAX_INTERRUPT_SOURCES, + "-F- PIO_ConfigureIt: Increase MAX_INTERRUPT_SOURCES\n\r"); + + // Define new source + trace_LOG(trace_DEBUG, "-D- PIO_ConfigureIt: Defining new source #%d.\n\r", numSources); + + pSource = &(pSources[numSources]); + pSource->pPin = pPin; + pSource->handler = handler; + numSources++; +} + +//------------------------------------------------------------------------------ +/// Enables the given interrupt source if it has been configured. +/// \param pPin Interrupt source to enable. +//------------------------------------------------------------------------------ +void PIO_EnableIt(const Pin *pPin) +{ + trace_LOG(trace_DEBUG, "-D- PIO_EnableIt()\n\r"); + + SANITY_CHECK(pPin); + +#ifndef NOASSERT + unsigned int i = 0; + unsigned char found = 0; + while ((i < numSources) && !found) { + + if (pSources[i].pPin == pPin) { + + found = 1; + } + i++; + } + ASSERT(found, "-F- PIO_EnableIt: Interrupt source has not been configured\n\r"); +#endif + + pPin->pio->PIO_ISR; + pPin->pio->PIO_IER = pPin->mask; +} + +//------------------------------------------------------------------------------ +/// Disables a given interrupt source. +/// \param pPin Interrupt source to disable. +//------------------------------------------------------------------------------ +void PIO_DisableIt(const Pin *pPin) +{ + SANITY_CHECK(pPin); + + trace_LOG(trace_DEBUG, "-D- PIO_DisableIt()\n\r"); + + pPin->pio->PIO_IDR = pPin->mask; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.h new file mode 100644 index 0000000..6f462ac --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.h @@ -0,0 +1,61 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Configuration and handling of interrupts on PIO status changes. +/// +/// !Usage +/// +/// -# Configure an status change interrupt on one or more pin(s) with +/// PIO_ConfigureIt. +/// -# Enable & disable interrupts on pins using PIO_EnableIt and +/// PIO_DisableIt. +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pio.h" + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void PIO_InitializeInterrupts(unsigned int priority); + +extern void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *)); + +extern void PIO_EnableIt(const Pin *pPin); + +extern void PIO_DisableIt(const Pin *pPin); + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pit/pit.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pit/pit.c new file mode 100644 index 0000000..40c8e03 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pit/pit.c @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pit.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Initialize the System timer for a period in second with a system clock +/// freq in MHz +/// \param period Period in second. +/// \param pit_frequency System clock frequency in MHz. +//------------------------------------------------------------------------------ +void PIT_Init(unsigned int period, + unsigned int pit_frequency) +{ + AT91C_BASE_PITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//------------------------------------------------------------------------------ +/// Set the PIT Periodic Interval Value +//------------------------------------------------------------------------------ +void PIT_SetPIV(unsigned int piv) +{ + AT91C_BASE_PITC->PITC_PIMR = piv | (AT91C_BASE_PITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//------------------------------------------------------------------------------ +/// Enable the PIT +//------------------------------------------------------------------------------ +void PIT_Enable(void) +{ + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//---------------------------------------------------------------------------- +/// Enable PIT periodic interrupt +//---------------------------------------------------------------------------- +void PIT_EnableIT(void) +{ + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//------------------------------------------------------------------------------ +/// Disable PIT periodic interrupt +//------------------------------------------------------------------------------ +void PIT_DisableIT(void) +{ + AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//------------------------------------------------------------------------------ +/// Read PIT mode register +//------------------------------------------------------------------------------ +unsigned int PIT_GetMode(void) +{ + return(AT91C_BASE_PITC->PITC_PIMR); +} + +//------------------------------------------------------------------------------ +/// Read PIT status register +//------------------------------------------------------------------------------ +unsigned int PIT_GetStatus(void) +{ + return(AT91C_BASE_PITC->PITC_PISR); +} + +//------------------------------------------------------------------------------ +/// Read PIT CPIV and PICNT without ressetting the counters +//------------------------------------------------------------------------------ +unsigned int PIT_GetPIIR(void) +{ + return(AT91C_BASE_PITC->PITC_PIIR); +} + +//------------------------------------------------------------------------------ +/// Read System timer CPIV and PICNT without ressetting the counters +//------------------------------------------------------------------------------ +unsigned int PIT_GetPIVR(void) +{ + return(AT91C_BASE_PITC->PITC_PIVR); +} diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pit/pit.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pit/pit.h new file mode 100644 index 0000000..8f62e25 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pit/pit.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Configuration and handling of PIT. +/// +/// !Usage +/// +/// -# Initialize System timer for a period in second with +/// PIT_Init +/// -# Set the PIT Periodic Interval Value with PIT_SetPIV +/// -# Enable the PIT with PIT_Enable +/// -# Enable & disable PIT interrupts using PIT_EnableInt and +/// PIT_DisableInt +/// -# Read PIT mode register +/// PIT_GetMode +/// -# Read PIT status register +/// PIT_GetStatus +/// -# Read PIT CPIV and PICNT without ressetting the counters +/// PIT_GetPIIR +/// -# Read System timer CPIV and PICNT without ressetting the counters +/// PIT_GetPIVR +//------------------------------------------------------------------------------ + +#ifndef PIT_H +#define PIT_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void PIT_Init(unsigned int period, unsigned int pit_frequency); +extern void PIT_SetPIV(unsigned int piv); +extern void PIT_Enable(void); +extern void PIT_EnableIT(void); +extern void PIT_DisableIT(void); +extern unsigned int PIT_GetMode(void); +extern unsigned int PIT_GetStatus(void); +extern unsigned int PIT_GetPIIR(void); +extern unsigned int PIT_GetPIVR(void); + +#endif //#ifndef PIT_H diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.c new file mode 100644 index 0000000..c04fc31 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pmc.h" +#include +#include +#include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +#if defined(at91sam7l64) || defined(at91sam7l128) +//------------------------------------------------------------------------------ +/// Sets the fast wake-up inputs that can get the device out of Wait mode. +/// \param inputs Fast wake-up inputs to enable. +//------------------------------------------------------------------------------ +void PMC_SetFastWakeUpInputs(unsigned int inputs) +{ + SANITY_CHECK((inputs & ~0xFF) == 0); + AT91C_BASE_PMC->PMC_FSMR = inputs; +} + +#if !defined(__ICCARM__) +__attribute__ ((section (".ramfunc"))) // GCC +#endif +//------------------------------------------------------------------------------ +/// Disables the main oscillator, making the device enter Wait mode. +//------------------------------------------------------------------------------ +void PMC_DisableMainOscillatorForWaitMode(void) +{ + AT91C_BASE_PMC->PMC_MOR = 0x37 << 16; + while ((AT91C_BASE_PMC->PMC_MOR & AT91C_PMC_MAINSELS) != AT91C_PMC_MAINSELS); +} + +#endif + +#if defined(at91sam7l) +//------------------------------------------------------------------------------ +/// Disables the main oscillator when NOT running on it. +//------------------------------------------------------------------------------ +void PMC_DisableMainOscillator(void) +{ + AT91C_BASE_PMC->PMC_MOR = 0x37 << 16; + while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MAINSELS) == AT91C_PMC_MAINSELS); +} +#endif + +//------------------------------------------------------------------------------ +/// Disables the processor clock, making the device enter Idle mode. +//------------------------------------------------------------------------------ +void PMC_DisableProcessorClock(void) +{ + AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_PCK; + while ((AT91C_BASE_PMC->PMC_SCSR & AT91C_PMC_PCK) != AT91C_PMC_PCK); +} + +//------------------------------------------------------------------------------ +/// Enables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used +/// to identify which peripheral is targetted. +/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx). +/// \param id Peripheral ID (AT91C_ID_xxx). +//------------------------------------------------------------------------------ +void PMC_EnablePeripheral(unsigned int id) +{ + SANITY_CHECK(id < 32); + + if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) == (1 << id)) { + + trace_LOG(trace_INFO, + "-I- PMC_EnablePeripheral: clock of peripheral" + " %u is already enabled\n\r", + id); + } + else { + + AT91C_BASE_PMC->PMC_PCER = 1 << id; + } +} + +//------------------------------------------------------------------------------ +/// Disables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used +/// to identify which peripheral is targetted. +/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx). +/// \param id Peripheral ID (AT91C_ID_xxx). +//------------------------------------------------------------------------------ +void PMC_DisablePeripheral(unsigned int id) +{ + SANITY_CHECK(id < 32); + + if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) != (1 << id)) { + + trace_LOG(trace_INFO, + "-I- PMC_DisablePeripheral: clock of peripheral" + " %u is not enabled\n\r", + id); + } + else { + + AT91C_BASE_PMC->PMC_PCDR = 1 << id; + } +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.h new file mode 100644 index 0000000..5b885df --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef PMC_H +#define PMC_H + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +#if defined(at91sam7l64) || defined(at91sam7l128) +extern void PMC_SetFastWakeUpInputs(unsigned int inputs); +extern void PMC_DisableMainOscillator(void); +extern +#ifdef __ICCARM__ +__ramfunc +#endif +void PMC_DisableMainOscillatorForWaitMode(void); +#endif + +extern void PMC_DisableProcessorClock(void); + +extern void PMC_EnablePeripheral(unsigned int id); + +extern void PMC_DisablePeripheral(unsigned int id); +#endif //#ifndef PMC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.c new file mode 100644 index 0000000..7bbe698 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.c @@ -0,0 +1,238 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pwmc.h" +#include +#include +#include + +//------------------------------------------------------------------------------ +// Local functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Finds a prescaler/divisor couple to generate the desired frequency from +/// MCK. +/// Returns the value to enter in PWMC_MR or 0 if the configuration cannot be +/// met. +/// \param frequency Desired frequency in Hz. +/// \param mck Master clock frequency in Hz. +//------------------------------------------------------------------------------ +static unsigned short FindClockConfiguration( + unsigned int frequency, + unsigned int mck) +{ + unsigned int divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024}; + unsigned char divisor = 0; + unsigned int prescaler; + + SANITY_CHECK(frequency < mck); + + // Find prescaler and divisor values + prescaler = (mck / divisors[divisor]) / frequency; + while ((prescaler > 255) && (divisor < 11)) { + + divisor++; + prescaler = (mck / divisors[divisor]) / frequency; + } + + // Return result + if (divisor < 11) { + + trace_LOG(trace_DEBUG, "-D- Found divisor=%u and prescaler=%u for freq=%uHz\n\r", + divisors[divisor], prescaler, frequency); + return prescaler | (divisor << 8); + } + else { + + return 0; + } +} + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures PWM a channel with the given parameters. +/// The PWM controller must have been clocked in the PMC prior to calling this +/// function. +/// \param channel Channel number. +/// \param prescaler Channel prescaler. +/// \param alignment Channel alignment. +/// \param polarity Channel polarity. +//------------------------------------------------------------------------------ +void PWMC_ConfigureChannel( + unsigned char channel, + unsigned int prescaler, + unsigned int alignment, + unsigned int polarity) +{ + SANITY_CHECK(prescaler < AT91C_PWMC_CPRE_MCKB); + SANITY_CHECK((alignment & ~AT91C_PWMC_CALG) == 0); + SANITY_CHECK((polarity & ~AT91C_PWMC_CPOL) == 0); + + // Disable channel + AT91C_BASE_PWMC->PWMC_DIS = 1 << channel; + + // Configure channel + AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR = prescaler | alignment | polarity; +} + +//------------------------------------------------------------------------------ +/// Configures PWM clocks A & B to run at the given frequencies. This function +/// finds the best MCK divisor and prescaler values automatically. +/// \param clka Desired clock A frequency (0 if not used). +/// \param clkb Desired clock B frequency (0 if not used). +/// \param mck Master clock frequency. +//------------------------------------------------------------------------------ +void PWMC_ConfigureClocks(unsigned int clka, unsigned int clkb, unsigned int mck) +{ + unsigned int mode = 0; + unsigned int result; + + // Clock A + if (clka != 0) { + + result = FindClockConfiguration(clka, mck); + ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clka); + mode |= result; + } + + // Clock B + if (clkb != 0) { + + result = FindClockConfiguration(clkb, mck); + ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clkb); + mode |= (result << 16); + } + + // Configure clocks + trace_LOG(trace_DEBUG, "-D- Setting PWMC_MR = 0x%08X\n\r", mode); + AT91C_BASE_PWMC->PWMC_MR = mode; +} + +//------------------------------------------------------------------------------ +/// Sets the period value used by a PWM channel. This function writes directly +/// to the CPRD register if the channel is disabled; otherwise, it uses the +/// update register CUPD. +/// \param channel Channel number. +/// \param period Period value. +//------------------------------------------------------------------------------ +void PWMC_SetPeriod(unsigned char channel, unsigned short period) +{ + // If channel is disabled, write to CPRD + if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) { + + AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR = period; + } + // Otherwise use update register + else { + + AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR |= AT91C_PWMC_CPD; + AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = period; + } +} + +//------------------------------------------------------------------------------ +/// Sets the duty cycle used by a PWM channel. This function writes directly to +/// the CDTY register if the channel is disabled; otherwise it uses the +/// update register CUPD. +/// Note that the duty cycle must always be inferior or equal to the channel +/// period. +/// \param channel Channel number. +/// \param duty Duty cycle value. +//------------------------------------------------------------------------------ +void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty) +{ + SANITY_CHECK(duty <= AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR); + + // SAM7S errata +#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \ + || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \ + || defined(at91sam7s256) || defined(at91sam7s512) + ASSERT(duty > 0, "-F- Duty cycle value 0 is not permitted on SAM7S chips.\n\r"); + ASSERT((duty > 1) || (AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR & AT91C_PWMC_CALG), + "-F- Duty cycle value 1 is not permitted in left-aligned mode on SAM7S chips.\n\r"); +#endif + + // If channel is disabled, write to CDTY + if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) { + + AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CDTYR = duty; + } + // Otherwise use update register + else { + + AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR &= ~AT91C_PWMC_CPD; + AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = duty; + } +} + +//------------------------------------------------------------------------------ +/// Enables the given PWM channel. This does NOT enable the corresponding pin; +/// this must be done in the user code. +/// \param channel Channel number. +//------------------------------------------------------------------------------ +void PWMC_EnableChannel(unsigned char channel) +{ + AT91C_BASE_PWMC->PWMC_ENA = 1 << channel; +} + +//------------------------------------------------------------------------------ +/// Disables the given PWM channel. +/// \param channel Channel number. +//------------------------------------------------------------------------------ +void PWMC_DisableChannel(unsigned char channel) +{ + AT91C_BASE_PWMC->PWMC_DIS = 1 << channel; +} + +//------------------------------------------------------------------------------ +/// Enables the period interrupt for the given PWM channel. +/// \param channel Channel number. +//------------------------------------------------------------------------------ +void PWMC_EnableChannelIt(unsigned char channel) +{ + AT91C_BASE_PWMC->PWMC_IER = 1 << channel; +} + +//------------------------------------------------------------------------------ +/// Disables the period interrupt for the given PWM channel. +/// \param channel Channel number. +//------------------------------------------------------------------------------ +void PWMC_DisableChannelIt(unsigned char channel) +{ + AT91C_BASE_PWMC->PWMC_IDR = 1 << channel; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.h new file mode 100644 index 0000000..fd20abf --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.h @@ -0,0 +1,61 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef PWMC_H +#define PWMC_H + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void PWMC_ConfigureChannel( + unsigned char channel, + unsigned int prescaler, + unsigned int alignment, + unsigned int polarity); + +extern void PWMC_ConfigureClocks + (unsigned int clka, + unsigned int clkb, + unsigned int mck); + +extern void PWMC_SetPeriod(unsigned char channel, unsigned short period); + +extern void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty); + +extern void PWMC_EnableChannel(unsigned char channel); + +extern void PWMC_DisableChannel(unsigned char channel); + +extern void PWMC_EnableChannelIt(unsigned char channel); + +extern void PWMC_DisableChannelIt(unsigned char channel); + +#endif //#ifndef PWMC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.c new file mode 100644 index 0000000..6b93365 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include + +//----------------------------------------------------------------------------- +// Macros +//----------------------------------------------------------------------------- + +/// WRITE_RSTC: Write RSTC register +#define WRITE_RSTC(pRstc, regName, value) pRstc->regName = (value) + +/// READ_RSTC: Read RSTC registers +#define READ_RSTC(pRstc, regName) (pRstc->regName) + +//----------------------------------------------------------------------------- +// Defines +//----------------------------------------------------------------------------- + +/// Keywords to write to the reset registers +#define RSTC_KEY_PASSWORD (0xA5UL << 24) + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Configure the mode of the RSTC peripheral. +/// The configuration is computed by the lib (AT91C_RSTC_*). +/// \param rstc Pointer to an RSTC peripheral. +/// \param rmr Desired mode configuration. +//----------------------------------------------------------------------------- +void RSTC_ConfigureMode(AT91PS_RSTC rstc, unsigned int rmr) +{ + rmr &= ~AT91C_RSTC_KEY; + WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD); +} + +//----------------------------------------------------------------------------- +/// Enable/Disable the detection of a low level on the pin NRST as User Reset +/// \param rstc Pointer to an RSTC peripheral. +/// \param enable 1 to enable & 0 to disable. +//----------------------------------------------------------------------------- +void RSTC_SetUserResetEnable(AT91PS_RSTC rstc, unsigned char enable) +{ + unsigned int rmr = READ_RSTC(rstc, RSTC_RMR) & (~AT91C_RSTC_KEY); + if (enable) { + + rmr |= AT91C_RSTC_URSTEN; + } + else { + + rmr &= ~AT91C_RSTC_URSTEN; + } + WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD); +} + +//----------------------------------------------------------------------------- +/// Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST). +/// \param rstc Pointer to an RSTC peripheral. +/// \param enable 1 to enable & 0 to disable. +//----------------------------------------------------------------------------- +void RSTC_SetUserResetInterruptEnable(AT91PS_RSTC rstc, unsigned char enable) +{ + unsigned int rmr = READ_RSTC(rstc, RSTC_RMR) & (~AT91C_RSTC_KEY); + if (enable) { + + rmr |= AT91C_RSTC_URSTIEN; + } + else { + + rmr &= ~AT91C_RSTC_URSTIEN; + } + WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD); +} + +//----------------------------------------------------------------------------- +/// Setup the external reset length. The length is asserted during a time of +/// pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s. +/// \param rstc Pointer to an RSTC peripheral. +/// \param powl Power length defined. +//----------------------------------------------------------------------------- +void RSTC_SetExtResetLength(AT91PS_RSTC rstc, unsigned char powl) +{ + unsigned int rmr = READ_RSTC(rstc, RSTC_RMR); + rmr &= ~(AT91C_RSTC_KEY | AT91C_RSTC_ERSTL); + rmr |= (powl << 8) & AT91C_RSTC_ERSTL; + WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD); +} + + +//----------------------------------------------------------------------------- +/// Resets the processor. +/// \param rstc Pointer to an RSTC peripheral. +//----------------------------------------------------------------------------- +void RSTC_ProcessorReset(AT91PS_RSTC rstc) +{ + WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_PROCRST | RSTC_KEY_PASSWORD); +} + +//----------------------------------------------------------------------------- +/// Resets the peripherals. +/// \param rstc Pointer to an RSTC peripheral. +//----------------------------------------------------------------------------- +void RSTC_PeripheralReset(AT91PS_RSTC rstc) +{ + WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_PERRST | RSTC_KEY_PASSWORD); +} + +//----------------------------------------------------------------------------- +/// Asserts the NRST pin for external resets. +/// \param rstc Pointer to an RSTC peripheral. +//----------------------------------------------------------------------------- +void RSTC_ExtReset(AT91PS_RSTC rstc) +{ + WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_EXTRST | RSTC_KEY_PASSWORD); +} + +//----------------------------------------------------------------------------- +/// Return NRST pin level ( 1 or 0 ). +/// \param rstc Pointer to an RSTC peripheral. +//----------------------------------------------------------------------------- +unsigned char RSTC_GetNrstLevel(AT91PS_RSTC rstc) +{ + if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_NRSTL) { + + return 1; + } + return 0; +} + +//----------------------------------------------------------------------------- +/// Returns 1 if at least one high-to-low transition of NRST (User Reset) has +/// been detected since the last read of RSTC_RSR. +/// \param rstc Pointer to an RSTC peripheral. +//----------------------------------------------------------------------------- +unsigned char RSTC_IsUserReseetDetected(AT91PS_RSTC rstc) +{ + if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_URSTS) { + + return 1; + } + return 0; +} + +//----------------------------------------------------------------------------- +/// Return 1 if a software reset command is being performed by the reset +/// controller. The reset controller is busy. +/// \param rstc Pointer to an RSTC peripheral. +//----------------------------------------------------------------------------- +unsigned char RSTC_IsBusy(AT91PS_RSTC rstc) +{ + if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_SRCMP) { + + return 1; + } + return 0; +} diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.h new file mode 100644 index 0000000..5306714 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _RSTC_H +#define _RSTC_H + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +extern void RSTC_ConfigureMode(AT91PS_RSTC rstc, unsigned int rmr); + +extern void RSTC_SetUserResetEnable(AT91PS_RSTC rstc, unsigned char enable); + +extern void RSTC_SetUserResetInterruptEnable(AT91PS_RSTC rstc, + unsigned char enable); + +extern void RSTC_SetExtResetLength(AT91PS_RSTC rstc, unsigned char powl); + +extern void RSTC_ProcessorReset(AT91PS_RSTC rstc); + +extern void RSTC_PeripheralReset(AT91PS_RSTC rstc); + +extern void RSTC_ExtReset(AT91PS_RSTC rstc); + +extern unsigned char RSTC_GetNrstLevel(AT91PS_RSTC rstc); + +extern unsigned char RSTC_IsUserReseetDetected(AT91PS_RSTC rstc); + +extern unsigned char RSTC_IsBusy(AT91PS_RSTC rstc); + +#endif // #ifndef _RSTC_H diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.c new file mode 100644 index 0000000..841966e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.c @@ -0,0 +1,338 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef trace_LEVEL + #define trace_LEVEL trace_INFO +#endif + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "rtc.h" +#include +#include +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Sets the RTC in either 12- or 24-hour mode. +/// \param mode Hour mode. +//------------------------------------------------------------------------------ +void RTC_SetHourMode(unsigned int mode) +{ + SANITY_CHECK((mode & 0xFFFFFFFE) == 0); + + trace_LOG(trace_DEBUG, "-D- RTC_SetHourMode()\n\r"); + + AT91C_BASE_RTC->RTC_MR = mode; +} + +//------------------------------------------------------------------------------ +/// Enables the selected interrupt sources of the RTC. +/// \param sources Interrupt sources to enable. +//------------------------------------------------------------------------------ +void RTC_EnableIt(unsigned int sources) +{ + SANITY_CHECK((sources & ~0x1F) == 0); + + trace_LOG(trace_DEBUG, "-D- RTC_EnableIt()\n\r"); + + AT91C_BASE_RTC->RTC_IER = sources; +} + +//------------------------------------------------------------------------------ +/// Disables the selected interrupt sources of the RTC. +/// \param sources Interrupt sources to disable. +//------------------------------------------------------------------------------ +void RTC_DisableIt(unsigned int sources) +{ + SANITY_CHECK((sources & ~0x1F) == 0); + + trace_LOG(trace_DEBUG, "-D- RTC_DisableIt()\n\r"); + + AT91C_BASE_RTC->RTC_IDR = sources; +} + +//------------------------------------------------------------------------------ +/// Sets the current time in the RTC. +/// \param hour Current hour. +/// \param minute Current minute. +/// \param second Current second. +//------------------------------------------------------------------------------ +void RTC_SetTime(unsigned char hour, unsigned char minute, unsigned char second) +{ + unsigned int time; + + SANITY_CHECK(hour < 24); + SANITY_CHECK(minute < 60); + SANITY_CHECK(second < 60); + + trace_LOG(trace_DEBUG, "-D- RTC_SetTime(%02d:%02d:%02d)\n\r", hour, minute, second); + + time = (second % 10) | ((second / 10) << 4) + | ((minute % 10) << 8) | ((minute / 10) << 12); + + // 12-hour mode + if ((AT91C_BASE_RTC->RTC_MR & AT91C_RTC_HRMOD) == AT91C_RTC_HRMOD) { + + if (hour > 12) { + + hour -= 12; + time |= AT91C_RTC_AMPM; + } + } + + time |= ((hour % 10) << 16) | ((hour / 10) << 20); + + // Set time + AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDTIM; + while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD); + AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD; + AT91C_BASE_RTC->RTC_TIMR = time; + AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDTIM; + SANITY_CHECK((AT91C_BASE_RTC->RTC_CR & AT91C_RTC_UPDTIM) != AT91C_RTC_UPDTIM); +} + +//------------------------------------------------------------------------------ +/// Retrieves the current time as stored in the RTC in several variables. +/// \param pHour If not null, current hour is stored in this variable. +/// \param pMinute If not null, current minute is stored in this variable. +/// \param pSecond If not null, current second is stored in this variable. +//------------------------------------------------------------------------------ +void RTC_GetTime( + unsigned char *pHour, + unsigned char *pMinute, + unsigned char *pSecond) +{ + unsigned int time; + + SANITY_CHECK(pHour || pMinute || pSecond); + + trace_LOG(trace_DEBUG, "-D- RTC_GetTime()\n\r"); + + // Get current RTC time + time = AT91C_BASE_RTC->RTC_TIMR; + while (time != AT91C_BASE_RTC->RTC_TIMR) { + + time = AT91C_BASE_RTC->RTC_TIMR; + } + + // Hour + if (pHour) { + + *pHour = ((time & 0x00300000) >> 20) * 10 + + ((time & 0x000F0000) >> 16); + if ((time & AT91C_RTC_AMPM) == AT91C_RTC_AMPM) { + + *pHour += 12; + } + } + + // Minute + if (pMinute) { + + *pMinute = ((time & 0x00007000) >> 12) * 10 + + ((time & 0x00000F00) >> 8); + } + + // Second + if (pSecond) { + + *pSecond = ((time & 0x00000070) >> 4) * 10 + + (time & 0x0000000F); + } +} + +//------------------------------------------------------------------------------ +/// Sets a time alarm on the RTC. The match is performed only on the provided +/// variables; setting all pointers to 0 disables the time alarm. +/// Note: in AM/PM mode, the hour value must have bit #7 set for PM, cleared for +/// AM (as expected in the time registers). +/// \param pHour If not null, the time alarm will hour-match this value. +/// \param pMinute If not null, the time alarm will minute-match this value. +/// \param pSecond If not null, the time alarm will second-match this value. +//------------------------------------------------------------------------------ +void RTC_SetTimeAlarm( + unsigned char *pHour, + unsigned char *pMinute, + unsigned char *pSecond) +{ + unsigned int alarm = 0; + + SANITY_CHECK(!pHour || ((*pHour & 0x80) == 0)); + SANITY_CHECK(!pMinute || (*pMinute < 60)); + SANITY_CHECK(!pSecond || (*pSecond < 60)); + + trace_LOG(trace_DEBUG, "-D- RTC_SetTimeAlarm()\n\r"); + + // Hour + if (pHour) { + + alarm |= AT91C_RTC_HOUREN | ((*pHour / 10) << 20) | ((*pHour % 10) << 16); + } + + // Minute + if (pMinute) { + + alarm |= AT91C_RTC_MINEN | ((*pMinute / 10) << 12) | ((*pMinute % 10) << 8); + } + + // Second + if (pSecond) { + + alarm |= AT91C_RTC_SECEN | ((*pSecond / 10) << 4) | (*pSecond % 10); + } + + AT91C_BASE_RTC->RTC_TIMALR = alarm; +} + +//------------------------------------------------------------------------------ +/// Retrieves the current year, month and day from the RTC. Month, day and week +/// values are numbered starting at 1. +/// \param pYear Current year (optional). +/// \param pMonth Current month (optional). +/// \param pDay Current day (optional). +/// \param pWeek Current day in current week (optional). +//------------------------------------------------------------------------------ +void RTC_GetDate( + unsigned short *pYear, + unsigned char *pMonth, + unsigned char *pDay, + unsigned char *pWeek) +{ + unsigned int date; + + // Get current date (multiple reads are necessary to insure a stable value) + do { + + date = AT91C_BASE_RTC->RTC_CALR; + } + while (date != AT91C_BASE_RTC->RTC_CALR); + + // Retrieve year + if (pYear) { + + *pYear = (((date >> 4) & 0x7) * 1000) + + ((date & 0xF) * 100) + + (((date >> 12) & 0xF) * 10) + + ((date >> 8) & 0xF); + } + + // Retrieve month + if (pMonth) { + + *pMonth = (((date >> 20) & 1) * 10) + ((date >> 16) & 0xF); + } + + // Retrieve day + if (pDay) { + + *pDay = (((date >> 28) & 0x3) * 10) + ((date >> 24) & 0xF); + } + + // Retrieve week + if (pWeek) { + + *pWeek = ((date >> 21) & 0x7); + } +} + +//------------------------------------------------------------------------------ +/// Sets the current year, month and day in the RTC. Month, day and week values +/// must be numbered starting from 1. +/// \param year Current year. +/// \param month Current month. +/// \param day Current day. +/// \param week Day number in current week. +//------------------------------------------------------------------------------ +void RTC_SetDate( + unsigned short year, + unsigned char month, + unsigned char day, + unsigned char week) +{ + unsigned int date; + + SANITY_CHECK((year >= 1900) && (year <= 2099)); + SANITY_CHECK((month >= 1) && (month <= 12)); + SANITY_CHECK((day >= 1) && (day <= 31)); + SANITY_CHECK((week >= 1) && (week <= 7)); + + // Convert values to date register value + date = ((year / 100) % 10) + | ((year / 1000) << 4) + | ((year % 10) << 8) + | (((year / 10) % 10) << 12) + | ((month % 10) << 16) + | ((month / 10) << 20) + | (week << 21) + | ((day % 10) << 24) + | ((day / 10) << 28); + + // Update calendar register + AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDCAL; + while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD); + AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD; + AT91C_BASE_RTC->RTC_CALR = date; + AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDCAL; +} + +//------------------------------------------------------------------------------ +/// Sets a date alarm in the RTC. The alarm will match only the provided values; +/// passing a null-pointer disables the corresponding field match. +/// \param pMonth If not null, the RTC alarm will month-match this value. +/// \param pDay If not null, the RTC alarm will day-match this value. +//------------------------------------------------------------------------------ +void RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay) +{ + unsigned int alarm = 0; + + SANITY_CHECK(!pMonth || ((*pMonth >= 1) && (*pMonth <= 12))); + SANITY_CHECK(!pDay || ((*pDay >= 1) && (*pDay <= 31))); + + trace_LOG(trace_DEBUG, "-D- RTC_SetDateAlarm()\n\r"); + + // Compute alarm field value + if (pMonth) { + + alarm |= AT91C_RTC_MONTHEN | ((*pMonth / 10) << 20) | ((*pMonth % 10) << 16); + } + if (pDay) { + + alarm |= AT91C_RTC_DATEEN | ((*pDay / 10) << 28) | ((*pDay % 10) << 24); + } + + // Set alarm + AT91C_BASE_RTC->RTC_CALALR = alarm; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.h new file mode 100644 index 0000000..3fbbdcf --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef RTC_H +#define RTC_H + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void RTC_SetHourMode(unsigned int mode); + +extern void RTC_EnableIt(unsigned int sources); + +extern void RTC_DisableIt(unsigned int sources); + +extern void RTC_SetTime( + unsigned char hour, + unsigned char minute, + unsigned char second); + +extern void RTC_GetTime( + unsigned char *pHour, + unsigned char *pMinute, + unsigned char *pSecond); + +extern void RTC_SetTimeAlarm( + unsigned char *pHour, + unsigned char *pMinute, + unsigned char *pSecond); + +void RTC_GetDate( + unsigned short *pYear, + unsigned char *pMonth, + unsigned char *pDay, + unsigned char *pWeek); + +extern void RTC_SetDate( + unsigned short year, + unsigned char month, + unsigned char day, + unsigned char week); + +extern void RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay); + +#endif //#ifndef RTC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.c new file mode 100644 index 0000000..5322108 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "rtt.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Changes the prescaler value of the given RTT and restarts it. This function +/// disables RTT interrupt sources. +/// \param rtt Pointer to a AT91S_RTTC instance. +/// \param prescaler Prescaler value for the RTT. +//------------------------------------------------------------------------------ +void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler) +{ + rtt->RTTC_RTMR = (prescaler | AT91C_RTTC_RTTRST); +} + +//------------------------------------------------------------------------------ +/// Returns the current value of the RTT timer value. +/// \param rtt Pointer to a AT91S_RTTC instance. +//------------------------------------------------------------------------------ +unsigned int RTT_GetTime(AT91S_RTTC *rtt) +{ + return rtt->RTTC_RTVR; +} + +//------------------------------------------------------------------------------ +/// Enables the specified RTT interrupt sources. +/// \param rtt Pointer to a AT91S_RTTC instance. +/// \param sources Bitmask of interrupts to enable. +//------------------------------------------------------------------------------ +void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources) +{ + ASSERT((sources & 0x0004FFFF) == 0, + "RTT_EnableIT: Wrong sources value.\n\r"); + rtt->RTTC_RTMR |= sources; +} + +//------------------------------------------------------------------------------ +/// Returns the status register value of the given RTT. +/// \param rtt Pointer to an AT91S_RTTC instance. +//------------------------------------------------------------------------------ +unsigned int RTT_GetStatus(AT91S_RTTC *rtt) +{ + return rtt->RTTC_RTSR; +} + +//------------------------------------------------------------------------------ +/// Configures the RTT to generate an alarm at the given time. +/// \param pRtt Pointer to an AT91S_RTTC instance. +/// \param time Alarm time. +//------------------------------------------------------------------------------ +void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time) +{ + SANITY_CHECK(time > 0); + + pRtt->RTTC_RTAR = time - 1; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.h new file mode 100644 index 0000000..f92abe8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef RTT_H +#define RTT_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#ifndef AT91C_BASE_RTTC + #define AT91C_BASE_RTTC AT91C_BASE_RTTC0 +#endif + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler); + +extern unsigned int RTT_GetTime(AT91S_RTTC *rtt); + +extern void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources); + +extern unsigned int RTT_GetStatus(AT91S_RTTC *rtt); + +extern void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time); + +#endif //#ifndef RTT_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.c new file mode 100644 index 0000000..4331ea8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "slcdc.h" +#include +#include + +#include + +//------------------------------------------------------------------------------ +// Local definitions +//------------------------------------------------------------------------------ + +/// Size of SLCDC buffer in bytes. +#define BUFFER_SIZE 320 + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Initializes the Segment LCD controller. +/// \param commons Number of commons used by the display. +/// \param segments Number of segments used by the display. +/// \param bias Bias value. +/// \param timeSetting Buffer timing value. +//------------------------------------------------------------------------------ +void SLCDC_Configure( + unsigned int commons, + unsigned int segments, + unsigned int bias, + unsigned int timeSetting) +{ + SANITY_CHECK((commons > 0) && (commons <= 10)); + SANITY_CHECK((segments > 0) && (segments <= 40)); + SANITY_CHECK((bias & ~AT91C_SLCDC_BIAS) == 0); + SANITY_CHECK((timeSetting & ~(0xF << 16)) == 0); + SANITY_CHECK((timeSetting >> 16) < 0x0A); + + // Enable peripheral clock + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SLCD; + AT91C_BASE_SLCDC->SLCDC_MR = (commons - 1) | ((segments - 1) << 8) | bias | timeSetting; +} + +//------------------------------------------------------------------------------ +/// Clears the SLCD display buffer. +//------------------------------------------------------------------------------ +void SLCDC_Clear(void) +{ + memset((void *) AT91C_BASE_SLCDC->SLCDC_MEM, 0, BUFFER_SIZE); +} + +//------------------------------------------------------------------------------ +/// Enables the SLCD controller. +//------------------------------------------------------------------------------ +void SLCDC_Enable(void) +{ + AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDEN; + while (AT91C_BASE_SLCDC -> SLCDC_SR != AT91C_SLCDC_ENA); +} + +//------------------------------------------------------------------------------ +/// Disables the SLCD controller. +//------------------------------------------------------------------------------ +void SLCDC_Disable(void) +{ + AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDDIS; +} + +//------------------------------------------------------------------------------ +/// Enables the SLCD low power mode. +//------------------------------------------------------------------------------ +void SLCDC_EnableLowPowerMode(void) +{ + unsigned int value; + + value = AT91C_BASE_SLCDC->SLCDC_MR; + value &= ~AT91C_SLCDC_LPMODE; + value |=AT91C_SLCDC_LPMODE; + AT91C_BASE_SLCDC->SLCDC_MR = value; +} + +//------------------------------------------------------------------------------ +/// Disables the SLCD low power mode +//------------------------------------------------------------------------------ +void SLCDC_DisableLowPowerMode(void) +{ + unsigned int value; + + value = AT91C_BASE_SLCDC->SLCDC_MR; + value &= ~AT91C_SLCDC_LPMODE; + AT91C_BASE_SLCDC->SLCDC_MR = value; +} + +//------------------------------------------------------------------------------ +/// Adjusts the frame frequency. Frequency = FsCLK / (prescaler * divider . NCOM) +/// \param prescalerValue Prescaler value +/// \param dividerValue Divider value +//------------------------------------------------------------------------------ +void SLCDC_SetFrameFreq(unsigned int prescalerValue, unsigned int dividerValue) +{ + SANITY_CHECK((prescalerValue & ~AT91C_SLCDC_PRESC) == 0); + SANITY_CHECK((dividerValue & (~(0x07 << 8))) == 0); + + AT91C_BASE_SLCDC->SLCDC_FRR = prescalerValue | dividerValue; +} + +//------------------------------------------------------------------------------ +/// Sets the display mode (normal/force off/force on/blinking). +/// \param mode Display mode to be set +//------------------------------------------------------------------------------ +void SLCDC_SetDisplayMode(unsigned int mode) +{ + unsigned int value; + + SANITY_CHECK(mode < 8); + + value = AT91C_BASE_SLCDC->SLCDC_DR; + value &= ~AT91C_SLCDC_DISPMODE; + value |= mode; + AT91C_BASE_SLCDC->SLCDC_DR = value; +} + +//------------------------------------------------------------------------------ +/// Adjusts the display blinking frequency. +/// Blinking frequency = Frame Frequency / LCDBLKFREQ. +/// \param frequency Frequency value. +//------------------------------------------------------------------------------ +void SLCDC_SetBlinkFreq(unsigned int frequency) +{ + unsigned int value; + + SANITY_CHECK((frequency & ~(0xFF << 8)) == 0); + + value = AT91C_BASE_SLCDC->SLCDC_DR; + value &= ~AT91C_SLCDC_BLKFREQ; + value |= frequency; + AT91C_BASE_SLCDC->SLCDC_DR = frequency; +} + +//------------------------------------------------------------------------------ +/// Enables the selected SLCDC interrupt sources. +/// \param sources Interrupt sources to enable. +//------------------------------------------------------------------------------ +void SLCDC_EnableInterrupts(unsigned int sources) +{ + SANITY_CHECK((sources & 0xFFFFFFFA) == 0); + + AT91C_BASE_SLCDC->SLCDC_IER = sources; +} + +//------------------------------------------------------------------------------ +/// Disables the selected SLCDC interrupt sources. +/// \param sources Interrupt sources to disable. +//------------------------------------------------------------------------------ +void SLCDC_DisableInterrupts(unsigned int sources) +{ + SANITY_CHECK((sources & 0xFFFFFFFA) == 0); + + AT91C_BASE_SLCDC->SLCDC_IDR = sources; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.h new file mode 100644 index 0000000..63a8299 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef SLCDC_H +#define SLCDC_H + +//------------------------------------------------------------------------------ +// Global definitions +//------------------------------------------------------------------------------ + +/// Number of segments in SLCD. +#define S7LEKLCD_NUM_SEGMENTS 40 +/// Number of commons in SLCD. +#define S7LEKLCD_NUM_COMMONS 10 + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void SLCDC_Configure( + unsigned int commons, + unsigned int segments, + unsigned int bias, + unsigned int timeSetting); + +extern void SLCDC_Clear(void); + +extern void SLCDC_Enable(void); + +extern void SLCDC_Disable(void); + +extern void SLCDC_SetFrameFreq( + unsigned int prescalerValue, + unsigned int dividerValue); + +extern void SLCDC_SetDisplayMode(unsigned int mode); + +extern void SLCDC_SetBlinkFreq(unsigned int frequency); + +extern void SLCDC_EnableInterrupts(unsigned int sources); + +extern void SLCDC_DisableInterrupts(unsigned int sources); + +#endif //#ifndef SLCDC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/spi/spi.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/spi/spi.c new file mode 100644 index 0000000..e77d28f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/spi/spi.c @@ -0,0 +1,189 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "spi.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Enables a SPI peripheral +/// \param spi Pointer to an AT91S_SPI instance. +//------------------------------------------------------------------------------ +void SPI_Enable(AT91S_SPI *spi) +{ + spi->SPI_CR = AT91C_SPI_SPIEN; +} + +//------------------------------------------------------------------------------ +/// Disables a SPI peripheral. +/// \param spi Pointer to an AT91S_SPI instance. +//------------------------------------------------------------------------------ +void SPI_Disable(AT91S_SPI *spi) +{ + spi->SPI_CR = AT91C_SPI_SPIDIS; +} + +//------------------------------------------------------------------------------ +/// Configures a SPI peripheral as specified. The configuration can be computed +/// using several macros (see "SPI configuration macros") and the constants +/// defined in LibV3 (AT91C_SPI_*). +/// \param spi Pointer to an AT91S_SPI instance. +/// \param id Peripheral ID of the SPI. +/// \param configuration Value of the SPI configuration register. +//------------------------------------------------------------------------------ +void SPI_Configure(AT91S_SPI *spi, + unsigned int id, + unsigned int configuration) +{ + AT91C_BASE_PMC->PMC_PCER = 1 << id; + spi->SPI_CR = AT91C_SPI_SPIDIS | AT91C_SPI_SWRST; + spi->SPI_MR = configuration; +} + +//------------------------------------------------------------------------------ +/// Configures a chip select of a SPI peripheral. The chip select configuration +/// is computed using the definition provided by the LibV3 (AT91C_SPI_*). +/// \param spi Pointer to an AT91S_SPI instance. +/// \param npcs Chip select to configure (1, 2, 3 or 4). +/// \param configuration Desired chip select configuration. +//------------------------------------------------------------------------------ +void SPI_ConfigureNPCS(AT91S_SPI *spi, + unsigned int npcs, + unsigned int configuration) +{ + spi->SPI_CSR[npcs] = configuration; +} + +//------------------------------------------------------------------------------ +/// Sends data through a SPI peripheral. If the SPI is configured to use a fixed +/// peripheral select, the npcs value is meaningless. Otherwise, it identifies +/// the component which shall be addressed. +/// \param spi Pointer to an AT91S_SPI instance. +/// \param npcs Chip select of the component to address (1, 2, 3 or 4). +/// \param data Word of data to send. +//------------------------------------------------------------------------------ +void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data) +{ + // Discard contents of RDR register + //volatile unsigned int discard = spi->SPI_RDR; + + // Send data + while ((spi->SPI_SR & AT91C_SPI_TXEMPTY) == 0); + spi->SPI_TDR = data | SPI_PCS(npcs); + while ((spi->SPI_SR & AT91C_SPI_TDRE) == 0); +} + +//------------------------------------------------------------------------------ +/// Sends the contents of buffer through a SPI peripheral, using the PDC to +/// take care of the transfer. +/// \param spi Pointer to an AT91S_SPI instance. +/// \param buffer Data buffer to send. +/// \param length Length of the data buffer. +//------------------------------------------------------------------------------ +unsigned char SPI_WriteBuffer(AT91S_SPI *spi, + void *buffer, + unsigned int length) +{ + // Check if first bank is free + if (spi->SPI_TCR == 0) { + + spi->SPI_TPR = (unsigned int) buffer; + spi->SPI_TCR = length; + spi->SPI_PTCR = AT91C_PDC_TXTEN; + return 1; + } + // Check if second bank is free + else if (spi->SPI_TNCR == 0) { + + spi->SPI_TNPR = (unsigned int) buffer; + spi->SPI_TNCR = length; + return 1; + } + + // No free banks + return 0; +} + +//------------------------------------------------------------------------------ +/// Returns 1 if there is no pending write operation on the SPI; otherwise +/// returns 0. +/// \param pSpi Pointer to an AT91S_SPI instance. +//------------------------------------------------------------------------------ +unsigned char SPI_IsFinished(AT91S_SPI *pSpi) +{ + return ((pSpi->SPI_SR & AT91C_SPI_TXEMPTY) != 0); +} + +//------------------------------------------------------------------------------ +/// Reads and returns the last word of data received by a SPI peripheral. This +/// method must be called after a successful SPI_Write call. +/// \param spi Pointer to an AT91S_SPI instance. +//------------------------------------------------------------------------------ +unsigned short SPI_Read(AT91S_SPI *spi) +{ + while ((spi->SPI_SR & AT91C_SPI_RDRF) == 0); + return spi->SPI_RDR & 0xFFFF; +} + +//------------------------------------------------------------------------------ +/// Reads data from a SPI peripheral until the provided buffer is filled. This +/// method does NOT need to be called after SPI_Write or SPI_WriteBuffer. +/// \param spi Pointer to an AT91S_SPI instance. +/// \param buffer Data buffer to store incoming bytes. +/// \param length Length in bytes of the data buffer. +//------------------------------------------------------------------------------ +unsigned char SPI_ReadBuffer(AT91S_SPI *spi, + void *buffer, + unsigned int length) +{ + // Check if the first bank is free + if (spi->SPI_RCR == 0) { + + spi->SPI_RPR = (unsigned int) buffer; + spi->SPI_RCR = length; + spi->SPI_PTCR = AT91C_PDC_RXTEN; + return 1; + } + // Check if second bank is free + else if (spi->SPI_RNCR == 0) { + + spi->SPI_RNPR = (unsigned int) buffer; + spi->SPI_RNCR = length; + return 1; + } + + // No free bank + return 0; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/spi/spi.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/spi/spi.h new file mode 100644 index 0000000..39d803e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/spi/spi.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Definitions for SPI peripheral usage. +/// +/// !Usage +/// +/// -# Enable the SPI pins required by the application (see pio.h). +/// -# Configure the SPI using the SPI_Configure function. This enables the +/// peripheral clock. The mode register is loaded with the given value. +/// -# Configure all the necessary chip selects with SPI_ConfigureNPCS. +/// -# Enable the SPI by calling SPI_Enable. +/// -# Send/receive data using SPI_Write and SPI_Read. Note that SPI_Read +/// must be called after SPI_Write to retrieve the last value read. +/// -# Send/receive data using the PDC with the SPI_WriteBuffer and +/// SPI_ReadBuffer functions. +/// -# Disable the SPI by calling SPI_Disable. +//------------------------------------------------------------------------------ + +#ifndef SPI_H +#define SPI_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SPI configuration macros" +/// This page lists several macros which should be used when configuring a SPI +/// peripheral. +/// +/// !Macros +/// - SPI_PCS +/// - SPI_SCBR +/// - SPI_DLYBS +/// - SPI_DLYBCT + +/// Calculate the PCS field value given the chip select NPCS value +#define SPI_PCS(npcs) ((~(1 << npcs) & 0xF) << 16) + +/// Calculates the value of the CSR SCBR field given the baudrate and MCK. +#define SPI_SCBR(baudrate, masterClock) \ + ((unsigned int) (masterClock / baudrate) << 8) + +/// Calculates the value of the CSR DLYBS field given the desired delay (in ns) +#define SPI_DLYBS(delay, masterClock) \ + ((unsigned int) (((masterClock / 1000000) * delay) / 1000) << 16) + +/// Calculates the value of the CSR DLYBCT field given the desired delay (in ns) +#define SPI_DLYBCT(delay, masterClock) \ + ((unsigned int) (((masterClock / 1000000) * delay) / 32000) << 16) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void SPI_Enable(AT91S_SPI *spi); +extern void SPI_Disable(AT91S_SPI *spi); +extern void SPI_Configure(AT91S_SPI *spi, + unsigned int id, + unsigned int configuration); +extern void SPI_ConfigureNPCS(AT91S_SPI *spi, + unsigned int npcs, + unsigned int configuration); +extern void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data); +extern unsigned char SPI_WriteBuffer(AT91S_SPI *spi, + void *buffer, + unsigned int length); + +extern unsigned char SPI_IsFinished(AT91S_SPI *pSpi); + +extern unsigned short SPI_Read(AT91S_SPI *spi); +extern unsigned char SPI_ReadBuffer(AT91S_SPI *spi, + void *buffer, + unsigned int length); + +#endif //#ifndef SPI_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.c new file mode 100644 index 0000000..c0cb000 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.c @@ -0,0 +1,243 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "ssc.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Configures a SSC peripheral. If the divided clock is not used, the master +/// clock frequency can be set to 0. +/// \note The emitter and transmitter are disabled by this function. +/// \param ssc Pointer to an AT91S_SSC instance. +/// \param id Peripheral ID of the SSC. +//------------------------------------------------------------------------------ +void SSC_Configure(AT91S_SSC *ssc, + unsigned int id, + unsigned int bitRate, + unsigned int masterClock) +{ + // Enable SSC peripheral clock + AT91C_BASE_PMC->PMC_PCER = 1 << id; + + // Reset, disable receiver & transmitter + ssc->SSC_CR = AT91C_SSC_RXDIS | AT91C_SSC_TXDIS | AT91C_SSC_SWRST; + ssc->SSC_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS; + + // Configure clock frequency + if (bitRate != 0) { + + ssc->SSC_CMR = masterClock / (2 * bitRate); + } + else { + + ssc->SSC_CMR = 0; + } +} + +//------------------------------------------------------------------------------ +/// Configures the transmitter of a SSC peripheral. Several macros can be used +/// to compute the values of the Transmit Clock Mode Register (TCMR) and the +/// Transmit Frame Mode Register (TFMR) (see "SSC configuration macros"). +/// \param ssc Pointer to a AT91S_SSC instance. +/// \param tcmr Transmit Clock Mode Register value. +/// \param tfmr Transmit Frame Mode Register value. +//------------------------------------------------------------------------------ +void SSC_ConfigureTransmitter(AT91S_SSC *ssc, + unsigned int tcmr, + unsigned int tfmr) +{ + ssc->SSC_TCMR = tcmr; + ssc->SSC_TFMR = tfmr; +} + +//------------------------------------------------------------------------------ +/// Configures the receiver of a SSC peripheral. Several macros can be used +/// to compute the values of the Receive Clock Mode Register (TCMR) and the +/// Receive Frame Mode Register (TFMR) (see "SSC configuration macros"). +/// \param ssc Pointer to a AT91S_SSC instance. +/// \param rcmr Receive Clock Mode Register value. +/// \param rfmr Receive Frame Mode Register value. +//------------------------------------------------------------------------------ +void SSC_ConfigureReceiver(AT91S_SSC *ssc, + unsigned int rcmr, + unsigned int rfmr) +{ + ssc->SSC_RCMR = rcmr; + ssc->SSC_RFMR = rfmr; +} + +//------------------------------------------------------------------------------ +/// Enables the transmitter of a SSC peripheral. +/// \param ssc Pointer to an AT91S_SSC instance. +//------------------------------------------------------------------------------ +void SSC_EnableTransmitter(AT91S_SSC *ssc) +{ + ssc->SSC_CR = AT91C_SSC_TXEN; +} + +//------------------------------------------------------------------------------ +/// Disables the transmitter of a SSC peripheral. +/// \param ssc Pointer to an AT91S_SSC instance. +//------------------------------------------------------------------------------ +void SSC_DisableTransmitter(AT91S_SSC *ssc) +{ + ssc->SSC_CR = AT91C_SSC_TXDIS; +} + +//------------------------------------------------------------------------------ +/// Enables the receiver of a SSC peripheral. +/// \param ssc Pointer to an AT91S_SSC instance. +//------------------------------------------------------------------------------ +void SSC_EnableReceiver(AT91S_SSC *ssc) +{ + ssc->SSC_CR = AT91C_SSC_RXEN; +} + +//------------------------------------------------------------------------------ +/// Disables the receiver of a SSC peripheral. +/// \param ssc Pointer to an AT91S_SSC instance. +//------------------------------------------------------------------------------ +void SSC_DisableReceiver(AT91S_SSC *ssc) +{ + ssc->SSC_CR = AT91C_SSC_RXDIS; +} + +//------------------------------------------------------------------------------ +/// Enables one or more interrupt sources of a SSC peripheral. +/// \param ssc Pointer to an AT91S_SSC instance. +/// \param sources Interrupt sources to enable. +//------------------------------------------------------------------------------ +void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources) +{ + ssc->SSC_IER = sources; +} + +//------------------------------------------------------------------------------ +/// Disables one or more interrupt sources of a SSC peripheral. +/// \param ssc Pointer to an AT91S_SSC instance. +/// \param sources Interrupt source to disable. +//------------------------------------------------------------------------------ +void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources) +{ + ssc->SSC_IDR = sources; +} + +//------------------------------------------------------------------------------ +/// Sends one data frame through a SSC peripheral. If another frame is currently +/// being sent, this function waits for the previous transfer to complete. +/// \param ssc Pointer to an AT91S_SSC instance. +/// \param frame Data frame to send. +//------------------------------------------------------------------------------ +void SSC_Write(AT91S_SSC *ssc, unsigned int frame) +{ + while ((ssc->SSC_SR & AT91C_SSC_TXRDY) == 0); + ssc->SSC_THR = frame; +} + +//------------------------------------------------------------------------------ +/// Sends the contents of a data buffer a SSC peripheral, using the PDC. Returns +/// true if the buffer has been queued for transmission; otherwise returns +/// false. +/// \param ssc Pointer to an AT91S_SSC instance. +/// \param buffer Data buffer to send. +/// \param length Size of the data buffer. +//------------------------------------------------------------------------------ +unsigned char SSC_WriteBuffer(AT91S_SSC *ssc, + void *buffer, + unsigned int length) +{ + // Check if first bank is free + if (ssc->SSC_TCR == 0) { + + ssc->SSC_TPR = (unsigned int) buffer; + ssc->SSC_TCR = length; + ssc->SSC_PTCR = AT91C_PDC_TXTEN; + return 1; + } + // Check if second bank is free + else if (ssc->SSC_TNCR == 0) { + + ssc->SSC_TNPR = (unsigned int) buffer; + ssc->SSC_TNCR = length; + return 1; + } + + // No free banks + return 0; +} + +//------------------------------------------------------------------------------ +/// Waits until one frame is received on a SSC peripheral, and returns it. +/// \param ssc Pointer to an AT91S_SSC instance. +//------------------------------------------------------------------------------ +unsigned int SSC_Read(AT91S_SSC *ssc) +{ + while ((ssc->SSC_SR & AT91C_SSC_RXRDY) == 0); + return ssc->SSC_RHR; +} + +//------------------------------------------------------------------------------ +/// Reads data coming from a SSC peripheral receiver and stores it into the +/// provided buffer. Returns true if the buffer has been queued for reception; +/// otherwise returns false. +/// \param ssc Pointer to an AT91S_SSC instance. +/// \param buffer Data buffer used for reception. +/// \param length Size in bytes of the data buffer. +//------------------------------------------------------------------------------ +unsigned char SSC_ReadBuffer(AT91S_SSC *ssc, + void *buffer, + unsigned int length) +{ + // Check if the first bank is free + if (ssc->SSC_RCR == 0) { + + ssc->SSC_RPR = (unsigned int) buffer; + ssc->SSC_RCR = length; + ssc->SSC_PTCR = AT91C_PDC_RXTEN; + return 1; + } + // Check if second bank is free + else if (ssc->SSC_RNCR == 0) { + + ssc->SSC_RNPR = (unsigned int) buffer; + ssc->SSC_RNCR = length; + return 1; + } + + // No free bank + return 0; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.h new file mode 100644 index 0000000..4fade3a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.h @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Set of functions and definition for using a SSC +/// peripheral. +/// +/// !Usage +/// +/// -# Configure the SSC to operate at a specific frequency by calling +/// SSC_Configure(). This function enables the peripheral clock of the SSC, +/// but not its PIOs. +/// -# Configure the transmitter and/or the receiver using the +/// SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions. +/// -# Enable the PIOs or the transmitter and/or the received using +/// CHIP_EnableSSCTransmitter() and CHIP_EnableSSCReceiver(). +/// -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter() +/// and SSC_EnableReceiver() +/// -# Send data through the transmitter using SSC_Write() and SSC_WriteBuffer() +/// -# Receive data from the receiver using SSC_Read() and SSC_ReadBuffer() +/// -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter() +/// and SSC_DisableReceiver() +//------------------------------------------------------------------------------ + +#ifndef SSC_H +#define SSC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SSC configuration macros" +/// This page lists several macros which are used when configuring a SSC +/// peripheral. +/// +/// !Macros +/// - SSC_STTDLY +/// - SSC_PERIOD +/// - SSC_DATLEN +/// - SSC_DATNB +/// - SSC_FSLEN + +/// Calculates the value of the STTDLY field given the number of clock cycles +/// before the first bit of a new frame is transmitted. +#define SSC_STTDLY(bits) (bits << 16) + +/// Calculates the value of the PERIOD field of the Transmit Clock Mode Register +/// of an SSC interface, given the desired clock divider. +#define SSC_PERIOD(divider) (((divider / 2) - 1) << 24) + +/// Calculates the value of the DATLEN field of the Transmit Frame Mode Register +/// of an SSC interface, given the number of bits in one sample. +#define SSC_DATLEN(bits) (bits - 1) + +/// Calculates the value of the DATNB field of the Transmit Frame Mode Register +/// of an SSC interface, given the number of samples in one frame. +#define SSC_DATNB(samples) ((samples -1) << 8) + +/// Calculates the value of the FSLEN field of the Transmit Frame Mode Register +/// of an SSC interface, given the number of transmit clock periods that the +/// frame sync signal should take. +#define SSC_FSLEN(periods) ((periods - 1) << 16) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void SSC_Configure(AT91S_SSC *ssc, + unsigned int id, + unsigned int bitRate, + unsigned int masterClock); +extern void SSC_ConfigureTransmitter(AT91S_SSC *ssc, + unsigned int tcmr, + unsigned int tfmr); +extern void SSC_ConfigureReceiver(AT91S_SSC *ssc, + unsigned int rcmr, + unsigned int rfmr); + +extern void SSC_EnableTransmitter(AT91S_SSC *ssc); +extern void SSC_DisableTransmitter(AT91S_SSC *ssc); +extern void SSC_EnableReceiver(AT91S_SSC *ssc); +extern void SSC_DisableReceiver(AT91S_SSC *ssc); + +extern void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources); +extern void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources); + +extern void SSC_Write(AT91S_SSC *ssc, unsigned int frame); +extern unsigned char SSC_WriteBuffer(AT91S_SSC *ssc, + void *buffer, + unsigned int length); +extern unsigned int SSC_Read(AT91S_SSC *ssc); +extern unsigned char SSC_ReadBuffer(AT91S_SSC *ssc, + void *buffer, + unsigned int length); + +#endif //#ifndef SSC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/supc/supc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/supc/supc.c new file mode 100644 index 0000000..b63194c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/supc/supc.c @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "supc.h" +#include +#include + +//------------------------------------------------------------------------------ +// Local definitions +//------------------------------------------------------------------------------ + +/// Key value for the SUPC_MR register. +#define SUPC_KEY ((unsigned int) (0xA5 << 24)) + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Enables the SLCD power supply. +/// \param internal If 1, the power supply is configured as internal; otherwise +/// it is set at external. +//------------------------------------------------------------------------------ +void SUPC_EnableSlcd(unsigned char internal) +{ + if (internal) { + + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_INTERNAL; + } + else { + + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_EXTERNAL; + } + while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) != AT91C_SUPC_LCDS); +} + +//------------------------------------------------------------------------------ +/// Disables the SLCD power supply. +//------------------------------------------------------------------------------ +void SUPC_DisableSlcd(void) +{ + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE); + while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) == AT91C_SUPC_LCDS); +} + +//------------------------------------------------------------------------------ +/// Sets the output voltage of the SLCD charge pump. +/// \param voltage Output voltage. +//------------------------------------------------------------------------------ +void SUPC_SetSlcdVoltage(unsigned int voltage) +{ + SANITY_CHECK((voltage & ~AT91C_SUPC_LCDOUT) == 0); + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDOUT) | voltage; +} + +#if !defined(__ICCARM__) +__attribute__ ((section (".ramfunc"))) // GCC +#endif +//------------------------------------------------------------------------------ +/// Enables the flash power supply with the given wake-up setting. +/// \param time Wake-up time. +//------------------------------------------------------------------------------ +void SUPC_EnableFlash(unsigned int time) +{ + AT91C_BASE_SUPC->SUPC_FWUTR = time; + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_FLASHON; + while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) != AT91C_SUPC_FLASHS); +} + +#if !defined(__ICCARM__) +__attribute__ ((section (".ramfunc"))) // GCC +#endif +//------------------------------------------------------------------------------ +/// Disables the flash power supply. +//------------------------------------------------------------------------------ +void SUPC_DisableFlash(void) +{ + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_FLASHON); + while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) == AT91C_SUPC_FLASHS); +} + +//------------------------------------------------------------------------------ +/// Sets the voltage regulator output voltage. +/// \param voltage Voltage to set. +//------------------------------------------------------------------------------ +void SUPC_SetVoltageOutput(unsigned int voltage) +{ + SANITY_CHECK((voltage & ~AT91C_SUPC_VRVDD) == 0); + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRVDD) | voltage; +} + +//------------------------------------------------------------------------------ +/// Puts the voltage regulator in deep mode. +//------------------------------------------------------------------------------ +void SUPC_EnableDeepMode(void) +{ + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_VRDEEP; +} + +//------------------------------------------------------------------------------ +/// Puts the voltage regulator in normal mode. +//------------------------------------------------------------------------------ +void SUPC_DisableDeepMode(void) +{ + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRDEEP); +} + +//----------------------------------------------------------------------------- +/// Enables the backup SRAM power supply, so its data is saved while the device +/// is in backup mode. +//----------------------------------------------------------------------------- +void SUPC_EnableSram(void) +{ + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_SRAMON; +} + +//----------------------------------------------------------------------------- +/// Disables the backup SRAM power supply. +//----------------------------------------------------------------------------- +void SUPC_DisableSram(void) +{ + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_SRAMON); +} + +//----------------------------------------------------------------------------- +/// Enables the RTC power supply. +//----------------------------------------------------------------------------- +void SUPC_EnableRtc(void) +{ + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_RTCON; + while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) != AT91C_SUPC_RTS); +} + +//----------------------------------------------------------------------------- +/// Disables the RTC power supply. +//----------------------------------------------------------------------------- +void SUPC_DisableRtc(void) +{ + AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_RTCON); + while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) == AT91C_SUPC_RTS); +} + +//----------------------------------------------------------------------------- +/// Sets the BOD sampling mode (or disables it). +/// \param mode BOD sampling mode. +//----------------------------------------------------------------------------- +void SUPC_SetBodSampling(unsigned int mode) +{ + SANITY_CHECK((mode & ~AT91C_SUPC_BODSMPL) == 0); + AT91C_BASE_SUPC->SUPC_BOMR &= ~AT91C_SUPC_BODSMPL; + AT91C_BASE_SUPC->SUPC_BOMR |= mode; +} + +//------------------------------------------------------------------------------ +/// Disables the voltage regulator, which makes the device enter backup mode. +//------------------------------------------------------------------------------ +void SUPC_DisableVoltageRegulator(void) +{ + AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_VROFF; + while (1); +} + +//------------------------------------------------------------------------------ +/// Shuts the device down so it enters Off mode. +//------------------------------------------------------------------------------ +void SUPC_Shutdown(void) +{ + AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_SHDW; + while (1); +} + +//------------------------------------------------------------------------------ +/// Sets the wake-up sources when in backup mode. +/// \param sources Wake-up sources to enable. +//------------------------------------------------------------------------------ +void SUPC_SetWakeUpSources(unsigned int sources) +{ + SANITY_CHECK((sources & ~0x0000000B) == 0); + AT91C_BASE_SUPC->SUPC_WUMR &= ~0x0000000B; + AT91C_BASE_SUPC->SUPC_WUMR |= sources; +} + +//------------------------------------------------------------------------------ +/// Sets the wake-up inputs when in backup mode. +/// \param inputs Wake up inputs to enable. +//------------------------------------------------------------------------------ +void SUPC_SetWakeUpInputs(unsigned int inputs) +{ + SANITY_CHECK((inputs & ~0xFFFF) == 0); + AT91C_BASE_SUPC->SUPC_WUIR &= ~0xFFFF; + AT91C_BASE_SUPC->SUPC_WUIR |= inputs; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/supc/supc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/supc/supc.h new file mode 100644 index 0000000..f90df93 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/supc/supc.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef SUPC_H +#define SUPC_H + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void SUPC_EnableSlcd(unsigned char internal); + +extern void SUPC_DisableSlcd(void); + +extern void SUPC_SetSlcdVoltage(unsigned int voltage); + +extern +#ifdef __ICCARM__ +__ramfunc // IAR +#endif +void SUPC_EnableFlash(unsigned int time); + +extern +#ifdef __ICCARM__ +__ramfunc // IAR +#endif +void SUPC_DisableFlash(void); + +extern void SUPC_SetVoltageOutput(unsigned int voltage); + +extern void SUPC_EnableDeepMode(void); + +extern void SUPC_EnableSram(void); + +extern void SUPC_DisableSram(void); + +extern void SUPC_EnableRtc(void); + +extern void SUPC_DisableRtc(void); + +extern void SUPC_SetBodSampling(unsigned int mode); + +extern void SUPC_DisableDeepMode(void); + +extern void SUPC_DisableVoltageRegulator(void); + +extern void SUPC_Shutdown(void); + +extern void SUPC_SetWakeUpSources(unsigned int sources); + +extern void SUPC_SetWakeUpInputs(unsigned int inputs); + +#endif //#ifndef SUPC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tc/tc.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tc/tc.c new file mode 100644 index 0000000..2cce960 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tc/tc.c @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "tc.h" + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures a Timer Counter to operate in the given mode. Timer is stopped +/// after configuration and must be restarted with TC_Start(). +/// to obtain the target frequency. +/// \param pTc Pointer to an AT91S_TC instance. +/// \param mode Operating mode. +//------------------------------------------------------------------------------ +void TC_Configure(AT91S_TC *pTc, unsigned int mode) +{ + // Disable TC clock + pTc->TC_CCR = AT91C_TC_CLKDIS; + + // Disable interrupts + pTc->TC_IDR = 0xFFFFFFFF; + + // Clear status register + pTc->TC_SR; + + // Set mode + pTc->TC_CMR = mode; +} + +//------------------------------------------------------------------------------ +/// Starts the timer clock. +/// \param pTc Pointer to an AT91S_TC instance. +//------------------------------------------------------------------------------ +void TC_Start(AT91S_TC *pTc) +{ + pTc->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; +} + +//------------------------------------------------------------------------------ +/// Stops the timer clock. +/// \param pTc Pointer to an AT91S_TC instance. +//------------------------------------------------------------------------------ +void TC_Stop(AT91S_TC *pTc) +{ + pTc->TC_CCR = AT91C_TC_CLKDIS; +} + +//------------------------------------------------------------------------------ +/// Finds the best MCK divisor given the timer frequency and MCK. The result +/// is guaranteed to satisfy the following equation: +/// (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) +/// with DIV being the highest possible value. +/// Returns 1 if a divisor could be found; otherwise returns 0. +/// \param freq Desired timer frequency. +/// \param mck Master clock frequency. +/// \param div Divisor value. +/// \param tcclks TCCLKS field value for divisor. +//------------------------------------------------------------------------------ +unsigned char TC_FindMckDivisor( + unsigned int freq, + unsigned int mck, + unsigned int *div, + unsigned int *tcclks) +{ + const unsigned int divisors[5] = {2, 8, 32, 128, +#if defined(at91sam9260) || defined(at91sam9261) || defined(at91sam9263) \ + || defined(at91sam9xe) || defined(at91sam9rl64) || defined(at91cap9) + BOARD_MCK / 32768}; +#else + 1024}; +#endif + unsigned int index = 0; + + // Satisfy lower bound + while (freq < ((mck / divisors[index]) / 65536)) { + + index++; + + // If no divisor can be found, return 0 + if (index == 5) { + + return 0; + } + } + + // Try to maximise DIV while satisfying upper bound + while (index < 4) { + + if (freq > (mck / divisors[index + 1])) { + + break; + } + index++; + } + + // Store results + if (div) { + + *div = divisors[index]; + } + if (tcclks) { + + *tcclks = index; + } + + return 1; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tc/tc.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tc/tc.h new file mode 100644 index 0000000..5e4e3ef --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tc/tc.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef TC_H +#define TC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +#if !defined(AT91C_ID_TC0) && defined(AT91C_ID_TC012) + #define AT91C_ID_TC0 AT91C_ID_TC012 +#endif + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void TC_Configure(AT91S_TC *pTc, unsigned int mode); + +extern void TC_Start(AT91S_TC *pTc); + +extern void TC_Stop(AT91S_TC *pTc); + +extern unsigned char TC_FindMckDivisor( + unsigned int freq, + unsigned int mck, + unsigned int *div, + unsigned int *tcclks); + +#endif //#ifndef TC_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.c new file mode 100644 index 0000000..558d3d8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.c @@ -0,0 +1,232 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef trace_LEVEL + #define trace_LEVEL 1 +#endif + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "tdes.h" +#include +#include +#include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures the triple-DES peripheral to cipher/decipher, use single-DES or +/// triple-DES, use two or three keys (when in triple-DES mode), start manually, +/// automatically or via the PDC and use the given operating mode (ECB, CBC, +/// CFB or OFB). +/// \param cipher Encrypts if 1, decrypts if 0. +/// \param tdesmod Single- or triple-DES mode. +/// \param keymod Use two or three keys (must be 0 in single-DES mode). +/// \param smod Start mode. +/// \param opmod Encryption/decryption mode. +//------------------------------------------------------------------------------ +void TDES_Configure( + unsigned char cipher, + unsigned int tdesmod, + unsigned int keymod, + unsigned int smod, + unsigned int opmod) +{ + trace_LOG(trace_DEBUG, "-D- TDES_Configure()\n\r"); + SANITY_CHECK((cipher & 0xFFFFFFFE) == 0); + SANITY_CHECK((tdesmod & 0xFFFFFFFD) == 0); + SANITY_CHECK((keymod & 0xFFFFFFEF) == 0); + SANITY_CHECK((smod & 0xFFFFFCFF) == 0); + SANITY_CHECK((opmod & 0xFFFFCFFF) == 0); + + // Reset peripheral + AT91C_BASE_TDES->TDES_CR = AT91C_TDES_SWRST; + + // Configure mode register + AT91C_BASE_TDES->TDES_MR = cipher | tdesmod | keymod | smod | opmod; +} + +//------------------------------------------------------------------------------ +/// Starts the encryption or decryption process if the TDES peripheral is +/// configured in manual or PDC mode. +//------------------------------------------------------------------------------ +void TDES_Start(void) +{ + trace_LOG(trace_DEBUG, "-D- TDES_Start()\n\r"); + SANITY_CHECK(((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL) + || ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_PDC)); + + // Manual mode + if ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL) { + + AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; + } + // PDC mode + else { + + AT91C_BASE_TDES->TDES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; + } +} + +//------------------------------------------------------------------------------ +/// Returns the current status register value of the TDES peripheral. +//------------------------------------------------------------------------------ +unsigned int TDES_GetStatus(void) +{ + trace_LOG(trace_DEBUG, "-D- TDES_GetStatus()\n\r"); + + return AT91C_BASE_TDES->TDES_ISR; +} + +//------------------------------------------------------------------------------ +/// Sets the 64-bits keys (one, two or three depending on the configuration) +/// that shall be used by the TDES algorithm. +/// \param pKey1 Pointer to key #1. +/// \param pKey2 Pointer to key #2 (shall be 0 in single-DES mode). +/// \param pKey3 Pointer to key #3 (shall be 0 when using two keys). +//------------------------------------------------------------------------------ +void TDES_SetKeys( + const unsigned int *pKey1, + const unsigned int *pKey2, + const unsigned int *pKey3) +{ + trace_LOG(trace_DEBUG, "-D- TDES_SetKeys()\n\r"); + SANITY_CHECK(pKey1); + SANITY_CHECK((pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD)) + || (!pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0))); + SANITY_CHECK((pKey3 + && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD) + && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0)) + || + (!pKey3 + && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD) + && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == AT91C_TDES_KEYMOD)) + || + (!pKey3 + && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0) + && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0))); + + // Write key #1 + if (pKey1) { + + AT91C_BASE_TDES->TDES_KEY1WxR[0] = pKey1[0]; + AT91C_BASE_TDES->TDES_KEY1WxR[1] = pKey1[1]; + } + + // Write key #2 + if (pKey1) { + + AT91C_BASE_TDES->TDES_KEY2WxR[0] = pKey2[0]; + AT91C_BASE_TDES->TDES_KEY2WxR[1] = pKey2[1]; + } + + // Write key #2 + if (pKey1) { + + AT91C_BASE_TDES->TDES_KEY3WxR[0] = pKey3[0]; + AT91C_BASE_TDES->TDES_KEY3WxR[1] = pKey3[1]; + } +} + +//------------------------------------------------------------------------------ +/// Sets the input data to encrypt/decrypt using TDES. +/// \param pInput Pointer to the 64-bits input data. +//------------------------------------------------------------------------------ +void TDES_SetInputData(const unsigned int *pInput) +{ + trace_LOG(trace_DEBUG, "-D- TDES_SetInputData()\n\r"); + SANITY_CHECK(pInput); + + AT91C_BASE_TDES->TDES_IDATAxR[0] = pInput[0]; + AT91C_BASE_TDES->TDES_IDATAxR[1] = pInput[1]; +} + +//------------------------------------------------------------------------------ +/// Sets the input data buffer to encrypt/decrypt when in PDC mode. +/// \param pInput Pointer to the input data. +/// \param size Size of buffer in bytes. +//------------------------------------------------------------------------------ +void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size) +{ + trace_LOG(trace_DEBUG, "-D- TDES_SetInputBuffer()\n\r"); + SANITY_CHECK(pInput); + SANITY_CHECK((size > 0) && ((size % 8) == 0)); + + AT91C_BASE_TDES->TDES_TPR = (unsigned int) pInput; + AT91C_BASE_TDES->TDES_TCR = size / 4; +} + +//------------------------------------------------------------------------------ +/// Stores the output data from the last TDES operation into the given 64-bits +/// buffers. +/// \param pOutput Pointer to a 64-bits output buffer. +//------------------------------------------------------------------------------ +void TDES_GetOutputData(unsigned int *pOutput) +{ + trace_LOG(trace_DEBUG, "-D- TDES_GetOutputData()\n\r"); + SANITY_CHECK(pOutput); + + pOutput[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; + pOutput[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; +} + +//------------------------------------------------------------------------------ +/// Sets the output buffer which will receive the encrypted/decrypted data when +/// using the PDC. +/// \param pOutput Pointer to the output data. +/// \param size Size of buffer in bytes. +//------------------------------------------------------------------------------ +void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size) +{ + trace_LOG(trace_DEBUG, "-D- TDES_SetOutputBuffer()\n\r"); + SANITY_CHECK(pOutput); + SANITY_CHECK((size > 0) && ((size % 8) == 0)); + + AT91C_BASE_TDES->TDES_RPR = (unsigned int) pOutput; + AT91C_BASE_TDES->TDES_RCR = size / 4; +} + +//------------------------------------------------------------------------------ +/// Sets the initialization vector to use when the TDES algorithm is configured +/// in a chained block mode (CBC, CFB or OFB). +/// \param pVector Pointer to the 64-bits vector. +//------------------------------------------------------------------------------ +void TDES_SetVector(const unsigned int *pVector) +{ + trace_LOG(trace_DEBUG, "-D- TDES_SetVector()\n\r"); + SANITY_CHECK(pVector); + + AT91C_BASE_TDES->TDES_IVxR[0] = pVector[0]; + AT91C_BASE_TDES->TDES_IVxR[1] = pVector[1]; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.h new file mode 100644 index 0000000..b73a634 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef TDES_H +#define TDES_H + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void TDES_Configure( + unsigned char cipher, + unsigned int tdesmod, + unsigned int keymod, + unsigned int smod, + unsigned int opmod); + +extern void TDES_Start(void); + +extern unsigned int TDES_GetStatus(void); + +extern void TDES_SetKeys( + const unsigned int *pKey1, + const unsigned int *pKey2, + const unsigned int *pKey3); + +extern void TDES_SetInputData(const unsigned int *pInput); + +extern void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size); + +extern void TDES_GetOutputData(unsigned int *pOutput); + +extern void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size); + +extern void TDES_SetVector(const unsigned int *pVector); + +#endif //#ifndef TDES_H diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/twi/twi.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/twi/twi.c new file mode 100644 index 0000000..4312e7b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/twi/twi.c @@ -0,0 +1,281 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef trace_LEVEL + #define trace_LEVEL 1 +#endif + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "twi.h" +#include +#include +#include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures a TWI peripheral to operate in master mode, at the given +/// frequency (in Hz). The duty cycle of the TWI clock is set to 50%. +/// \param pTwi Pointer to an AT91S_TWI instance. +/// \param twck Desired TWI clock frequency. +/// \param mck Master clock frequency. +//------------------------------------------------------------------------------ +void TWI_Configure(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck) +{ + unsigned int ckdiv = 0; + unsigned int cldiv; + unsigned char ok = 0; + + trace_LOG(trace_DEBUG, "-D- TWI_Configure()\n\r"); + SANITY_CHECK(pTwi); + + // Reset the TWI + pTwi->TWI_CR = AT91C_TWI_SWRST; + + // Set master mode + pTwi->TWI_CR = AT91C_TWI_MSEN; + + // Configure clock + while (!ok) { + + cldiv = ((mck / (2 * twck)) - 3) / power(2, ckdiv); + if (cldiv <= 255) { + + ok = 1; + } + else { + + ckdiv++; + } + } + + ASSERT(ckdiv < 8, "-F- Cannot find valid TWI clock parameters\n\r"); + trace_LOG(trace_INFO, "-D- Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", ckdiv, cldiv); + pTwi->TWI_CWGR = (ckdiv << 16) | (cldiv << 8) | cldiv; +} + +//------------------------------------------------------------------------------ +/// Sends a STOP condition on the TWI. +/// \param pTwi Pointer to an AT91S_TWI instance. +//------------------------------------------------------------------------------ +void TWI_Stop(AT91S_TWI *pTwi) +{ + SANITY_CHECK(pTwi); + + pTwi->TWI_CR = AT91C_TWI_STOP; +} + +//------------------------------------------------------------------------------ +/// Starts a read operation on the TWI bus with the specified slave, and returns +/// immediately. Data must then be read using TWI_ReadByte() whenever a byte is +/// available (poll using TWI_ByteReceived()). +/// \param pTwi Pointer to an AT91S_TWI instance. +/// \param address Slave address on the bus. +/// \param iaddress Optional internal address bytes. +/// \param isize Number of internal address bytes. +//----------------------------------------------------------------------------- +void TWI_StartRead( + AT91S_TWI *pTwi, + unsigned char address, + unsigned int iaddress, + unsigned char isize) +{ + trace_LOG(trace_DEBUG, "-D- TWI_StartRead()\n\r"); + SANITY_CHECK(pTwi); + SANITY_CHECK((address & 0x80) == 0); + SANITY_CHECK((iaddress & 0xFF000000) == 0); + SANITY_CHECK(isize < 4); + + // Set slave address and number of internal address bytes + pTwi->TWI_MMR = (isize << 8) | AT91C_TWI_MREAD | (address << 16); + + // Set internal address bytes + pTwi->TWI_IADR = iaddress; + + // Send START condition + pTwi->TWI_CR = AT91C_TWI_START; +} + +//----------------------------------------------------------------------------- +/// Reads a byte from the TWI bus. The read operation must have been started +/// using TWI_StartRead() and a byte must be available (check with +/// TWI_ByteReceived()). +/// Returns the byte read. +/// \param pTwi Pointer to an AT91S_TWI instance. +//----------------------------------------------------------------------------- +unsigned char TWI_ReadByte(AT91S_TWI *pTwi) +{ + SANITY_CHECK(pTwi); + + return pTwi->TWI_RHR; +} + +//----------------------------------------------------------------------------- +/// Sends a byte of data to one of the TWI slaves on the bus. This function +/// must be called once before TWI_StartWrite() with the first byte of data +/// to send, then it shall be called repeatedly after that to send the +/// remaining bytes. +/// \param pTwi Pointer to an AT91S_TWI instance. +/// \param byte Byte to send. +//----------------------------------------------------------------------------- +void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte) +{ + SANITY_CHECK(pTwi); + + pTwi->TWI_THR = byte; +} + +//----------------------------------------------------------------------------- +/// Starts a write operation on the TWI to access the selected slave, then +/// returns immediately. A byte of data must be provided to start the write; +/// other bytes are written next. +/// \param pTwi Pointer to an AT91S_TWI instance. +/// \param address Address of slave to acccess on the bus. +/// \param iaddress Optional slave internal address. +/// \param isize Number of internal address bytes. +/// \param byte First byte to send. +//----------------------------------------------------------------------------- +void TWI_StartWrite( + AT91S_TWI *pTwi, + unsigned char address, + unsigned int iaddress, + unsigned char isize, + unsigned char byte) +{ + trace_LOG(trace_DEBUG, "-D- TWI_StartWrite()\n\r"); + SANITY_CHECK(pTwi); + SANITY_CHECK((address & 0x80) == 0); + SANITY_CHECK((iaddress & 0xFF000000) == 0); + SANITY_CHECK(isize < 4); + + // Set slave address and number of internal address bytes + pTwi->TWI_MMR = (isize << 8) | (address << 16); + + // Set internal address bytes + pTwi->TWI_IADR = iaddress; + + // Write first byte to send + TWI_WriteByte(pTwi, byte); +} + +//----------------------------------------------------------------------------- +/// Returns 1 if a byte has been received and can be read on the given TWI +/// peripheral; otherwise, returns 0. This function resets the status register +/// of the TWI. +/// \param pTwi Pointer to an AT91S_TWI instance. +//----------------------------------------------------------------------------- +unsigned char TWI_ByteReceived(AT91S_TWI *pTwi) +{ + return ((pTwi->TWI_SR & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY); +} + +//----------------------------------------------------------------------------- +/// Returns 1 if a byte has been sent, so another one can be stored for +/// transmission; otherwise returns 0. This function clears the status register +/// of the TWI. +/// \param pTwi Pointer to an AT91S_TWI instance. +//----------------------------------------------------------------------------- +unsigned char TWI_ByteSent(AT91S_TWI *pTwi) +{ + return ((pTwi->TWI_SR & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY); +} + +//----------------------------------------------------------------------------- +/// Returns 1 if the current transmission is complete (the STOP has been sent); +/// otherwise returns 0. +/// \param pTwi Pointer to an AT91S_TWI instance. +//----------------------------------------------------------------------------- +unsigned char TWI_TransferComplete(AT91S_TWI *pTwi) +{ + return ((pTwi->TWI_SR & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP); +} + +//----------------------------------------------------------------------------- +/// Enables the selected interrupts sources on a TWI peripheral. +/// \param pTwi Pointer to an AT91S_TWI instance. +/// \param sources Bitwise OR of selected interrupt sources. +//----------------------------------------------------------------------------- +void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources) +{ + SANITY_CHECK(pTwi); + SANITY_CHECK((sources & 0xFFFFFEF8) == 0); + + pTwi->TWI_IER = sources; +} + +//----------------------------------------------------------------------------- +/// Disables the selected interrupts sources on a TWI peripheral. +/// \param pTwi Pointer to an AT91S_TWI instance. +/// \param sources Bitwise OR of selected interrupt sources. +//----------------------------------------------------------------------------- +void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources) +{ + SANITY_CHECK(pTwi); + SANITY_CHECK((sources & 0xFFFFFEF8) == 0); + + pTwi->TWI_IDR = sources; +} + +//----------------------------------------------------------------------------- +/// Returns the current status register of the given TWI peripheral. This +/// resets the internal value of the status register, so further read may yield +/// different values. +/// \param pTwi Pointer to an AT91S_TWI instance. +//----------------------------------------------------------------------------- +unsigned int TWI_GetStatus(AT91S_TWI *pTwi) +{ + SANITY_CHECK(pTwi); + + return pTwi->TWI_SR; +} + +//----------------------------------------------------------------------------- +/// Returns the current status register of the given TWI peripheral, but +/// masking interrupt sources which are not currently enabled. +/// This resets the internal value of the status register, so further read may +/// yield different values. +/// \param pTwi Pointer to an AT91S_TWI instance. +//----------------------------------------------------------------------------- +unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi) +{ + unsigned int status; + + SANITY_CHECK(pTwi); + + status = pTwi->TWI_SR; + status &= pTwi->TWI_IMR; + + return status; +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/twi/twi.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/twi/twi.h new file mode 100644 index 0000000..401126e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/twi/twi.h @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef TWI_H +#define TWI_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Global definitions +//------------------------------------------------------------------------------ + +// Missing AT91C_TWI_TXRDY definition. +#ifndef AT91C_TWI_TXRDY + #define AT91C_TWI_TXRDY AT91C_TWI_TXRDY_MASTER +#endif + +// Missing AT91C_TWI_TXCOMP definition. +#ifndef AT91C_TWI_TXCOMP + #define AT91C_TWI_TXCOMP AT91C_TWI_TXCOMP_MASTER +#endif + +//------------------------------------------------------------------------------ +// Global macros +//------------------------------------------------------------------------------ + +/// Returns 1 if the TXRDY bit (ready to transmit data) is set in the given +/// status register value. +#define TWI_STATUS_TXRDY(status) ((status & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY) + +/// Returns 1 if the RXRDY bit (ready to receive data) is set in the given +/// status register value. +#define TWI_STATUS_RXRDY(status) ((status & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY) + +/// Returns 1 if the TXCOMP bit (transfer complete) is set in the given +/// status register value. +#define TWI_STATUS_TXCOMP(status) ((status & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP) + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void TWI_Configure(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck); + +extern void TWI_Stop(AT91S_TWI *pTwi); + +extern void TWI_StartRead( + AT91S_TWI *pTwi, + unsigned char address, + unsigned int iaddress, + unsigned char isize); + +extern unsigned char TWI_ReadByte(AT91S_TWI *pTwi); + +extern void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte); + +extern void TWI_StartWrite( + AT91S_TWI *pTwi, + unsigned char address, + unsigned int iaddress, + unsigned char isize, + unsigned char byte); + +extern unsigned char TWI_ByteReceived(AT91S_TWI *pTwi); + +extern unsigned char TWI_ByteSent(AT91S_TWI *pTwi); + +extern unsigned char TWI_TransferComplete(AT91S_TWI *pTwi); + +extern void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources); + +extern void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources); + +extern unsigned int TWI_GetStatus(AT91S_TWI *pTwi); + +extern unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi); + +#endif //#ifndef TWI_H diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/usart/usart.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/usart/usart.c new file mode 100644 index 0000000..35e08e0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/usart/usart.c @@ -0,0 +1,259 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "usart.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Configures an USART peripheral with the specified parameters. +/// \param usart Pointer to the USART peripheral to configure. +/// \param mode Desired value for the USART mode register (see the datasheet). +/// \param baudrate Baudrate at which the USART should operate (in Hz). +/// \param masterClock Frequency of the system master clock (in Hz). +//------------------------------------------------------------------------------ +void USART_Configure(AT91S_USART *usart, + unsigned int mode, + unsigned int baudrate, + unsigned int masterClock) +{ + // Reset and disable receiver & transmitter + usart->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX + | AT91C_US_RXDIS | AT91C_US_TXDIS; + + // Configure mode + usart->US_MR = mode; + + // Configure baudrate + // Asynchronous, no oversampling + if (((mode & AT91C_US_SYNC) == 0) + && ((mode & AT91C_US_OVER) == 0)) { + + usart->US_BRGR = (masterClock / baudrate) / 16; + } + // TODO other modes +} + +//------------------------------------------------------------------------------ +/// Enables or disables the transmitter of an USART peripheral. +/// \param usart Pointer to an USART peripheral +/// \param enabled If true, the transmitter is enabled; otherwise it is +/// disabled. +//------------------------------------------------------------------------------ +void USART_SetTransmitterEnabled(AT91S_USART *usart, + unsigned char enabled) +{ + if (enabled) { + + usart->US_CR = AT91C_US_TXEN; + } + else { + + usart->US_CR = AT91C_US_TXDIS; + } +} + +//------------------------------------------------------------------------------ +/// Enables or disables the receiver of an USART peripheral +/// \param usart Pointer to an USART peripheral +/// \param enabled If true, the receiver is enabled; otherwise it is disabled. +//------------------------------------------------------------------------------ +void USART_SetReceiverEnabled(AT91S_USART *usart, + unsigned char enabled) +{ + if (enabled) { + + usart->US_CR = AT91C_US_RXEN; + } + else { + + usart->US_CR = AT91C_US_RXDIS; + } +} + +//------------------------------------------------------------------------------ +/// Sends one packet of data through the specified USART peripheral. This +/// function operates synchronously, so it only returns when the data has been +/// actually sent. +/// \param usart Pointer to an USART peripheral. +/// \param data Data to send including 9nth bit and sync field if necessary (in +/// the same format as the US_THR register in the datasheet). +/// \param timeOut Time out value (0 = no timeout). +//------------------------------------------------------------------------------ +void USART_Write( + AT91S_USART *usart, + unsigned short data, + volatile unsigned int timeOut) +{ + if (timeOut == 0) { + + while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0); + } + else { + + while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0) { + + if (timeOut == 0) { + + trace_LOG(trace_ERROR, "-E- USART_Write: Timed out.\n\r"); + return; + } + timeOut--; + } + } + + usart->US_THR = data; +} + +//------------------------------------------------------------------------------ +/// Sends the contents of a data buffer through the specified USART peripheral. +/// This function returns immediately (1 if the buffer has been queued, 0 +/// otherwise); poll the ENDTX and TXBUFE bits of the USART status register +/// to check for the transfer completion. +/// \param usart Pointer to an USART peripheral. +/// \param buffer Pointer to the data buffer to send. +/// \param size Size of the data buffer (in bytes). +//------------------------------------------------------------------------------ +unsigned char USART_WriteBuffer( + AT91S_USART *usart, + void *buffer, + unsigned int size) +{ + // Check if the first PDC bank is free + if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) { + + usart->US_TPR = (unsigned int) buffer; + usart->US_TCR = size; + usart->US_PTCR = AT91C_PDC_TXTEN; + + return 1; + } + // Check if the second PDC bank is free + else if (usart->US_TNCR == 0) { + + usart->US_TNPR = (unsigned int) buffer; + usart->US_TNCR = size; + + return 1; + } + else { + + return 0; + } +} + +//------------------------------------------------------------------------------ +/// Reads and return a packet of data on the specified USART peripheral. This +/// function operates asynchronously, so it waits until some data has been +/// received. +/// \param usart Pointer to an USART peripheral. +/// \param timeOut Time out value (0 -> no timeout). +//------------------------------------------------------------------------------ +unsigned short USART_Read( + AT91S_USART *usart, + volatile unsigned int timeOut) +{ + if (timeOut == 0) { + + while ((usart->US_CSR & AT91C_US_RXRDY) == 0); + } + else { + + while ((usart->US_CSR & AT91C_US_RXRDY) == 0) { + + if (timeOut == 0) { + + trace_LOG(trace_ERROR, "-E- USART_Read: Timed out.\n\r"); + return 0; + } + timeOut--; + } + } + + return usart->US_RHR; +} + +//------------------------------------------------------------------------------ +/// Reads data from an USART peripheral, filling the provided buffer until it +/// becomes full. This function returns immediately with 1 if the buffer has +/// been queued for transmission; otherwise 0. +/// \param usart Pointer to an USART peripheral. +/// \param buffer Pointer to the buffer where the received data will be stored. +/// \param size Size of the data buffer (in bytes). +//------------------------------------------------------------------------------ +unsigned char USART_ReadBuffer(AT91S_USART *usart, + void *buffer, + unsigned int size) +{ + // Check if the first PDC bank is free + if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) { + + usart->US_RPR = (unsigned int) buffer; + usart->US_RCR = size; + usart->US_PTCR = AT91C_PDC_RXTEN; + + return 1; + } + // Check if the second PDC bank is free + else if (usart->US_RNCR == 0) { + + usart->US_RNPR = (unsigned int) buffer; + usart->US_RNCR = size; + + return 1; + } + else { + + return 0; + } +} + +//------------------------------------------------------------------------------ +/// Returns 1 if some data has been received and can be read from an USART; +/// otherwise returns 0. +/// \param usart Pointer to an AT91S_USART instance. +//------------------------------------------------------------------------------ +unsigned char USART_IsDataAvailable(AT91S_USART *usart) +{ + if ((usart->US_CSR & AT91C_US_RXRDY) != 0) { + + return 1; + } + else { + + return 0; + } +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/usart/usart.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/usart/usart.h new file mode 100644 index 0000000..3150ec0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/peripherals/usart/usart.h @@ -0,0 +1,112 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// This module provides several definitions and methods for using an USART +/// peripheral. +/// +/// !Usage +/// -# Enable the USART peripheral clock in the PMC. +/// -# Enable the required USART PIOs (see pio.h). +/// -# Configure the UART by calling USART_Configure. +/// -# Enable the transmitter and/or the receiver of the USART using +/// USART_SetTransmitterEnabled and USART_SetReceiverEnabled. +/// -# Send data through the USART using the USART_Write and +/// USART_WriteBuffer methods. +/// -# Receive data from the USART using the USART_Read and +/// USART_ReadBuffer functions; the availability of data can be polled +/// with USART_IsDataAvailable. +/// -# Disable the transmitter and/or the receiver of the USART with +/// USART_SetTransmitterEnabled and USART_SetReceiverEnabled. +//------------------------------------------------------------------------------ + +#ifndef USART_H +#define USART_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USART modes" +/// This page lists several common operating modes for an USART peripheral. +/// +/// !Modes +/// - USART_MODE_ASYNCHRONOUS + +/// Basic asynchronous mode, i.e. 8 bits no parity. +#define USART_MODE_ASYNCHRONOUS (AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USART_Configure( + AT91S_USART *usart, + unsigned int mode, + unsigned int baudrate, + unsigned int masterClock); + +extern void USART_SetTransmitterEnabled(AT91S_USART *usart, unsigned char enabled); + +extern void USART_SetReceiverEnabled(AT91S_USART *usart, unsigned char enabled); + +extern void USART_Write( + AT91S_USART *usart, + unsigned short data, + volatile unsigned int timeOut); + +extern unsigned char USART_WriteBuffer( + AT91S_USART *usart, + void *buffer, + unsigned int size); + +extern unsigned short USART_Read( + AT91S_USART *usart, + volatile unsigned int timeOut); + +extern unsigned char USART_ReadBuffer( + AT91S_USART *usart, + void *buffer, + unsigned int size); + +extern unsigned char USART_IsDataAvailable(AT91S_USART *usart); + +#endif //#ifndef USART_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/assert.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/assert.h new file mode 100644 index 0000000..bb491e2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/assert.h @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: Assert + + About: Purpose + Definition of the ASSERT() macro, which is used for runtime condition + verifying. + + About: Usage + 1 - Use in your code to check the value of function parameters, + return values, etc. *Warning:* the ASSERT condition must not have + any side-effect; otherwise, the program may not work properly + anymore when assertions are disabled. + 2 - Use SANITY_CHECK to perform checks with a default error message + (outputs the file and line number where the error occured). This + reduces memory overhead caused by assertion error strings. + 3 - Initialize the to see failed assertions at run-time. + 4 - Disable assertions by defining the NOASSERT symbol at compilation + time. +*/ + +#ifndef ASSERT_H +#define ASSERT_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ +/* + Macro: ASSERT + Check that the given condition is true, otherwise displays an error + message and stops the program execution. + + Parameters: + condition - Condition to verify. + string - Formatted string to output if the condition fails. + ... - Additional arguments depending on the formatted string. +*/ +#if !defined(NOASSERT) && !defined(NOTRACE) + + //char sanityError[] = "Sanity check failed at %s:%d\n\r"; + + #define ASSERT(condition, ...) { \ + if (!(condition)) { \ + printf(__VA_ARGS__); \ + while (1); \ + } \ + } + #define SANITY_ERROR "Sanity check failed at %s:%d\n\r" + #define SANITY_CHECK(condition) ASSERT(condition, SANITY_ERROR, __FILE__, __LINE__) +#else + #define ASSERT(...) + #define SANITY_CHECK(...) +#endif + +#endif //#ifndef ASSERT_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/led.c b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/led.c new file mode 100644 index 0000000..71af371 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/led.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: LED implementation + + About: Purpose + Implementation of LED-related functionalities. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "led.h" +#include +#include + +//------------------------------------------------------------------------------ +// Internal variables +//------------------------------------------------------------------------------ + +#ifdef PINS_LEDS +static const Pin pinsLeds[] = {PINS_LEDS}; +static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds); +#endif + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +/* + Function: LED_Configure + Configures the pin associated with the given LED number. + + Parameters: + led - Number of the LED to configure. + + Returns: + 1 if the LED exists and has been configured; otherwise 0. +*/ +unsigned char LED_Configure(unsigned int led) +{ +#ifdef PINS_LEDS + // Check that LED exists + if (led >= numLeds) { + + return 0; + } + + // Configure LED + return (PIO_Configure(&pinsLeds[led], 1)); +#else + return 0; +#endif +} + +/* + Function: LED_Set + Turns a LED on. + + Parameters: + led - Number of the LED to turn on. + + Returns: + 1 if the LED has been turned on; 0 otherwise. +*/ +unsigned char LED_Set(unsigned int led) +{ +#ifdef PINS_LEDS + // Check if LED exists + if (led >= numLeds) { + + return 0; + } + + // Turn LED on + if (pinsLeds[led].type == PIO_OUTPUT_0) { + + PIO_Set(&pinsLeds[led]); + } + else { + + PIO_Clear(&pinsLeds[led]); + } + + return 1; +#else + return 0; +#endif +} + +/* + Function: LED_Clear + Turns a LED off. + + Parameters: + led - Number of the LED to turn off. + + Returns: + 1 if the LED has been turned off; 0 otherwise. +*/ +unsigned char LED_Clear(unsigned int led) +{ +#ifdef PINS_LEDS + // Check if LED exists + if (led >= numLeds) { + + return 0; + } + + // Turn LED off + if (pinsLeds[led].type == PIO_OUTPUT_0) { + + PIO_Clear(&pinsLeds[led]); + } + else { + + PIO_Set(&pinsLeds[led]); + } + + return 1; +#else + return 0; +#endif +} + +/* + Function: LED_Toggle + Toggles the current state of a LED. + + Parameters: + led - Number of the LED to toggle. + + Returns: + 1 if the LED has been toggled; otherwise 0. +*/ +unsigned char LED_Toggle(unsigned int led) +{ +#ifdef PINS_LEDS + // Check if LED exists + if (led >= numLeds) { + + return 0; + } + + // Toggle LED + if (PIO_GetOutputDataStatus(&pinsLeds[led])) { + + PIO_Clear(&pinsLeds[led]); + } + else { + + PIO_Set(&pinsLeds[led]); + } + + return 1; +#else + return 0; +#endif +} + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/led.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/led.h new file mode 100644 index 0000000..2e44a9f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/led.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: LED + + About: Purpose + Small set of functions for simple and portable LED usage. + + About: Usage + 1 - Configure one or more LEDs using and + . + 2 - Set, clear and toggle LEDs using , and + . + 3 - Get the current status of a LED using . + + LEDs are numbered starting from 0; the number of LEDs depend on the + board being used. All the functions defined here will compile properly + regardless of whether the LED is defined or not; they will simply + return 0 when a LED which does not exist is given as an argument. + Also, these functions take into account how each LED is connected on to + board; thus, might change the level on the corresponding pin + to 0 or 1, but it will always light the LED on; same thing for the other + methods. +*/ + +#ifndef LED_H +#define LED_H + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char LED_Configure(unsigned int led); +extern unsigned char LED_Set(unsigned int led); +extern unsigned char LED_Clear(unsigned int led); +extern unsigned char LED_Toggle(unsigned int led); + +#endif //#ifndef LED_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/trace.h b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/trace.h new file mode 100644 index 0000000..10f9bd7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/Atmel/at91lib/utility/trace.h @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: Trace + + About: Purpose + Standard output methods for reporting debug information, warnings and + errors, which can be turned on/off. + + About: Usage + 1 - Initialize the DBGU using . + 2 - Uses the macro to output traces throughout the program. + 3 - Turn off all traces by defining the NOTRACE symbol during + compilation. + 4 - Disable a group of trace by changing the value of + during compilation; traces with a level below are not + generated. +*/ + +#ifndef TRACE_H +#define TRACE_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#if !defined(NOTRACE) + #include + #include + #include + #include +#endif + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ +/* + Constants: Trace levels + trace_FATAL - Indicates a major error which prevents the program from + going any further. + trace_ERROR - Indicates an error which may not stop the program + execution, but which indicates there is a problem with the code. + trace_WARNING - Indicates that a minor error has happened. In most case + it can be discarded safely; it may even be expected. + trace_INFO - Informational trace about the program execution. Should + enable the user to see the execution flow. + trace_DEBUG - Traces whose only purpose is for debugging the program, + and which do not produce meaningful information otherwise. +*/ +#define trace_DEBUG 0 +#define trace_INFO 1 +#define trace_WARNING 2 +#define trace_ERROR 3 +#define trace_FATAL 4 + +/* + Constant: trace_LEVEL + Minimum level of traces that are output. By default, all traces are + output; change the value of this symbol during compilation for a more + restrictive behavior. +*/ +#if !defined(trace_LEVEL) + #define trace_LEVEL 0 +#endif + +/* + Macro: trace_CONFIGURE + Initializes the DBGU unless the NOTRACE symbol has been defined. + + Parameters: + mode - DBGU mode. + baudrate - DBGU baudrate. + mck - Master clock frequency. +*/ +#if !defined(NOTRACE) + #define trace_CONFIGURE(mode, baudrate, mck) { \ + const Pin pinsDbgu[] = {PINS_DBGU}; \ + PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \ + DBGU_Configure(mode, baudrate, mck); \ + } +#else + #define trace_CONFIGURE(...) +#endif + +/* + Macro: trace_LOG + Outputs a formatted string using if the log level is high + enough. Can be disabled by defining the NOTRACE symbol during + compilation. + + Parameters: + level - Trace level (see ). + format - Formatted string to output. + ... - Additional parameters, depending on the formatted string. +*/ +#if !defined(NOTRACE) + #define trace_LOG(level, ...) { \ + if (level >= trace_LEVEL) { \ + printf(__VA_ARGS__); \ + } \ + } +#else + #define trace_LOG(...) +#endif + +#endif //#ifndef TRACE_H + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/EULA.txt b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/EULA.txt new file mode 100644 index 0000000..e5b3790 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/EULA.txt @@ -0,0 +1,145 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +In summary, this license agreement allows you to use this software only on +Luminary Micro microcontrollers, on an as-is basis, with no warranties. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + +This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the Software, +you are agreeing to be bound by the terms of this Agreement. If you do not +agree to all of the terms of this Agreement, do not download the Software. If +you change your mind later, stop using the Software and delete all copies of +the Software in your possession or control. Any copies of the Software that you +have already distributed, where permitted, and do not destroy will continue to +be governed by this Agreement. Your prior use will also continue to be governed +by this Agreement. + +1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive, +non-transferable rights solely and exclusively on or for LMI's microcontroller +products: (1) to use and reproduce the Software, (2) to prepare derivative +works of the Software, (3) to distribute the Software and derivative works +thereof in source (human-readable) form and object (machine-readable) form, (4) +to sublicense to others the right to use the distributed Software, (5) permit +the Software and derivative works thereof to communicate with "viral open +source" software (as defined below); provided however that you may not combine +the two separate and independent works to form a larger program, and (6) +combine the Software and derivative works thereof with "non-viral open source" +software (as defined below). For the purposes of this Agreement, "viral open +source" software means open source software made available on license terms, +such as the GNU General Public License (GPL), that would alter the foregoing +license grant restrictions if combined with the Software. For the purposes of +this Agreement, "non-viral open source" software means open source software +made available on license terms that would not alter the foregoing license +grant restrictions if combined with the Software. For the avoidance of any +doubt, the foregoing license grant does not permit you to combine the Software +and derivative works thereof with "viral open-source" software in order to +sublicense to others the right to use the combined software product. If you +violate any of the terms or restrictions of this Agreement, LMI may immediately +terminate this Agreement, and require that you stop using and delete all copies +of the Software in your possession or control. + +2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the Software, +and United States copyright laws and international treaty provisions protect +the Software. Therefore, you must treat the Software like any other copyrighted +material (e.g. a book or musical recording). You may not use or copy the +Software for any other purpose than what is described in this Agreement. Except +as expressly provided herein, LMI does not grant to you any express or implied +rights under any LMI or third-party patents, copyrights, trademarks, or trade +secrets. Additionally, you must reproduce and apply any copyright or other +proprietary rights notices included on or embedded in the Software to any +copies or derivative works made thereof, in whole or in part, if any. + +3. SUPPORT. LMI is NOT obligated to provide any support, upgrades or new +releases of the Software. If you wish, you may contact LMI and report problems +and provide suggestions regarding the Software. LMI has no obligation +whatsoever to respond in any way to such a problem report or suggestion. LMI +may make changes to the Software at any time, without any obligation to notify +or provide updated versions of the Software to you. + +4. INDEMNITY. You agree to fully defend and indemnify LMI from any and all +claims, liabilities, and costs (including reasonable attorney's fees) related +to (1) your use (including your sub-licensee's use, if permitted) of the +Software or (2) your violation of the terms and conditions of this Agreement. + +5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault +tolerant and is not designed, manufactured or intended by LMI for incorporation +into products intended for use or resale in on-line control equipment in +hazardous, dangerous to life or potentially life-threatening environments +requiring fail-safe performance, such as in the operation of nuclear +facilities, aircraft navigation or communication systems, air traffic control, +direct life support machines or weapons systems, in which the failure of +products could lead directly to death, personal injury or severe physical or +environmental damage ("High Risk Activities"). You specifically represent and +warrant that you will not use the Software or any derivative work of the +Software for High Risk Activities. + +6. PRODUCT LABELING. You are not authorized to use any LMI trademarks, brand +names, or logos. + +7. COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must use the Software in +accordance with all applicable U.S. laws, regulations and statutes. You agree +that neither you nor your licensees (if any) intend to or will, directly or +indirectly, export or transmit the Software to any country in violation of U.S. +export restrictions. + +8. GOVERNMENT USE. Use of the Software and any corresponding documentation, if +any, is provided with RESTRICTED RIGHTS. Use, duplication or disclosure by the +Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) +of The Rights in Technical Data and Computer Software clause at DFARS +252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial Computer +Software--Restricted Rights at 48 CFR 52.227-19, as applicable. Manufacturer is +Luminary Micro, Inc., 108 Wild Basin Road, Ste 350, Austin, Texas 78746. + +9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI +EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED "AS +IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, +WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING OUT +OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING THE +SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A WARRANTY OR +REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK DEVELOPED WITH +OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF THE +INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES. + +10. LIMITATION OF LIABILITY. IN NO EVENT WILL LMI BE LIABLE, WHETHER IN +CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, +CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR +ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, +SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. + +11. CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and laws of +the United States and the State of Texas, USA, without regard to conflicts of +laws principles, will apply to all matters relating to this Agreement or the +Software, and you agree that any litigation will be subject to the exclusive +jurisdiction of the state or federal courts in Austin, Travis County, Texas, +USA. You agree that regardless of any statute or law to the contrary, any claim +or cause of action arising out of or related to this Agreement or the Software +must be filed within one (1) year after such claim or cause of action arose or +be forever barred. YOU EXPRESSLY AGREE THAT YOU WAIVE YOUR INDIVIDUAL RIGHT TO +A TRIAL BY JURY IN ANY COURT OF COMPETENT JURISDICTION FOR ANY ACTION, DISPUTE, +CLAIM, OR CONTROVERSY CONCERNING THIS AGREEMENT OR FOR ANY ACTION, DISPUTE, +CLAIM, OR CONTROVERSY ARISING OUT OF OR RELATING TO ANY INTERPRETATION, +CONSTRUCTION, PERFORMANCE OR BREACH OF THIS AGREEMENT. + +12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement between +you and LMI regarding the subject matter of this Agreement, and supersedes all +prior communications, negotiations, understandings, agreements or +representations, either written or oral, if any. This Agreement may only be +amended in written form, executed by you and LMI. + +13. SEVERABILITY. If any provision of this Agreement is held for any reason to +be invalid or unenforceable, then the remaining provisions of this Agreement +will be unimpaired and, unless a modification or replacement of the invalid or +unenforceable provision is further held to deprive you or LMI of a material +benefit, in which case the Agreement will immediately terminate, the invalid or +unenforceable provision will be replaced with a provision that is valid and +enforceable and that comes closest to the intention underlying the invalid or +unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/IAR/driverlib.a b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/IAR/driverlib.a new file mode 100644 index 0000000..b64d7bb Binary files /dev/null and b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/IAR/driverlib.a differ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/IAR/grlib.a b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/IAR/grlib.a new file mode 100644 index 0000000..b6eb559 Binary files /dev/null and b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/IAR/grlib.a differ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Keil/driverlib.lib b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Keil/driverlib.lib new file mode 100644 index 0000000..29bdec8 Binary files /dev/null and b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Keil/driverlib.lib differ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Keil/grlib.lib b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Keil/grlib.lib new file mode 100644 index 0000000..2d07866 Binary files /dev/null and b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Keil/grlib.lib differ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Rowley/libdriver.a b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Rowley/libdriver.a new file mode 100644 index 0000000..bb089ef Binary files /dev/null and b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Rowley/libdriver.a differ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Rowley/libgr.a b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Rowley/libgr.a new file mode 100644 index 0000000..a402ccf Binary files /dev/null and b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/Rowley/libgr.a differ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/adc.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/adc.h new file mode 100644 index 0000000..2eec710 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/adc.h @@ -0,0 +1,142 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceOverflowClear(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceUnderflowClear(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); +extern void ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libdriver.a b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libdriver.a new file mode 100644 index 0000000..5aab524 Binary files /dev/null and b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libdriver.a differ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libgr.a b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libgr.a new file mode 100644 index 0000000..4712250 Binary files /dev/null and b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libgr.a differ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/can.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/can.h new file mode 100644 index 0000000..b6c99b3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/can.h @@ -0,0 +1,453 @@ +//***************************************************************************** +// +// can.h - Defines and Macros for the CAN controller. +// +// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __CAN_H__ +#define __CAN_H__ + +//***************************************************************************** +// +//! \addtogroup can_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** + +//***************************************************************************** +// +//! These are the flags used by the tCANMsgObject variable when calling the +//! CANMessageSet() and CANMessageGet() functions. +// +//***************************************************************************** +typedef enum +{ + // + //! This indicates that transmit interrupts should be enabled, or are + //! enabled. + // + MSG_OBJ_TX_INT_ENABLE = 0x00000001, + + // + //! This indicates that receive interrupts should be enabled, or are + //! enabled. + // + MSG_OBJ_RX_INT_ENABLE = 0x00000002, + + // + //! This indicates that a message object will use or is using an extended + //! identifier. + // + MSG_OBJ_EXTENDED_ID = 0x00000004, + + // + //! This indicates that a message object will use or is using filtering + //! based on the object's message identifier. + // + MSG_OBJ_USE_ID_FILTER = 0x00000008, + + // + //! This indicates that new data was available in the message object. + // + MSG_OBJ_NEW_DATA = 0x00000080, + + // + //! This indicates that data was lost since this message object was last + //! read. + // + MSG_OBJ_DATA_LOST = 0x00000100, + + // + //! This indicates that a message object will use or is using filtering + //! based on the direction of the transfer. If the direction filtering is + //! used, then ID filtering must also be enabled. + // + MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER), + + // + //! This indicates that a message object will use or is using message + //! identifier filtering based on the extended identifier. If the extended + //! identifier filtering is used, then ID filtering must also be enabled. + // + MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER), + + // + //! This indicates that a message object is a remote frame. + // + MSG_OBJ_REMOTE_FRAME = 0x00000040, + + // + //! This indicates that a message object has no flags set. + // + MSG_OBJ_NO_FLAGS = 0x00000000 +} +tCANObjFlags; + +//***************************************************************************** +// +//! This define is used with the #tCANObjFlags enumerated values to allow +//! checking only status flags and not configuration flags. +// +//***************************************************************************** +#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) + +//***************************************************************************** +// +//! The structure used for encapsulating all the items associated with a CAN +//! message object in the CAN controller. +// +//***************************************************************************** +typedef struct +{ + // + //! The CAN message identifier used for 11 or 29 bit identifiers. + // + unsigned long ulMsgID; + + // + //! The message identifier mask used when identifier filtering is enabled. + // + unsigned long ulMsgIDMask; + + // + //! This value holds various status flags and settings specified by + //! tCANObjFlags. + // + unsigned long ulFlags; + + // + //! This value is the number of bytes of data in the message object. + // + unsigned long ulMsgLen; + + // + //! This is a pointer to the message object's data. + // + unsigned char *pucMsgData; +} +tCANMsgObject; + +//***************************************************************************** +// +//! This structure is used for encapsulating the values associated with setting +//! up the bit timing for a CAN controller. The structure is used when calling +//! the CANGetBitTiming and CANSetBitTiming functions. +// +//***************************************************************************** +typedef struct +{ + // + //! This value holds the sum of the Synchronization, Propagation, and Phase + //! Buffer 1 segments, measured in time quanta. The valid values for this + //! setting range from 2 to 16. + // + unsigned int uSyncPropPhase1Seg; + + // + //! This value holds the Phase Buffer 2 segment in time quanta. The valid + //! values for this setting range from 1 to 8. + // + unsigned int uPhase2Seg; + + // + //! This value holds the Resynchronization Jump Width in time quanta. The + //! valid values for this setting range from 1 to 4. + // + unsigned int uSJW; + + // + //! This value holds the CAN_CLK divider used to determine time quanta. + //! The valid values for this setting range from 1 to 1023. + // + unsigned int uQuantumPrescaler; + +} +tCANBitClkParms; + +//***************************************************************************** +// +//! This data type is used to identify the interrupt status register. This is +//! used when calling the CANIntStatus() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the CAN interrupt status information. + // + CAN_INT_STS_CAUSE, + + // + //! Read a message object's interrupt status. + // + CAN_INT_STS_OBJECT +} +tCANIntStsReg; + +//***************************************************************************** +// +//! This data type is used to identify which of several status registers to +//! read when calling the CANStatusGet() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the full CAN controller status. + // + CAN_STS_CONTROL, + + // + //! Read the full 32-bit mask of message objects with a transmit request + //! set. + // + CAN_STS_TXREQUEST, + + // + //! Read the full 32-bit mask of message objects with new data available. + // + CAN_STS_NEWDAT, + + // + //! Read the full 32-bit mask of message objects that are enabled. + // + CAN_STS_MSGVAL +} +tCANStsReg; + +//***************************************************************************** +// +//! These definitions are used to specify interrupt sources to CANIntEnable() +//! and CANIntDisable(). +// +//***************************************************************************** +typedef enum +{ + // + //! This flag is used to allow a CAN controller to generate error + //! interrupts. + // + CAN_INT_ERROR = 0x00000008, + + // + //! This flag is used to allow a CAN controller to generate status + //! interrupts. + // + CAN_INT_STATUS = 0x00000004, + + // + //! This flag is used to allow a CAN controller to generate any CAN + //! interrupts. If this is not set, then no interrupts will be generated + //! by the CAN controller. + // + CAN_INT_MASTER = 0x00000002 +} +tCANIntFlags; + +//***************************************************************************** +// +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CANMessageSet() API. +// +//***************************************************************************** +typedef enum +{ + // + //! Transmit message object. + // + MSG_OBJ_TYPE_TX, + + // + //! Transmit remote request message object + // + MSG_OBJ_TYPE_TX_REMOTE, + + // + //! Receive message object. + // + MSG_OBJ_TYPE_RX, + + // + //! Receive remote request message object. + // + MSG_OBJ_TYPE_RX_REMOTE, + + // + //! Remote frame receive remote, with auto-transmit message object. + // + MSG_OBJ_TYPE_RXTX_REMOTE +} +tMsgObjType; + +//***************************************************************************** +// +//! The following enumeration contains all error or status indicators that can +//! be returned when calling the CANStatusGet() function. +// +//***************************************************************************** +typedef enum +{ + // + //! CAN controller has entered a Bus Off state. + // + CAN_STATUS_BUS_OFF = 0x00000080, + + // + //! CAN controller error level has reached warning level. + // + CAN_STATUS_EWARN = 0x00000040, + + // + //! CAN controller error level has reached error passive level. + // + CAN_STATUS_EPASS = 0x00000020, + + // + //! A message was received successfully since the last read of this status. + // + CAN_STATUS_RXOK = 0x00000010, + + // + //! A message was transmitted successfully since the last read of this + //! status. + // + CAN_STATUS_TXOK = 0x00000008, + + // + //! This is the mask for the last error code field. + // + CAN_STATUS_LEC_MSK = 0x00000007, + + // + //! There was no error. + // + CAN_STATUS_LEC_NONE = 0x00000000, + + // + //! A bit stuffing error has occurred. + // + CAN_STATUS_LEC_STUFF = 0x00000001, + + // + //! A formatting error has occurred. + // + CAN_STATUS_LEC_FORM = 0x00000002, + + // + //! An acknowledge error has occurred. + // + CAN_STATUS_LEC_ACK = 0x00000003, + + // + //! The bus remained a bit level of 1 for longer than is allowed. + // + CAN_STATUS_LEC_BIT1 = 0x00000004, + + // + //! The bus remained a bit level of 0 for longer than is allowed. + // + CAN_STATUS_LEC_BIT0 = 0x00000005, + + // + //! A CRC error has occurred. + // + CAN_STATUS_LEC_CRC = 0x00000006, + + // + //! This is the mask for the CAN Last Error Code (LEC). + // + CAN_STATUS_LEC_MASK = 0x00000007 +} +tCANStatusCtrl; + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void CANInit(unsigned long ulBase); +extern void CANEnable(unsigned long ulBase); +extern void CANDisable(unsigned long ulBase); +extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); +extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); +extern unsigned long CANReadReg(unsigned long ulRegAddress); +extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue); +extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tMsgObjType eMsgType); +extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tBoolean bClrPendingInt); +extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg); +extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID); +extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void CANIntUnregister(unsigned long ulBase); +extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr); +extern unsigned long CANIntStatus(unsigned long ulBase, + tCANIntStsReg eIntStsReg); +extern tBoolean CANRetryGet(unsigned long ulBase); +extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry); +extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, + unsigned long *pulTxCount); +extern long CANGetIntNumber(unsigned long ulBase); +extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister, + int iSize); +extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister, + int iSize); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // __CAN_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/comp.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/comp.h new file mode 100644 index 0000000..144a7f2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/comp.h @@ -0,0 +1,134 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and combined together with values from the other +// groups via a logical OR. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#ifndef DEPRECATED +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#endif +#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/cpu.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/cpu.h new file mode 100644 index 0000000..e33baff --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/cpu.h @@ -0,0 +1,61 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern unsigned long CPUcpsid(void); +extern unsigned long CPUcpsie(void); +extern void CPUwfi(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/debug.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/debug.h new file mode 100644 index 0000000..e7acc85 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/debug.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/ethernet.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/ethernet.h new file mode 100644 index 0000000..f464e8c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/ethernet.h @@ -0,0 +1,173 @@ +//***************************************************************************** +// +// ethernet.h - Defines and Macros for the ethernet module. +// +// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ETHERNET_H__ +#define __ETHERNET_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to EthernetConfigSet as the ulConfig value, and +// returned from EthernetConfigGet. +// +//***************************************************************************** +#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP) +#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets +#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous +#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast +#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode +#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation +#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding + +//***************************************************************************** +// +// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and +// EthernetIntClear as the ulIntFlags parameter, and returned from +// EthernetIntStatus. +// +//***************************************************************************** +#define ETH_INT_PHY 0x040 // PHY Event/Interrupt +#define ETH_INT_MDIO 0x020 // Management Transaction +#define ETH_INT_RXER 0x010 // RX Error +#define ETH_INT_RXOF 0x008 // RX FIFO Overrun +#define ETH_INT_TX 0x004 // TX Complete +#define ETH_INT_TXER 0x002 // TX Error +#define ETH_INT_RX 0x001 // RX Complete + +//***************************************************************************** +// +// Helper Macros for Ethernet Processing +// +//***************************************************************************** +// +// htonl/ntohl - big endian/little endian byte swapping macros for +// 32-bit (long) values +// +//***************************************************************************** +#ifndef htonl + #define htonl(a) \ + ((((a) >> 24) & 0x000000ff) | \ + (((a) >> 8) & 0x0000ff00) | \ + (((a) << 8) & 0x00ff0000) | \ + (((a) << 24) & 0xff000000)) +#endif + +#ifndef ntohl + #define ntohl(a) htonl((a)) +#endif + +//***************************************************************************** +// +// htons/ntohs - big endian/little endian byte swapping macros for +// 16-bit (short) values +// +//***************************************************************************** +#ifndef htons + #define htons(a) \ + ((((a) >> 8) & 0x00ff) | \ + (((a) << 8) & 0xff00)) +#endif + +#ifndef ntohs + #define ntohs(a) htons((a)) +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk); +extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern unsigned long EthernetConfigGet(unsigned long ulBase); +extern void EthernetMACAddrSet(unsigned long ulBase, + unsigned char *pucMACAddr); +extern void EthernetMACAddrGet(unsigned long ulBase, + unsigned char *pucMACAddr); +extern void EthernetEnable(unsigned long ulBase); +extern void EthernetDisable(unsigned long ulBase); +extern tBoolean EthernetPacketAvail(unsigned long ulBase); +extern tBoolean EthernetSpaceAvail(unsigned long ulBase); +extern long EthernetPacketGetNonBlocking(unsigned long ulBase, + unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketPutNonBlocking(unsigned long ulBase, + unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen); +extern void EthernetIntRegister(unsigned long ulBase, + void (*pfnHandler)(void)); +extern void EthernetIntUnregister(unsigned long ulBase); +extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, + unsigned long ulData); +extern unsigned long EthernetPHYRead(unsigned long ulBase, + unsigned char ucRegAddr); + +//***************************************************************************** +// +// Several Ethernet APIs have been renamed, with the original function name +// being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define EthernetInit(a) \ + EthernetInitExpClk(a, SysCtlClockGet()) +#define EthernetPacketNonBlockingGet(a, b, c) \ + EthernetPacketGetNonBlocking(a, b, c) +#define EthernetPacketNonBlockingPut(a, b, c) \ + EthernetPacketPutNonBlocking(a, b, c) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ETHERNET_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/gpio.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/gpio.h new file mode 100644 index 0000000..9002d20 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/gpio.h @@ -0,0 +1,156 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfnIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort, + unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/grlib.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/grlib.h new file mode 100644 index 0000000..b404f1a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/grlib.h @@ -0,0 +1,1285 @@ +//***************************************************************************** +// +// grlib.h - Prototypes for the low level primitives provided by the graphics +// library. +// +// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Graphics Library. +// +//***************************************************************************** + +#ifndef __GRLIB_H__ +#define __GRLIB_H__ + +//***************************************************************************** +// +//! \addtogroup primitives_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! This structure defines the extents of a rectangle. All points greater than +//! or equal to the minimum and less than or equal to the maximum are part of +//! the rectangle. +// +//***************************************************************************** +typedef struct +{ + // + //! The minimum X coordinate of the rectangle. + // + short sXMin; + + // + //! The minimum Y coordinate of the rectangle. + // + short sYMin; + + // + //! The maximum X coordinate of the rectangle. + // + short sXMax; + + // + //! The maximum Y coordinate of the rectangle. + // + short sYMax; +} +tRectangle; + +//***************************************************************************** +// +//! This structure defines the characteristics of a display driver. +// +//***************************************************************************** +typedef struct +{ + // + //! The size of this structure. + // + long lSize; + + // + //! A pointer to display driver-specific data. + // + void *pvDisplayData; + + // + //! The width of this display. + // + unsigned short usWidth; + + // + //! The height of this display. + // + unsigned short usHeight; + + // + //! A pointer to the function to draw a pixel on this display. + // + void (*pfnPixelDraw)(void *pvDisplayData, long lX, long lY, + unsigned long ulValue); + + // + //! A pointer to the function to draw multiple pixels on this display. + // + void (*pfnPixelDrawMultiple)(void *pvDisplayData, long lX, long lY, + long lX0, long lCount, long lBPP, + const unsigned char *pucData, + const unsigned char *pucPalette); + + // + //! A pointer to the function to draw a horizontal line on this display. + // + void (*pfnLineDrawH)(void *pvDisplayData, long lX1, long lX2, long lY, + unsigned long ulValue); + + // + //! A pointer to the function to draw a vertical line on this display. + // + void (*pfnLineDrawV)(void *pvDisplayData, long lX, long lY1, long lY2, + unsigned long ulValue); + + // + //! A pointer to the function to draw a filled rectangle on this display. + // + void (*pfnRectFill)(void *pvDisplayData, const tRectangle *pRect, + unsigned long ulValue); + + // + //! A pointer to the function to translate 24-bit RGB colors to + //! display-specific colors. + // + unsigned long (*pfnColorTranslate)(void *pvDisplayData, + unsigned long ulValue); + + // + //! A pointer to the function to flush any cached drawing operations on + //! this display. + // + void (*pfnFlush)(void *pvDisplayData); +} +tDisplay; + +//***************************************************************************** +// +//! This structure describes a font used for drawing text onto the screen. +// +//***************************************************************************** +typedef struct +{ + // + //! The format of the font. Can be one of FONT_FMT_UNCOMPRESSED or + //! FONT_FMT_PIXEL_RLE. + // + unsigned char ucFormat; + + // + //! The maximum width of a character; this is the width of the widest + //! character in the font, though any individual character may be narrower + //! than this width. + // + unsigned char ucMaxWidth; + + // + //! The height of the character cell; this may be taller than the font data + //! for the characters (to provide inter-line spacing). + // + unsigned char ucHeight; + + // + //! The offset between the top of the character cell and the baseline of + //! the glyph. The baseline is the bottom row of a capital letter, below + //! which only the descenders of the lower case letters occur. + // + unsigned char ucBaseline; + + // + //! The offset within pucData to the data for each character in the font. + // + unsigned short pusOffset[96]; + + // + //! A pointer to the data for the font. + // + const unsigned char *pucData; +} +tFont; + +//***************************************************************************** +// +//! Indicates that the font data is stored in an uncompressed format. +// +//***************************************************************************** +#define FONT_FMT_UNCOMPRESSED 0x00 + +//***************************************************************************** +// +//! Indicates that the font data is stored using a pixel-based RLE format. +// +//***************************************************************************** +#define FONT_FMT_PIXEL_RLE 0x01 + +//***************************************************************************** +// +//! Indicates that the image data is not compressed and represents each pixel +//! with a single bit. +// +//***************************************************************************** +#define IMAGE_FMT_1BPP_UNCOMP 0x01 + +//***************************************************************************** +// +//! Indicates that the image data is not compressed and represents each pixel +//! with four bits. +// +//***************************************************************************** +#define IMAGE_FMT_4BPP_UNCOMP 0x04 + +//***************************************************************************** +// +//! Indicates that the image data is not compressed and represents each pixel +//! with eight bits. +// +//***************************************************************************** +#define IMAGE_FMT_8BPP_UNCOMP 0x08 + +//***************************************************************************** +// +//! Indicates that the image data is compressed and represents each pixel with +//! a single bit. +// +//***************************************************************************** +#define IMAGE_FMT_1BPP_COMP 0x81 + +//***************************************************************************** +// +//! Indicates that the image data is compressed and represents each pixel with +//! four bits. +// +//***************************************************************************** +#define IMAGE_FMT_4BPP_COMP 0x84 + +//***************************************************************************** +// +//! Indicates that the image data is compressed and represents each pixel with +//! eight bits. +// +//***************************************************************************** +#define IMAGE_FMT_8BPP_COMP 0x88 + +//***************************************************************************** +// +//! This structure defines a drawing context to be used to draw onto the +//! screen. Multiple drawing contexts may exist at any time. +// +//***************************************************************************** +typedef struct +{ + // + //! The size of this structure. + // + long lSize; + + // + //! The screen onto which drawing operations are performed. + // + const tDisplay *pDisplay; + + // + //! The clipping region to be used when drawing onto the screen. + // + tRectangle sClipRegion; + + // + //! The color used to draw primitives onto the screen. + // + unsigned long ulForeground; + + // + //! The background color used to draw primitives onto the screen. + // + unsigned long ulBackground; + + // + //! The font used to render text onto the screen. + // + const tFont *pFont; +} +tContext; + +//***************************************************************************** +// +//! Sets the background color to be used. +//! +//! \param pContext is a pointer to the drawing context to modify. +//! \param ulValue is the 24-bit RGB color to be used. +//! +//! This function sets the background color to be used for drawing operations +//! in the specified drawing context. +//! +//! \return None. +// +//***************************************************************************** +#define GrContextBackgroundSet(pContext, ulValue) \ + do \ + { \ + tContext *pC = pContext; \ + pC->ulBackground = DpyColorTranslate(pC->pDisplay, ulValue); \ + } \ + while(0) + +//***************************************************************************** +// +//! Sets the background color to be used. +//! +//! \param pContext is a pointer to the drawing context to modify. +//! \param ulValue is the display driver-specific color to be used. +//! +//! This function sets the background color to be used for drawing operations +//! in the specified drawing context, using a color that has been previously +//! translated to a driver-specific color (for example, via +//! DpyColorTranslate()). +//! +//! \return None. +// +//***************************************************************************** +#define GrContextBackgroundSetTranslated(pContext, ulValue) \ + do \ + { \ + tContext *pC = pContext; \ + pC->ulBackground = ulValue; \ + } \ + while(0) + +//***************************************************************************** +// +//! Gets the width of the display being used by this drawing context. +//! +//! \param pContext is a pointer to the drawing context to query. +//! +//! This function returns the width of the display that is being used by this +//! drawing context. +//! +//! \return Returns the width of the display in pixels. +// +//***************************************************************************** +#define GrContextDpyWidthGet(pContext) \ + (DpyWidthGet((pContext)->pDisplay)) + +//***************************************************************************** +// +//! Gets the height of the display being used by this drawing context. +//! +//! \param pContext is a pointer to the drawing context to query. +//! +//! This function returns the height of the display that is being used by this +//! drawing context. +//! +//! \return Returns the height of the display in pixels. +// +//***************************************************************************** +#define GrContextDpyHeightGet(pContext) \ + (DpyHeightGet((pContext)->pDisplay)) + +//***************************************************************************** +// +//! Sets the font to be used. +//! +//! \param pContext is a pointer to the drawing context to modify. +//! \param pFnt is a pointer to the font to be used. +//! +//! This function sets the font to be used for string drawing operations in the +//! specified drawing context. +//! +//! \return None. +// +//***************************************************************************** +#define GrContextFontSet(pContext, pFnt) \ + do \ + { \ + tContext *pC = pContext; \ + const tFont *pF = pFnt; \ + pC->pFont = pF; \ + } \ + while(0) + +//***************************************************************************** +// +//! Sets the foreground color to be used. +//! +//! \param pContext is a pointer to the drawing context to modify. +//! \param ulValue is the 24-bit RGB color to be used. +//! +//! This function sets the color to be used for drawing operations in the +//! specified drawing context. +//! +//! \return None. +// +//***************************************************************************** +#define GrContextForegroundSet(pContext, ulValue) \ + do \ + { \ + tContext *pC = pContext; \ + pC->ulForeground = DpyColorTranslate(pC->pDisplay, ulValue); \ + } \ + while(0) + +//***************************************************************************** +// +//! Sets the foreground color to be used. +//! +//! \param pContext is a pointer to the drawing context to modify. +//! \param ulValue is the display driver-specific color to be used. +//! +//! This function sets the foreground color to be used for drawing operations +//! in the specified drawing context, using a color that has been previously +//! translated to a driver-specific color (for example, via +//! DpyColorTranslate()). +//! +//! \return None. +// +//***************************************************************************** +#define GrContextForegroundSetTranslated(pContext, ulValue) \ + do \ + { \ + tContext *pC = pContext; \ + pC->ulForeground = ulValue; \ + } \ + while(0) + +//***************************************************************************** +// +//! Flushes any cached drawing operations. +//! +//! \param pContext is a pointer to the drawing context to use. +//! +//! This function flushes any cached drawing operations. For display drivers +//! that draw into a local frame buffer before writing to the actual display, +//! calling this function will cause the display to be updated to match the +//! contents of the local frame buffer. +//! +//! \return None. +// +//***************************************************************************** +#define GrFlush(pContext) \ + do \ + { \ + const tContext *pC = pContext; \ + DpyFlush(pC->pDisplay); \ + } \ + while(0) + +//***************************************************************************** +// +//! Gets the baseline of a font. +//! +//! \param pFont is a pointer to the font to query. +//! +//! This function determines the baseline position of a font. The baseline is +//! the offset between the top of the font and the bottom of the capital +//! letters. The only font data that exists below the baseline are the +//! descenders on some lower-case letters (such as ``y''). +//! +//! \return Returns the baseline of the font, in pixels. +// +//***************************************************************************** +#define GrFontBaselineGet(pFont) \ + ((pFont)->ucBaseline) + +//***************************************************************************** +// +//! Gets the height of a font. +//! +//! \param pFont is a pointer to the font to query. +//! +//! This function determines the height of a font. The height is the offset +//! between the top of the font and the bottom of the font, including any +//! ascenders and descenders. +//! +//! \return Returns the height of the font, in pixels. +// +//***************************************************************************** +#define GrFontHeightGet(pFont) \ + ((pFont)->ucHeight) + +//***************************************************************************** +// +//! Gets the maximum width of a font. +//! +//! \param pFont is a pointer to the font to query. +//! +//! This function determines the maximum width of a font. The maximum width is +//! the width of the widest individual character in the font. +//! +//! \return Returns the maximum width of the font, in pixels. +// +//***************************************************************************** +#define GrFontMaxWidthGet(pFont) \ + ((pFont)->ucMaxWidth) + +//***************************************************************************** +// +//! Gets the number of colors in an image. +//! +//! \param pucImage is a pointer to the image to query. +//! +//! This function determines the number of colors in the palette of an image. +//! This is only valid for 4bpp and 8bpp images; 1bpp images do not contain a +//! palette. +//! +//! \return Returns the number of colors in the image. +// +//***************************************************************************** +#define GrImageColorsGet(pucImage) \ + (((unsigned char *)pucImage)[5] + 1) + +//***************************************************************************** +// +//! Gets the height of an image. +//! +//! \param pucImage is a pointer to the image to query. +//! +//! This function determines the height of an image in pixels. +//! +//! \return Returns the height of the image in pixels. +// +//***************************************************************************** +#define GrImageHeightGet(pucImage) \ + (*(unsigned short *)(pucImage + 3)) + +//***************************************************************************** +// +//! Gets the width of an image. +//! +//! \param pucImage is a pointer to the image to query. +//! +//! This function determines the width of an image in pixels. +//! +//! \return Returns the width of the image in pixels. +// +//***************************************************************************** +#define GrImageWidthGet(pucImage) \ + (*(unsigned short *)(pucImage + 1)) + +//***************************************************************************** +// +//! Determines the size of the buffer for a 1 BPP off-screen image. +//! +//! \param lWidth is the width of the image in pixels. +//! \param lHeight is the height of the image in pixels. +//! +//! This function determines the size of the memory buffer required to hold a +//! 1 BPP off-screen image of the specified geometry. +//! +//! \return Returns the number of bytes required by the image. +// +//***************************************************************************** +#define GrOffScreen1BPPSize(lWidth, lHeight) \ + (5 + (((lWidth + 7) / 8) * lHeight)) + +//***************************************************************************** +// +//! Determines the size of the buffer for a 4 BPP off-screen image. +//! +//! \param lWidth is the width of the image in pixels. +//! \param lHeight is the height of the image in pixels. +//! +//! This function determines the size of the memory buffer required to hold a +//! 4 BPP off-screen image of the specified geometry. +//! +//! \return Returns the number of bytes required by the image. +// +//***************************************************************************** +#define GrOffScreen4BPPSize(lWidth, lHeight) \ + (6 + (16 * 3) + (((lWidth + 1) / 2) * lHeight)) + +//***************************************************************************** +// +//! Determines the size of the buffer for an 8 BPP off-screen image. +//! +//! \param lWidth is the width of the image in pixels. +//! \param lHeight is the height of the image in pixels. +//! +//! This function determines the size of the memory buffer required to hold an +//! 8 BPP off-screen image of the specified geometry. +//! +//! \return Returns the number of bytes required by the image. +// +//***************************************************************************** +#define GrOffScreen8BPPSize(lWidth, lHeight) \ + (6 + (256 * 3) + (lWidth * lHeight)) + +//***************************************************************************** +// +//! Draws a pixel. +//! +//! \param pContext is a pointer to the drawing context to use. +//! \param lX is the X coordinate of the pixel. +//! \param lY is the Y coordinate of the pixel. +//! +//! This function draws a pixel if it resides within the clipping region. +//! +//! \return None. +// +//***************************************************************************** +#define GrPixelDraw(pContext, lX, lY) \ + do \ + { \ + const tContext *pC = pContext; \ + if((lX >= pC->sClipRegion.sXMin) && \ + (lX <= pC->sClipRegion.sXMax) && \ + (lY >= pC->sClipRegion.sYMin) && \ + (lY <= pC->sClipRegion.sYMax)) \ + { \ + DpyPixelDraw(pC->pDisplay, lX, lY, pC->ulForeground); \ + } \ + } \ + while(0) + +//***************************************************************************** +// +//! Gets the baseline of a string. +//! +//! \param pContext is a pointer to the drawing context to query. +//! +//! This function determines the baseline position of a string. The baseline +//! is the offset between the top of the string and the bottom of the capital +//! letters. The only string data that exists below the baseline are the +//! descenders on some lower-case letters (such as ``y''). +//! +//! \return Returns the baseline of the string, in pixels. +// +//***************************************************************************** +#define GrStringBaselineGet(pContext) \ + ((pContext)->pFont->ucBaseline) + +//***************************************************************************** +// +//! Draws a centered string. +//! +//! \param pContext is a pointer to the drawing context to use. +//! \param pcString is a pointer to the string to be drawn. +//! \param lLength is the number of characters from the string that should be +//! drawn on the screen. +//! \param lX is the X coordinate of the center of the string position on the +//! screen. +//! \param lY is the Y coordinate of the center of the string position on the +//! screen. +//! \param bOpaque is \b true if the background of each character should be +//! drawn and \b false if it should not (leaving the background as is). +//! +//! This function draws a string of test on the screen centered upon the +//! provided position. The \e lLength parameter allows a portion of the +//! string to be examined without having to insert a NULL character at the +//! stopping point (which would not be possible if the string was located in +//! flash); specifying a length of -1 will cause the entire string to be +//! rendered (subject to clipping). +//! +//! \return None. +// +//***************************************************************************** +#define GrStringDrawCentered(pContext, pcString, lLength, lX, lY, bOpaque) \ + do \ + { \ + const tContext *pC = pContext; \ + const char *pcStr = pcString; \ + \ + GrStringDraw(pC, pcStr, lLength, \ + (lX) - (GrStringWidthGet(pC, pcStr, lLength) / 2), \ + (lY) - (pC->pFont->ucBaseline / 2), bOpaque); \ + } \ + while(0) + +//***************************************************************************** +// +//! Gets the height of a string. +//! +//! \param pContext is a pointer to the drawing context to query. +//! +//! This function determines the height of a string. The height is the offset +//! between the top of the string and the bottom of the string, including any +//! ascenders and descenders. Note that this will not account for the case +//! where the string in question does not have any characters that use +//! descenders but the font in the drawing context does contain characters with +//! descenders. +//! +//! \return Returns the height of the string, in pixels. +// +//***************************************************************************** +#define GrStringHeightGet(pContext) \ + ((pContext)->pFont->ucHeight) + +//***************************************************************************** +// +//! Gets the maximum width of a character in a string. +//! +//! \param pContext is a pointer to the drawing context to query. +//! +//! This function determines the maximum width of a character in a string. The +//! maximum width is the width of the widest individual character in the font +//! used to render the string, which may be wider than the widest character +//! that is used to render a particular string. +//! +//! \return Returns the maximum width of a character in a string, in pixels. +// +//***************************************************************************** +#define GrStringMaxWidthGet(pContext) \ + ((pContext)->pFont->ucMaxWidth) + +//***************************************************************************** +// +// A set of color definitions. This set is the subset of the X11 colors (from +// rgb.txt) that are supported by typical web browsers. +// +//***************************************************************************** +#define ClrAliceBlue 0x00F0F8FF +#define ClrAntiqueWhite 0x00FAEBD7 +#define ClrAqua 0x0000FFFF +#define ClrAquamarine 0x007FFFD4 +#define ClrAzure 0x00F0FFFF +#define ClrBeige 0x00F5F5DC +#define ClrBisque 0x00FFE4C4 +#define ClrBlack 0x00000000 +#define ClrBlanchedAlmond 0x00FFEBCD +#define ClrBlue 0x000000FF +#define ClrBlueViolet 0x008A2BE2 +#define ClrBrown 0x00A52A2A +#define ClrBurlyWood 0x00DEB887 +#define ClrCadetBlue 0x005F9EA0 +#define ClrChartreuse 0x007FFF00 +#define ClrChocolate 0x00D2691E +#define ClrCoral 0x00FF7F50 +#define ClrCornflowerBlue 0x006495ED +#define ClrCornsilk 0x00FFF8DC +#define ClrCrimson 0x00DC143C +#define ClrCyan 0x0000FFFF +#define ClrDarkBlue 0x0000008B +#define ClrDarkCyan 0x00008B8B +#define ClrDarkGoldenrod 0x00B8860B +#define ClrDarkGray 0x00A9A9A9 +#define ClrDarkGreen 0x00006400 +#define ClrDarkKhaki 0x00BDB76B +#define ClrDarkMagenta 0x008B008B +#define ClrDarkOliveGreen 0x00556B2F +#define ClrDarkOrange 0x00FF8C00 +#define ClrDarkOrchid 0x009932CC +#define ClrDarkRed 0x008B0000 +#define ClrDarkSalmon 0x00E9967A +#define ClrDarkSeaGreen 0x008FBC8F +#define ClrDarkSlateBlue 0x00483D8B +#define ClrDarkSlateGray 0x002F4F4F +#define ClrDarkTurquoise 0x0000CED1 +#define ClrDarkViolet 0x009400D3 +#define ClrDeepPink 0x00FF1493 +#define ClrDeepSkyBlue 0x0000BFFF +#define ClrDimGray 0x00696969 +#define ClrDodgerBlue 0x001E90FF +#define ClrFireBrick 0x00B22222 +#define ClrFloralWhite 0x00FFFAF0 +#define ClrForestGreen 0x00228B22 +#define ClrFuchsia 0x00FF00FF +#define ClrGainsboro 0x00DCDCDC +#define ClrGhostWhite 0x00F8F8FF +#define ClrGold 0x00FFD700 +#define ClrGoldenrod 0x00DAA520 +#define ClrGray 0x00808080 +#define ClrGreen 0x00008000 +#define ClrGreenYellow 0x00ADFF2F +#define ClrHoneydew 0x00F0FFF0 +#define ClrHotPink 0x00FF69B4 +#define ClrIndianRed 0x00CD5C5C +#define ClrIndigo 0x004B0082 +#define ClrIvory 0x00FFFFF0 +#define ClrKhaki 0x00F0E68C +#define ClrLavender 0x00E6E6FA +#define ClrLavenderBlush 0x00FFF0F5 +#define ClrLawnGreen 0x007CFC00 +#define ClrLemonChiffon 0x00FFFACD +#define ClrLightBlue 0x00ADD8E6 +#define ClrLightCoral 0x00F08080 +#define ClrLightCyan 0x00E0FFFF +#define ClrLightGoldenrodYellow 0x00FAFAD2 +#define ClrLightGreen 0x0090EE90 +#define ClrLightGrey 0x00D3D3D3 +#define ClrLightPink 0x00FFB6C1 +#define ClrLightSalmon 0x00FFA07A +#define ClrLightSeaGreen 0x0020B2AA +#define ClrLightSkyBlue 0x0087CEFA +#define ClrLightSlateGray 0x00778899 +#define ClrLightSteelBlue 0x00B0C4DE +#define ClrLightYellow 0x00FFFFE0 +#define ClrLime 0x0000FF00 +#define ClrLimeGreen 0x0032CD32 +#define ClrLinen 0x00FAF0E6 +#define ClrMagenta 0x00FF00FF +#define ClrMaroon 0x00800000 +#define ClrMediumAquamarine 0x0066CDAA +#define ClrMediumBlue 0x000000CD +#define ClrMediumOrchid 0x00BA55D3 +#define ClrMediumPurple 0x009370DB +#define ClrMediumSeaGreen 0x003CB371 +#define ClrMediumSlateBlue 0x007B68EE +#define ClrMediumSpringGreen 0x0000FA9A +#define ClrMediumTurquoise 0x0048D1CC +#define ClrMediumVioletRed 0x00C71585 +#define ClrMidnightBlue 0x00191970 +#define ClrMintCream 0x00F5FFFA +#define ClrMistyRose 0x00FFE4E1 +#define ClrMoccasin 0x00FFE4B5 +#define ClrNavajoWhite 0x00FFDEAD +#define ClrNavy 0x00000080 +#define ClrOldLace 0x00FDF5E6 +#define ClrOlive 0x00808000 +#define ClrOliveDrab 0x006B8E23 +#define ClrOrange 0x00FFA500 +#define ClrOrangeRed 0x00FF4500 +#define ClrOrchid 0x00DA70D6 +#define ClrPaleGoldenrod 0x00EEE8AA +#define ClrPaleGreen 0x0098FB98 +#define ClrPaleTurquoise 0x00AFEEEE +#define ClrPaleVioletRed 0x00DB7093 +#define ClrPapayaWhip 0x00FFEFD5 +#define ClrPeachPuff 0x00FFDAB9 +#define ClrPeru 0x00CD853F +#define ClrPink 0x00FFC0CB +#define ClrPlum 0x00DDA0DD +#define ClrPowderBlue 0x00B0E0E6 +#define ClrPurple 0x00800080 +#define ClrRed 0x00FF0000 +#define ClrRosyBrown 0x00BC8F8F +#define ClrRoyalBlue 0x004169E1 +#define ClrSaddleBrown 0x008B4513 +#define ClrSalmon 0x00FA8072 +#define ClrSandyBrown 0x00F4A460 +#define ClrSeaGreen 0x002E8B57 +#define ClrSeashell 0x00FFF5EE +#define ClrSienna 0x00A0522D +#define ClrSilver 0x00C0C0C0 +#define ClrSkyBlue 0x0087CEEB +#define ClrSlateBlue 0x006A5ACD +#define ClrSlateGray 0x00708090 +#define ClrSnow 0x00FFFAFA +#define ClrSpringGreen 0x0000FF7F +#define ClrSteelBlue 0x004682B4 +#define ClrTan 0x00D2B48C +#define ClrTeal 0x00008080 +#define ClrThistle 0x00D8BFD8 +#define ClrTomato 0x00FF6347 +#define ClrTurquoise 0x0040E0D0 +#define ClrViolet 0x00EE82EE +#define ClrWheat 0x00F5DEB3 +#define ClrWhite 0x00FFFFFF +#define ClrWhiteSmoke 0x00F5F5F5 +#define ClrYellow 0x00FFFF00 +#define ClrYellowGreen 0x009ACD32 + +//***************************************************************************** +// +// Masks and shifts to aid in color format translation by drivers. +// +//***************************************************************************** +#define ClrRedMask 0x00FF0000 +#define ClrRedShift 16 +#define ClrGreenMask 0x0000FF00 +#define ClrGreenShift 8 +#define ClrBlueMask 0x000000FF +#define ClrBlueShift 0 + +//***************************************************************************** +// +// Prototypes for the predefined fonts in the graphics library. ..Cm.. is the +// computer modern font, which is a serif font. ..Cmsc.. is the computer +// modern small-caps font, which is also a serif font. ..Cmss.. is the +// computer modern sans-serif font. +// +//***************************************************************************** +extern const tFont g_sFontCm12; +extern const tFont g_sFontCm12b; +extern const tFont g_sFontCm12i; +extern const tFont g_sFontCm14; +extern const tFont g_sFontCm14b; +extern const tFont g_sFontCm14i; +extern const tFont g_sFontCm16; +extern const tFont g_sFontCm16b; +extern const tFont g_sFontCm16i; +extern const tFont g_sFontCm18; +extern const tFont g_sFontCm18b; +extern const tFont g_sFontCm18i; +extern const tFont g_sFontCm20; +extern const tFont g_sFontCm20b; +extern const tFont g_sFontCm20i; +extern const tFont g_sFontCm22; +extern const tFont g_sFontCm22b; +extern const tFont g_sFontCm22i; +extern const tFont g_sFontCm24; +extern const tFont g_sFontCm24b; +extern const tFont g_sFontCm24i; +extern const tFont g_sFontCm26; +extern const tFont g_sFontCm26b; +extern const tFont g_sFontCm26i; +extern const tFont g_sFontCm28; +extern const tFont g_sFontCm28b; +extern const tFont g_sFontCm28i; +extern const tFont g_sFontCm30; +extern const tFont g_sFontCm30b; +extern const tFont g_sFontCm30i; +extern const tFont g_sFontCm32; +extern const tFont g_sFontCm32b; +extern const tFont g_sFontCm32i; +extern const tFont g_sFontCm34; +extern const tFont g_sFontCm34b; +extern const tFont g_sFontCm34i; +extern const tFont g_sFontCm36; +extern const tFont g_sFontCm36b; +extern const tFont g_sFontCm36i; +extern const tFont g_sFontCm38; +extern const tFont g_sFontCm38b; +extern const tFont g_sFontCm38i; +extern const tFont g_sFontCm40; +extern const tFont g_sFontCm40b; +extern const tFont g_sFontCm40i; +extern const tFont g_sFontCm42; +extern const tFont g_sFontCm42b; +extern const tFont g_sFontCm42i; +extern const tFont g_sFontCm44; +extern const tFont g_sFontCm44b; +extern const tFont g_sFontCm44i; +extern const tFont g_sFontCm46; +extern const tFont g_sFontCm46b; +extern const tFont g_sFontCm46i; +extern const tFont g_sFontCm48; +extern const tFont g_sFontCm48b; +extern const tFont g_sFontCm48i; +extern const tFont g_sFontCmsc12; +extern const tFont g_sFontCmsc14; +extern const tFont g_sFontCmsc16; +extern const tFont g_sFontCmsc18; +extern const tFont g_sFontCmsc20; +extern const tFont g_sFontCmsc22; +extern const tFont g_sFontCmsc24; +extern const tFont g_sFontCmsc26; +extern const tFont g_sFontCmsc28; +extern const tFont g_sFontCmsc30; +extern const tFont g_sFontCmsc32; +extern const tFont g_sFontCmsc34; +extern const tFont g_sFontCmsc36; +extern const tFont g_sFontCmsc38; +extern const tFont g_sFontCmsc40; +extern const tFont g_sFontCmsc42; +extern const tFont g_sFontCmsc44; +extern const tFont g_sFontCmsc46; +extern const tFont g_sFontCmsc48; +extern const tFont g_sFontCmss12; +extern const tFont g_sFontCmss12b; +extern const tFont g_sFontCmss12i; +extern const tFont g_sFontCmss14; +extern const tFont g_sFontCmss14b; +extern const tFont g_sFontCmss14i; +extern const tFont g_sFontCmss16; +extern const tFont g_sFontCmss16b; +extern const tFont g_sFontCmss16i; +extern const tFont g_sFontCmss18; +extern const tFont g_sFontCmss18b; +extern const tFont g_sFontCmss18i; +extern const tFont g_sFontCmss20; +extern const tFont g_sFontCmss20b; +extern const tFont g_sFontCmss20i; +extern const tFont g_sFontCmss22; +extern const tFont g_sFontCmss22b; +extern const tFont g_sFontCmss22i; +extern const tFont g_sFontCmss24; +extern const tFont g_sFontCmss24b; +extern const tFont g_sFontCmss24i; +extern const tFont g_sFontCmss26; +extern const tFont g_sFontCmss26b; +extern const tFont g_sFontCmss26i; +extern const tFont g_sFontCmss28; +extern const tFont g_sFontCmss28b; +extern const tFont g_sFontCmss28i; +extern const tFont g_sFontCmss30; +extern const tFont g_sFontCmss30b; +extern const tFont g_sFontCmss30i; +extern const tFont g_sFontCmss32; +extern const tFont g_sFontCmss32b; +extern const tFont g_sFontCmss32i; +extern const tFont g_sFontCmss34; +extern const tFont g_sFontCmss34b; +extern const tFont g_sFontCmss34i; +extern const tFont g_sFontCmss36; +extern const tFont g_sFontCmss36b; +extern const tFont g_sFontCmss36i; +extern const tFont g_sFontCmss38; +extern const tFont g_sFontCmss38b; +extern const tFont g_sFontCmss38i; +extern const tFont g_sFontCmss40; +extern const tFont g_sFontCmss40b; +extern const tFont g_sFontCmss40i; +extern const tFont g_sFontCmss42; +extern const tFont g_sFontCmss42b; +extern const tFont g_sFontCmss42i; +extern const tFont g_sFontCmss44; +extern const tFont g_sFontCmss44b; +extern const tFont g_sFontCmss44i; +extern const tFont g_sFontCmss46; +extern const tFont g_sFontCmss46b; +extern const tFont g_sFontCmss46i; +extern const tFont g_sFontCmss48; +extern const tFont g_sFontCmss48b; +extern const tFont g_sFontCmss48i; +extern const tFont g_sFontFixed6x8; + +//***************************************************************************** +// +//! Translates a 24-bit RGB color to a display driver-specific color. +//! +//! \param pDisplay is the pointer to the display driver structure for the +//! display to operate upon. +//! \param ulValue is the 24-bit RGB color. The least-significant byte is the +//! blue channel, the next byte is the green channel, and the third byte is the +//! red channel. +//! +//! This function translates a 24-bit RGB color into a value that can be +//! written into the display's frame buffer in order to reproduce that color, +//! or the closest possible approximation of that color. +//! +//! \return Returns the display-driver specific color. +// +//***************************************************************************** +#define DpyColorTranslate(pDisplay, ulValue) \ + ((pDisplay)->pfnColorTranslate((pDisplay)->pvDisplayData, ulValue)) + +//***************************************************************************** +// +//! Flushes cached drawing operations. +//! +//! \param pDisplay is the pointer to the display driver structure for the +//! display to operate upon. +//! +//! This function flushes any cached drawing operations on a display. +//! +//! \return None. +// +//***************************************************************************** +#define DpyFlush(pDisplay) \ + do \ + { \ + const tDisplay *pD = pDisplay; \ + pD->pfnFlush(pD->pvDisplayData); \ + } \ + while(0) + +//***************************************************************************** +// +//! Gets the height of the display. +//! +//! \param pDisplay is a pointer to the display driver structure for the +//! display to query. +//! +//! This function determines the height of the display. +//! +//! \return Returns the height of the display in pixels. +// +//***************************************************************************** +#define DpyHeightGet(pDisplay) \ + ((pDisplay)->usHeight) + +//***************************************************************************** +// +//! Draws a horizontal line on a display. +//! +//! \param pDisplay is the pointer to the display driver structure for the +//! display to operate upon. +//! \param lX1 is the starting X coordinate of the line. +//! \param lX2 is the ending X coordinate of the line. +//! \param lY is the Y coordinate of the line. +//! \param ulValue is the color to draw the line. +//! +//! This function draws a horizontal line on a display. This assumes that +//! clipping has already been performed, and that both end points of the line +//! are within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +#define DpyLineDrawH(pDisplay, lX1, lX2, lY, ulValue) \ + do \ + { \ + const tDisplay *pD = pDisplay; \ + pD->pfnLineDrawH(pD->pvDisplayData, lX1, lX2, lY, ulValue); \ + } \ + while(0) + +//***************************************************************************** +// +//! Draws a vertical line on a display. +//! +//! \param pDisplay is the pointer to the display driver structure for the +//! display to operate upon. +//! \param lX is the X coordinate of the line. +//! \param lY1 is the starting Y coordinate of the line. +//! \param lY2 is the ending Y coordinate of the line. +//! \param ulValue is the color to draw the line. +//! +//! This function draws a vertical line on a display. This assumes that +//! clipping has already been performed, and that both end points of the line +//! are within the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +#define DpyLineDrawV(pDisplay, lX, lY1, lY2, ulValue) \ + do \ + { \ + const tDisplay *pD = pDisplay; \ + pD->pfnLineDrawV(pD->pvDisplayData, lX, lY1, lY2, ulValue); \ + } \ + while(0) + +//***************************************************************************** +// +//! Draws a pixel on a display. +//! +//! \param pDisplay is the pointer to the display driver structure for the +//! display to operate upon. +//! \param lX is the X coordinate of the pixel. +//! \param lY is the Y coordinate of the pixel. +//! \param ulValue is the color to draw the pixel. +//! +//! This function draws a pixel on a display. This assumes that clipping has +//! already been performed. +//! +//! \return None. +// +//***************************************************************************** +#define DpyPixelDraw(pDisplay, lX, lY, ulValue) \ + do \ + { \ + const tDisplay *pD = pDisplay; \ + pD->pfnPixelDraw(pD->pvDisplayData, lX, lY, ulValue); \ + } \ + while(0) + +//***************************************************************************** +// +//! Draws a horizontal sequence of pixels on a display. +//! +//! \param pDisplay is the pointer to the display driver structure for the +//! display to operate upon. +//! \param lX is the X coordinate of the first pixel. +//! \param lY is the Y coordinate of the first pixel. +//! \param lX0 is sub-pixel offset within the pixel data, which is valid for 1 +//! or 4 bit per pixel formats. +//! \param lCount is the number of pixels to draw. +//! \param lBPP is the number of bits per pixel; must be 1, 4, or 8. +//! \param pucData is a pointer to the pixel data. For 1 and 4 bit per pixel +//! formats, the most significant bit(s) represent the left-most pixel. +//! \param pucPalette is a pointer to the palette used to draw the pixels. +//! +//! This function draws a horizontal sequence of pixels on a display, using the +//! supplied palette. For 1 bit per pixel format, the palette contains +//! pre-translated colors; for 4 and 8 bit per pixel formats, the palette +//! contains 24-bit RGB values that must be translated before being written to +//! the display. +//! +//! \return None. +// +//***************************************************************************** +#define DpyPixelDrawMultiple(pDisplay, lX, lY, lX0, lCount, lBPP, pucData, \ + pucPalette) \ + do \ + { \ + const tDisplay *pD = pDisplay; \ + pD->pfnPixelDrawMultiple(pD->pvDisplayData, lX, lY, lX0, lCount, \ + lBPP, pucData, pucPalette); \ + } \ + while(0) + +//***************************************************************************** +// +//! Fills a rectangle on a display. +//! +//! \param pDisplay is the pointer to the display driver structure for the +//! display to operate upon. +//! \param pRect is a pointer to the structure describing the rectangle to +//! fill. +//! \param ulValue is the color to fill the rectangle. +//! +//! This function fills a rectangle on the display. This assumes that clipping +//! has already been performed, and that all sides of the rectangle are within +//! the extents of the display. +//! +//! \return None. +// +//***************************************************************************** +#define DpyRectFill(pDisplay, pRect, ulValue) \ + do \ + { \ + const tDisplay *pD = pDisplay; \ + pD->pfnRectFill(pD->pvDisplayData, pRect, ulValue); \ + } \ + while(0) + +//***************************************************************************** +// +//! Gets the width of the display. +//! +//! \param pDisplay is a pointer to the display driver structure for the +//! display to query. +//! +//! This function determines the width of the display. +//! +//! \return Returns the width of the display in pixels. +// +//***************************************************************************** +#define DpyWidthGet(pDisplay) \ + ((pDisplay)->usWidth) + +//***************************************************************************** +// +// Prototypes for the graphics library functions. +// +//***************************************************************************** +extern void GrCircleDraw(const tContext *pContext, long lX, long lY, + long lRadius); +extern void GrCircleFill(const tContext *pContext, long lX, long lY, + long lRadius); +extern void GrContextClipRegionSet(tContext *pContext, tRectangle *pRect); +extern void GrContextInit(tContext *pContext, const tDisplay *pDisplay); +extern void GrImageDraw(const tContext *pContext, + const unsigned char *pucImage, long lX, long lY); +extern void GrLineDraw(const tContext *pContext, long lX1, long lY1, long lX2, + long lY2); +extern void GrLineDrawH(const tContext *pContext, long lX1, long lX2, long lY); +extern void GrLineDrawV(const tContext *pContext, long lX, long lY1, long lY2); +extern void GrOffScreen1BPPInit(tDisplay *pDisplay, unsigned char *pucImage, + long lWidth, long lHeight); +extern void GrOffScreen4BPPInit(tDisplay *pDisplay, unsigned char *pucImage, + long lWidth, long lHeight); +extern void GrOffScreen4BPPPaletteSet(tDisplay *pDisplay, + unsigned long *pulPalette, + unsigned long ulOffset, + unsigned long ulCount); +extern void GrOffScreen8BPPInit(tDisplay *pDisplay, unsigned char *pucImage, + long lWidth, long lHeight); +extern void GrOffScreen8BPPPaletteSet(tDisplay *pDisplay, + unsigned long *pulPalette, + unsigned long ulOffset, + unsigned long ulCount); +extern void GrRectDraw(const tContext *pContext, const tRectangle *pRect); +extern void GrRectFill(const tContext *pContext, const tRectangle *pRect); +extern void GrStringDraw(const tContext *pContext, const char *pcString, + long lLength, long lX, long lY, + unsigned long bOpaque); +extern long GrStringWidthGet(const tContext *pContext, const char *pcString, + long lLength); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // __GRLIB_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hibernate.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hibernate.h new file mode 100644 index 0000000..d17bfbe --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hibernate.h @@ -0,0 +1,131 @@ +//***************************************************************************** +// +// hibernate.h - API definition for the Hibernation module. +// +// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HIBERNATE_H__ +#define __HIBERNATE_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macros needed for selecting the clock source for HibernateClockSelect() +// +//***************************************************************************** +#define HIBERNATE_CLOCK_SEL_RAW 0x04 +#define HIBERNATE_CLOCK_SEL_DIV128 0x00 + +//***************************************************************************** +// +// Macros need to configure wake events for HibernateWakeSet() +// +//***************************************************************************** +#define HIBERNATE_WAKE_PIN 0x10 +#define HIBERNATE_WAKE_RTC 0x08 + +//***************************************************************************** +// +// Macros needed to configure low battery detect for HibernateLowBatSet() +// +//***************************************************************************** +#define HIBERNATE_LOW_BAT_DETECT 0x20 +#define HIBERNATE_LOW_BAT_ABORT 0xA0 + +//***************************************************************************** +// +// Macros defining interrupt source bits for the interrupt functions. +// +//***************************************************************************** +#define HIBERNATE_INT_PIN_WAKE 0x08 +#define HIBERNATE_INT_LOW_BAT 0x04 +#define HIBERNATE_INT_RTC_MATCH_0 0x01 +#define HIBERNATE_INT_RTC_MATCH_1 0x02 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void HibernateEnableExpClk(unsigned long ulHibClk); +extern void HibernateDisable(void); +extern void HibernateClockSelect(unsigned long ulClockInput); +extern void HibernateRTCEnable(void); +extern void HibernateRTCDisable(void); +extern void HibernateWakeSet(unsigned long ulWakeFlags); +extern unsigned long HibernateWakeGet(void); +extern void HibernateLowBatSet(unsigned long ulLowBatFlags); +extern unsigned long HibernateLowBatGet(void); +extern void HibernateRTCSet(unsigned long ulRTCValue); +extern unsigned long HibernateRTCGet(void); +extern void HibernateRTCMatch0Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch0Get(void); +extern void HibernateRTCMatch1Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch1Get(void); +extern void HibernateRTCTrimSet(unsigned long ulTrim); +extern unsigned long HibernateRTCTrimGet(void); +extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateRequest(void); +extern void HibernateIntEnable(unsigned long ulIntFlags); +extern void HibernateIntDisable(unsigned long ulIntFlags); +extern void HibernateIntRegister(void (*pfnHandler)(void)); +extern void HibernateIntUnregister(void); +extern unsigned long HibernateIntStatus(tBoolean bMasked); +extern void HibernateIntClear(unsigned long ulIntFlags); +extern unsigned int HibernateIsActive(void); + +//***************************************************************************** +// +// Several Hibernate module APIs have been renamed, with the original function +// name being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define HibernateEnable(a) \ + HibernateEnableExpClk(a, SysCtlClockGet()) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HIBERNATE_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_adc.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_adc.h new file mode 100644 index 0000000..69427a3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_adc.h @@ -0,0 +1,614 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_M 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_M 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_M 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_M 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_M 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_M 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_M 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_M 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control. +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter. +#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator. +#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator. +#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator. +#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator. +#define ADC_TMLB_LB 0x00000001 // Loopback control signals +#define ADC_TMLB_CNT_S 6 // Sample counter shift +#define ADC_TMLB_MUX_S 0 // Input channel number shift + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +#define ADC_SSMUX0_MUX7_M 0x70000000 // 8th Sample Input Select. +#define ADC_SSMUX0_MUX6_M 0x07000000 // 7th Sample Input Select. +#define ADC_SSMUX0_MUX5_M 0x00700000 // 6th Sample Input Select. +#define ADC_SSMUX0_MUX4_M 0x00070000 // 5th Sample Input Select. +#define ADC_SSMUX0_MUX3_M 0x00007000 // 4th Sample Input Select. +#define ADC_SSMUX0_MUX2_M 0x00000700 // 3rd Sample Input Select. +#define ADC_SSMUX0_MUX1_M 0x00000070 // 2nd Sample Input Select. +#define ADC_SSMUX0_MUX0_M 0x00000007 // 1st Sample Input Select. +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable. +#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence. +#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select. +#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable. +#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence. +#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select. +#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable. +#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence. +#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select. +#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable. +#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence. +#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select. +#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select. +#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable. +#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence. +#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select. +#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select. +#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable. +#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence. +#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select. +#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select. +#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable. +#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence. +#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select. +#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select. +#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable. +#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence. +#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data. +#define ADC_SSFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full. +#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty. +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer. +#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer. +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +#define ADC_SSMUX1_MUX3_M 0x00007000 // 4th Sample Input Select. +#define ADC_SSMUX1_MUX2_M 0x00000700 // 3rd Sample Input Select. +#define ADC_SSMUX1_MUX1_M 0x00000070 // 2nd Sample Input Select. +#define ADC_SSMUX1_MUX0_M 0x00000007 // 1st Sample Input Select. +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select. +#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable. +#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence. +#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select. +#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select. +#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable. +#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence. +#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select. +#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select. +#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable. +#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence. +#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select. +#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select. +#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable. +#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence. +#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data. +#define ADC_SSFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full. +#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty. +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer. +#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer. +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +#define ADC_SSMUX2_MUX3_M 0x00007000 // 4th Sample Input Select. +#define ADC_SSMUX2_MUX2_M 0x00000700 // 3rd Sample Input Select. +#define ADC_SSMUX2_MUX1_M 0x00000070 // 2nd Sample Input Select. +#define ADC_SSMUX2_MUX0_M 0x00000007 // 1st Sample Input Select. +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select. +#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable. +#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence. +#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select. +#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select. +#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable. +#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence. +#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select. +#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select. +#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable. +#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence. +#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select. +#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select. +#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable. +#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence. +#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data. +#define ADC_SSFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full. +#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty. +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer. +#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer. +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +#define ADC_SSMUX3_MUX0_M 0x00000007 // 1st Sample Input Select. +#define ADC_SSMUX3_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select. +#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable. +#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence. +#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data. +#define ADC_SSFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full. +#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty. +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer. +#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer. +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the ADC sequence register offsets. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_EMUX +// register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSPRI +// register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSMUX0, +// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present +// in all registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSCTL0, +// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present +// in all registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSFIFO0, +// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0, +// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the loopback ADC +// data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif + +#endif // __HW_ADC_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_can.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_can.h new file mode 100644 index 0000000..bc64f0d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_can.h @@ -0,0 +1,757 @@ +//***************************************************************************** +// +// hw_can.h - Defines and macros used when accessing the can. +// +// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_CAN_H__ +#define __HW_CAN_H__ + +//***************************************************************************** +// +// The following are defines for the CAN register offsets. +// +//***************************************************************************** +#define CAN_O_CTL 0x00000000 // Control register +#define CAN_O_STS 0x00000004 // Status register +#define CAN_O_ERR 0x00000008 // Error register +#define CAN_O_BIT 0x0000000C // Bit Timing register +#define CAN_O_INT 0x00000010 // Interrupt register +#define CAN_O_TST 0x00000014 // Test register +#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register +#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. +#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. +#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register +#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register +#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. +#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. +#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. +#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register +#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register +#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register +#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register +#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. +#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. +#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register +#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register +#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. +#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. +#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. +#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register +#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register +#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register +#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register +#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register +#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register +#define CAN_O_NWDA1 0x00000120 // New Data 1 register +#define CAN_O_NWDA2 0x00000124 // New Data 2 register +#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending +#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending +#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid +#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_CTL register. +// +//***************************************************************************** +#define CAN_CTL_TEST 0x00000080 // Test mode enable +#define CAN_CTL_CCE 0x00000040 // Configuration change enable +#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission +#define CAN_CTL_EIE 0x00000008 // Error interrupt enable +#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable +#define CAN_CTL_IE 0x00000002 // Module interrupt enable +#define CAN_CTL_INIT 0x00000001 // Initialization + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_STS register. +// +//***************************************************************************** +#define CAN_STS_BOFF 0x00000080 // Bus Off status +#define CAN_STS_EWARN 0x00000040 // Error Warning status +#define CAN_STS_EPASS 0x00000020 // Error Passive status +#define CAN_STS_RXOK 0x00000010 // Received Message Successful +#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful +#define CAN_STS_LEC_M 0x00000007 // Last Error Code +#define CAN_STS_LEC_NONE 0x00000000 // No error +#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error +#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error +#define CAN_STS_LEC_ACK 0x00000003 // Ack error +#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error +#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error +#define CAN_STS_LEC_CRC 0x00000006 // CRC error +#define CAN_STS_LEC_NOEVENT 0x00000007 // Unused + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_ERR register. +// +//***************************************************************************** +#define CAN_ERR_RP 0x00008000 // Receive error passive status +#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter. +#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter. +#define CAN_ERR_REC_S 8 // Receive error counter bit pos +#define CAN_ERR_TEC_S 0 // Transmit error counter bit pos + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_BIT register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point. +#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample + // Point. +#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width. +#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescalar. +#define CAN_BIT_TSEG2_S 12 +#define CAN_BIT_TSEG1_S 8 +#define CAN_BIT_SJW_S 6 +#define CAN_BIT_BRP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_INT register. +// +//***************************************************************************** +#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier. +#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending +#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TST register. +// +//***************************************************************************** +#define CAN_TST_RX 0x00000080 // CAN_RX pin status +#define CAN_TST_TX_M 0x00000060 // Overide control of CAN_TX pin +#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX +#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX +#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX +#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX +#define CAN_TST_LBACK 0x00000010 // Loop back mode +#define CAN_TST_SILENT 0x00000008 // Silent mode +#define CAN_TST_BASIC 0x00000004 // Basic mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_BRPE register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescalar Extension. +#define CAN_BRPE_BRPE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TXRQ1 register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits. +#define CAN_TXRQ1_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TXRQ2 register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits. +#define CAN_TXRQ2_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_NWDA1 register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits. +#define CAN_NWDA1_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_NWDA2 register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits. +#define CAN_NWDA2_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CRQ register. +// +//***************************************************************************** +#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag. +#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number. +#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; + // it is interpreted as 0x20, or + // object 32. + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CMSK register. +// +//***************************************************************************** +#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read. +#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits. +#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits. +#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits. +#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit. +#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data. +#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request. +#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3. +#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7. + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. +// +//***************************************************************************** +#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask. +#define CAN_IF1MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. +// +//***************************************************************************** +#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier. +#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction. +#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask. +#define CAN_IF1MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. +// +//***************************************************************************** +#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier. +#define CAN_IF1ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. +// +//***************************************************************************** +#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid. +#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier. +#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction. +#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier. +#define CAN_IF1ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MCTL register. +// +//***************************************************************************** +#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data. +#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost. +#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending. +#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask. +#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable. +#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable. +#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable. +#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request. +#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer. +#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code. +#define CAN_IF1MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA1 register. +// +//***************************************************************************** +#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data. +#define CAN_IF1DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA2 register. +// +//***************************************************************************** +#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data. +#define CAN_IF1DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB1 register. +// +//***************************************************************************** +#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data. +#define CAN_IF1DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB2 register. +// +//***************************************************************************** +#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data. +#define CAN_IF1DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CRQ register. +// +//***************************************************************************** +#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag. +#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number. +#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; + // it is interpreted as 0x20, or + // object 32. + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CMSK register. +// +//***************************************************************************** +#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read. +#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits. +#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits. +#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits. +#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit. +#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data. +#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request. +#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3. +#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7. + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. +// +//***************************************************************************** +#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask. +#define CAN_IF2MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. +// +//***************************************************************************** +#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier. +#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction. +#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask. +#define CAN_IF2MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. +// +//***************************************************************************** +#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier. +#define CAN_IF2ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. +// +//***************************************************************************** +#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid. +#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier. +#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction. +#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier. +#define CAN_IF2ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MCTL register. +// +//***************************************************************************** +#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data. +#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost. +#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending. +#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask. +#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable. +#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable. +#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable. +#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request. +#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer. +#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code. +#define CAN_IF2MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA1 register. +// +//***************************************************************************** +#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data. +#define CAN_IF2DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA2 register. +// +//***************************************************************************** +#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data. +#define CAN_IF2DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB1 register. +// +//***************************************************************************** +#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data. +#define CAN_IF2DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB2 register. +// +//***************************************************************************** +#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data. +#define CAN_IF2DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1INT register. +// +//***************************************************************************** +#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits. +#define CAN_MSG1INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2INT register. +// +//***************************************************************************** +#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits. +#define CAN_MSG2INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1VAL register. +// +//***************************************************************************** +#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits. +#define CAN_MSG1VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2VAL register. +// +//***************************************************************************** +#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits. +#define CAN_MSG2VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the CAN register offsets. +// +//***************************************************************************** +#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. +#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. +#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. +#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the can +// registers. +// +//***************************************************************************** +#define CAN_RV_IF1MSK2 0x0000FFFF +#define CAN_RV_IF1MSK1 0x0000FFFF +#define CAN_RV_IF2MSK1 0x0000FFFF +#define CAN_RV_IF2MSK2 0x0000FFFF +#define CAN_RV_BIT 0x00002301 +#define CAN_RV_CTL 0x00000001 +#define CAN_RV_IF1CRQ 0x00000001 +#define CAN_RV_IF2CRQ 0x00000001 +#define CAN_RV_TXRQ2 0x00000000 +#define CAN_RV_IF2DB1 0x00000000 +#define CAN_RV_INT 0x00000000 +#define CAN_RV_IF1DB2 0x00000000 +#define CAN_RV_BRPE 0x00000000 +#define CAN_RV_IF2DA2 0x00000000 +#define CAN_RV_MSGVAL2 0x00000000 +#define CAN_RV_TXRQ1 0x00000000 +#define CAN_RV_IF1MCTL 0x00000000 +#define CAN_RV_IF1DB1 0x00000000 +#define CAN_RV_STS 0x00000000 +#define CAN_RV_MSGINT1 0x00000000 +#define CAN_RV_IF1DA2 0x00000000 +#define CAN_RV_TST 0x00000000 +#define CAN_RV_IF1ARB1 0x00000000 +#define CAN_RV_IF1ARB2 0x00000000 +#define CAN_RV_NWDA2 0x00000000 +#define CAN_RV_IF2CMSK 0x00000000 +#define CAN_RV_NWDA1 0x00000000 +#define CAN_RV_IF1DA1 0x00000000 +#define CAN_RV_IF2DA1 0x00000000 +#define CAN_RV_IF2MCTL 0x00000000 +#define CAN_RV_MSGVAL1 0x00000000 +#define CAN_RV_IF1CMSK 0x00000000 +#define CAN_RV_ERR 0x00000000 +#define CAN_RV_IF2ARB2 0x00000000 +#define CAN_RV_MSGINT2 0x00000000 +#define CAN_RV_IF2ARB1 0x00000000 +#define CAN_RV_IF2DB2 0x00000000 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_STS +// register. +// +//***************************************************************************** +#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_ERR +// register. +// +//***************************************************************************** +#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status +#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status +#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos +#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_BIT +// register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point +#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point +#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width +#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_INT +// register. +// +//***************************************************************************** +#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_TST +// register. +// +//***************************************************************************** +#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_BRPE +// register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1CRQ +// and CAN_IF1CRQ registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status +#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1CMSK +// and CAN_IF2CMSK registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read +#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit +#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) +#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) +#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 +#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1MSK1 +// and CAN_IF2MSK1 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1MSK2 +// and CAN_IF2MSK2 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier +#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction +#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1ARB1 +// and CAN_IF2ARB1 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFARB1_ID 0x0000FFFF // Identifier + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1ARB2 +// and CAN_IF2ARB2 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid +#define CAN_IFARB2_XTD 0x00004000 // Extended identifier +#define CAN_IFARB2_DIR 0x00002000 // Message direction +#define CAN_IFARB2_ID 0x00001FFF // Message identifier + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1MCTL +// and CAN_IF2MCTL registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data +#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost +#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending +#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask +#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable +#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable +#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable +#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request +#define CAN_IFMCTL_EOB 0x00000080 // End of buffer +#define CAN_IFMCTL_DLC 0x0000000F // Data length code + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1DA1 +// and CAN_IF2DA1 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1DA2 +// and CAN_IF2DA2 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1DB1 +// and CAN_IF2DB1 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_IF1DB2 +// and CAN_IF2DB2 registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_TXRQ1 +// register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_TXRQ2 +// register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_NWDA1 +// register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_NWDA2 +// register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_MSGINT1 +// register. +// +//***************************************************************************** +#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_MSGINT2 +// register. +// +//***************************************************************************** +#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_MSGVAL1 +// register. +// +//***************************************************************************** +#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the CAN_MSGVAL2 +// register. +// +//***************************************************************************** +#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits + +#endif + +#endif // __HW_CAN_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_comp.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_comp.h new file mode 100644 index 0000000..2109bb7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_comp.h @@ -0,0 +1,278 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following are defines for the comparator register offsets. +// +//***************************************************************************** +#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked + // Interrupt Status +#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt + // Status +#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt + // Enable +#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference + // Voltage Control +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACMIS register. +// +//***************************************************************************** +#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt + // Status. +#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt + // Status. +#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt + // Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACRIS register. +// +//***************************************************************************** +#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status. +#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status. +#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACINTEN register. +// +//***************************************************************************** +#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable. +#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable. +#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACREFCTL +// register. +// +//***************************************************************************** +#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable. +#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range. +#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref. +#define COMP_ACREFCTL_VREF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. +// +//***************************************************************************** +#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL0 register. +// +//***************************************************************************** +#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable. +#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive. +#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value +#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value. +#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense. +#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value. +#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense. +#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. +// +//***************************************************************************** +#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL1 register. +// +//***************************************************************************** +#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable. +#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive. +#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value +#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value. +#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense. +#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value. +#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense. +#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. +// +//***************************************************************************** +#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL2 register. +// +//***************************************************************************** +#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable. +#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive. +#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value +#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value. +#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense. +#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value. +#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense. +#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the comparator register offsets. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the COMP_MIS, +// COMP_RIS, and COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the COMP_REFCTL +// register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the COMP_ACSTAT0, +// COMP_ACSTAT1, and COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the COMP_ACCTL0, +// COMP_ACCTL1, and COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following are deprecated defines for the reset values for the comparator +// registers. +// +//***************************************************************************** +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. + +#endif + +#endif // __HW_COMP_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_ethernet.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_ethernet.h new file mode 100644 index 0000000..dac2706 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_ethernet.h @@ -0,0 +1,576 @@ +//***************************************************************************** +// +// hw_ethernet.h - Macros used when accessing the Ethernet hardware. +// +// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ETHERNET_H__ +#define __HW_ETHERNET_H__ + +//***************************************************************************** +// +// The following are defines for the MAC register offsets in the Ethernet +// Controller. +// +//***************************************************************************** +#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt + // Status +#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register +#define MAC_O_IM 0x00000004 // Interrupt Mask Register +#define MAC_O_RCTL 0x00000008 // Receive Control Register +#define MAC_O_TCTL 0x0000000C // Transmit Control Register +#define MAC_O_DATA 0x00000010 // Data Register +#define MAC_O_IA0 0x00000014 // Individual Address Register 0 +#define MAC_O_IA1 0x00000018 // Individual Address Register 1 +#define MAC_O_THR 0x0000001C // Threshold Register +#define MAC_O_MCTL 0x00000020 // Management Control Register +#define MAC_O_MDV 0x00000024 // Management Divider Register +#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg +#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg +#define MAC_O_NP 0x00000034 // Number of Packets Register +#define MAC_O_TR 0x00000038 // Transmission Request Register +#define MAC_O_TS 0x0000003C // Timer Support Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_IACK register. +// +//***************************************************************************** +#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt +#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete +#define MAC_IACK_RXER 0x00000010 // Clear RX Error +#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun +#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy +#define MAC_IACK_TXER 0x00000002 // Clear TX Error +#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_IM register. +// +//***************************************************************************** +#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt +#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete +#define MAC_IM_RXERM 0x00000010 // Mask RX Error +#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun +#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy +#define MAC_IM_TXERM 0x00000002 // Mask TX Error +#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_RCTL register. +// +//***************************************************************************** +#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO +#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC +#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode +#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets +#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_TCTL register. +// +//***************************************************************************** +#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode +#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation +#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding +#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_IA0 register. +// +//***************************************************************************** +#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4. +#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3. +#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2. +#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1. +#define MAC_IA0_MACOCT4_S 24 +#define MAC_IA0_MACOCT3_S 16 +#define MAC_IA0_MACOCT2_S 8 +#define MAC_IA0_MACOCT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_IA1 register. +// +//***************************************************************************** +#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6. +#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5. +#define MAC_IA1_MACOCT6_S 8 +#define MAC_IA1_MACOCT5_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_TXTH register. +// +//***************************************************************************** +#define MAC_THR_THRESH_M 0x0000003F // Threshold Value. +#define MAC_THR_THRESH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_MCTL register. +// +//***************************************************************************** +#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address. +#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write +#define MAC_MCTL_START 0x00000001 // Start MII Transaction +#define MAC_MCTL_REGADR_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_MDV register. +// +//***************************************************************************** +#define MAC_MDV_DIV_M 0x000000FF // Clock Divider. +#define MAC_MDV_DIV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_MTXD register. +// +//***************************************************************************** +#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data. +#define MAC_MTXD_MDTX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_MRXD register. +// +//***************************************************************************** +#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data. +#define MAC_MRXD_MDRX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_NP register. +// +//***************************************************************************** +#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive + // FIFO. +#define MAC_NP_NPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_TXRQ register. +// +//***************************************************************************** +#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_TS register. +// +//***************************************************************************** +#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic + +//***************************************************************************** +// +// The following are defines for the Ethernet Controller PHY registers. +// +//***************************************************************************** +#define PHY_MR24 0x00000018 // Ethernet PHY Management Register + // 24 -MDI/MDIX Control +#define PHY_MR23 0x00000017 // Ethernet PHY Management Register + // 23 - LED Configuration +#define PHY_MR19 0x00000013 // Ethernet PHY Management Register + // 19 - Transceiver Control +#define PHY_MR18 0x00000012 // Ethernet PHY Management Register + // 18 - Diagnostic +#define PHY_MR17 0x00000011 // Ethernet PHY Management Register + // 17 - Interrupt Control/Status +#define PHY_MR16 0x00000010 // Ethernet PHY Management Register + // 16 - Vendor-Specific +#define PHY_MR6 0x00000006 // Ethernet PHY Management Register + // 6 - Auto-Negotiation Expansion +#define PHY_MR5 0x00000005 // Ethernet PHY Management Register + // 5 - Auto-Negotiation Link + // Partner Base Page Ability +#define PHY_MR4 0x00000004 // Ethernet PHY Management Register + // 4 - Auto-Negotiation + // Advertisement +#define PHY_MR3 0x00000003 // Ethernet PHY Management Register + // 3 - PHY Identifier 2 +#define PHY_MR2 0x00000002 // Ethernet PHY Management Register + // 2 - PHY Identifier 1 +#define PHY_MR1 0x00000001 // Ethernet PHY Management Register + // 1 - Status +#define PHY_MR0 0x00000000 // Ethernet PHY Management Register + // 0 - Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR0 register. +// +//***************************************************************************** +#define PHY_MR0_RESET 0x00008000 // Reset Registers. +#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode. +#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select. +#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable. +#define PHY_MR0_PWRDN 0x00000800 // Power Down. +#define PHY_MR0_ISO 0x00000400 // Isolate. +#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation. +#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode. +#define PHY_MR0_COLT 0x00000080 // Collision Test. + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_O_RIS register. +// +//***************************************************************************** +#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt. +#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete. +#define MAC_RIS_RXER 0x00000010 // Receive Error. +#define MAC_RIS_FOV 0x00000008 // FIFO Overrrun. +#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty. +#define MAC_RIS_TXER 0x00000002 // Transmit Error. +#define MAC_RIS_RXINT 0x00000001 // Packet Received. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR1 register. +// +//***************************************************************************** +#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode. +#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode. +#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode. +#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode. +#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble + // Suppressed. +#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete. +#define PHY_MR1_RFAULT 0x00000010 // Remote Fault. +#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation. +#define PHY_MR1_LINK 0x00000004 // Link Made. +#define PHY_MR1_JAB 0x00000002 // Jabber Condition. +#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR2 register. +// +//***************************************************************************** +#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique + // Identifier[21:6]. +#define PHY_MR2_OUI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR3 register. +// +//***************************************************************************** +#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique + // Identifier[5:0]. +#define PHY_MR3_MN_M 0x000003F0 // Model Number. +#define PHY_MR3_RN_M 0x0000000F // Revision Number. +#define PHY_MR3_OUI_S 10 +#define PHY_MR3_MN_S 4 +#define PHY_MR3_RN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR4 register. +// +//***************************************************************************** +#define PHY_MR4_NP 0x00008000 // Next Page. +#define PHY_MR4_RF 0x00002000 // Remote Fault. +#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3]. +#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2]. +#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1]. +#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0]. +#define PHY_MR4_S_M 0x0000001F // Selector Field. +#define PHY_MR4_S_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR5 register. +// +//***************************************************************************** +#define PHY_MR5_NP 0x00008000 // Next Page. +#define PHY_MR5_ACK 0x00004000 // Acknowledge. +#define PHY_MR5_RF 0x00002000 // Remote Fault. +#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field. +#define PHY_MR5_S_M 0x0000001F // Selector Field. +#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3 +#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T +#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5 +#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394 +#define PHY_MR5_A_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR6 register. +// +//***************************************************************************** +#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault. +#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able. +#define PHY_MR6_PRX 0x00000002 // New Page Received. +#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation + // Able. + +//***************************************************************************** +// +// The following are defines for the bit fields in the MAC_O_DATA register. +// +//***************************************************************************** +#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data. +#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data. +#define MAC_DATA_RXDATA_S 0 +#define MAC_DATA_TXDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR16 register. +// +//***************************************************************************** +#define PHY_MR16_RPTR 0x00008000 // Repeater Mode. +#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity. +#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode. +#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing. +#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode. +#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable. +#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity. +#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass. +#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR17 register. +// +//***************************************************************************** +#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable. +#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable. +#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable. +#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault + // Interrupt Enable. +#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable. +#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt + // Enable. +#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable. +#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete + // Interrupt Enable. +#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt. +#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt. +#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt. +#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault + // Interrupt. +#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt. +#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt. +#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt. +#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete + // Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR18 register. +// +//***************************************************************************** +#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure. +#define PHY_MR18_DPLX 0x00000800 // Duplex Mode. +#define PHY_MR18_RATE 0x00000400 // Rate. +#define PHY_MR18_RXSD 0x00000200 // Receive Detection. +#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR19 register. +// +//***************************************************************************** +#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection. +#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion + // loss +#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion + // loss +#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion + // loss +#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion + // loss + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR23 register. +// +//***************************************************************************** +#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source. +#define PHY_MR23_LED1_LINK 0x00000000 // Link OK +#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1) +#define PHY_MR23_LED1_TX 0x00000020 // TX Activity +#define PHY_MR23_LED1_RX 0x00000030 // RX Activity +#define PHY_MR23_LED1_COL 0x00000040 // Collision +#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode +#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode +#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex +#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX + // Activity +#define PHY_MR23_LED0_M 0x0000000F // LED0 Source. +#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0) +#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity +#define PHY_MR23_LED0_TX 0x00000002 // TX Activity +#define PHY_MR23_LED0_RX 0x00000003 // RX Activity +#define PHY_MR23_LED0_COL 0x00000004 // Collision +#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode +#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode +#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex +#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX + // Activity + +//***************************************************************************** +// +// The following are defines for the bit fields in the PHY_MR24 register. +// +//***************************************************************************** +#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode. +#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable. +#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration. +#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete. +#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed. +#define PHY_MR24_MDIX_SD_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the MAC register offsets in the +// Ethernet Controller. +// +//***************************************************************************** +#define MAC_O_IS 0x00000000 // Interrupt Status Register +#define MAC_O_MADD 0x00000028 // Management Address Register + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the MAC +// registers. +// +//***************************************************************************** +#define MAC_RV_MDV 0x00000080 +#define MAC_RV_IM 0x0000007F +#define MAC_RV_THR 0x0000003F +#define MAC_RV_RCTL 0x00000008 +#define MAC_RV_IA0 0x00000000 +#define MAC_RV_TCTL 0x00000000 +#define MAC_RV_DATA 0x00000000 +#define MAC_RV_MRXD 0x00000000 +#define MAC_RV_TR 0x00000000 +#define MAC_RV_IS 0x00000000 +#define MAC_RV_NP 0x00000000 +#define MAC_RV_MCTL 0x00000000 +#define MAC_RV_MTXD 0x00000000 +#define MAC_RV_IA1 0x00000000 +#define MAC_RV_IACK 0x00000000 +#define MAC_RV_MADD 0x00000000 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_IS +// register. +// +//***************************************************************************** +#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt +#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete +#define MAC_IS_RXER 0x00000010 // RX Error +#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun +#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy +#define MAC_IS_TXER 0x00000002 // TX Error +#define MAC_IS_RXINT 0x00000001 // RX Packet Available + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_IA0 +// register. +// +//***************************************************************************** +#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address +#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address +#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address +#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_IA1 +// register. +// +//***************************************************************************** +#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address +#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_TXTH +// register. +// +//***************************************************************************** +#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_MCTL +// register. +// +//***************************************************************************** +#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_MDV +// register. +// +//***************************************************************************** +#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_MTXD +// register. +// +//***************************************************************************** +#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_MRXD +// register. +// +//***************************************************************************** +#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the MAC_NP +// register. +// +//***************************************************************************** +#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO + +#endif + +#endif // __HW_ETHERNET_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_flash.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_flash.h new file mode 100644 index 0000000..cbb7237 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_flash.h @@ -0,0 +1,296 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following are defines for the FLASH register offsets. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00C // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_RMCTL 0x400FE0F0 // ROM Control +#define FLASH_RMVER 0x400FE0F4 // ROM Version Register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register +#define FLASH_USERDBG 0x400FE1D0 // User Debug +#define FLASH_USERREG0 0x400FE1E0 // User Register 0 +#define FLASH_USERREG1 0x400FE1E4 // User Register 1 +#define FLASH_USERREG2 0x400FE1E8 // User Register 2 +#define FLASH_USERREG3 0x400FE1EC // User Register 3 +#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 +#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 +#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 +#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 +#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 +#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 +#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 +#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_M 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word +#define FLASH_FMC_WRKEY_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt + // Status. +#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask. +#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear. +#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE and +// FLASH_FMPPE registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value. +#define FLASH_USECRL_S 0 + +//***************************************************************************** +// +// The following are defines for the erase size of the FLASH block that is +// erased by an erase operation, and the protect size is the size of the FLASH +// block that is protected by each protection register. +// +//***************************************************************************** +#define FLASH_PROTECT_SIZE 0x00000800 +#define FLASH_ERASE_SIZE 0x00000400 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMA register. +// +//***************************************************************************** +#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset. +#define FLASH_FMA_OFFSET_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMD register. +// +//***************************************************************************** +#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value. +#define FLASH_FMD_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERDBG register. +// +//***************************************************************************** +#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written. +#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data. +#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1. +#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0. +#define FLASH_USERDBG_DATA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG0 register. +// +//***************************************************************************** +#define FLASH_USERREG0_NW 0x80000000 // Not Written. +#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data. +#define FLASH_USERREG0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG1 register. +// +//***************************************************************************** +#define FLASH_USERREG1_NW 0x80000000 // Not Written. +#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data. +#define FLASH_USERREG1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMCTL register. +// +//***************************************************************************** +#define FLASH_RMCTL_BA 0x00000001 // Boot Alias. + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMVER register. +// +//***************************************************************************** +#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents. +#define FLASH_RMVER_CONT_LM 0x00000000 // Boot Loader & DriverLib +#define FLASH_RMVER_SIZE_M 0x00FF0000 // ROM Size. +#define FLASH_RMVER_SIZE_11K 0x00000000 // 11KB Size +#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version. +#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision. +#define FLASH_RMVER_VER_S 8 +#define FLASH_RMVER_REV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG2 register. +// +//***************************************************************************** +#define FLASH_USERREG2_NW 0x80000000 // Not Written. +#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data. +#define FLASH_USERREG2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG3 register. +// +//***************************************************************************** +#define FLASH_USERREG3_NW 0x80000000 // Not Written. +#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data. +#define FLASH_USERREG3_DATA_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_FMC +// register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_FCRIS +// register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_FCIM +// register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_FMIS +// register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the FLASH_USECRL +// register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +#endif + +#endif // __HW_FLASH_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_gpio.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_gpio.h new file mode 100644 index 0000000..3b4d598 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_gpio.h @@ -0,0 +1,136 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO Register offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Interrupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_LOCK 0x00000520 // Lock register. +#define GPIO_O_CR 0x00000524 // Commit register. +#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock. +#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked +#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked +#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register +#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on + // DustDevil-class devices and + // later. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the GPIO Register offsets. +// +//***************************************************************************** +#define GPIO_O_PeriphID4 0x00000FD0 +#define GPIO_O_PeriphID5 0x00000FD4 +#define GPIO_O_PeriphID6 0x00000FD8 +#define GPIO_O_PeriphID7 0x00000FDC +#define GPIO_O_PeriphID0 0x00000FE0 +#define GPIO_O_PeriphID1 0x00000FE4 +#define GPIO_O_PeriphID2 0x00000FE8 +#define GPIO_O_PeriphID3 0x00000FEC +#define GPIO_O_PCellID0 0x00000FF0 +#define GPIO_O_PCellID1 0x00000FF4 +#define GPIO_O_PCellID2 0x00000FF8 +#define GPIO_O_PCellID3 0x00000FFC + +//***************************************************************************** +// +// The following are deprecated defines for the GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_PCellID1 0x000000F0 +#define GPIO_RV_PCellID3 0x000000B1 +#define GPIO_RV_PeriphID0 0x00000061 +#define GPIO_RV_PeriphID1 0x00000010 +#define GPIO_RV_PCellID0 0x0000000D +#define GPIO_RV_PCellID2 0x00000005 +#define GPIO_RV_PeriphID2 0x00000004 +#define GPIO_RV_LOCK 0x00000001 // Lock register RV. +#define GPIO_RV_PeriphID7 0x00000000 +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_PeriphID4 0x00000000 +#define GPIO_RV_PeriphID5 0x00000000 +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_PeriphID6 0x00000000 +#define GPIO_RV_PeriphID3 0x00000000 +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. + +#endif + +#endif // __HW_GPIO_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_hibernate.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_hibernate.h new file mode 100644 index 0000000..4d2c6d1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_hibernate.h @@ -0,0 +1,245 @@ +//***************************************************************************** +// +// hw_hibernate.h - Defines and Macros for the Hibernation module. +// +// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_HIBERNATE_H__ +#define __HW_HIBERNATE_H__ + +//***************************************************************************** +// +// The following are defines for the Hibernation module register addresses. +// +//***************************************************************************** +#define HIB_RTCC 0x400FC000 // Hibernate RTC counter +#define HIB_RTCM0 0x400FC004 // Hibernate RTC match 0 +#define HIB_RTCM1 0x400FC008 // Hibernate RTC match 1 +#define HIB_RTCLD 0x400FC00C // Hibernate RTC load +#define HIB_CTL 0x400FC010 // Hibernate RTC control +#define HIB_IM 0x400FC014 // Hibernate interrupt mask +#define HIB_RIS 0x400FC018 // Hibernate raw interrupt status +#define HIB_MIS 0x400FC01C // Hibernate masked interrupt stat +#define HIB_IC 0x400FC020 // Hibernate interrupt clear +#define HIB_RTCT 0x400FC024 // Hibernate RTC trim +#define HIB_DATA 0x400FC030 // Hibernate data area + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC counter +// register. +// +//***************************************************************************** +#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter. +#define HIB_RTCC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC match 0 +// register. +// +//***************************************************************************** +#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0. +#define HIB_RTCM0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC match 1 +// register. +// +//***************************************************************************** +#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1. +#define HIB_RTCM1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC load +// register. +// +//***************************************************************************** +#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load. +#define HIB_RTCLD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate control +// register +// +//***************************************************************************** +#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable. +#define HIB_CTL_VABORT 0x00000080 // low bat abort +#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator +#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect +#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin +#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match +#define HIB_CTL_CLKSEL 0x00000004 // clock input selection +#define HIB_CTL_HIBREQ 0x00000002 // request hibernation +#define HIB_CTL_RTCEN 0x00000001 // RTC enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate interrupt mask +// reg. +// +//***************************************************************************** +#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt +#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate raw interrupt +// status. +// +//***************************************************************************** +#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt +#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate masked int +// status. +// +//***************************************************************************** +#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt +#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt + // Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate interrupt +// clear reg. +// +//***************************************************************************** +#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt +#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate RTC trim +// register. +// +//***************************************************************************** +#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value. +#define HIB_RTCT_TRIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the Hibernate data register. +// +//***************************************************************************** +#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV + // Registers[63:0]. +#define HIB_DATA_RTD_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the Hibernation module register +// addresses. +// +//***************************************************************************** +#define HIB_DATA_END 0x400FC130 // end of data area, exclusive + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// counter register. +// +//***************************************************************************** +#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// match 0 register. +// +//***************************************************************************** +#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// match 1 register. +// +//***************************************************************************** +#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// load register. +// +//***************************************************************************** +#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate raw +// interrupt status. +// +//***************************************************************************** +#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate +// masked int status. +// +//***************************************************************************** +#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate RTC +// trim register. +// +//***************************************************************************** +#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the Hibernate +// data register. +// +//***************************************************************************** +#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask + +#endif + +#endif // __HW_HIBERNATE_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_i2c.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_i2c.h new file mode 100644 index 0000000..2fa3623 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_i2c.h @@ -0,0 +1,413 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the offsets between the I2C master and slave +// registers. +// +//***************************************************************************** +#define I2C_O_MSA 0x00000000 // I2C Master Slave Address +#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address +#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status +#define I2C_O_MCS 0x00000004 // I2C Master Control/Status +#define I2C_O_SDR 0x00000008 // I2C Slave Data +#define I2C_O_MDR 0x00000008 // I2C Master Data +#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period +#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask +#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status +#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask +#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status +#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt + // Status +#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear +#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt + // Status +#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear +#define I2C_O_MCR 0x00000020 // I2C Master Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address. +#define I2C_MSA_RS 0x00000001 // Receive not Send +#define I2C_MSA_SA_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address. +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +#define I2C_SCSR_FBR 0x00000004 // First Byte Received. +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request. +#define I2C_SCSR_DA 0x00000001 // Device Active. +#define I2C_SCSR_RREQ 0x00000001 // Receive Request. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy. +#define I2C_MCS_IDLE 0x00000020 // I2C Idle. +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost. +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable. +#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data. +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address. +#define I2C_MCS_STOP 0x00000004 // Generate STOP. +#define I2C_MCS_START 0x00000002 // Generate START. +#define I2C_MCS_ERROR 0x00000002 // Error. +#define I2C_MCS_RUN 0x00000001 // I2C Master Enable. +#define I2C_MCS_BUSY 0x00000001 // I2C Busy. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer. +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // Data Transferred. +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period. +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask. +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask. +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status. +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status. +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +#define I2C_MIMR_IM 0x00000001 // Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status. +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status. +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear. +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear. +#define I2C_SICR_DATAIC 0x00000001 // Data Clear Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +#define I2C_MICR_IC 0x00000001 // Interrupt Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable. +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable. +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the offsets between the I2C master +// and slave registers. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following are deprecated defines for the I2C master register offsets. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following are deprecated defines for the I2C slave register offsets. +// +//***************************************************************************** +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C master +// slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Control and Status register. +// +//***************************************************************************** +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ERR_MASK 0x0000001C +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run + +//***************************************************************************** +// +// The following are deprecated defines for the values used in determining the +// contents of the I2C Master Timer Period register. +// +//***************************************************************************** +#define I2C_SCL_FAST 400000 // SCL fast frequency +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Interrupt Mask register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Raw Interrupt Status register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Masked Interrupt Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Interrupt Clear register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Master +// Configuration register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave Own +// Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Control/Status register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Interrupt Mask register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave Raw +// Interrupt Status register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Masked Interrupt Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C Slave +// Interrupt Clear register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SIMR +// register. +// +//***************************************************************************** +#define I2C_SIMR_IM 0x00000001 // Interrupt Mask. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SRIS +// register. +// +//***************************************************************************** +#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SMIS +// register. +// +//***************************************************************************** +#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status. + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the I2C_O_SICR +// register. +// +//***************************************************************************** +#define I2C_SICR_IC 0x00000001 // Clear Interrupt. + +#endif + +#endif // __HW_I2C_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_ints.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_ints.h new file mode 100644 index 0000000..238a51a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_ints.h @@ -0,0 +1,134 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI0 23 // SSI0 Rx and Tx +#define INT_I2C0 24 // I2C0 Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI0 29 // Quadrature Encoder 0 +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control +#define INT_GPIOF 46 // GPIO Port F +#define INT_GPIOG 47 // GPIO Port G +#define INT_GPIOH 48 // GPIO Port H +#define INT_UART2 49 // UART2 Rx and Tx +#define INT_SSI1 50 // SSI1 Rx and Tx +#define INT_TIMER3A 51 // Timer 3 subtimer A +#define INT_TIMER3B 52 // Timer 3 subtimer B +#define INT_I2C1 53 // I2C1 Master and Slave +#define INT_QEI1 54 // Quadrature Encoder 1 +#define INT_CAN0 55 // CAN0 +#define INT_CAN1 56 // CAN1 +#define INT_CAN2 57 // CAN2 +#define INT_ETH 58 // Ethernet +#define INT_HIBERNATE 59 // Hibernation module +#define INT_USB0 60 // USB 0 Controller +#define INT_PWM3 61 // PWM Generator 3 +#define INT_UDMA 62 // uDMA controller +#define INT_UDMAERR 63 // uDMA Error + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 64 + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_QEI 29 // Quadrature Encoder + +#endif + +#endif // __HW_INTS_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_memmap.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_memmap.h new file mode 100644 index 0000000..1f5e7db --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_memmap.h @@ -0,0 +1,111 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI0_BASE 0x40008000 // SSI0 +#define SSI1_BASE 0x40009000 // SSI1 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define UART2_BASE 0x4000E000 // UART2 +#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master +#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave +#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master +#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F +#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G +#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H +#define PWM_BASE 0x40028000 // PWM +#define QEI0_BASE 0x4002C000 // QEI0 +#define QEI1_BASE 0x4002D000 // QEI1 +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define TIMER3_BASE 0x40033000 // Timer3 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define CAN0_BASE 0x40040000 // CAN0 +#define CAN1_BASE 0x40041000 // CAN1 +#define CAN2_BASE 0x40042000 // CAN2 +#define ETH_BASE 0x40048000 // Ethernet +#define MAC_BASE 0x40048000 // Ethernet +#define USB0_BASE 0x40050000 // USB 0 Controller +#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) +#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) +#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) +#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) +#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) +#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) +#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) +#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) +#define HIB_BASE 0x400FC000 // Hibernation Module +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define UDMA_BASE 0x400FF000 // uDMA Controller +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the base address of the memories +// and peripherals. +// +//***************************************************************************** +#define SSI_BASE 0x40008000 // SSI +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define QEI_BASE 0x4002C000 // QEI + +#endif + +#endif // __HW_MEMMAP_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_nvic.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_nvic.h new file mode 100644 index 0000000..10b7ffc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_nvic.h @@ -0,0 +1,1024 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register +#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register +#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register +#define NVIC_PRI11 0xE000E42C // IRQ 44 to 47 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable +#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable +#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable +#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable +#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable +#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable +#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable +#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend +#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend +#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend +#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend +#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend +#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend +#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active +#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active +#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active +#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask +#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask +#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask +#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask +#define NVIC_PRI8_INT35_S 24 +#define NVIC_PRI8_INT34_S 16 +#define NVIC_PRI8_INT33_S 8 +#define NVIC_PRI8_INT32_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask +#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask +#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask +#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask +#define NVIC_PRI9_INT39_S 24 +#define NVIC_PRI9_INT38_S 16 +#define NVIC_PRI9_INT37_S 8 +#define NVIC_PRI9_INT36_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask +#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask +#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask +#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask +#define NVIC_PRI10_INT43_S 24 +#define NVIC_PRI10_INT42_S 16 +#define NVIC_PRI10_INT41_S 8 +#define NVIC_PRI10_INT40_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask +#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_pwm.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_pwm.h new file mode 100644 index 0000000..59d93d1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_pwm.h @@ -0,0 +1,677 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// The following are defines for the PWM Module Register offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register +#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value +#define PWM_O_0_CTL 0x00000040 // PWM0 Control +#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger + // Enable +#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status +#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear +#define PWM_O_0_LOAD 0x00000050 // PWM0 Load +#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter +#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A +#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B +#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control +#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control +#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control +#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay +#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band + // Falling-Edge-Delay +#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 +#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period +#define PWM_O_1_CTL 0x00000080 // PWM1 Control +#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt Enable +#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status +#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear +#define PWM_O_1_LOAD 0x00000090 // PWM1 Load +#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter +#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A +#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B +#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control +#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control +#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control +#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay +#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band + // Falling-Edge-Delay +#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 +#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period +#define PWM_O_2_CTL 0x000000C0 // PWM2 Control +#define PWM_O_2_INTEN 0x000000C4 // PWM2 InterruptEnable +#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status +#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear +#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load +#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter +#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A +#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B +#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control +#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control +#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control +#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay +#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band + // Falling-Edge-Delay +#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 +#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period +#define PWM_O_3_CTL 0x00000100 // PWM3 Control +#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger + // Enable +#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status +#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear +#define PWM_O_3_LOAD 0x00000110 // PWM3 Load +#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter +#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A +#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B +#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control +#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control +#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control +#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay +#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band + // Falling-Edge-Delay +#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 +#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period +#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense +#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 +#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense +#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 +#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense +#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 +#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense +#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Master Control +// register. +// +//***************************************************************************** +#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3. +#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2. +#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1. +#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Time Base Sync +// register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC3 0x00000008 // Reset generator 3 counter +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Output Enable +// register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 pin enable +#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 pin enable +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM7INV 0x00000080 // PWM7 pin invert +#define PWM_INVERT_PWM6INV 0x00000040 // PWM6 pin invert +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT7 0x00000080 // PWM7 pin fault +#define PWM_FAULT_FAULT6 0x00000040 // PWM6 pin fault +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM4 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM3 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM2 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM1 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM0 pin fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT3 0x00000008 // Fault3 Interrupt Status. +#define PWM_STATUS_FAULT2 0x00000004 // Fault2 Interrupt Status. +#define PWM_STATUS_FAULT1 0x00000002 // Fault1 Interrupt Status. +#define PWM_STATUS_FAULT0 0x00000001 // Fault0 Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg +#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition +#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base +#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base + +//***************************************************************************** +// +// The following are defines for the PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input. +#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum fault period enabled +#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source. +#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for + // the PWMnDBFALL register. +#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode. +#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode. +#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode. +#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode. +#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block + +//***************************************************************************** +// +// The following are defines for the PWM Generator extended offsets. +// +//***************************************************************************** +#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense +#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status +#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base +#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base +#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base +#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base + +//***************************************************************************** +// +// The following are defines for the PWM_X Interrupt/Trigger Enable Register +// bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 + +//***************************************************************************** +// +// The following are defines for the PWM_X Raw Interrupt Status Register bit +// definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INTEN register. +// +//***************************************************************************** +#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3. +#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2. +#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1. +#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable. +#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0. +#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable. +#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable. +#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable. +#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_RIS register. +// +//***************************************************************************** +#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3. +#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2. +#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1. +#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0. +#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted. +#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted. +#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted. +#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted. +#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ISC register. +// +//***************************************************************************** +#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted. +#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted. +#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted. +#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted. +#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted. +#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status. +#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status. +#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status. +#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_ISC register. +// +//***************************************************************************** +#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt. +#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt. +#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt. +#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt. +#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt. +#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_LOAD register. +// +//***************************************************************************** +#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value. +#define PWM_X_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_COUNT register. +// +//***************************************************************************** +#define PWM_X_COUNT_M 0x0000FFFF // Counter Value. +#define PWM_X_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPA register. +// +//***************************************************************************** +#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value. +#define PWM_X_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPB register. +// +//***************************************************************************** +#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value. +#define PWM_X_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENA register. +// +//***************************************************************************** +#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down. +#define PWM_X_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal. +#define PWM_X_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0. +#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1. +#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up. +#define PWM_X_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal. +#define PWM_X_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0. +#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1. +#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down. +#define PWM_X_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal. +#define PWM_X_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0. +#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1. +#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up. +#define PWM_X_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal. +#define PWM_X_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0. +#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1. +#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load. +#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal. +#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0. +#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1. +#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0. +#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing. +#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal. +#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0. +#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENB register. +// +//***************************************************************************** +#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down. +#define PWM_X_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal. +#define PWM_X_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Set the output signal to 0. +#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1. +#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up. +#define PWM_X_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal. +#define PWM_X_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Set the output signal to 0. +#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1. +#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down. +#define PWM_X_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal. +#define PWM_X_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Set the output signal to 0. +#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1. +#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up. +#define PWM_X_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal. +#define PWM_X_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Set the output signal to 0. +#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1. +#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load. +#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal. +#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0. +#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1. +#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0. +#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing. +#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal. +#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0. +#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBCTL register. +// +//***************************************************************************** +#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBRISE register. +// +//***************************************************************************** +#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay. +#define PWM_X_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBFALL register. +// +//***************************************************************************** +#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay. +#define PWM_X_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULTVAL register. +// +//***************************************************************************** +#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value. +#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value. +#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value. +#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value. +#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value. +#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value. +#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value. +#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period. +#define PWM_X_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSEN register. +// +//***************************************************************************** +#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense. +#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense. +#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense. +#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3. +#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2. +#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1. +#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0. + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3. +#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2. +#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1. +#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the PWM Master +// Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following are deprecated defines for the PWM Interrupt Register bit +// definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the PWM Status +// register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Interrupt Status Register +// bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Generator A/B Control +// Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Generator A/B Control +// Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one +#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero +#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal +#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action + +//***************************************************************************** +// +// The following are deprecated defines for the PWM_X Dead Band Control +// Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// The following are deprecated defines for the PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output + // pins +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output + // pins +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_X_COUNT 0x00000000 // The current counter value + +#endif + +#endif // __HW_PWM_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_qei.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_qei.h new file mode 100644 index 0000000..386fe0b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_qei.h @@ -0,0 +1,199 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following are defines for the QEI register offsets. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // Configuration and control reg. +#define QEI_O_STAT 0x00000004 // Status register +#define QEI_O_POS 0x00000008 // Current position register +#define QEI_O_MAXPOS 0x0000000C // Maximum position register +#define QEI_O_LOAD 0x00000010 // Velocity timer load register +#define QEI_O_TIME 0x00000014 // Velocity timer register +#define QEI_O_COUNT 0x00000018 // Velocity pulse count register +#define QEI_O_SPEED 0x0000001C // Velocity speed register +#define QEI_O_INTEN 0x00000020 // Interrupt enable register +#define QEI_O_RIS 0x00000024 // Raw interrupt status register +#define QEI_O_ISC 0x00000028 // Interrupt status register + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_CTL register. +// +//***************************************************************************** +#define QEI_CTL_STALLEN 0x00001000 // Stall enable +#define QEI_CTL_INVI 0x00000800 // Invert Index input +#define QEI_CTL_INVB 0x00000400 // Invert PhB input +#define QEI_CTL_INVA 0x00000200 // Invert PhA input +#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask +#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 +#define QEI_CTL_VELEN 0x00000020 // Velocity enable +#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode +#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode +#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode +#define QEI_CTL_SWAP 0x00000002 // Swap input signals +#define QEI_CTL_ENABLE 0x00000001 // QEI enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation +#define QEI_STAT_ERROR 0x00000001 // Signalling error detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current encoder position +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase error detected +#define QEI_INTEN_DIR 0x00000004 // Direction change +#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired +#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase error detected +#define QEI_RIS_DIR 0x00000004 // Direction change +#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired +#define QEI_RIS_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_ISC register. +// +//***************************************************************************** +#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt. +#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt. +#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired + // Interrupt. +#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the QEI_ISC +// register. +// +//***************************************************************************** +#define QEI_INT_ERROR 0x00000008 // Phase error detected +#define QEI_INT_DIR 0x00000004 // Direction change +#define QEI_INT_TIMER 0x00000002 // Velocity timer expired +#define QEI_INT_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following are deprecated defines for the reset values for the QEI +// registers. +// +//***************************************************************************** +#define QEI_RV_POS 0x00000000 // Current position register +#define QEI_RV_LOAD 0x00000000 // Velocity timer load register +#define QEI_RV_CTL 0x00000000 // Configuration and control reg. +#define QEI_RV_RIS 0x00000000 // Raw interrupt status register +#define QEI_RV_ISC 0x00000000 // Interrupt status register +#define QEI_RV_SPEED 0x00000000 // Velocity speed register +#define QEI_RV_INTEN 0x00000000 // Interrupt enable register +#define QEI_RV_STAT 0x00000000 // Status register +#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register +#define QEI_RV_MAXPOS 0x00000000 // Maximum position register +#define QEI_RV_TIME 0x00000000 // Velocity timer register + +#endif + +#endif // __HW_QEI_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_ssi.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_ssi.h new file mode 100644 index 0000000..f10fc55 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_ssi.h @@ -0,0 +1,220 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following are defines for the SSI register offsets. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register +#define SSI_O_DMACTL 0x00000024 // SSI DMA Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate. +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_M 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select. +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data +#define SSI_CR0_SCR_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI clock prescale +// register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor. +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data. +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt + // Mask. +#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask. +#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt + // Mask. +#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt + // Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt + // Status. +#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt + // Status. +#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw + // Interrupt Status. +#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw + // Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked + // Interrupt Status. +#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked + // Interrupt Status. +#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked + // Interrupt Status. +#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked + // Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt + // Clear. +#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt + // Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable. +#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SSI Control +// register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_DSS 0x0000000F // Data size select + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SSI clock +// prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following are deprecated defines for the SSI controller's FIFO size. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the interrupt +// mask set and clear, raw interrupt, masked interrupt, and interrupt clear +// registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif + +#endif // __HW_SSI_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_sysctl.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_sysctl.h new file mode 100644 index 0000000..5d9877b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_sysctl.h @@ -0,0 +1,1334 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following are defines for the system control register addresses. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400FE000 // Device identification register 0 +#define SYSCTL_DID1 0x400FE004 // Device identification register 1 +#define SYSCTL_DC0 0x400FE008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400FE010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400FE014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400FE018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400FE01C // Device capabilities register 4 +#define SYSCTL_DC5 0x400FE020 // Device capabilities register 5 +#define SYSCTL_DC6 0x400FE024 // Device capabilities register 6 +#define SYSCTL_DC7 0x400FE028 // Device capabilities register 7 +#define SYSCTL_PBORCTL 0x400FE030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400FE034 // LDO power control register +#define SYSCTL_SRCR0 0x400FE040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400FE044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400FE048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400FE050 // Raw interrupt status register +#define SYSCTL_IMC 0x400FE054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400FE058 // Interrupt status register +#define SYSCTL_RESC 0x400FE05C // Reset cause register +#define SYSCTL_RCC 0x400FE060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400FE064 // PLL configuration register +#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High Speed Control +#define SYSCTL_RCC2 0x400FE070 // Run-mode clock config register 2 +#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control +#define SYSCTL_RCGC0 0x400FE100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400FE104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400FE108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400FE110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400FE114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400FE118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400FE124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep-mode clock config reg +#define SYSCTL_CLKVCLR 0x400FE150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400FE160 // LDO reset control register + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_M 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 +#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_SANDSTORM \ + 0x00000000 // Sandstorm-class Device +#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device +#define SYSCTL_DID0_CLASS_DUSTDEVIL \ + 0x00030000 // DustDevil-class Device +#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) +#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer + // revision) +#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer + // revision) +#define SYSCTL_DID0_MIN_M 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 +#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 +#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 +#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 +#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version. +#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format + // definition, indicating a + // Stellaris LM3Snnn device. +#define SYSCTL_DID1_VER_1 0x10000000 // First revision of the DID1 + // register format, indicating a + // Stellaris Fury-class device. +#define SYSCTL_DID1_FAM_M 0x0F000000 // Family. +#define SYSCTL_DID1_FAM_STELLARIS \ + 0x00000000 // Stellaris family of + // microcontollers, that is, all + // devices with external part + // numbers starting with LM3S. +#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 +#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 +#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110 +#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133 +#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138 +#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150 +#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162 +#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165 +#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332 +#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435 +#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439 +#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512 +#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538 +#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601 +#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607 +#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608 +#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620 +#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625 +#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626 +#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627 +#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635 +#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637 +#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751 +#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776 +#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850 +#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911 +#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918 +#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937 +#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958 +#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960 +#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968 +#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 +#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 +#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276 +#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 +#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 +#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 +#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 +#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601 +#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608 +#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616 +#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 +#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 +#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 +#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671 +#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678 +#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 +#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 +#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776 +#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911 +#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918 +#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 +#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 +#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 +#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 +#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651 +#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739 +#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748 +#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749 +#define SYSCTL_DID1_PRTNO_3759 0x00460000 // LM3S3759 +#define SYSCTL_DID1_PRTNO_3768 0x00480000 // LM3S3768 +#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632 +#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652 +#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662 +#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732 +#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737 +#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739 +#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747 +#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749 +#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752 +#define SYSCTL_DID1_PRTNO_5757 0x009B0000 // LM3S5757 +#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762 +#define SYSCTL_DID1_PRTNO_5767 0x009D0000 // LM3S5767 +#define SYSCTL_DID1_PRTNO_5768 0x00A90000 // LM3S5768 +#define SYSCTL_DID1_PRTNO_5769 0x00A80000 // LM3S5769 +#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 +#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 +#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 +#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 +#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 +#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537 +#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 +#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611 +#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618 +#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 +#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 +#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 +#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753 +#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911 +#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918 +#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 +#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950 +#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 +#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 +#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530 +#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538 +#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630 +#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730 +#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733 +#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738 +#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930 +#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933 +#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938 +#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962 +#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970 +#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971 +#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count. +#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package +#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48 pin package +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package +#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64 pin package +#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C + // to 105C) +#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type. +#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_S 16 // Part number shift + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash +#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift +#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider. +#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock + // with a PLL divider of 4. +#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a + // PLL divider of 8. +#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a + // PLL divider of 10. +#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex-M3 MPU present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present. +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C1 0x00004000 // I2C 1 present +#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present +#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present +#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present +#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Pin Present. +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present. +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present +#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present. +#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present. +#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable. +#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present. +#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present. +#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA is present. +#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM is present. +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay. +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BORTIM_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage. +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset. +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset. +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor. +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider. +#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor. +#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable. +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // Using a 1MHz crystal +#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // Using a 1.8432MHz crystal +#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // Using a 2MHz crystal +#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // Using a 2.4576MHz crystal +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10.0 MHz (USB) +#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12.0 MHz (USB) +#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz +#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz +#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz +#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16.0 MHz (USB) +#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 KHz internal oscillator +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_S 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_M 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value. +#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value. +#define SYSCTL_PLLCFG_F_S 5 +#define SYSCTL_PLLCFG_R_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System clock divider +#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 +#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 +#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 +#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 +#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 +#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 +#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 +#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 +#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 +#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 +#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 +#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 +#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 +#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 +#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 +#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 +#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 +#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 +#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 +#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 +#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 +#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 +#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 +#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 +#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 +#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 +#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 +#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 +#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 +#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 +#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 +#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 +#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 +#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 +#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 +#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 +#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 +#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 +#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 +#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 +#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 +#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 +#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 +#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 +#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 +#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 +#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 +#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 +#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 +#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 +#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 +#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 +#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 +#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 +#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 +#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 +#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 +#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 +#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 +#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 +#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 +#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 +#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 +#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL. +#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass +#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // System Clock Source. +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. +#define SYSCTL_RCC2_SYSDIV2_S 23 // Shift to the SYSDIV2 field + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override. +#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 +#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 +#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 +#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 +#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 +#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 +#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 +#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 +#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 +#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 +#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 +#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 +#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 +#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 +#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 +#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 +#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 +#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 +#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 +#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 +#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 +#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 +#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 +#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 +#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 +#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 +#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 +#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 +#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 +#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 +#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 +#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 +#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 +#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 +#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 +#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 +#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 +#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 +#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 +#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 +#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 +#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 +#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 +#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 +#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 +#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 +#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 +#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 +#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 +#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 +#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 +#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 +#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 +#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 +#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 +#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 +#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 +#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 +#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 +#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 +#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 +#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 +#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 +#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source. +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. +#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source. +#define SYSCTL_DSLPCLKCFG_D_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control. +#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control. +#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control. +#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control. +#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control. +#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control. +#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control. +#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control. +#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control. +#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control. +#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control. +#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control. +#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control. +#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control. +#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control. +#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control. +#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control. +#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control. +#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control. +#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control. +#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control. +#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control. +#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control. +#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control. +#define SYSCTL_SRCR2_UDMA 0x00002000 // UDMA Reset Control. +#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control. +#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control. +#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control. +#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control. +#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control. +#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control. +#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control. +#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt + // Status. +#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt + // Status. +#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status. +#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt + // Status. +#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw + // Interrupt Status. +#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw + // Interrupt Status. +#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw + // Interrupt Status. +#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt + // Status. +#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask. +#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask. +#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask. +#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask. +#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault + // Interrupt Mask. +#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt + // Mask. +#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt + // Mask. +#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask. +#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt + // Status. +#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt + // Status. +#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt + // Status. +#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt + // Status. +#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked + // Interrupt Status. +#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked + // Interrupt Status. +#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked + // Interrupt Status. +#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control. +#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control. +#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control. +#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control. +#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control. +#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed. +#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control. +#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock + // Gating. +#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock + // Gating. +#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock + // Gating. +#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control. +#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control. +#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control. +#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control. +#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control. +#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control. +#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control. +#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control. +#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control. +#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control. +#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control. +#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control. +#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control. +#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control. +#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control. +#define SYSCTL_RCGC2_UDMA 0x00002000 // UDMA Clock Gating Control. +#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control. +#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control. +#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control. +#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control. +#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control. +#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control. +#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control. +#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control. +#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control. +#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control. +#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control. +#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control. +#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed. +#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second +#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second +#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second +#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second +#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control. +#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock + // Gating. +#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock + // Gating. +#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock + // Gating. +#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control. +#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control. +#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control. +#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control. +#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control. +#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control. +#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control. +#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control. +#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control. +#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control. +#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control. +#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control. +#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control. +#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control. +#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control. +#define SYSCTL_SCGC2_UDMA 0x00002000 // UDMA Clock Gating Control. +#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control. +#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control. +#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control. +#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control. +#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control. +#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control. +#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control. +#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control. +#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control. +#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control. +#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control. +#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control. +#define SYSCTL_DCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed. +#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second +#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second +#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second +#define SYSCTL_DCGC0_ADCSPD1M 0x00000300 // 1M samples/second +#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control. +#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock + // Gating. +#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock + // Gating. +#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock + // Gating. +#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control. +#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control. +#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control. +#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control. +#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control. +#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control. +#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control. +#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control. +#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control. +#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control. +#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control. +#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control. +#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control. +#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control. +#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control. +#define SYSCTL_DCGC2_UDMA 0x00002000 // UDMA Clock Gating Control. +#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control. +#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control. +#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control. +#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control. +#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control. +#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control. +#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control. +#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present. +#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present. +#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present. +#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present. +#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault feature is + // active. +#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC feature is + // active. +#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present. +#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present. +#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present. +#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present. +#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present. +#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present. +#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present. +#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +#define SYSCTL_DC6_USB0_M 0x00000003 // This specifies that USB0 is + // present and its capability. +#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is DEVICE or HOST +#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB is OTG + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed. +#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed. +#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed. +#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed. +#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed. +#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed. +#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed. +#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25. +#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24. +#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23. +#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22. +#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11. +#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10. +#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9. +#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8. +#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5. +#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4. +#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3. +#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2. +#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1. +#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the system control register +// addresses. +// +//***************************************************************************** +#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0 +#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DID0 +// register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DID1 +// register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC0 +// register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC1 +// register. +// +//***************************************************************************** +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC2 +// register. +// +//***************************************************************************** +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DC3 +// register. +// +//***************************************************************************** +#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0, +// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module +#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module +#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1, +// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 +#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 +#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 +#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2, +// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_ETH 0x50000000 // ETH module +#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module +#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module +#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RIS, +// SYSCTL_IMC, and SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RESC +// register. +// +//***************************************************************************** +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RCC +// register. +// +//***************************************************************************** +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG +// register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RCC2 +// register. +// +//***************************************************************************** +#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider +#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_DSLPCLKCFG register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override +#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif + +#endif // __HW_SYSCTL_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_timer.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_timer.h new file mode 100644 index 0000000..2036d54 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_timer.h @@ -0,0 +1,407 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following are defines for the timer register offsets. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration. +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode. +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode. +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load + // Register High. +#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load + // Register Low. +#define TIMER_TAILR_TAILRH_S 16 +#define TIMER_TAILR_TAILRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load + // Register. +#define TIMER_TBILR_TBILRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High. +#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low. +#define TIMER_TAMATCHR_TAMRH_S 16 +#define TIMER_TAMATCHR_TAMRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low. +#define TIMER_TBMATCHR_TBMRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High. +#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low. +#define TIMER_TAR_TARH_S 16 +#define TIMER_TAR_TARL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB. +#define TIMER_TBR_TBRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode + // Select. +#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode. +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode. +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode. +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode. +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode + // Select. +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode. +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode. +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode. +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode. +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked + // Interrupt. +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked + // Interrupt. +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked + // Interrupt. +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt. +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked + // Interrupt. +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked + // Interrupt. +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked + // Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale. +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale. +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match. +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match. +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the timer +// registers. +// +//***************************************************************************** +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_CFG +// register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnMR +// register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_CTL +// register. +// +//***************************************************************************** +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_MIS +// register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TAILR +// register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TBILR +// register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPR +// register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPMR +// register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TAR +// register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TBR +// register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif + +#endif // __HW_TIMER_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_types.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_types.h new file mode 100644 index 0000000..11da8e4 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_types.h @@ -0,0 +1,153 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +//***************************************************************************** +// +// Helper Macros for determining silicon revisions, etc. +// +// These macros will be used by Driverlib at "run-time" to create necessary +// conditional code blocks that will allow a single version of the Driverlib +// "binary" code to support multiple(all) Stellaris silicon revisions. +// +// It is expected that these macros will be used inside of a standard 'C' +// conditional block of code, e.g. +// +// if(CLASS_IS_SANDSTORM) +// { +// do some Sandstorm-class specific code here. +// } +// +// By default, these macros will be defined as run-time checks of the +// appropriate register(s) to allow creation of run-time conditional code +// blocks for a common DriverLib across the entire Stellaris family. +// +// However, if code-space optimization is required, these macros can be "hard- +// coded" for a specific version of Stellaris silicon. Many compilers will +// then detect the "hard-coded" conditionals, and appropriately optimize the +// code blocks, eliminating any "unreachable" code. This would result in +// a smaller Driverlib, thus producing a smaller final application size, but +// at the cost of limiting the Driverlib binary to a specific Stellaris +// silicon revision. +// +//***************************************************************************** +#ifndef CLASS_IS_SANDSTORM +#define CLASS_IS_SANDSTORM \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM))) +#endif + +#ifndef CLASS_IS_FURY +#define CLASS_IS_FURY \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY)) +#endif + +#ifndef CLASS_IS_DUSTDEVIL +#define CLASS_IS_DUSTDEVIL \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL)) +#endif + +#ifndef REVISION_IS_A0 +#define REVISION_IS_A0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A2 +#define REVISION_IS_A2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_C1 +#define REVISION_IS_C1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1)) +#endif + +#ifndef REVISION_IS_C2 +#define REVISION_IS_C2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2)) +#endif + +//***************************************************************************** +// +// Deprecated silicon class and revision detection macros. +// +//***************************************************************************** +#ifndef DEPRECATED +#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM +#define DEVICE_IS_FURY CLASS_IS_FURY +#define DEVICE_IS_REVA2 REVISION_IS_A2 +#define DEVICE_IS_REVC1 REVISION_IS_C1 +#define DEVICE_IS_REVC2 REVISION_IS_C2 +#endif + +#endif // __HW_TYPES_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_uart.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_uart.h new file mode 100644 index 0000000..3c67a55 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_uart.h @@ -0,0 +1,341 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the UART Register offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCRH 0x0000002C // UART Line Control +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_DMACTL 0x00000048 // UART DMA Control + +//***************************************************************************** +// +// The following are defines for the Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received. +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// The following are defines for the Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// The following are defines for the Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor. +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// The following are defines for the Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor. +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// The following are defines for the Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable +#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// The following are defines for the Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // RX FIFO Level Interrupt Mask +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full +#define UART_IFLS_TX_M 0x00000007 // TX FIFO Level Interrupt Mask +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// The following are defines for the Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// The following are defines for the Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// The following are defines for the Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear. +#define UART_ECR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select. +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length. +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs. +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select. +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select. +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable. +#define UART_LCRH_BRK 0x00000001 // UART Send Break. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor. +#define UART_ILPR_ILPDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error. +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable. +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the UART Register offsets. +// +//***************************************************************************** +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_PeriphID4 0x00000FD0 +#define UART_O_PeriphID5 0x00000FD4 +#define UART_O_PeriphID6 0x00000FD8 +#define UART_O_PeriphID7 0x00000FDC +#define UART_O_PeriphID0 0x00000FE0 +#define UART_O_PeriphID1 0x00000FE4 +#define UART_O_PeriphID2 0x00000FE8 +#define UART_O_PeriphID3 0x00000FEC +#define UART_O_PCellID0 0x00000FF0 +#define UART_O_PCellID1 0x00000FF4 +#define UART_O_PCellID2 0x00000FF8 +#define UART_O_PCellID3 0x00000FFC + +//***************************************************************************** +// +// The following are deprecated defines for the Data Register bits +// +//***************************************************************************** +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// The following are deprecated defines for the Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// The following are deprecated defines for the Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// The following are deprecated defines for the Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// The following are deprecated defines for the Interrupt FIFO Level Select +// Register bits +// +//***************************************************************************** +#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask +#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask + +//***************************************************************************** +// +// The following are deprecated defines for the Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// The following are deprecated defines for the Reset Values for UART +// Registers. +// +//***************************************************************************** +#define UART_RV_CTL 0x00000300 +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID3 0x000000B1 +#define UART_RV_FR 0x00000090 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_IM 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_IBRD 0x00000000 + +#endif + +#endif // __HW_UART_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_udma.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_udma.h new file mode 100644 index 0000000..46dab8b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_udma.h @@ -0,0 +1,312 @@ +//***************************************************************************** +// +// hw_udma.h - Macros for use in accessing the UDMA registers. +// +// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// The following are defines for the Micro Direct Memory Access (uDMA) offsets. +// +//***************************************************************************** +#define UDMA_STAT 0x400FF000 // DMA Status +#define UDMA_CFG 0x400FF004 // DMA Configuration +#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer +#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control + // Base Pointer +#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait on Request + // Status +#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request +#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set +#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear +#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set +#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear +#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set +#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear +#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate + // Set +#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate + // Clear +#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set +#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear +#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear + +//***************************************************************************** +// +// Micro Direct Memory Access (uDMA) offsets. +// +//***************************************************************************** +#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer. +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_STAT register. +// +//***************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available DMA Channels Minus 1. +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine State. +#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle +#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data +#define UDMA_STAT_STATE_RD_SRCENDP \ + 0x00000020 // Reading source end pointer +#define UDMA_STAT_STATE_RD_DSTENDP \ + 0x00000030 // Reading destination end pointer +#define UDMA_STAT_STATE_RD_SRCDAT \ + 0x00000040 // Reading source data +#define UDMA_STAT_STATE_WR_DSTDAT \ + 0x00000050 // Writing destination data +#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for DMA request to clear +#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data +#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled +#define UDMA_STAT_STATE_DONE 0x00000090 // Done +#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable. +#define UDMA_STAT_DMACHANS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer. +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CFG register. +// +//***************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CTLBASE register. +// +//***************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address. +#define UDMA_CTLBASE_ADDR_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment. +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size. +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment. +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size. +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size. +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1). +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst. +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // DMA Transfer Mode. +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTBASE register. +// +//***************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer. +#define UDMA_ALTBASE_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_WAITSTAT register. +// +//***************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status. +#define UDMA_WAITSTAT_WAITREQ_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_SWREQ register. +// +//***************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request. +#define UDMA_SWREQ_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTSET +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set. +#define UDMA_USEBURSTSET_SET__0 0x00000000 // No Effect +#define UDMA_USEBURSTSET_SET__1 0x00000001 // Burst Only + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTCLR +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear. +#define UDMA_USEBURSTCLR_CLR__0 0x00000000 // No Effect +#define UDMA_USEBURSTCLR_CLR__1 0x00000001 // Single and Burst + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKSET +// register. +// +//***************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set. +#define UDMA_REQMASKSET_SET__0 0x00000000 // No Effect +#define UDMA_REQMASKSET_SET__1 0x00000001 // Masked + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKCLR +// register. +// +//***************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear. +#define UDMA_REQMASKCLR_CLR__0 0x00000000 // No Effect +#define UDMA_REQMASKCLR_CLR__1 0x00000001 // Clear Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENASET register. +// +//***************************************************************************** +#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set. +#define UDMA_ENASET_SET__0 0x00000000 // Disabled +#define UDMA_ENASET_SET__1 0x00000001 // Enabled +#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set. +#define UDMA_ENASET_CHENSET__0 0x00000000 // No Effect +#define UDMA_ENASET_CHENSET__1 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENACLR register. +// +//***************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable. +#define UDMA_ENACLR_CLR__0 0x00000000 // No Effect +#define UDMA_ENACLR_CLR__1 0x00000001 // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTSET register. +// +//***************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set. +#define UDMA_ALTSET_SET__0 0x00000000 // No Effect +#define UDMA_ALTSET_SET__1 0x00000001 // Alternate + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTCLR register. +// +//***************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear. +#define UDMA_ALTCLR_CLR__0 0x00000000 // No Effect +#define UDMA_ALTCLR_CLR__1 0x00000001 // Primary + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOSET register. +// +//***************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set. +#define UDMA_PRIOSET_SET__0 0x00000000 // No Effect +#define UDMA_PRIOSET_SET__1 0x00000001 // High Priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOCLR register. +// +//***************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear. +#define UDMA_PRIOCLR_CLR__0 0x00000000 // No Effect +#define UDMA_PRIOCLR_CLR__1 0x00000001 // Default Priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ERRCLR register. +// +//***************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // DMA Bus Error Status. + +#endif // __HW_UDMA_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_usb.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_usb.h new file mode 100644 index 0000000..d6b91cd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_usb.h @@ -0,0 +1,1309 @@ +//***************************************************************************** +// +// hw_usb.h - Macros for use in accessing the USB registers. +// +// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_USB_H__ +#define __HW_USB_H__ + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus (USB) Controller +// offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBus Pulse Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device Resume Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device Resume Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device Resume Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address. +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // ISO Update. +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect. +#define USB_POWER_RESET 0x00000008 // Reset. +#define USB_POWER_RESUME 0x00000004 // Resume Signaling. +#define USB_POWER_SUSPEND 0x00000002 // Suspend Mode. +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt. +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt. +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt. +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt. +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt. +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable. +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable. +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable. +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable. +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable. +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBus Error. +#define USB_IS_SESREQ 0x00000040 // Session Request. +#define USB_IS_DISCON 0x00000020 // Session Disconnect. +#define USB_IS_CONN 0x00000010 // Session Connect. +#define USB_IS_SOF 0x00000008 // Start of Frame. +#define USB_IS_BABBLE 0x00000004 // Babble Detected. +#define USB_IS_RESET 0x00000004 // Reset Signal Detected. +#define USB_IS_RESUME 0x00000002 // Resume Signal Detected. +#define USB_IS_SUSPEND 0x00000001 // Suspend Signal Detected. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt. +#define USB_IE_SESREQ 0x00000040 // Enable Session Request + // Interrupt. +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt. +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt. +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt. +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt. +#define USB_IE_RESET 0x00000004 // Enable Reset Interrupt. +#define USB_IE_RESUME 0x00000002 // Enable Resume Interrupt. +#define USB_IE_SUSPND 0x00000001 // Enable Suspend Interrupt. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number. +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index. +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode. +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access. +#define USB_TEST_FORCEFS 0x00000020 // Force Full Speed. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data. +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode. +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected. +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected. +#define USB_DEVCTL_VBUS_M 0x00000018 // VBus Level. +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBusValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBusValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode. +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request. +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support. +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size. +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support. +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size. +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address. +#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0 +#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address. +#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0 +#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait. +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID. +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap. +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap. +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address. +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address. +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port. +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address. +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators. +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address. +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port. +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout. +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear. +#define USB_CSRL0_STATUS 0x00000040 // Status Packet. +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear. +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet. +#define USB_CSRL0_STALL 0x00000020 // Send Stall. +#define USB_CSRL0_SETEND 0x00000010 // Setup End. +#define USB_CSRL0_ERROR 0x00000010 // Error. +#define USB_CSRL0_DATAEND 0x00000008 // Data End. +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet. +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled. +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready. +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_CSRH0_DT 0x00000002 // Data Toggle. +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // Count. +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit. +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MULT_M 0x0000F800 // Multiplier. +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP1_MULT_S 11 +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL1_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL1_ERROR 0x00000004 // Error. +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH1_ISO 0x00000040 // ISO. +#define USB_TXCSRH1_MODE 0x00000020 // Mode. +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MULT_M 0x0000F800 // Multiplier. +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP1_MULT_S 11 +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL1_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL1_OVER 0x00000004 // Overrun. +#define USB_RXCSRL1_ERROR 0x00000004 // Error. +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH1_ISO 0x00000040 // ISO. +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH1_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MULT_M 0x0000F800 // Multiplier. +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP2_MULT_S 11 +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL2_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL2_ERROR 0x00000004 // Error. +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH2_ISO 0x00000040 // ISO. +#define USB_TXCSRH2_MODE 0x00000020 // Mode. +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MULT_M 0x0000F800 // Multiplier. +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP2_MULT_S 11 +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL2_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL2_ERROR 0x00000004 // Error. +#define USB_RXCSRL2_OVER 0x00000004 // Overrun. +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH2_ISO 0x00000040 // ISO. +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH2_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MULT_M 0x0000F800 // Multiplier. +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_TXMAXP3_MULT_S 11 +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_INCTX 0x00000080 // Incomplete Transmit. +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle. +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled. +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet. +#define USB_TXCSRL3_STALL 0x00000010 // Send Stall. +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO. +#define USB_TXCSRL3_ERROR 0x00000004 // Error. +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun. +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty. +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set. +#define USB_TXCSRH3_ISO 0x00000040 // ISO. +#define USB_TXCSRH3_MODE 0x00000020 // Mode. +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable. +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle. +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode. +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable. +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MULT_M 0x0000F800 // Multiplier. +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload. +#define USB_RXMAXP3_MULT_S 11 +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle. +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled. +#define USB_RXCSRL3_STALL 0x00000020 // Send Stall. +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet. +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO. +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error. +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout. +#define USB_RXCSRL3_ERROR 0x00000004 // Error. +#define USB_RXCSRL3_OVER 0x00000004 // Overrun. +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full. +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear. +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request. +#define USB_RXCSRH3_ISO 0x00000040 // ISO. +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable. +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error. +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode. +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable. +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle. +#define USB_RXCSRH3_INCRX 0x00000001 // Incomplete Receive. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count. +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed. +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol. +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed. +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol. +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number. +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit. +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count. +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable. +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable. +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action. +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable. +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense. +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable. +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable. +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration. +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt + // Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // Resume Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // Resume Interrupt Mask. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // Resume Interrupt Status and + // Clear. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBus Pulse Length. +#define USB_VPLEN_VPLEN_S 0 + +#endif // __HW_USB_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_watchdog.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_watchdog.h new file mode 100644 index 0000000..5e8991b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/hw_watchdog.h @@ -0,0 +1,179 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following are defines for the Watchdog Timer register offsets. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock. +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value. +#define WDT_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value. +#define WDT_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear. +#define WDT_ICR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status. + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt + // Status. + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the Watchdog Timer register +// offsets. +// +//***************************************************************************** +#define WDT_O_PeriphID4 0x00000FD0 +#define WDT_O_PeriphID5 0x00000FD4 +#define WDT_O_PeriphID6 0x00000FD8 +#define WDT_O_PeriphID7 0x00000FDC +#define WDT_O_PeriphID0 0x00000FE0 +#define WDT_O_PeriphID1 0x00000FE4 +#define WDT_O_PeriphID2 0x00000FE8 +#define WDT_O_PeriphID3 0x00000FEC +#define WDT_O_PCellID0 0x00000FF0 +#define WDT_O_PCellID1 0x00000FF4 +#define WDT_O_PCellID2 0x00000FF8 +#define WDT_O_PCellID3 0x00000FFC + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the WDT_TEST +// register. +// +//***************************************************************************** +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable + +//***************************************************************************** +// +// The following are deprecated defines for the reset values for the WDT +// registers. +// +//***************************************************************************** +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_PCellID1 0x000000F0 +#define WDT_RV_PCellID3 0x000000B1 +#define WDT_RV_PeriphID1 0x00000018 +#define WDT_RV_PeriphID2 0x00000018 +#define WDT_RV_PCellID0 0x0000000D +#define WDT_RV_PCellID2 0x00000005 +#define WDT_RV_PeriphID0 0x00000005 +#define WDT_RV_PeriphID3 0x00000001 +#define WDT_RV_PeriphID5 0x00000000 +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_PeriphID4 0x00000000 +#define WDT_RV_PeriphID6 0x00000000 +#define WDT_RV_PeriphID7 0x00000000 +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register + +#endif + +#endif // __HW_WATCHDOG_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/i2c.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/i2c.h new file mode 100644 index 0000000..50aeecd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/i2c.h @@ -0,0 +1,156 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +//***************************************************************************** +// +// Several I2C APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define I2CMasterInit(a, b) \ + I2CMasterInitExpClk(a, SysCtlClockGet(), b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/interrupt.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/interrupt.h new file mode 100644 index 0000000..feaaf1c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/interrupt.h @@ -0,0 +1,77 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. +// +//***************************************************************************** +#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean IntMasterEnable(void); +extern tBoolean IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/lmi_flash.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/lmi_flash.h new file mode 100644 index 0000000..e53883f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/lmi_flash.h @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); +extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); +extern long FlashUserSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/lmi_timer.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/lmi_timer.h new file mode 100644 index 0000000..0a0d545 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/lmi_timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/mpu.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/mpu.h new file mode 100644 index 0000000..a52f501 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/mpu.h @@ -0,0 +1,151 @@ +//***************************************************************************** +// +// mpu.h - Defines and Macros for the memory protection unit. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __MPU_H__ +#define __MPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Flags that can be passed to MPUEnable.. +// +//***************************************************************************** +#define MPU_CONFIG_PRIV_DEFAULT 4 +#define MPU_CONFIG_HARDFLT_NMI 2 +#define MPU_CONFIG_NONE 0 + +//***************************************************************************** +// +// Flags for the region size to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_SIZE_32B (4 << 1) +#define MPU_RGN_SIZE_64B (5 << 1) +#define MPU_RGN_SIZE_128B (6 << 1) +#define MPU_RGN_SIZE_256B (7 << 1) +#define MPU_RGN_SIZE_512B (8 << 1) + +#define MPU_RGN_SIZE_1K (9 << 1) +#define MPU_RGN_SIZE_2K (10 << 1) +#define MPU_RGN_SIZE_4K (11 << 1) +#define MPU_RGN_SIZE_8K (12 << 1) +#define MPU_RGN_SIZE_16K (13 << 1) +#define MPU_RGN_SIZE_32K (14 << 1) +#define MPU_RGN_SIZE_64K (15 << 1) +#define MPU_RGN_SIZE_128K (16 << 1) +#define MPU_RGN_SIZE_256K (17 << 1) +#define MPU_RGN_SIZE_512K (18 << 1) + +#define MPU_RGN_SIZE_1M (19 << 1) +#define MPU_RGN_SIZE_2M (20 << 1) +#define MPU_RGN_SIZE_4M (21 << 1) +#define MPU_RGN_SIZE_8M (22 << 1) +#define MPU_RGN_SIZE_16M (23 << 1) +#define MPU_RGN_SIZE_32M (24 << 1) +#define MPU_RGN_SIZE_64M (25 << 1) +#define MPU_RGN_SIZE_128M (26 << 1) +#define MPU_RGN_SIZE_256M (27 << 1) +#define MPU_RGN_SIZE_512M (28 << 1) + +#define MPU_RGN_SIZE_1G (29 << 1) +#define MPU_RGN_SIZE_2G (30 << 1) +#define MPU_RGN_SIZE_4G (31 << 1) + +//***************************************************************************** +// +// Flags for the permissions to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_PERM_EXEC 0x00000000 +#define MPU_RGN_PERM_NOEXEC 0x10000000 +#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000 +#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000 +#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000 +#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000 +#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000 +#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000 + +//***************************************************************************** +// +// Flags for the sub-region to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_SUB_RGN_DISABLE_0 0x00000100 +#define MPU_SUB_RGN_DISABLE_1 0x00000200 +#define MPU_SUB_RGN_DISABLE_2 0x00000400 +#define MPU_SUB_RGN_DISABLE_3 0x00000800 +#define MPU_SUB_RGN_DISABLE_4 0x00001000 +#define MPU_SUB_RGN_DISABLE_5 0x00002000 +#define MPU_SUB_RGN_DISABLE_6 0x00004000 +#define MPU_SUB_RGN_DISABLE_7 0x00008000 + +//***************************************************************************** +// +// Flags to enable or disable a region, to be passed to MPURegionSet. +// +//***************************************************************************** +#define MPU_RGN_ENABLE 1 +#define MPU_RGN_DISABLE 0 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void MPUEnable(unsigned long ulMPUConfig); +extern void MPUDisable(void); +extern unsigned long MPURegionCountGet(void); +extern void MPURegionEnable(unsigned long ulRegion); +extern void MPURegionDisable(unsigned long ulRegion); +extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr, + unsigned long ulFlags); +extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr, + unsigned long *pulFlags); +extern void MPUIntRegister(void (*pfnHandler)(void)); +extern void MPUIntUnregister(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __MPU_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/pwm.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/pwm.h new file mode 100644 index 0000000..cdb0725 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/pwm.h @@ -0,0 +1,270 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode +#define PWM_GEN_MODE_FAULT_LATCHED \ + 0x00040000 // Fault is latched +#define PWM_GEN_MODE_FAULT_UNLATCHED \ + 0x00000000 // Fault is not latched +#define PWM_GEN_MODE_FAULT_MINPER \ + 0x00020000 // Enable min fault period +#define PWM_GEN_MODE_FAULT_NO_MINPER \ + 0x00000000 // Disable min fault period +#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support +#define PWM_GEN_MODE_FAULT_LEGACY \ + 0x00000000 // Disable extended fault support +#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur + // immediately +#define PWM_GEN_MODE_DB_SYNC_LOCAL \ + 0x0000A800 // Deadband updates locally + // synchronized +#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ + 0x0000FC00 // Deadband updates globally + // synchronized +#define PWM_GEN_MODE_GEN_NO_SYNC \ + 0x00000000 // Generator mode updates occur + // immediately +#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ + 0x00000280 // Generator mode updates locally + // synchronized +#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ + 0x000003C0 // Generator mode updates globally + // synchronized + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt +#ifndef DEPRECATED +#define PWM_INT_FAULT 0x00010000 // Fault interrupt +#endif +#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt +#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt +#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt +#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt +#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 +#define PWM_GEN_3 0x00000100 // Offset address of Gen3 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 +#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 + +#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range +#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range +#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range +#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 +#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 +#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 +#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 +#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_0 +// +//***************************************************************************** +#define PWM_FAULT_GROUP_0 0 + +#define PWM_FAULT_FAULT0 0x00000001 +#define PWM_FAULT_FAULT1 0x00000002 +#define PWM_FAULT_FAULT2 0x00000004 +#define PWM_FAULT_FAULT3 0x00000008 +#define PWM_FAULT_ACMP0 0x00010000 +#define PWM_FAULT_ACMP1 0x00020000 +#define PWM_FAULT_ACMP2 0x00040000 + +//***************************************************************************** +// +// Defines to identify the sense of each of the external FAULTn signals +// +//***************************************************************************** +#define PWM_FAULT0_SENSE_HIGH 0x00000000 +#define PWM_FAULT0_SENSE_LOW 0x00000001 +#define PWM_FAULT1_SENSE_HIGH 0x00000000 +#define PWM_FAULT1_SENSE_LOW 0x00000002 +#define PWM_FAULT2_SENSE_HIGH 0x00000000 +#define PWM_FAULT2_SENSE_LOW 0x00000004 +#define PWM_FAULT3_SENSE_HIGH 0x00000000 +#define PWM_FAULT3_SENSE_LOW 0x00000008 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFaultLevel(unsigned long ulBase, + unsigned long ulPWMOutBits, + tBoolean bDriveHigh); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultSuppress); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void PWMFaultIntClearExt(unsigned long ulBase, + unsigned long ulFaultInts); +extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulMinFaultPeriod, + unsigned long ulFaultSenses); +extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, + unsigned long ulFaultTriggers); +extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase, + unsigned long ulGen, + unsigned long ulGroup); +extern unsigned long PWMGenFaultStatus(unsigned long ulBase, + unsigned long ulGen, + unsigned long ulGroup); +extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulGroup, + unsigned long ulFaultTriggers); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/qei.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/qei.h new file mode 100644 index 0000000..5d1f39c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/qei.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/rit128x96x4.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/rit128x96x4.h new file mode 100644 index 0000000..eeec8e6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/rit128x96x4.h @@ -0,0 +1,53 @@ +//***************************************************************************** +// +// rit128x96x4.h - Prototypes for the driver for the RITEK 128x96x4 graphical +// OLED display. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __RIT128X96X4_H__ +#define __RIT128X96X4_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void RIT128x96x4Clear(void); +extern void RIT128x96x4StringDraw(const char *pcStr, + unsigned long ulX, + unsigned long ulY, + unsigned char ucLevel); +extern void RIT128x96x4ImageDraw(const unsigned char *pucImage, + unsigned long ulX, + unsigned long ulY, + unsigned long ulWidth, + unsigned long ulHeight); +extern void RIT128x96x4Init(unsigned long ulFrequency); +extern void RIT128x96x4Enable(unsigned long ulFrequency); +extern void RIT128x96x4Disable(void); +extern void RIT128x96x4DisplayOn(void); +extern void RIT128x96x4DisplayOff(void); + +#endif // __RIT128X96X4_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/rom.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/rom.h new file mode 100644 index 0000000..d066c68 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/rom.h @@ -0,0 +1,1251 @@ +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_APITABLE ((unsigned long *)0x01000010) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1])) +#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2])) +#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3])) +#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4])) +#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5])) +#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6])) +#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7])) +#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8])) +#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9])) +#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10])) +#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11])) +#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12])) +#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13])) +#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14])) + +//***************************************************************************** +// +// Macros for calling ROM functions in the ADC API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCSequenceDataGet \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long *pulBuffer))ROM_ADCTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + tBoolean bMasked))ROM_ADCTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCSequenceEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCSequenceDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCSequenceConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long ulTrigger, \ + unsigned long ulPriority))ROM_ADCTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCSequenceStepConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum, \ + unsigned long ulStep, \ + unsigned long ulConfig))ROM_ADCTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCSequenceOverflow \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCSequenceOverflowClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCSequenceUnderflow \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCSequenceUnderflowClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCProcessorTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSequenceNum))ROM_ADCTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ADCHardwareOversampleConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulFactor))ROM_ADCTABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Comparator API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ComparatorIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ComparatorConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + unsigned long ulConfig))ROM_COMPARATORTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ComparatorRefSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulRef))ROM_COMPARATORTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ComparatorValueGet \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ComparatorIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ComparatorIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulComp))ROM_COMPARATORTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_ComparatorIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned long ulComp, \ + tBoolean bMasked))ROM_COMPARATORTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Flash API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashProgram \ + ((long (*)(unsigned long *pulData, \ + unsigned long ulAddress, \ + unsigned long ulCount))ROM_FLASHTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashUsecGet \ + ((unsigned long (*)(void))ROM_FLASHTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashUsecSet \ + ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashErase \ + ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashProtectSet \ + ((long (*)(unsigned long ulAddress, \ + tFlashProtection eProtect))ROM_FLASHTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashProtectSave \ + ((long (*)(void))ROM_FLASHTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashUserGet \ + ((long (*)(unsigned long *pulUser0, \ + unsigned long *pulUser1))ROM_FLASHTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashUserSet \ + ((long (*)(unsigned long ulUser0, \ + unsigned long ulUser1))ROM_FLASHTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashUserSave \ + ((long (*)(void))ROM_FLASHTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashIntEnable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashIntDisable \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashIntGetStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_FlashIntClear \ + ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the GPIO API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinWrite \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned char ucVal))ROM_GPIOTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIODirModeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulPinIO))ROM_GPIOTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIODirModeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOIntTypeSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulIntType))ROM_GPIOTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOIntTypeGet \ + ((unsigned long (*)(unsigned long ulPort, \ + unsigned char ucPin))ROM_GPIOTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPadConfigSet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins, \ + unsigned long ulStrength, \ + unsigned long ulPadType))ROM_GPIOTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPadConfigGet \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPin, \ + unsigned long *pulStrength, \ + unsigned long *pulPadType))ROM_GPIOTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinIntEnable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinIntDisable \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinIntStatus \ + ((long (*)(unsigned long ulPort, \ + tBoolean bMasked))ROM_GPIOTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinIntClear \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinRead \ + ((long (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeCAN \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeComparator \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeGPIOInput \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeGPIOOutput \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeI2C \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypePWM \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeQEI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeSSI \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeTimer \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeUART \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_GPIOPinTypeGPIOOutputOD \ + ((void (*)(unsigned long ulPort, \ + unsigned char ucPins))ROM_GPIOTABLE[22]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2C API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_I2CTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulI2CClk, \ + tBoolean bFast))ROM_I2CTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveInit \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucSlaveAddr))ROM_I2CTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterIntEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterIntDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveIntStatus \ + ((tBoolean (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_I2CTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterIntClear \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveIntClear \ + ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucSlaveAddr, \ + tBoolean bReceive))ROM_I2CTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterBusBusy \ + ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterControl \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulCmd))ROM_I2CTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterErr \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CMasterDataGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveStatus \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_I2CTABLE[22]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_I2CSlaveDataGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UpdateI2C \ + ((void (*)(void))ROM_I2CTABLE[24]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Interrupt API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_IntEnable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_IntDisable \ + ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_IntPriorityGroupingGet \ + ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_IntPrioritySet \ + ((void (*)(unsigned long ulInterrupt, \ + unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_IntPriorityGet \ + ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PWM API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMPulseWidthSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOut, \ + unsigned long ulWidth))ROM_PWMTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMGenConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulConfig))ROM_PWMTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMGenPeriodSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulPeriod))ROM_PWMTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMGenPeriodGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMGenEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMGenDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMPulseWidthGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulPWMOut))ROM_PWMTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMDeadBandEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned short usRise, \ + unsigned short usFall))ROM_PWMTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMDeadBandDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen))ROM_PWMTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMSyncUpdate \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenBits))ROM_PWMTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMSyncTimeBase \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenBits))ROM_PWMTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMOutputState \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bEnable))ROM_PWMTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMOutputInvert \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bInvert))ROM_PWMTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMOutputFault \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPWMOutBits, \ + tBoolean bFaultSuppress))ROM_PWMTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMGenIntTrigEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulIntTrig))ROM_PWMTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMGenIntTrigDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulIntTrig))ROM_PWMTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMGenIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + tBoolean bMasked))ROM_PWMTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMGenIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGen, \ + unsigned long ulInts))ROM_PWMTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenFault))ROM_PWMTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulGenFault))ROM_PWMTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMFaultIntClear \ + ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_PWMIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_PWMTABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the QEI API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIPositionGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIEnable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIDisable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig, \ + unsigned long ulMaxPosition))ROM_QEITABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIPositionSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPosition))ROM_QEITABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIDirectionGet \ + ((long (*)(unsigned long ulBase))ROM_QEITABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIErrorGet \ + ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIVelocityEnable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIVelocityDisable \ + ((void (*)(unsigned long ulBase))ROM_QEITABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIVelocityConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulPreDiv, \ + unsigned long ulPeriod))ROM_QEITABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIVelocityGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_QEITABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_QEIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_QEITABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SSI API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIDataPut \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SSITABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulSSIClk, \ + unsigned long ulProtocol, \ + unsigned long ulMode, \ + unsigned long ulBitRate, \ + unsigned long ulDataWidth))ROM_SSITABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIEnable \ + ((void (*)(unsigned long ulBase))ROM_SSITABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIDisable \ + ((void (*)(unsigned long ulBase))ROM_SSITABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_SSITABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_SSITABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIDataPutNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long ulData))ROM_SSITABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIDataGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SSITABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SSIDataGetNonBlocking \ + ((long (*)(unsigned long ulBase, \ + unsigned long *pulData))ROM_SSITABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UpdateSSI \ + ((void (*)(void))ROM_SSITABLE[11]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysCtl API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlSRAMSizeGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlFlashSizeGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPinPresent \ + ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPeripheralPresent \ + ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPeripheralReset \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPeripheralEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPeripheralDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPeripheralSleepEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPeripheralSleepDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPeripheralDeepSleepEnable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPeripheralDeepSleepDisable \ + ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPeripheralClockGating \ + ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlIntEnable \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlIntDisable \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlIntClear \ + ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlIntStatus \ + ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlLDOSet \ + ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlLDOGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlReset \ + ((void (*)(void))ROM_SYSCTLTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlDeepSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlResetCauseGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[21]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlResetCauseClear \ + ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlClockGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[24]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPWMClockSet \ + ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlPWMClockGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[26]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlADCSpeedSet \ + ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlADCSpeedGet \ + ((unsigned long (*)(void))ROM_SYSCTLTABLE[28]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlGPIOAHBEnable \ + ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysCtlGPIOAHBDisable \ + ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysTick API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysTickValueGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysTickPeriodSet \ + ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_SysTickPeriodGet \ + ((unsigned long (*)(void))ROM_SYSTICKTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Timer API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerConfigure \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulConfig))ROM_TIMERTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerControlLevel \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bInvert))ROM_TIMERTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerControlTrigger \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bEnable))ROM_TIMERTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerControlEvent \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulEvent))ROM_TIMERTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerControlStall \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + tBoolean bStall))ROM_TIMERTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerRTCEnable \ + ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerRTCDisable \ + ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerPrescaleSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerPrescaleGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerLoadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerLoadGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerValueGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerMatchSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTimer, \ + unsigned long ulValue))ROM_TIMERTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerMatchGet \ + ((unsigned long (*)(unsigned long ulBase, \ + unsigned long ulTimer))ROM_TIMERTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_TimerIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_TIMERTABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UART API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTCharPut \ + ((void (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTParityModeSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulParity))ROM_UARTTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTParityModeGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulTxLevel, \ + unsigned long ulRxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(unsigned long ulBase, \ + unsigned long *pulTxLevel, \ + unsigned long *pulRxLevel))ROM_UARTTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long ulBaud, \ + unsigned long ulConfig))ROM_UARTTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulUARTClk, \ + unsigned long *pulBaud, \ + unsigned long *pulConfig))ROM_UARTTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTEnable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTDisable \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTEnableSIR \ + ((void (*)(unsigned long ulBase, \ + tBoolean bLowPower))ROM_UARTTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTDisableSIR \ + ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTCharsAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTSpaceAvail \ + ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTCharGetNonBlocking \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTCharGet \ + ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTCharPutNonBlocking \ + ((tBoolean (*)(unsigned long ulBase, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTBreakCtl \ + ((void (*)(unsigned long ulBase, \ + tBoolean bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTIntEnable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[17]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTIntDisable \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[18]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_UARTTABLE[19]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UARTIntClear \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulIntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_UpdateUART \ + ((void (*)(void))ROM_UARTTABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Watchdog API. +// +//***************************************************************************** +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogIntClear \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogRunning \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogResetEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogResetDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogLock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogUnlock \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogLockState \ + ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogReloadSet \ + ((void (*)(unsigned long ulBase, \ + unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogReloadGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogValueGet \ + ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogIntEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogIntStatus \ + ((unsigned long (*)(unsigned long ulBase, \ + tBoolean bMasked))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogStallEnable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(TARGET_IS_DUSTDEVIL_RA0) +#define ROM_WatchdogStallDisable \ + ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) +#endif + +#endif // __ROM_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/ssi.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/ssi.h new file mode 100644 index 0000000..013aadb --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/ssi.h @@ -0,0 +1,128 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SSIDataGetNonBlocking(unsigned long ulBase, + unsigned long *pulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); +extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); + +//***************************************************************************** +// +// Several SSI APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define SSIConfig(a, b, c, d, e) \ + SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e) +#define SSIDataNonBlockingGet(a, b) \ + SSIDataGetNonBlocking(a, b) +#define SSIDataNonBlockingPut(a, b) \ + SSIDataPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/sysctl.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/sysctl.h new file mode 100644 index 0000000..55f847f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/sysctl.h @@ -0,0 +1,391 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module +#define SYSCTL_PERIPH_ADC 0x00100001 // ADC +#define SYSCTL_PERIPH_PWM 0x00100010 // PWM +#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 +#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 +#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2 +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#endif +#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 +#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#endif +#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 +#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#endif +#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 +#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 +#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 +#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 +#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F +#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G +#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H +#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA +#define SYSCTL_PERIPH_USB0 0x20100001 // USB0 +#define SYSCTL_PERIPH_ETH 0x20105000 // ETH +#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588 +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex-M3 MPU + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin +#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 +#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 +#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 +#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 +#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 +#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 +#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 +#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 +#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 +#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 +#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 +#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 +#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 +#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 +#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 +#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 +#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 +#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 +#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 +#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 +#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 +#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 +#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 +#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 +#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 +#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 +#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 +#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 +#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 +#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 +#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 +#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 +#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 +#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 +#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 +#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 +#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 +#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 +#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 +#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 +#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 +#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 +#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 +#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 +#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 +#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 +#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 +#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz +#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz +#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz +#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz +#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz +#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz +#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz +#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz +#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz +#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_OSC_INT30 0x80000030 // Oscillator source is int. 30 KHz +#define SYSCTL_OSC_EXT32 0x80000038 // Oscillator source is ext. 32 KHz +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlDelay(unsigned long ulCount); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); +extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral); +extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/systick.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/systick.h new file mode 100644 index 0000000..cdab807 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/systick.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/timer.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/timer.h new file mode 100644 index 0000000..34a6177 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/timer.h @@ -0,0 +1,154 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +//***************************************************************************** +// +// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used +// instead to return the timer to its reset state. +// +//***************************************************************************** +#ifndef DEPRECATED +extern void TimerQuiesce(unsigned long ulBase); +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/uart.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/uart.h new file mode 100644 index 0000000..eb286f8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/uart.h @@ -0,0 +1,178 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter +// and returned by UARTConfigGetExpClk in the pulConfig parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ulParity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and +// returned by UARTFIFOLevelGet in the pulTxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and +// returned by UARTFIFOLevelGet in the pulRxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel); +extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); +extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); +extern void UARTDisableSIR(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); +extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); + +//***************************************************************************** +// +// Several UART APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define UARTConfigSet(a, b, c) \ + UARTConfigSetExpClk(a, SysCtlClockGet(), b, c) +#define UARTConfigGet(a, b, c) \ + UARTConfigGetExpClk(a, SysCtlClockGet(), b, c) +#define UARTCharNonBlockingGet(a) \ + UARTCharGetNonBlocking(a) +#define UARTCharNonBlockingPut(a, b) \ + UARTCharPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/ustdlib.c b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/ustdlib.c new file mode 100644 index 0000000..e68b143 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/ustdlib.c @@ -0,0 +1,670 @@ +//***************************************************************************** +// +// ustdlib.c - Simple standard library functions. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +#include +#include +#include "debug.h" + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// A mapping from an integer between 0 and 15 to its ASCII character +// equivalent. +// +//***************************************************************************** +static const char * const g_pcHex = "0123456789abcdef"; + +//***************************************************************************** +// +//! A simple vsnprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. +//! +//! \param pcBuf points to the buffer where the converted string is stored. +//! \param ulSize is the size of the buffer. +//! \param pcString is the format string. +//! \param vaArgP is the list of optional arguments, which depend on the +//! contents of the format string. +//! +//! This function is very similar to the C library vsnprintf() +//! function. Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%\% to print out a \% character +//! +//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% +//! and the format character, which specifies the minimum number of characters +//! to use for that value; if preceeded by a 0 then the extra characters will +//! be filled with zeros instead of spaces. For example, ``\%8d'' will use +//! eight characters to print the decimal value with spaces added to reach +//! eight; ``\%08d'' will use eight characters as well but will add zeros +//! instead of spaces. +//! +//! The type of the arguments after \b pcString must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The \b ulSize parameter limits the number of characters that will be +//! stored in the buffer pointed to by \b pcBuf to prevent the possibility +//! of a buffer overflow. The buffer size should be large enough to hold +//! the expected converted output string, including the null termination +//! character. +//! +//! The function will return the number of characters that would be +//! converted as if there were no limit on the buffer size. Therefore +//! it is possible for the function to return a count that is greater than +//! the specified buffer size. If this happens, it means that the output +//! was truncated. +//! +//! \return the number of characters that were to be stored, not including +//! the NULL termination character, regardless of space in the buffer. +// +//***************************************************************************** +int +uvsnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, + va_list vaArgP) +{ + unsigned long ulIdx, ulValue, ulCount, ulBase; + char *pcStr, cFill; + int iConvertCount = 0; + + // + // Check the arguments. + // + ASSERT(pcString != 0); + ASSERT(pcBuf != 0); + ASSERT(ulSize != 0); + + // + // Adjust buffer size limit to allow one space for null termination. + // + if(ulSize) + { + ulSize--; + } + + // + // Initialize the count of characters converted. + // + iConvertCount = 0; + + // + // Loop while there are more characters in the format string. + // + while(*pcString) + { + // + // Find the first non-% character, or the end of the string. + // + for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0'); + ulIdx++) + { + } + + // + // Write this portion of the string to the output buffer. If + // there are more characters to write than there is space in the + // buffer, then only write as much as will fit in the buffer. + // + if(ulIdx > ulSize) + { + strncpy(pcBuf, pcString, ulSize); + pcBuf += ulSize; + ulSize = 0; + } + else + { + strncpy(pcBuf, pcString, ulIdx); + pcBuf += ulIdx; + ulSize -= ulIdx; + } + + // + // Update the conversion count. This will be the number of + // characters that should have been written, even if there was + // not room in the buffer. + // + iConvertCount += ulIdx; + + // + // Skip the portion of the format string that was written. + // + pcString += ulIdx; + + // + // See if the next character is a %. + // + if(*pcString == '%') + { + // + // Skip the %. + // + pcString++; + + // + // Set the digit count to zero, and the fill character to space + // (i.e. to the defaults). + // + ulCount = 0; + cFill = ' '; + + // + // It may be necessary to get back here to process more characters. + // Goto's aren't pretty, but effective. I feel extremely dirty for + // using not one but two of the beasts. + // +again: + + // + // Determine how to handle the next character. + // + switch(*pcString++) + { + // + // Handle the digit characters. + // + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + // + // If this is a zero, and it is the first digit, then the + // fill character is a zero instead of a space. + // + if((pcString[-1] == '0') && (ulCount == 0)) + { + cFill = '0'; + } + + // + // Update the digit count. + // + ulCount *= 10; + ulCount += pcString[-1] - '0'; + + // + // Get the next character. + // + goto again; + } + + // + // Handle the %c command. + // + case 'c': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(vaArgP, unsigned long); + + // + // Copy the character to the output buffer, if + // there is room. Update the buffer size remaining. + // + if(ulSize != 0) + { + *pcBuf++ = (char)ulValue; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + + // + // This command has been handled. + // + break; + } + + // + // Handle the %d command. + // + case 'd': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(vaArgP, unsigned long); + + // + // If the value is negative, make it positive and stick a + // minus sign in the beginning of the buffer. + // + if((long)ulValue < 0) + { + ulValue = -(long)ulValue; + + if(ulSize != 0) + { + *pcBuf++ = '-'; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + + // + // Set the base to 10. + // + ulBase = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %s command. + // + case 's': + { + // + // Get the string pointer from the varargs. + // + pcStr = va_arg(vaArgP, char *); + + // + // Determine the length of the string. + // + for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++) + { + } + + // + // Copy the string to the output buffer. Only copy + // as much as will fit in the buffer. Update the + // output buffer pointer and the space remaining. + // + if(ulIdx > ulSize) + { + strncpy(pcBuf, pcStr, ulSize); + pcBuf += ulSize; + ulSize = 0; + } + else + { + strncpy(pcBuf, pcStr, ulIdx); + pcBuf += ulIdx; + ulSize -= ulIdx; + } + + // + // Update the conversion count. This will be the number of + // characters that should have been written, even if there + // was not room in the buffer. + // + iConvertCount += ulIdx; + + // + // + // This command has been handled. + // + break; + } + + // + // Handle the %u command. + // + case 'u': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(vaArgP, unsigned long); + + // + // Set the base to 10. + // + ulBase = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %x and %X commands. Note that they are treated + // identically; i.e. %X will use lower case letters for a-f + // instead of the upper case letters is should use. + // + case 'x': + case 'X': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(vaArgP, unsigned long); + + // + // Set the base to 16. + // + ulBase = 16; + + // + // Determine the number of digits in the string version of + // the value. + // +convert: + for(ulIdx = 1; + (((ulIdx * ulBase) <= ulValue) && + (((ulIdx * ulBase) / ulBase) == ulIdx)); + ulIdx *= ulBase, ulCount--) + { + } + + // + // Provide additional padding at the beginning of the + // string conversion if needed. + // + if((ulCount > 1) && (ulCount < 16)) + { + for(ulCount--; ulCount; ulCount--) + { + // + // Copy the character to the output buffer if + // there is room. + // + if(ulSize != 0) + { + *pcBuf++ = cFill; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + } + + // + // Convert the value into a string. + // + for(; ulIdx; ulIdx /= ulBase) + { + // + // Copy the character to the output buffer if + // there is room. + // + if(ulSize != 0) + { + *pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase]; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + + // + // This command has been handled. + // + break; + } + + // + // Handle the %% command. + // + case '%': + { + // + // Simply write a single %. + // + if(ulSize != 0) + { + *pcBuf++ = pcString[-1]; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + + // + // This command has been handled. + // + break; + } + + // + // Handle all other commands. + // + default: + { + // + // Indicate an error. + // + if(ulSize >= 5) + { + strncpy(pcBuf, "ERROR", 5); + pcBuf += 5; + ulSize -= 5; + } + else + { + strncpy(pcBuf, "ERROR", ulSize); + pcBuf += ulSize; + ulSize = 0; + } + + // + // Update the conversion count. + // + iConvertCount += 5; + + // + // This command has been handled. + // + break; + } + } + } + } + + // + // Null terminate the string in the buffer. + // + *pcBuf = 0; + return(iConvertCount); +} + +//***************************************************************************** +// +//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. +//! +//! \param pcBuf is the buffer where the converted string is stored. +//! \param pcString is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library sprintf() function. +//! Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%\% to print out a \% character +//! +//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% +//! and the format character, which specifies the minimum number of characters +//! to use for that value; if preceeded by a 0 then the extra characters will +//! be filled with zeros instead of spaces. For example, ``\%8d'' will use +//! eight characters to print the decimal value with spaces added to reach +//! eight; ``\%08d'' will use eight characters as well but will add zeros +//! instead of spaces. +//! +//! The type of the arguments after \b pcString must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The caller must ensure that the buffer pcBuf is large enough to hold the +//! entire converted string, including the null termination character. +//! +//! \return The count of characters that were written to the output buffer, +//! not including the NULL termination character. +// +//***************************************************************************** +int +usprintf(char *pcBuf, const char *pcString, ...) +{ + va_list vaArgP; + int iRet; + + // + // Start the varargs processing. + // + va_start(vaArgP, pcString); + + // + // Call vsnprintf to perform the conversion. Use a + // large number for the buffer size. + // + iRet = uvsnprintf(pcBuf, 0xffff, pcString, vaArgP); + + // + // End the varargs processing. + // + va_end(vaArgP); + + // + // Return the conversion count. + // + return(iRet); +} + +//***************************************************************************** +// +//! A simple snprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. +//! +//! \param pcBuf is the buffer where the converted string is stored. +//! \param ulSize is the size of the buffer. +//! \param pcString is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library sprintf() function. +//! Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%\% to print out a \% character +//! +//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% +//! and the format character, which specifies the minimum number of characters +//! to use for that value; if preceeded by a 0 then the extra characters will +//! be filled with zeros instead of spaces. For example, ``\%8d'' will use +//! eight characters to print the decimal value with spaces added to reach +//! eight; ``\%08d'' will use eight characters as well but will add zeros +//! instead of spaces. +//! +//! The type of the arguments after \b pcString must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The function will copy at most \b ulSize - 1 characters into the +//! buffer \b pcBuf. One space is reserved in the buffer for the null +//! termination character. +//! +//! The function will return the number of characters that would be +//! converted as if there were no limit on the buffer size. Therefore +//! it is possible for the function to return a count that is greater than +//! the specified buffer size. If this happens, it means that the output +//! was truncated. +//! +//! \return the number of characters that were to be stored, not including +//! the NULL termination character, regardless of space in the buffer. +// +//***************************************************************************** +int +usnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, ...) +{ +int iRet; + + va_list vaArgP; + + // + // Start the varargs processing. + // + va_start(vaArgP, pcString); + + // + // Call vsnprintf to perform the conversion. + // + iRet = uvsnprintf(pcBuf, ulSize, pcString, vaArgP); + + // + // End the varargs processing. + // + va_end(vaArgP); + + // + // Return the conversion count. + // + return(iRet); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/watchdog.h b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/watchdog.h new file mode 100644 index 0000000..4816538 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/LuminaryMicro/watchdog.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. You may not combine +// this software with "viral" open-source software in order to form a larger +// program. Any use in violation of the foregoing restrictions may subject +// the user to criminal sanctions under applicable laws, as well as to civil +// liability for the breach of the terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 2523 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallEnable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/cortexm3_macro.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/cortexm3_macro.h new file mode 100644 index 0000000..c67240e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/cortexm3_macro.h @@ -0,0 +1,51 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : cortexm3_macro.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : Header file for cortexm3_macro.s. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CORTEXM3_MACRO_H +#define __CORTEXM3_MACRO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void __WFI(void); +void __WFE(void); +void __SEV(void); +void __ISB(void); +void __DSB(void); +void __DMB(void); +void __SVC(void); +u32 __MRS_CONTROL(void); +void __MSR_CONTROL(u32 Control); +void __SETPRIMASK(void); +void __RESETPRIMASK(void); +void __SETFAULTMASK(void); +void __RESETFAULTMASK(void); +void __BASEPRICONFIG(u32 NewPriority); +u32 __GetBASEPRI(void); +u16 __REV_HalfWord(u16 Data); +u32 __REV_Word(u32 Data); + +#endif /* __CORTEXM3_MACRO_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/lcd.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/lcd.h new file mode 100644 index 0000000..73f44b9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/lcd.h @@ -0,0 +1,179 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : lcd.h +* Author : MCD Application Team +* Date First Issued : mm/dd/yyyy +* Description : This file contains all the functions prototypes for the +* lcd software driver. +******************************************************************************** +* History: +* mm/dd/yyyy +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LCD_H +#define __LCD_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* LCD Registers */ +#define R0 0x00 +#define R1 0x01 +#define R2 0x02 +#define R3 0x03 +#define R5 0x05 +#define R6 0x06 +#define R13 0x0D +#define R14 0x0E +#define R15 0x0F +#define R16 0x10 +#define R17 0x11 +#define R18 0x12 +#define R19 0x13 +#define R20 0x14 +#define R21 0x15 +#define R22 0x16 +#define R23 0x17 +#define R24 0x18 +#define R25 0x19 +#define R26 0x1A +#define R27 0x1B +#define R28 0x1C +#define R29 0x1D +#define R30 0x1E +#define R31 0x1F +#define R32 0x20 +#define R36 0x24 +#define R37 0x25 +#define R40 0x28 +#define R43 0x2B +#define R45 0x2D +#define R49 0x31 +#define R50 0x32 +#define R51 0x33 +#define R52 0x34 +#define R53 0x35 +#define R55 0x37 +#define R59 0x3B +#define R60 0x3C +#define R61 0x3D +#define R62 0x3E +#define R63 0x3F +#define R64 0x40 +#define R65 0x41 +#define R66 0x42 +#define R67 0x43 +#define R68 0x44 +#define R69 0x45 +#define R70 0x46 +#define R71 0x47 +#define R72 0x48 +#define R73 0x49 +#define R74 0x4A +#define R75 0x4B +#define R76 0x4C +#define R77 0x4D +#define R78 0x4E +#define R79 0x4F +#define R80 0x50 +#define R118 0x76 +#define R134 0x86 +#define R135 0x87 +#define R136 0x88 +#define R137 0x89 +#define R139 0x8B +#define R140 0x8C +#define R141 0x8D +#define R143 0x8F +#define R144 0x90 +#define R145 0x91 +#define R146 0x92 +#define R147 0x93 +#define R148 0x94 +#define R149 0x95 +#define R150 0x96 +#define R151 0x97 +#define R152 0x98 +#define R153 0x99 +#define R154 0x9A +#define R157 0x9D +#define R192 0xC0 +#define R193 0xC1 + +/* LCD Control pins */ +#define CtrlPin_NCS GPIO_Pin_2 /* PB.02 */ +#define CtrlPin_RS GPIO_Pin_7 /* PD.07 */ +#define CtrlPin_NWR GPIO_Pin_15 /* PD.15 */ + +/* LCD color */ +#define White 0xFFFF +#define Black 0x0000 +#define Blue 0x001F +#define Orange 0x051F +#define Red 0xF800 +#define Magenta 0xF81F +#define Green 0x07E0 +#define Cyan 0x7FFF +#define Yellow 0xFFE0 + +#define Line0 0 +#define Line1 24 +#define Line2 48 +#define Line3 72 +#define Line4 96 +#define Line5 120 +#define Line6 144 +#define Line7 168 +#define Line8 192 +#define Line9 216 + +#define Horizontal 0x00 +#define Vertical 0x01 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/*----- High layer function -----*/ +void LCD_Init(void); +void LCD_SetTextColor(vu16 Color); +void LCD_SetBackColor(vu16 Color); +void LCD_ClearLine(u8 Line); +void LCD_Clear(void); +void LCD_SetCursor(u8 Xpos, u16 Ypos); +void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c); +void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii); +void LCD_DisplayStringLine(u8 Line, u8 *ptr); +void LCD_DisplayString(u8 Line, u8 *ptr); +void LCD_ScrollText(u8 Line, u8 *ptr); +void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width); +void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction); +void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width); +void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius); +void LCD_DrawMonoPict(uc32 *Pict); +void LCD_DrawBMP(u32 BmpAddress); + +/*----- Medium layer function -----*/ +void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue); +u8 LCD_ReadReg(u8 LCD_Reg); +void LCD_WriteRAM(u16 RGB_Code); +u16 LCD_ReadRAM(void); +void LCD_PowerOn(void); +void LCD_DisplayOn(void); +void LCD_DisplayOff(void); + +/*----- Low layer function -----*/ +void LCD_CtrlLinesConfig(void); +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal); +void LCD_SPIConfig(void); + +#endif /* __LCD_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/misc.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/misc.h new file mode 100644 index 0000000..e8b2dd7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/misc.h @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the + * miscellaneous firmware library functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /* 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /* 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /* 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /* 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /* 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/spi_flash.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/spi_flash.h new file mode 100644 index 0000000..5bd8a96 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/spi_flash.h @@ -0,0 +1,53 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : spi_flash.h +* Author : MCD Application Team +* Date First Issued : 02/05/2007 +* Description : Header for spi_flash.c file. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPI_FLASH_H +#define __SPI_FLASH_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define Low 0x00 /* Chip Select line low */ +#define High 0x01 /* Chip Select line high */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/*----- High layer function -----*/ +void SPI_FLASH_Init(void); +void SPI_FLASH_SectorErase(u32 SectorAddr); +void SPI_FLASH_BulkErase(void); +void SPI_FLASH_PageWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite); +void SPI_FLASH_BufferWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite); +void SPI_FLASH_BufferRead(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead); +u32 SPI_FLASH_ReadID(void); +void SPI_FLASH_StartReadSequence(u32 ReadAddr); + +/*----- Low layer function -----*/ +u8 SPI_FLASH_ReadByte(void); +void SPI_FLASH_ChipSelect(u8 State); +u8 SPI_FLASH_SendByte(u8 byte); +u16 SPI_FLASH_SendHalfWord(u16 HalfWord); +void SPI_FLASH_WriteEnable(void); +void SPI_FLASH_WaitForWriteEnd(void); + +#endif /* __SPI_FLASH_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_adc.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_adc.h new file mode 100644 index 0000000..8e90539 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_adc.h @@ -0,0 +1,269 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_adc.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* ADC firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* ADC Init structure definition */ +typedef struct +{ + u32 ADC_Mode; + FunctionalState ADC_ScanConvMode; + FunctionalState ADC_ContinuousConvMode; + u32 ADC_ExternalTrigConv; + u32 ADC_DataAlign; + u8 ADC_NbrOfChannel; +}ADC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* ADC dual mode -------------------------------------------------------------*/ +#define ADC_Mode_Independent ((u32)0x00000000) +#define ADC_Mode_RegInjecSimult ((u32)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000) +#define ADC_Mode_InjecSimult ((u32)0x00050000) +#define ADC_Mode_RegSimult ((u32)0x00060000) +#define ADC_Mode_FastInterl ((u32)0x00070000) +#define ADC_Mode_SlowInterl ((u32)0x00080000) +#define ADC_Mode_AlterTrig ((u32)0x00090000) + +#define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \ + (MODE == ADC_Mode_RegInjecSimult) || \ + (MODE == ADC_Mode_RegSimult_AlterTrig) || \ + (MODE == ADC_Mode_InjecSimult_FastInterl) || \ + (MODE == ADC_Mode_InjecSimult_SlowInterl) || \ + (MODE == ADC_Mode_InjecSimult) || \ + (MODE == ADC_Mode_RegSimult) || \ + (MODE == ADC_Mode_FastInterl) || \ + (MODE == ADC_Mode_SlowInterl) || \ + (MODE == ADC_Mode_AlterTrig)) + +/* ADC extrenal trigger sources for regular channels conversion --------------*/ +#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000) +#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000) +#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11 ((u32)0x000C0000) +#define ADC_ExternalTrigConv_None ((u32)0x000E0000) + +#define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \ + (TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \ + (TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \ + (TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \ + (TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \ + (TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \ + (TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \ + (TRIG1 == ADC_ExternalTrigConv_None)) + +/* ADC data align ------------------------------------------------------------*/ +#define ADC_DataAlign_Right ((u32)0x00000000) +#define ADC_DataAlign_Left ((u32)0x00000800) + +#define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \ + (ALIGN == ADC_DataAlign_Left)) + +/* ADC channels --------------------------------------------------------------*/ +#define ADC_Channel_0 ((u8)0x00) +#define ADC_Channel_1 ((u8)0x01) +#define ADC_Channel_2 ((u8)0x02) +#define ADC_Channel_3 ((u8)0x03) +#define ADC_Channel_4 ((u8)0x04) +#define ADC_Channel_5 ((u8)0x05) +#define ADC_Channel_6 ((u8)0x06) +#define ADC_Channel_7 ((u8)0x07) +#define ADC_Channel_8 ((u8)0x08) +#define ADC_Channel_9 ((u8)0x09) +#define ADC_Channel_10 ((u8)0x0A) +#define ADC_Channel_11 ((u8)0x0B) +#define ADC_Channel_12 ((u8)0x0C) +#define ADC_Channel_13 ((u8)0x0D) +#define ADC_Channel_14 ((u8)0x0E) +#define ADC_Channel_15 ((u8)0x0F) +#define ADC_Channel_16 ((u8)0x10) +#define ADC_Channel_17 ((u8)0x11) + +#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \ + (CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \ + (CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \ + (CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \ + (CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \ + (CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \ + (CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \ + (CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \ + (CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17)) + +/* ADC sampling times --------------------------------------------------------*/ +#define ADC_SampleTime_1Cycles5 ((u8)0x00) +#define ADC_SampleTime_7Cycles5 ((u8)0x01) +#define ADC_SampleTime_13Cycles5 ((u8)0x02) +#define ADC_SampleTime_28Cycles5 ((u8)0x03) +#define ADC_SampleTime_41Cycles5 ((u8)0x04) +#define ADC_SampleTime_55Cycles5 ((u8)0x05) +#define ADC_SampleTime_71Cycles5 ((u8)0x06) +#define ADC_SampleTime_239Cycles5 ((u8)0x07) + +#define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \ + (TIME == ADC_SampleTime_7Cycles5) || \ + (TIME == ADC_SampleTime_13Cycles5) || \ + (TIME == ADC_SampleTime_28Cycles5) || \ + (TIME == ADC_SampleTime_41Cycles5) || \ + (TIME == ADC_SampleTime_55Cycles5) || \ + (TIME == ADC_SampleTime_71Cycles5) || \ + (TIME == ADC_SampleTime_239Cycles5)) + +/* ADC extrenal trigger sources for injected channels conversion -------------*/ +#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((u32)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000) + +#define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + (TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \ + (TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + (TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \ + (TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \ + (TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + (TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \ + (TRIG == ADC_ExternalTrigInjecConv_None)) + +/* ADC injected channel selection --------------------------------------------*/ +#define ADC_InjectedChannel_1 ((u8)0x14) +#define ADC_InjectedChannel_2 ((u8)0x18) +#define ADC_InjectedChannel_3 ((u8)0x1C) +#define ADC_InjectedChannel_4 ((u8)0x20) + +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \ + (CHANNEL == ADC_InjectedChannel_2) || \ + (CHANNEL == ADC_InjectedChannel_3) || \ + (CHANNEL == ADC_InjectedChannel_4)) + +/* ADC analog watchdog selection ---------------------------------------------*/ +#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000) +#define ADC_AnalogWatchdog_None ((u32)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_None)) + +/* ADC interrupts definition -------------------------------------------------*/ +#define ADC_IT_EOC ((u16)0x0220) +#define ADC_IT_AWD ((u16)0x0140) +#define ADC_IT_JEOC ((u16)0x0480) + +#define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00)) +#define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \ + (IT == ADC_IT_JEOC)) + +/* ADC flags definition ------------------------------------------------------*/ +#define ADC_FLAG_AWD ((u8)0x01) +#define ADC_FLAG_EOC ((u8)0x02) +#define ADC_FLAG_JEOC ((u8)0x04) +#define ADC_FLAG_JSTRT ((u8)0x08) +#define ADC_FLAG_STRT ((u8)0x10) + +#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \ + (FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \ + (FLAG == ADC_FLAG_STRT)) + +/* ADC thresholds ------------------------------------------------------------*/ +#define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF) + +/* ADC injected offset -------------------------------------------------------*/ +#define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF) + +/* ADC injected length -------------------------------------------------------*/ +#define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4)) + +/* ADC injected rank ---------------------------------------------------------*/ +#define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4)) + +/* ADC regular length --------------------------------------------------------*/ +#define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10)) + +/* ADC regular rank ----------------------------------------------------------*/ +#define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10)) + +/* ADC regular discontinuous mode number -------------------------------------*/ +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +u16 ADC_GetConversionValue(ADC_TypeDef* ADCx); +u32 ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset); +u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel); +void ADC_TempSensorCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT); + +#endif /*__STM32F10x_ADC_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_bkp.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_bkp.h new file mode 100644 index 0000000..82224d1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_bkp.h @@ -0,0 +1,73 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_bkp.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* BKP firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Tamper Pin active level*/ +#define BKP_TamperPinLevel_High ((u16)0x0000) +#define BKP_TamperPinLevel_Low ((u16)0x0001) + +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) ((LEVEL == BKP_TamperPinLevel_High) || \ + (LEVEL == BKP_TamperPinLevel_Low)) + +/* Data Backup Register */ +#define BKP_DR1 ((u16)0x0004) +#define BKP_DR2 ((u16)0x0008) +#define BKP_DR3 ((u16)0x000C) +#define BKP_DR4 ((u16)0x0010) +#define BKP_DR5 ((u16)0x0014) +#define BKP_DR6 ((u16)0x0018) +#define BKP_DR7 ((u16)0x001C) +#define BKP_DR8 ((u16)0x0020) +#define BKP_DR9 ((u16)0x0024) +#define BKP_DR10 ((u16)0x0028) + +#define IS_BKP_DR(DR) ((DR == BKP_DR1) || (DR == BKP_DR2) || (DR == BKP_DR3) || \ + (DR == BKP_DR4) || (DR == BKP_DR5) || (DR == BKP_DR6) || \ + (DR == BKP_DR7) || (DR == BKP_DR8) || (DR == BKP_DR9) || \ + (DR == BKP_DR10)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) (VALUE <= 0x7F) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState); +void BKP_SetRTCCalibrationValue(u8 CalibrationValue); +void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data); +u16 BKP_ReadBackupRegister(u16 BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#endif /* __STM32F10x_BKP_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_can.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_can.h new file mode 100644 index 0000000..bd7f538 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_can.h @@ -0,0 +1,269 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_can.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* CAN firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* CAN init structure definition */ +typedef struct +{ + FunctionalState CAN_TTCM; + FunctionalState CAN_ABOM; + FunctionalState CAN_AWUM; + FunctionalState CAN_NART; + FunctionalState CAN_RFLM; + FunctionalState CAN_TXFP; + u8 CAN_Mode; + u8 CAN_SJW; + u8 CAN_BS1; + u8 CAN_BS2; + u8 CAN_Clock; + u16 CAN_Prescaler; +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + u8 CAN_FilterNumber; + u8 CAN_FilterMode; + u8 CAN_FilterScale; + u16 CAN_FilterIdHigh; + u16 CAN_FilterIdLow; + u16 CAN_FilterMaskIdHigh; + u16 CAN_FilterMaskIdLow; + u16 CAN_FilterFIFOAssignment; + FunctionalState CAN_FilterActivation; +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + u32 StdId; + u32 ExtId; + u8 IDE; + u8 RTR; + u8 DLC; + u8 Data[8]; +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + u32 StdId; + u32 ExtId; + u8 IDE; + u8 RTR; + u8 DLC; + u8 Data[8]; + u8 FMI; +} CanRxMsg; + +/* Exported constants --------------------------------------------------------*/ + +/* CAN sleep constants */ +#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */ +#define CANINITOK ((u8)0x01) /* CAN initialization failed */ + +/* CAN operating mode */ +#define CAN_Mode_Normal ((u8)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((u8)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) ((MODE == CAN_Mode_Normal) || (MODE == CAN_Mode_LoopBack)|| \ + (MODE == CAN_Mode_Silent) || (MODE == CAN_Mode_Silent_LoopBack)) + +/* CAN synchronisation jump width */ +#define CAN_SJW_0tq ((u8)0x00) /* 0 time quantum */ +#define CAN_SJW_1tq ((u8)0x01) /* 1 time quantum */ +#define CAN_SJW_2tq ((u8)0x02) /* 2 time quantum */ +#define CAN_SJW_3tq ((u8)0x03) /* 3 time quantum */ + +#define IS_CAN_SJW(SJW) ((SJW == CAN_SJW_0tq) || (SJW == CAN_SJW_1tq)|| \ + (SJW == CAN_SJW_2tq) || (SJW == CAN_SJW_3tq)) + +/* time quantum in bit segment 1 */ +#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */ + +#define IS_CAN_BS1(BS1) (BS1 <= CAN_BS1_16tq) + +/* time quantum in bit segment 2 */ +#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */ + +#define IS_CAN_BS2(BS2) (BS2 <= CAN_BS2_8tq) + +/* CAN clock selected */ +#define CAN_Clock_8MHz ((u8)0x00) /* 8MHz XTAL clock selected */ +#define CAN_Clock_APB ((u8)0x01) /* APB clock selected */ + +#define IS_CAN_CLOCK(CLOCK) ((CLOCK == CAN_Clock_8MHz) || (CLOCK == CAN_Clock_APB)) + +/* CAN clock prescaler */ +#define IS_CAN_PRESCALER(PRESCALER) ((PRESCALER >= 1) && (PRESCALER <= 1024)) + +/* CAN filter number */ +#define IS_CAN_FILTER_NUMBER(NUMBER) (NUMBER <= 13) + +/* CAN filter mode */ +#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */ +#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) ((MODE == CAN_FilterMode_IdMask) || \ + (MODE == CAN_FilterMode_IdList)) + +/* CAN filter scale */ +#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */ +#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */ + +#define IS_CAN_FILTER_SCALE(SCALE) ((SCALE == CAN_FilterScale_16bit) || \ + (SCALE == CAN_FilterScale_32bit)) + +/* CAN filter FIFO assignation */ +#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */ + +#define IS_CAN_FILTER_FIFO(FIFO) ((FIFO == CAN_FilterFIFO0) || \ + (FIFO == CAN_FilterFIFO1)) + +/* CAN Tx */ +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) (TRANSMITMAILBOX <= ((u8)0x02)) +#define IS_CAN_STDID(STDID) (STDID <= ((u32)0x7FF)) +#define IS_CAN_EXTID(EXTID) (EXTID <= ((u32)0x3FFFF)) +#define IS_CAN_DLC(DLC) (DLC <= ((u8)0x08)) + +/* CAN identifier type */ +#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */ +#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */ + +#define IS_CAN_IDTYPE(IDTYPE) ((IDTYPE == CAN_ID_STD) || (IDTYPE == CAN_ID_EXT)) + +/* CAN remote transmission request */ +#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */ +#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */ + +#define IS_CAN_RTR(RTR) ((RTR == CAN_RTR_DATA) || (RTR == CAN_RTR_REMOTE)) + +/* CAN transmit constants */ +#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */ +#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */ +#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */ +#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN receive FIFO number constants */ +#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */ +#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */ + +#define IS_CAN_FIFO(FIFO) ((FIFO == CAN_FIFO0) || (FIFO == CAN_FIFO1)) + +/* CAN sleep constants */ +#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */ +#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */ + +/* CAN wake up constants */ +#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */ +#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */ + +/* CAN flags */ +#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */ + +#define IS_CAN_FLAG(FLAG) ((FLAG == CAN_FLAG_EWG) || (FLAG == CAN_FLAG_EPV) ||\ + (FLAG == CAN_FLAG_BOF)) + +/* CAN interrupts */ +#define CAN_IT_RQCP0 ((u8)0x05) /* Request completed mailbox 0 */ +#define CAN_IT_RQCP1 ((u8)0x06) /* Request completed mailbox 1 */ +#define CAN_IT_RQCP2 ((u8)0x07) /* Request completed mailbox 2 */ +#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */ +#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */ +#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */ +#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */ +#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */ +#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */ +#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */ +#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */ +#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */ +#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */ +#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */ +#define CAN_IT_ERR ((u32)0x00008000) /* Error */ +#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */ +#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */ + +#define IS_CAN_IT(IT) ((IT == CAN_IT_RQCP0) || (IT == CAN_IT_RQCP1) ||\ + (IT == CAN_IT_RQCP2) || (IT == CAN_IT_TME) ||\ + (IT == CAN_IT_FMP0) || (IT == CAN_IT_FF0) ||\ + (IT == CAN_IT_FOV0) || (IT == CAN_IT_FMP1) ||\ + (IT == CAN_IT_FF1) || (IT == CAN_IT_FOV1) ||\ + (IT == CAN_IT_EWG) || (IT == CAN_IT_EPV) ||\ + (IT == CAN_IT_BOF) || (IT == CAN_IT_LEC) ||\ + (IT == CAN_IT_ERR) || (IT == CAN_IT_WKU) ||\ + (IT == CAN_IT_SLK)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported function protypes ----------------------------------------------- */ +void CAN_DeInit(void); +u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState); +u8 CAN_Transmit(CanTxMsg* TxMessage); +u32 CAN_TransmitStatus(u8 TransmitMailbox); +void CAN_CancelTransmit(u8 Mailbox); +void CAN_FIFORelease(u8 FIFONumber); +u8 CAN_MessagePending(u8 FIFONumber); +void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage); +u8 CAN_Sleep(void); +u8 CAN_WakeUp(void); +FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG); +void CAN_ClearFlag(u32 CAN_FLAG); +ITStatus CAN_GetITStatus(u32 CAN_IT); +void CAN_ClearITPendingBit(u32 CAN_IT); + +#endif /* __STM32F10x_CAN_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h new file mode 100644 index 0000000..ef33aa3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h @@ -0,0 +1,85 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions + * @{ + */ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#endif /* __STM32F10x_CRC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h new file mode 100644 index 0000000..59caa27 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h @@ -0,0 +1,261 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; + uint32_t DAC_WaveGeneration; + uint32_t DAC_LFSRUnmask_TriangleAmplitude; + uint32_t DAC_OutputBuffer; +}DAC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) +#define DAC_Trigger_Software ((uint32_t)0x0000003C) + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_noise_wave_generation_mask_triangle_wave_generation_max_amplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +#endif /*__STM32F10x_DAC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h new file mode 100644 index 0000000..7af3b66 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the DBGMCU + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions + * @{ + */ + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#endif /* __STM32F10x_DBGMCU_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dma.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dma.h new file mode 100644 index 0000000..95274ad --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dma.h @@ -0,0 +1,224 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_dma.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* DMA firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* DMA Init structure definition */ +typedef struct +{ + u32 DMA_PeripheralBaseAddr; + u32 DMA_MemoryBaseAddr; + u32 DMA_DIR; + u32 DMA_BufferSize; + u32 DMA_PeripheralInc; + u32 DMA_MemoryInc; + u32 DMA_PeripheralDataSize; + u32 DMA_MemoryDataSize; + u32 DMA_Mode; + u32 DMA_Priority; + u32 DMA_M2M; +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* DMA data transfer direction -----------------------------------------------*/ +#define DMA_DIR_PeripheralDST ((u32)0x00000010) +#define DMA_DIR_PeripheralSRC ((u32)0x00000000) + +#define IS_DMA_DIR(DIR) ((DIR == DMA_DIR_PeripheralDST) || \ + (DIR == DMA_DIR_PeripheralSRC)) + +/* DMA peripheral incremented mode -------------------------------------------*/ +#define DMA_PeripheralInc_Enable ((u32)0x00000040) +#define DMA_PeripheralInc_Disable ((u32)0x00000000) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) ((STATE == DMA_PeripheralInc_Enable) || \ + (STATE == DMA_PeripheralInc_Disable)) + +/* DMA memory incremented mode -----------------------------------------------*/ +#define DMA_MemoryInc_Enable ((u32)0x00000080) +#define DMA_MemoryInc_Disable ((u32)0x00000000) + +#define IS_DMA_MEMORY_INC_STATE(STATE) ((STATE == DMA_MemoryInc_Enable) || \ + (STATE == DMA_MemoryInc_Disable)) + +/* DMA peripheral data size --------------------------------------------------*/ +#define DMA_PeripheralDataSize_Byte ((u32)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100) +#define DMA_PeripheralDataSize_Word ((u32)0x00000200) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) ((SIZE == DMA_PeripheralDataSize_Byte) || \ + (SIZE == DMA_PeripheralDataSize_HalfWord) || \ + (SIZE == DMA_PeripheralDataSize_Word)) + +/* DMA memory data size ------------------------------------------------------*/ +#define DMA_MemoryDataSize_Byte ((u32)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400) +#define DMA_MemoryDataSize_Word ((u32)0x00000800) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) ((SIZE == DMA_MemoryDataSize_Byte) || \ + (SIZE == DMA_MemoryDataSize_HalfWord) || \ + (SIZE == DMA_MemoryDataSize_Word)) + +/* DMA circular/normal mode --------------------------------------------------*/ +#define DMA_Mode_Circular ((u32)0x00000020) +#define DMA_Mode_Normal ((u32)0x00000000) + +#define IS_DMA_MODE(MODE) ((MODE == DMA_Mode_Circular) || (MODE == DMA_Mode_Normal)) + +/* DMA priority level --------------------------------------------------------*/ +#define DMA_Priority_VeryHigh ((u32)0x00003000) +#define DMA_Priority_High ((u32)0x00002000) +#define DMA_Priority_Medium ((u32)0x00001000) +#define DMA_Priority_Low ((u32)0x00000000) + +#define IS_DMA_PRIORITY(PRIORITY) ((PRIORITY == DMA_Priority_VeryHigh) || \ + (PRIORITY == DMA_Priority_High) || \ + (PRIORITY == DMA_Priority_Medium) || \ + (PRIORITY == DMA_Priority_Low)) + +/* DMA memory to memory ------------------------------------------------------*/ +#define DMA_M2M_Enable ((u32)0x00004000) +#define DMA_M2M_Disable ((u32)0x00000000) + +#define IS_DMA_M2M_STATE(STATE) ((STATE == DMA_M2M_Enable) || (STATE == DMA_M2M_Disable)) + +/* DMA interrupts definition -------------------------------------------------*/ +#define DMA_IT_TC ((u32)0x00000002) +#define DMA_IT_HT ((u32)0x00000004) +#define DMA_IT_TE ((u32)0x00000008) + +#define IS_DMA_CONFIG_IT(IT) (((IT & 0xFFFFFFF1) == 0x00) && (IT != 0x00)) + +#define DMA_IT_GL1 ((u32)0x00000001) +#define DMA_IT_TC1 ((u32)0x00000002) +#define DMA_IT_HT1 ((u32)0x00000004) +#define DMA_IT_TE1 ((u32)0x00000008) +#define DMA_IT_GL2 ((u32)0x00000010) +#define DMA_IT_TC2 ((u32)0x00000020) +#define DMA_IT_HT2 ((u32)0x00000040) +#define DMA_IT_TE2 ((u32)0x00000080) +#define DMA_IT_GL3 ((u32)0x00000100) +#define DMA_IT_TC3 ((u32)0x00000200) +#define DMA_IT_HT3 ((u32)0x00000400) +#define DMA_IT_TE3 ((u32)0x00000800) +#define DMA_IT_GL4 ((u32)0x00001000) +#define DMA_IT_TC4 ((u32)0x00002000) +#define DMA_IT_HT4 ((u32)0x00004000) +#define DMA_IT_TE4 ((u32)0x00008000) +#define DMA_IT_GL5 ((u32)0x00010000) +#define DMA_IT_TC5 ((u32)0x00020000) +#define DMA_IT_HT5 ((u32)0x00040000) +#define DMA_IT_TE5 ((u32)0x00080000) +#define DMA_IT_GL6 ((u32)0x00100000) +#define DMA_IT_TC6 ((u32)0x00200000) +#define DMA_IT_HT6 ((u32)0x00400000) +#define DMA_IT_TE6 ((u32)0x00800000) +#define DMA_IT_GL7 ((u32)0x01000000) +#define DMA_IT_TC7 ((u32)0x02000000) +#define DMA_IT_HT7 ((u32)0x04000000) +#define DMA_IT_TE7 ((u32)0x08000000) + +#define IS_DMA_CLEAR_IT(IT) (((IT & 0xF0000000) == 0x00) && (IT != 0x00)) +#define IS_DMA_GET_IT(IT) ((IT == DMA_IT_GL1) || (IT == DMA_IT_TC1) || \ + (IT == DMA_IT_HT1) || (IT == DMA_IT_TE1) || \ + (IT == DMA_IT_GL2) || (IT == DMA_IT_TC2) || \ + (IT == DMA_IT_HT2) || (IT == DMA_IT_TE2) || \ + (IT == DMA_IT_GL3) || (IT == DMA_IT_TC3) || \ + (IT == DMA_IT_HT3) || (IT == DMA_IT_TE3) || \ + (IT == DMA_IT_GL4) || (IT == DMA_IT_TC4) || \ + (IT == DMA_IT_HT4) || (IT == DMA_IT_TE4) || \ + (IT == DMA_IT_GL5) || (IT == DMA_IT_TC5) || \ + (IT == DMA_IT_HT5) || (IT == DMA_IT_TE5) || \ + (IT == DMA_IT_GL6) || (IT == DMA_IT_TC6) || \ + (IT == DMA_IT_HT6) || (IT == DMA_IT_TE6) || \ + (IT == DMA_IT_GL7) || (IT == DMA_IT_TC7) || \ + (IT == DMA_IT_HT7) || (IT == DMA_IT_TE7)) + +/* DMA flags definition ------------------------------------------------------*/ +#define DMA_FLAG_GL1 ((u32)0x00000001) +#define DMA_FLAG_TC1 ((u32)0x00000002) +#define DMA_FLAG_HT1 ((u32)0x00000004) +#define DMA_FLAG_TE1 ((u32)0x00000008) +#define DMA_FLAG_GL2 ((u32)0x00000010) +#define DMA_FLAG_TC2 ((u32)0x00000020) +#define DMA_FLAG_HT2 ((u32)0x00000040) +#define DMA_FLAG_TE2 ((u32)0x00000080) +#define DMA_FLAG_GL3 ((u32)0x00000100) +#define DMA_FLAG_TC3 ((u32)0x00000200) +#define DMA_FLAG_HT3 ((u32)0x00000400) +#define DMA_FLAG_TE3 ((u32)0x00000800) +#define DMA_FLAG_GL4 ((u32)0x00001000) +#define DMA_FLAG_TC4 ((u32)0x00002000) +#define DMA_FLAG_HT4 ((u32)0x00004000) +#define DMA_FLAG_TE4 ((u32)0x00008000) +#define DMA_FLAG_GL5 ((u32)0x00010000) +#define DMA_FLAG_TC5 ((u32)0x00020000) +#define DMA_FLAG_HT5 ((u32)0x00040000) +#define DMA_FLAG_TE5 ((u32)0x00080000) +#define DMA_FLAG_GL6 ((u32)0x00100000) +#define DMA_FLAG_TC6 ((u32)0x00200000) +#define DMA_FLAG_HT6 ((u32)0x00400000) +#define DMA_FLAG_TE6 ((u32)0x00800000) +#define DMA_FLAG_GL7 ((u32)0x01000000) +#define DMA_FLAG_TC7 ((u32)0x02000000) +#define DMA_FLAG_HT7 ((u32)0x04000000) +#define DMA_FLAG_TE7 ((u32)0x08000000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG & 0xF0000000) == 0x00) && (FLAG != 0x00)) +#define IS_DMA_GET_FLAG(FLAG) ((FLAG == DMA_FLAG_GL1) || (FLAG == DMA_FLAG_TC1) || \ + (FLAG == DMA_FLAG_HT1) || (FLAG == DMA_FLAG_TE1) || \ + (FLAG == DMA_FLAG_GL2) || (FLAG == DMA_FLAG_TC2) || \ + (FLAG == DMA_FLAG_HT2) || (FLAG == DMA_FLAG_TE2) || \ + (FLAG == DMA_FLAG_GL3) || (FLAG == DMA_FLAG_TC3) || \ + (FLAG == DMA_FLAG_HT3) || (FLAG == DMA_FLAG_TE3) || \ + (FLAG == DMA_FLAG_GL4) || (FLAG == DMA_FLAG_TC4) || \ + (FLAG == DMA_FLAG_HT4) || (FLAG == DMA_FLAG_TE4) || \ + (FLAG == DMA_FLAG_GL5) || (FLAG == DMA_FLAG_TC5) || \ + (FLAG == DMA_FLAG_HT5) || (FLAG == DMA_FLAG_TE5) || \ + (FLAG == DMA_FLAG_GL6) || (FLAG == DMA_FLAG_TC6) || \ + (FLAG == DMA_FLAG_HT6) || (FLAG == DMA_FLAG_TE6) || \ + (FLAG == DMA_FLAG_GL7) || (FLAG == DMA_FLAG_TC7) || \ + (FLAG == DMA_FLAG_HT7) || (FLAG == DMA_FLAG_TE7)) + +/* DMA Buffer Size -----------------------------------------------------------*/ +#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE >= 0x1) && (SIZE < 0x10000)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState); +u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx); +FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG); +void DMA_ClearFlag(u32 DMA_FLAG); +ITStatus DMA_GetITStatus(u32 DMA_IT); +void DMA_ClearITPendingBit(u32 DMA_IT); + +#endif /*__STM32F10x_DMA_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_exti.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_exti.h new file mode 100644 index 0000000..2c6d4b6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_exti.h @@ -0,0 +1,111 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_exti.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* EXTI firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* EXTI mode enumeration -----------------------------------------------------*/ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) ((MODE == EXTI_Mode_Interrupt) || (MODE == EXTI_Mode_Event)) + +/* EXTI Trigger enumeration --------------------------------------------------*/ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) ((TRIGGER == EXTI_Trigger_Rising) || \ + (TRIGGER == EXTI_Trigger_Falling) || \ + (TRIGGER == EXTI_Trigger_Rising_Falling)) + +/* EXTI Init Structure definition --------------------------------------------*/ +typedef struct +{ + u32 EXTI_Line; + EXTIMode_TypeDef EXTI_Mode; + EXTITrigger_TypeDef EXTI_Trigger; + FunctionalState EXTI_LineCmd; +}EXTI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* EXTI Lines ----------------------------------------------------------------*/ +#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16 + Connected to the PVD Output */ +#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17 + Connected to the RTC Alarm event */ +#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18 + Connected to the USB Wakeup from + suspend event */ + +#define IS_EXTI_LINE(LINE) (((LINE & (u32)0xFFF80000) == 0x00) && (LINE != (u16)0x00)) + +#define IS_GET_EXTI_LINE(LINE) ((LINE == EXTI_Line0) || (LINE == EXTI_Line1) || \ + (LINE == EXTI_Line2) || (LINE == EXTI_Line3) || \ + (LINE == EXTI_Line4) || (LINE == EXTI_Line5) || \ + (LINE == EXTI_Line6) || (LINE == EXTI_Line7) || \ + (LINE == EXTI_Line8) || (LINE == EXTI_Line9) || \ + (LINE == EXTI_Line10) || (LINE == EXTI_Line11) || \ + (LINE == EXTI_Line12) || (LINE == EXTI_Line13) || \ + (LINE == EXTI_Line14) || (LINE == EXTI_Line15) || \ + (LINE == EXTI_Line16) || (LINE == EXTI_Line17) || \ + (LINE == EXTI_Line18)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(u32 EXTI_Line); +FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line); +void EXTI_ClearFlag(u32 EXTI_Line); +ITStatus EXTI_GetITStatus(u32 EXTI_Line); +void EXTI_ClearITPendingBit(u32 EXTI_Line); + +#endif /* __STM32F10x_EXTI_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h new file mode 100644 index 0000000..5daf2b6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h @@ -0,0 +1,305 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @defgroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) +/** + * @} + */ + +/** @defgroup Half_Cycle_Enable_Disable + * @{ + */ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** + * @} + */ + +/** @defgroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ + +/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density + ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */ + +/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density + ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions + * @{ + */ + +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG); +void FLASH_ClearFlag(uint16_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +#endif /* __STM32F10x_FLASH_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h new file mode 100644 index 0000000..c1ea587 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h @@ -0,0 +1,598 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the FSMC + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/** @defgroup FSMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ + +typedef struct +{ + uint32_t FSMC_AddressSetupTime; + uint32_t FSMC_AddressHoldTime; + uint32_t FSMC_DataSetupTime; + uint32_t FSMC_BusTurnAroundDuration; + uint32_t FSMC_CLKDivision; + uint32_t FSMC_DataLatency; + uint32_t FSMC_AccessMode; +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; + uint32_t FSMC_DataAddressMux; + uint32_t FSMC_MemoryType; + uint32_t FSMC_MemoryDataWidth; + uint32_t FSMC_BurstAccessMode; + uint32_t FSMC_WaitSignalPolarity; + uint32_t FSMC_WrapMode; + uint32_t FSMC_WaitSignalActive; + uint32_t FSMC_WriteOperation; + uint32_t FSMC_WaitSignal; + uint32_t FSMC_ExtendedMode; + uint32_t FSMC_WriteBurst; + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the ExtendedMode is not used*/ + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;/* Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t FSMC_SetupTime; + uint32_t FSMC_WaitSetupTime; + uint32_t FSMC_HoldSetupTime; + uint32_t FSMC_HiZSetupTime; +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; + uint32_t FSMC_Waitfeature; + uint32_t FSMC_MemoryDataWidth; + uint32_t FSMC_ECC; + uint32_t FSMC_ECCPageSize; + uint32_t FSMC_TCLRSetupTime; + uint32_t FSMC_TARSetupTime; + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; + uint32_t FSMC_TCLRSetupTime; + uint32_t FSMC_TARSetupTime; + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /* FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_Banks_definitions + * @{ + */ + +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) +/** + * @} + */ + +/** @defgroup NOR_SRAM_Banks + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ + +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ + +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ + +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ + +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ + +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ + +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ + +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ + +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup NAND_and_PCCARD_Banks + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ + +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Data_Width + * @{ + */ +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC + * @{ + */ + +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ + +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ + +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ + +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ + +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ + +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ + +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ + +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ + +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ + +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Functions + * @{ + */ + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#endif /*__STM32F10x_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_gpio.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_gpio.h new file mode 100644 index 0000000..8d6ef84 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_gpio.h @@ -0,0 +1,195 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_gpio.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* GPIO firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Output Maximum frequency selection ----------------------------------------*/ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; + +#define IS_GPIO_SPEED(SPEED) ((SPEED == GPIO_Speed_10MHz) || (SPEED == GPIO_Speed_2MHz) || \ + (SPEED == GPIO_Speed_50MHz)) + +/* Configuration Mode enumeration --------------------------------------------*/ +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) ((MODE == GPIO_Mode_AIN) || (MODE == GPIO_Mode_IN_FLOATING) || \ + (MODE == GPIO_Mode_IPD) || (MODE == GPIO_Mode_IPU) || \ + (MODE == GPIO_Mode_Out_OD) || (MODE == GPIO_Mode_Out_PP) || \ + (MODE == GPIO_Mode_AF_OD) || (MODE == GPIO_Mode_AF_PP)) + +/* GPIO Init structure definition */ +typedef struct +{ + u16 GPIO_Pin; + GPIOSpeed_TypeDef GPIO_Speed; + GPIOMode_TypeDef GPIO_Mode; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) ((ACTION == Bit_RESET) || (ACTION == Bit_SET)) + +/* Exported constants --------------------------------------------------------*/ +/* GPIO pins define ----------------------------------------------------------*/ +#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */ + +#define IS_GPIO_PIN(PIN) (((PIN & (u16)0x00) == 0x00) && (PIN != (u16)0x00)) + +/* GPIO Remap define ---------------------------------------------------------*/ +#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN ((u32)0x001D4000) /* CAN Alternate Function mapping */ +#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */ +#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ + +#define IS_GPIO_REMAP(REMAP) ((REMAP == GPIO_Remap_SPI1) || (REMAP == GPIO_Remap_I2C1) || \ + (REMAP == GPIO_Remap_USART1) || (REMAP == GPIO_Remap_USART2) || \ + (REMAP == GPIO_PartialRemap_USART3) || (REMAP == GPIO_FullRemap_USART3) || \ + (REMAP == GPIO_PartialRemap_TIM1) || (REMAP == GPIO_FullRemap_TIM1) || \ + (REMAP == GPIO_PartialRemap1_TIM2) || (REMAP == GPIO_PartialRemap2_TIM2) || \ + (REMAP == GPIO_FullRemap_TIM2) || (REMAP == GPIO_PartialRemap_TIM3) || \ + (REMAP == GPIO_FullRemap_TIM3) || (REMAP == GPIO_Remap_TIM4) || \ + (REMAP == GPIO_Remap1_CAN) || (REMAP == GPIO_Remap2_CAN) || \ + (REMAP == GPIO_Remap_PD01) || (REMAP == GPIO_Remap_SWJ_NoJTRST) || \ + (REMAP == GPIO_Remap_SWJ_JTAGDisable) || (REMAP == GPIO_Remap_SWJ_Disable)) + +/* GPIO Port Sources ---------------------------------------------------------*/ +#define GPIO_PortSourceGPIOA ((u8)0x00) +#define GPIO_PortSourceGPIOB ((u8)0x01) +#define GPIO_PortSourceGPIOC ((u8)0x02) +#define GPIO_PortSourceGPIOD ((u8)0x03) +#define GPIO_PortSourceGPIOE ((u8)0x04) + +#define IS_GPIO_PORT_SOURCE(PORTSOURCE) ((PORTSOURCE == GPIO_PortSourceGPIOA) || \ + (PORTSOURCE == GPIO_PortSourceGPIOB) || \ + (PORTSOURCE == GPIO_PortSourceGPIOC) || \ + (PORTSOURCE == GPIO_PortSourceGPIOD) || \ + (PORTSOURCE == GPIO_PortSourceGPIOE)) + +/* GPIO Pin sources ----------------------------------------------------------*/ +#define GPIO_PinSource0 ((u8)0x00) +#define GPIO_PinSource1 ((u8)0x01) +#define GPIO_PinSource2 ((u8)0x02) +#define GPIO_PinSource3 ((u8)0x03) +#define GPIO_PinSource4 ((u8)0x04) +#define GPIO_PinSource5 ((u8)0x05) +#define GPIO_PinSource6 ((u8)0x06) +#define GPIO_PinSource7 ((u8)0x07) +#define GPIO_PinSource8 ((u8)0x08) +#define GPIO_PinSource9 ((u8)0x09) +#define GPIO_PinSource10 ((u8)0x0A) +#define GPIO_PinSource11 ((u8)0x0B) +#define GPIO_PinSource12 ((u8)0x0C) +#define GPIO_PinSource13 ((u8)0x0D) +#define GPIO_PinSource14 ((u8)0x0E) +#define GPIO_PinSource15 ((u8)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) ((PINSOURCE == GPIO_PinSource0) || \ + (PINSOURCE == GPIO_PinSource1) || \ + (PINSOURCE == GPIO_PinSource2) || \ + (PINSOURCE == GPIO_PinSource3) || \ + (PINSOURCE == GPIO_PinSource4) || \ + (PINSOURCE == GPIO_PinSource5) || \ + (PINSOURCE == GPIO_PinSource6) || \ + (PINSOURCE == GPIO_PinSource7) || \ + (PINSOURCE == GPIO_PinSource8) || \ + (PINSOURCE == GPIO_PinSource9) || \ + (PINSOURCE == GPIO_PinSource10) || \ + (PINSOURCE == GPIO_PinSource11) || \ + (PINSOURCE == GPIO_PinSource12) || \ + (PINSOURCE == GPIO_PinSource13) || \ + (PINSOURCE == GPIO_PinSource14) || \ + (PINSOURCE == GPIO_PinSource15)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); + +#endif /* __STM32F10x_GPIO_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_i2c.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_i2c.h new file mode 100644 index 0000000..d0d000c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_i2c.h @@ -0,0 +1,286 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_i2c.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* I2C firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* I2C Init structure definition */ +typedef struct +{ + u16 I2C_Mode; + u16 I2C_DutyCycle; + u16 I2C_OwnAddress1; + u16 I2C_Ack; + u16 I2C_AcknowledgedAddress; + u32 I2C_ClockSpeed; +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* I2C modes */ +#define I2C_Mode_I2C ((u16)0x0000) +#define I2C_Mode_SMBusDevice ((u16)0x0002) +#define I2C_Mode_SMBusHost ((u16)0x000A) + +#define IS_I2C_MODE(MODE) ((MODE == I2C_Mode_I2C) || \ + (MODE == I2C_Mode_SMBusDevice) || \ + (MODE == I2C_Mode_SMBusHost)) +/* I2C duty cycle in fast mode */ +#define I2C_DutyCycle_16_9 ((u16)0x4000) +#define I2C_DutyCycle_2 ((u16)0xBFFF) + +#define IS_I2C_DUTY_CYCLE(CYCLE) ((CYCLE == I2C_DutyCycle_16_9) || \ + (CYCLE == I2C_DutyCycle_2)) + +/* I2C cknowledgementy */ +#define I2C_Ack_Enable ((u16)0x0400) +#define I2C_Ack_Disable ((u16)0x0000) + +#define IS_I2C_ACK_STATE(STATE) ((STATE == I2C_Ack_Enable) || \ + (STATE == I2C_Ack_Disable)) + +/* I2C transfer direction */ +#define I2C_Direction_Transmitter ((u8)0x00) +#define I2C_Direction_Receiver ((u8)0x01) + +#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_Direction_Transmitter) || \ + (DIRECTION == I2C_Direction_Receiver)) + +/* I2C acknowledged address defines */ +#define I2C_AcknowledgedAddress_7bit ((u16)0x4000) +#define I2C_AcknowledgedAddress_10bit ((u16)0xC000) + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_AcknowledgedAddress_7bit) || \ + (ADDRESS == I2C_AcknowledgedAddress_10bit)) + +/* I2C registers */ +#define I2C_Register_CR1 ((u8)0x00) +#define I2C_Register_CR2 ((u8)0x04) +#define I2C_Register_OAR1 ((u8)0x08) +#define I2C_Register_OAR2 ((u8)0x0C) +#define I2C_Register_DR ((u8)0x10) +#define I2C_Register_SR1 ((u8)0x14) +#define I2C_Register_SR2 ((u8)0x18) +#define I2C_Register_CCR ((u8)0x1C) +#define I2C_Register_TRISE ((u8)0x20) + +#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_Register_CR1) || \ + (REGISTER == I2C_Register_CR2) || \ + (REGISTER == I2C_Register_OAR1) || \ + (REGISTER == I2C_Register_OAR2) || \ + (REGISTER == I2C_Register_DR) || \ + (REGISTER == I2C_Register_SR1) || \ + (REGISTER == I2C_Register_SR2) || \ + (REGISTER == I2C_Register_CCR) || \ + (REGISTER == I2C_Register_TRISE)) + +/* I2C SMBus alert pin level */ +#define I2C_SMBusAlert_Low ((u16)0x2000) +#define I2C_SMBusAlert_High ((u16)0xCFFF) + +#define IS_I2C_SMBUS_ALERT(ALERT) ((ALERT == I2C_SMBusAlert_Low) || \ + (ALERT == I2C_SMBusAlert_High)) + +/* I2C PEC position */ +#define I2C_PECPosition_Next ((u16)0x0800) +#define I2C_PECPosition_Current ((u16)0xF7FF) + +#define IS_I2C_PEC_POSITION(POSITION) ((POSITION == I2C_PECPosition_Next) || \ + (POSITION == I2C_PECPosition_Current)) + +/* I2C interrupts definition */ +#define I2C_IT_BUF ((u16)0x0400) +#define I2C_IT_EVT ((u16)0x0200) +#define I2C_IT_ERR ((u16)0x0100) + +#define IS_I2C_CONFIG_IT(IT) (((IT & (u16)0xF8FF) == 0x00) && (IT != 0x00)) + +/* I2C interrupts definition */ +#define I2C_IT_SMBALERT ((u32)0x10008000) +#define I2C_IT_TIMEOUT ((u32)0x10004000) +#define I2C_IT_PECERR ((u32)0x10001000) +#define I2C_IT_OVR ((u32)0x10000800) +#define I2C_IT_AF ((u32)0x10000400) +#define I2C_IT_ARLO ((u32)0x10000200) +#define I2C_IT_BERR ((u32)0x10000100) +#define I2C_IT_TXE ((u32)0x00000080) +#define I2C_IT_RXNE ((u32)0x00000040) +#define I2C_IT_STOPF ((u32)0x60000010) +#define I2C_IT_ADD10 ((u32)0x20000008) +#define I2C_IT_BTF ((u32)0x60000004) +#define I2C_IT_ADDR ((u32)0xA0000002) +#define I2C_IT_SB ((u32)0x20000001) + +#define IS_I2C_CLEAR_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \ + (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \ + (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \ + (IT == I2C_IT_BERR) || (IT == I2C_IT_STOPF) || \ + (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \ + (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB)) + +#define IS_I2C_GET_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \ + (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \ + (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \ + (IT == I2C_IT_BERR) || (IT == I2C_IT_TXE) || \ + (IT == I2C_IT_RXNE) || (IT == I2C_IT_STOPF) || \ + (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \ + (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB)) + +/* I2C flags definition */ +#define I2C_FLAG_DUALF ((u32)0x00800000) +#define I2C_FLAG_SMBHOST ((u32)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000) +#define I2C_FLAG_GENCALL ((u32)0x00100000) +#define I2C_FLAG_TRA ((u32)0x00040000) +#define I2C_FLAG_BUSY ((u32)0x00020000) +#define I2C_FLAG_MSL ((u32)0x00010000) +#define I2C_FLAG_SMBALERT ((u32)0x10008000) +#define I2C_FLAG_TIMEOUT ((u32)0x10004000) +#define I2C_FLAG_PECERR ((u32)0x10001000) +#define I2C_FLAG_OVR ((u32)0x10000800) +#define I2C_FLAG_AF ((u32)0x10000400) +#define I2C_FLAG_ARLO ((u32)0x10000200) +#define I2C_FLAG_BERR ((u32)0x10000100) +#define I2C_FLAG_TXE ((u32)0x00000080) +#define I2C_FLAG_RXNE ((u32)0x00000040) +#define I2C_FLAG_STOPF ((u32)0x60000010) +#define I2C_FLAG_ADD10 ((u32)0x20000008) +#define I2C_FLAG_BTF ((u32)0x60000004) +#define I2C_FLAG_ADDR ((u32)0xA0000002) +#define I2C_FLAG_SB ((u32)0x20000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((FLAG == I2C_FLAG_SMBALERT) || (FLAG == I2C_FLAG_TIMEOUT) || \ + (FLAG == I2C_FLAG_PECERR) || (FLAG == I2C_FLAG_OVR) || \ + (FLAG == I2C_FLAG_AF) || (FLAG == I2C_FLAG_ARLO) || \ + (FLAG == I2C_FLAG_BERR) || (FLAG == I2C_FLAG_STOPF) || \ + (FLAG == I2C_FLAG_ADD10) || (FLAG == I2C_FLAG_BTF) || \ + (FLAG == I2C_FLAG_ADDR) || (FLAG == I2C_FLAG_SB)) + +#define IS_I2C_GET_FLAG(FLAG) ((FLAG == I2C_FLAG_DUALF) || (FLAG == I2C_FLAG_SMBHOST) || \ + (FLAG == I2C_FLAG_SMBDEFAULT) || (FLAG == I2C_FLAG_GENCALL) || \ + (FLAG == I2C_FLAG_TRA) || (FLAG == I2C_FLAG_BUSY) || \ + (FLAG == I2C_FLAG_MSL) || (FLAG == I2C_FLAG_SMBALERT) || \ + (FLAG == I2C_FLAG_TIMEOUT) || (FLAG == I2C_FLAG_PECERR) || \ + (FLAG == I2C_FLAG_OVR) || (FLAG == I2C_FLAG_AF) || \ + (FLAG == I2C_FLAG_ARLO) || (FLAG == I2C_FLAG_BERR) || \ + (FLAG == I2C_FLAG_TXE) || (FLAG == I2C_FLAG_RXNE) || \ + (FLAG == I2C_FLAG_STOPF) || (FLAG == I2C_FLAG_ADD10) || \ + (FLAG == I2C_FLAG_BTF) || (FLAG == I2C_FLAG_ADDR) || \ + (FLAG == I2C_FLAG_SB)) + +/* I2C Events */ +/* EV1 */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */ + +/* EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */ + +/* EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */ + +/* EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */ + +/* EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */ + +/* EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */ + +/* EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/* EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/* EV3_1 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */ + +#define IS_I2C_EVENT(EVENT) ((EVENT == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + (EVENT == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + (EVENT == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + (EVENT == I2C_EVENT_MASTER_MODE_SELECT) || \ + (EVENT == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + (EVENT == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + (EVENT == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + (EVENT == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + (EVENT == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + (EVENT == I2C_EVENT_SLAVE_ACK_FAILURE)) + +/* I2C own address1 -----------------------------------------------------------*/ +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (ADDRESS1 <= 0x3FF) +/* I2C clock speed ------------------------------------------------------------*/ +#define IS_I2C_CLOCK_SPEED(SPEED) ((SPEED >= 0x1) && (SPEED <= 400000)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data); +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction); +u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +u8 I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle); +u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx); +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT); + +#endif /*__STM32F10x_I2C_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_it.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_it.h new file mode 100644 index 0000000..90ed398 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_it.h @@ -0,0 +1,86 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_it.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains the headers of the interrupt handlers. +******************************************************************************** +* History: +* mm/dd/yyyy: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMIException(void); +void HardFaultException(void); +void MemManageException(void); +void BusFaultException(void); +void UsageFaultException(void); +void DebugMonitor(void); +void SVCHandler(void); +void PendSVC(void); +void SysTickHandler(void); +void WWDG_IRQHandler(void); +void PVD_IRQHandler(void); +void TAMPER_IRQHandler(void); +void RTC_IRQHandler(void); +void FLASH_IRQHandler(void); +void RCC_IRQHandler(void); +void EXTI0_IRQHandler(void); +void EXTI1_IRQHandler(void); +void EXTI2_IRQHandler(void); +void EXTI3_IRQHandler(void); +void EXTI4_IRQHandler(void); +void DMAChannel1_IRQHandler(void); +void DMAChannel2_IRQHandler(void); +void DMAChannel3_IRQHandler(void); +void DMAChannel4_IRQHandler(void); +void DMAChannel5_IRQHandler(void); +void DMAChannel6_IRQHandler(void); +void DMAChannel7_IRQHandler(void); +void ADC_IRQHandler(void); +void USB_HP_CAN_TX_IRQHandler(void); +void USB_LP_CAN_RX0_IRQHandler(void); +void CAN_RX1_IRQHandler(void); +void CAN_SCE_IRQHandler(void); +void EXTI9_5_IRQHandler(void); +void TIM1_BRK_IRQHandler(void); +void TIM1_UP_IRQHandler(void); +void TIM1_TRG_COM_IRQHandler(void); +void TIM1_CC_IRQHandler(void); +void TIM2_IRQHandler(void); +void TIM3_IRQHandler(void); +void TIM4_IRQHandler(void); +void I2C1_EV_IRQHandler(void); +void I2C1_ER_IRQHandler(void); +void I2C2_EV_IRQHandler(void); +void I2C2_ER_IRQHandler(void); +void SPI1_IRQHandler(void); +void SPI2_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +void USART3_IRQHandler(void); +void EXTI15_10_IRQHandler(void); +void RTCAlarm_IRQHandler(void); +void USBWakeUp_IRQHandler(void); + +#endif /* __STM32F10x_IT_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_iwdg.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_iwdg.h new file mode 100644 index 0000000..7cfc6ed --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_iwdg.h @@ -0,0 +1,73 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_iwdg.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* IWDG firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Write access to IWDG_PR and IWDG_RLR registers */ +#define IWDG_WriteAccess_Enable ((u16)0x5555) +#define IWDG_WriteAccess_Disable ((u16)0x0000) + +#define IS_IWDG_WRITE_ACCESS(ACCESS) ((ACCESS == IWDG_WriteAccess_Enable) || \ + (ACCESS == IWDG_WriteAccess_Disable)) + +/* IWDG prescaler */ +#define IWDG_Prescaler_4 ((u8)0x00) +#define IWDG_Prescaler_8 ((u8)0x01) +#define IWDG_Prescaler_16 ((u8)0x02) +#define IWDG_Prescaler_32 ((u8)0x03) +#define IWDG_Prescaler_64 ((u8)0x04) +#define IWDG_Prescaler_128 ((u8)0x05) +#define IWDG_Prescaler_256 ((u8)0x06) + +#define IS_IWDG_PRESCALER(PRESCALER) ((PRESCALER == IWDG_Prescaler_4) || \ + (PRESCALER == IWDG_Prescaler_8) || \ + (PRESCALER == IWDG_Prescaler_16) || \ + (PRESCALER == IWDG_Prescaler_32) || \ + (PRESCALER == IWDG_Prescaler_64) || \ + (PRESCALER == IWDG_Prescaler_128)|| \ + (PRESCALER == IWDG_Prescaler_256)) + +/* IWDG Flag */ +#define IWDG_FLAG_PVU ((u16)0x0001) +#define IWDG_FLAG_RVU ((u16)0x0002) + +#define IS_IWDG_FLAG(FLAG) ((FLAG == IWDG_FLAG_PVU) || (FLAG == IWDG_FLAG_RVU)) + +#define IS_IWDG_RELOAD(RELOAD) (RELOAD <= 0xFFF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess); +void IWDG_SetPrescaler(u8 IWDG_Prescaler); +void IWDG_SetReload(u16 Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG); + +#endif /* __STM32F10x_IWDG_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_lib.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_lib.h new file mode 100644 index 0000000..26d4e41 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_lib.h @@ -0,0 +1,112 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_lib.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file includes the peripherals header files in the +* user application. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_LIB_H +#define __STM32F10x_LIB_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +#ifdef _ADC + #include "stm32f10x_adc.h" +#endif /*_ADC */ + +#ifdef _BKP + #include "stm32f10x_bkp.h" +#endif /*_BKP */ + +#ifdef _CAN + #include "stm32f10x_can.h" +#endif /*_CAN */ + +#ifdef _DMA + #include "stm32f10x_dma.h" +#endif /*_DMA */ + +#ifdef _EXTI + #include "stm32f10x_exti.h" +#endif /*_EXTI */ + +#ifdef _FLASH + #include "stm32f10x_flash.h" +#endif /*_FLASH */ + +#ifdef _GPIO + #include "stm32f10x_gpio.h" +#endif /*_GPIO */ + +#ifdef _I2C + #include "stm32f10x_i2c.h" +#endif /*_I2C */ + +#ifdef _IWDG + #include "stm32f10x_iwdg.h" +#endif /*_IWDG */ + +#ifdef _NVIC + #include "stm32f10x_nvic.h" +#endif /*_NVIC */ + +#ifdef _PWR + #include "stm32f10x_pwr.h" +#endif /*_PWR */ + +#ifdef _RCC + #include "stm32f10x_rcc.h" +#endif /*_RCC */ + +#ifdef _RTC + #include "stm32f10x_rtc.h" +#endif /*_RTC */ + +#ifdef _SPI + #include "stm32f10x_spi.h" +#endif /*_SPI */ + +#ifdef _SysTick + #include "stm32f10x_systick.h" +#endif /*_SysTick */ + +#ifdef _TIM1 + #include "stm32f10x_tim1.h" +#endif /*_TIM1 */ + +#ifdef _TIM + #include "stm32f10x_tim.h" +#endif /*_TIM */ + +#ifdef _USART + #include "stm32f10x_usart.h" +#endif /*_USART */ + +#ifdef _WWDG + #include "stm32f10x_wwdg.h" +#endif /*_WWDG */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void debug(void); + +#endif /* __STM32F10x_LIB_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_map.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_map.h new file mode 100644 index 0000000..f14f87a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_map.h @@ -0,0 +1,870 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_map.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the peripheral register's definitions +* and memory mapping. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_MAP_H +#define __STM32F10x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_conf.h" +#include "stm32f10x_type.h" +#include "cortexm3_macro.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------ Analog to Digital Converter -----------------------*/ +typedef struct +{ + vu32 SR; + vu32 CR1; + vu32 CR2; + vu32 SMPR1; + vu32 SMPR2; + vu32 JOFR1; + vu32 JOFR2; + vu32 JOFR3; + vu32 JOFR4; + vu32 HTR; + vu32 LTR; + vu32 SQR1; + vu32 SQR2; + vu32 SQR3; + vu32 JSQR; + vu32 JDR1; + vu32 JDR2; + vu32 JDR3; + vu32 JDR4; + vu32 DR; +} ADC_TypeDef; + +/*------------------------ Backup Registers ----------------------------------*/ +typedef struct +{ + u32 RESERVED0; + vu16 DR1; + u16 RESERVED1; + vu16 DR2; + u16 RESERVED2; + vu16 DR3; + u16 RESERVED3; + vu16 DR4; + u16 RESERVED4; + vu16 DR5; + u16 RESERVED5; + vu16 DR6; + u16 RESERVED6; + vu16 DR7; + u16 RESERVED7; + vu16 DR8; + u16 RESERVED8; + vu16 DR9; + u16 RESERVED9; + vu16 DR10; + u16 RESERVED10; + vu16 RTCCR; + u16 RESERVED11; + vu16 CR; + u16 RESERVED12; + vu16 CSR; + u16 RESERVED13; +} BKP_TypeDef; + +/*------------------------ Controller Area Network ---------------------------*/ +typedef struct +{ + vu32 TIR; + vu32 TDTR; + vu32 TDLR; + vu32 TDHR; +} CAN_TxMailBox_TypeDef; + +typedef struct +{ + vu32 RIR; + vu32 RDTR; + vu32 RDLR; + vu32 RDHR; +} CAN_FIFOMailBox_TypeDef; + +typedef struct +{ + vu32 FR0; + vu32 FR1; +} CAN_FilterRegister_TypeDef; + +typedef struct +{ + vu32 MCR; + vu32 MSR; + vu32 TSR; + vu32 RF0R; + vu32 RF1R; + vu32 IER; + vu32 ESR; + vu32 BTR; + u32 RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + u32 RESERVED1[12]; + vu32 FMR; + vu32 FM0R; + u32 RESERVED2[1]; + vu32 FS0R; + u32 RESERVED3[1]; + vu32 FFA0R; + u32 RESERVED4[1]; + vu32 FA0R; + u32 RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/*------------------------ DMA Controller ------------------------------------*/ +typedef struct +{ + vu32 CCR; + vu32 CNDTR; + vu32 CPAR; + vu32 CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + vu32 ISR; + vu32 IFCR; +} DMA_TypeDef; + +/*------------------------ External Interrupt/Event Controller ---------------*/ +typedef struct +{ + vu32 IMR; + vu32 EMR; + vu32 RTSR; + vu32 FTSR; + vu32 SWIER; + vu32 PR; +} EXTI_TypeDef; + +/*------------------------ FLASH and Option Bytes Registers ------------------*/ +typedef struct +{ + vu32 ACR; + vu32 KEYR; + vu32 OPTKEYR; + vu32 SR; + vu32 CR; + vu32 AR; + vu32 RESERVED; + vu32 OBR; + vu32 WRPR; +} FLASH_TypeDef; + +typedef struct +{ + vu16 RDP; + vu16 USER; + vu16 Data0; + vu16 Data1; + vu16 WRP0; + vu16 WRP1; + vu16 WRP2; + vu16 WRP3; +} OB_TypeDef; + +/*------------------------ General Purpose and Alternate Function IO ---------*/ +typedef struct +{ + vu32 CRL; + vu32 CRH; + vu32 IDR; + vu32 ODR; + vu32 BSRR; + vu32 BRR; + vu32 LCKR; +} GPIO_TypeDef; + +typedef struct +{ + vu32 EVCR; + vu32 MAPR; + vu32 EXTICR[4]; +} AFIO_TypeDef; + +/*------------------------ Inter-integrated Circuit Interface ----------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 OAR1; + u16 RESERVED2; + vu16 OAR2; + u16 RESERVED3; + vu16 DR; + u16 RESERVED4; + vu16 SR1; + u16 RESERVED5; + vu16 SR2; + u16 RESERVED6; + vu16 CCR; + u16 RESERVED7; + vu16 TRISE; + u16 RESERVED8; +} I2C_TypeDef; + +/*------------------------ Independent WATCHDOG ------------------------------*/ +typedef struct +{ + vu32 KR; + vu32 PR; + vu32 RLR; + vu32 SR; +} IWDG_TypeDef; + +/*------------------------ Nested Vectored Interrupt Controller --------------*/ +typedef struct +{ + vu32 Enable[2]; + u32 RESERVED0[30]; + vu32 Disable[2]; + u32 RSERVED1[30]; + vu32 Set[2]; + u32 RESERVED2[30]; + vu32 Clear[2]; + u32 RESERVED3[30]; + vu32 Active[2]; + u32 RESERVED4[62]; + vu32 Priority[11]; +} NVIC_TypeDef; + +typedef struct +{ + vu32 CPUID; + vu32 IRQControlState; + vu32 ExceptionTableOffset; + vu32 AIRC; + vu32 SysCtrl; + vu32 ConfigCtrl; + vu32 SystemPriority[3]; + vu32 SysHandlerCtrl; + vu32 ConfigFaultStatus; + vu32 HardFaultStatus; + vu32 DebugFaultStatus; + vu32 MemoryManageFaultAddr; + vu32 BusFaultAddr; +} SCB_TypeDef; + +/*------------------------ Power Controller ----------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CSR; +} PWR_TypeDef; + +/*------------------------ Reset and Clock Controller ------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFGR; + vu32 CIR; + vu32 APB2RSTR; + vu32 APB1RSTR; + vu32 AHBENR; + vu32 APB2ENR; + vu32 APB1ENR; + vu32 BDCR; + vu32 CSR; +} RCC_TypeDef; + +/*------------------------ Real-Time Clock -----------------------------------*/ +typedef struct +{ + vu16 CRH; + u16 RESERVED0; + vu16 CRL; + u16 RESERVED1; + vu16 PRLH; + u16 RESERVED2; + vu16 PRLL; + u16 RESERVED3; + vu16 DIVH; + u16 RESERVED4; + vu16 DIVL; + u16 RESERVED5; + vu16 CNTH; + u16 RESERVED6; + vu16 CNTL; + u16 RESERVED7; + vu16 ALRH; + u16 RESERVED8; + vu16 ALRL; + u16 RESERVED9; +} RTC_TypeDef; + +/*------------------------ Serial Peripheral Interface -----------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SR; + u16 RESERVED2; + vu16 DR; + u16 RESERVED3; + vu16 CRCPR; + u16 RESERVED4; + vu16 RXCRCR; + u16 RESERVED5; + vu16 TXCRCR; + u16 RESERVED6; + vu16 I2SCFGR; + u16 RESERVED7; + vu16 I2SPR; + u16 RESERVED8; + +} SPI_TypeDef; + +/*------------------------ SystemTick ----------------------------------------*/ +typedef struct +{ + vu32 CTRL; + vu32 LOAD; + vu32 VAL; + vuc32 CALIB; +} SysTick_TypeDef; + +/*------------------------ Advanced Control Timer ----------------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SMCR; + u16 RESERVED2; + vu16 DIER; + u16 RESERVED3; + vu16 SR; + u16 RESERVED4; + vu16 EGR; + u16 RESERVED5; + vu16 CCMR1; + u16 RESERVED6; + vu16 CCMR2; + u16 RESERVED7; + vu16 CCER; + u16 RESERVED8; + vu16 CNT; + u16 RESERVED9; + vu16 PSC; + u16 RESERVED10; + vu16 ARR; + u16 RESERVED11; + vu16 RCR; + u16 RESERVED12; + vu16 CCR1; + u16 RESERVED13; + vu16 CCR2; + u16 RESERVED14; + vu16 CCR3; + u16 RESERVED15; + vu16 CCR4; + u16 RESERVED16; + vu16 BDTR; + u16 RESERVED17; + vu16 DCR; + u16 RESERVED18; + vu16 DMAR; + u16 RESERVED19; +} TIM1_TypeDef; + +/*------------------------ General Purpose Timer -----------------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SMCR; + u16 RESERVED2; + vu16 DIER; + u16 RESERVED3; + vu16 SR; + u16 RESERVED4; + vu16 EGR; + u16 RESERVED5; + vu16 CCMR1; + u16 RESERVED6; + vu16 CCMR2; + u16 RESERVED7; + vu16 CCER; + u16 RESERVED8; + vu16 CNT; + u16 RESERVED9; + vu16 PSC; + u16 RESERVED10; + vu16 ARR; + u16 RESERVED11[3]; + vu16 CCR1; + u16 RESERVED12; + vu16 CCR2; + u16 RESERVED13; + vu16 CCR3; + u16 RESERVED14; + vu16 CCR4; + u16 RESERVED15[3]; + vu16 DCR; + u16 RESERVED16; + vu16 DMAR; + u16 RESERVED17; +} TIM_TypeDef; + +/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ +typedef struct +{ + vu16 SR; + u16 RESERVED0; + vu16 DR; + u16 RESERVED1; + vu16 BRR; + u16 RESERVED2; + vu16 CR1; + u16 RESERVED3; + vu16 CR2; + u16 RESERVED4; + vu16 CR3; + u16 RESERVED5; + vu16 GTPR; + u16 RESERVED6; +} USART_TypeDef; + +/*------------------------ Window WATCHDOG -----------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFR; + vu32 SR; +} WWDG_TypeDef; + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Peripheral and SRAM base address in the alias region */ +#define PERIPH_BB_BASE ((u32)0x42000000) +#define SRAM_BB_BASE ((u32)0x22000000) + +/* Peripheral and SRAM base address in the bit-band region */ +#define SRAM_BASE ((u32)0x20000000) +#define PERIPH_BASE ((u32)0x40000000) + +/* Flash refisters base address */ +#define FLASH_BASE ((u32)0x40022000) +/* Flash Option Bytes base address */ +#define OB_BASE ((u32)0x1FFFF800) + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +/* System Control Space memory map */ +#define SCS_BASE ((u32)0xE000E000) + +#define SysTick_BASE (SCS_BASE + 0x0010) +#define NVIC_BASE (SCS_BASE + 0x0100) +#define SCB_BASE (SCS_BASE + 0x0D00) + + +/******************************************************************************/ +/* IPs' declaration */ +/******************************************************************************/ + +/*------------------- Non Debug Mode -----------------------------------------*/ +#ifndef DEBUG +#ifdef _TIM2 + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#endif /*_TIM2 */ + +#ifdef _TIM3 + #define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#endif /*_TIM3 */ + +#ifdef _TIM4 + #define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#endif /*_TIM4 */ + +#ifdef _RTC + #define RTC ((RTC_TypeDef *) RTC_BASE) +#endif /*_RTC */ + +#ifdef _WWDG + #define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#endif /*_WWDG */ + +#ifdef _IWDG + #define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#endif /*_IWDG */ + +#ifdef _SPI2 + #define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#endif /*_SPI2 */ + +#ifdef _USART2 + #define USART2 ((USART_TypeDef *) USART2_BASE) +#endif /*_USART2 */ + +#ifdef _USART3 + #define USART3 ((USART_TypeDef *) USART3_BASE) +#endif /*_USART3 */ + +#ifdef _I2C1 + #define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#endif /*_I2C1 */ + +#ifdef _I2C2 + #define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#endif /*_I2C2 */ + +#ifdef _CAN + #define CAN ((CAN_TypeDef *) CAN_BASE) +#endif /*_CAN */ + +#ifdef _BKP + #define BKP ((BKP_TypeDef *) BKP_BASE) +#endif /*_BKP */ + +#ifdef _PWR + #define PWR ((PWR_TypeDef *) PWR_BASE) +#endif /*_PWR */ + +#ifdef _AFIO + #define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#endif /*_AFIO */ + +#ifdef _EXTI + #define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#endif /*_EXTI */ + +#ifdef _GPIOA + #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#endif /*_GPIOA */ + +#ifdef _GPIOB + #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#endif /*_GPIOB */ + +#ifdef _GPIOC + #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#endif /*_GPIOC */ + +#ifdef _GPIOD + #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#endif /*_GPIOD */ + +#ifdef _GPIOE + #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#endif /*_GPIOE */ + +#ifdef _ADC1 + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#endif /*_ADC1 */ + +#ifdef _ADC2 + #define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#endif /*_ADC2 */ + +#ifdef _TIM1 + #define TIM1 ((TIM1_TypeDef *) TIM1_BASE) +#endif /*_TIM1 */ + +#ifdef _SPI1 + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#endif /*_SPI1 */ + +#ifdef _USART1 + #define USART1 ((USART_TypeDef *) USART1_BASE) +#endif /*_USART1 */ + +#ifdef _DMA + #define DMA ((DMA_TypeDef *) DMA_BASE) +#endif /*_DMA */ + +#ifdef _DMA_Channel1 + #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE) +#endif /*_DMA_Channel1 */ + +#ifdef _DMA_Channel2 + #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE) +#endif /*_DMA_Channel2 */ + +#ifdef _DMA_Channel3 + #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE) +#endif /*_DMA_Channel3 */ + +#ifdef _DMA_Channel4 + #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE) +#endif /*_DMA_Channel4 */ + +#ifdef _DMA_Channel5 + #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE) +#endif /*_DMA_Channel5 */ + +#ifdef _DMA_Channel6 + #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE) +#endif /*_DMA_Channel6 */ + +#ifdef _DMA_Channel7 + #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE) +#endif /*_DMA_Channel7 */ + +#ifdef _FLASH + #define FLASH ((FLASH_TypeDef *) FLASH_BASE) + #define OB ((OB_TypeDef *) OB_BASE) +#endif /*_FLASH */ + +#ifdef _RCC + #define RCC ((RCC_TypeDef *) RCC_BASE) +#endif /*_RCC */ + +#ifdef _SysTick + #define SysTick ((SysTick_TypeDef *) SysTick_BASE) +#endif /*_SysTick */ + +#ifdef _NVIC + #define NVIC ((NVIC_TypeDef *) NVIC_BASE) +#endif /*_NVIC */ + +#ifdef _SCB + #define SCB ((SCB_TypeDef *) SCB_BASE) +#endif /*_SCB */ +/*---------------------- Debug Mode -----------------------------------------*/ +#else /* DEBUG */ +#ifdef _TIM2 + EXT TIM_TypeDef *TIM2; +#endif /*_TIM2 */ + +#ifdef _TIM3 + EXT TIM_TypeDef *TIM3; +#endif /*_TIM3 */ + +#ifdef _TIM4 + EXT TIM_TypeDef *TIM4; +#endif /*_TIM4 */ + +#ifdef _RTC + EXT RTC_TypeDef *RTC; +#endif /*_RTC */ + +#ifdef _WWDG + EXT WWDG_TypeDef *WWDG; +#endif /*_WWDG */ + +#ifdef _IWDG + EXT IWDG_TypeDef *IWDG; +#endif /*_IWDG */ + +#ifdef _SPI2 + EXT SPI_TypeDef *SPI2; +#endif /*_SPI2 */ + +#ifdef _USART2 + EXT USART_TypeDef *USART2; +#endif /*_USART2 */ + +#ifdef _USART3 + EXT USART_TypeDef *USART3; +#endif /*_USART3 */ + +#ifdef _I2C1 + EXT I2C_TypeDef *I2C1; +#endif /*_I2C1 */ + +#ifdef _I2C2 + EXT I2C_TypeDef *I2C2; +#endif /*_I2C2 */ + +#ifdef _CAN + EXT CAN_TypeDef *CAN; +#endif /*_CAN */ + +#ifdef _BKP + EXT BKP_TypeDef *BKP; +#endif /*_BKP */ + +#ifdef _PWR + EXT PWR_TypeDef *PWR; +#endif /*_PWR */ + +#ifdef _AFIO + EXT AFIO_TypeDef *AFIO; +#endif /*_AFIO */ + +#ifdef _EXTI + EXT EXTI_TypeDef *EXTI; +#endif /*_EXTI */ + +#ifdef _GPIOA + EXT GPIO_TypeDef *GPIOA; +#endif /*_GPIOA */ + +#ifdef _GPIOB + EXT GPIO_TypeDef *GPIOB; +#endif /*_GPIOB */ + +#ifdef _GPIOC + EXT GPIO_TypeDef *GPIOC; +#endif /*_GPIOC */ + +#ifdef _GPIOD + EXT GPIO_TypeDef *GPIOD; +#endif /*_GPIOD */ + +#ifdef _GPIOE + EXT GPIO_TypeDef *GPIOE; +#endif /*_GPIOE */ + +#ifdef _ADC1 + EXT ADC_TypeDef *ADC1; +#endif /*_ADC1 */ + +#ifdef _ADC2 + EXT ADC_TypeDef *ADC2; +#endif /*_ADC2 */ + +#ifdef _TIM1 + EXT TIM1_TypeDef *TIM1; +#endif /*_TIM1 */ + +#ifdef _SPI1 + EXT SPI_TypeDef *SPI1; +#endif /*_SPI1 */ + +#ifdef _USART1 + EXT USART_TypeDef *USART1; +#endif /*_USART1 */ + +#ifdef _DMA + EXT DMA_TypeDef *DMA; +#endif /*_DMA */ + +#ifdef _DMA_Channel1 + EXT DMA_Channel_TypeDef *DMA_Channel1; +#endif /*_DMA_Channel1 */ + +#ifdef _DMA_Channel2 + EXT DMA_Channel_TypeDef *DMA_Channel2; +#endif /*_DMA_Channel2 */ + +#ifdef _DMA_Channel3 + EXT DMA_Channel_TypeDef *DMA_Channel3; +#endif /*_DMA_Channel3 */ + +#ifdef _DMA_Channel4 + EXT DMA_Channel_TypeDef *DMA_Channel4; +#endif /*_DMA_Channel4 */ + +#ifdef _DMA_Channel5 + EXT DMA_Channel_TypeDef *DMA_Channel5; +#endif /*_DMA_Channel5 */ + +#ifdef _DMA_Channel6 + EXT DMA_Channel_TypeDef *DMA_Channel6; +#endif /*_DMA_Channel6 */ + +#ifdef _DMA_Channel7 + EXT DMA_Channel_TypeDef *DMA_Channel7; +#endif /*_DMA_Channel7 */ + +#ifdef _FLASH + EXT FLASH_TypeDef *FLASH; + EXT OB_TypeDef *OB; +#endif /*_FLASH */ + +#ifdef _RCC + EXT RCC_TypeDef *RCC; +#endif /*_RCC */ + +#ifdef _SysTick + EXT SysTick_TypeDef *SysTick; +#endif /*_SysTick */ + +#ifdef _NVIC + EXT NVIC_TypeDef *NVIC; +#endif /*_NVIC */ + +#ifdef _SCB + EXT SCB_TypeDef *SCB; +#endif /*_SCB */ + +#endif /* DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_MAP_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_nvic.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_nvic.h new file mode 100644 index 0000000..5cfacf8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_nvic.h @@ -0,0 +1,255 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* NVIC firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_NVIC_H +#define __STM32F10x_NVIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* NVIC Init Structure definition */ +typedef struct +{ + u8 NVIC_IRQChannel; + u8 NVIC_IRQChannelPreemptionPriority; + u8 NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* IRQ Channels --------------------------------------------------------------*/ +#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */ +#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */ +#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */ +#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */ +#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */ +#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */ +#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */ +#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */ +#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */ +#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */ +#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */ +#define DMAChannel1_IRQChannel ((u8)0x0B) /* DMA Channel 1 global Interrupt */ +#define DMAChannel2_IRQChannel ((u8)0x0C) /* DMA Channel 2 global Interrupt */ +#define DMAChannel3_IRQChannel ((u8)0x0D) /* DMA Channel 3 global Interrupt */ +#define DMAChannel4_IRQChannel ((u8)0x0E) /* DMA Channel 4 global Interrupt */ +#define DMAChannel5_IRQChannel ((u8)0x0F) /* DMA Channel 5 global Interrupt */ +#define DMAChannel6_IRQChannel ((u8)0x10) /* DMA Channel 6 global Interrupt */ +#define DMAChannel7_IRQChannel ((u8)0x11) /* DMA Channel 7 global Interrupt */ +#define ADC_IRQChannel ((u8)0x12) /* ADC global Interrupt */ +#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */ +#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */ +#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */ +#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */ +#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */ +#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */ +#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */ +#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */ +#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */ +#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */ +#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */ +#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */ +#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */ +#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */ +#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */ +#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */ +#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */ +#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */ +#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */ +#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */ +#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */ +#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */ +#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */ +#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */ + +#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \ + (CHANNEL == PVD_IRQChannel) || \ + (CHANNEL == TAMPER_IRQChannel) || \ + (CHANNEL == RTC_IRQChannel) || \ + (CHANNEL == FLASH_IRQChannel) || \ + (CHANNEL == RCC_IRQChannel) || \ + (CHANNEL == EXTI0_IRQChannel) || \ + (CHANNEL == EXTI1_IRQChannel) || \ + (CHANNEL == EXTI2_IRQChannel) || \ + (CHANNEL == EXTI3_IRQChannel) || \ + (CHANNEL == EXTI4_IRQChannel) || \ + (CHANNEL == DMAChannel1_IRQChannel) || \ + (CHANNEL == DMAChannel2_IRQChannel) || \ + (CHANNEL == DMAChannel3_IRQChannel) || \ + (CHANNEL == DMAChannel4_IRQChannel) || \ + (CHANNEL == DMAChannel5_IRQChannel) || \ + (CHANNEL == DMAChannel6_IRQChannel) || \ + (CHANNEL == DMAChannel7_IRQChannel) || \ + (CHANNEL == ADC_IRQChannel) || \ + (CHANNEL == USB_HP_CAN_TX_IRQChannel) || \ + (CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \ + (CHANNEL == CAN_RX1_IRQChannel) || \ + (CHANNEL == CAN_SCE_IRQChannel) || \ + (CHANNEL == EXTI9_5_IRQChannel) || \ + (CHANNEL == TIM1_BRK_IRQChannel) || \ + (CHANNEL == TIM1_UP_IRQChannel) || \ + (CHANNEL == TIM1_TRG_COM_IRQChannel) || \ + (CHANNEL == TIM1_CC_IRQChannel) || \ + (CHANNEL == TIM2_IRQChannel) || \ + (CHANNEL == TIM3_IRQChannel) || \ + (CHANNEL == TIM4_IRQChannel) || \ + (CHANNEL == I2C1_EV_IRQChannel) || \ + (CHANNEL == I2C1_ER_IRQChannel) || \ + (CHANNEL == I2C2_EV_IRQChannel) || \ + (CHANNEL == I2C2_ER_IRQChannel) || \ + (CHANNEL == SPI1_IRQChannel) || \ + (CHANNEL == SPI2_IRQChannel) || \ + (CHANNEL == USART1_IRQChannel) || \ + (CHANNEL == USART2_IRQChannel) || \ + (CHANNEL == USART3_IRQChannel) || \ + (CHANNEL == EXTI15_10_IRQChannel) || \ + (CHANNEL == RTCAlarm_IRQChannel) || \ + (CHANNEL == USBWakeUp_IRQChannel)) + +/* System Handlers -----------------------------------------------------------*/ +#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */ +#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */ +#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */ +#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */ +#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */ +#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */ +#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */ +#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */ +#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */ + +#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault)) + +#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault) || \ + (HANDLER == SystemHandler_SVCall) || \ + (HANDLER == SystemHandler_DebugMonitor) || \ + (HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_SVCall)) + +#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \ + (HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault) || \ + (HANDLER == SystemHandler_SVCall) || \ + (HANDLER == SystemHandler_DebugMonitor) || \ + (HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \ + (HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault) || \ + (HANDLER == SystemHandler_DebugMonitor)) + +#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault)) + + +/* Vector Table Base ---------------------------------------------------------*/ +#define NVIC_VectTab_RAM ((u32)0x20000000) +#define NVIC_VectTab_FLASH ((u32)0x00000000) + +#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \ + (VECTTAB == NVIC_VectTab_FLASH)) + +/* System Low Power ----------------------------------------------------------*/ +#define NVIC_LP_SEVONPEND ((u8)0x10) +#define NVIC_LP_SLEEPDEEP ((u8)0x04) +#define NVIC_LP_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \ + (LP == NVIC_LP_SLEEPDEEP) || \ + (LP == NVIC_LP_SLEEPONEXIT)) + +/* Preemption Priority Group -------------------------------------------------*/ +#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \ + (GROUP == NVIC_PriorityGroup_1) || \ + (GROUP == NVIC_PriorityGroup_2) || \ + (GROUP == NVIC_PriorityGroup_3) || \ + (GROUP == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) (PRIORITY < 0x10) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) (PRIORITY < 0x10) +#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x3FFFFF) +#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NVIC_DeInit(void); +void NVIC_SCBDeInit(void); +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SETPRIMASK(void); +void NVIC_RESETPRIMASK(void); +void NVIC_SETFAULTMASK(void); +void NVIC_RESETFAULTMASK(void); +void NVIC_BASEPRICONFIG(u32 NewPriority); +u32 NVIC_GetBASEPRI(void); +u16 NVIC_GetCurrentPendingIRQChannel(void); +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel); +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel); +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel); +u16 NVIC_GetCurrentActiveHandler(void); +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel); +u32 NVIC_GetCPUID(void); +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset); +void NVIC_GenerateSystemReset(void); +void NVIC_GenerateCoreReset(void); +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState); +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState); +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority); +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler); +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler); +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler); +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler); +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler); +u32 NVIC_GetFaultAddress(u32 SystemHandler); + +#endif /* __STM32F10x_NVIC_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_pwr.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_pwr.h new file mode 100644 index 0000000..4bbc291 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_pwr.h @@ -0,0 +1,81 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_pwr.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* PWR firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* PVD detection level */ +#define PWR_PVDLevel_2V2 ((u32)0x00000000) +#define PWR_PVDLevel_2V3 ((u32)0x00000020) +#define PWR_PVDLevel_2V4 ((u32)0x00000040) +#define PWR_PVDLevel_2V5 ((u32)0x00000060) +#define PWR_PVDLevel_2V6 ((u32)0x00000080) +#define PWR_PVDLevel_2V7 ((u32)0x000000A0) +#define PWR_PVDLevel_2V8 ((u32)0x000000C0) +#define PWR_PVDLevel_2V9 ((u32)0x000000E0) + +#define IS_PWR_PVD_LEVEL(LEVEL) ((LEVEL == PWR_PVDLevel_2V2) || (LEVEL == PWR_PVDLevel_2V3)|| \ + (LEVEL == PWR_PVDLevel_2V4) || (LEVEL == PWR_PVDLevel_2V5)|| \ + (LEVEL == PWR_PVDLevel_2V6) || (LEVEL == PWR_PVDLevel_2V7)|| \ + (LEVEL == PWR_PVDLevel_2V8) || (LEVEL == PWR_PVDLevel_2V9)) + +/* Regulator state is STOP mode */ +#define PWR_Regulator_ON ((u32)0x00000000) +#define PWR_Regulator_LowPower ((u32)0x00000001) + +#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR == PWR_Regulator_ON) || \ + (REGULATOR == PWR_Regulator_LowPower)) + +/* STOP mode entry */ +#define PWR_STOPEntry_WFI ((u8)0x01) +#define PWR_STOPEntry_WFE ((u8)0x02) + +#define IS_PWR_STOP_ENTRY(ENTRY) ((ENTRY == PWR_STOPEntry_WFI) || (ENTRY == PWR_STOPEntry_WFE)) + +/* PWR Flag */ +#define PWR_FLAG_WU ((u32)0x00000001) +#define PWR_FLAG_SB ((u32)0x00000002) +#define PWR_FLAG_PVDO ((u32)0x00000004) + +#define IS_PWR_GET_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB) || \ + (FLAG == PWR_FLAG_PVDO)) +#define IS_PWR_CLEAR_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(u32 PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG); +void PWR_ClearFlag(u32 PWR_FLAG); + +#endif /* __STM32F10x_PWR_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rcc.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rcc.h new file mode 100644 index 0000000..b7d0aa3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rcc.h @@ -0,0 +1,276 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_rcc.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* RCC firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u32 SYSCLK_Frequency; + u32 HCLK_Frequency; + u32 PCLK1_Frequency; + u32 PCLK2_Frequency; + u32 ADCCLK_Frequency; +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* HSE configuration */ +#define RCC_HSE_OFF ((u32)0x00000000) +#define RCC_HSE_ON ((u32)0x00010000) +#define RCC_HSE_Bypass ((u32)0x00040000) + +#define IS_RCC_HSE(HSE) ((HSE == RCC_HSE_OFF) || (HSE == RCC_HSE_ON) || \ + (HSE == RCC_HSE_Bypass)) + +/* PLL entry clock source */ +#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000) + +#define IS_RCC_PLL_SOURCE(SOURCE) ((SOURCE == RCC_PLLSource_HSI_Div2) || \ + (SOURCE == RCC_PLLSource_HSE_Div1) || \ + (SOURCE == RCC_PLLSource_HSE_Div2)) + +/* PLL multiplication factor */ +#define RCC_PLLMul_2 ((u32)0x00000000) +#define RCC_PLLMul_3 ((u32)0x00040000) +#define RCC_PLLMul_4 ((u32)0x00080000) +#define RCC_PLLMul_5 ((u32)0x000C0000) +#define RCC_PLLMul_6 ((u32)0x00100000) +#define RCC_PLLMul_7 ((u32)0x00140000) +#define RCC_PLLMul_8 ((u32)0x00180000) +#define RCC_PLLMul_9 ((u32)0x001C0000) +#define RCC_PLLMul_10 ((u32)0x00200000) +#define RCC_PLLMul_11 ((u32)0x00240000) +#define RCC_PLLMul_12 ((u32)0x00280000) +#define RCC_PLLMul_13 ((u32)0x002C0000) +#define RCC_PLLMul_14 ((u32)0x00300000) +#define RCC_PLLMul_15 ((u32)0x00340000) +#define RCC_PLLMul_16 ((u32)0x00380000) + +#define IS_RCC_PLL_MUL(MUL) ((MUL == RCC_PLLMul_2) || (MUL == RCC_PLLMul_3) ||\ + (MUL == RCC_PLLMul_4) || (MUL == RCC_PLLMul_5) ||\ + (MUL == RCC_PLLMul_6) || (MUL == RCC_PLLMul_7) ||\ + (MUL == RCC_PLLMul_8) || (MUL == RCC_PLLMul_9) ||\ + (MUL == RCC_PLLMul_10) || (MUL == RCC_PLLMul_11) ||\ + (MUL == RCC_PLLMul_12) || (MUL == RCC_PLLMul_13) ||\ + (MUL == RCC_PLLMul_14) || (MUL == RCC_PLLMul_15) ||\ + (MUL == RCC_PLLMul_16)) + +/* System clock source */ +#define RCC_SYSCLKSource_HSI ((u32)0x00000000) +#define RCC_SYSCLKSource_HSE ((u32)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002) + +#define IS_RCC_SYSCLK_SOURCE(SOURCE) ((SOURCE == RCC_SYSCLKSource_HSI) || \ + (SOURCE == RCC_SYSCLKSource_HSE) || \ + (SOURCE == RCC_SYSCLKSource_PLLCLK)) + +/* AHB clock source */ +#define RCC_SYSCLK_Div1 ((u32)0x00000000) +#define RCC_SYSCLK_Div2 ((u32)0x00000080) +#define RCC_SYSCLK_Div4 ((u32)0x00000090) +#define RCC_SYSCLK_Div8 ((u32)0x000000A0) +#define RCC_SYSCLK_Div16 ((u32)0x000000B0) +#define RCC_SYSCLK_Div64 ((u32)0x000000C0) +#define RCC_SYSCLK_Div128 ((u32)0x000000D0) +#define RCC_SYSCLK_Div256 ((u32)0x000000E0) +#define RCC_SYSCLK_Div512 ((u32)0x000000F0) + +#define IS_RCC_HCLK(HCLK) ((HCLK == RCC_SYSCLK_Div1) || (HCLK == RCC_SYSCLK_Div2) || \ + (HCLK == RCC_SYSCLK_Div4) || (HCLK == RCC_SYSCLK_Div8) || \ + (HCLK == RCC_SYSCLK_Div16) || (HCLK == RCC_SYSCLK_Div64) || \ + (HCLK == RCC_SYSCLK_Div128) || (HCLK == RCC_SYSCLK_Div256) || \ + (HCLK == RCC_SYSCLK_Div512)) + +/* APB1/APB2 clock source */ +#define RCC_HCLK_Div1 ((u32)0x00000000) +#define RCC_HCLK_Div2 ((u32)0x00000400) +#define RCC_HCLK_Div4 ((u32)0x00000500) +#define RCC_HCLK_Div8 ((u32)0x00000600) +#define RCC_HCLK_Div16 ((u32)0x00000700) + +#define IS_RCC_PCLK(PCLK) ((PCLK == RCC_HCLK_Div1) || (PCLK == RCC_HCLK_Div2) || \ + (PCLK == RCC_HCLK_Div4) || (PCLK == RCC_HCLK_Div8) || \ + (PCLK == RCC_HCLK_Div16)) + +/* RCC Interrupt source */ +#define RCC_IT_LSIRDY ((u8)0x01) +#define RCC_IT_LSERDY ((u8)0x02) +#define RCC_IT_HSIRDY ((u8)0x04) +#define RCC_IT_HSERDY ((u8)0x08) +#define RCC_IT_PLLRDY ((u8)0x10) +#define RCC_IT_CSS ((u8)0x80) + +#define IS_RCC_IT(IT) (((IT & (u8)0xE0) == 0x00) && (IT != 0x00)) +#define IS_RCC_GET_IT(IT) ((IT == RCC_IT_LSIRDY) || (IT == RCC_IT_LSERDY) || \ + (IT == RCC_IT_HSIRDY) || (IT == RCC_IT_HSERDY) || \ + (IT == RCC_IT_PLLRDY) || (IT == RCC_IT_CSS)) +#define IS_RCC_CLEAR_IT(IT) (((IT & (u8)0x60) == 0x00) && (IT != 0x00)) + +/* USB clock source */ +#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00) +#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01) + +#define IS_RCC_USBCLK_SOURCE(SOURCE) ((SOURCE == RCC_USBCLKSource_PLLCLK_1Div5) || \ + (SOURCE == RCC_USBCLKSource_PLLCLK_Div1)) + +/* ADC clock source */ +#define RCC_PCLK2_Div2 ((u32)0x00000000) +#define RCC_PCLK2_Div4 ((u32)0x00004000) +#define RCC_PCLK2_Div6 ((u32)0x00008000) +#define RCC_PCLK2_Div8 ((u32)0x0000C000) + +#define IS_RCC_ADCCLK(ADCCLK) ((ADCCLK == RCC_PCLK2_Div2) || (ADCCLK == RCC_PCLK2_Div4) || \ + (ADCCLK == RCC_PCLK2_Div6) || (ADCCLK == RCC_PCLK2_Div8)) + +/* LSE configuration */ +#define RCC_LSE_OFF ((u8)0x00) +#define RCC_LSE_ON ((u8)0x01) +#define RCC_LSE_Bypass ((u8)0x04) + +#define IS_RCC_LSE(LSE) ((LSE == RCC_LSE_OFF) || (LSE == RCC_LSE_ON) || \ + (LSE == RCC_LSE_Bypass)) + +/* RTC clock source */ +#define RCC_RTCCLKSource_LSE ((u32)0x00000100) +#define RCC_RTCCLKSource_LSI ((u32)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300) + +#define IS_RCC_RTCCLK_SOURCE(SOURCE) ((SOURCE == RCC_RTCCLKSource_LSE) || \ + (SOURCE == RCC_RTCCLKSource_LSI) || \ + (SOURCE == RCC_RTCCLKSource_HSE_Div128)) + +/* AHB peripheral */ +#define RCC_AHBPeriph_DMA ((u32)0x00000001) +#define RCC_AHBPeriph_SRAM ((u32)0x00000004) +#define RCC_AHBPeriph_FLITF ((u32)0x00000010) + +#define IS_RCC_AHB_PERIPH(PERIPH) (((PERIPH & 0xFFFFFFEA) == 0x00) && (PERIPH != 0x00)) + +/* APB2 peripheral */ +#define RCC_APB2Periph_AFIO ((u32)0x00000001) +#define RCC_APB2Periph_GPIOA ((u32)0x00000004) +#define RCC_APB2Periph_GPIOB ((u32)0x00000008) +#define RCC_APB2Periph_GPIOC ((u32)0x00000010) +#define RCC_APB2Periph_GPIOD ((u32)0x00000020) +#define RCC_APB2Periph_GPIOE ((u32)0x00000040) +#define RCC_APB2Periph_ADC1 ((u32)0x00000200) +#define RCC_APB2Periph_ADC2 ((u32)0x00000400) +#define RCC_APB2Periph_TIM1 ((u32)0x00000800) +#define RCC_APB2Periph_SPI1 ((u32)0x00001000) +#define RCC_APB2Periph_USART1 ((u32)0x00004000) +#define RCC_APB2Periph_ALL ((u32)0x00005E7D) + +#define IS_RCC_APB2_PERIPH(PERIPH) (((PERIPH & 0xFFFFA182) == 0x00) && (PERIPH != 0x00)) + +/* APB1 peripheral */ +#define RCC_APB1Periph_TIM2 ((u32)0x00000001) +#define RCC_APB1Periph_TIM3 ((u32)0x00000002) +#define RCC_APB1Periph_TIM4 ((u32)0x00000004) +#define RCC_APB1Periph_WWDG ((u32)0x00000800) +#define RCC_APB1Periph_SPI2 ((u32)0x00004000) +#define RCC_APB1Periph_USART2 ((u32)0x00020000) +#define RCC_APB1Periph_USART3 ((u32)0x00040000) +#define RCC_APB1Periph_I2C1 ((u32)0x00200000) +#define RCC_APB1Periph_I2C2 ((u32)0x00400000) +#define RCC_APB1Periph_USB ((u32)0x00800000) +#define RCC_APB1Periph_CAN ((u32)0x02000000) +#define RCC_APB1Periph_BKP ((u32)0x08000000) +#define RCC_APB1Periph_PWR ((u32)0x10000000) +#define RCC_APB1Periph_ALL ((u32)0x1AE64807) + +#define IS_RCC_APB1_PERIPH(PERIPH) (((PERIPH & 0xE519B7F8) == 0x00) && (PERIPH != 0x00)) + +/* Clock source to output on MCO pin */ +#define RCC_MCO_NoClock ((u8)0x00) +#define RCC_MCO_SYSCLK ((u8)0x04) +#define RCC_MCO_HSI ((u8)0x05) +#define RCC_MCO_HSE ((u8)0x06) +#define RCC_MCO_PLLCLK_Div2 ((u8)0x07) + +#define IS_RCC_MCO(MCO) ((MCO == RCC_MCO_NoClock) || (MCO == RCC_MCO_HSI) || \ + (MCO == RCC_MCO_SYSCLK) || (MCO == RCC_MCO_HSE) || \ + (MCO == RCC_MCO_PLLCLK_Div2)) + +/* RCC Flag */ +#define RCC_FLAG_HSIRDY ((u8)0x20) +#define RCC_FLAG_HSERDY ((u8)0x31) +#define RCC_FLAG_PLLRDY ((u8)0x39) +#define RCC_FLAG_LSERDY ((u8)0x41) +#define RCC_FLAG_LSIRDY ((u8)0x61) +#define RCC_FLAG_PINRST ((u8)0x7A) +#define RCC_FLAG_PORRST ((u8)0x7B) +#define RCC_FLAG_SFTRST ((u8)0x7C) +#define RCC_FLAG_IWDGRST ((u8)0x7D) +#define RCC_FLAG_WWDGRST ((u8)0x7E) +#define RCC_FLAG_LPWRRST ((u8)0x7F) + +#define IS_RCC_FLAG(FLAG) ((FLAG == RCC_FLAG_HSIRDY) || (FLAG == RCC_FLAG_HSERDY) || \ + (FLAG == RCC_FLAG_PLLRDY) || (FLAG == RCC_FLAG_LSERDY) || \ + (FLAG == RCC_FLAG_LSIRDY) || (FLAG == RCC_FLAG_PINRST) || \ + (FLAG == RCC_FLAG_PORRST) || (FLAG == RCC_FLAG_SFTRST) || \ + (FLAG == RCC_FLAG_IWDGRST)|| (FLAG == RCC_FLAG_WWDGRST)|| \ + (FLAG == RCC_FLAG_LPWRRST)) + +#define IS_RCC_CALIBRATION_VALUE(VALUE) (VALUE <= 0x1F) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RCC_DeInit(void); +void RCC_HSEConfig(u32 RCC_HSE); +void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource); +u8 RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(u32 RCC_HCLK); +void RCC_PCLK1Config(u32 RCC_PCLK1); +void RCC_PCLK2Config(u32 RCC_PCLK2); +void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(u32 RCC_USBCLKSource); +void RCC_ADCCLKConfig(u32 RCC_ADCCLK); +void RCC_LSEConfig(u32 RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(u8 RCC_MCO); +FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(u8 RCC_IT); +void RCC_ClearITPendingBit(u8 RCC_IT); + +#endif /* __STM32F10x_RCC_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rtc.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rtc.h new file mode 100644 index 0000000..6f8c4e0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rtc.h @@ -0,0 +1,75 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_rtc.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* RTC firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* RTC interrupts define -----------------------------------------------------*/ +#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */ + +#define IS_RTC_IT(IT) (((IT & (u16)0xFFF8) == 0x00) && (IT != 0x00)) + +#define IS_RTC_GET_IT(IT) ((IT == RTC_IT_OW) || (IT == RTC_IT_ALR) || \ + (IT == RTC_IT_SEC)) + +/* RTC interrupts flags ------------------------------------------------------*/ +#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */ + +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFFF0) == 0x00) && (FLAG != 0x00)) + +#define IS_RTC_GET_FLAG(FLAG) ((FLAG == RTC_FLAG_RTOFF) || (FLAG == RTC_FLAG_RSF) || \ + (FLAG == RTC_FLAG_OW) || (FLAG == RTC_FLAG_ALR) || \ + (FLAG == RTC_FLAG_SEC)) + +#define IS_RTC_PRESCALER(PRESCALER) (PRESCALER <= 0xFFFFF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +u32 RTC_GetCounter(void); +void RTC_SetCounter(u32 CounterValue); +u32 RTC_GetPrescaler(void); +void RTC_SetPrescaler(u32 PrescalerValue); +void RTC_SetAlarm(u32 AlarmValue); +u32 RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG); +void RTC_ClearFlag(u16 RTC_FLAG); +ITStatus RTC_GetITStatus(u16 RTC_IT); +void RTC_ClearITPendingBit(u16 RTC_IT); + +#endif /* __STM32F10x_RTC_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h new file mode 100644 index 0000000..4353fc1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h @@ -0,0 +1,486 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the SDIO + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @defgroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint8_t SDIO_ClockDiv; + uint32_t SDIO_ClockEdge; + uint32_t SDIO_ClockBypass; + uint32_t SDIO_ClockPowerSave; + uint32_t SDIO_BusWide; + uint32_t SDIO_HardwareFlowControl; +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; + uint32_t SDIO_CmdIndex; + uint32_t SDIO_Response; + uint32_t SDIO_Wait; + uint32_t SDIO_CPSM; +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; + uint32_t SDIO_DataLength; + uint32_t SDIO_DataBlockSize; + uint32_t SDIO_TransferDir; + uint32_t SDIO_TransferMode; + uint32_t SDIO_DPSM; +} SDIO_DataInitTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save_ + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control_ + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_soucres + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index_ + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /* SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /* SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /* SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#endif /* __STM32F10x_SDIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_spi.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_spi.h new file mode 100644 index 0000000..98c1477 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_spi.h @@ -0,0 +1,452 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the SPI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +/* Includes ------------------------------------------------------------------*/ +//#include "stm32f10x.h" +#include "stm32f10x_map.h" + +#define uint16_t unsigned short +#define uint8_t unsigned char +#define uint32_t unsigned long + +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define GPIO_Remap_SPI3 ( 1UL << 28UL ) +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; + uint16_t SPI_Mode; + uint16_t SPI_DataSize; + uint16_t SPI_CPOL; + uint16_t SPI_CPHA; + uint16_t SPI_NSS; + uint16_t SPI_BaudRatePrescaler; + uint16_t SPI_FirstBit; + uint16_t SPI_CRCPolynomial; +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint16_t I2S_Mode; + uint16_t I2S_Standard; + uint16_t I2S_DataFormat; + uint16_t I2S_MCLKOutput; + uint16_t I2S_AudioFreq; + uint16_t I2S_CPOL; +}I2S_InitTypeDef; + +/** + * @} + */ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI1_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == SPI3_BASE)) +#define IS_SPI_23_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == SPI3_BASE)) + +/** @defgroup SPI_data_direction_mode + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_master_slave_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler_ + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx) || \ + ((MODE) == I2S_Mode_MasterRx) ) +/** + * @} + */ + +/** @defgroup I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_48k ((uint16_t)48000) +#define I2S_AudioFreq_44k ((uint16_t)44100) +#define I2S_AudioFreq_22k ((uint16_t)22050) +#define I2S_AudioFreq_16k ((uint16_t)16000) +#define I2S_AudioFreq_8k ((uint16_t)8000) +#define I2S_AudioFreq_Default ((uint16_t)2) +#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \ + ((FREQ) == I2S_AudioFreq_44k) || \ + ((FREQ) == I2S_AudioFreq_22k) || \ + ((FREQ) == I2S_AudioFreq_16k) || \ + ((FREQ) == I2S_AudioFreq_8k) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_mangement + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ + ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#endif /*__STM32F10x_SPI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_systick.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_systick.h new file mode 100644 index 0000000..7060805 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_systick.h @@ -0,0 +1,68 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_systick.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* SysTick firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SYSTICK_H +#define __STM32F10x_SYSTICK_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* SysTick clock source */ +#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((u32)0x00000004) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) ((SOURCE == SysTick_CLKSource_HCLK) || \ + (SOURCE == SysTick_CLKSource_HCLK_Div8)) + +/* SysTick counter state */ +#define SysTick_Counter_Disable ((u32)0xFFFFFFFE) +#define SysTick_Counter_Enable ((u32)0x00000001) +#define SysTick_Counter_Clear ((u32)0x00000000) + +#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SysTick_Counter_Disable) || \ + (COUNTER == SysTick_Counter_Enable) || \ + (COUNTER == SysTick_Counter_Clear)) + +/* SysTick Flag */ +#define SysTick_FLAG_COUNT ((u8)0x30) +#define SysTick_FLAG_SKEW ((u8)0x5E) +#define SysTick_FLAG_NOREF ((u8)0x5F) + +#define IS_SYSTICK_FLAG(FLAG) ((FLAG == SysTick_FLAG_COUNT) || \ + (FLAG == SysTick_FLAG_SKEW) || \ + (FLAG == SysTick_FLAG_NOREF)) + +#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) || (RELOAD <= 0xFFFFFF)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SysTick_CLKSourceConfig(u32 SysTick_CLKSource); +void SysTick_SetReload(u32 Reload); +void SysTick_CounterCmd(u32 SysTick_Counter); +void SysTick_ITConfig(FunctionalState NewState); +u32 SysTick_GetCounter(void); +FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG); + +#endif /* __STM32F10x_SYSTICK_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim.h new file mode 100644 index 0000000..12f8378 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim.h @@ -0,0 +1,513 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_tim.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* TIM firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* TIM Base Init structure definition */ +typedef struct +{ + u16 TIM_Period; /* Period value */ + u16 TIM_Prescaler; /* Prescaler value */ + u16 TIM_ClockDivision; /* Timer clock division */ + u16 TIM_CounterMode; /* Timer Counter mode */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + u16 TIM_OCMode; /* Timer Output Compare Mode */ + u16 TIM_Channel; /* Timer Channel */ + u16 TIM_Pulse; /* PWM or OC Channel pulse length */ + u16 TIM_OCPolarity; /* PWM, OCM or OPM Channel polarity */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + u16 TIM_ICMode; /* Timer Input Capture Mode */ + u16 TIM_Channel; /* Timer Channel */ + u16 TIM_ICPolarity; /* Input Capture polarity */ + u16 TIM_ICSelection; /* Input Capture selection */ + u16 TIM_ICPrescaler; /* Input Capture prescaler */ + u8 TIM_ICFilter; /* Input Capture filter */ +} TIM_ICInitTypeDef; + +/* Exported constants -------------------------------------------------------*/ +/* TIM Ouput Compare modes --------------------------------------------------*/ +#define TIM_OCMode_Timing ((u16)0x0000) +#define TIM_OCMode_Active ((u16)0x0010) +#define TIM_OCMode_Inactive ((u16)0x0020) +#define TIM_OCMode_Toggle ((u16)0x0030) +#define TIM_OCMode_PWM1 ((u16)0x0060) +#define TIM_OCMode_PWM2 ((u16)0x0070) + +#define IS_TIM_OC_MODE(MODE) ((MODE == TIM_OCMode_Timing) || \ + (MODE == TIM_OCMode_Active) || \ + (MODE == TIM_OCMode_Inactive) || \ + (MODE == TIM_OCMode_Toggle)|| \ + (MODE == TIM_OCMode_PWM1) || \ + (MODE == TIM_OCMode_PWM2)) + +/* TIM Input Capture modes --------------------------------------------------*/ +#define TIM_ICMode_ICAP ((u16)0x0007) +#define TIM_ICMode_PWMI ((u16)0x0006) + +#define IS_TIM_IC_MODE(MODE) ((MODE == TIM_ICMode_ICAP) || \ + (MODE == TIM_ICMode_PWMI)) + +/* TIM One Pulse Mode -------------------------------------------------------*/ +#define TIM_OPMode_Single ((u16)0x0008) +#define TIM_OPMode_Repetitive ((u16)0x0000) + +#define IS_TIM_OPM_MODE(MODE) ((MODE == TIM_OPMode_Single) || \ + (MODE == TIM_OPMode_Repetitive)) + +/* TIM Channel --------------------------------------------------------------*/ +#define TIM_Channel_1 ((u16)0x0000) +#define TIM_Channel_2 ((u16)0x0001) +#define TIM_Channel_3 ((u16)0x0002) +#define TIM_Channel_4 ((u16)0x0003) + +#define IS_TIM_CHANNEL(CHANNEL) ((CHANNEL == TIM_Channel_1) || \ + (CHANNEL == TIM_Channel_2) || \ + (CHANNEL == TIM_Channel_3) || \ + (CHANNEL == TIM_Channel_4)) + +/* TIM Clock Division CKD ---------------------------------------------------*/ +#define TIM_CKD_DIV1 ((u16)0x0000) +#define TIM_CKD_DIV2 ((u16)0x0100) +#define TIM_CKD_DIV4 ((u16)0x0200) + +#define IS_TIM_CKD_DIV(DIV) ((DIV == TIM_CKD_DIV1) || \ + (DIV == TIM_CKD_DIV2) || \ + (DIV == TIM_CKD_DIV4)) + +/* TIM Counter Mode ---------------------------------------------------------*/ +#define TIM_CounterMode_Up ((u16)0x0000) +#define TIM_CounterMode_Down ((u16)0x0010) +#define TIM_CounterMode_CenterAligned1 ((u16)0x0020) +#define TIM_CounterMode_CenterAligned2 ((u16)0x0040) +#define TIM_CounterMode_CenterAligned3 ((u16)0x0060) + +#define IS_TIM_COUNTER_MODE(MODE) ((MODE == TIM_CounterMode_Up) || \ + (MODE == TIM_CounterMode_Down) || \ + (MODE == TIM_CounterMode_CenterAligned1) || \ + (MODE == TIM_CounterMode_CenterAligned2) || \ + (MODE == TIM_CounterMode_CenterAligned3)) + +/* TIM Output Compare Polarity ----------------------------------------------*/ +#define TIM_OCPolarity_High ((u16)0x0000) +#define TIM_OCPolarity_Low ((u16)0x0002) + +#define IS_TIM_OC_POLARITY(POLARITY) ((POLARITY == TIM_OCPolarity_High) || \ + (POLARITY == TIM_OCPolarity_Low)) + +/* TIM Input Capture Polarity -----------------------------------------------*/ +#define TIM_ICPolarity_Rising ((u16)0x0000) +#define TIM_ICPolarity_Falling ((u16)0x0002) + +#define IS_TIM_IC_POLARITY(POLARITY) ((POLARITY == TIM_ICPolarity_Rising) || \ + (POLARITY == TIM_ICPolarity_Falling)) + +/* TIM Input Capture Channel Selection -------------------------------------*/ +#define TIM_ICSelection_DirectTI ((u16)0x0001) +#define TIM_ICSelection_IndirectTI ((u16)0x0002) +#define TIM_ICSelection_TRGI ((u16)0x0003) + +#define IS_TIM_IC_SELECTION(SELECTION) ((SELECTION == TIM_ICSelection_DirectTI) || \ + (SELECTION == TIM_ICSelection_IndirectTI) || \ + (SELECTION == TIM_ICSelection_TRGI)) + +/* TIM Input Capture Prescaler ----------------------------------------------*/ +#define TIM_ICPSC_DIV1 ((u16)0x0000) +#define TIM_ICPSC_DIV2 ((u16)0x0004) +#define TIM_ICPSC_DIV4 ((u16)0x0008) +#define TIM_ICPSC_DIV8 ((u16)0x000C) + +#define IS_TIM_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM_ICPSC_DIV1) || \ + (PRESCALER == TIM_ICPSC_DIV2) || \ + (PRESCALER == TIM_ICPSC_DIV4) || \ + (PRESCALER == TIM_ICPSC_DIV8)) + +/* TIM Input Capture Filer Value ---------------------------------------------*/ +#define IS_TIM_IC_FILTER(ICFILTER) (ICFILTER <= 0xF) + +/* TIM interrupt sources ----------------------------------------------------*/ +#define TIM_IT_Update ((u16)0x0001) +#define TIM_IT_CC1 ((u16)0x0002) +#define TIM_IT_CC2 ((u16)0x0004) +#define TIM_IT_CC3 ((u16)0x0008) +#define TIM_IT_CC4 ((u16)0x0010) +#define TIM_IT_Trigger ((u16)0x0040) + +#define IS_TIM_IT(IT) (((IT & (u16)0xFFA0) == 0x0000) && (IT != 0x0000)) + +#define IS_TIM_GET_IT(IT) ((IT == TIM_IT_Update) || \ + (IT == TIM_IT_CC1) || \ + (IT == TIM_IT_CC2) || \ + (IT == TIM_IT_CC3) || \ + (IT == TIM_IT_CC4) || \ + (IT == TIM_IT_Trigger)) + +/* TIM DMA Base address -----------------------------------------------------*/ +#define TIM_DMABase_CR1 ((u16)0x0000) +#define TIM_DMABase_CR2 ((u16)0x0001) +#define TIM_DMABase_SMCR ((u16)0x0002) +#define TIM_DMABase_DIER ((u16)0x0003) +#define TIM_DMABase_SR ((u16)0x0004) +#define TIM_DMABase_EGR ((u16)0x0005) +#define TIM_DMABase_CCMR1 ((u16)0x0006) +#define TIM_DMABase_CCMR2 ((u16)0x0007) +#define TIM_DMABase_CCER ((u16)0x0008) +#define TIM_DMABase_CNT ((u16)0x0009) +#define TIM_DMABase_PSC ((u16)0x000A) +#define TIM_DMABase_ARR ((u16)0x000B) +#define TIM_DMABase_CCR1 ((u16)0x000D) +#define TIM_DMABase_CCR2 ((u16)0x000E) +#define TIM_DMABase_CCR3 ((u16)0x000F) +#define TIM_DMABase_CCR4 ((u16)0x0010) +#define TIM_DMABase_DCR ((u16)0x0012) + +#define IS_TIM_DMA_BASE(BASE) ((BASE == TIM_DMABase_CR1) || \ + (BASE == TIM_DMABase_CR2) || \ + (BASE == TIM_DMABase_SMCR) || \ + (BASE == TIM_DMABase_DIER) || \ + (BASE == TIM_DMABase_SR) || \ + (BASE == TIM_DMABase_EGR) || \ + (BASE == TIM_DMABase_CCMR1) || \ + (BASE == TIM_DMABase_CCMR2) || \ + (BASE == TIM_DMABase_CCER) || \ + (BASE == TIM_DMABase_CNT) || \ + (BASE == TIM_DMABase_PSC) || \ + (BASE == TIM_DMABase_ARR) || \ + (BASE == TIM_DMABase_CCR1) || \ + (BASE == TIM_DMABase_CCR2) || \ + (BASE == TIM_DMABase_CCR3) || \ + (BASE == TIM_DMABase_CCR4) || \ + (BASE == TIM_DMABase_DCR)) + +/* TIM DMA Burst Length -----------------------------------------------------*/ +#define TIM_DMABurstLength_1Byte ((u16)0x0000) +#define TIM_DMABurstLength_2Bytes ((u16)0x0100) +#define TIM_DMABurstLength_3Bytes ((u16)0x0200) +#define TIM_DMABurstLength_4Bytes ((u16)0x0300) +#define TIM_DMABurstLength_5Bytes ((u16)0x0400) +#define TIM_DMABurstLength_6Bytes ((u16)0x0500) +#define TIM_DMABurstLength_7Bytes ((u16)0x0600) +#define TIM_DMABurstLength_8Bytes ((u16)0x0700) +#define TIM_DMABurstLength_9Bytes ((u16)0x0800) +#define TIM_DMABurstLength_10Bytes ((u16)0x0900) +#define TIM_DMABurstLength_11Bytes ((u16)0x0A00) +#define TIM_DMABurstLength_12Bytes ((u16)0x0B00) +#define TIM_DMABurstLength_13Bytes ((u16)0x0C00) +#define TIM_DMABurstLength_14Bytes ((u16)0x0D00) +#define TIM_DMABurstLength_15Bytes ((u16)0x0E00) +#define TIM_DMABurstLength_16Bytes ((u16)0x0F00) +#define TIM_DMABurstLength_17Bytes ((u16)0x1000) +#define TIM_DMABurstLength_18Bytes ((u16)0x1100) + +#define IS_TIM_DMA_LENGTH(LENGTH) ((LENGTH == TIM_DMABurstLength_1Byte) || \ + (LENGTH == TIM_DMABurstLength_2Bytes) || \ + (LENGTH == TIM_DMABurstLength_3Bytes) || \ + (LENGTH == TIM_DMABurstLength_4Bytes) || \ + (LENGTH == TIM_DMABurstLength_5Bytes) || \ + (LENGTH == TIM_DMABurstLength_6Bytes) || \ + (LENGTH == TIM_DMABurstLength_7Bytes) || \ + (LENGTH == TIM_DMABurstLength_8Bytes) || \ + (LENGTH == TIM_DMABurstLength_9Bytes) || \ + (LENGTH == TIM_DMABurstLength_10Bytes) || \ + (LENGTH == TIM_DMABurstLength_11Bytes) || \ + (LENGTH == TIM_DMABurstLength_12Bytes) || \ + (LENGTH == TIM_DMABurstLength_13Bytes) || \ + (LENGTH == TIM_DMABurstLength_14Bytes) || \ + (LENGTH == TIM_DMABurstLength_15Bytes) || \ + (LENGTH == TIM_DMABurstLength_16Bytes) || \ + (LENGTH == TIM_DMABurstLength_17Bytes) || \ + (LENGTH == TIM_DMABurstLength_18Bytes)) + +/* TIM DMA sources ----------------------------------------------------------*/ +#define TIM_DMA_Update ((u16)0x0100) +#define TIM_DMA_CC1 ((u16)0x0200) +#define TIM_DMA_CC2 ((u16)0x0400) +#define TIM_DMA_CC3 ((u16)0x0800) +#define TIM_DMA_CC4 ((u16)0x1000) +#define TIM_DMA_Trigger ((u16)0x4000) + +#define IS_TIM_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0xA0FF) == 0x0000) && (SOURCE != 0x0000)) + +/* TIM External Trigger Prescaler -------------------------------------------*/ +#define TIM_ExtTRGPSC_OFF ((u16)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000) + +#define IS_TIM_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM_ExtTRGPSC_OFF) || \ + (PRESCALER == TIM_ExtTRGPSC_DIV2) || \ + (PRESCALER == TIM_ExtTRGPSC_DIV4) || \ + (PRESCALER == TIM_ExtTRGPSC_DIV8)) + +/* TIM Input Trigger Selection ---------------------------------------------*/ +#define TIM_TS_ITR0 ((u16)0x0000) +#define TIM_TS_ITR1 ((u16)0x0010) +#define TIM_TS_ITR2 ((u16)0x0020) +#define TIM_TS_ITR3 ((u16)0x0030) +#define TIM_TS_TI1F_ED ((u16)0x0040) +#define TIM_TS_TI1FP1 ((u16)0x0050) +#define TIM_TS_TI2FP2 ((u16)0x0060) +#define TIM_TS_ETRF ((u16)0x0070) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \ + (SELECTION == TIM_TS_ITR1) || \ + (SELECTION == TIM_TS_ITR2) || \ + (SELECTION == TIM_TS_ITR3) || \ + (SELECTION == TIM_TS_TI1F_ED) || \ + (SELECTION == TIM_TS_TI1FP1) || \ + (SELECTION == TIM_TS_TI2FP2) || \ + (SELECTION == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \ + (SELECTION == TIM_TS_ITR1) || \ + (SELECTION == TIM_TS_ITR2) || \ + (SELECTION == TIM_TS_ITR3)) + +#define IS_TIM_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_TI1F_ED) || \ + (SELECTION == TIM_TS_TI1FP1) || \ + (SELECTION == TIM_TS_TI2FP2)) + +/* TIM External Trigger Polarity --------------------------------------------*/ +#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000) + +#define IS_TIM_EXT_POLARITY(POLARITY) ((POLARITY == TIM_ExtTRGPolarity_Inverted) || \ + (POLARITY == TIM_ExtTRGPolarity_NonInverted)) + +/* TIM Prescaler Reload Mode ------------------------------------------------*/ +#define TIM_PSCReloadMode_Update ((u16)0x0000) +#define TIM_PSCReloadMode_Immediate ((u16)0x0001) + +#define IS_TIM_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM_PSCReloadMode_Update) || \ + (RELOAD == TIM_PSCReloadMode_Immediate)) + +/* TIM Forced Action --------------------------------------------------------*/ +#define TIM_ForcedAction_Active ((u16)0x0050) +#define TIM_ForcedAction_InActive ((u16)0x0040) + +#define IS_TIM_FORCED_ACTION(ACTION) ((ACTION == TIM_ForcedAction_Active) || \ + (ACTION == TIM_ForcedAction_InActive)) + +/* TIM Encoder Mode ---------------------------------------------------------*/ +#define TIM_EncoderMode_TI1 ((u16)0x0001) +#define TIM_EncoderMode_TI2 ((u16)0x0002) +#define TIM_EncoderMode_TI12 ((u16)0x0003) + +#define IS_TIM_ENCODER_MODE(MODE) ((MODE == TIM_EncoderMode_TI1) || \ + (MODE == TIM_EncoderMode_TI2) || \ + (MODE == TIM_EncoderMode_TI12)) + +/* TIM Event Source ---------------------------------------------------------*/ +#define TIM_EventSource_Update ((u16)0x0001) +#define TIM_EventSource_CC1 ((u16)0x0002) +#define TIM_EventSource_CC2 ((u16)0x0004) +#define TIM_EventSource_CC3 ((u16)0x0008) +#define TIM_EventSource_CC4 ((u16)0x0010) +#define TIM_EventSource_Trigger ((u16)0x0040) + +#define IS_TIM_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFFA0) == 0x0000) && (SOURCE != 0x0000)) + + +/* TIM Update Source --------------------------------------------------------*/ +#define TIM_UpdateSource_Global ((u16)0x0000) +#define TIM_UpdateSource_Regular ((u16)0x0001) + +#define IS_TIM_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM_UpdateSource_Global) || \ + (SOURCE == TIM_UpdateSource_Regular)) + +/* TIM Ouput Compare Preload State ------------------------------------------*/ +#define TIM_OCPreload_Enable ((u16)0x0008) +#define TIM_OCPreload_Disable ((u16)0x0000) + +#define IS_TIM_OCPRELOAD_STATE(STATE) ((STATE == TIM_OCPreload_Enable) || \ + (STATE == TIM_OCPreload_Disable)) + +/* TIM Ouput Compare Fast State ---------------------------------------------*/ +#define TIM_OCFast_Enable ((u16)0x0004) +#define TIM_OCFast_Disable ((u16)0x0000) + +#define IS_TIM_OCFAST_STATE(STATE) ((STATE == TIM_OCFast_Enable) || \ + (STATE == TIM_OCFast_Disable)) + +/* TIM Trigger Output Source ------------------------------------------------*/ +#define TIM_TRGOSource_Reset ((u16)0x0000) +#define TIM_TRGOSource_Enable ((u16)0x0010) +#define TIM_TRGOSource_Update ((u16)0x0020) +#define TIM_TRGOSource_OC1 ((u16)0x0030) +#define TIM_TRGOSource_OC1Ref ((u16)0x0040) +#define TIM_TRGOSource_OC2Ref ((u16)0x0050) +#define TIM_TRGOSource_OC3Ref ((u16)0x0060) +#define TIM_TRGOSource_OC4Ref ((u16)0x0070) + +#define IS_TIM_TRGO_SOURCE(SOURCE) ((SOURCE == TIM_TRGOSource_Reset) || \ + (SOURCE == TIM_TRGOSource_Enable) || \ + (SOURCE == TIM_TRGOSource_Update) || \ + (SOURCE == TIM_TRGOSource_OC1) || \ + (SOURCE == TIM_TRGOSource_OC1Ref) || \ + (SOURCE == TIM_TRGOSource_OC2Ref) || \ + (SOURCE == TIM_TRGOSource_OC3Ref) || \ + (SOURCE == TIM_TRGOSource_OC4Ref)) + +/* TIM Slave Mode -----------------------------------------------------------*/ +#define TIM_SlaveMode_Reset ((u16)0x0004) +#define TIM_SlaveMode_Gated ((u16)0x0005) +#define TIM_SlaveMode_Trigger ((u16)0x0006) +#define TIM_SlaveMode_External1 ((u16)0x0007) + + +#define IS_TIM_SLAVE_MODE(MODE) ((MODE == TIM_SlaveMode_Reset) || \ + (MODE == TIM_SlaveMode_Gated) || \ + (MODE == TIM_SlaveMode_Trigger) || \ + (MODE == TIM_SlaveMode_External1)) + +/* TIM TIx External Clock Source --------------------------------------------*/ +#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040) + +#define IS_TIM_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM_TIxExternalCLK1Source_TI1) || \ + (SOURCE == TIM_TIxExternalCLK1Source_TI2) || \ + (SOURCE == TIM_TIxExternalCLK1Source_TI1ED)) + + +/* TIM Master Slave Mode ----------------------------------------------------*/ +#define TIM_MasterSlaveMode_Enable ((u16)0x0080) +#define TIM_MasterSlaveMode_Disable ((u16)0x0000) + +#define IS_TIM_MSM_STATE(STATE) ((STATE == TIM_MasterSlaveMode_Enable) || \ + (STATE == TIM_MasterSlaveMode_Disable)) + +/* TIM Flags ----------------------------------------------------------------*/ +#define TIM_FLAG_Update ((u16)0x0001) +#define TIM_FLAG_CC1 ((u16)0x0002) +#define TIM_FLAG_CC2 ((u16)0x0004) +#define TIM_FLAG_CC3 ((u16)0x0008) +#define TIM_FLAG_CC4 ((u16)0x0010) +#define TIM_FLAG_Trigger ((u16)0x0040) +#define TIM_FLAG_CC1OF ((u16)0x0200) +#define TIM_FLAG_CC2OF ((u16)0x0400) +#define TIM_FLAG_CC3OF ((u16)0x0800) +#define TIM_FLAG_CC4OF ((u16)0x1000) + +#define IS_TIM_GET_FLAG(FLAG) ((FLAG == TIM_FLAG_Update) || \ + (FLAG == TIM_FLAG_CC1) || \ + (FLAG == TIM_FLAG_CC2) || \ + (FLAG == TIM_FLAG_CC3) || \ + (FLAG == TIM_FLAG_CC4) || \ + (FLAG == TIM_FLAG_Trigger) || \ + (FLAG == TIM_FLAG_CC1OF) || \ + (FLAG == TIM_FLAG_CC2OF) || \ + (FLAG == TIM_FLAG_CC3OF) || \ + (FLAG == TIM_FLAG_CC4OF)) + +#define IS_TIM_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE1A0) == 0x0000) && (FLAG != 0x0000)) + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState); +void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource, + u16 TIM_ICPolarity, u8 ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, + u16 TIM_IC1Polarity, u16 TIM_IC2Polarity); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD); +u16 TIM_GetCapture1(TIM_TypeDef* TIMx); +u16 TIM_GetCapture2(TIM_TypeDef* TIMx); +u16 TIM_GetCapture3(TIM_TypeDef* TIMx); +u16 TIM_GetCapture4(TIM_TypeDef* TIMx); +u16 TIM_GetCounter(TIM_TypeDef* TIMx); +u16 TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT); + +#endif /*__STM32F10x_TIM_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim1.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim1.h new file mode 100644 index 0000000..b83761d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim1.h @@ -0,0 +1,644 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_tim1.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* TIM1 firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* mm/dd/yyyy: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM1_H +#define __STM32F10x_TIM1_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* TIM1 Time Base Init structure definition */ +typedef struct +{ + u16 TIM1_Prescaler; + u16 TIM1_CounterMode; + u16 TIM1_Period; + u16 TIM1_ClockDivision; + u8 TIM1_RepetitionCounter; +} TIM1_TimeBaseInitTypeDef; + +/* TIM1 Output Compare Init structure definition */ +typedef struct +{ + u16 TIM1_OCMode; + u16 TIM1_OutputState; + u16 TIM1_OutputNState; + u16 TIM1_Pulse; + u16 TIM1_OCPolarity; + u16 TIM1_OCNPolarity; + u16 TIM1_OCIdleState; + u16 TIM1_OCNIdleState; +} TIM1_OCInitTypeDef; + +/* TIM1 Input Capture Init structure definition */ +typedef struct +{ + u16 TIM1_Channel; + u16 TIM1_ICPolarity; + u16 TIM1_ICSelection; + u16 TIM1_ICPrescaler; + u8 TIM1_ICFilter; +} TIM1_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + u16 TIM1_OSSRState; + u16 TIM1_OSSIState; + u16 TIM1_LOCKLevel; + u16 TIM1_DeadTime; + u16 TIM1_Break; + u16 TIM1_BreakPolarity; + u16 TIM1_AutomaticOutput; +} TIM1_BDTRInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* TIM1 Output Compare and PWM modes ----------------------------------------*/ +#define TIM1_OCMode_Timing ((u16)0x0000) +#define TIM1_OCMode_Active ((u16)0x0010) +#define TIM1_OCMode_Inactive ((u16)0x0020) +#define TIM1_OCMode_Toggle ((u16)0x0030) +#define TIM1_OCMode_PWM1 ((u16)0x0060) +#define TIM1_OCMode_PWM2 ((u16)0x0070) + +#define IS_TIM1_OC_MODE(MODE) ((MODE == TIM1_OCMode_Timing) || \ + (MODE == TIM1_OCMode_Active) || \ + (MODE == TIM1_OCMode_Inactive) || \ + (MODE == TIM1_OCMode_Toggle)|| \ + (MODE == TIM1_OCMode_PWM1) || \ + (MODE == TIM1_OCMode_PWM2)) + +#define IS_TIM1_OCM(MODE)((MODE == TIM1_OCMode_Timing) || \ + (MODE == TIM1_OCMode_Active) || \ + (MODE == TIM1_OCMode_Inactive) || \ + (MODE == TIM1_OCMode_Toggle)|| \ + (MODE == TIM1_OCMode_PWM1) || \ + (MODE == TIM1_OCMode_PWM2) || \ + (MODE == TIM1_ForcedAction_Active) || \ + (MODE == TIM1_ForcedAction_InActive)) +/* TIM1 One Pulse Mode ------------------------------------------------------*/ +#define TIM1_OPMode_Single ((u16)0x0001) +#define TIM1_OPMode_Repetitive ((u16)0x0000) + +#define IS_TIM1_OPM_MODE(MODE) ((MODE == TIM1_OPMode_Single) || \ + (MODE == TIM1_OPMode_Repetitive)) + +/* TIM1 Channel -------------------------------------------------------------*/ +#define TIM1_Channel_1 ((u16)0x0000) +#define TIM1_Channel_2 ((u16)0x0001) +#define TIM1_Channel_3 ((u16)0x0002) +#define TIM1_Channel_4 ((u16)0x0003) + +#define IS_TIM1_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \ + (CHANNEL == TIM1_Channel_2) || \ + (CHANNEL == TIM1_Channel_3) || \ + (CHANNEL == TIM1_Channel_4)) + +#define IS_TIM1_PWMI_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \ + (CHANNEL == TIM1_Channel_2)) + +#define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \ + (CHANNEL == TIM1_Channel_2) || \ + (CHANNEL == TIM1_Channel_3)) +/* TIM1 Clock Division CKD --------------------------------------------------*/ +#define TIM1_CKD_DIV1 ((u16)0x0000) +#define TIM1_CKD_DIV2 ((u16)0x0100) +#define TIM1_CKD_DIV4 ((u16)0x0200) + +#define IS_TIM1_CKD_DIV(DIV) ((DIV == TIM1_CKD_DIV1) || \ + (DIV == TIM1_CKD_DIV2) || \ + (DIV == TIM1_CKD_DIV4)) + +/* TIM1 Counter Mode --------------------------------------------------------*/ +#define TIM1_CounterMode_Up ((u16)0x0000) +#define TIM1_CounterMode_Down ((u16)0x0010) +#define TIM1_CounterMode_CenterAligned1 ((u16)0x0020) +#define TIM1_CounterMode_CenterAligned2 ((u16)0x0040) +#define TIM1_CounterMode_CenterAligned3 ((u16)0x0060) + +#define IS_TIM1_COUNTER_MODE(MODE) ((MODE == TIM1_CounterMode_Up) || \ + (MODE == TIM1_CounterMode_Down) || \ + (MODE == TIM1_CounterMode_CenterAligned1) || \ + (MODE == TIM1_CounterMode_CenterAligned2) || \ + (MODE == TIM1_CounterMode_CenterAligned3)) + +/* TIM1 Output Compare Polarity ---------------------------------------------*/ +#define TIM1_OCPolarity_High ((u16)0x0000) +#define TIM1_OCPolarity_Low ((u16)0x0001) + +#define IS_TIM1_OC_POLARITY(POLARITY) ((POLARITY == TIM1_OCPolarity_High) || \ + (POLARITY == TIM1_OCPolarity_Low)) + +/* TIM1 Output Compare N Polarity -------------------------------------------*/ +#define TIM1_OCNPolarity_High ((u16)0x0000) +#define TIM1_OCNPolarity_Low ((u16)0x0001) + +#define IS_TIM1_OCN_POLARITY(POLARITY) ((POLARITY == TIM1_OCNPolarity_High) || \ + (POLARITY == TIM1_OCNPolarity_Low)) + +/* TIM1 Output Compare states -----------------------------------------------*/ +#define TIM1_OutputState_Disable ((u16)0x0000) +#define TIM1_OutputState_Enable ((u16)0x0001) + +#define IS_TIM1_OUTPUT_STATE(STATE) ((STATE == TIM1_OutputState_Disable) || \ + (STATE == TIM1_OutputState_Enable)) + +/* TIM1 Output Compare N States ---------------------------------------------*/ +#define TIM1_OutputNState_Disable ((u16)0x0000) +#define TIM1_OutputNState_Enable ((u16)0x0001) + +#define IS_TIM1_OUTPUTN_STATE(STATE) ((STATE == TIM1_OutputNState_Disable) || \ + (STATE == TIM1_OutputNState_Enable)) + +/* Break Input enable/disable -----------------------------------------------*/ +#define TIM1_Break_Enable ((u16)0x1000) +#define TIM1_Break_Disable ((u16)0x0000) + +#define IS_TIM1_BREAK_STATE(STATE) ((STATE == TIM1_Break_Enable) || \ + (STATE == TIM1_Break_Disable)) + +/* Break Polarity -----------------------------------------------------------*/ +#define TIM1_BreakPolarity_Low ((u16)0x0000) +#define TIM1_BreakPolarity_High ((u16)0x2000) + +#define IS_TIM1_BREAK_POLARITY(POLARITY) ((POLARITY == TIM1_BreakPolarity_Low) || \ + (POLARITY == TIM1_BreakPolarity_High)) + +/* TIM1 AOE Bit Set/Reset ---------------------------------------------------*/ +#define TIM1_AutomaticOutput_Enable ((u16)0x4000) +#define TIM1_AutomaticOutput_Disable ((u16)0x0000) + +#define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) ((STATE == TIM1_AutomaticOutput_Enable) || \ + (STATE == TIM1_AutomaticOutput_Disable)) +/* Lock levels --------------------------------------------------------------*/ +#define TIM1_LOCKLevel_OFF ((u16)0x0000) +#define TIM1_LOCKLevel_1 ((u16)0x0100) +#define TIM1_LOCKLevel_2 ((u16)0x0200) +#define TIM1_LOCKLevel_3 ((u16)0x0300) + +#define IS_TIM1_LOCK_LEVEL(LEVEL) ((LEVEL == TIM1_LOCKLevel_OFF) || \ + (LEVEL == TIM1_LOCKLevel_1) || \ + (LEVEL == TIM1_LOCKLevel_2) || \ + (LEVEL == TIM1_LOCKLevel_3)) + +/* OSSI: Off-State Selection for Idle mode states ---------------------------*/ +#define TIM1_OSSIState_Enable ((u16)0x0400) +#define TIM1_OSSIState_Disable ((u16)0x0000) + +#define IS_TIM1_OSSI_STATE(STATE) ((STATE == TIM1_OSSIState_Enable) || \ + (STATE == TIM1_OSSIState_Disable)) + +/* OSSR: Off-State Selection for Run mode states ----------------------------*/ +#define TIM1_OSSRState_Enable ((u16)0x0800) +#define TIM1_OSSRState_Disable ((u16)0x0000) + +#define IS_TIM1_OSSR_STATE(STATE) ((STATE == TIM1_OSSRState_Enable) || \ + (STATE == TIM1_OSSRState_Disable)) + +/* TIM1 Output Compare Idle State -------------------------------------------*/ +#define TIM1_OCIdleState_Set ((u16)0x0001) +#define TIM1_OCIdleState_Reset ((u16)0x0000) + +#define IS_TIM1_OCIDLE_STATE(STATE) ((STATE == TIM1_OCIdleState_Set) || \ + (STATE == TIM1_OCIdleState_Reset)) + +/* TIM1 Output Compare N Idle State -----------------------------------------*/ +#define TIM1_OCNIdleState_Set ((u16)0x0001) +#define TIM1_OCNIdleState_Reset ((u16)0x0000) + +#define IS_TIM1_OCNIDLE_STATE(STATE) ((STATE == TIM1_OCNIdleState_Set) || \ + (STATE == TIM1_OCNIdleState_Reset)) + +/* TIM1 Input Capture Polarity ----------------------------------------------*/ +#define TIM1_ICPolarity_Rising ((u16)0x0000) +#define TIM1_ICPolarity_Falling ((u16)0x0001) + +#define IS_TIM1_IC_POLARITY(POLARITY) ((POLARITY == TIM1_ICPolarity_Rising) || \ + (POLARITY == TIM1_ICPolarity_Falling)) + +/* TIM1 Input Capture Selection ---------------------------------------------*/ +#define TIM1_ICSelection_DirectTI ((u16)0x0001) +#define TIM1_ICSelection_IndirectTI ((u16)0x0002) +#define TIM1_ICSelection_TRGI ((u16)0x0003) + +#define IS_TIM1_IC_SELECTION(SELECTION) ((SELECTION == TIM1_ICSelection_DirectTI) || \ + (SELECTION == TIM1_ICSelection_IndirectTI) || \ + (SELECTION == TIM1_ICSelection_TRGI)) + +/* TIM1 Input Capture Prescaler ---------------------------------------------*/ +#define TIM1_ICPSC_DIV1 ((u16)0x0000) +#define TIM1_ICPSC_DIV2 ((u16)0x0004) +#define TIM1_ICPSC_DIV4 ((u16)0x0008) +#define TIM1_ICPSC_DIV8 ((u16)0x000C) + +#define IS_TIM1_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ICPSC_DIV1) || \ + (PRESCALER == TIM1_ICPSC_DIV2) || \ + (PRESCALER == TIM1_ICPSC_DIV4) || \ + (PRESCALER == TIM1_ICPSC_DIV8)) + +/* TIM1 Input Capture Filer Value ---------------------------------------------*/ +#define IS_TIM1_IC_FILTER(ICFILTER) (ICFILTER <= 0xF) + +/* TIM1 interrupt sources ---------------------------------------------------*/ +#define TIM1_IT_Update ((u16)0x0001) +#define TIM1_IT_CC1 ((u16)0x0002) +#define TIM1_IT_CC2 ((u16)0x0004) +#define TIM1_IT_CC3 ((u16)0x0008) +#define TIM1_IT_CC4 ((u16)0x0010) +#define TIM1_IT_COM ((u16)0x0020) +#define TIM1_IT_Trigger ((u16)0x0040) +#define TIM1_IT_Break ((u16)0x0080) + +#define IS_TIM1_IT(IT) (((IT & (u16)0xFF00) == 0x0000) && (IT != 0x0000)) + +#define IS_TIM1_GET_IT(IT) ((IT == TIM1_IT_Update) || \ + (IT == TIM1_IT_CC1) || \ + (IT == TIM1_IT_CC2) || \ + (IT == TIM1_IT_CC3) || \ + (IT == TIM1_IT_CC4) || \ + (IT == TIM1_IT_COM) || \ + (IT == TIM1_IT_Trigger) || \ + (IT == TIM1_IT_Break)) + +/* TIM1 DMA Base address ----------------------------------------------------*/ +#define TIM1_DMABase_CR1 ((u16)0x0000) +#define TIM1_DMABase_CR2 ((u16)0x0001) +#define TIM1_DMABase_SMCR ((u16)0x0002) +#define TIM1_DMABase_DIER ((u16)0x0003) +#define TIM1_DMABase_SR ((u16)0x0004) +#define TIM1_DMABase_EGR ((u16)0x0005) +#define TIM1_DMABase_CCMR1 ((u16)0x0006) +#define TIM1_DMABase_CCMR2 ((u16)0x0007) +#define TIM1_DMABase_CCER ((u16)0x0008) +#define TIM1_DMABase_CNT ((u16)0x0009) +#define TIM1_DMABase_PSC ((u16)0x000A) +#define TIM1_DMABase_ARR ((u16)0x000B) +#define TIM1_DMABase_RCR ((u16)0x000C) +#define TIM1_DMABase_CCR1 ((u16)0x000D) +#define TIM1_DMABase_CCR2 ((u16)0x000E) +#define TIM1_DMABase_CCR3 ((u16)0x000F) +#define TIM1_DMABase_CCR4 ((u16)0x0010) +#define TIM1_DMABase_BDTR ((u16)0x0011) +#define TIM1_DMABase_DCR ((u16)0x0012) + +#define IS_TIM1_DMA_BASE(BASE) ((BASE == TIM1_DMABase_CR1) || \ + (BASE == TIM1_DMABase_CR2) || \ + (BASE == TIM1_DMABase_SMCR) || \ + (BASE == TIM1_DMABase_DIER) || \ + (BASE == TIM1_DMABase_SR) || \ + (BASE == TIM1_DMABase_EGR) || \ + (BASE == TIM1_DMABase_CCMR1) || \ + (BASE == TIM1_DMABase_CCMR2) || \ + (BASE == TIM1_DMABase_CCER) || \ + (BASE == TIM1_DMABase_CNT) || \ + (BASE == TIM1_DMABase_PSC) || \ + (BASE == TIM1_DMABase_ARR) || \ + (BASE == TIM1_DMABase_RCR) || \ + (BASE == TIM1_DMABase_CCR1) || \ + (BASE == TIM1_DMABase_CCR2) || \ + (BASE == TIM1_DMABase_CCR3) || \ + (BASE == TIM1_DMABase_CCR4) || \ + (BASE == TIM1_DMABase_BDTR) || \ + (BASE == TIM1_DMABase_DCR)) + +/* TIM1 DMA Burst Length ----------------------------------------------------*/ +#define TIM1_DMABurstLength_1Byte ((u16)0x0000) +#define TIM1_DMABurstLength_2Bytes ((u16)0x0100) +#define TIM1_DMABurstLength_3Bytes ((u16)0x0200) +#define TIM1_DMABurstLength_4Bytes ((u16)0x0300) +#define TIM1_DMABurstLength_5Bytes ((u16)0x0400) +#define TIM1_DMABurstLength_6Bytes ((u16)0x0500) +#define TIM1_DMABurstLength_7Bytes ((u16)0x0600) +#define TIM1_DMABurstLength_8Bytes ((u16)0x0700) +#define TIM1_DMABurstLength_9Bytes ((u16)0x0800) +#define TIM1_DMABurstLength_10Bytes ((u16)0x0900) +#define TIM1_DMABurstLength_11Bytes ((u16)0x0A00) +#define TIM1_DMABurstLength_12Bytes ((u16)0x0B00) +#define TIM1_DMABurstLength_13Bytes ((u16)0x0C00) +#define TIM1_DMABurstLength_14Bytes ((u16)0x0D00) +#define TIM1_DMABurstLength_15Bytes ((u16)0x0E00) +#define TIM1_DMABurstLength_16Bytes ((u16)0x0F00) +#define TIM1_DMABurstLength_17Bytes ((u16)0x1000) +#define TIM1_DMABurstLength_18Bytes ((u16)0x1100) + +#define IS_TIM1_DMA_LENGTH(LENGTH) ((LENGTH == TIM1_DMABurstLength_1Byte) || \ + (LENGTH == TIM1_DMABurstLength_2Bytes) || \ + (LENGTH == TIM1_DMABurstLength_3Bytes) || \ + (LENGTH == TIM1_DMABurstLength_4Bytes) || \ + (LENGTH == TIM1_DMABurstLength_5Bytes) || \ + (LENGTH == TIM1_DMABurstLength_6Bytes) || \ + (LENGTH == TIM1_DMABurstLength_7Bytes) || \ + (LENGTH == TIM1_DMABurstLength_8Bytes) || \ + (LENGTH == TIM1_DMABurstLength_9Bytes) || \ + (LENGTH == TIM1_DMABurstLength_10Bytes) || \ + (LENGTH == TIM1_DMABurstLength_11Bytes) || \ + (LENGTH == TIM1_DMABurstLength_12Bytes) || \ + (LENGTH == TIM1_DMABurstLength_13Bytes) || \ + (LENGTH == TIM1_DMABurstLength_14Bytes) || \ + (LENGTH == TIM1_DMABurstLength_15Bytes) || \ + (LENGTH == TIM1_DMABurstLength_16Bytes) || \ + (LENGTH == TIM1_DMABurstLength_17Bytes) || \ + (LENGTH == TIM1_DMABurstLength_18Bytes)) + +/* TIM1 DMA sources ---------------------------------------------------------*/ +#define TIM1_DMA_Update ((u16)0x0100) +#define TIM1_DMA_CC1 ((u16)0x0200) +#define TIM1_DMA_CC2 ((u16)0x0400) +#define TIM1_DMA_CC3 ((u16)0x0800) +#define TIM1_DMA_CC4 ((u16)0x1000) +#define TIM1_DMA_COM ((u16)0x2000) +#define TIM1_DMA_Trigger ((u16)0x4000) + +#define IS_TIM1_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0x80FF) == 0x0000) && (SOURCE != 0x0000)) + +/* TIM1 External Trigger Prescaler ------------------------------------------*/ +#define TIM1_ExtTRGPSC_OFF ((u16)0x0000) +#define TIM1_ExtTRGPSC_DIV2 ((u16)0x1000) +#define TIM1_ExtTRGPSC_DIV4 ((u16)0x2000) +#define TIM1_ExtTRGPSC_DIV8 ((u16)0x3000) + +#define IS_TIM1_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ExtTRGPSC_OFF) || \ + (PRESCALER == TIM1_ExtTRGPSC_DIV2) || \ + (PRESCALER == TIM1_ExtTRGPSC_DIV4) || \ + (PRESCALER == TIM1_ExtTRGPSC_DIV8)) + +/* TIM1 Internal Trigger Selection ------------------------------------------*/ +#define TIM1_TS_ITR0 ((u16)0x0000) +#define TIM1_TS_ITR1 ((u16)0x0010) +#define TIM1_TS_ITR2 ((u16)0x0020) +#define TIM1_TS_ITR3 ((u16)0x0030) +#define TIM1_TS_TI1F_ED ((u16)0x0040) +#define TIM1_TS_TI1FP1 ((u16)0x0050) +#define TIM1_TS_TI2FP2 ((u16)0x0060) +#define TIM1_TS_ETRF ((u16)0x0070) + +#define IS_TIM1_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \ + (SELECTION == TIM1_TS_ITR1) || \ + (SELECTION == TIM1_TS_ITR2) || \ + (SELECTION == TIM1_TS_ITR3) || \ + (SELECTION == TIM1_TS_TI1F_ED) || \ + (SELECTION == TIM1_TS_TI1FP1) || \ + (SELECTION == TIM1_TS_TI2FP2) || \ + (SELECTION == TIM1_TS_ETRF)) + +#define IS_TIM1_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \ + (SELECTION == TIM1_TS_ITR1) || \ + (SELECTION == TIM1_TS_ITR2) || \ + (SELECTION == TIM1_TS_ITR3)) + +#define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_TI1F_ED) || \ + (SELECTION == TIM1_TS_TI1FP1) || \ + (SELECTION == TIM1_TS_TI2FP2)) + +/* TIM1 External Trigger Polarity -------------------------------------------*/ +#define TIM1_ExtTRGPolarity_Inverted ((u16)0x8000) +#define TIM1_ExtTRGPolarity_NonInverted ((u16)0x0000) + +#define IS_TIM1_EXT_POLARITY(POLARITY) ((POLARITY == TIM1_ExtTRGPolarity_Inverted) || \ + (POLARITY == TIM1_ExtTRGPolarity_NonInverted)) + +/* TIM1 Prescaler Reload Mode -----------------------------------------------*/ +#define TIM1_PSCReloadMode_Update ((u16)0x0000) +#define TIM1_PSCReloadMode_Immediate ((u16)0x0001) + +#define IS_TIM1_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM1_PSCReloadMode_Update) || \ + (RELOAD == TIM1_PSCReloadMode_Immediate)) + +/* TIM1 Forced Action -------------------------------------------------------*/ +#define TIM1_ForcedAction_Active ((u16)0x0050) +#define TIM1_ForcedAction_InActive ((u16)0x0040) + +#define IS_TIM1_FORCED_ACTION(ACTION) ((ACTION == TIM1_ForcedAction_Active) || \ + (ACTION == TIM1_ForcedAction_InActive)) + +/* TIM1 Encoder Mode --------------------------------------------------------*/ +#define TIM1_EncoderMode_TI1 ((u16)0x0001) +#define TIM1_EncoderMode_TI2 ((u16)0x0002) +#define TIM1_EncoderMode_TI12 ((u16)0x0003) + +#define IS_TIM1_ENCODER_MODE(MODE) ((MODE == TIM1_EncoderMode_TI1) || \ + (MODE == TIM1_EncoderMode_TI2) || \ + (MODE == TIM1_EncoderMode_TI12)) + +/* TIM1 Event Source --------------------------------------------------------*/ +#define TIM1_EventSource_Update ((u16)0x0001) +#define TIM1_EventSource_CC1 ((u16)0x0002) +#define TIM1_EventSource_CC2 ((u16)0x0004) +#define TIM1_EventSource_CC3 ((u16)0x0008) +#define TIM1_EventSource_CC4 ((u16)0x0010) +#define TIM1_EventSource_COM ((u16)0x0020) +#define TIM1_EventSource_Trigger ((u16)0x0040) +#define TIM1_EventSource_Break ((u16)0x0080) + +#define IS_TIM1_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFF00) == 0x0000) && (SOURCE != 0x0000)) + + +/* TIM1 Update Source -------------------------------------------------------*/ +#define TIM1_UpdateSource_Global ((u16)0x0000) +#define TIM1_UpdateSource_Regular ((u16)0x0001) + +#define IS_TIM1_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM1_UpdateSource_Global) || \ + (SOURCE == TIM1_UpdateSource_Regular)) + +/* TIM1 Ouput Compare Preload State ------------------------------------------*/ +#define TIM1_OCPreload_Enable ((u16)0x0001) +#define TIM1_OCPreload_Disable ((u16)0x0000) + +#define IS_TIM1_OCPRELOAD_STATE(STATE) ((STATE == TIM1_OCPreload_Enable) || \ + (STATE == TIM1_OCPreload_Disable)) + +/* TIM1 Ouput Compare Fast State ---------------------------------------------*/ +#define TIM1_OCFast_Enable ((u16)0x0001) +#define TIM1_OCFast_Disable ((u16)0x0000) + +#define IS_TIM1_OCFAST_STATE(STATE) ((STATE == TIM1_OCFast_Enable) || \ + (STATE == TIM1_OCFast_Disable)) + +/* TIM1 Trigger Output Source -----------------------------------------------*/ +#define TIM1_TRGOSource_Reset ((u16)0x0000) +#define TIM1_TRGOSource_Enable ((u16)0x0010) +#define TIM1_TRGOSource_Update ((u16)0x0020) +#define TIM1_TRGOSource_OC1 ((u16)0x0030) +#define TIM1_TRGOSource_OC1Ref ((u16)0x0040) +#define TIM1_TRGOSource_OC2Ref ((u16)0x0050) +#define TIM1_TRGOSource_OC3Ref ((u16)0x0060) +#define TIM1_TRGOSource_OC4Ref ((u16)0x0070) + +#define IS_TIM1_TRGO_SOURCE(SOURCE) ((SOURCE == TIM1_TRGOSource_Reset) || \ + (SOURCE == TIM1_TRGOSource_Enable) || \ + (SOURCE == TIM1_TRGOSource_Update) || \ + (SOURCE == TIM1_TRGOSource_OC1) || \ + (SOURCE == TIM1_TRGOSource_OC1Ref) || \ + (SOURCE == TIM1_TRGOSource_OC2Ref) || \ + (SOURCE == TIM1_TRGOSource_OC3Ref) || \ + (SOURCE == TIM1_TRGOSource_OC4Ref)) + +/* TIM1 Slave Mode ----------------------------------------------------------*/ +#define TIM1_SlaveMode_Reset ((u16)0x0004) +#define TIM1_SlaveMode_Gated ((u16)0x0005) +#define TIM1_SlaveMode_Trigger ((u16)0x0006) +#define TIM1_SlaveMode_External1 ((u16)0x0007) + +#define IS_TIM1_SLAVE_MODE(MODE) ((MODE == TIM1_SlaveMode_Reset) || \ + (MODE == TIM1_SlaveMode_Gated) || \ + (MODE == TIM1_SlaveMode_Trigger) || \ + (MODE == TIM1_SlaveMode_External1)) + +/* TIM1 TIx External Clock Source -------------------------------------------*/ +#define TIM1_TIxExternalCLK1Source_TI1 ((u16)0x0050) +#define TIM1_TIxExternalCLK1Source_TI2 ((u16)0x0060) +#define TIM1_TIxExternalCLK1Source_TI1ED ((u16)0x0040) + +#define IS_TIM1_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM1_TIxExternalCLK1Source_TI1) || \ + (SOURCE == TIM1_TIxExternalCLK1Source_TI2) || \ + (SOURCE == TIM1_TIxExternalCLK1Source_TI1ED)) + +/* TIM1 Master Slave Mode ---------------------------------------------------*/ +#define TIM1_MasterSlaveMode_Enable ((u16)0x0001) +#define TIM1_MasterSlaveMode_Disable ((u16)0x0000) + +#define IS_TIM1_MSM_STATE(STATE) ((STATE == TIM1_MasterSlaveMode_Enable) || \ + (STATE == TIM1_MasterSlaveMode_Disable)) + +/* TIM1 Flags ---------------------------------------------------------------*/ +#define TIM1_FLAG_Update ((u16)0x0001) +#define TIM1_FLAG_CC1 ((u16)0x0002) +#define TIM1_FLAG_CC2 ((u16)0x0004) +#define TIM1_FLAG_CC3 ((u16)0x0008) +#define TIM1_FLAG_CC4 ((u16)0x0010) +#define TIM1_FLAG_COM ((u16)0x0020) +#define TIM1_FLAG_Trigger ((u16)0x0040) +#define TIM1_FLAG_Break ((u16)0x0080) +#define TIM1_FLAG_CC1OF ((u16)0x0200) +#define TIM1_FLAG_CC2OF ((u16)0x0400) +#define TIM1_FLAG_CC3OF ((u16)0x0800) +#define TIM1_FLAG_CC4OF ((u16)0x1000) + +#define IS_TIM1_GET_FLAG(FLAG) ((FLAG == TIM1_FLAG_Update) || \ + (FLAG == TIM1_FLAG_CC1) || \ + (FLAG == TIM1_FLAG_CC2) || \ + (FLAG == TIM1_FLAG_CC3) || \ + (FLAG == TIM1_FLAG_CC4) || \ + (FLAG == TIM1_FLAG_COM) || \ + (FLAG == TIM1_FLAG_Trigger) || \ + (FLAG == TIM1_FLAG_Break) || \ + (FLAG == TIM1_FLAG_CC1OF) || \ + (FLAG == TIM1_FLAG_CC2OF) || \ + (FLAG == TIM1_FLAG_CC3OF) || \ + (FLAG == TIM1_FLAG_CC4OF)) + +#define IS_TIM1_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE100) == 0x0000) && (FLAG != 0x0000)) + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void TIM1_DeInit(void); +void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct); +void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct); +void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct); +void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct); +void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct); +void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct); +void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct); +void TIM1_Cmd(FunctionalState NewState); +void TIM1_CtrlPWMOutputs(FunctionalState Newstate); +void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState); +void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength); +void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate); +void TIM1_InternalClockConfig(void); +void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter); +void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter); +void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource); +void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, u16 TIM1_ICPolarity, + u8 ICFilter); +void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource); +void TIM1_UpdateDisableConfig(FunctionalState Newstate); +void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource); +void TIM1_SelectHallSensor(FunctionalState Newstate); +void TIM1_SelectOnePulseMode(u16 TIM1_OPMode); +void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource); +void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode); +void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode); +void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity, + u16 TIM1_IC2Polarity); +void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode); +void TIM1_CounterModeConfig(u16 TIM1_CounterMode); +void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction); +void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction); +void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction); +void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction); +void TIM1_ARRPreloadConfig(FunctionalState Newstate); +void TIM1_SelectCOM(FunctionalState Newstate); +void TIM1_SelectCCDMA(FunctionalState Newstate); +void TIM1_CCPreloadControl(FunctionalState Newstate); +void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload); +void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload); +void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload); +void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload); +void TIM1_OC1FastConfig(u16 TIM1_OCFast); +void TIM1_OC2FastConfig(u16 TIM1_OCFast); +void TIM1_OC3FastConfig(u16 TIM1_OCFast); +void TIM1_OC4FastConfig(u16 TIM1_OCFast); +void TIM1_GenerateEvent(u16 TIM1_EventSource); +void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity); +void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate); +void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate); +void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode); +void TIM1_SetAutoreload(u16 Autoreload); +void TIM1_SetCompare1(u16 Compare1); +void TIM1_SetCompare2(u16 Compare2); +void TIM1_SetCompare3(u16 Compare3); +void TIM1_SetCompare4(u16 Compare4); +void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler); +void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler); +void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler); +void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler); +void TIM1_SetClockDivision(u16 TIM1_CKD); +u16 TIM1_GetCapture1(void); +u16 TIM1_GetCapture2(void); +u16 TIM1_GetCapture3(void); +u16 TIM1_GetCapture4(void); +u16 TIM1_GetCounter(void); +u16 TIM1_GetPrescaler(void); +FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG); +void TIM1_ClearFlag(u16 TIM1_Flag); +ITStatus TIM1_GetITStatus(u16 TIM1_IT); +void TIM1_ClearITPendingBit(u16 TIM1_IT); + +#endif /*__STM32F10x_TIM1_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_type.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_type.h new file mode 100644 index 0000000..d6e83a9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_type.h @@ -0,0 +1,76 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_type.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the common data types used for the +* STM32F10x firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TYPE_H +#define __STM32F10x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)2147483648uL) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_TYPE_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_usart.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_usart.h new file mode 100644 index 0000000..e8c44aa --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_usart.h @@ -0,0 +1,219 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_usart.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* USART firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* UART Init Structure definition */ +typedef struct +{ + u32 USART_BaudRate; + u16 USART_WordLength; + u16 USART_StopBits; + u16 USART_Parity; + u16 USART_HardwareFlowControl; + u16 USART_Mode; + u16 USART_Clock; + u16 USART_CPOL; + u16 USART_CPHA; + u16 USART_LastBit; +} USART_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* USART Word Length ---------------------------------------------------------*/ +#define USART_WordLength_8b ((u16)0x0000) +#define USART_WordLength_9b ((u16)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WordLength_8b) || \ + (LENGTH == USART_WordLength_9b)) + +/* USART Stop Bits -----------------------------------------------------------*/ +#define USART_StopBits_1 ((u16)0x0000) +#define USART_StopBits_0_5 ((u16)0x1000) +#define USART_StopBits_2 ((u16)0x2000) +#define USART_StopBits_1_5 ((u16)0x3000) + +#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_StopBits_1) || \ + (STOPBITS == USART_StopBits_0_5) || \ + (STOPBITS == USART_StopBits_2) || \ + (STOPBITS == USART_StopBits_1_5)) +/* USART Parity --------------------------------------------------------------*/ +#define USART_Parity_No ((u16)0x0000) +#define USART_Parity_Even ((u16)0x0400) +#define USART_Parity_Odd ((u16)0x0600) + +#define IS_USART_PARITY(PARITY) ((PARITY == USART_Parity_No) || \ + (PARITY == USART_Parity_Even) || \ + (PARITY == USART_Parity_Odd)) + +/* USART Hardware Flow Control -----------------------------------------------*/ +#define USART_HardwareFlowControl_None ((u16)0x0000) +#define USART_HardwareFlowControl_RTS ((u16)0x0100) +#define USART_HardwareFlowControl_CTS ((u16)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300) + +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + ((CONTROL == USART_HardwareFlowControl_None) || \ + (CONTROL == USART_HardwareFlowControl_RTS) || \ + (CONTROL == USART_HardwareFlowControl_CTS) || \ + (CONTROL == USART_HardwareFlowControl_RTS_CTS)) + +/* USART Mode ----------------------------------------------------------------*/ +#define USART_Mode_Rx ((u16)0x0004) +#define USART_Mode_Tx ((u16)0x0008) + +#define IS_USART_MODE(MODE) (((MODE & (u16)0xFFF3) == 0x00) && (MODE != (u16)0x00)) + +/* USART Clock ---------------------------------------------------------------*/ +#define USART_Clock_Disable ((u16)0x0000) +#define USART_Clock_Enable ((u16)0x0800) + +#define IS_USART_CLOCK(CLOCK) ((CLOCK == USART_Clock_Disable) || \ + (CLOCK == USART_Clock_Enable)) + +/* USART Clock Polarity ------------------------------------------------------*/ +#define USART_CPOL_Low ((u16)0x0000) +#define USART_CPOL_High ((u16)0x0400) + +#define IS_USART_CPOL(CPOL) ((CPOL == USART_CPOL_Low) || (CPOL == USART_CPOL_High)) + +/* USART Clock Phase ---------------------------------------------------------*/ +#define USART_CPHA_1Edge ((u16)0x0000) +#define USART_CPHA_2Edge ((u16)0x0200) +#define IS_USART_CPHA(CPHA) ((CPHA == USART_CPHA_1Edge) || (CPHA == USART_CPHA_2Edge)) + +/* USART Last Bit ------------------------------------------------------------*/ +#define USART_LastBit_Disable ((u16)0x0000) +#define USART_LastBit_Enable ((u16)0x0100) + +#define IS_USART_LASTBIT(LASTBIT) ((LASTBIT == USART_LastBit_Disable) || \ + (LASTBIT == USART_LastBit_Enable)) + +/* USART Interrupt definition ------------------------------------------------*/ +#define USART_IT_PE ((u16)0x0028) +#define USART_IT_TXE ((u16)0x0727) +#define USART_IT_TC ((u16)0x0626) +#define USART_IT_RXNE ((u16)0x0525) +#define USART_IT_IDLE ((u16)0x0424) +#define USART_IT_LBD ((u16)0x0846) +#define USART_IT_CTS ((u16)0x096A) +#define USART_IT_ERR ((u16)0x0060) +#define USART_IT_ORE ((u16)0x0360) +#define USART_IT_NE ((u16)0x0260) +#define USART_IT_FE ((u16)0x0160) + +#define IS_USART_CONFIG_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \ + (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \ + (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \ + (IT == USART_IT_CTS) || (IT == USART_IT_ERR)) + +#define IS_USART_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \ + (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \ + (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \ + (IT == USART_IT_CTS) || (IT == USART_IT_ORE) || \ + (IT == USART_IT_NE) || (IT == USART_IT_FE)) + +/* USART DMA Requests --------------------------------------------------------*/ +#define USART_DMAReq_Tx ((u16)0x0080) +#define USART_DMAReq_Rx ((u16)0x0040) + +#define IS_USART_DMAREQ(DMAREQ) (((DMAREQ & (u16)0xFF3F) == 0x00) && (DMAREQ != (u16)0x00)) + +/* USART WakeUp methods ------------------------------------------------------*/ +#define USART_WakeUp_IdleLine ((u16)0x0000) +#define USART_WakeUp_AddressMark ((u16)0x0800) + +#define IS_USART_WAKEUP(WAKEUP) ((WAKEUP == USART_WakeUp_IdleLine) || \ + (WAKEUP == USART_WakeUp_AddressMark)) + +/* USART LIN Break Detection Length ------------------------------------------*/ +#define USART_LINBreakDetectLength_10b ((u16)0x0000) +#define USART_LINBreakDetectLength_11b ((u16)0x0020) + +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + ((LENGTH == USART_LINBreakDetectLength_10b) || \ + (LENGTH == USART_LINBreakDetectLength_11b)) + +/* USART IrDA Low Power ------------------------------------------------------*/ +#define USART_IrDAMode_LowPower ((u16)0x0004) +#define USART_IrDAMode_Normal ((u16)0x0000) + +#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IrDAMode_LowPower) || \ + (MODE == USART_IrDAMode_Normal)) + +/* USART Flags ---------------------------------------------------------------*/ +#define USART_FLAG_CTS ((u16)0x0200) +#define USART_FLAG_LBD ((u16)0x0100) +#define USART_FLAG_TXE ((u16)0x0080) +#define USART_FLAG_TC ((u16)0x0040) +#define USART_FLAG_RXNE ((u16)0x0020) +#define USART_FLAG_IDLE ((u16)0x0010) +#define USART_FLAG_ORE ((u16)0x0008) +#define USART_FLAG_NE ((u16)0x0004) +#define USART_FLAG_FE ((u16)0x0002) +#define USART_FLAG_PE ((u16)0x0001) + +#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_TXE) || \ + (FLAG == USART_FLAG_TC) || (FLAG == USART_FLAG_RXNE) || \ + (FLAG == USART_FLAG_IDLE) || (FLAG == USART_FLAG_LBD) || \ + (FLAG == USART_FLAG_CTS) || (FLAG == USART_FLAG_ORE) || \ + (FLAG == USART_FLAG_NE) || (FLAG == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFC00) == 0x00) && (FLAG != (u16)0x00)) + +#define IS_USART_ADDRESS(ADDRESS) (ADDRESS <= 0xF) +#define IS_USART_DATA(DATA) (DATA <= 0x1FF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, u16 Data); +u16 USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT); + +#endif /* __STM32F10x_USART_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_wwdg.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_wwdg.h new file mode 100644 index 0000000..2230b58 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_wwdg.h @@ -0,0 +1,58 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_wwdg.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* WWDG firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* WWDG Prescaler */ +#define WWDG_Prescaler_1 ((u32)0x00000000) +#define WWDG_Prescaler_2 ((u32)0x00000080) +#define WWDG_Prescaler_4 ((u32)0x00000100) +#define WWDG_Prescaler_8 ((u32)0x00000180) + +#define IS_WWDG_PRESCALER(PRESCALER) ((PRESCALER == WWDG_Prescaler_1) || \ + (PRESCALER == WWDG_Prescaler_2) || \ + (PRESCALER == WWDG_Prescaler_4) || \ + (PRESCALER == WWDG_Prescaler_8)) + +#define IS_WWDG_WINDOW_VALUE(VALUE) (VALUE <= 0x7F) + +#define IS_WWDG_COUNTER(COUNTER) ((COUNTER >= 0x40) && (COUNTER <= 0x7F)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void WWDG_DeInit(void); +void WWDG_SetPrescaler(u32 WWDG_Prescaler); +void WWDG_SetWindowValue(u8 WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(u8 Counter); +void WWDG_Enable(u8 Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#endif /* __STM32F10x_WWDG_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h new file mode 100644 index 0000000..11f15b0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h @@ -0,0 +1,1118 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32fxxx_eth.h +* Author : MCD Application Team +* Version : V0.0.1 +* Date : 12/17/2008 +* Desciption : This file contains all the functions prototypes for the +* ETHERNET firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32FXXX_ETH_H +#define __STM32FXXX_ETH_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32fxxx_eth_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* ETHERNET MAC Init structure definition */ +typedef struct { + /* MAC ----------------------------------*/ + u32 ETH_AutoNegotiation; /* Selects or not the AutoNegotiation with the external PHY */ + u32 ETH_Watchdog; /* Enable/disable Watchdog timer */ + u32 ETH_Jabber; /* Enable/disable Jabber timer */ + u32 ETH_JumboFrame; /* Enable/disable Jumbo frame */ + u32 ETH_InterFrameGap; /* Selects minimum IFG between frames during transmission */ + u32 ETH_CarrierSense; /* Enable/disable Carrier Sense */ + u32 ETH_Speed; /* Indicates the Ethernet speed: 10/100 Mbps */ + u32 ETH_ReceiveOwn; /* Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */ + u32 ETH_LoopbackMode; /* Enable/disable internal MAC MII Loopback mode */ + u32 ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ + u32 ETH_ChecksumOffload; /* Enable/disable the calculation of complement sum of all received Ethernet frame payloads */ + u32 ETH_RetryTransmission; /* Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */ + u32 ETH_AutomaticPadCRCStrip; /* Enable/disable Automatic MAC Pad/CRC Stripping */ + u32 ETH_BackOffLimit; /* Selects the BackOff limit value */ + u32 ETH_DeferralCheck; /* Enable/disable deferral check function (Half-Duplex mode) */ + u32 ETH_ReceiveAll; /* Enable/disable all frames reception by the MAC (No fitering)*/ + u32 ETH_SourceAddrFilter; /* Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */ + u32 ETH_PassControlFrames; /* Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */ + u32 ETH_BroadcastFramesReception; /* Enable/disable reception of Broadcast Frames */ + u32 ETH_DestinationAddrFilter; /* Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */ + u32 ETH_PromiscuousMode; /* Enable/disable Promiscuous Mode */ + u32 ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + u32 ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + u32 ETH_HashTableHigh; /* This field contains the higher 32 bits of Hash table. */ + u32 ETH_HashTableLow; /* This field contains the lower 32 bits of Hash table. */ + u32 ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the transmit control frame */ + u32 ETH_ZeroQuantaPause; /* Enable/disable the automatic generation of Zero-Quanta Pause Control frames */ + u32 ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */ + u32 ETH_UnicastPauseFrameDetect; /* Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */ + u32 ETH_ReceiveFlowControl; /* Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */ + u32 ETH_TransmitFlowControl; /* Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */ + u32 ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */ + u32 ETH_VLANTagIdentifier; /* VLAN tag identifier for receive frames */ + + /* DMA --------------------------*/ + u32 ETH_DropTCPIPChecksumErrorFrame; /* Enable/disable Dropping of TCP/IP Checksum Error Frames */ + u32 ETH_ReceiveStoreForward; /* Enable/disable Receive store and forward */ + u32 ETH_FlushReceivedFrame; /* Enable/disable flushing of received frames */ + u32 ETH_TransmitStoreForward; /* Enable/disable Transmit store and forward */ + u32 ETH_TransmitThresholdControl; /* Selects the Transmit Threshold Control */ + u32 ETH_ForwardErrorFrames; /* Enable/disable forward to DMA of all frames except runt error frames */ + u32 ETH_ForwardUndersizedGoodFrames; /* Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */ + u32 ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO */ + u32 ETH_SecondFrameOperate; /* Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */ + u32 ETH_AddressAlignedBeats; /* Enable/disable Address Aligned Beats */ + u32 ETH_FixedBurst; /* Enable/disable the AHB Master interface fixed burst transfers */ + u32 ETH_RxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Rx DMA transaction */ + u32 ETH_TxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Tx DMA transaction */ + u32 ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + u32 ETH_DMAArbitration; /* Selects DMA Tx/Rx arbitration */ +}ETH_InitTypeDef; + +/*----------------------------------------------------------------------------*/ +/* DMA descriptors types */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET DMA Desciptors data structure definition */ +typedef struct { + volatile u32 Status; /* Status */ + volatile u32 ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + volatile u32 Buffer1Addr; /* Buffer1 address pointer */ + volatile u32 Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* ETHERNET Frames defines */ +/*----------------------------------------------------------------------------*/ +/* ENET Buffers setting */ +#define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /* Ethernet CRC */ +#define ETH_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ + +/*--------------------------------------------------------*/ +/* Ethernet DMA descriptors registers bits definition */ +/*--------------------------------------------------------*/ +/* DMA Tx Desciptor ---------------------------------------------------------*/ +/*----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ----------------------------------------------------------------------------------------------*/ + +/* Bit definition of TDES0 register: DMA Tx descriptor status register */ +#define ETH_DMATxDesc_OWN (0x80000000UL) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((u32)0x40000000) /* Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((u32)0x20000000) /* Last Segment */ +#define ETH_DMATxDesc_FS ((u32)0x10000000) /* First Segment */ +#define ETH_DMATxDesc_DC ((u32)0x08000000) /* Disable CRC */ +#define ETH_DMATxDesc_DP ((u32)0x04000000) /* Disable Padding */ +#define ETH_DMATxDesc_TTSE ((u32)0x02000000) /* Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((u32)0x00C00000) /* Checksum Insertion Control: 4 cases */ + #define ETH_DMATxDesc_CIC_ByPass ((u32)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ + #define ETH_DMATxDesc_CIC_IPV4Header ((u32)0x00400000) /* IPV4 header Checksum Insertion */ + #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((u32)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ + #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((u32)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((u32)0x00200000) /* Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((u32)0x00100000) /* Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((u32)0x00020000) /* Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((u32)0x00010000) /* IP Header Error */ +#define ETH_DMATxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((u32)0x00004000) /* Jabber Timeout */ +#define ETH_DMATxDesc_FF ((u32)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((u32)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((u32)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((u32)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((u32)0x00000200) /* Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((u32)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((u32)0x00000080) /* VLAN Frame */ +#define ETH_DMATxDesc_CC ((u32)0x00000078) /* Collision Count */ +#define ETH_DMATxDesc_ED ((u32)0x00000004) /* Excessive Deferral */ +#define ETH_DMATxDesc_UF ((u32)0x00000002) /* Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((u32)0x00000001) /* Deferred Bit */ + +/* Bit definition of TDES1 register */ +#define ETH_DMATxDesc_TBS2 ((u32)0x1FFF0000) /* Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((u32)0x00001FFF) /* Transmit Buffer1 Size */ + +/* Bit definition of TDES2 register */ +#define ETH_DMATxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Bit definition of TDES3 register */ +#define ETH_DMATxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/* DMA Rx descriptor ---------------------------------------------------------*/ +/*--------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + --------------------------------------------------------------------------------------------------------------------*/ + +/* Bit definition of RDES0 register: DMA Rx descriptor status register */ +#define ETH_DMARxDesc_OWN ((u32)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((u32)0x40000000) /* DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((u32)0x3FFF0000) /* Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((u32)0x00004000) /* Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((u32)0x00002000) /* SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((u32)0x00001000) /* Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((u32)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((u32)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((u32)0x00000200) /* First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((u32)0x00000100) /* Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((u32)0x00000080) /* IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_RxLongFrame ((u32)0x00000080) /* (Giant Frame)Rx - frame is longer than 1518/1522 */ +#define ETH_DMARxDesc_LC ((u32)0x00000040) /* Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((u32)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((u32)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((u32)0x00000008) /* Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((u32)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((u32)0x00000002) /* CRC error */ +#define ETH_DMARxDesc_MAMPCE ((u32)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/* Bit definition of RDES1 register */ +#define ETH_DMARxDesc_DIC ((u32)0x80000000) /* Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((u32)0x1FFF0000) /* Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((u32)0x00008000) /* Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((u32)0x00004000) /* Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((u32)0x00001FFF) /* Receive Buffer1 Size */ + +/* Bit definition of RDES2 register */ +#define ETH_DMARxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Bit definition of RDES3 register */ +#define ETH_DMARxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/*----------------------------------------------------------------------------*/ +/* Desciption of common PHY registers */ +/*----------------------------------------------------------------------------*/ +/* PHY Read/write Timeouts */ +#define PHY_READ_TO ((u32)0x0004FFFF) +#define PHY_WRITE_TO ((u32)0x0004FFFF) + +/* PHY Reset Delay */ +#define PHY_ResetDelay ((u32)0x000FFFFF) + +/* PHY Config Delay */ +#define PHY_ConfigDelay ((u32)0x00FFFFFF) + +/* PHY Register address */ +#define PHY_BCR 0 /* Tranceiver Basic Control Register */ +#define PHY_BSR 1 /* Tranceiver Basic Status Register */ + +/* PHY basic Control register */ +#define PHY_Reset ((u16)0x8000) /* PHY Reset */ +#define PHY_Loopback ((u16)0x4000) /* Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((u16)0x2100) /* Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((u16)0x2000) /* Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((u16)0x0100) /* Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((u16)0x0000) /* Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((u16)0x1000) /* Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((u16)0x0200) /* Restart auto-negotiation function */ +#define PHY_Powerdown ((u16)0x0800) /* Select the power down mode */ +#define PHY_Isolate ((u16)0x0400) /* Isolate PHY from MII */ + +/* PHY basic status register */ +#define PHY_AutoNego_Complete ((u16)0x0020) /* Auto-Negotioation process completed */ +#define PHY_Linked_Status ((u16)0x0004) /* Valid link established */ +#define PHY_Jabber_detection ((u16)0x0002) /* Jabber condition detected */ + +/* The PHY status register value change from a PHY to another so the user have to update + this value depending on the used external PHY */ +/* For LAN8700 */ +//#define PHY_SR 31 /* Tranceiver Status Register */ +/* For DP83848 */ +#define PHY_SR 16 /* Tranceiver Status Register */ + +/* PHY status register */ +/* The Speed and Duplex mask values change from a PHY to another so the user have to update + this value depending on the used external PHY */ +/* For LAN8700 */ +//#define PHY_Speed_Status ((u16)0x0004) /* Configured information of Speed: 10Mbps */ +//#define PHY_Duplex_Status ((u16)0x0010) /* Configured information of Duplex: Full-duplex */ +/* For DP83848 */ +#define PHY_Speed_Status ((u16)0x0002) /* Configured information of Speed: 10Mbps */ +#define PHY_Duplex_Status ((u16)0x0004) /* Configured information of Duplex: Full-duplex */ + +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ + ((REG) == PHY_BSR) || \ + ((REG) == PHY_SR)) + +/*----------------------------------------------------------------------------*/ +/* MAC defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET AutoNegotiation --------------------------------------------------*/ +#define ETH_AutoNegotiation_Enable ((u32)0x00000001) +#define ETH_AutoNegotiation_Disable ((u32)0x00000000) + +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ + ((CMD) == ETH_AutoNegotiation_Disable)) + +/* ETHERNET watchdog ---------------------------------------------------------*/ +#define ETH_Watchdog_Enable ((u32)0x00000000) +#define ETH_Watchdog_Disable ((u32)0x00800000) + +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ + ((CMD) == ETH_Watchdog_Disable)) + +/* ETHERNET Jabber -----------------------------------------------------------*/ +#define ETH_Jabber_Enable ((u32)0x00000000) +#define ETH_Jabber_Disable ((u32)0x00400000) + +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ + ((CMD) == ETH_Jabber_Disable)) + +/* ETHERNET Jumbo Frame ------------------------------------------------------*/ +#define ETH_JumboFrame_Enable ((u32)0x00100000) +#define ETH_JumboFrame_Disable ((u32)0x00000000) + +#define IS_ETH_JUMBO_FRAME(CMD) (((CMD) == ETH_JumboFrame_Enable) || \ + ((CMD) == ETH_JumboFrame_Disable)) + +/* ETHERNET Inter Frame Gap --------------------------------------------------*/ +#define ETH_InterFrameGap_96Bit ((u32)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((u32)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((u32)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((u32)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((u32)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ + +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ + ((GAP) == ETH_InterFrameGap_88Bit) || \ + ((GAP) == ETH_InterFrameGap_80Bit) || \ + ((GAP) == ETH_InterFrameGap_72Bit) || \ + ((GAP) == ETH_InterFrameGap_64Bit) || \ + ((GAP) == ETH_InterFrameGap_56Bit) || \ + ((GAP) == ETH_InterFrameGap_48Bit) || \ + ((GAP) == ETH_InterFrameGap_40Bit)) + +/* ETHERNET Carrier Sense ----------------------------------------------------*/ +#define ETH_CarrierSense_Enable ((u32)0x00000000) +#define ETH_CarrierSense_Disable ((u32)0x00010000) + +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ + ((CMD) == ETH_CarrierSense_Disable)) + +/* ETHERNET Speed ------------------------------------------------------------*/ +#define ETH_Speed_10M ((u32)0x00000000) +#define ETH_Speed_100M ((u32)0x00004000) + +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ + ((SPEED) == ETH_Speed_100M)) + +/* ETHERNET Receive Own ------------------------------------------------------*/ +#define ETH_ReceiveOwn_Enable ((u32)0x00000000) +#define ETH_ReceiveOwn_Disable ((u32)0x00002000) + +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ + ((CMD) == ETH_ReceiveOwn_Disable)) + +/* ETHERNET Loop back Mode ---------------------------------------------------*/ +#define ETH_LoopbackMode_Enable ((u32)0x00001000) +#define ETH_LoopbackMode_Disable ((u32)0x00000000) + +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ + ((CMD) == ETH_LoopbackMode_Disable)) + +/* ETHERNET Duplex mode ------------------------------------------------------*/ +#define ETH_Mode_FullDuplex ((u32)0x00000800) +#define ETH_Mode_HalfDuplex ((u32)0x00000000) + +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ + ((MODE) == ETH_Mode_HalfDuplex)) + +/* ETHERNET Checksum Offload -------------------------------------------------*/ +#define ETH_ChecksumOffload_Enable ((u32)0x00000400) +#define ETH_ChecksumOffload_Disable ((u32)0x00000000) + +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ + ((CMD) == ETH_ChecksumOffload_Disable)) + +/* ETHERNET Retry Transmission -----------------------------------------------*/ +#define ETH_RetryTransmission_Enable ((u32)0x00000000) +#define ETH_RetryTransmission_Disable ((u32)0x00000200) + +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ + ((CMD) == ETH_RetryTransmission_Disable)) + +/* ETHERNET Automatic Pad/CRC Strip ------------------------------------------*/ +#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000) + +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ + ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) + +/* ETHERNET Back-Off limit ---------------------------------------------------*/ +#define ETH_BackOffLimit_10 ((u32)0x00000000) +#define ETH_BackOffLimit_8 ((u32)0x00000020) +#define ETH_BackOffLimit_4 ((u32)0x00000040) +#define ETH_BackOffLimit_1 ((u32)0x00000060) + +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ + ((LIMIT) == ETH_BackOffLimit_8) || \ + ((LIMIT) == ETH_BackOffLimit_4) || \ + ((LIMIT) == ETH_BackOffLimit_1)) + +/* ETHERNET Deferral Check ---------------------------------------------------*/ +#define ETH_DeferralCheck_Enable ((u32)0x00000010) +#define ETH_DeferralCheck_Disable ((u32)0x00000000) + +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ + ((CMD) == ETH_DeferralCheck_Disable)) + +/* ETHERNET Receive All ------------------------------------------------------*/ +#define ETH_ReceiveAll_Enable ((u32)0x80000000) +#define ETH_ReceiveAll_Disable ((u32)0x00000000) + +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ + ((CMD) == ETH_ReceiveAll_Disable)) + +/* ETHERNET Source Addr Filter ------------------------------------------------*/ +#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300) +#define ETH_SourceAddrFilter_Disable ((u32)0x00000000) + +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Disable)) + +/* ETHERNET Pass Control Frames ----------------------------------------------*/ +#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ + +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) + +/* ETHERNET Broadcast Frames Reception ---------------------------------------*/ +#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020) + +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ + ((CMD) == ETH_BroadcastFramesReception_Disable)) + +/* ETHERNET Destination Addr Filter ------------------------------------------*/ +#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008) + +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ + ((FILTER) == ETH_DestinationAddrFilter_Inverse)) + +/* ETHERNET Promiscuous Mode -------------------------------------------------*/ +#define ETH_PromiscuousMode_Enable ((u32)0x00000001) +#define ETH_PromiscuousMode_Disable ((u32)0x00000000) + +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ + ((CMD) == ETH_PromiscuousMode_Disable)) + +/* ETHERNET multicast frames filter --------------------------------------------*/ +#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000) +#define ETH_MulticastFramesFilter_None ((u32)0x00000010) + +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ + ((FILTER) == ETH_MulticastFramesFilter_None)) + +/* ETHERNET unicast frames filter --------------------------------------------*/ +#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000) + +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_Perfect)) + +/* ETHERNET Pause Time ------------------------------------------------*/ +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) + +/* ETHERNET Zero Quanta Pause ------------------------------------------------*/ +#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080) + +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ + ((CMD) == ETH_ZeroQuantaPause_Disable)) + +/* ETHERNET Pause Low Threshold ----------------------------------------------*/ +#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */ + +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) + +/* ETHERNET Unicast Pause Frame Detect ---------------------------------------*/ +#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000) + +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ + ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) + +/* ETHERNET Receive Flow Control ---------------------------------------------*/ +#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000) + +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ + ((CMD) == ETH_ReceiveFlowControl_Disable)) + +/* ETHERNET Transmit Flow Control --------------------------------------------*/ +#define ETH_TransmitFlowControl_Enable ((u32)0x00000002) +#define ETH_TransmitFlowControl_Disable ((u32)0x00000000) + +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ + ((CMD) == ETH_TransmitFlowControl_Disable)) + +/* ETHERNET VLAN Tag Comparison ----------------------------------------------*/ +#define ETH_VLANTagComparison_12Bit ((u32)0x00010000) +#define ETH_VLANTagComparison_16Bit ((u32)0x00000000) + +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ + ((COMPARISON) == ETH_VLANTagComparison_16Bit)) + +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) + +/* ETHERNET MAC Flags ---------------------------------------------------*/ +#define ETH_MAC_FLAG_TST ((u32)0x00000200) /* Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) /* MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) /* MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((u32)0x00000010) /* MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((u32)0x00000008) /* PMT flag (on MAC) */ + +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) + +/* ETHERNET MAC Interrupts ---------------------------------------------------*/ +#define ETH_MAC_IT_TST ((u32)0x00000200) /* Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((u32)0x00000040) /* MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((u32)0x00000020) /* MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((u32)0x00000010) /* MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((u32)0x00000008) /* PMT interrupt (on MAC) */ + +#define IS_ETH_MAC_IT(IT) ((((IT) & (u32)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) + +/* ETHERNET MAC addresses ----------------------------------------------------*/ +#define ETH_MAC_Address0 ((u32)0x00000000) +#define ETH_MAC_Address1 ((u32)0x00000008) +#define ETH_MAC_Address2 ((u32)0x00000010) +#define ETH_MAC_Address3 ((u32)0x00000018) + +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ + ((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) + +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) + +/* ETHERNET MAC addresses filter: SA/DA filed of received frames ------------*/ +#define ETH_MAC_AddressFilter_SA ((u32)0x00000000) +#define ETH_MAC_AddressFilter_DA ((u32)0x00000008) + +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ + ((FILTER) == ETH_MAC_AddressFilter_DA)) + +/* ETHERNET MAC addresses filter: Mask bytes ---------------------------------*/ +#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */ + +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ + ((MASK) == ETH_MAC_AddressMask_Byte5) || \ + ((MASK) == ETH_MAC_AddressMask_Byte4) || \ + ((MASK) == ETH_MAC_AddressMask_Byte3) || \ + ((MASK) == ETH_MAC_AddressMask_Byte2) || \ + ((MASK) == ETH_MAC_AddressMask_Byte1)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet DMA Desciptors defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET DMA Tx descriptor flags --------------------------------------------------------*/ +#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ + ((FLAG) == ETH_DMATxDesc_IC) || \ + ((FLAG) == ETH_DMATxDesc_LS) || \ + ((FLAG) == ETH_DMATxDesc_FS) || \ + ((FLAG) == ETH_DMATxDesc_DC) || \ + ((FLAG) == ETH_DMATxDesc_DP) || \ + ((FLAG) == ETH_DMATxDesc_TTSE) || \ + ((FLAG) == ETH_DMATxDesc_TER) || \ + ((FLAG) == ETH_DMATxDesc_TCH) || \ + ((FLAG) == ETH_DMATxDesc_TTSS) || \ + ((FLAG) == ETH_DMATxDesc_IHE) || \ + ((FLAG) == ETH_DMATxDesc_ES) || \ + ((FLAG) == ETH_DMATxDesc_JT) || \ + ((FLAG) == ETH_DMATxDesc_FF) || \ + ((FLAG) == ETH_DMATxDesc_PCE) || \ + ((FLAG) == ETH_DMATxDesc_LCA) || \ + ((FLAG) == ETH_DMATxDesc_NC) || \ + ((FLAG) == ETH_DMATxDesc_LCO) || \ + ((FLAG) == ETH_DMATxDesc_EC) || \ + ((FLAG) == ETH_DMATxDesc_VF) || \ + ((FLAG) == ETH_DMATxDesc_CC) || \ + ((FLAG) == ETH_DMATxDesc_ED) || \ + ((FLAG) == ETH_DMATxDesc_UF) || \ + ((FLAG) == ETH_DMATxDesc_DB)) + +/* ETHERNET DMA Tx descriptor segment ----------------------------------------*/ +#define ETH_DMATxDesc_LastSegment ((u32)0x40000000) /* Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((u32)0x20000000) /* First Segment */ + +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ + ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) + +/* ETHERNET DMA Tx descriptor Checksum Insertion Control --------------------*/ +#define ETH_DMATxDesc_ChecksumByPass ((u32)0x00000000) /* Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((u32)0x00400000) /* IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((u32)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((u32)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) + +/* ETHERNET DMA Tx Desciptor buffer size */ +#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) + +/* ETHERNET DMA Rx descriptor flags --------------------------------------------------------*/ +#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ + ((FLAG) == ETH_DMARxDesc_AFM) || \ + ((FLAG) == ETH_DMARxDesc_ES) || \ + ((FLAG) == ETH_DMARxDesc_DE) || \ + ((FLAG) == ETH_DMARxDesc_SAF) || \ + ((FLAG) == ETH_DMARxDesc_LE) || \ + ((FLAG) == ETH_DMARxDesc_OE) || \ + ((FLAG) == ETH_DMARxDesc_VLAN) || \ + ((FLAG) == ETH_DMARxDesc_FS) || \ + ((FLAG) == ETH_DMARxDesc_LS) || \ + ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ + ((FLAG) == ETH_DMARxDesc_RxLongFrame) || \ + ((FLAG) == ETH_DMARxDesc_LC) || \ + ((FLAG) == ETH_DMARxDesc_FT) || \ + ((FLAG) == ETH_DMARxDesc_RWT) || \ + ((FLAG) == ETH_DMARxDesc_RE) || \ + ((FLAG) == ETH_DMARxDesc_DBE) || \ + ((FLAG) == ETH_DMARxDesc_CE) || \ + ((FLAG) == ETH_DMARxDesc_MAMPCE)) + +/* ETHERNET DMA Rx descriptor buffers ---------------------------------------*/ +#define ETH_DMARxDesc_Buffer1 ((u32)0x00000000) /* DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((u32)0x00000001) /* DMA Rx Desc Buffer2 */ + +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ + ((BUFFER) == ETH_DMARxDesc_Buffer2)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet DMA defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET Drop TCP/IP Checksum Error Frame ---------------------------------*/ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000) + +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ + ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) + +/* ETHERNET Receive Store Forward --------------------------------------------*/ +#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000) + +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ + ((CMD) == ETH_ReceiveStoreForward_Disable)) + +/* ETHERNET Flush Received Frame ---------------------------------------------*/ +#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000) + +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ + ((CMD) == ETH_FlushReceivedFrame_Disable)) + +/* ETHERNET Transmit Store Forward -------------------------------------------*/ +#define ETH_TransmitStoreForward_Enable ((u32)0x00200000) +#define ETH_TransmitStoreForward_Disable ((u32)0x00000000) + +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ + ((CMD) == ETH_TransmitStoreForward_Disable)) + +/* ETHERNET Transmit Threshold Control ---------------------------------------*/ +#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ + +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) + +/* ETHERNET Forward Error Frames ---------------------------------------------*/ +#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000) + +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ + ((CMD) == ETH_ForwardErrorFrames_Disable)) + +/* ETHERNET Forward Undersized Good Frames -----------------------------------*/ +#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000) + +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ + ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) + +/* ETHERNET Receive Threshold Control ----------------------------------------*/ +#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ + +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) + +/* ETHERNET Second Frame Operate ---------------------------------------------*/ +#define ETH_SecondFrameOperate_Enable ((u32)0x00000004) +#define ETH_SecondFrameOperate_Disable ((u32)0x00000000) + +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ + ((CMD) == ETH_SecondFrameOperate_Disable)) + +/* ETHERNET Address Aligned Beats --------------------------------------------*/ +#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000) + +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ + ((CMD) == ETH_AddressAlignedBeats_Disable)) + +/* ETHERNET Fixed Burst ------------------------------------------------------*/ +#define ETH_FixedBurst_Enable ((u32)0x00010000) +#define ETH_FixedBurst_Disable ((u32)0x00000000) + +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ + ((CMD) == ETH_FixedBurst_Disable)) + +/* ETHERNET Rx DMA Burst Length ----------------------------------------------*/ +#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + +#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ + +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) + +/* ETHERNET Tx DMA Burst Length ----------------------------------------------*/ +#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + +#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) + +/* ETHERNET DMA Desciptor SkipLength */ +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) + +/* ETHERNET DMA Arbitration --------------------------------------------------*/ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002) + +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ + ((RATIO) == ETH_DMAArbitration_RxPriorTx)) + +/* ETHERNET DMA Flags ---------------------------------------------------*/ +#define ETH_DMA_FLAG_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */ + +#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((u32)0x00010000) /* Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((u32)0x00008000) /* Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((u32)0x00004000) /* Early receive flag */ +#define ETH_DMA_FLAG_FBE ((u32)0x00002000) /* Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((u32)0x00000400) /* Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((u32)0x00000200) /* Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((u32)0x00000100) /* Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((u32)0x00000080) /* Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((u32)0x00000040) /* Receive flag */ +#define ETH_DMA_FLAG_TU ((u32)0x00000020) /* Underflow flag */ +#define ETH_DMA_FLAG_RO ((u32)0x00000010) /* Overflow flag */ +#define ETH_DMA_FLAG_TJT ((u32)0x00000008) /* Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((u32)0x00000004) /* Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((u32)0x00000002) /* Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((u32)0x00000001) /* Transmit flag */ + +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (u32)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ + ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) + +/* ETHERNET DMA Interrupts ---------------------------------------------------*/ +#define ETH_DMA_IT_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */ + +#define ETH_DMA_IT_NIS ((u32)0x00010000) /* Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((u32)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((u32)0x00004000) /* Early receive interrupt */ +#define ETH_DMA_IT_FBE ((u32)0x00002000) /* Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((u32)0x00000400) /* Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((u32)0x00000200) /* Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((u32)0x00000100) /* Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((u32)0x00000080) /* Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((u32)0x00000040) /* Receive interrupt */ +#define ETH_DMA_IT_TU ((u32)0x00000020) /* Underflow interrupt */ +#define ETH_DMA_IT_RO ((u32)0x00000010) /* Overflow interrupt */ +#define ETH_DMA_IT_TJT ((u32)0x00000008) /* Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((u32)0x00000004) /* Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((u32)0x00000002) /* Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((u32)0x00000001) /* Transmit interrupt */ + +#define IS_ETH_DMA_IT(IT) ((((IT) & (u32)0xFFFE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) + +/* ETHERNET DMA transmit process state --------------------------------------------------------*/ +#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) /* Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) /* Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */ + +/* ETHERNET DMA receive process state --------------------------------------------------------*/ +#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) /* Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) /* Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */ + +/* ETHERNET DMA overflow --------------------------------------------------------*/ +#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) /* Overflow bit for missed frame counter */ + +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ + ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet PMT defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET PMT Flags --------------------------------------------------------*/ +#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) /* Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((u32)0x00000020) /* Magic Packet Received */ + +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet MMC defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET MMC Tx Interrupts */ +#define ETH_MMC_IT_TGF ((u32)0x00200000) /* When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((u32)0x00004000) /* When Tx good single col counter reaches half the maximum value */ + +/* ETHERNET MMC Rx Interrupts */ +#define ETH_MMC_IT_RGUF ((u32)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((u32)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((u32)0x10000020) /* When Rx crc error counter reaches half the maximum value */ + +#define IS_ETH_MMC_IT(IT) (((((IT) & (u32)0xFFDF3FFF) == 0x00) || (((IT) & (u32)0xEFFDFF9F) == 0x00)) && \ + ((IT) != 0x00)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) + +/* ETHERNET MMC Registers */ +#define ETH_MMCCR ((u32)0x00000100) /* MMC CR register */ +#define ETH_MMCRIR ((u32)0x00000104) /* MMC RIR register */ +#define ETH_MMCTIR ((u32)0x00000108) /* MMC TIR register */ +#define ETH_MMCRIMR ((u32)0x0000010C) /* MMC RIMR register */ +#define ETH_MMCTIMR ((u32)0x00000110) /* MMC TIMR register */ +#define ETH_MMCTGFSCCR ((u32)0x0000014C) /* MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((u32)0x00000150) /* MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((u32)0x00000168) /* MMC TGFCR register */ +#define ETH_MMCRFCECR ((u32)0x00000194) /* MMC RFCECR register */ +#define ETH_MMCRFAECR ((u32)0x00000198) /* MMC RFAECR register */ +#define ETH_MMCRGUFCR ((u32)0x000001C4) /* MMC RGUFCR register */ + +/* ETHERNET MMC registers */ +#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ + ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ + ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ + ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ + ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ + ((REG) == ETH_MMCRGUFCR)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet PTP defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET PTP time update method -------------------------------------------*/ +#define ETH_PTP_FineUpdate ((u32)0x00000001) /* Fine Update method */ +#define ETH_PTP_CoarseUpdate ((u32)0x00000000) /* Coarse Update method */ + +#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ + ((UPDATE) == ETH_PTP_CoarseUpdate)) + +/* ETHERNET PTP Flags --------------------------------------------------------*/ +#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) /* Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) /* Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) /* Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) /* Time Stamp Initialize */ + +#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ + ((FLAG) == ETH_PTP_FLAG_TSITE) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTI)) + +/* ETHERNET PTP subsecond increment */ +#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) + +/* ETHERNET PTP time sign ----------------------------------------------------*/ +#define ETH_PTP_PositiveTime ((u32)0x00000000) /* Positive time value */ +#define ETH_PTP_NegativeTime ((u32)0x80000000) /* Negative time value */ + +#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ + ((SIGN) == ETH_PTP_NegativeTime)) + +/* ETHERNET PTP time stamp low update */ +#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) + +/* ETHERNET PTP registers */ +#define ETH_PTPTSCR ((u32)0x00000700) /* PTP TSCR register */ +#define ETH_PTPSSIR ((u32)0x00000704) /* PTP SSIR register */ +#define ETH_PTPTSHR ((u32)0x00000708) /* PTP TSHR register */ +#define ETH_PTPTSLR ((u32)0x0000070C) /* PTP TSLR register */ +#define ETH_PTPTSHUR ((u32)0x00000710) /* PTP TSHUR register */ +#define ETH_PTPTSLUR ((u32)0x00000714) /* PTP TSLUR register */ +#define ETH_PTPTSAR ((u32)0x00000718) /* PTP TSAR register */ +#define ETH_PTPTTHR ((u32)0x0000071C) /* PTP TTHR register */ +#define ETH_PTPTTLR ((u32)0x00000720) /* PTP TTLR register */ + +#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ + ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ + ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ + ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ + ((REG) == ETH_PTPTTLR)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void ETH_DeInit(void); +u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +void ETH_Start(void); +u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength); +u32 ETH_HandleRxPkt(u32 addr); + + +u32 ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); + +/*--------------------------------- PHY ------------------------------------*/ +u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg); +u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue); +u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState); +/*--------------------------------- MAC ------------------------------------*/ +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT); +void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr); +void ETH_GetMACAddress(u32 MacAddr, u8 *Addr); +void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter); +void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte); +/*----------------------- DMA Tx/Rx descriptors ----------------------------*/ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, u32 TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag); +u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer); +/*--------------------------------- DMA ------------------------------------*/ +FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG); +void ETH_DMAClearFlag(u32 ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT); +void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT); +u32 ETH_GetTransmitProcessState(void); +u32 ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow); +u32 ETH_GetRxOverflowMissedFrameCounter(void); +u32 ETH_GetBufferUnavailableMissedFrameCounter(void); +u32 ETH_GetCurrentTxDescStartAddress(void); +u32 ETH_GetCurrentRxDescStartAddress(void); +u32 ETH_GetCurrentTxBufferAddress(void); +u32 ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); +/*--------------------------------- PMT ------------------------------------*/ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); +/*--------------------------------- MMC ------------------------------------*/ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT); +u32 ETH_GetMMCRegister(u32 ETH_MMCReg); +/*--------------------------------- PTP ------------------------------------*/ +u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab); +u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(u32 UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue); +void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue); +void ETH_SetPTPTimeStampAddend(u32 Value); +void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue); +u32 ETH_GetPTPRegister(u32 ETH_PTPReg); + +#endif /* __STM32FXXX_ETH_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h new file mode 100644 index 0000000..93f7fb3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h @@ -0,0 +1,58 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f_eth_conf.h +* Author : MCD Application Team +* Version : VX.Y.Z +* Date : mm/dd/2008 +* Description : ETHERNET firmware library configuration file. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F_ETH_CONF_H +#define __STM32F_ETH_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to compile the ETHERNET firmware library in DEBUG mode, + this will expanse the "assert_param" macro in the firmware library code (see + "Exported macro" section below) */ +/*#define ETH_DEBUG 1*/ + +/* Comment the line below to disable the specific peripheral inclusion */ +/************************************* ETHERNET *******************************/ +#define _ETH_MAC +//#define _ETH_PTP +//#define _ETH_MMC +#define _ETH_DMA + +/* Exported macro ------------------------------------------------------------*/ +#ifdef ETH_DEBUG +/******************************************************************************* +* Macro Name : eth_assert_param +* Description : The eth_assert_param macro is used for ethernet function's parameters +* check. +* It is used only if the ethernet library is compiled in DEBUG mode. +* Input : - expr: If expr is false, it calls assert_failed function +* which reports the name of the source file and the source +* line number of the call that failed. +* If expr is true, it returns no value. +* Return : None +*******************************************************************************/ + #define eth_assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(u8* file, u32 line); +#else + #define eth_assert_param(expr) ((void)0) +#endif /* ETH_DEBUG */ + +#endif /* __STM32F_ETH_CONF_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h new file mode 100644 index 0000000..a501d70 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h @@ -0,0 +1,39 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32fxxx_eth_lib.h +* Author : MCD Application Team +* Version : V2.0.2 +* Date : 07/11/2008 +* Description : This file includes the peripherals header files in the +* user application. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32FXXX_ETH_LIB_H +#define __STM32FXXX_ETH_LIB_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32fxxx_eth_map.h" + +#ifdef _ETH_MAC +//RP_Modif + #include "ipport.h" + #include "netbuf.h" + #include "stm32fxxx_eth.h" +#endif /*_ETH_MAC */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void eth_debug(void); + +#endif /* __STM32FXXX_ETH_LIB_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h new file mode 100644 index 0000000..cae9ce0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h @@ -0,0 +1,593 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32fxxx_eth_map.h +* Author : MCD Application Team +* Version : VX.Y.Z +* Date : mm/dd/2008 +* Description : This file contains all ETHERNET peripheral register's +* definitions and memory mapping. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32FXXX_ETH_MAP_H +#define __STM32FXXX_ETH_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ + +#include "stm32fxxx_eth_conf.h" +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* Ethernet Peripheral registers structures */ +/******************************************************************************/ + +typedef struct +{ + vu32 MACCR; + vu32 MACFFR; + vu32 MACHTHR; + vu32 MACHTLR; + vu32 MACMIIAR; + vu32 MACMIIDR; + vu32 MACFCR; + vu32 MACVLANTR; + vu32 RESERVED0[2]; + vu32 MACRWUFFR; + vu32 MACPMTCSR; + vu32 RESERVED1[2]; + vu32 MACSR; + vu32 MACIMR; + vu32 MACA0HR; + vu32 MACA0LR; + vu32 MACA1HR; + vu32 MACA1LR; + vu32 MACA2HR; + vu32 MACA2LR; + vu32 MACA3HR; + vu32 MACA3LR; +} ETH_MAC_TypeDef; + +typedef struct +{ + vu32 MMCCR; + vu32 MMCRIR; + vu32 MMCTIR; + vu32 MMCRIMR; + vu32 MMCTIMR; + vu32 RESERVED0[14]; + vu32 MMCTGFSCCR; + vu32 MMCTGFMSCCR; + vu32 RESERVED1[5]; + vu32 MMCTGFCR; + vu32 RESERVED2[10]; + vu32 MMCRFCECR; + vu32 MMCRFAER; + vu32 RESERVED3[10]; + vu32 MMCRGUFCR; +} ETH_MMC_TypeDef; + +typedef struct +{ + vu32 PTPTSCR; + vu32 PTPSSIR; + vu32 PTPTSHR; + vu32 PTPTSLR; + vu32 PTPTSHUR; + vu32 PTPTSLUR; + vu32 PTPTSAR; + vu32 PTPTTHR; + vu32 PTPTTLR; +} ETH_PTP_TypeDef; + +typedef struct +{ + vu32 DMABMR; + vu32 DMATPDR; + vu32 DMARPDR; + vu32 DMARDLAR; + vu32 DMATDLAR; + vu32 DMASR; + vu32 DMAOMR; + vu32 DMAIER; + vu32 DMAMFBOCR; + vu32 RESERVED0[9]; + vu32 DMACHTDR; + vu32 DMACHRDR; + vu32 DMACHTBAR; + vu32 DMACHRBAR; +} ETH_DMA_TypeDef; + +/******************************************************************************/ +/* Ethernet MAC Registers bits definitions */ +/******************************************************************************/ +//#define IPNAME_REGNAME_BITNAME /* BIT MASK */ + +/* Bit definition for Ethernet MAC Control Register register */ +#define ETH_MACCR_WD ((u32)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((u32)0x00400000) /* Jabber disable */ +#define ETH_MACCR_JFE ((u32)0x00100000) /* Jumbo frame enable */ +#define ETH_MACCR_IFG ((u32)0x000E0000) /* Inter-frame gap */ + #define ETH_MACCR_IFG_96Bit ((u32)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((u32)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((u32)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((u32)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((u32)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((u32)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((u32)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((u32)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((u32)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((u32)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((u32)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((u32)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((u32)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((u32)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((u32)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((u32)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((u32)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling + a transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((u32)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((u32)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((u32)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((u32)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((u32)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((u32)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((u32)0x00000004) /* Receiver enable */ + +/* Bit definition for Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA ((u32)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((u32)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((u32)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((u32)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((u32)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((u32)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((u32)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((u32)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((u32)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((u32)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((u32)0x00000001) /* Promiscuous mode */ + +/* Bit definition for Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH ((u32)0xFFFFFFFF) /* Hash table high */ + +/* Bit definition for Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL ((u32)0xFFFFFFFF) /* Hash table low */ + +/* Bit definition for Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA ((u32)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((u32)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((u32)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((u32)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((u32)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((u32)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((u32)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((u32)0x00000001) /* MII busy */ + +/* Bit definition for Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_MD ((u32)0x0000FFFF) /* MII data: read/write data from/to PHY */ + +/* Bit definition for Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT ((u32)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((u32)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((u32)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((u32)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((u32)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((u32)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((u32)0x00000001) /* Flow control busy/backpressure activate */ + +/* Bit definition for Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTC ((u32)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((u32)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D ((u32)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. + Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ +/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask + Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask + Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask + Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask + Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command + Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset + Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 + Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +/* Bit definition for Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((u32)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((u32)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((u32)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((u32)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((u32)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((u32)0x00000001) /* Power Down */ + +/* Bit definition for Ethernet MAC Status Register */ +#define ETH_MACSR_TSTS ((u32)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((u32)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((u32)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((u32)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((u32)0x00000008) /* PMT status */ + +/* Bit definition for Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_TSTIM ((u32)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((u32)0x00000008) /* PMT interrupt mask */ + +/* Bit definition for Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) /* MAC address0 high */ + +/* Bit definition for Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) /* MAC address0 low */ + +/* Bit definition for Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE ((u32)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((u32)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((u32)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((u32)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L ((u32)0xFFFFFFFF) /* MAC address1 low */ + +/* Bit definition for Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE ((u32)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((u32)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((u32)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((u32)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L ((u32)0xFFFFFFFF) /* MAC address2 low */ + +/* Bit definition for Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE ((u32)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((u32)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((u32)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((u32)0x0000FFFF) /* MAC address3 high */ + +/* Bit definition for Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L ((u32)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* Ethernet MMC Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCF ((u32)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((u32)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((u32)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((u32)0x00000001) /* Counters Reset */ + +/* Bit definition for Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RGUFS ((u32)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((u32)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((u32)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS ((u32)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((u32)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((u32)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RGUFM ((u32)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((u32)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((u32)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM ((u32)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((u32)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((u32)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ +#define ETH_MMCTGFSCCR_TGFSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ +#define ETH_MMCTGFCR_TGFC ((u32)0xFFFFFFFF) /* Number of good frames transmitted. */ + +/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ +#define ETH_MMCRFCECR_RFCEC ((u32)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +#define ETH_MMCRFAECR_RFAEC ((u32)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ +#define ETH_MMCRGUFCR_RGUFC ((u32)0xFFFFFFFF) /* Number of good unicast frames received. */ + +/******************************************************************************/ +/* Ethernet PTP Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +#define ETH_PTPTSCR_TSARU ((u32)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((u32)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((u32)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((u32)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((u32)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((u32)0x00000001) /* Time stamp enable */ + +/* Bit definition for Ethernet PTP Sub-Second Increment Register */ +#define ETH_PTPSSIR_STSSI ((u32)0x000000FF) /* System time Sub-second increment value */ + +/* Bit definition for Ethernet PTP Time Stamp High Register */ +#define ETH_PTPTSHR_STS ((u32)0xFFFFFFFF) /* System Time second */ + +/* Bit definition for Ethernet PTP Time Stamp Low Register */ +#define ETH_PTPTSLR_STPNS ((u32)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((u32)0x7FFFFFFF) /* System Time sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp High Update Register */ +#define ETH_PTPTSHUR_TSUS ((u32)0xFFFFFFFF) /* Time stamp update seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ +#define ETH_PTPTSLUR_TSUPNS ((u32)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((u32)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Addend Register */ +#define ETH_PTPTSAR_TSA ((u32)0xFFFFFFFF) /* Time stamp addend */ + +/* Bit definition for Ethernet PTP Target Time High Register */ +#define ETH_PTPTTHR_TTSH ((u32)0xFFFFFFFF) /* Target time stamp high */ + +/* Bit definition for Ethernet PTP Target Time Low Register */ +#define ETH_PTPTTLR_TTSL ((u32)0xFFFFFFFF) /* Target time stamp low */ + +/******************************************************************************/ +/* Ethernet DMA Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_AAB ((u32)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((u32)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((u32)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((u32)0x007E0000) /* RxDMA PBL */ + /* Values to be confirmed: maybe they are inversed */ + #define ETH_DMABMR_RDP_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((u32)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((u32)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((u32)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((u32)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((u32)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((u32)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((u32)0x00003F00) /* Programmable burst length */ + /* Values to be confirmed: maybe they are inversed */ + #define ETH_DMABMR_PBL_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_DSL ((u32)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((u32)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((u32)0x00000001) /* Software reset */ + +/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD ((u32)0xFFFFFFFF) /* Transmit poll demand */ + +/* Bit definition for Ethernet DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD ((u32)0xFFFFFFFF) /* Receive poll demand */ + +/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL ((u32)0xFFFFFFFF) /* Start of receive list */ + +/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL ((u32)0xFFFFFFFF) /* Start of transmit list */ + +/* Bit definition for Ethernet DMA Status Register */ +#define ETH_DMASR_TSTS ((u32)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((u32)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((u32)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((u32)0x03800000) /* Error bits status */ + /* combination with EBS[2:0] for GetFlagStatus function */ + #define ETH_DMASR_EBS_DescAccess ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((u32)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((u32)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((u32)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((u32)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((u32)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((u32)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((u32)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((u32)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((u32)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((u32)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((u32)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((u32)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((u32)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((u32)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((u32)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((u32)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((u32)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((u32)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((u32)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((u32)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((u32)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((u32)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((u32)0x00000001) /* Transmit status */ + +/* Bit definition for Ethernet DMA Operation Mode Register */ +#define ETH_DMAOMR_DTCEFD ((u32)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((u32)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((u32)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((u32)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((u32)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((u32)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((u32)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((u32)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((u32)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((u32)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((u32)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((u32)0x00000002) /* Start/stop receive */ + +/* Bit definition for Ethernet DMA Interrupt Enable Register */ +#define ETH_DMAIER_NISE ((u32)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((u32)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((u32)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((u32)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((u32)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((u32)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((u32)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((u32)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((u32)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((u32)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((u32)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((u32)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((u32)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((u32)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((u32)0x00000001) /* Transmit interrupt enable */ + +/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((u32)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((u32)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((u32)0x0000FFFF) /* Number of frames missed by the controller */ + +/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP ((u32)0xFFFFFFFF) /* Host transmit descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP ((u32)0xFFFFFFFF) /* Host receive descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP ((u32)0xFFFFFFFF) /* Host transmit buffer address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP ((u32)0xFFFFFFFF) /* Host receive buffer address pointer */ + +/******************************************************************************/ +/* Macros */ +/******************************************************************************/ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* ETHERNET registers base address */ +#define ETH_BASE ((u32)0x40028000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/*------------------------ Non Debug Mode ------------------------------------*/ +#ifndef ETH_DEBUG +#ifdef _ETH_MAC + #define ETH_MAC ((ETH_MAC_TypeDef *) ETH_MAC_BASE) +#endif /*_ETH_MAC */ + +#ifdef _ETH_MMC + #define ETH_MMC ((ETH_MMC_TypeDef *) ETH_MMC_BASE) +#endif /*_ETH_MMC */ + +#ifdef _ETH_PTP + #define ETH_PTP ((ETH_PTP_TypeDef *) ETH_PTP_BASE) +#endif /*_ETH_PTP */ + +#ifdef _ETH_DMA + #define ETH_DMA ((ETH_DMA_TypeDef *) ETH_DMA_BASE) +#endif /*_ETH_DMA */ + +/*------------------------ Debug Mode ----------------------------------------*/ +#else /* ETH_DEBUG */ +#ifdef _ETH_MAC + EXT ETH_MAC_TypeDef *ETH_MAC; +#endif /*_ETH_MAC */ + +#ifdef _ETH_MMC + EXT ETH_MMC_TypeDef *ETH_MMC; +#endif /*_ETH_MMC */ + +#ifdef _ETH_PTP + EXT ETH_PTP_TypeDef *ETH_PTP; +#endif /*_ETH_PTP */ + +#ifdef _ETH_DMA + EXT ETH_DMA_TypeDef *ETH_DMA; +#endif /*_ETH_DMA */ + +#endif /* ETH_DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32FXXX_ETH_MAP_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_iar.s b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_iar.s new file mode 100644 index 0000000..cb20961 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_iar.s @@ -0,0 +1,278 @@ +;******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +;* File Name : cortexm3_macro.s +;* Author : MCD Application Team +;* Date First Issued : 02/19/2007 +;* Description : Instruction wrappers for special Cortex-M3 instructions. +;******************************************************************************* +; History: +; 04/02/2007: V0.2 +; 02/19/2007: V0.1 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + + SECTION .text:CODE(2) + + ; Exported functions + EXPORT __WFI + EXPORT __WFE + EXPORT __SEV + EXPORT __ISB + EXPORT __DSB + EXPORT __DMB + EXPORT __SVC + EXPORT __MRS_CONTROL + EXPORT __MSR_CONTROL + EXPORT __MRS_PSP + EXPORT __MSR_PSP + EXPORT __MRS_MSP + EXPORT __MSR_MSP + EXPORT __SETPRIMASK + EXPORT __RESETPRIMASK + EXPORT __SETFAULTMASK + EXPORT __RESETFAULTMASK + EXPORT __BASEPRICONFIG + EXPORT __GetBASEPRI + EXPORT __REV_HalfWord + EXPORT __REV_Word + +;******************************************************************************* +; Function Name : __WFI +; Description : Assembler function for the WFI instruction. +; Input : None +; Return : None +;******************************************************************************* +__WFI + + WFI + BX r14 + +;******************************************************************************* +; Function Name : __WFE +; Description : Assembler function for the WFE instruction. +; Input : None +; Return : None +;******************************************************************************* +__WFE + + WFE + BX r14 + +;******************************************************************************* +; Function Name : __SEV +; Description : Assembler function for the SEV instruction. +; Input : None +; Return : None +;******************************************************************************* +__SEV + + SEV + BX r14 + +;******************************************************************************* +; Function Name : __ISB +; Description : Assembler function for the ISB instruction. +; Input : None +; Return : None +;******************************************************************************* +__ISB + + ISB + BX r14 + +;******************************************************************************* +; Function Name : __DSB +; Description : Assembler function for the DSB instruction. +; Input : None +; Return : None +;******************************************************************************* +__DSB + + DSB + BX r14 + +;******************************************************************************* +; Function Name : __DMB +; Description : Assembler function for the DMB instruction. +; Input : None +; Return : None +;******************************************************************************* +__DMB + + DMB + BX r14 + +;******************************************************************************* +; Function Name : __SVC +; Description : Assembler function for the SVC instruction. +; Input : None +; Return : None +;******************************************************************************* +__SVC + + SVC 0x01 + BX r14 + +;******************************************************************************* +; Function Name : __MRS_CONTROL +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Cortex-M3 CONTROL register value. +;******************************************************************************* +__MRS_CONTROL + + MRS r0, CONTROL + BX r14 + +;******************************************************************************* +; Function Name : __MSR_CONTROL +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Cortex-M3 CONTROL register new value. +; Return : None +;******************************************************************************* +__MSR_CONTROL + + MSR CONTROL, r0 + ISB + BX r14 + +;******************************************************************************* +; Function Name : __MRS_PSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Process Stack value. +;******************************************************************************* +__MRS_PSP + + MRS r0, PSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_PSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Process Stack new value. +; Return : None +;******************************************************************************* +__MSR_PSP + + MSR PSP, r0 ; set Process Stack value + BX r14 + +;******************************************************************************* +; Function Name : __MRS_MSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Main Stack value. +;******************************************************************************* +__MRS_MSP + + MRS r0, MSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_MSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Main Stack new value. +; Return : None +;******************************************************************************* +__MSR_MSP + + MSR MSP, r0 ; set Main Stack value + BX r14 + +;******************************************************************************* +; Function Name : __SETPRIMASK +; Description : Assembler function to set the PRIMASK. +; Input : None +; Return : None +;******************************************************************************* +__SETPRIMASK + + CPSID i + BX r14 + +;******************************************************************************* +; Function Name : __RESETPRIMASK +; Description : Assembler function to reset the PRIMASK. +; Input : None +; Return : None +;******************************************************************************* +__RESETPRIMASK + + CPSIE i + BX r14 + +;******************************************************************************* +; Function Name : __SETFAULTMASK +; Description : Assembler function to set the FAULTMASK. +; Input : None +; Return : None +;******************************************************************************* +__SETFAULTMASK + + CPSID f + BX r14 + +;******************************************************************************* +; Function Name : __RESETFAULTMASK +; Description : Assembler function to reset the FAULTMASK. +; Input : None +; Return : None +;******************************************************************************* +__RESETFAULTMASK + + CPSIE f + BX r14 + +;******************************************************************************* +; Function Name : __BASEPRICONFIG +; Description : Assembler function to set the Base Priority. +; Input : - r0 : Base Priority new value +; Return : None +;******************************************************************************* +__BASEPRICONFIG + + MSR BASEPRI, r0 + BX r14 + +;******************************************************************************* +; Function Name : __GetBASEPRI +; Description : Assembler function to get the Base Priority value. +; Input : None +; Return : - r0 : Base Priority value +;******************************************************************************* +__GetBASEPRI + + MRS r0, BASEPRI_MAX + BX r14 + +;******************************************************************************* +; Function Name : __REV_HalfWord +; Description : Reverses the byte order in HalfWord(16-bit) input variable. +; Input : - r0 : specifies the input variable +; Return : - r0 : holds tve variable value after byte reversing. +;******************************************************************************* +__REV_HalfWord + + REV16 r0, r0 + BX r14 + +;******************************************************************************* +; Function Name : __REV_Word +; Description : Reverses the byte order in Word(32-bit) input variable. +; Input : - r0 : specifies the input variable +; Return : - r0 : holds tve variable value after byte reversing. +;******************************************************************************* +__REV_Word + + REV r0, r0 + BX r14 + + END + +;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE***** diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_rvds.s b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_rvds.s new file mode 100644 index 0000000..4032f21 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_rvds.s @@ -0,0 +1,284 @@ +;******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +;* File Name : cortexm3_macro.s +;* Author : MCD Application Team +;* Date First Issued : 09/29/2006 +;* Description : Instruction wrappers for special Cortex-M3 instructions. +;******************************************************************************* +; History: +; 05/21/2007: V0.3 +; 04/02/2007: V0.2 +; 02/05/2007: V0.1 +; 09/29/2006: V0.01 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + + ; Exported functions + EXPORT __WFI + EXPORT __WFE + EXPORT __SEV + EXPORT __ISB + EXPORT __DSB + EXPORT __DMB + EXPORT __SVC + EXPORT __MRS_CONTROL + EXPORT __MSR_CONTROL + EXPORT __MRS_PSP + EXPORT __MSR_PSP + EXPORT __MRS_MSP + EXPORT __MSR_MSP + EXPORT __SETPRIMASK + EXPORT __RESETPRIMASK + EXPORT __SETFAULTMASK + EXPORT __RESETFAULTMASK + EXPORT __BASEPRICONFIG + EXPORT __GetBASEPRI + EXPORT __REV_HalfWord + EXPORT __REV_Word + +;******************************************************************************* +; Function Name : __WFI +; Description : Assembler function for the WFI instruction. +; Input : None +; Return : None +;******************************************************************************* +__WFI + + WFI + BX r14 + +;******************************************************************************* +; Function Name : __WFE +; Description : Assembler function for the WFE instruction. +; Input : None +; Return : None +;******************************************************************************* +__WFE + + WFE + BX r14 + +;******************************************************************************* +; Function Name : __SEV +; Description : Assembler function for the SEV instruction. +; Input : None +; Return : None +;******************************************************************************* +__SEV + + SEV + BX r14 + +;******************************************************************************* +; Function Name : __ISB +; Description : Assembler function for the ISB instruction. +; Input : None +; Return : None +;******************************************************************************* +__ISB + + ISB + BX r14 + +;******************************************************************************* +; Function Name : __DSB +; Description : Assembler function for the DSB instruction. +; Input : None +; Return : None +;******************************************************************************* +__DSB + + DSB + BX r14 + +;******************************************************************************* +; Function Name : __DMB +; Description : Assembler function for the DMB instruction. +; Input : None +; Return : None +;******************************************************************************* +__DMB + + DMB + BX r14 + +;******************************************************************************* +; Function Name : __SVC +; Description : Assembler function for the SVC instruction. +; Input : None +; Return : None +;******************************************************************************* +__SVC + + SVC 0x01 + BX r14 + +;******************************************************************************* +; Function Name : __MRS_CONTROL +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Cortex-M3 CONTROL register value. +;******************************************************************************* +__MRS_CONTROL + + MRS r0, CONTROL + BX r14 + +;******************************************************************************* +; Function Name : __MSR_CONTROL +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Cortex-M3 CONTROL register new value. +; Return : None +;******************************************************************************* +__MSR_CONTROL + + MSR CONTROL, r0 + ISB + BX r14 + +;******************************************************************************* +; Function Name : __MRS_PSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Process Stack value. +;******************************************************************************* +__MRS_PSP + + MRS r0, PSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_PSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Process Stack new value. +; Return : None +;******************************************************************************* +__MSR_PSP + + MSR PSP, r0 ; set Process Stack value + BX r14 + +;******************************************************************************* +; Function Name : __MRS_MSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Main Stack value. +;******************************************************************************* +__MRS_MSP + + MRS r0, MSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_MSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Main Stack new value. +; Return : None +;******************************************************************************* +__MSR_MSP + + MSR MSP, r0 ; set Main Stack value + BX r14 + +;******************************************************************************* +; Function Name : __SETPRIMASK +; Description : Assembler function to set the PRIMASK. +; Input : None +; Return : None +;******************************************************************************* +__SETPRIMASK + + CPSID i + BX r14 + +;******************************************************************************* +; Function Name : __RESETPRIMASK +; Description : Assembler function to reset the PRIMASK. +; Input : None +; Return : None +;******************************************************************************* +__RESETPRIMASK + + CPSIE i + BX r14 + +;******************************************************************************* +; Function Name : __SETFAULTMASK +; Description : Assembler function to set the FAULTMASK. +; Input : None +; Return : None +;******************************************************************************* +__SETFAULTMASK + + CPSID f + BX r14 + +;******************************************************************************* +; Function Name : __RESETFAULTMASK +; Description : Assembler function to reset the FAULTMASK. +; Input : None +; Return : None +;******************************************************************************* +__RESETFAULTMASK + + CPSIE f + BX r14 + +;******************************************************************************* +; Function Name : __BASEPRICONFIG +; Description : Assembler function to set the Base Priority. +; Input : - r0 : Base Priority new value +; Return : None +;******************************************************************************* +__BASEPRICONFIG + + MSR BASEPRI, r0 + BX r14 + +;******************************************************************************* +; Function Name : __GetBASEPRI +; Description : Assembler function to get the Base Priority value. +; Input : None +; Return : - r0 : Base Priority value +;******************************************************************************* +__GetBASEPRI + + MRS r0, BASEPRI_MAX + BX r14 + +;******************************************************************************* +; Function Name : __REV_HalfWord +; Description : Reverses the byte order in HalfWord(16-bit) input variable. +; Input : - r0 : specifies the input variable +; Return : - r0 : holds tve variable value after byte reversing. +;******************************************************************************* +__REV_HalfWord + + REV16 r0, r0 + BX r14 + +;******************************************************************************* +; Function Name : __REV_Word +; Description : Reverses the byte order in Word(32-bit) input variable. +; Input : - r0 : specifies the input variable +; Return : - r0 : holds tve variable value after byte reversing. +;******************************************************************************* +__REV_Word + + REV r0, r0 + BX r14 + + END + +;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE***** diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/lcd.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/lcd.c new file mode 100644 index 0000000..55a6e86 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/lcd.c @@ -0,0 +1,1305 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : lcd.c +* Author : MCD Application Team +* Date First Issued : mm/dd/yyyy +* Description : This file includes the LCD driver for AM-240320LTNQW00H +* liquid Crystal Display Module of STM32F10x-EVAL. +******************************************************************************** +* History: +* mm/dd/yyyy +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" +#include "lcd.h" +#include "spi_flash.h" + +#include "FreeRTOS.h" +#include "task.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + /* ASCII Table: each character is 16 column (16dots large) + and 24 raw (24 dots high) */ + const uc16 ASCII_Table[] = + { + /* Space ' ' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '!' */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '"' */ + 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '#' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60, + 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318, + 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000, + /* '$' */ + 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C, + 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C, + 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000, + /* '%' */ + 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611, + 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460, + 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000, + /* '&' */ + 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0, + 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06, + 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ''' */ + 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '(' */ + 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060, + 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000, + /* ')' */ + 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000, + /* '*' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '+' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ',' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, + /* '-' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '.' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '/' */ + 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, + 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0, + 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '0' */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C, + 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '1' */ + 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '2' */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '3' */ + 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600, + 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '4' */ + 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60, + 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00, + 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '5' */ + 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC, + 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '6' */ + 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC, + 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '7' */ + 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380, + 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '8' */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638, + 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38, + 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '9' */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C, + 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C, + 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ':' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ';' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000, + /* '<' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0, + 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '=' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '>' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0, + 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '?' */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00, + 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '@' */ + 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411, + 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004, + 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'A' */ + 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60, + 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C, + 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'B' */ + 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C, + 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C, + 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'C' */ + 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006, + 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C, + 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'D' */ + 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006, + 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06, + 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'E' */ + 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'F' */ + 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'G' */ + 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003, + 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C, + 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'H' */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'I' */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'J' */ + 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738, + 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'K' */ + 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6, + 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'L' */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'M' */ + 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836, + 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6, + 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'N' */ + 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC, + 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C, + 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'O' */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'P' */ + 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'Q' */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C, + 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'R' */ + 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806, + 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'S' */ + 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C, + 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C, + 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'T' */ + 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'U' */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'V' */ + 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C, + 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'W' */ + 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366, + 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C, + 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'X' */ + 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0, + 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C, + 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'Y' */ + 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660, + 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'Z' */ + 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600, + 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006, + 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '[' */ + 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000, + /* '\' */ + 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0, + 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ']' */ + 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000, + /* '^' */ + 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630, + 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '_' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ''' */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'a' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8, + 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C, + 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'b' */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'c' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0, + 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30, + 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'd' */ + 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'e' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30, + 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'f' */ + 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'g' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8, + 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18, + 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000, + /* 'h' */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'i' */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'j' */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000, + /* 'k' */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C, + 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C, + 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'l' */ + 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'm' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF, + 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, + 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'n' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'o' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30, + 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'p' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000, + /* 'q' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000, + /* 'r' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0, + 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 's' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0, + 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 't' */ + 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'u' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818, + 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38, + 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'v' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18, + 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'w' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1, + 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C, + 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'x' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38, + 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30, + 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'y' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830, + 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380, + 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000, + /* 'z' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '{' */ + 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000, + /* '|' */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, + /* '}' */ + 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000, + /* '~' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + }; +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + /* Global variables to set the written text color */ +static vu16 TextColor = 0x0000, BackColor = 0xFFFF; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +static u32 StrLength(u8 *Str); + +/******************************************************************************* +* Function Name : LCD_Init +* Description : Initializes LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Init(void) +{ +/* Configure the LCD Control pins --------------------------------------------*/ + LCD_CtrlLinesConfig(); + +/* Configure the SPI2 interface ----------------------------------------------*/ + LCD_SPIConfig(); + +/* Enable the LCD Oscillator -------------------------------------------------*/ + LCD_WriteReg(R1, 0x10); + LCD_WriteReg(R0, 0xA0); + LCD_WriteReg(R3, 0x01); + vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */ + LCD_WriteReg(R3, 0x00); + LCD_WriteReg(R43, 0x04); + + LCD_WriteReg(R40, 0x18); + LCD_WriteReg(R26, 0x05); + LCD_WriteReg(R37, 0x05); + LCD_WriteReg(R25, 0x00); + +/* LCD Power On --------------------------------------------------------------*/ + LCD_WriteReg(R28, 0x73); + LCD_WriteReg(R36, 0x74); + LCD_WriteReg(R30, 0x01); + LCD_WriteReg(R24, 0xC1); + vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */ + LCD_WriteReg(R24, 0xE1); + LCD_WriteReg(R24, 0xF1); + vTaskDelay( 60 / portTICK_PERIOD_MS ); /* Delay 60 ms */ + LCD_WriteReg(R24, 0xF5); + vTaskDelay( 60 / portTICK_PERIOD_MS ); /* Delay 60 ms */ + LCD_WriteReg(R27, 0x09); + vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */ + LCD_WriteReg(R31, 0x11); + LCD_WriteReg(R32, 0x0E); + LCD_WriteReg(R30, 0x81); + vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */ + +/* Chip Set ------------------------------------------------------------------*/ + LCD_WriteReg(R157, 0x00); + LCD_WriteReg(R192, 0x00); + + LCD_WriteReg(R14, 0x00); + LCD_WriteReg(R15, 0x00); + LCD_WriteReg(R16, 0x00); + LCD_WriteReg(R17, 0x00); + LCD_WriteReg(R18, 0x00); + LCD_WriteReg(R19, 0x00); + LCD_WriteReg(R20, 0x00); + LCD_WriteReg(R21, 0x00); + LCD_WriteReg(R22, 0x00); + LCD_WriteReg(R23, 0x00); + + LCD_WriteReg(R52, 0x01); + LCD_WriteReg(R53, 0x00); + + LCD_WriteReg(R75, 0x00); + LCD_WriteReg(R76, 0x00); + LCD_WriteReg(R78, 0x00); + LCD_WriteReg(R79, 0x00); + LCD_WriteReg(R80, 0x00); + + LCD_WriteReg(R60, 0x00); + LCD_WriteReg(R61, 0x00); + LCD_WriteReg(R62, 0x01); + LCD_WriteReg(R63, 0x3F); + LCD_WriteReg(R64, 0x02); + LCD_WriteReg(R65, 0x02); + LCD_WriteReg(R66, 0x00); + LCD_WriteReg(R67, 0x00); + LCD_WriteReg(R68, 0x00); + LCD_WriteReg(R69, 0x00); + LCD_WriteReg(R70, 0xEF); + LCD_WriteReg(R71, 0x00); + LCD_WriteReg(R72, 0x00); + LCD_WriteReg(R73, 0x01); + LCD_WriteReg(R74, 0x3F); + + LCD_WriteReg(R29, 0x08); /* R29:Gate scan direction setting */ + + LCD_WriteReg(R134, 0x00); + LCD_WriteReg(R135, 0x30); + LCD_WriteReg(R136, 0x02); + LCD_WriteReg(R137, 0x05); + + LCD_WriteReg(R141, 0x01); /* R141:Register set-up mode for one line clock */ + LCD_WriteReg(R139, 0x20); /* R139:One line SYSCLK number in one-line */ + LCD_WriteReg(R51, 0x01); /* R51:N line inversion setting */ + LCD_WriteReg(R55, 0x01); /* R55:Scanning method setting */ + LCD_WriteReg(R118, 0x00); + +/* Gamma Set -----------------------------------------------------------------*/ + LCD_WriteReg(R143, 0x10); + LCD_WriteReg(R144, 0x67); + LCD_WriteReg(R145, 0x07); + LCD_WriteReg(R146, 0x65); + LCD_WriteReg(R147, 0x07); + LCD_WriteReg(R148, 0x01); + LCD_WriteReg(R149, 0x76); + LCD_WriteReg(R150, 0x56); + LCD_WriteReg(R151, 0x00); + LCD_WriteReg(R152, 0x06); + LCD_WriteReg(R153, 0x03); + LCD_WriteReg(R154, 0x00); + +/* Display On ----------------------------------------------------------------*/ + LCD_WriteReg(R1, 0x50); + LCD_WriteReg(R5, 0x04); + + LCD_WriteReg(R0, 0x80); + LCD_WriteReg(R59, 0x01); + vTaskDelay( 40 / portTICK_PERIOD_MS ); /* Delay 40 ms */ + LCD_WriteReg(R0, 0x20); +} + +/******************************************************************************* +* Function Name : LCD_SetTextColor +* Description : Sets the Text color. +* Input : - Color: specifies the Text color code RGB(5-6-5). +* Output : - TextColor: Text color global variable used by LCD_DrawChar +* and LCD_DrawPicture functions. +* Return : None +*******************************************************************************/ +void LCD_SetTextColor(vu16 Color) +{ + TextColor = Color; +} + +/******************************************************************************* +* Function Name : LCD_SetBackColor +* Description : Sets the Background color. +* Input : - Color: specifies the Background color code RGB(5-6-5). +* Output : - BackColor: Background color global variable used by +* LCD_DrawChar and LCD_DrawPicture functions. +* Return : None +*******************************************************************************/ +void LCD_SetBackColor(vu16 Color) +{ + BackColor = Color; +} + +/******************************************************************************* +* Function Name : LCD_ClearLine +* Description : Clears the selected line. +* Input : - Line: the Line to be cleared. +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* Output : None +* Return : None +*******************************************************************************/ +void LCD_ClearLine(u8 Line) +{ + LCD_DisplayStringLine(Line, " "); +} + +/******************************************************************************* +* Function Name : LCD_Clear +* Description : Clears the hole LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Clear(void) +{ + u32 index = 0; + + LCD_SetCursor(0x00, 0x013F); + + for(index = 0; index < 0x12C00; index++) + { + LCD_WriteRAM(White); + } +} + +/******************************************************************************* +* Function Name : LCD_SetCursor +* Description : Sets the cursor position. +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetCursor(u8 Xpos, u16 Ypos) +{ + LCD_WriteReg(R66, Xpos); + LCD_WriteReg(R67, ((Ypos & 0x100)>> 8)); + LCD_WriteReg(R68, (Ypos & 0xFF)); +} + +/******************************************************************************* +* Function Name : LCD_DrawChar +* Description : Draws a character on LCD. +* Input : - Xpos: the Line where to display the character shape. +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* - Ypos: start column address. +* - c: pointer to the character data. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c) +{ + u32 index = 0, i = 0; + u8 Xaddress = 0; + + Xaddress = Xpos; + + LCD_SetCursor(Xaddress, Ypos); + + for(index = 0; index < 24; index++) + { + for(i = 0; i < 16; i++) + { + if((c[index] & (1 << i)) == 0x00) + { + LCD_WriteRAM(BackColor); + } + else + { + LCD_WriteRAM(TextColor); + } + } + Xaddress++; + LCD_SetCursor(Xaddress, Ypos); + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayChar +* Description : Displays one character (16dots width, 24dots height). +* Input : - Line: the Line where to display the character shape . +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* - Column: start column address. +* - Ascii: character ascii code, must be between 0x20 and 0x7E. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii) +{ + Ascii -= 32; + LCD_DrawChar(Line, Column, &ASCII_Table[Ascii * 24]); +} + +/******************************************************************************* +* Function Name : LCD_DisplayStringLine +* Description : Displays a maximum of 20 char on the LCD. +* Input : - Line: the Line where to display the character shape . +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* - *ptr: pointer to string to display on LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayStringLine(u8 Line, u8 *ptr) +{ + u32 i = 0; + u16 refcolumn = 319; + + /* Send the string character by character on lCD */ + while ((*ptr != 0) & (i < 20)) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, *ptr); + /* Decrement the column position by 16 */ + refcolumn -= 16; + /* Point on the next character */ + ptr++; + /* Increment the character counter */ + i++; + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayString +* Description : Displays a maximum of 200 char on the LCD. +* Input : - Line: the starting Line where to display the character shape. +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* - *ptr: pointer to string to display on LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayString(u8 Line, u8 *ptr) +{ + u32 i = 0, column = 0, index = 0, spaceindex = 0; + u16 refcolumn = 319; + u32 length = 0; + + /* Get the string length */ + length = StrLength(ptr); + if(length > 200) + { + /* Set the Cursor position */ + LCD_SetCursor(Line, 0x013F); + /* Clear the Selected Line */ + LCD_ClearLine(Line); + LCD_DisplayStringLine(Line, " String too long "); + } + else + { + /* Set the Cursor position */ + LCD_SetCursor(Line, 0x013F); + /* Clear the Selected Line */ + LCD_ClearLine(Line); + + while(length--) + { + if(index == 20) + { + if(*ptr == 0x20) + { + ptr++; + } + else + { + for(i = 0; i < spaceindex; i++) + { + LCD_DisplayChar(Line, column, ' '); + column -= 16; + } + ptr -= (spaceindex - 1); + length += (spaceindex - 1); + } + Line += 24; + /* Clear the Selected Line */ + LCD_ClearLine(Line); + refcolumn = 319; + index = 0; + } + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, *ptr); + + /* Increment character number in one line */ + index++; + + /* Decrement the column position by 16 */ + refcolumn -= 16; + /* Point on the next character */ + ptr++; + /* Increment the number of character after the last space */ + spaceindex++; + if(*ptr == 0x20) + { + spaceindex = 0; + column = refcolumn - 16; + } + } + } +} + +/******************************************************************************* +* Function Name : LCD_ScrollText +* Description : +* Input : +* Output : None +* Return : None +*******************************************************************************/ +void LCD_ScrollText(u8 Line, u8 *ptr) +{ + u32 i = 0, length = 0, x = 0; + u16 refcolumn = 319; + + /* Get the string length */ + length = StrLength(ptr); + + while(1) + { + /* Send the string character by character on lCD */ + while ((*ptr != 0) & (i < 20)) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, *ptr); + /* Decrement the column position by 16 */ + refcolumn -= 16; + /* Point on the next character */ + ptr++; + /* Increment the character counter */ + i++; + } + vTaskDelay( 100 / portTICK_PERIOD_MS ); + i = 0; + //LCD_ClearLine(Line); + ptr -= length; + x++; + if(refcolumn < 16) + { + x = 0; + } + refcolumn = 319 - (x * 16); + } +} + +/******************************************************************************* +* Function Name : LCD_SetDisplayWindow +* Description : Sets a display window +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* - Height: display window height. +* - Width: display window width. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width) +{ + LCD_WriteReg(R1, 0xD0); + LCD_WriteReg(R5, 0x14); + + LCD_WriteReg(R69, Xpos); + LCD_WriteReg(R70, (Xpos + Height + 1)); + + LCD_WriteReg(R71, ((Ypos & 0x100)>> 8)); + LCD_WriteReg(R72, (Ypos & 0xFF)); + + LCD_WriteReg(R73, (((Ypos + Width + 1) & 0x100)>> 8)); + LCD_WriteReg(R74, ((Ypos + Width + 1) & 0xFF)); + + LCD_SetCursor(Xpos, Ypos); +} + +/******************************************************************************* +* Function Name : LCD_DrawLine +* Description : Displays a line. +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* - Length: line length. +* - Direction: line direction. +* This parameter can be one of the following values: Vertical +* or Horizontal. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction) +{ + u32 i = 0; + + LCD_SetCursor(Xpos, Ypos); + + if(Direction == Horizontal) + { + for(i = 0; i < Length; i++) + { + LCD_WriteRAM(TextColor); + } + } + else + { + for(i = 0; i < Length; i++) + { + + LCD_WriteRAM(TextColor); + Xpos++; + LCD_SetCursor(Xpos, Ypos); + } + } +} + +/******************************************************************************* +* Function Name : LCD_DrawRect +* Description : Displays a rectangle. +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* - Height: display rectangle height. +* - Width: display rectangle width. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width) +{ + LCD_DrawLine(Xpos, Ypos, Width, Horizontal); + LCD_DrawLine((Xpos + Height), Ypos, Width, Horizontal); + + LCD_DrawLine(Xpos, Ypos, Height, Vertical); + LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, Vertical); +} + +/******************************************************************************* +* Function Name : LCD_DrawCircle +* Description : Displays a circle. +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* - Height: display rectangle height. +* - Width: display rectangle width. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius) +{ + s32 D; /* Decision Variable */ + u32 CurX; /* Current X Value */ + u32 CurY; /* Current Y Value */ + + D = 3 - (Radius << 1); + CurX = 0; + CurY = Radius; + + while (CurX <= CurY) + { + LCD_SetCursor(Xpos + CurX, Ypos + CurY); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos + CurX, Ypos - CurY); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurX, Ypos + CurY); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurX, Ypos - CurY); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos + CurY, Ypos + CurX); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos + CurY, Ypos - CurX); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurY, Ypos + CurX); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurY, Ypos - CurX); + LCD_WriteRAM(TextColor); + + if (D < 0) + { + D += (CurX << 2) + 6; + } + else + { + D += ((CurX - CurY) << 2) + 10; + CurY--; + } + CurX++; + } +} + +/******************************************************************************* +* Function Name : LCD_DrawMonoPict +* Description : Displays a monocolor picture. +* Input : - Pict: pointer to the picture array. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawMonoPict(uc32 *Pict) +{ + u32 index = 0, i = 0; + + LCD_SetCursor(0, 319); + + for(index = 0; index < 2400; index++) + { + for(i = 0; i < 32; i++) + { + if((Pict[index] & (1 << i)) == 0x00) + { + LCD_WriteRAM(BackColor); + } + else + { + LCD_WriteRAM(TextColor); + } + } + } +} + +/******************************************************************************* +* Function Name : LCD_DrawBMP +* Description : Displays a bitmap picture loaded in the SPI Flash. +* Input : - BmpAddress: Bmp picture address in the SPI Flash. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawBMP(u32 BmpAddress) +{ + u32 i = 0; + + LCD_WriteReg(R1, 0xD0); + LCD_WriteReg(R5, 0x04); + + LCD_SetCursor(239, 0x013F); + + SPI_FLASH_StartReadSequence(BmpAddress); + + /* Disable SPI1 */ + SPI_Cmd(SPI1, DISABLE); + /* SPI in 16-bit mode */ + SPI_DataSizeConfig(SPI1, SPI_DataSize_16b); + /* Enable SPI1 */ + SPI_Cmd(SPI1, ENABLE); + + for(i = 0; i < 76800; i++) + { + LCD_WriteRAM(__REV_HalfWord(SPI_FLASH_SendHalfWord(0xA5A5))); + } + + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(1); + + /* Disable SPI1 */ + SPI_Cmd(SPI1, DISABLE); + /* SPI in 8-bit mode */ + SPI_DataSizeConfig(SPI1, SPI_DataSize_8b); + /* Enable SPI1 */ + SPI_Cmd(SPI1, ENABLE); +} + +/******************************************************************************* +* Function Name : LCD_WriteReg +* Description : Writes to the selected LCD register. +* Input : - LCD_Reg: address of the selected register. +* - LCD_RegValue: value to write to the selected register. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue) +{ + u16 tmp = 0; + + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET); + LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET); + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET); + + tmp = LCD_Reg << 8; + tmp |= LCD_RegValue; + + SPI_SendData(SPI2, tmp); + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET); +} + +/******************************************************************************* +* Function Name : LCD_ReadReg +* Description : Reads the selected LCD Register. +* Input : None +* Output : None +* Return : LCD Register Value. +*******************************************************************************/ +u8 LCD_ReadReg(u8 LCD_Reg) +{ + u16 tmp = 0; + + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET); + LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET); + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET); + + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + SPI_SendData(SPI2, LCD_Reg); + + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET); + + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + SPI_SendData(SPI2, 0xFF); + + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)== RESET) + { + } + tmp = SPI_ReceiveData(SPI2); + + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET); + return tmp; +} + +/******************************************************************************* +* Function Name : LCD_WriteRAM +* Description : Writes to the LCD RAM. +* Input : - RGB_Code: the pixel color in RGB mode (5-6-5). +* Output : None +* Return : None +*******************************************************************************/ +void LCD_WriteRAM(u16 RGB_Code) +{ + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET); + LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET); + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET); + + SPI_SendData(SPI2, RGB_Code); + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET); +} + +/******************************************************************************* +* Function Name : LCD_ReadRAM +* Description : Reads the LCD RAM. +* Input : None +* Output : None +* Return : LCD RAM Value. +*******************************************************************************/ +u16 LCD_ReadRAM(void) +{ + u16 tmp = 0; + + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET); + LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET); + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET); + + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + SPI_SendData(SPI2, 0xFF); + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)==RESET) + { + } + tmp = SPI_ReceiveData(SPI2); + + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET); + + return tmp; +} + +/******************************************************************************* +* Function Name : LCD_PowerOn +* Description : +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_PowerOn(void) +{ + /* Power On Set */ + LCD_WriteReg(R28, 0x73); + LCD_WriteReg(R36, 0x74); + LCD_WriteReg(R30, 0x01); + LCD_WriteReg(R24, 0xC1); + vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */ + LCD_WriteReg(R24, 0xE1); + LCD_WriteReg(R24, 0xF1); + vTaskDelay( 60 / portTICK_PERIOD_MS ); /* Delay 60 ms */ + LCD_WriteReg(R24, 0xF5); + vTaskDelay( 60 / portTICK_PERIOD_MS ); /* Delay 60 ms */ + LCD_WriteReg(R27, 0x09); + vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */ + LCD_WriteReg(R31, 0x11); + LCD_WriteReg(R32, 0x0E); + LCD_WriteReg(R30, 0x81); + vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */ +} + +/******************************************************************************* +* Function Name : LCD_DisplayOn +* Description : Enables the Display. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayOn(void) +{ + LCD_WriteReg(R1, 0x50); + LCD_WriteReg(R5, 0x04); + + /* Display On */ + LCD_WriteReg(R0, 0x80); + LCD_WriteReg(R59, 0x01); + vTaskDelay( 40 / portTICK_PERIOD_MS ); /* Delay 40 ms */ + LCD_WriteReg(R0, 0x20); +} + +/******************************************************************************* +* Function Name : LCD_DisplayOff +* Description : Disables the Display. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayOff(void) +{ + /* Display Off */ + LCD_WriteReg(R0, 0xA0); + vTaskDelay( 40 / portTICK_PERIOD_MS ); /* Delay 40 ms */ + LCD_WriteReg(R59, 0x00); +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesConfig +* Description : Configures LCD control lines in Output Push-Pull mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure NCS (PB.02) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Configure NWR(RNW), RS (PD.15, PD.07) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_15; + GPIO_Init(GPIOD, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesWrite +* Description : Sets or reset LCD control lines. +* Input : - GPIOx: where x can be B or D to select the GPIO peripheral. +* - CtrlPins: the Control line. This parameter can be: +* - CtrlPin_NCS: Chip Select pin (PB.02) +* - CtrlPin_NWR: Read/Write Selection pin (PD.15) +* - CtrlPin_RS: Register/RAM Selection pin (PD.07) +* - BitVal: specifies the value to be written to the selected bit. +* This parameter can be: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal) +{ + /* Set or Reset the control line */ + GPIO_WriteBit(GPIOx, CtrlPins, BitVal); +} + +/******************************************************************************* +* Function Name : LCD_SPIConfig +* Description : Configures the SPI2 interface. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SPIConfig(void) +{ + SPI_InitTypeDef SPI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOA clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + + /* Enable SPI2 clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); + + /* Configure SPI2 pins: NSS, SCK, MISO and MOSI */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* SPI2 Config */ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_Init(SPI2, &SPI_InitStructure); + + /* SPI2 enable */ + SPI_Cmd(SPI2, ENABLE); +} + +/******************************************************************************* +* Function Name : StrLength +* Description : Returns length of string. +* Input : - Str: Character Pointer. +* Output : None +* Return : String length. +*******************************************************************************/ +static u32 StrLength(u8 *Str) +{ + u32 Index = 0; + + /* Increment the Index unless the end of string */ + for(Index = 0; *Str != '\0'; Str++, Index++) + { + } + + return Index; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/misc.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/misc.c new file mode 100644 index 0000000..4378727 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/misc.c @@ -0,0 +1,230 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file provides all the miscellaneous firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @defgroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and + * subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval : None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure + * that contains the configuration information for the + * specified NVIC peripheral. + * @retval : None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or + * FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. + * This value must be a multiple of 0x100. + * @retval : None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter + * low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 + * selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as + * SysTick clock source. + * @retval : None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_adc.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_adc.c new file mode 100644 index 0000000..caf94a2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_adc.c @@ -0,0 +1,1321 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_adc.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the ADC firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ADC ADON mask */ +#define CR2_ADON_Set ((u32)0x00000001) +#define CR2_ADON_Reset ((u32)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((u16)0x0100) +#define CR2_DMA_Reset ((u16)0xFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((u16)0x0008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((u16)0x0004) + +/* ADC SWSTRT mask */ +#define CR2_SWSTRT_Set ((u32)0x00400000) + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((u32)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((u32)0x00000800) +#define CR1_DISCEN_Reset ((u32)0xFFFFF7FF) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((u32)0x00100000) +#define CR2_EXTTRIG_Reset ((u32)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTRT_Set ((u32)0x00500000) +#define CR2_EXTTRIG_SWSTRT_Reset ((u32)0xFFAFFFFF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((u32)0x00000400) +#define CR1_JAUTO_Reset ((u32)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((u32)0x00001000) +#define CR1_JDISCEN_Reset ((u32)0xFFFFEFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((u32)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((u32)0x00008000) +#define CR2_JEXTTRIG_Reset ((u32)0xFFFF7FFF) + +/* ADC JSWSTRT mask */ +#define CR2_JSWSTRT_Set ((u32)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTRT_Set ((u32)0x00208000) +#define CR2_JEXTTRIG_JSWSTRT_Reset ((u32)0xFFDF7FFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((u32)0xFFFFFFE0) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((u8)0x1F) +#define SQR2_SQ_Set ((u8)0x1F) +#define SQR1_SQ_Set ((u8)0x1F) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((u8)0x1F) + +/* ADC JL mask */ +#define JSQR_JL_Reset ((u32)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((u8)0x07) +#define SMPR2_SMP_Set ((u8)0x07) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((u32)0xFF3FFDFF) + +/* ADC TSPD mask */ +#define CR2_TSPD_Set ((u32)0x00800000) +#define CR2_TSPD_Reset ((u32)0xFF7FFFFF) + +/* ADC JDRx registers= offset */ +#define JDR_Offset ((u8)0x28) + +/* ADC registers Masks */ +#define CR1_CLEAR_Mask ((u32)0xFFF0FEFF) +#define CR2_CLEAR_Mask ((u32)0xFFF1F7FD) +#define SQR1_CLEAR_Mask ((u32)0xFF0FFFFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ADC_DeInit +* Description : Deinitializes the ADCx peripheral registers to their default +* reset values. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + switch (*(u32*)&ADCx) + { + case ADC1_BASE: + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + break; + + case ADC2_BASE: + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : ADC_Init +* Description : Initializes the ADCx according to the specified parameters +* in the ADC_InitStruct. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_InitStruct: pointer to a ADC_InitTypeDef structure that +* contains the configuration information for the specified +* ADC peripheral. +* Output : None +* Return : None +******************************************************************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + u32 tmpreg1 = 0; + u8 tmpreg2 = 0; + + /* Check the parameters */ + assert(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMODE and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMODE bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTTRIG bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTTRIG bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1); + tmpreg1 |= ((u32)tmpreg2 << 20); + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_StructInit +* Description : Fills each ADC_InitStruct member with its default value. +* Input : ADC_InitStruct : pointer to a ADC_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/******************************************************************************* +* Function Name : ADC_Cmd +* Description : Enables or disables the specified ADC peripheral. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the ADCx peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_DMACmd +* Description : Enables or disables the specified ADC DMA request. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_ITConfig +* Description : Enables or disables the specified ADC interrupts. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_IT: specifies the ADC interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - ADC_IT_EOC: End of conversion interrupt mask +* - ADC_IT_AWD: Analog watchdog interrupt mask +* - ADC_IT_JEOC: End of injected conversion interrupt mask +* - NewState: new state of the specified ADC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState) +{ + u8 itmask = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + assert(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (u8)ADC_IT; + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(u32)itmask); + } +} + +/******************************************************************************* +* Function Name : ADC_ResetCalibration +* Description : Resets the ADC calibration registers. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Resets the selected ADC calibartion registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/******************************************************************************* +* Function Name : ADC_GetResetCalibrationStatus +* Description : Gets the ADC reset calibration registers status. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC Reset Calibration registers (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u16)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_StartCalibration +* Description : Starts the calibration process. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/******************************************************************************* +* Function Name : ADC_GetCalibrationStatus +* Description : Gets the ADC calibration status. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC calibration (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (u16)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_SoftwareStartConvCmd +* Description : Enables or disables the ADC software start conversion . +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC software start conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + /* Starts the selected ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTRT_Set; + } + else + { + /* Stops the selected ADC conversion */ + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTRT_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetSoftwareStartConvStatus +* Description : Gets the ADC Software start conversion Status. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC software start conversion (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the status of SWSTRT bit */ + if ((ADCx->CR2 & CR2_SWSTRT_Set) != (u32)RESET) + { + /* SWSTRT bit is set */ + bitstatus = SET; + } + else + { + /* SWSTRT bit is reset */ + bitstatus = RESET; + } + /* Return the SWSTRT bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_DiscModeChannelCountConfig +* Description : Configures the discontinuous mode for the selected ADC regular +* group channel. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - Number: specifies the discontinuous mode regular channel +* count value. This mumber must be between 1 and 8. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number) +{ + u32 tmpreg1 = 0; + u8 tmpreg2 = 0; + + /* Check the parameters */ + assert(IS_ADC_REGULAR_DISC_NUMBER(Number)); + + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= ((u32)tmpreg2 << 13); + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_DiscModeCmd +* Description : Enables or disables the discontinuous mode on regular group +* channel for the specified ADC +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC discontinuous mode +* on regular group channel. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_RegularChannelConfig +* Description : Configures for the selected ADC regular channel its corresponding +* rank in the sequencer and its sample time. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_Channel: the ADC channel to configure. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC Channel0 selected +* - ADC_Channel_1: ADC Channel1 selected +* - ADC_Channel_2: ADC Channel2 selected +* - ADC_Channel_3: ADC Channel3 selected +* - ADC_Channel_4: ADC Channel4 selected +* - ADC_Channel_5: ADC Channel5 selected +* - ADC_Channel_6: ADC Channel6 selected +* - ADC_Channel_7: ADC Channel7 selected +* - ADC_Channel_8: ADC Channel8 selected +* - ADC_Channel_9: ADC Channel9 selected +* - ADC_Channel_10: ADC Channel10 selected +* - ADC_Channel_11: ADC Channel11 selected +* - ADC_Channel_12: ADC Channel12 selected +* - ADC_Channel_13: ADC Channel13 selected +* - ADC_Channel_14: ADC Channel14 selected +* - ADC_Channel_15: ADC Channel15 selected +* - ADC_Channel_16: ADC Channel16 selected +* - ADC_Channel_17: ADC Channel17 selected +* - Rank: The rank in the regular group sequencer. This parameter +* must be between 1 to 16. +* - ADC_SampleTime: The sample time value to be set for the +* selected channel. +* This parameter can be one of the following values: +* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles +* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles +* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles +* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles +* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles +* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles +* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles +* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles +* Output : None +* Return : None +*******************************************************************************/ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime) +{ + u32 tmpreg1 = 0, tmpreg2 = 0; + + /* Check the parameters */ + assert(IS_ADC_CHANNEL(ADC_Channel)); + assert(IS_ADC_REGULAR_RANK(Rank)); + assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/******************************************************************************* +* Function Name : ADC_ExternalTrigConvCmd +* Description : Enables or disables the ADCx conversion through external trigger. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC external trigger +* start of conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetConversionValue +* Description : Returns the last ADC conversion result data for regular channel. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The Data conversion value. +*******************************************************************************/ +u16 ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Return the selected ADC conversion value */ + return (u16) ADCx->DR; +} + +/******************************************************************************* +* Function Name : ADC_GetDualModeConversionValue +* Description : Returns the last ADCs conversion result data in dual mode. +* Output : None +* Return : The Data conversion value. +*******************************************************************************/ +u32 ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return ADC1->DR; +} + +/******************************************************************************* +* Function Name : ADC_AutoInjectedConvCmd +* Description : Enables or disables the automatic injected group conversion +* after regular one. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC auto injected +* conversion +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_InjectedDiscModeCmd +* Description : Enables or disables the discontinuous mode for injected group +* channel for the specified ADC +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC discontinuous mode +* on injected group channel. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_ExternalTrigInjectedConvConfig +* Description : Configures the external trigger for injected channels conversion. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_ExternalTrigInjecConv: specifies the ADC trigger to +* start injected conversion. +* This parameter can be one of the following values: +* - ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event +* selected +* - ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture +* compare4 selected +* - ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event +* selected +* - ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture +* compare1 selected +* - ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture +* compare4 selected +* - ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event +* selected +* - ADC_ExternalTrigInjecConv_Ext_Interrupt15: External +* interrupt 15 event selected +* - ADC_ExternalTrigInjecConv_None: Injected conversion +* started by software and not by external trigger +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/******************************************************************************* +* Function Name : ADC_ExternalTrigInjectedConvCmd +* Description : Enables or disables the ADCx injected channels conversion +* through external trigger +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC external trigger +* start of injected conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_SoftwareStartInjectedConvCmd +* Description : Enables or disables the start of the injected channels conversion. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC software start +* injected conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + /* Starts the selected ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTRT_Set; + } + else + { + /* Stops the selected ADC injected conversion */ + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTRT_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetSoftwareStartInjectedConvCmdStatus +* Description : Gets the ADC Software start injected conversion Status. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC software start injected conversion (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the status of JSWSTRT bit */ + if ((ADCx->CR2 & CR2_JSWSTRT_Set) != (u32)RESET) + { + /* JSWSTRT bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTRT bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTRT bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_InjectedChannelConfig +* Description : Configures for the selected ADC injected channel its corresponding +* rank in the sequencer and its sample time. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_Channel: the ADC channel to configure. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC Channel0 selected +* - ADC_Channel_1: ADC Channel1 selected +* - ADC_Channel_2: ADC Channel2 selected +* - ADC_Channel_3: ADC Channel3 selected +* - ADC_Channel_4: ADC Channel4 selected +* - ADC_Channel_5: ADC Channel5 selected +* - ADC_Channel_6: ADC Channel6 selected +* - ADC_Channel_7: ADC Channel7 selected +* - ADC_Channel_8: ADC Channel8 selected +* - ADC_Channel_9: ADC Channel9 selected +* - ADC_Channel_10: ADC Channel10 selected +* - ADC_Channel_11: ADC Channel11 selected +* - ADC_Channel_12: ADC Channel12 selected +* - ADC_Channel_13: ADC Channel13 selected +* - ADC_Channel_14: ADC Channel14 selected +* - ADC_Channel_15: ADC Channel15 selected +* - ADC_Channel_16: ADC Channel16 selected +* - ADC_Channel_17: ADC Channel17 selected +* - Rank: The rank in the injected group sequencer. This parameter +* must be between 1 to 4. +* - ADC_SampleTime: The sample time value to be set for the +* selected channel. +* This parameter can be one of the following values: +* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles +* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles +* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles +* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles +* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles +* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles +* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles +* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime) +{ + u32 tmpreg1 = 0, tmpreg2 = 0; + u8 tmpreg3 = 0; + + /* Check the parameters */ + assert(IS_ADC_CHANNEL(ADC_Channel)); + assert(IS_ADC_INJECTED_RANK(Rank)); + assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (u8)((tmpreg1 & (u32)~JSQR_JL_Reset)>> 20); + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (u32)JSQR_JSQ_Set << (5 * ((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (u32)ADC_Channel << (5 * ((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_InjectedSequencerLengthConfig +* Description : Configures the sequencer for injected channels +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - Length: The sequencer length. +* This parameter must be a number between 1 to 4. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length) +{ + u32 tmpreg1 = 0; + u8 tmpreg2 = 0; + + /* Check the parameters */ + assert(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= (u32)tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_SetInjectedOffset +* Description : Set the injected channels conversion value offset +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_InjectedChannel: the ADC injected channel to set its +* offset. +* This parameter can be one of the following values: +* - ADC_InjectedChannel_1: Injected Channel1 selected +* - ADC_InjectedChannel_2: Injected Channel2 selected +* - ADC_InjectedChannel_3: Injected Channel3 selected +* - ADC_InjectedChannel_4: Injected Channel4 selected +* Output : None +* Return : None +*******************************************************************************/ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset) +{ + /* Check the parameters */ + assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert(IS_ADC_OFFSET(Offset)); + + /* Set the selected injected channel data offset */ + *((u32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset; +} + +/******************************************************************************* +* Function Name : ADC_GetInjectedConversionValue +* Description : Returns the ADC conversion result data for the selected +* injected channel +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_InjectedChannel: the converted ADC injected channel. +* This parameter can be one of the following values: +* - ADC_InjectedChannel_1: Injected Channel1 selected +* - ADC_InjectedChannel_2: Injected Channel2 selected +* - ADC_InjectedChannel_3: Injected Channel3 selected +* - ADC_InjectedChannel_4: Injected Channel4 selected +* Output : None +* Return : The Data conversion value. +*******************************************************************************/ +u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel) +{ + /* Check the parameters */ + assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + /* Returns the selected injected channel conversion data value */ + return (u16) (*(u32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset))); +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogCmd +* Description : Enables or disables the analog watchdog on single/all regular +* or injected channels +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_AnalogWatchdog: the ADC analog watchdog configuration. +* This parameter can be one of the following values: +* - ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on +* a single regular channel +* - ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on +* a single injected channel +* - ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog +* watchdog on a single regular or injected channel +* - ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on +* all regular channel +* - ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on +* all injected channel +* - ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog +* on all regular and injected channels +* - ADC_AnalogWatchdog_None: No channel guarded by the +* analog watchdog +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogThresholdsConfig +* Description : Configures the High and low thresholds of the analog watchdog. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - HighThreshold: the ADC analog watchdog High threshold value. +* This parameter must be a 12bit value. +* - LowThreshold: the ADC analog watchdog Low threshold value. +* This parameter must be a 12bit value. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, + u16 LowThreshold) +{ + /* Check the parameters */ + assert(IS_ADC_THRESHOLD(HighThreshold)); + assert(IS_ADC_THRESHOLD(LowThreshold)); + + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogSingleChannelConfig +* Description : Configures the analog watchdog guarded single channel +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_Channel: the ADC channel to configure for the analog +* watchdog. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC Channel0 selected +* - ADC_Channel_1: ADC Channel1 selected +* - ADC_Channel_2: ADC Channel2 selected +* - ADC_Channel_3: ADC Channel3 selected +* - ADC_Channel_4: ADC Channel4 selected +* - ADC_Channel_5: ADC Channel5 selected +* - ADC_Channel_6: ADC Channel6 selected +* - ADC_Channel_7: ADC Channel7 selected +* - ADC_Channel_8: ADC Channel8 selected +* - ADC_Channel_9: ADC Channel9 selected +* - ADC_Channel_10: ADC Channel10 selected +* - ADC_Channel_11: ADC Channel11 selected +* - ADC_Channel_12: ADC Channel12 selected +* - ADC_Channel_13: ADC Channel13 selected +* - ADC_Channel_14: ADC Channel14 selected +* - ADC_Channel_15: ADC Channel15 selected +* - ADC_Channel_16: ADC Channel16 selected +* - ADC_Channel_17: ADC Channel17 selected +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_ADC_CHANNEL(ADC_Channel)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/******************************************************************************* +* Function Name : ADC_TempSensorCmd +* Description : Enables or disables the temperature sensor. +* Input : - NewState: new state of the temperature sensor. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_TempSensorCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the temperature sensor */ + ADC1->CR2 |= CR2_TSPD_Set; + } + else + { + /* Disable the temperature sensor */ + ADC1->CR2 &= CR2_TSPD_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetFlagStatus +* Description : Checks whether the specified ADC flag is set or not. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - ADC_FLAG_AWD: Analog watchdog flag +* - ADC_FLAG_EOC: End of conversion flag +* - ADC_FLAG_JEOC: End of injected group conversion flag +* - ADC_FLAG_JSTRT: Start of injected group conversion flag +* - ADC_FLAG_STRT: Start of regular group conversion flag +* Output : None +* Return : The new state of ADC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_ADC_GET_FLAG(ADC_FLAG)); + + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (u8)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_ClearFlag +* Description : Clears the ADCx's pending flags. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - ADC_FLAG_AWD: Analog watchdog flag +* - ADC_FLAG_EOC: End of conversion flag +* - ADC_FLAG_JEOC: End of injected group conversion flag +* - ADC_FLAG_JSTRT: Start of injected group conversion flag +* - ADC_FLAG_STRT: Start of regular group conversion flag +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG) +{ + /* Check the parameters */ + assert(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->SR &= ~(u32)ADC_FLAG; +} + +/******************************************************************************* +* Function Name : ADC_GetITStatus +* Description : Checks whether the specified ADC interrupt has occurred or not. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_IT: specifies the ADC interrupt source to check. +* This parameter can be one of the following values: +* - ADC_IT_EOC: End of conversion interrupt mask +* - ADC_IT_AWD: Analog watchdog interrupt mask +* - ADC_IT_JEOC: End of injected conversion interrupt mask +* Output : None +* Return : The new state of ADC_IT (SET or RESET). +*******************************************************************************/ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT) +{ + ITStatus bitstatus = RESET; + u8 itmask = 0, enablestatus; + + /* Check the parameters */ + assert(IS_ADC_GET_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (u8)(ADC_IT >> 8); + + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (u8)ADC_IT) ; + + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (u8)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_ClearITPendingBit +* Description : Clears the ADCs interrupt pending bits. +* Input : - ADC_IT: specifies the ADC interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - ADC_IT_EOC: End of conversion interrupt mask +* - ADC_IT_AWD: Analog watchdog interrupt mask +* - ADC_IT_JEOC: End of injected conversion interrupt mask +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT) +{ + u8 itmask = 0; + + /* Check the parameters */ + assert(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (u8)(ADC_IT >> 8); + + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR &= ~(u32)itmask; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_bkp.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_bkp.c new file mode 100644 index 0000000..a8616e0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_bkp.c @@ -0,0 +1,263 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_bkp.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the BKP firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ BKP registers bit address in the alias region ----------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- RTCCR Register ---*/ +/* Alias word address of CCO bit */ +#define RTCCR_OFFSET (BKP_OFFSET + 0x2C) +#define CCO_BitNumber 0x07 +#define RTCCR_CCO_BB (PERIPH_BB_BASE + (RTCCR_OFFSET * 32) + (CCO_BitNumber * 4)) + +/* --- CR Register ---*/ +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + + +/* ---------------------- BKP registers bit mask ------------------------ */ +/* RTCCR register bit mask */ +#define RTCCR_CAL_Mask ((u16)0xFF80) + +/* CSR register bit mask */ +#define CSR_CTE_Set ((u16)0x0001) +#define CSR_CTI_Set ((u16)0x0002) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : BKP_DeInit +* Description : Deinitializes the BKP peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/******************************************************************************* +* Function Name : BKP_TamperPinLevelConfig +* Description : Configures the Tamper Pin active level. +* Input : - BKP_TamperPinLevel: specifies the Tamper Pin active level. +* This parameter can be one of the following values: +* - BKP_TamperPinLevel_High: Tamper pin active on high level +* - BKP_TamperPinLevel_Low: Tamper pin active on low level +* Output : None +* Return : None +*******************************************************************************/ +void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + + *(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/******************************************************************************* +* Function Name : BKP_TamperPinCmd +* Description : Enables or disables the Tamper Pin activation. +* Input : - NewState: new state of the Tamper Pin activation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_TPE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : BKP_ITConfig +* Description : Enables or disables the Tamper Pin Interrupt. +* Input : - NewState: new state of the Tamper Pin Interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CSR_TPIE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : BKP_RTCCalibrationClockOutputCmd +* Description : Enables or disables the output of the Calibration Clock. +* Input : - NewState: new state of the Calibration Clock output. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) RTCCR_CCO_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : BKP_SetRTCCalibrationValue +* Description : Sets RTC Clock Calibration value. +* Input : - CalibrationValue: specifies the RTC Clock Calibration value. +* This parameter must be a number between 0 and 0x7F. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_SetRTCCalibrationValue(u8 CalibrationValue) +{ + u16 tmpreg = 0; + + /* Check the parameters */ + assert(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + + tmpreg = BKP->RTCCR; + + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_Mask; + + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/******************************************************************************* +* Function Name : BKP_WriteBackupRegister +* Description : Writes user data to the specified Data Backup Register. +* Input : - BKP_DR: specifies the Data Backup Register. +* This parameter can be BKP_DRx where x:[1, 10] +* - Data: data to write +* Output : None +* Return : None +*******************************************************************************/ +void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data) +{ + /* Check the parameters */ + assert(IS_BKP_DR(BKP_DR)); + + *(vu16 *) (BKP_BASE + BKP_DR) = Data; +} + +/******************************************************************************* +* Function Name : BKP_ReadBackupRegister +* Description : Reads data from the specified Data Backup Register. +* Input : - BKP_DR: specifies the Data Backup Register. +* This parameter can be BKP_DRx where x:[1, 10] +* Output : None +* Return : The content of the specified Data Backup Register +*******************************************************************************/ +u16 BKP_ReadBackupRegister(u16 BKP_DR) +{ + /* Check the parameters */ + assert(IS_BKP_DR(BKP_DR)); + + return (*(vu16 *) (BKP_BASE + BKP_DR)); +} + +/******************************************************************************* +* Function Name : BKP_GetFlagStatus +* Description : Checks whether the Tamper Pin Event flag is set or not. +* Input : None +* Output : None +* Return : The new state of the Tamper Pin Event flag (SET or RESET). +*******************************************************************************/ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(vu32 *) CSR_TEF_BB); +} + +/******************************************************************************* +* Function Name : BKP_ClearFlag +* Description : Clears Tamper Pin Event pending flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= CSR_CTE_Set; +} + +/******************************************************************************* +* Function Name : BKP_GetITStatus +* Description : Checks whether the Tamper Pin Interrupt has occurred or not. +* Input : None +* Output : None +* Return : The new state of the Tamper Pin Interrupt (SET or RESET). +*******************************************************************************/ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(vu32 *) CSR_TIF_BB); +} + +/******************************************************************************* +* Function Name : BKP_ClearITPendingBit +* Description : Clears Tamper Pin Interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= CSR_CTI_Set; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_can.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_can.c new file mode 100644 index 0000000..3457f0d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_can.c @@ -0,0 +1,873 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_can.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the CAN firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ +/* CAN Master Control Register bits */ +#define CAN_MCR_INRQ ((u32)0x00000001) /* Initialization request */ +#define CAN_MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */ +#define CAN_MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */ +#define CAN_MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */ +#define CAN_MCR_NART ((u32)0x00000010) /* No automatic retransmission */ +#define CAN_MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */ +#define CAN_MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */ +#define CAN_MCR_TTCM ((u32)0x00000080) /* time triggered communication */ + +/* CAN Master Status Register bits */ +#define CAN_MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */ +#define CAN_MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */ +#define CAN_MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */ + +/* CAN Transmit Status Register bits */ +#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */ +#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */ +#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */ +#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */ +#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */ +#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */ +#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */ +#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */ +#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */ +#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */ +#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */ +#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */ + +/* CAN Receive FIFO 0 Register bits */ +#define CAN_RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */ +#define CAN_RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */ +#define CAN_RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */ + +/* CAN Receive FIFO 1 Register bits */ +#define CAN_RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */ +#define CAN_RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */ +#define CAN_RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */ + +/* CAN Error Status Register bits */ +#define CAN_ESR_EWGF ((u32)0x00000001) /* Error warning flag */ +#define CAN_ESR_EPVF ((u32)0x00000002) /* Error passive flag */ +#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-off flag */ + +/* CAN Mailbox Transmit Request */ +#define CAN_TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define CAN_FMR_FINIT ((u32)0x00000001) /* Filter init mode */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit); + +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_DeInit(void) +{ + /* Enable CAN reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE); + /* Release CAN from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE); +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + contains the configuration information for the CAN peripheral. +* Output : None. +* Return : Constant indicates initialization succeed which will be +* CANINITFAILED or CANINITOK. +*******************************************************************************/ +u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + u8 InitStatus = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert(IS_CAN_CLOCK(CAN_InitStruct->CAN_Clock)); + assert(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Request initialisation */ + CAN->MCR = CAN_MCR_INRQ; + + /* ...and check acknowledged */ + if ((CAN->MSR & CAN_MSR_INAK) == 0) + { + InitStatus = CANINITFAILED; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CAN->MCR |= CAN_MCR_TTCM; + } + else + { + CAN->MCR &= ~CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CAN->MCR |= CAN_MCR_ABOM; + } + else + { + CAN->MCR &= ~CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CAN->MCR |= CAN_MCR_AWUM; + } + else + { + CAN->MCR &= ~CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CAN->MCR |= CAN_MCR_NART; + } + else + { + CAN->MCR &= ~CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CAN->MCR |= CAN_MCR_RFLM; + } + else + { + CAN->MCR &= ~CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CAN->MCR |= CAN_MCR_TXFP; + } + else + { + CAN->MCR &= ~CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) | + ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) | + ((u32)CAN_InitStruct->CAN_Clock << 15) | ((u32)CAN_InitStruct->CAN_Prescaler - 1); + + InitStatus = CANINITOK; + + /* Request leave initialisation */ + CAN->MCR &= ~CAN_MCR_INRQ; + + /* ...and check acknowledged */ + if ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CANINITFAILED; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/******************************************************************************* +* Function Name : CAN_FilterInit +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_FilterInitStruct. +* Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef +* structure that contains the configuration information. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + u16 FilterNumber_BitPos = 0; + + /* Check the parameters */ + assert(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + FilterNumber_BitPos = (u16)((u16)0x0001 << ((u16)CAN_FilterInitStruct->CAN_FilterNumber)); + + /* Initialisation mode for the filter */ + CAN->FMR |= CAN_FMR_FINIT; + + /* Filter Deactivation */ + CAN->FA0R &= ~(u32)FilterNumber_BitPos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN->FS0R &= ~(u32)FilterNumber_BitPos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh); + } + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN->FS0R |= FilterNumber_BitPos; + + /* 32-bit identifier or First 32-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow); + + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN->FM0R &= ~(u32)FilterNumber_BitPos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN->FM0R |= (u32)FilterNumber_BitPos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN->FFA0R &= ~(u32)FilterNumber_BitPos; + } + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN->FFA0R |= (u32)FilterNumber_BitPos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN->FA0R |= FilterNumber_BitPos; + } + + /* Leave the initialisation mode for the filter */ + CAN->FMR &= ~CAN_FMR_FINIT; +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its default value. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_0tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Clock member */ + CAN_InitStruct->CAN_Clock = CAN_Clock_APB; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/******************************************************************************* +* Function Name : CAN_ITConfig +* Description : Enables or disables the CAN interrupts. +* Input : - CAN_IT: specifies the CAN interrupt sources to be enabled or +* disabled. +* - NewState: new state of the CAN interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_CAN_IT(CAN_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CAN interrupt */ + CAN->IER |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CAN->IER &= ~CAN_IT; + } +} + +/******************************************************************************* +* Function Name : CAN_Transmit +* Description : Initiates the transmission of a message. +* Input : TxMessage: pointer to a structure which contains CAN Id, CAN +* DLC and CAN datas. +* Output : None. +* Return : The number of the mailbox that is used for transmission +* or CAN_NO_MB if there is no empty mailbox. +*******************************************************************************/ +u8 CAN_Transmit(CanTxMsg* TxMessage) +{ + u8 TransmitMailbox = 0; + + /* Check the parameters */ + assert(IS_CAN_STDID(TxMessage->StdId)); + assert(IS_CAN_EXTID(TxMessage->StdId)); + assert(IS_CAN_IDTYPE(TxMessage->IDE)); + assert(IS_CAN_RTR(TxMessage->RTR)); + assert(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CAN->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + TransmitMailbox = 0; + } + else if ((CAN->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + TransmitMailbox = 1; + } + else if ((CAN->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + TransmitMailbox = 2; + } + else + { + TransmitMailbox = CAN_NO_MB; + } + + if (TransmitMailbox != CAN_NO_MB) + { + /* Set up the Id */ + TxMessage->StdId &= (u32)0x000007FF; + TxMessage->StdId = TxMessage->StdId << 21; + TxMessage->ExtId &= (u32)0x0003FFFF; + TxMessage->ExtId <<= 3; + + CAN->sTxMailBox[TransmitMailbox].TIR &= CAN_TMIDxR_TXRQ; + CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->ExtId | + TxMessage->IDE | TxMessage->RTR); + + /* Set up the DLC */ + TxMessage->DLC &= (u8)0x0000000F; + CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0; + CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) | ((u32)TxMessage->Data[2] << 16) | + ((u32)TxMessage->Data[1] << 8) | ((u32)TxMessage->Data[0])); + CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) | ((u32)TxMessage->Data[6] << 16) | + ((u32)TxMessage->Data[5] << 8) | ((u32)TxMessage->Data[4])); + + /* Request transmission */ + CAN->sTxMailBox[TransmitMailbox].TIR |= CAN_TMIDxR_TXRQ; + } + + return TransmitMailbox; +} + +/******************************************************************************* +* Function Name : CAN_TransmitStatus +* Description : Check the transmission of a message. +* Input : TransmitMailbox: the number of the mailbox that is used for +* transmission. +* Output : None. +* Return : CANTXOK if the CAN driver transmits the message, CANTXFAILED +* in an other case. +*******************************************************************************/ +u32 CAN_TransmitStatus(u8 TransmitMailbox) +{ + /* RQCP, TXOK and TME bits */ + u32 State = 0; + + /* Check the parameters */ + assert(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (0): State |= ((CAN->TSR & CAN_TSR_RQCP0) << 2); + State |= ((CAN->TSR & CAN_TSR_TXOK0) >> 0); + State |= ((CAN->TSR & CAN_TSR_TME0) >> 26); + break; + case (1): State |= ((CAN->TSR & CAN_TSR_RQCP1) >> 6); + State |= ((CAN->TSR & CAN_TSR_TXOK1) >> 8); + State |= ((CAN->TSR & CAN_TSR_TME1) >> 27); + break; + case (2): State |= ((CAN->TSR & CAN_TSR_RQCP2) >> 14); + State |= ((CAN->TSR & CAN_TSR_TXOK2) >> 16); + State |= ((CAN->TSR & CAN_TSR_TME2) >> 28); + break; + default: + State = CANTXFAILED; + break; + } + + switch (State) + { + /* transmit pending */ + case (0x0): State = CANTXPENDING; + break; + /* transmit failed */ + case (0x5): State = CANTXFAILED; + break; + /* transmit succedeed */ + case (0x7): State = CANTXOK; + break; + default: + State = CANTXFAILED; + break; + } + + return State; +} + +/******************************************************************************* +* Function Name : CAN_CancelTransmit +* Description : Cancels a transmit request. +* Input : Mailbox number. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_CancelTransmit(u8 Mailbox) +{ + /* Check the parameters */ + assert(IS_CAN_TRANSMITMAILBOX(Mailbox)); + + /* abort transmission */ + switch (Mailbox) + { + case (0): CAN->TSR |= CAN_TSR_ABRQ0; + break; + case (1): CAN->TSR |= CAN_TSR_ABRQ1; + break; + case (2): CAN->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} + +/******************************************************************************* +* Function Name : CAN_FIFORelease +* Description : Release a FIFO. +* Input : FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_FIFORelease(u8 FIFONumber) +{ + /* Check the parameters */ + assert(IS_CAN_FIFO(FIFONumber)); + + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CAN->RF0R = CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CAN->RF1R = CAN_RF1R_RFOM1; + } +} + +/******************************************************************************* +* Function Name : CAN_MessagePending +* Description : Return the number of pending messages. +* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. +* Output : None. +* Return : NbMessage which is the number of pending message. +*******************************************************************************/ +u8 CAN_MessagePending(u8 FIFONumber) +{ + u8 MessagePending=0; + + /* Check the parameters */ + assert(IS_CAN_FIFO(FIFONumber)); + + if (FIFONumber == CAN_FIFO0) + { + MessagePending = (u8)(CAN->RF0R&(u32)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + MessagePending = (u8)(CAN->RF1R&(u32)0x03); + } + else + { + MessagePending = 0; + } + return MessagePending; +} + +/******************************************************************************* +* Function Name : CAN_Receive +* Description : Receives a message. +* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. +* Output : RxMessage: pointer to a structure which contains CAN Id, +* CAN DLC, CAN datas and FMI number. +* Return : None. +*******************************************************************************/ +void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert(IS_CAN_FIFO(FIFONumber)); + + /* Get the Id */ + RxMessage->StdId = (u32)0x000007FF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 21); + RxMessage->ExtId = (u32)0x0003FFFF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 3); + + RxMessage->IDE = (u32)0x00000004 & CAN->sFIFOMailBox[FIFONumber].RIR; + RxMessage->RTR = (u32)0x00000002 & CAN->sFIFOMailBox[FIFONumber].RIR; + + /* Get the DLC */ + RxMessage->DLC = (u32)0x0000000F & CAN->sFIFOMailBox[FIFONumber].RDTR; + + /* Get the FMI */ + RxMessage->FMI = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDTR >> 8); + + /* Get the data field */ + RxMessage->Data[0] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 24); + + RxMessage->Data[4] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 24); + + /* Release the FIFO */ + CAN_FIFORelease(FIFONumber); +} + +/******************************************************************************* +* Function Name : CAN_Sleep +* Description : Enters the low power mode. +* Input : None. +* Output : None. +* Return : CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. +*******************************************************************************/ +u8 CAN_Sleep(void) +{ + u8 SleepStatus = 0; + + /* Sleep mode entering request */ + CAN->MCR |= CAN_MCR_SLEEP; + SleepStatus = CANSLEEPOK; + + /* Sleep mode status */ + if ((CAN->MCR&CAN_MCR_SLEEP) == 0) + { + /* Sleep mode not entered */ + SleepStatus = CANSLEEPFAILED; + } + + /* At this step, sleep mode status */ + return SleepStatus; +} + +/******************************************************************************* +* Function Name : CAN_WakeUp +* Description : Wakes the CAN up. +* Input : None. +* Output : None. +* Return : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other +* case. +*******************************************************************************/ +u8 CAN_WakeUp(void) +{ + u8 WakeUpStatus = 0; + + /* Wake up request */ + CAN->MCR &= ~CAN_MCR_SLEEP; + WakeUpStatus = CANWAKEUPFAILED; + + /* Sleep mode status */ + if ((CAN->MCR&CAN_MCR_SLEEP) == 0) + { + /* Sleep mode exited */ + WakeUpStatus = CANWAKEUPOK; + } + + /* At this step, sleep mode status */ + return WakeUpStatus; +} + +/******************************************************************************* +* Function Name : CAN_GetFlagStatus +* Description : Checks whether the CAN flag is set or not. +* Input : CAN_FLAG: specifies the flag to check. +* Output : None. +* Return : The new state of CAN_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_CAN_FLAG(CAN_FLAG)); + + /* Check the status of the specified CAN flag */ + if ((CAN->ESR & CAN_FLAG) != (u32)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : CAN_ClearFlag +* Description : Clears the CAN's pending flags. +* Input : CAN_FLAG: specifies the flag to clear. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_ClearFlag(u32 CAN_FLAG) +{ + /* Check the parameters */ + assert(IS_CAN_FLAG(CAN_FLAG)); + + /* Clear the selected CAN flags */ + CAN->ESR &= ~CAN_FLAG; +} + +/******************************************************************************* +* Function Name : CAN_GetITStatus +* Description : Checks whether the CAN interrupt has occurred or not. +* Input : CAN_IT: specifies the CAN interrupt source to check. +* Output : None. +* Return : The new state of CAN_IT (SET or RESET). +*******************************************************************************/ +ITStatus CAN_GetITStatus(u32 CAN_IT) +{ + ITStatus pendingbitstatus = RESET; + + /* Check the parameters */ + assert(IS_CAN_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_RQCP0: + pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP0); + break; + case CAN_IT_RQCP1: + pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP1); + break; + case CAN_IT_RQCP2: + pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP2); + break; + case CAN_IT_FF0: + pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FF1: + pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_EWG: + pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_SLK: + pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_WKU: + pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI); + break; + + default : + pendingbitstatus = RESET; + break; + } + + /* Return the CAN_IT status */ + return pendingbitstatus; +} + +/******************************************************************************* +* Function Name : CAN_ClearITPendingBit +* Description : Clears the CANs interrupt pending bits. +* Input : CAN_IT: specifies the interrupt pending bit to clear. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_ClearITPendingBit(u32 CAN_IT) +{ + /* Check the parameters */ + assert(IS_CAN_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_RQCP0: + CAN->TSR = CAN_TSR_RQCP0; /* rc_w1*/ + break; + case CAN_IT_RQCP1: + CAN->TSR = CAN_TSR_RQCP1; /* rc_w1*/ + break; + case CAN_IT_RQCP2: + CAN->TSR = CAN_TSR_RQCP2; /* rc_w1*/ + break; + case CAN_IT_FF0: + CAN->RF0R = CAN_RF0R_FULL0; /* rc_w1*/ + break; + case CAN_IT_FOV0: + CAN->RF0R = CAN_RF0R_FOVR0; /* rc_w1*/ + break; + case CAN_IT_FF1: + CAN->RF1R = CAN_RF1R_FULL1; /* rc_w1*/ + break; + case CAN_IT_FOV1: + CAN->RF1R = CAN_RF1R_FOVR1; /* rc_w1*/ + break; + case CAN_IT_EWG: + CAN->ESR &= ~ CAN_ESR_EWGF; /* rw */ + break; + case CAN_IT_EPV: + CAN->ESR &= ~ CAN_ESR_EPVF; /* rw */ + break; + case CAN_IT_BOF: + CAN->ESR &= ~ CAN_ESR_BOFF; /* rw */ + break; + case CAN_IT_WKU: + CAN->MSR = CAN_MSR_WKUI; /* rc_w1*/ + break; + case CAN_IT_SLK: + CAN->MSR = CAN_MSR_SLAKI; /* rc_w1*/ + break; + default : + break; + } +} + +/******************************************************************************* +* Function Name : CheckITStatus +* Description : Checks whether the CAN interrupt has occurred or not. +* Input : CAN_Reg: specifies the CAN interrupt register to check. +* It_Bit: specifies the interrupt source bit to check. +* Output : None. +* Return : The new state of the CAN Interrupt (SET or RESET). +*******************************************************************************/ +static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (u32)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_crc.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_crc.c new file mode 100644 index 0000000..b0663fa --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_crc.c @@ -0,0 +1,164 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.c + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_crc.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @defgroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Defines + * @{ + */ + +/* CR register bit mask */ + +#define CR_RESET_Set ((uint32_t)0x00000001) + +/** + * @} + */ + +/** @defgroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval : None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CR_RESET_Set; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval : 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be + * computed + * @param BufferLength: length of the buffer to be computed + * @retval : 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval : 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval : None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval : 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dac.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dac.c new file mode 100644 index 0000000..4b196dc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dac.c @@ -0,0 +1,412 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.c + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file provides all the DAC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dac.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @defgroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Defines + * @{ + */ + +/* DAC EN mask */ +#define CR_EN_Set ((uint32_t)0x00000001) + +/* DAC DMAEN mask */ +#define CR_DMAEN_Set ((uint32_t)0x00001000) + +/* CR register Mask */ +#define CR_CLEAR_Mask ((uint32_t)0x00000FFE) + +/* DAC SWTRIG mask */ +#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_Set ((uint32_t)0x00000003) +#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_Offset ((uint32_t)0x00000008) +#define DHR12R2_Offset ((uint32_t)0x00000014) +#define DHR12RD_Offset ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_Offset ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default + * reset values. + * @param None + * @retval : None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that + * contains the configuration information for the specified + * DAC channel. + * @retval : None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave genration, + mask/amplitude for wave genration */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure + * which will be initialized. + * @retval : None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= CR_EN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= ~(CR_EN_Set << DAC_Channel); + } +} + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= CR_DMAEN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_Set ; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignement for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding + * register. + * @retval : None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + /* Set the DAC channel1 selected data holding register */ + *((__IO uint32_t *)(DAC_BASE + DHR12R1_Offset + DAC_Align)) = (uint32_t)Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignement for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding + * register. + * @retval : None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + /* Set the DAC channel2 selected data holding register */ + *((__IO uint32_t *)(DAC_BASE + DHR12R2_Offset + DAC_Align)) = (uint32_t)Data; +} + +/** + * @brief Set the specified data holding register value for dual channel + * DAC. + * @param DAC_Align: Specifies the data alignement for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data + * holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data + * holding register. + * @retval : None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0; + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + /* Set the dual DAC selected data holding register */ + *((__IO uint32_t *)(DAC_BASE + DHR12RD_Offset + DAC_Align)) = data; +} + +/** + * @brief Returns the last data output value of the selected DAC cahnnel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval : The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*)(DAC_BASE + DOR_Offset + ((uint32_t)DAC_Channel >> 2))); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dbgmcu.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dbgmcu.c new file mode 100644 index 0000000..d64262d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dbgmcu.c @@ -0,0 +1,152 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.c + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dbgmcu.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/** @defgroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval : Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval : Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_Mask); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBGMCU_Periph: specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN 1 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is + * halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is + * halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dma.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dma.c new file mode 100644 index 0000000..30239b7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dma.c @@ -0,0 +1,503 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_dma.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the DMA firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* DMA ENABLE mask */ +#define CCR_ENABLE_Set ((u32)0x00000001) +#define CCR_ENABLE_Reset ((u32)0xFFFFFFFE) + +/* DMA Channelx interrupt pending bit masks */ +#define DMA_Channel1_IT_Mask ((u32)0x0000000F) +#define DMA_Channel2_IT_Mask ((u32)0x000000F0) +#define DMA_Channel3_IT_Mask ((u32)0x00000F00) +#define DMA_Channel4_IT_Mask ((u32)0x0000F000) +#define DMA_Channel5_IT_Mask ((u32)0x000F0000) +#define DMA_Channel6_IT_Mask ((u32)0x00F00000) +#define DMA_Channel7_IT_Mask ((u32)0x0F000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((u32)0xFFFF800F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : DMA_DeInit +* Description : Deinitializes the DMA Channelx registers to their default reset +* values. +* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA +* Channel. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx) +{ + /* DMA Channelx disable */ + DMA_Cmd(DMA_Channelx, DISABLE); + + /* Reset Channelx control register */ + DMA_Channelx->CCR = 0; + + /* Reset Channelx remaining bytes register */ + DMA_Channelx->CNDTR = 0; + + /* Reset Channelx peripheral address register */ + DMA_Channelx->CPAR = 0; + + /* Reset Channelx memory address register */ + DMA_Channelx->CMAR = 0; + + switch (*(u32*)&DMA_Channelx) + { + case DMA_Channel1_BASE: + /* Reset interrupt pending bits for Channel1 */ + DMA->IFCR |= DMA_Channel1_IT_Mask; + break; + + case DMA_Channel2_BASE: + /* Reset interrupt pending bits for Channel2 */ + DMA->IFCR |= DMA_Channel2_IT_Mask; + break; + + case DMA_Channel3_BASE: + /* Reset interrupt pending bits for Channel3 */ + DMA->IFCR |= DMA_Channel3_IT_Mask; + break; + + case DMA_Channel4_BASE: + /* Reset interrupt pending bits for Channel4 */ + DMA->IFCR |= DMA_Channel4_IT_Mask; + break; + + case DMA_Channel5_BASE: + /* Reset interrupt pending bits for Channel5 */ + DMA->IFCR |= DMA_Channel5_IT_Mask; + break; + + case DMA_Channel6_BASE: + /* Reset interrupt pending bits for Channel6 */ + DMA->IFCR |= DMA_Channel6_IT_Mask; + break; + + case DMA_Channel7_BASE: + /* Reset interrupt pending bits for Channel7 */ + DMA->IFCR |= DMA_Channel7_IT_Mask; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : DMA_Init +* Description : Initializes the DMA Channelx according to the specified +* parameters in the DMA_InitStruct. +* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA +* Channel. +* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that +* contains the configuration information for the specified +* DMA Channel. +* Output : None +* Return : None +******************************************************************************/ +void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMA Channelx CCR Configuration -----------------*/ + /* Get the DMA_Channelx CCR value */ + tmpreg = DMA_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMA Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRCULAR bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + /* Write to DMA Channelx CCR */ + DMA_Channelx->CCR = tmpreg; + +/*--------------------------- DMA Channelx CNBTR Configuration ---------------*/ + /* Write to DMA Channelx CNBTR */ + DMA_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMA Channelx CPAR Configuration ----------------*/ + /* Write to DMA Channelx CPAR */ + DMA_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMA Channelx CMAR Configuration ----------------*/ + /* Write to DMA Channelx CMAR */ + DMA_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/******************************************************************************* +* Function Name : DMA_StructInit +* Description : Fills each DMA_InitStruct member with its default value. +* Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/******************************************************************************* +* Function Name : DMA_Cmd +* Description : Enables or disables the specified DMA Channel. +* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA +* Channel. +* - NewState: new state of the DMAx Channel. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Channelx */ + DMA_Channelx->CCR |= CCR_ENABLE_Set; + } + else + { + /* Disable the selected DMA Channelx */ + DMA_Channelx->CCR &= CCR_ENABLE_Reset; + } +} + +/******************************************************************************* +* Function Name : DMA_ITConfig +* Description : Enables or disables the specified DMA interrupts. +* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - DMA_IT_TC: Transfer complete interrupt mask +* - DMA_IT_HT: Half transfer interrupt mask +* - DMA_IT_TE: Transfer error interrupt mask +* - NewState: new state of the specified DMA interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_DMA_CONFIG_IT(DMA_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMA_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMA_Channelx->CCR &= ~DMA_IT; + } +} + +/******************************************************************************* +* Function Name : DMA_GetCurrDataCounter +* Description : Returns the number of remaining data units in the current +* DMA Channel transfer. +* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA +* Channel. +* Output : None +* Return : The number of remaining data units in the current DMA Channel +* transfer.. +*******************************************************************************/ +u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx) +{ + /* Return the current memory address value for Channelx */ + return ((u16)(DMA_Channelx->CNDTR)); +} + +/******************************************************************************* +* Function Name : DMA_GetFlagStatus +* Description : Checks whether the specified DMA flag is set or not. +* Input : - DMA_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - DMA_FLAG_GL1: Channel1 global flag. +* - DMA_FLAG_TC1: Channel1 transfer complete flag. +* - DMA_FLAG_HT1: Channel1 half transfer flag. +* - DMA_FLAG_TE1: Channel1 transfer error flag. +* - DMA_FLAG_GL2: Channel2 global flag. +* - DMA_FLAG_TC2: Channel2 transfer complete flag. +* - DMA_FLAG_HT2: Channel2 half transfer flag. +* - DMA_FLAG_TE2: Channel2 transfer error flag. +* - DMA_FLAG_GL3: Channel3 global flag. +* - DMA_FLAG_TC3: Channel3 transfer complete flag. +* - DMA_FLAG_HT3: Channel3 half transfer flag. +* - DMA_FLAG_TE3: Channel3 transfer error flag. +* - DMA_FLAG_GL4: Channel4 global flag. +* - DMA_FLAG_TC4: Channel4 transfer complete flag. +* - DMA_FLAG_HT4: Channel4 half transfer flag. +* - DMA_FLAG_TE4: Channel4 transfer error flag. +* - DMA_FLAG_GL5: Channel5 global flag. +* - DMA_FLAG_TC5: Channel5 transfer complete flag. +* - DMA_FLAG_HT5: Channel5 half transfer flag. +* - DMA_FLAG_TE5: Channel5 transfer error flag. +* - DMA_FLAG_GL6: Channel6 global flag. +* - DMA_FLAG_TC6: Channel6 transfer complete flag. +* - DMA_FLAG_HT6: Channel6 half transfer flag. +* - DMA_FLAG_TE6: Channel6 transfer error flag. +* - DMA_FLAG_GL7: Channel7 global flag. +* - DMA_FLAG_TC7: Channel7 transfer complete flag. +* - DMA_FLAG_HT7: Channel7 half transfer flag. +* - DMA_FLAG_TE7: Channel7 transfer error flag. +* Output : None +* Return : The new state of DMA_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Check the status of the specified DMA flag */ + if ((DMA->ISR & DMA_FLAG) != (u32)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : DMA_ClearFlag +* Description : Clears the DMA's pending flags. +* Input : - DMA_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - DMA_FLAG_GL1: Channel1 global flag. +* - DMA_FLAG_TC1: Channel1 transfer complete flag. +* - DMA_FLAG_HT1: Channel1 half transfer flag. +* - DMA_FLAG_TE1: Channel1 transfer error flag. +* - DMA_FLAG_GL2: Channel2 global flag. +* - DMA_FLAG_TC2: Channel2 transfer complete flag. +* - DMA_FLAG_HT2: Channel2 half transfer flag. +* - DMA_FLAG_TE2: Channel2 transfer error flag. +* - DMA_FLAG_GL3: Channel3 global flag. +* - DMA_FLAG_TC3: Channel3 transfer complete flag. +* - DMA_FLAG_HT3: Channel3 half transfer flag. +* - DMA_FLAG_TE3: Channel3 transfer error flag. +* - DMA_FLAG_GL4: Channel4 global flag. +* - DMA_FLAG_TC4: Channel4 transfer complete flag. +* - DMA_FLAG_HT4: Channel4 half transfer flag. +* - DMA_FLAG_TE4: Channel4 transfer error flag. +* - DMA_FLAG_GL5: Channel5 global flag. +* - DMA_FLAG_TC5: Channel5 transfer complete flag. +* - DMA_FLAG_HT5: Channel5 half transfer flag. +* - DMA_FLAG_TE5: Channel5 transfer error flag. +* - DMA_FLAG_GL6: Channel6 global flag. +* - DMA_FLAG_TC6: Channel6 transfer complete flag. +* - DMA_FLAG_HT6: Channel6 half transfer flag. +* - DMA_FLAG_TE6: Channel6 transfer error flag. +* - DMA_FLAG_GL7: Channel7 global flag. +* - DMA_FLAG_TC7: Channel7 transfer complete flag. +* - DMA_FLAG_HT7: Channel7 half transfer flag. +* - DMA_FLAG_TE7: Channel7 transfer error flag. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearFlag(u32 DMA_FLAG) +{ + /* Check the parameters */ + assert(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + + /* Clear the selected DMA flags */ + DMA->IFCR = DMA_FLAG; +} + +/******************************************************************************* +* Function Name : DMA_GetITStatus +* Description : Checks whether the specified DMA interrupt has occurred or not. +* Input : - DMA_IT: specifies the DMA interrupt source to check. +* This parameter can be one of the following values: +* - DMA_IT_GL1: Channel1 global interrupt. +* - DMA_IT_TC1: Channel1 transfer complete interrupt. +* - DMA_IT_HT1: Channel1 half transfer interrupt. +* - DMA_IT_TE1: Channel1 transfer error interrupt. +* - DMA_IT_GL2: Channel2 global interrupt. +* - DMA_IT_TC2: Channel2 transfer complete interrupt. +* - DMA_IT_HT2: Channel2 half transfer interrupt. +* - DMA_IT_TE2: Channel2 transfer error interrupt. +* - DMA_IT_GL3: Channel3 global interrupt. +* - DMA_IT_TC3: Channel3 transfer complete interrupt. +* - DMA_IT_HT3: Channel3 half transfer interrupt. +* - DMA_IT_TE3: Channel3 transfer error interrupt. +* - DMA_IT_GL4: Channel4 global interrupt. +* - DMA_IT_TC4: Channel4 transfer complete interrupt. +* - DMA_IT_HT4: Channel4 half transfer interrupt. +* - DMA_IT_TE4: Channel4 transfer error interrupt. +* - DMA_IT_GL5: Channel5 global interrupt. +* - DMA_IT_TC5: Channel5 transfer complete interrupt. +* - DMA_IT_HT5: Channel5 half transfer interrupt. +* - DMA_IT_TE5: Channel5 transfer error interrupt. +* - DMA_IT_GL6: Channel6 global interrupt. +* - DMA_IT_TC6: Channel6 transfer complete interrupt. +* - DMA_IT_HT6: Channel6 half transfer interrupt. +* - DMA_IT_TE6: Channel6 transfer error interrupt. +* - DMA_IT_GL7: Channel7 global interrupt. +* - DMA_IT_TC7: Channel7 transfer complete interrupt. +* - DMA_IT_HT7: Channel7 half transfer interrupt. +* - DMA_IT_TE7: Channel7 transfer error interrupt. +* Output : None +* Return : The new state of DMA_IT (SET or RESET). +*******************************************************************************/ +ITStatus DMA_GetITStatus(u32 DMA_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_DMA_GET_IT(DMA_IT)); + + /* Check the status of the specified DMA interrupt */ + if ((DMA->ISR & DMA_IT) != (u32)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : DMA_ClearITPendingBit +* Description : Clears the DMAs interrupt pending bits. +* Input : - DMA_IT: specifies the DMA interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - DMA_IT_GL1: Channel1 global interrupt. +* - DMA_IT_TC1: Channel1 transfer complete interrupt. +* - DMA_IT_HT1: Channel1 half transfer interrupt. +* - DMA_IT_TE1: Channel1 transfer error interrupt. +* - DMA_IT_GL2: Channel2 global interrupt. +* - DMA_IT_TC2: Channel2 transfer complete interrupt. +* - DMA_IT_HT2: Channel2 half transfer interrupt. +* - DMA_IT_TE2: Channel2 transfer error interrupt. +* - DMA_IT_GL3: Channel3 global interrupt. +* - DMA_IT_TC3: Channel3 transfer complete interrupt. +* - DMA_IT_HT3: Channel3 half transfer interrupt. +* - DMA_IT_TE3: Channel3 transfer error interrupt. +* - DMA_IT_GL4: Channel4 global interrupt. +* - DMA_IT_TC4: Channel4 transfer complete interrupt. +* - DMA_IT_HT4: Channel4 half transfer interrupt. +* - DMA_IT_TE4: Channel4 transfer error interrupt. +* - DMA_IT_GL5: Channel5 global interrupt. +* - DMA_IT_TC5: Channel5 transfer complete interrupt. +* - DMA_IT_HT5: Channel5 half transfer interrupt. +* - DMA_IT_TE5: Channel5 transfer error interrupt. +* - DMA_IT_GL6: Channel6 global interrupt. +* - DMA_IT_TC6: Channel6 transfer complete interrupt. +* - DMA_IT_HT6: Channel6 half transfer interrupt. +* - DMA_IT_TE6: Channel6 transfer error interrupt. +* - DMA_IT_GL7: Channel7 global interrupt. +* - DMA_IT_TC7: Channel7 transfer complete interrupt. +* - DMA_IT_HT7: Channel7 half transfer interrupt. +* - DMA_IT_TE7: Channel7 transfer error interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearITPendingBit(u32 DMA_IT) +{ + /* Check the parameters */ + assert(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Clear the selected DMA interrupt pending bits */ + DMA->IFCR = DMA_IT; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ + diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_exti.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_exti.c new file mode 100644 index 0000000..811d94b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_exti.c @@ -0,0 +1,219 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_exti.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the EXTI firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define EXTI_LineNone ((u32)0x00000) /* No interrupt selected */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : EXTI_DeInit +* Description : Deinitializes the EXTI peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x0007FFFF; +} + +/******************************************************************************* +* Function Name : EXTI_Init +* Description : Initializes the EXTI peripheral according to the specified +* parameters in the EXTI_InitStruct. +* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* that contains the configuration information for the EXTI +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + /* Check the parameters */ + assert(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)|= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Trigger)|= EXTI_InitStruct->EXTI_Line; + } + } + else + { + /* Disable the selected external lines */ + *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)&= ~EXTI_InitStruct->EXTI_Line; + } +} + +/******************************************************************************* +* Function Name : EXTI_StructInit +* Description : Fills each EXTI_InitStruct member with its reset value. +* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LineNone; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EXTI_GenerateSWInterrupt +* Description : Generates a Software interrupt. +* Input : - EXTI_Line: specifies the EXTI lines to be enabled or +* disabled. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_GenerateSWInterrupt(u32 EXTI_Line) +{ + /* Check the parameters */ + assert(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/******************************************************************************* +* Function Name : EXTI_GetFlagStatus +* Description : Checks whether the specified EXTI line flag is set or not. +* Input : - EXTI_Line: specifies the EXTI lines flag to check. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : The new state of EXTI_Line (SET or RESET). +*******************************************************************************/ +FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : EXTI_ClearFlag +* Description : Clears the EXTIs line pending flags. +* Input : - EXTI_Line: specifies the EXTI lines flags to clear. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_ClearFlag(u32 EXTI_Line) +{ + /* Check the parameters */ + assert(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/******************************************************************************* +* Function Name : EXTI_GetITStatus +* Description : Checks whether the specified EXTI line is asserted or not. +* Input : - EXTI_Line: specifies the EXTI lines to check. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : The new state of EXTI_Line (SET or RESET). +*******************************************************************************/ +ITStatus EXTI_GetITStatus(u32 EXTI_Line) +{ + ITStatus bitstatus = RESET; + u32 enablestatus = 0; + + /* Check the parameters */ + assert(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + + if (((EXTI->PR & EXTI_Line) != (u32)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : EXTI_ClearITPendingBit +* Description : Clears the EXTIs line pending bits. +* Input : - EXTI_Line: specifies the EXTI lines to clear. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_ClearITPendingBit(u32 EXTI_Line) +{ + /* Check the parameters */ + assert(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_flash.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_flash.c new file mode 100644 index 0000000..1d966e4 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_flash.c @@ -0,0 +1,881 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.c + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file provides all the FLASH firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_flash.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @defgroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0x00001FFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0x00001FFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0x00001FFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0x00001FDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x00000FFF) +#define ProgramTimeout ((uint32_t)0x0000000F) + +/** + * @} + */ + +/** @defgroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_FunctionPrototypes + * @{ + */ + +static void delay(void); +/** + * @} + */ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Sets the code latency value. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @retval : None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Half cycle flash access. + * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. + * This parameter can be one of the following values: + * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable + * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable + * @retval : None + */ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable + * @retval : None + */ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @param None + * @retval : None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/** + * @brief Locks the FLASH Program Erase Controller. + * @param None + * @retval : None + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the FCR */ + FLASH->CR |= CR_LOCK_Set; +} + +/** + * @brief Erases a specified FLASH page. + * @param Page_Address: The page address to be erased. + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_BUSY) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @param None + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_BUSY) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases the FLASH option bytes. + * @param None + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + /* Enable the readout access */ + OB->RDP= RDP_Key; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_BUSY) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + *(__IO uint16_t*)(Address + 2) = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_BUSY) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_BUSY) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @param FLASH_Pages: specifies the address of the pages to be + * write protected. This parameter can be: + * @arg For STM32F10Xxx Medium-density devices (FLASH page size equal to 1 KB) + * A value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages124to127 + * @arg For STM32F10Xxx High-density devices (FLASH page size equal to 2 KB) + * A value between FLASH_WRProt_Pages0to1 and FLASH_WRProt_Pages60to61 + * or FLASH_WRProt_Pages62to255 + * @arg FLASH_WRProt_AllPages + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * If the user has already programmed the other option bytes before + * calling this function, he must re-program them since this + * function erases all option bytes. + * @param Newstate: new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_BUSY) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / + * RST_STDBY. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = ( OB_IWDG | OB_STOP |OB_STDBY) | (uint16_t)0xF8; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_BUSY) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @param None + * @retval : The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OBR >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @param None + * @retval : The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Falsh write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set + * or not. + * @param None + * @retval : FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @param None + * @retval : FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @param FLASH_IT: specifies the FLASH interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @param NewState: new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag + * @retval : The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASHs pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @retval : None + */ +void FLASH_ClearFlag(uint16_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @param None + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if(FLASH->SR & FLASH_FLAG_PGERR) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if(FLASH->SR & FLASH_FLAG_WRPRTERR) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @param Timeout: FLASH progamming Timeout + * @retval : FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or + * FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetStatus(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + delay(); + status = FLASH_GetStatus(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @brief Inserts a time delay. + * @param None + * @retval : None + */ +static void delay(void) +{ + __IO uint32_t i = 0; + for(i = 0xFF; i != 0; i--) + { + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_fsmc.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_fsmc.c new file mode 100644 index 0000000..020711b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_fsmc.c @@ -0,0 +1,865 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.c + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file provides all the FSMC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/** @defgroup FSMC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup FSMC_Private_Defines + * @{ + */ + +/* --------------------- FSMC registers bit mask ---------------------------- */ + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FSMC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval : None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval : None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default + * reset values. + * @param None + * @retval : None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the + * specified parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for + * the FSMC NOR/SRAM specified Banks. + * @retval : None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for + * the FSMC NAND specified Banks. + * @retval : None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified + * parameters in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef + * structure that contains the configuration information for + * the FSMC PCCARD Bank. + * @retval : None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * @retval : None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * @retval : None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef + * structure which will be initialized. + * @retval : None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; + } + } +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; + } +} + +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval : The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval : The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMCs pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @retval : None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval : The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMCs interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval : None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_gpio.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_gpio.c new file mode 100644 index 0000000..571a00d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_gpio.c @@ -0,0 +1,515 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_gpio.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the GPIO firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register ---*/ +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((u8)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + +#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80) +#define LSB_MASK ((u16)0xFFFF) +#define DBGAFR_POSITION_MASK ((u32)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((u32)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((u32)0x00200000) +#define DBGAFR_NUMBITS_MASK ((u32)0x00100000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + switch (*(u32*)&GPIOx) + { + case GPIOA_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + break; + + case GPIOB_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + break; + + case GPIOC_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + break; + + case GPIOD_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + break; + + case GPIOE_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : GPIO_AFIODeInit +* Description : Deinitializes the Alternate Functions (remap, event control +* and EXTI configuration) registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + u32 tmpreg = 0x00, pinmask = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + +/*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F); + + if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00) + { + /* Check the parameters */ + assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (u32)GPIO_InitStruct->GPIO_Speed; + } + +/*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((u32)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((u32)0x0F) << pos; + tmpreg &= ~pinmask; + + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((u32)0x01) << pinpos); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((u32)0x01) << pinpos); + } + } + } + GPIOx->CRL = tmpreg; + tmpreg = 0; + } + +/*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((u32)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((u32)0x0F) << pos; + tmpreg &= ~pinmask; + + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Fills each GPIO_InitStruct member with its default value. +* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/******************************************************************************* +* Function Name : GPIO_ReadInputDataBit +* Description : Reads the specified input port pin. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* : - GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* Output : None +* Return : The input port pin value. +*******************************************************************************/ +u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + u8 bitstatus = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET) + { + bitstatus = (u8)Bit_SET; + } + else + { + bitstatus = (u8)Bit_RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : GPIO_ReadInputData +* Description : Reads the specified GPIO input data port. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* Output : None +* Return : GPIO input data port value. +*******************************************************************************/ +u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + return ((u16)GPIOx->IDR); +} + +/******************************************************************************* +* Function Name : GPIO_ReadOutputDataBit +* Description : Reads the specified output data port bit. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* : - GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* Output : None +* Return : The output port pin value. +*******************************************************************************/ +u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + u8 bitstatus = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET) + { + bitstatus = (u8)Bit_SET; + } + else + { + bitstatus = (u8)Bit_RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : GPIO_ReadOutputData +* Description : Reads the specified GPIO output data port. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* Output : None +* Return : GPIO output data port value. +*******************************************************************************/ +u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + return ((u16)GPIOx->ODR); +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be written. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* - BitVal: specifies the value to be written to the selected bit. +* This parameter can be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert(IS_GPIO_PIN(GPIO_Pin)); + assert(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes data to the specified GPIO data port. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* - PortVal: specifies the value to be written to the port output +* data register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal) +{ + GPIOx->ODR = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_PinLockConfig +* Description : Locks GPIO Pins configuration registers. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be written. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + u32 tmp = 0x00010000; + + /* Check the parameters */ + assert(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/******************************************************************************* +* Function Name : GPIO_EventOutputConfig +* Description : Selects the GPIO pin used as Event output. +* Input : - GPIO_PortSource: selects the GPIO port to be used as source +* for Event output. +* This parameter can be GPIO_PortSourceGPIOx where x can be +* (A..E). +* - GPIO_PinSource: specifies the pin for the Event output. +* This parameter can be GPIO_PinSourcex where x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource) +{ + u32 tmpreg = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource)); + assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (u32)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + + AFIO->EVCR = tmpreg; +} + +/******************************************************************************* +* Function Name : GPIO_EventOutputCmd +* Description : Enables or disables the Event Output. +* Input : - NewState: new state of the Event output. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) EVCR_EVOE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : GPIO_PinRemapConfig +* Description : Changes the mapping of the specified pin. +* Input : - GPIO_Remap: selects the pin to remap. +* This parameter can be one of the following values: +* - GPIO_Remap_SPI1 +* - GPIO_Remap_I2C1 +* - GPIO_Remap_USART1 +* - GPIO_Remap_USART2 +* - GPIO_PartialRemap_USART3 +* - GPIO_FullRemap_USART3 +* - GPIO_PartialRemap_TIM1 +* - GPIO_FullRemap_TIM1 +* - GPIO_PartialRemap1_TIM2 +* - GPIO_PartialRemap2_TIM2 +* - GPIO_FullRemap_TIM2 +* - GPIO_PartialRemap_TIM3 +* - GPIO_FullRemap_TIM3 +* - GPIO_Remap_TIM4 +* - GPIO_Remap1_CAN +* - GPIO_Remap2_CAN +* - GPIO_Remap_PD01 +* - GPIO_Remap_SWJ_NoJTRST +* - GPIO_Remap_SWJ_JTAGDisable +* - GPIO_Remap_SWJ_Disable +* - NewState: new state of the port pin remapping. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState) +{ + u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_REMAP(GPIO_Remap)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + tmpreg = AFIO->MAPR; + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((u32)0x03) << tmpmask; + tmpreg &= ~tmp1; + } + else + { + tmpreg &= ~tmp; + } + + if (NewState != DISABLE) + { + if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK) + { + tmpreg |= (tmp << 0x10); + } + else + { + tmpreg |= tmp; + } + } + AFIO->MAPR = tmpreg; +} + +/******************************************************************************* +* Function Name : GPIO_EXTILineConfig +* Description : Selects the GPIO pin used as EXTI Line. +* Input : - GPIO_PortSource: selects the GPIO port to be used as +* source for EXTI lines. +* - GPIO_PinSource: specifies the EXTI line to be configured. +* This parameter can be GPIO_PinSourcex where x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource)); + assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03)); + + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03))); +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_i2c.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_i2c.c new file mode 100644 index 0000000..2809b83 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_i2c.c @@ -0,0 +1,1186 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_i2c.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the I2C firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* I2C SPE mask */ +#define CR1_PE_Set ((u16)0x0001) +#define CR1_PE_Reset ((u16)0xFFFE) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((u16)0x0800) +#define CR2_DMAEN_Reset ((u16)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((u16)0x1000) +#define CR2_LAST_Reset ((u16)0xEFFF) + +/* I2C START mask */ +#define CR1_START_Set ((u16)0x0100) +#define CR1_START_Reset ((u16)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((u16)0x0200) +#define CR1_STOP_Reset ((u16)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((u16)0x0400) +#define CR1_ACK_Reset ((u16)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((u16)0x0040) +#define CR1_ENGC_Reset ((u16)0xFFBF) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((u16)0x0001) +#define OAR1_ADD0_Reset ((u16)0xFFFE) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((u16)0x8000) +#define CR1_SWRST_Reset ((u16)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((u16)0x1000) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((u16)0x0020) +#define CR1_ENPEC_Reset ((u16)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((u16)0x0010) +#define CR1_ENARP_Reset ((u16)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((u16)0x0080) +#define CR1_NOSTRETCH_Reset ((u16)0xFF7F) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((u16)0x0001) +#define OAR2_ENDUAL_Reset ((u16)0xFFFE) + +/* I2C F/S mask */ +#define CCR_FS_Set ((u16)0x8000) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((u16)0xFF01) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((u16)0xFFC0) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((u16)0x0FFF) + +/* I2C FLAG mask */ +#define I2C_FLAG_Mask ((u32)0x00FFFFFF) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((u16)0xFBF5) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : I2C_DeInit +* Description : Deinitializes the I2Cx peripheral registers to their default +* reset values. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + switch (*(u32*)&I2Cx) + { + case I2C1_BASE: + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + break; + + case I2C2_BASE: + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : I2C_Init +* Description : Initializes the I2Cx according to the specified parameters +* in the I2C_InitStruct. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that +* contains the configuration information for the specified +* I2C peripheral. +* Output : None +* Return : None +******************************************************************************/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u16 tmpreg = 0, freqrange = 0; + u16 result = 0x04; + u32 pclk1clock = 12000000; + RCC_ClocksTypeDef RCC_Clocks; + + /* Check the parameters */ + assert(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + assert(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get PCLK1Clock frequency value */ + RCC_GetClocksFreq(&RCC_Clocks); + pclk1clock = RCC_Clocks.PCLK1_Frequency; + /* Set frequency bits depending on PCLK1Clock value */ + freqrange = (u16)(pclk1clock / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable I2Cx to configure TRISE */ + I2C_Cmd(I2Cx, DISABLE); + + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time: ((1000/(1000000000/pclk1clock))+1 */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (u16)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= result | CCR_FS_Set; + /* Set Maximum Rise Time: ((300/(1000000000/pclk1clock))+1 */ + I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1); + } + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + + /* Enable I2Cx */ + I2C_Cmd(I2Cx, ENABLE); + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/******************************************************************************* +* Function Name : I2C_StructInit +* Description : Fills each I2C_InitStruct member with its default value. +* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; +} + +/******************************************************************************* +* Function Name : I2C_Cmd +* Description : Enables or disables the specified I2C peripheral. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_DMACmd +* Description : Enables or disables the specified I2C DMA requests. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_DMALastTransferCmd +* Description : Specifies that the next DMA transfer is the last one. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C DMA last transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Next DMA end of transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA end of transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTART +* Description : Generates I2Cx communication START condition. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C START condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTOP +* Description : Generates I2Cx communication STOP condition. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C STOP condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_AcknowledgeConfig +* Description : Enables or disables the specified I2C acknowledge feature. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C Acknowledgement. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_OwnAddress2Config +* Description : Configures the specified I2C own address2. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - Address: specifies the 7bit I2C own address2. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address) +{ + u16 tmpreg = 0; + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + /* Set I2Cx Own address2 */ + tmpreg |= (u16)(Address & (u16)0x00FE); + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/******************************************************************************* +* Function Name : I2C_DualAddressCmd +* Description : Enables or disables the specified I2C dual addressing mode. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C dual addressing mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GeneralCallCmd +* Description : Enables or disables the specified I2C general call feature. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C General call. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_ITConfig +* Description : Enables or disables the specified I2C interrupts. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_IT: specifies the I2C interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - I2C_IT_BUF: Buffer interrupt mask +* - I2C_IT_EVT: Event interrupt mask +* - I2C_IT_ERR: Error interrupt mask +* - NewState: new state of the specified I2C interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + assert(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (u16)~I2C_IT; + } +} + +/******************************************************************************* +* Function Name : I2C_SendData +* Description : Sends a data byte through the I2Cx peripheral. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - Data: Byte to be transmitted.. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data) +{ + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/******************************************************************************* +* Function Name : I2C_ReceiveData +* Description : Returns the most recent received data by the I2Cx peripheral. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Return the data in the DR register */ + return (u8)I2Cx->DR; +} + +/******************************************************************************* +* Function Name : I2C_Send7bitAddress +* Description : Transmits the address byte to select the slave device. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - Address: specifies the slave address which will be transmitted +* - Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. +* This parameter can be one of the following values +* - I2C_Direction_Transmitter: Transmitter mode +* - I2C_Direction_Receiver: Receiver mode +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction) +{ + /* Check the parameters */ + assert(IS_I2C_DIRECTION(I2C_Direction)); + + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address ADD0 bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/******************************************************************************* +* Function Name : I2C_ReadRegister +* Description : Reads the specified I2C register and returns its value. +* Input1 : - I2C_Register: specifies the register to read. +* This parameter can be one of the following values: +* - I2C_Register_CR1: CR1 register. +* - I2C_Register_CR2: CR2 register. +* - I2C_Register_OAR1: OAR1 register. +* - I2C_Register_OAR2: OAR2 register. +* - I2C_Register_DR: DR register. +* - I2C_Register_SR1: SR1 register. +* - I2C_Register_SR2: SR2 register. +* - I2C_Register_CCR: CCR register. +* - I2C_Register_TRISE: TRISE register. +* Output : None +* Return : The value of the read register. +*******************************************************************************/ +u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + /* Check the parameters */ + assert(IS_I2C_REGISTER(I2C_Register)); + + /* Return the selected register value */ + return (*(u16 *)(*((u32 *)&I2Cx) + I2C_Register)); +} + +/******************************************************************************* +* Function Name : I2C_SoftwareResetCmd +* Description : Enables or disables the specified I2C software reset. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C software reset. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_SMBusAlertConfig +* Description : Drives the SMBusAlert pin high or low for the specified I2C. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_SMBusAlert: specifies SMBAlert pin level. +* This parameter can be one of the following values: +* - I2C_SMBusAlert_Low: SMBAlert pin driven low +* - I2C_SMBusAlert_High: SMBAlert pin driven high +* Output : None +* Return : None +*******************************************************************************/ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert) +{ + /* Check the parameters */ + assert(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/******************************************************************************* +* Function Name : I2C_TransmitPEC +* Description : Enables the specified I2C PEC transfer. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx) +{ + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; +} + +/******************************************************************************* +* Function Name : I2C_PECPositionConfig +* Description : Selects the specified I2C PEC position. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_PECPosition: specifies the PEC position. +* This parameter can be one of the following values: +* - I2C_PECPosition_Next: PEC bit indicates that current +* byte is PEC +* - I2C_PECPosition_Current: PEC bit indicates that the +* next byte is PEC +* Output : None +* Return : None +*******************************************************************************/ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition) +{ + /* Check the parameters */ + assert(IS_I2C_PEC_POSITION(I2C_PECPosition)); + + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* PEC indicates that the next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* PEC indicates that the current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/******************************************************************************* +* Function Name : I2C_CalculatePEC +* Description : Enables or disables the PEC value calculation of the +* transfered bytes. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx PEC value calculation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GetPEC +* Description : Returns the PEC value for the specified I2C. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : The PEC value. +*******************************************************************************/ +u8 I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + u8 pec; + + /* Get the PEC value */ + pec = (I2Cx->SR2) >> 8; + /* Return the selected I2C PEC register value */ + return pec; +} + +/******************************************************************************* +* Function Name : I2C_ARPCmd +* Description : Enables or disables the specified I2C ARP. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx ARP. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_StretchClockCmd +* Description : Enables or disables the specified I2C Clock stretching. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx Clock stretching. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_FastModeDutyCycleConfig +* Description : Selects the specified I2C fast mode duty cycle. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_DutyCycle: specifies the fast mode duty cycle. +* This parameter can be one of the following values: +* - I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 +* - I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 +* Output : None +* Return : None +*******************************************************************************/ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle) +{ + /* Check the parameters */ + assert(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + +/******************************************************************************* +* Function Name : I2C_GetLastEvent +* Description : Returns the Last I2C Event. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : The last event +*******************************************************************************/ +u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + u32 LastEvent = 0; + u32 Flag1 = 0, Flag2 = 0; + + Flag1 = I2Cx->SR1; + Flag2 = I2Cx->SR2; + Flag2 = Flag2 << 16; + + /* Get the last event value from I2C status register */ + LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask; + + /* Return status */ + return LastEvent; +} + +/******************************************************************************* +* Function Name : I2C_CheckEvent +* Description : Checks whether the Last I2C Event is equal to the one passed +* as parameter. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_EVENT: specifies the event to be checked. +* This parameter can be one of the following values: +* - I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1 +* - I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 +* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 +* - I2C_EVENT_SLAVE_ACK_FAILURE : EV3-1 +* - I2C_EVENT_MASTER_MODE_SELECT : EV5 +* - I2C_EVENT_MASTER_MODE_SELECTED : EV6 +* - I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 +* - I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8 +* - I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 +* - I2C_EVENT_SLAVE_STOP_DETECTED : EV4 +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Last event is equal to the I2C_Event +* - ERROR: Last event is different from the I2C_Event +*******************************************************************************/ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT) +{ + u32 LastEvent = 0; + u32 Flag1 = 0, Flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert(IS_I2C_EVENT(I2C_EVENT)); + + Flag1 = I2Cx->SR1; + Flag2 = I2Cx->SR2; + Flag2 = Flag2 << 16; + + /* Get the last event value from I2C status register */ + LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask; + + /* Check whether the last event is equal to I2C_EVENT */ + if (LastEvent == I2C_EVENT ) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + + /* Return status */ + return status; +} + +/******************************************************************************* +* Function Name : I2C_GetFlagStatus +* Description : Checks whether the specified I2C flag is set or not. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - I2C_FLAG_DUALF: Dual flag (Slave mode) +* - I2C_FLAG_SMBHOST: SMBus host header (Slave mode) +* - I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) +* - I2C_FLAG_GENCALL: General call header flag (Slave mode) +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_MSL: Master/Slave flag +* - I2C_FLAG_SMBALERT: SMBus Alert flag +* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag +* - I2C_FLAG_PECERR: PEC error in reception flag +* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode) +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_TXE: Data register empty flag (Transmitter) +* - I2C_FLAG_RXNE: Data register not empty (Receiver) flag +* - I2C_FLAG_STOPF: Stop detection flag (Slave mode) +* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_ADDR: Address sent flag (Master mode) ADSL +* Address matched flag (Slave mode)ENDAD +* - I2C_FLAG_SB: Start bit flag (Master mode) +* Output : None +* Return : The new state of I2C_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + u32 i2cstatus = 0; + u32 Flag1 = 0, Flag2 = 0; + + /* Check the parameters */ + assert(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Read the I2Cx status register */ + Flag1 = I2Cx->SR1; + Flag2 = I2Cx->SR2; + Flag2 = (Flag2 & I2C_FLAG_Mask) << 16; + + /* Get the I2C status value */ + i2cstatus = Flag1 | Flag2; + + /* Get bit[27:0] of the flag */ + I2C_FLAG &= I2C_FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if ((i2cstatus & I2C_FLAG) != (u32)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : I2C_ClearFlag +* Description : Clears the I2Cx's pending flags. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - I2C_FLAG_SMBALERT: SMBus Alert flag +* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag +* - I2C_FLAG_PECERR: PEC error in reception flag +* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode) +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_STOPF: Stop detection flag (Slave mode) +* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_ADDR: Address sent flag (Master mode) ADSL +* Address matched flag (Slave mode)ENDAD +* - I2C_FLAG_SB: Start bit flag (Master mode) +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG) +{ + u32 flagpos = 0; + u8 flagindex = 0; + + /* Check the parameters */ + assert(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + + /* Get the I2C flag position */ + flagpos = I2C_FLAG & I2C_FLAG_Mask; + + /* Get the I2C flag index */ + flagindex = I2C_FLAG >> 28; + + /* Clear the flag by writing 0 */ + if (flagindex == 1) + { + /* Clear the selected I2C flag */ + I2Cx->SR1 &= ~flagpos; + } + /* Flags that need a read of the SR1 register to be cleared */ + else if (flagindex == 2) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + } + /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */ + else if (flagindex == 6) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* Write on the CR1 register */ + I2Cx->CR1 |= CR1_PE_Set; + } + /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */ + else /*flagindex == 0xA*/ + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* Read the SR2 register */ + (void)I2Cx->SR2; + } +} + +/******************************************************************************* +* Function Name : I2C_GetITStatus +* Description : Checks whether the specified I2C interrupt has occurred or not. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - I2C_IT_SMBALERT: SMBus Alert flag +* - I2C_IT_TIMEOUT: Timeout or Tlow error flag +* - I2C_IT_PECERR: PEC error in reception flag +* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_IT_AF: Acknowledge failure flag +* - I2C_IT_ARLO: Arbitration lost flag (Master mode) +* - I2C_IT_BERR: Bus error flag +* - I2C_IT_TXE: Data register empty flag (Transmitter) +* - I2C_IT_RXNE: Data register not empty (Receiver) flag +* - I2C_IT_STOPF: Stop detection flag (Slave mode) +* - I2C_IT_ADD10: 10-bit header sent flag (Master mode) +* - I2C_IT_BTF: Byte transfer finished flag +* - I2C_IT_ADDR: Address sent flag (Master mode) ADSL +* Address matched flag (Slave mode)ENDAD +* - I2C_IT_SB: Start bit flag (Master mode) +* Output : None +* Return : The new state of I2C_IT (SET or RESET). +*******************************************************************************/ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT) +{ + ITStatus bitstatus = RESET; + u32 i2cstatus = 0; + u32 Flag1 = 0, Flag2 = 0; + + /* Check the parameters */ + assert(IS_I2C_GET_IT(I2C_IT)); + + /* Read the I2Cx status register */ + Flag1 = I2Cx->SR1; + Flag2 = I2Cx->SR2; + Flag2 = (Flag2 & I2C_FLAG_Mask) << 16; + + /* Get the I2C status value */ + i2cstatus = Flag1 | Flag2; + + /* Get bit[27:0] of the flag */ + I2C_IT &= I2C_FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if ((i2cstatus & I2C_IT) != (u32)RESET) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : I2C_ClearITPendingBit +* Description : Clears the I2Cxs interrupt pending bits. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_IT: specifies the interrupt pending to clear. +* This parameter can be one of the following values: +* - I2C_IT_SMBALERT: SMBus Alert flag +* - I2C_IT_TIMEOUT: Timeout or Tlow error flag +* - I2C_IT_PECERR: PEC error in reception flag +* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_IT_AF: Acknowledge failure flag +* - I2C_IT_ARLO: Arbitration lost flag (Master mode) +* - I2C_IT_BERR: Bus error flag +* - I2C_IT_STOPF: Stop detection flag (Slave mode) +* - I2C_IT_ADD10: 10-bit header sent flag (Master mode) +* - I2C_IT_BTF: Byte transfer finished flag +* - I2C_IT_ADDR: Address sent flag (Master mode) ADSL +* Address matched flag (Slave mode)ENDAD +* - I2C_IT_SB: Start bit flag (Master mode) +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT) +{ + u32 flagpos = 0; + u8 flagindex = 0; + + /* Check the parameters */ + assert(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Get the I2C flag position */ + flagpos = I2C_IT & I2C_FLAG_Mask; + + /* Get the I2C flag index */ + flagindex = I2C_IT >> 28; + + /* Clear the flag by writing 0 */ + if (flagindex == 1) + { + /* Clear the selected I2C flag */ + I2Cx->SR1 &= ~flagpos; + } + /* Flags that need a read of the SR1 register to be cleared */ + else if (flagindex == 2) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + } + /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */ + else if (flagindex == 6) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* Write on the CR1 register */ + I2Cx->CR1 |= CR1_PE_Set; + } + /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */ + else /*flagindex == 0xA*/ + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* Read the SR2 register */ + (void)I2Cx->SR2; + } +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_iwdg.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_iwdg.c new file mode 100644 index 0000000..496e68d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_iwdg.c @@ -0,0 +1,152 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_iwdg.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the IWDG firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- IWDG registers bit mask ------------------------ */ +/* KR register bit mask */ +#define KR_Reload ((u16)0xAAAA) +#define KR_Enable ((u16)0xCCCC) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : IWDG_WriteAccessCmd +* Description : Enables or disables write access to IWDG_PR and IWDG_RLR +* registers. +* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and +* IWDG_RLR registers. +* This parameter can be one of the following values: +* - IWDG_WriteAccess_Enable: Enable write access to +* IWDG_PR and IWDG_RLR registers +* - IWDG_WriteAccess_Disable: Disable write access to +* IWDG_PR and IWDG_RLR registers +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess) +{ + /* Check the parameters */ + assert(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + + IWDG->KR = IWDG_WriteAccess; +} + +/******************************************************************************* +* Function Name : IWDG_SetPrescaler +* Description : Sets IWDG Prescaler value. +* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value. +* This parameter can be one of the following values: +* - IWDG_Prescaler_4: IWDG prescaler set to 4 +* - IWDG_Prescaler_8: IWDG prescaler set to 8 +* - IWDG_Prescaler_16: IWDG prescaler set to 16 +* - IWDG_Prescaler_32: IWDG prescaler set to 32 +* - IWDG_Prescaler_64: IWDG prescaler set to 64 +* - IWDG_Prescaler_128: IWDG prescaler set to 128 +* - IWDG_Prescaler_256: IWDG prescaler set to 256 +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_SetPrescaler(u8 IWDG_Prescaler) +{ + /* Check the parameters */ + assert(IS_IWDG_PRESCALER(IWDG_Prescaler)); + + IWDG->PR = IWDG_Prescaler; +} + +/******************************************************************************* +* Function Name : IWDG_SetReload +* Description : Sets IWDG Reload value. +* Input : - Reload: specifies the IWDG Reload value. +* This parameter must be a number between 0 and 0x0FFF. +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_SetReload(u16 Reload) +{ + /* Check the parameters */ + assert(IS_IWDG_RELOAD(Reload)); + + IWDG->RLR = Reload; +} + +/******************************************************************************* +* Function Name : IWDG_ReloadCounter +* Description : Reloads IWDG counter with value defined in the reload register +* (write access to IWDG_PR and IWDG_RLR registers disabled). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_Reload; +} + +/******************************************************************************* +* Function Name : IWDG_Enable +* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers +* disabled). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_Enable(void) +{ + IWDG->KR = KR_Enable; +} + +/******************************************************************************* +* Function Name : IWDG_GetFlagStatus +* Description : Checks whether the specified IWDG flag is set or not. +* Input : - IWDG_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - IWDG_FLAG_PVU: Prescaler Value Update on going +* - IWDG_FLAG_RVU: Reload Value Update on going +* Output : None +* Return : The new state of IWDG_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_IWDG_FLAG(IWDG_FLAG)); + + if ((IWDG->SR & IWDG_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_lib.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_lib.c new file mode 100644 index 0000000..7df2cb8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_lib.c @@ -0,0 +1,221 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_lib.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all peripherals pointers initialization. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#define EXT + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +#ifdef DEBUG +/******************************************************************************* +* Function Name : debug +* Description : This function initialize peripherals pointers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void debug(void) +{ + +/************************************* ADC ************************************/ +#ifdef _ADC1 + ADC1 = (ADC_TypeDef *) ADC1_BASE; +#endif /*_ADC1 */ + +#ifdef _ADC2 + ADC2 = (ADC_TypeDef *) ADC2_BASE; +#endif /*_ADC2 */ + +/************************************* BKP ************************************/ +#ifdef _BKP + BKP = (BKP_TypeDef *) BKP_BASE; +#endif /*_BKP */ + +/************************************* CAN ************************************/ +#ifdef _CAN + CAN = (CAN_TypeDef *) CAN_BASE; +#endif /*_CAN */ + +/************************************* DMA ************************************/ +#ifdef _DMA + DMA = (DMA_TypeDef *) DMA_BASE; +#endif /*_DMA */ + +#ifdef _DMA_Channel1 + DMA_Channel1 = (DMA_Channel_TypeDef *) DMA_Channel1_BASE; +#endif /*_DMA_Channel1 */ + +#ifdef _DMA_Channel2 + DMA_Channel2 = (DMA_Channel_TypeDef *) DMA_Channel2_BASE; +#endif /*_DMA_Channel2 */ + +#ifdef _DMA_Channel3 + DMA_Channel3 = (DMA_Channel_TypeDef *) DMA_Channel3_BASE; +#endif /*_DMA_Channel3 */ + +#ifdef _DMA_Channel4 + DMA_Channel4 = (DMA_Channel_TypeDef *) DMA_Channel4_BASE; +#endif /*_DMA_Channel4 */ + +#ifdef _DMA_Channel5 + DMA_Channel5 = (DMA_Channel_TypeDef *) DMA_Channel5_BASE; +#endif /*_DMA_Channel5 */ + +#ifdef _DMA_Channel6 + DMA_Channel6 = (DMA_Channel_TypeDef *) DMA_Channel6_BASE; +#endif /*_DMA_Channel6 */ + +#ifdef _DMA_Channel7 + DMA_Channel7 = (DMA_Channel_TypeDef *) DMA_Channel7_BASE; +#endif /*_DMA_Channel7 */ + +/************************************* EXTI ***********************************/ +#ifdef _EXTI + EXTI = (EXTI_TypeDef *) EXTI_BASE; +#endif /*_EXTI */ + +/************************************* FLASH and Option Bytes *****************/ +#ifdef _FLASH + FLASH = (FLASH_TypeDef *) FLASH_BASE; + OB = (OB_TypeDef *) OB_BASE; +#endif /*_FLASH */ + +/************************************* GPIO ***********************************/ +#ifdef _GPIOA + GPIOA = (GPIO_TypeDef *) GPIOA_BASE; +#endif /*_GPIOA */ + +#ifdef _GPIOB + GPIOB = (GPIO_TypeDef *) GPIOB_BASE; +#endif /*_GPIOB */ + +#ifdef _GPIOC + GPIOC = (GPIO_TypeDef *) GPIOC_BASE; +#endif /*_GPIOC */ + +#ifdef _GPIOD + GPIOD = (GPIO_TypeDef *) GPIOD_BASE; +#endif /*_GPIOD */ + +#ifdef _GPIOE + GPIOE = (GPIO_TypeDef *) GPIOE_BASE; +#endif /*_GPIOE */ + +#ifdef _AFIO + AFIO = (AFIO_TypeDef *) AFIO_BASE; +#endif /*_AFIO */ + +/************************************* I2C ************************************/ +#ifdef _I2C1 + I2C1 = (I2C_TypeDef *) I2C1_BASE; +#endif /*_I2C1 */ + +#ifdef _I2C2 + I2C2 = (I2C_TypeDef *) I2C2_BASE; +#endif /*_I2C2 */ + +/************************************* IWDG ***********************************/ +#ifdef _IWDG + IWDG = (IWDG_TypeDef *) IWDG_BASE; +#endif /*_IWDG */ + +/************************************* NVIC ***********************************/ +#ifdef _NVIC + NVIC = (NVIC_TypeDef *) NVIC_BASE; +#endif /*_NVIC */ + +#ifdef _SCB + SCB = (SCB_TypeDef *) SCB_BASE; +#endif /*_SCB */ + +/************************************* PWR ************************************/ +#ifdef _PWR + PWR = (PWR_TypeDef *) PWR_BASE; +#endif /*_PWR */ + +/************************************* RCC ************************************/ +#ifdef _RCC + RCC = (RCC_TypeDef *) RCC_BASE; +#endif /*_RCC */ + +/************************************* RTC ************************************/ +#ifdef _RTC + RTC = (RTC_TypeDef *) RTC_BASE; +#endif /*_RTC */ + +/************************************* SPI ************************************/ +#ifdef _SPI1 + SPI1 = (SPI_TypeDef *) SPI1_BASE; +#endif /*_SPI1 */ + +#ifdef _SPI2 + SPI2 = (SPI_TypeDef *) SPI2_BASE; +#endif /*_SPI2 */ + +/************************************* SysTick ********************************/ +#ifdef _SysTick + SysTick = (SysTick_TypeDef *) SysTick_BASE; +#endif /*_SysTick */ + +/************************************* TIM1 ***********************************/ +#ifdef _TIM1 + TIM1 = (TIM1_TypeDef *) TIM1_BASE; +#endif /*_TIM1 */ + +/************************************* TIM ************************************/ +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *) TIM2_BASE; +#endif /*_TIM2 */ + +#ifdef _TIM3 + TIM3 = (TIM_TypeDef *) TIM3_BASE; +#endif /*_TIM3 */ + +#ifdef _TIM4 + TIM4 = (TIM_TypeDef *) TIM4_BASE; +#endif /*_TIM4 */ + +/************************************* USART **********************************/ +#ifdef _USART1 + USART1 = (USART_TypeDef *) USART1_BASE; +#endif /*_USART1 */ + +#ifdef _USART2 + USART2 = (USART_TypeDef *) USART2_BASE; +#endif /*_USART2 */ + +#ifdef _USART3 + USART3 = (USART_TypeDef *) USART3_BASE; +#endif /*_USART3 */ + +/************************************* WWDG ***********************************/ +#ifdef _WWDG + WWDG = (WWDG_TypeDef *) WWDG_BASE; +#endif /*_WWDG */ +} +#endif + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_nvic.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_nvic.c new file mode 100644 index 0000000..79bb867 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_nvic.c @@ -0,0 +1,755 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the NVIC firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_nvic.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRC_VECTKEY_MASK ((u32)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : NVIC_DeInit +* Description : Deinitializes the NVIC peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_DeInit(void) +{ + u32 index = 0; + + NVIC->Disable[0] = 0xFFFFFFFF; + NVIC->Disable[1] = 0x000007FF; + NVIC->Clear[0] = 0xFFFFFFFF; + NVIC->Clear[1] = 0x000007FF; + + for(index = 0; index < 0x0B; index++) + { + NVIC->Priority[index] = 0x00000000; + } +} + +/******************************************************************************* +* Function Name : NVIC_SCBDeInit +* Description : Deinitializes the SCB peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SCBDeInit(void) +{ + u32 index = 0x00; + + SCB->IRQControlState = 0x0A000000; + SCB->ExceptionTableOffset = 0x00000000; + SCB->AIRC = AIRC_VECTKEY_MASK; + SCB->SysCtrl = 0x00000000; + SCB->ConfigCtrl = 0x00000000; + for(index = 0; index < 0x03; index++) + { + SCB->SystemPriority[index] = 0; + } + SCB->SysHandlerCtrl = 0x00000000; + SCB->ConfigFaultStatus = 0xFFFFFFFF; + SCB->HardFaultStatus = 0xFFFFFFFF; + SCB->DebugFaultStatus = 0xFFFFFFFF; +} + +/******************************************************************************* +* Function Name : NVIC_PriorityGroupConfig +* Description : Configures the priority grouping: pre-emption priority +* and subpriority. +* Input : - NVIC_PriorityGroup: specifies the priority grouping bits +* length. This parameter can be one of the following values: +* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority +* 4 bits for subpriority +* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority +* 3 bits for subpriority +* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority +* 2 bits for subpriority +* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority +* 1 bits for subpriority +* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority +* 0 bits for subpriority +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRC = AIRC_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/******************************************************************************* +* Function Name : NVIC_Init +* Description : Initializes the NVIC peripheral according to the specified +* parameters in the NVIC_InitStruct. +* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure +* that contains the configuration information for the +* specified NVIC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00; + u32 tmppre = 0, tmpsub = 0x0F; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel)); + assert(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + + tmppriority = tmppriority << 0x04; + tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08); + + tmpreg = NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)]; + tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08); + tmpreg &= ~tmpmask; + tmppriority &= tmpmask; + tmpreg |= tmppriority; + + NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->Enable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] = + (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->Disable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] = + (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F); + } +} + +/******************************************************************************* +* Function Name : NVIC_StructInit +* Description : Fills each NVIC_InitStruct member with its default value. +* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct) +{ + /* NVIC_InitStruct members default value */ + NVIC_InitStruct->NVIC_IRQChannel = 0x00; + NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00; + NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00; + NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : NVIC_SETPRIMASK +* Description : Enables the PRIMASK priority: Raises the execution priority to 0. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SETPRIMASK(void) +{ + __SETPRIMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_RESETPRIMASK +* Description : Disables the PRIMASK priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_RESETPRIMASK(void) +{ + __RESETPRIMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_SETFAULTMASK +* Description : Enables the FAULTMASK priority: Raises the execution priority to -1. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SETFAULTMASK(void) +{ + __SETFAULTMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_RESETFAULTMASK +* Description : Disables the FAULTMASK priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_RESETFAULTMASK(void) +{ + __RESETFAULTMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_BASEPRICONFIG +* Description : The execution priority can be changed from 15 (lowest + configurable priority) to 1. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_BASEPRICONFIG(u32 NewPriority) +{ + /* Check the parameters */ + assert(IS_NVIC_BASE_PRI(NewPriority)); + + __BASEPRICONFIG(NewPriority << 0x04); +} + +/******************************************************************************* +* Function Name : NVIC_GetBASEPRI +* Description : Returns the BASEPRI mask value. +* Input : None +* Output : None +* Return : BASEPRI register value +*******************************************************************************/ +u32 NVIC_GetBASEPRI(void) +{ + return (__GetBASEPRI()); +} + +/******************************************************************************* +* Function Name : NVIC_GetCurrentPendingIRQChannel +* Description : Returns the current pending IRQ channel identifier. +* Input : None +* Output : None +* Return : Pending IRQ Channel Identifier. +*******************************************************************************/ +u16 NVIC_GetCurrentPendingIRQChannel(void) +{ + return ((u16)((SCB->IRQControlState & (u32)0x003FF000) >> 0x0C)); +} + +/******************************************************************************* +* Function Name : NVIC_GetIRQChannelPendingBitStatus +* Description : Checks whether the specified IRQ Channel pending bit is set +* or not. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check. +* Output : None +* Return : The new state of IRQ Channel pending bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel) +{ + ITStatus pendingirqstatus = RESET; + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F)); + + if (((NVIC->Set[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp) + { + pendingirqstatus = SET; + } + else + { + pendingirqstatus = RESET; + } + return pendingirqstatus; +} + +/******************************************************************************* +* Function Name : NVIC_SetIRQChannelPendingBit +* Description : Sets the NVICs interrupt pending bit. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel) +{ + /* Check the parameters */ + assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + *(u32*)0xE000EF00 = (u32)NVIC_IRQChannel; +} + +/******************************************************************************* +* Function Name : NVIC_ClearIRQChannelPendingBit +* Description : Clears the NVICs interrupt pending bit. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel) +{ + /* Check the parameters */ + assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + NVIC->Clear[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F); +} + +/******************************************************************************* +* Function Name : NVIC_GetCurrentActiveHandler +* Description : Returns the current active Handler (IRQ Channel and +* SystemHandler) identifier. +* Input : None +* Output : None +* Return : Active Handler Identifier. +*******************************************************************************/ +u16 NVIC_GetCurrentActiveHandler(void) +{ + return ((u16)(SCB->IRQControlState & (u32)0x3FF)); +} + +/******************************************************************************* +* Function Name : NVIC_GetIRQChannelActiveBitStatus +* Description : Checks whether the specified IRQ Channel active bit is set +* or not. +* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check. +* Output : None +* Return : The new state of IRQ Channel active bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel) +{ + ITStatus activeirqstatus = RESET; + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F)); + + if (((NVIC->Active[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp ) + { + activeirqstatus = SET; + } + else + { + activeirqstatus = RESET; + } + return activeirqstatus; +} + +/******************************************************************************* +* Function Name : NVIC_GetCPUID +* Description : Returns the ID number, the version number and the implementation +* details of the Cortex-M3 core. +* Input : None +* Output : None +* Return : CPU ID. +*******************************************************************************/ +u32 NVIC_GetCPUID(void) +{ + return (SCB->CPUID); +} + +/******************************************************************************* +* Function Name : NVIC_SetVectorTable +* Description : Sets the vector table location and Offset. +* Input : - NVIC_VectTab: specifies if the vector table is in RAM or +* code memory. +* This parameter can be one of the following values: +* - NVIC_VectTab_RAM +* - NVIC_VectTab_FLASH +* - Offset: Vector Table base offset field. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset) +{ + /* Check the parameters */ + assert(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert(IS_NVIC_OFFSET(Offset)); + + SCB->ExceptionTableOffset = (((u32)Offset << 0x07) & (u32)0x1FFFFF80); + + SCB->ExceptionTableOffset |= NVIC_VectTab; +} + +/******************************************************************************* +* Function Name : NVIC_GenerateSystemReset +* Description : Generates a system reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_GenerateSystemReset(void) +{ + SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x04; +} + +/******************************************************************************* +* Function Name : NVIC_GenerateCoreReset +* Description : Generates a Core (Core + NVIC) reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_GenerateCoreReset(void) +{ + SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x01; +} + +/******************************************************************************* +* Function Name : NVIC_SystemLPConfig +* Description : Selects the condition for the system to enter low power mode. +* Input : - LowPowerMode: Specifies the new mode for the system to enter +* low power mode. +* This parameter can be one of the following values: +* - NVIC_LP_SEVONPEND +* - NVIC_LP_SLEEPDEEP +* - NVIC_LP_SLEEPONEXIT +* - NewState: new state of LP condition. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_NVIC_LP(LowPowerMode)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SysCtrl |= LowPowerMode; + } + else + { + SCB->SysCtrl &= (u32)(~(u32)LowPowerMode); + } +} + +/******************************************************************************* +* Function Name : NVIC_SystemHandlerConfig +* Description : Enables or disables the specified System Handlers. +* Input : - SystemHandler: specifies the system handler to be enabled +* or disabled. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - NewState: new state of specified System Handlers. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState) +{ + u32 tmpreg = 0x00; + + /* Check the parameters */ + assert(IS_CONFIG_SYSTEM_HANDLER(SystemHandler)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F); + + if (NewState != DISABLE) + { + SCB->SysHandlerCtrl |= tmpreg; + } + else + { + SCB->SysHandlerCtrl &= ~tmpreg; + } +} + +/******************************************************************************* +* Function Name : NVIC_SystemHandlerPriorityConfig +* Description : Configures the specified System Handlers priority. +* Input : - SystemHandler: specifies the system handler to be +* enabled or disabled. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_SVCall +* - SystemHandler_DebugMonitor +* - SystemHandler_PSV +* - SystemHandler_SysTick +* - SystemHandlerPreemptionPriority: new priority group of the +* specified system handlers. +* - SystemHandlerSubPriority: new sub priority of the specified +* system handlers. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority) +{ + u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00; + u32 tmppriority = 0x00; + + /* Check the parameters */ + assert(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler)); + assert(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority)); + assert(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority)); + + tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08; + tmp1 = (0x4 - tmppriority); + tmp2 = tmp2 >> tmppriority; + + tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1; + tmppriority |= SystemHandlerSubPriority & tmp2; + + tmppriority = tmppriority << 0x04; + tmp1 = SystemHandler & (u32)0xC0; + tmp1 = tmp1 >> 0x06; + tmp2 = (SystemHandler >> 0x08) & (u32)0x03; + tmppriority = tmppriority << (tmp2 * 0x08); + handlermask = (u32)0xFF << (tmp2 * 0x08); + + SCB->SystemPriority[tmp1] &= ~handlermask; + SCB->SystemPriority[tmp1] |= tmppriority; +} + +/******************************************************************************* +* Function Name : NVIC_GetSystemHandlerPendingBitStatus +* Description : Checks whether the specified System handlers pending bit is +* set or not. +* Input : - SystemHandler: specifies the system handler pending bit to +* check. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_SVCall +* Output : None +* Return : The new state of System Handler pending bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler) +{ + ITStatus bitstatus = RESET; + u32 tmp = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler)); + + tmppos = (SystemHandler >> 0x0A); + tmppos &= (u32)0x0F; + + tmppos = (u32)0x01 << tmppos; + + tmp = SCB->SysHandlerCtrl & tmppos; + + if (tmp == tmppos) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : NVIC_SetSystemHandlerPendingBit +* Description : Sets System Handler pending bit. +* Input : - SystemHandler: specifies the system handler pending bit +* to be set. +* This parameter can be one of the following values: +* - SystemHandler_NMI +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler)); + + /* Get the System Handler pending bit position */ + tmp = SystemHandler & (u32)0x1F; + /* Set the corresponding System Handler pending bit */ + SCB->IRQControlState |= ((u32)0x01 << tmp); +} + +/******************************************************************************* +* Function Name : NVIC_ClearSystemHandlerPendingBit +* Description : Clears System Handler pending bit. +* Input : - SystemHandler: specifies the system handler pending bit to +* be clear. +* This parameter can be one of the following values: +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_CLEAR_SYSTEM_HANDLER(SystemHandler)); + + /* Get the System Handler pending bit position */ + tmp = SystemHandler & (u32)0x1F; + /* Clear the corresponding System Handler pending bit */ + SCB->IRQControlState |= ((u32)0x01 << (tmp - 0x01)); +} + +/******************************************************************************* +* Function Name : NVIC_GetSystemHandlerActiveBitStatus +* Description : Checks whether the specified System handlers active bit is +* set or not. +* Input : - SystemHandler: specifies the system handler active bit to +* check. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_SVCall +* - SystemHandler_DebugMonitor +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : The new state of System Handler active bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler) +{ + ITStatus bitstatus = RESET; + + u32 tmp = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler)); + + tmppos = (SystemHandler >> 0x0E) & (u32)0x0F; + + tmppos = (u32)0x01 << tmppos; + + tmp = SCB->SysHandlerCtrl & tmppos; + + if (tmp == tmppos) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : NVIC_GetFaultHandlerSources +* Description : Returns the system fault handlers sources. +* Input : - SystemHandler: specifies the system handler to get its fault +* sources. +* This parameter can be one of the following values: +* - SystemHandler_HardFault +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_DebugMonitor +* Output : None +* Return : Source of the fault handler. +*******************************************************************************/ +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler) +{ + u32 faultsources = 0x00; + u32 tmpreg = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler)); + + tmpreg = (SystemHandler >> 0x12) & (u32)0x03; + tmppos = (SystemHandler >> 0x14) & (u32)0x03; + + if (tmpreg == 0x00) + { + faultsources = SCB->HardFaultStatus; + } + else if (tmpreg == 0x01) + { + faultsources = SCB->ConfigFaultStatus >> (tmppos * 0x08); + if (tmppos != 0x02) + { + faultsources &= (u32)0x0F; + } + else + { + faultsources &= (u32)0xFF; + } + } + else + { + faultsources = SCB->DebugFaultStatus; + } + return faultsources; +} + +/******************************************************************************* +* Function Name : NVIC_GetFaultAddress +* Description : Returns the address of the location that generated a fault +* handler. +* Input : - SystemHandler: specifies the system handler to get its +* fault address. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* Output : None +* Return : Fault address. +*******************************************************************************/ +u32 NVIC_GetFaultAddress(u32 SystemHandler) +{ + u32 faultaddress = 0x00; + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler)); + + tmp = (SystemHandler >> 0x16) & (u32)0x01; + + if (tmp == 0x00) + { + faultaddress = SCB->MemoryManageFaultAddr; + } + else + { + faultaddress = SCB->BusFaultAddr; + } + return faultaddress; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_pwr.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_pwr.c new file mode 100644 index 0000000..26b6dcc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_pwr.c @@ -0,0 +1,283 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_pwr.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the PWR firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ +/* CR register bit mask */ +#define CR_PDDS_Set ((u32)0x00000002) +#define CR_DS_Mask ((u32)0xFFFFFFFC) +#define CR_CWUF_Set ((u32)0x00000004) +#define CR_PLS_Mask ((u32)0xFFFFFF1F) + +/* --------- Cortex System Control register bit mask ---------------- */ +/* Cortex System Control register address */ +#define SCB_SysCtrl ((u32)0xE000ED10) +/* SLEEPDEEP bit mask */ +#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : PWR_DeInit +* Description : Deinitializes the PWR peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/******************************************************************************* +* Function Name : PWR_BackupAccessCmd +* Description : Enables or disables access to the RTC and backup registers. +* Input : - NewState: new state of the access to the RTC and backup +* registers. This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_DBP_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : PWR_PVDCmd +* Description : Enables or disables the Power Voltage Detector(PVD). +* Input : - NewState: new state of the PVD. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_PVDE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : PWR_PVDLevelConfig +* Description : Configures the value detected by the Power Voltage Detector(PVD). +* Input : - PWR_PVDLevel: specifies the PVD detection level +* This parameter can be one of the following values: +* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V +* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V +* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V +* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V +* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V +* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V +* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V +* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V +* Output : None +* Return : None +*******************************************************************************/ +void PWR_PVDLevelConfig(u32 PWR_PVDLevel) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + + tmpreg = PWR->CR; + + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_Mask; + + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/******************************************************************************* +* Function Name : PWR_WakeUpPinCmd +* Description : Enables or disables the WakeUp Pin functionality. +* Input : - NewState: new state of the WakeUp Pin functionality. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CSR_EWUP_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : PWR_EnterSTOPMode +* Description : Enters STOP mode. +* Input : - PWR_Regulator: specifies the regulator state in STOP mode. +* This parameter can be one of the following values: +* - PWR_Regulator_ON: STOP mode with regulator ON +* - PWR_Regulator_LowPower: STOP mode with +* regulator in low power mode +* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or +* WFE instruction. +* This parameter can be one of the following values: +* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction +* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction +* Output : None +* Return : None +*******************************************************************************/ +void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_PWR_REGULATOR(PWR_Regulator)); + assert(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_Mask; + + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } +} + +/******************************************************************************* +* Function Name : PWR_EnterSTANDBYMode +* Description : Enters STANDBY mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= CR_CWUF_Set; + + /* Select STANDBY mode */ + PWR->CR |= CR_PDDS_Set; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; + + /* Request Wait For Interrupt */ + __WFI(); +} + +/******************************************************************************* +* Function Name : PWR_GetFlagStatus +* Description : Checks whether the specified PWR flag is set or not. +* Input : - PWR_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - PWR_FLAG_WU: Wake Up flag +* - PWR_FLAG_SB: StandBy flag +* - PWR_FLAG_PVDO: PVD Output +* Output : None +* Return : The new state of PWR_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : PWR_ClearFlag +* Description : Clears the PWR's pending flags. +* Input : - PWR_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - PWR_FLAG_WU: Wake Up flag +* - PWR_FLAG_SB: StandBy flag +* Output : None +* Return : None +*******************************************************************************/ +void PWR_ClearFlag(u32 PWR_FLAG) +{ + /* Check the parameters */ + assert(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rcc.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rcc.c new file mode 100644 index 0000000..1cd00bd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rcc.c @@ -0,0 +1,1069 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_rcc.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the RCC firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) +#define USBPRE_BitNumber 0x16 +#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) + +/* --- BDCR Register ---*/ +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +/* ---------------------- RCC registers bit mask ------------------------ */ +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((u32)0xFFFBFFFF) +#define CR_HSEBYP_Set ((u32)0x00040000) +#define CR_HSEON_Reset ((u32)0xFFFEFFFF) +#define CR_HSEON_Set ((u32)0x00010000) +#define CR_HSITRIM_Mask ((u32)0xFFFFFF07) + +/* CFGR register bit mask */ +#define CFGR_PLL_Mask ((u32)0xFFC0FFFF) +#define CFGR_PLLMull_Mask ((u32)0x003C0000) +#define CFGR_PLLSRC_Mask ((u32)0x00010000) +#define CFGR_PLLXTPRE_Mask ((u32)0x00020000) +#define CFGR_SWS_Mask ((u32)0x0000000C) +#define CFGR_SW_Mask ((u32)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((u32)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((u32)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((u32)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RVMF_Set ((u32)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((u8)0x1F) + +/* Typical Value of the HSI in Hz */ +#define HSI_Value ((u32)8000000) + +/* BDCR register base address */ +#define BDCR_BASE (PERIPH_BASE + BDCR_OFFSET) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static uc8 ADCPrescTable[4] = {2, 4, 6, 8}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : RCC_DeInit +* Description : Deinitializes the RCC peripheral registers to their default +* reset values. +* - The HSITRIM[4:0] bits in RCC_CR register are not modified +* by this function. +* - The RCC_BDCR and RCC_CSR registers are not reset by this +* function. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_DeInit(void) +{ + /* Disable APB2 Peripheral Reset */ + RCC->APB2RSTR = 0x00000000; + + /* Disable APB1 Peripheral Reset */ + RCC->APB1RSTR = 0x00000000; + + /* FLITF and SRAM Clock ON */ + RCC->AHBENR = 0x00000014; + + /* Disable APB2 Peripheral Clock */ + RCC->APB2ENR = 0x00000000; + + /* Disable APB1 Peripheral Clock */ + RCC->APB1ENR = 0x00000000; + + /* Set HSION bit */ + RCC->CR |= (u32)0x00000001; + + /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/ + RCC->CFGR &= 0xF8FF0000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= 0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */ + RCC->CFGR &= 0xFF80FFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/******************************************************************************* +* Function Name : RCC_HSEConfig +* Description : Configures the External High Speed oscillator (HSE). +* Input : - RCC_HSE: specifies the new state of the HSE. +* This parameter can be one of the following values: +* - RCC_HSE_OFF: HSE oscillator OFF +* - RCC_HSE_ON: HSE oscillator ON +* - RCC_HSE_Bypass: HSE oscillator bypassed with external +* clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_HSEConfig(u32 RCC_HSE) +{ + /* Check the parameters */ + assert(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : RCC_AdjustHSICalibrationValue +* Description : Adjusts the Internal High Speed oscillator (HSI) calibration +* value. +* Input : - HSICalibrationValue: specifies the calibration trimming value. +* This parameter must be a number between 0 and 0x1F. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[7:3] bits */ + tmpreg &= CR_HSITRIM_Mask; + + /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */ + tmpreg |= (u32)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_HSICmd +* Description : Enables or disables the Internal High Speed oscillator (HSI). +* HSI can not be stopped if it is used directly or through the +* PLL as system clock, or if a Flash programmation is on going. +* Input : - NewState: new state of the HSI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_HSION_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_PLLConfig +* Description : Configures the PLL clock source and multiplication factor. +* This function must be used only when the PLL is disabled. +* Input : - RCC_PLLSource: specifies the PLL entry clock source. +* This parameter can be one of the following values: +* - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided +* by 2 selected as PLL clock entry +* - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected +* as PLL clock entry +* - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided +* by 2 selected as PLL clock entry +* - RCC_PLLMul: specifies the PLL multiplication factor. +* This parameter can be RCC_PLLMul_x where x:[2,16] +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + + /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */ + tmpreg &= CFGR_PLL_Mask; + + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_PLLCmd +* Description : Enables or disables the PLL. +* The PLL can not be disabled if it is used as system clock. +* Input : - NewState: new state of the PLL. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_PLLON_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_SYSCLKConfig +* Description : Configures the system clock (SYSCLK). +* Input : - RCC_SYSCLKSource: specifies the clock source used as system +* clock. This parameter can be one of the following values: +* - RCC_SYSCLKSource_HSI: HSI selected as system clock +* - RCC_SYSCLKSource_HSE: HSE selected as system clock +* - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_GetSYSCLKSource +* Description : Returns the clock source used as system clock. +* Input : None +* Output : None +* Return : The clock source used as system clock. The returned value can +* be one of the following: +* - 0x00: HSI used as system clock +* - 0x04: HSE used as system clock +* - 0x08: PLL used as system clock +*******************************************************************************/ +u8 RCC_GetSYSCLKSource(void) +{ + return ((u8)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/******************************************************************************* +* Function Name : RCC_HCLKConfig +* Description : Configures the AHB clock (HCLK). +* Input : - RCC_HCLK: defines the AHB clock. This clock is derived +* from the system clock (SYSCLK). +* This parameter can be one of the following values: +* - RCC_SYSCLK_Div1: AHB clock = SYSCLK +* - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 +* - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 +* - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 +* - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 +* - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 +* - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 +* - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 +* - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_HCLKConfig(u32 RCC_HCLK) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_HCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[7:4] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + + /* Set HPRE[7:4] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_PCLK1Config +* Description : Configures the Low Speed APB clock (PCLK1). +* Input : - RCC_PCLK1: defines the APB1 clock. This clock is derived +* from the AHB clock (HCLK). +* This parameter can be one of the following values: +* - RCC_HCLK_Div1: APB1 clock = HCLK +* - RCC_HCLK_Div2: APB1 clock = HCLK/2 +* - RCC_HCLK_Div4: APB1 clock = HCLK/4 +* - RCC_HCLK_Div8: APB1 clock = HCLK/8 +* - RCC_HCLK_Div16: APB1 clock = HCLK/16 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PCLK1Config(u32 RCC_PCLK1) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_PCLK(RCC_PCLK1)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[10:8] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + + /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */ + tmpreg |= RCC_PCLK1; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_PCLK2Config +* Description : Configures the High Speed APB clock (PCLK2). +* Input : - RCC_PCLK2: defines the APB2 clock. This clock is derived +* from the AHB clock (HCLK). +* This parameter can be one of the following values: +* - RCC_HCLK_Div1: APB2 clock = HCLK +* - RCC_HCLK_Div2: APB2 clock = HCLK/2 +* - RCC_HCLK_Div4: APB2 clock = HCLK/4 +* - RCC_HCLK_Div8: APB2 clock = HCLK/8 +* - RCC_HCLK_Div16: APB2 clock = HCLK/16 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PCLK2Config(u32 RCC_PCLK2) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_PCLK(RCC_PCLK2)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE2[13:11] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + + /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2 << 3; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_ITConfig +* Description : Enables or disables the specified RCC interrupts. +* Input : - RCC_IT: specifies the RCC interrupt sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - RCC_IT_LSIRDY: LSI ready interrupt +* - RCC_IT_LSERDY: LSE ready interrupt +* - RCC_IT_HSIRDY: HSI ready interrupt +* - RCC_IT_HSERDY: HSE ready interrupt +* - RCC_IT_PLLRDY: PLL ready interrupt +* - NewState: new state of the specified RCC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_IT(RCC_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */ + *(vu8 *) 0x40021009 |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */ + *(vu8 *) 0x40021009 &= ~(u32)RCC_IT; + } +} + +/******************************************************************************* +* Function Name : RCC_USBCLKConfig +* Description : Configures the USB clock (USBCLK). +* Input : - RCC_USBCLKSource: specifies the USB clock source. This clock +* is derived from the PLL output. +* This parameter can be one of the following values: +* - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 +* selected as USB clock source +* - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB +* clock source +* Output : None +* Return : None +*******************************************************************************/ +void RCC_USBCLKConfig(u32 RCC_USBCLKSource) +{ + /* Check the parameters */ + assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} + +/******************************************************************************* +* Function Name : RCC_ADCCLKConfig +* Description : Configures the ADC clock (ADCCLK). +* Input : - RCC_ADCCLK: defines the ADC clock. This clock is derived +* from the APB2 clock (PCLK2). +* This parameter can be one of the following values: +* - RCC_PCLK2_Div2: ADC clock = PCLK2/2 +* - RCC_PCLK2_Div4: ADC clock = PCLK2/4 +* - RCC_PCLK2_Div6: ADC clock = PCLK2/6 +* - RCC_PCLK2_Div8: ADC clock = PCLK2/8 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ADCCLKConfig(u32 RCC_ADCCLK) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_ADCCLK(RCC_ADCCLK)); + + tmpreg = RCC->CFGR; + + /* Clear ADCPRE[15:14] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + + /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */ + tmpreg |= RCC_ADCCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_LSEConfig +* Description : Configures the External Low Speed oscillator (LSE). +* Input : - RCC_LSE: specifies the new state of the LSE. +* This parameter can be one of the following values: +* - RCC_LSE_OFF: LSE oscillator OFF +* - RCC_LSE_ON: LSE oscillator ON +* - RCC_LSE_Bypass: LSE oscillator bypassed with external +* clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_LSEConfig(u32 RCC_LSE) +{ + /* Check the parameters */ + assert(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(vu8 *) BDCR_BASE = RCC_LSE_OFF; + + /* Reset LSEBYP bit */ + *(vu8 *) BDCR_BASE = RCC_LSE_OFF; + + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(vu8 *) BDCR_BASE = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : RCC_LSICmd +* Description : Enables or disables the Internal Low Speed oscillator (LSI). +* LSI can not be disabled if the IWDG is running. +* Input : - NewState: new state of the LSI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CSR_LSION_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_RTCCLKConfig +* Description : Configures the RTC clock (RTCCLK). +* Once the RTC clock is selected it cant be changed unless the +* Backup domain is reset. +* Input : - RCC_RTCCLKSource: specifies the RTC clock source. +* This parameter can be one of the following values: +* - RCC_RTCCLKSource_LSE: LSE oscillator clock used as RTC +* clock +* - RCC_RTCCLKSource_LSI: LSI oscillator clock used as RTC +* clock +* - RCC_RTCCLKSource_HSE_Div128: HSE oscillator clock divided +* by 128 used as RTC clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/******************************************************************************* +* Function Name : RCC_RTCCLKCmd +* Description : Enables or disables the RTC clock. +* This function must be used only after the RTC clock was +* selected using the RCC_RTCCLKConfig function. +* Input : - NewState: new state of the RTC clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) BDCR_RTCEN_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_GetClocksFreq +* Description : Returns the frequencies of different on chip clocks. +* Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which +* will hold the clocks frequencies. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_Value; + break; + + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllmull = ( pllmull >> 18) + 2; + + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; + } + else + {/* HSE selected as PLL clock entry */ + + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET) + {/* HSE oscillator clock divided by 2 */ + + RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull; + } + } + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/******************************************************************************* +* Function Name : RCC_AHBPeriphClockCmd +* Description : Enables or disables the AHB peripheral clock. +* Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. +* This parameter can be any combination of the following values: +* - RCC_AHBPeriph_DMA +* - RCC_AHBPeriph_SRAM +* - RCC_AHBPeriph_FLITF +* SRAM and FLITF clock can be disabled only during sleep mode. +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB2PeriphClockCmd +* Description : Enables or disables the High Speed APB (APB2) peripheral clock. +* Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB +* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE +* RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1 +* RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB1PeriphClockCmd +* Description : Enables or disables the Low Speed APB (APB1) peripheral clock. +* Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4 +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2 +* RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2 +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP +* RCC_APB1Periph_PWR, RCC_APB1Periph_ALL +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB2PeriphResetCmd +* Description : Forces or releases High Speed APB (APB2) peripheral reset. +* Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset. +* This parameter can be any combination of the following values: +* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB +* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE +* RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1 +* RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL +* - NewState: new state of the specified peripheral reset. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB1PeriphResetCmd +* Description : Forces or releases Low Speed APB (APB1) peripheral reset. +* Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset. +* This parameter can be any combination of the following values: +* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4 +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2 +* RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2 +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP +* RCC_APB1Periph_PWR, RCC_APB1Periph_ALL +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_BackupResetCmd +* Description : Forces or releases the Backup domain reset. +* Input : - NewState: new state of the Backup domain reset. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) BDCR_BDRST_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_ClockSecuritySystemCmd +* Description : Enables or disables the Clock Security System. +* Input : - NewState: new state of the Clock Security System.. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_CSSON_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_MCOConfig +* Description : Selects the clock source to output on MCO pin. +* Input : - RCC_MCO: specifies the clock source to output. +* This parameter can be one of the following values: +* - RCC_MCO_NoClock: No clock selected +* - RCC_MCO_SYSCLK: System clock selected +* - RCC_MCO_HSI: HSI oscillator clock selected +* - RCC_MCO_HSE: HSE oscillator clock selected +* - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected +* Output : None +* Return : None +*******************************************************************************/ +void RCC_MCOConfig(u8 RCC_MCO) +{ + /* Check the parameters */ + assert(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO[26:24] bits to select the MCO source */ + *(vu8 *) 0x40021007 = RCC_MCO; +} + +/******************************************************************************* +* Function Name : RCC_GetFlagStatus +* Description : Checks whether the specified RCC flag is set or not. +* Input : - RCC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - RCC_FLAG_HSIRDY: HSI oscillator clock ready +* - RCC_FLAG_HSERDY: HSE oscillator clock ready +* - RCC_FLAG_PLLRDY: PLL clock ready +* - RCC_FLAG_LSERDY: LSE oscillator clock ready +* - RCC_FLAG_LSIRDY: LSI oscillator clock ready +* - RCC_FLAG_PINRST: Pin reset +* - RCC_FLAG_PORRST: POR/PDR reset +* - RCC_FLAG_SFTRST: Software reset +* - RCC_FLAG_IWDGRST: Independent Watchdog reset +* - RCC_FLAG_WWDGRST: Window Watchdog reset +* - RCC_FLAG_LPWRRST: Low Power reset +* Output : None +* Return : The new state of RCC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG) +{ + u32 tmp = 0; + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + + if ((statusreg & ((u32)1 << tmp)) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : RCC_ClearFlag +* Description : Clears the RCC reset flags. +* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, +* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, +* RCC_FLAG_LPWRRST +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ClearFlag(void) +{ + /* Set RVMF bit to clear the reset flags */ + RCC->CSR |= CSR_RVMF_Set; +} + +/******************************************************************************* +* Function Name : RCC_GetITStatus +* Description : Checks whether the specified RCC interrupt has occurred or not. +* Input : - RCC_IT: specifies the RCC interrupt source to check. +* This parameter can be one of the following values: +* - RCC_IT_LSIRDY: LSI ready interrupt +* - RCC_IT_LSERDY: LSE ready interrupt +* - RCC_IT_HSIRDY: HSI ready interrupt +* - RCC_IT_HSERDY: HSE ready interrupt +* - RCC_IT_PLLRDY: PLL ready interrupt +* - RCC_IT_CSS: Clock Security System interrupt +* Output : None +* Return : The new state of RCC_IT (SET or RESET). +*******************************************************************************/ +ITStatus RCC_GetITStatus(u8 RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : RCC_ClearITPendingBit +* Description : Clears the RCCs interrupt pending bits. +* Input : - RCC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - RCC_IT_LSIRDY: LSI ready interrupt +* - RCC_IT_LSERDY: LSE ready interrupt +* - RCC_IT_HSIRDY: HSI ready interrupt +* - RCC_IT_HSERDY: HSE ready interrupt +* - RCC_IT_PLLRDY: PLL ready interrupt +* - RCC_IT_CSS: Clock Security System interrupt +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ClearITPendingBit(u8 RCC_IT) +{ + /* Check the parameters */ + assert(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(vu8 *) 0x4002100A = RCC_IT; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rtc.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rtc.c new file mode 100644 index 0000000..2163791 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rtc.c @@ -0,0 +1,342 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_rtc.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the RTC firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define CRL_CNF_Set ((u16)0x0010) /* Configuration Flag Enable Mask */ +#define CRL_CNF_Reset ((u16)0xFFEF) /* Configuration Flag Disable Mask */ +#define RTC_LSB_Mask ((u32)0x0000FFFF) /* RTC LSB Mask */ +#define RTC_MSB_Mask ((u32)0xFFFF0000) /* RTC MSB Mask */ +#define PRLH_MSB_Mask ((u32)0x000F0000) /* RTC Prescaler MSB Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : RTC_ITConfig +* Description : Enables or disables the specified RTC interrupts. +* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - RTC_IT_OW: Overflow interrupt +* - RTC_IT_ALR: Alarm interrupt +* - RTC_IT_SEC: Second interrupt +* - NewState: new state of the specified RTC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RTC_IT(RTC_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (u16)~RTC_IT; + } +} + +/******************************************************************************* +* Function Name : RTC_EnterConfigMode +* Description : Enters the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= CRL_CNF_Set; +} + +/******************************************************************************* +* Function Name : RTC_ExitConfigMode +* Description : Exits from the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= CRL_CNF_Reset; +} + +/******************************************************************************* +* Function Name : RTC_GetCounter +* Description : Gets the RTC counter value. +* Input : None +* Output : None +* Return : RTC counter value. +*******************************************************************************/ +u32 RTC_GetCounter(void) +{ + u16 tmp = 0; + tmp = RTC->CNTL; + + return (((u32)RTC->CNTH << 16 ) | tmp) ; +} + +/******************************************************************************* +* Function Name : RTC_SetCounter +* Description : Sets the RTC counter value. +* Input : - CounterValue: RTC counter new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetCounter(u32 CounterValue) +{ + RTC_EnterConfigMode(); + + /* Set RTC COUNTER MSB word */ + RTC->CNTH = (CounterValue & RTC_MSB_Mask) >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetPrescaler +* Description : Gets the RTC prescaler value. +* Input : None +* Output : None +* Return : RTC prescaler value. +*******************************************************************************/ +u32 RTC_GetPrescaler(void) +{ + u32 tmp = 0x00; + + tmp = ((u32)RTC->PRLH & (u32)0x000F) << 0x10; + tmp |= RTC->PRLL; + + return tmp; +} + +/******************************************************************************* +* Function Name : RTC_SetPrescaler +* Description : Sets the RTC prescaler value. +* Input : - PrescalerValue: RTC prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetPrescaler(u32 PrescalerValue) +{ + /* Check the parameters */ + assert(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 0x10; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_SetAlarm +* Description : Sets the RTC alarm value. +* Input : - AlarmValue: RTC alarm new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetAlarm(u32 AlarmValue) +{ + RTC_EnterConfigMode(); + + /* Set the ALARM MSB word */ + RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetDivider +* Description : Gets the RTC divider value. +* Input : None +* Output : None +* Return : RTC Divider value. +*******************************************************************************/ +u32 RTC_GetDivider(void) +{ + u32 tmp = 0x00; + + tmp = ((u32)RTC->DIVH & (u32)0x000F) << 0x10; + tmp |= RTC->DIVL; + + return tmp; +} + +/******************************************************************************* +* Function Name : RTC_WaitForLastTask +* Description : Waits until last write operation on RTC registers has finished. +* This function must be called before any write to RTC registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (u16)RESET) + { + } +} + +/******************************************************************************* +* Function Name : RTC_WaitForSynchro +* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) +* are synchronized with RTC APB clock. +* This function must be called before any read operation after +* an APB reset or an APB clock stop. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (u16)~RTC_FLAG_RSF; + + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (u16)RESET) + { + } +} + +/******************************************************************************* +* Function Name : RTC_GetFlagStatus +* Description : Checks whether the specified RTC flag is set or not. +* Input : - RTC_FLAG: specifies the flag to check. +* This parameter can be one the following values: +* - RTC_FLAG_RTOFF: RTC Operation OFF flag +* - RTC_FLAG_RSF: Registers Synchronized flag +* - RTC_FLAG_OW: Overflow flag +* - RTC_FLAG_ALR: Alarm flag +* - RTC_FLAG_SEC: Second flag +* Output : None +* Return : The new state of RTC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (u16)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : RTC_ClearFlag +* Description : Clears the RTCs pending flags. +* Input : - RTC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - RTC_FLAG_RSF: Registers Synchronized flag. This flag +* is cleared only after an APB reset or an APB Clock stop. +* - RTC_FLAG_OW: Overflow flag +* - RTC_FLAG_ALR: Alarm flag +* - RTC_FLAG_SEC: Second flag +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearFlag(u16 RTC_FLAG) +{ + /* Check the parameters */ + assert(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the coressponding RTC flag */ + RTC->CRL &= (u16)~RTC_FLAG; +} + +/******************************************************************************* +* Function Name : RTC_GetITStatus +* Description : Checks whether the specified RTC interrupt has occured or not. +* Input : - RTC_IT: specifies the RTC interrupts sources to check. +* This parameter can be one of the following values: +* - RTC_IT_OW: Overflow interrupt +* - RTC_IT_ALR: Alarm interrupt +* - RTC_IT_SEC: Second interrupt +* Output : None +* Return : The new state of the RTC_IT (SET or RESET). +*******************************************************************************/ +ITStatus RTC_GetITStatus(u16 RTC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)((RTC->CRL & RTC_IT) != (u16)RESET); + + if (((RTC->CRH & RTC_IT) != (u16)RESET) && bitstatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : RTC_ClearITPendingBit +* Description : Clears the RTCs interrupt pending bits. +* Input : - RTC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - RTC_IT_OW: Overflow interrupt +* - RTC_IT_ALR: Alarm interrupt +* - RTC_IT_SEC: Second interrupt +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearITPendingBit(u16 RTC_IT) +{ + /* Check the parameters */ + assert(IS_RTC_IT(RTC_IT)); + + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= (u16)~RTC_IT; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_sdio.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_sdio.c new file mode 100644 index 0000000..04c876e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_sdio.c @@ -0,0 +1,806 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.c + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file provides all the SDIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_sdio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/** @defgroup SDIO_Private_TypesDefinitions + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ + +/* --- CLKCR Register ---*/ + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/** + * @} + */ + +/** @defgroup SDIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default + * reset values. + * @param None + * @retval : None + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO + * peripheral. + * @retval : None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval : None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF + * @arg SDIO_PowerState_ON + * @retval : None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval : Power status of the controller. The returned value can + * be one of the following: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be + * enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information + * for the SDIO command. + * @retval : None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval : None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response + * received. + * @param None + * @retval : Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval : The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + return (*(__IO uint32_t *)(SDIO_RESP_ADDR + SDIO_RESP)); +} + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef + * structure that contains the configuration information + * for the SDIO command. + * @retval : None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef + * structure which will be initialized. + * @retval : None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval : Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval : Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval : None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read + * from FIFO. + * @param None + * @retval : Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parametre can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval : None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval : The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval : None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * interrupt + * @retval : The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIOs interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval : None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_spi.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_spi.c new file mode 100644 index 0000000..8aadc09 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_spi.c @@ -0,0 +1,836 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.c + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file provides all the SPI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @defgroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup SPI_Private_Defines + * @{ + */ + +/* SPI SPE mask */ +#define CR1_SPE_Set ((uint16_t)0x0040) +#define CR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((uint16_t)0x2000) +#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((uint16_t)0x0004) +#define CR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/** + * @} + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval : None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + switch (*(uint32_t*)&SPIx) + { + case SPI1_BASE: + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + break; + case SPI2_BASE: + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + break; + case SPI3_BASE: + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + break; + default: + break; + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified + * SPI peripheral. + * @retval : None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= SPI_Mode_Select; +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified + * SPI peripheral configured in I2S mode. + * @retval : None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + /* Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Compute the Real divider depending on the MCLK output state with a flaoting point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flaoting point */ + tmp = tmp/10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(I2S_Mode_Select | I2S_InitStruct->I2S_Mode | \ + I2S_InitStruct->I2S_Standard | I2S_InitStruct->I2S_DataFormat | \ + I2S_InitStruct->I2S_CPOL); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure + * which will be initialized. + * @retval : None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure + * which will be initialized. + * @retval : None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be : + * 1, 2 or 3 in SPI mode + * 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + /* Set the IT mask */ + itmask = (uint16_t)((uint16_t)1 << itpos); + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be : + * 1, 2 or 3 in SPI mode + * 2 or 3 in I2S mode + * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request + * to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI/I2S DMA transfer + * request. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be : + * 1, 2 or 3 in SPI mode + * 2 or 3 in I2S mode + * @param Data : Data to be transmitted.. + * @retval : None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be : + * 1, 2 or 3 in SPI mode + * 2 or 3 in I2S mode + * @retval : The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Configures internally by software the NSS pin for the selected + * SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval : None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval : None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval : None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/** + * @brief Enables or disables the CRC value calculation of the + * transfered bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for + * the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval : The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval : The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in + * bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval : None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx: where x can be : + * 1, 2 or 3 in SPI mode + * 2 or 3 in I2S mode + * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval : The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be : + * 1, 2 or 3 in SPI mode + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval : None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be : + * 1, 2 or 3 in SPI mode + * 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun Error interrupt. + * @retval : The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + /* Get the SPI/I2S IT index */ + itpos = (uint16_t)((uint16_t)0x01 << (SPI_I2S_IT & (uint8_t)0x0F)); + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + /* Set the IT mask */ + itmask = (uint16_t)((uint16_t)0x01 << itmask); + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: where x can be : + * 1, 2 or 3 in SPI mode + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR intetrrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval : None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + /* Get the SPI IT index */ + itpos = (uint16_t)((uint16_t)0x01 << (SPI_I2S_IT & (uint8_t)0x0F)); + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_systick.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_systick.c new file mode 100644 index 0000000..6f7a27e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_systick.c @@ -0,0 +1,195 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_systick.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the SysTick firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_systick.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- SysTick registers bit mask -------------------- */ +/* CTRL TICKINT Mask */ +#define CTRL_TICKINT_Set ((u32)0x00000002) +#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD) + +/* SysTick Flag Mask */ +#define FLAG_Mask ((u8)0x1F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SysTick_CLKSourceConfig +* Description : Configures the SysTick clock source. +* Input : - SysTick_CLKSource: specifies the SysTick clock source. +* This parameter can be one of the following values: +* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 +* selected as SysTick clock source. +* - SysTick_CLKSource_HCLK: AHB clock selected as +* SysTick clock source. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_CLKSourceConfig(u32 SysTick_CLKSource) +{ + /* Check the parameters */ + assert(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/******************************************************************************* +* Function Name : SysTick_SetReload +* Description : Sets SysTick Reload value. +* Input : - Reload: SysTick Reload new value. +* This parameter must be a number between 1 and 0xFFFFFF. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_SetReload(u32 Reload) +{ + /* Check the parameters */ + assert(IS_SYSTICK_RELOAD(Reload)); + + SysTick->LOAD = Reload; +} + +/******************************************************************************* +* Function Name : SysTick_CounterCmd +* Description : Enables or disables the SysTick counter. +* Input : - SysTick_Counter: new state of the SysTick counter. +* This parameter can be one of the following values: +* - SysTick_Counter_Disable: Disable counter +* - SysTick_Counter_Enable: Enable counter +* - SysTick_Counter_Clear: Clear counter value to 0 +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_CounterCmd(u32 SysTick_Counter) +{ + /* Check the parameters */ + assert(IS_SYSTICK_COUNTER(SysTick_Counter)); + + if (SysTick_Counter == SysTick_Counter_Clear) + { + SysTick->VAL = SysTick_Counter_Clear; + } + else + { + if (SysTick_Counter == SysTick_Counter_Enable) + { + SysTick->CTRL |= SysTick_Counter_Enable; + } + else + { + SysTick->CTRL &= SysTick_Counter_Disable; + } + } +} + +/******************************************************************************* +* Function Name : SysTick_ITConfig +* Description : Enables or disables the SysTick Interrupt. +* Input : - NewState: new state of the SysTick Interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SysTick->CTRL |= CTRL_TICKINT_Set; + } + else + { + SysTick->CTRL &= CTRL_TICKINT_Reset; + } +} + +/******************************************************************************* +* Function Name : SysTick_GetCounter +* Description : Gets SysTick counter value. +* Input : None +* Output : None +* Return : SysTick current value +*******************************************************************************/ +u32 SysTick_GetCounter(void) +{ + return(SysTick->VAL); +} + +/******************************************************************************* +* Function Name : SysTick_GetFlagStatus +* Description : Checks whether the specified SysTick flag is set or not. +* Input : - SysTick_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - SysTick_FLAG_COUNT +* - SysTick_FLAG_SKEW +* - SysTick_FLAG_NOREF +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG) +{ + u32 tmp = 0; + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_SYSTICK_FLAG(SysTick_FLAG)); + + /* Get the SysTick register index */ + tmp = SysTick_FLAG >> 5; + + if (tmp == 1) /* The flag to check is in CTRL register */ + { + statusreg = SysTick->CTRL; + } + else /* The flag to check is in CALIB register */ + { + statusreg = SysTick->CALIB; + } + + /* Get the flag position */ + tmp = SysTick_FLAG & FLAG_Mask; + + if ((statusreg & ((u32)1 << tmp)) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim.c new file mode 100644 index 0000000..5fd374e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim.c @@ -0,0 +1,2348 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_tim.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the TIM firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- TIM registers bit mask ------------------------ */ +#define CR1_CEN_Set ((u16)0x0001) +#define CR1_CEN_Reset ((u16)0x03FE) +#define CR1_UDIS_Set ((u16)0x0002) +#define CR1_UDIS_Reset ((u16)0x03FD) +#define CR1_URS_Set ((u16)0x0004) +#define CR1_URS_Reset ((u16)0x03FB) +#define CR1_OPM_Mask ((u16)0x03F7) +#define CR1_CounterMode_Mask ((u16)0x039F) +#define CR1_ARPE_Set ((u16)0x0080) +#define CR1_ARPE_Reset ((u16)0x037F) +#define CR1_CKD_Mask ((u16)0x00FF) + +#define CR2_CCDS_Set ((u16)0x0008) +#define CR2_CCDS_Reset ((u16)0x0007) +#define CR2_MMS_Mask ((u16)0x0080) +#define CR2_TI1S_Set ((u16)0x0080) +#define CR2_TI1S_Reset ((u16)0xFF70) + +#define SMCR_SMS_Mask ((u16)0xFFF0) +#define SMCR_ETR_Mask ((u16)0x00F7) +#define SMCR_TS_Mask ((u16)0xFF87) +#define SMCR_MSM_Mask ((u16)0xFF77) +#define SMCR_ECE_Set ((u16)0x4000) + +#define CCMR_CC13S_Mask ((u16)0x7F7C) +#define CCMR_CC24S_Mask ((u16)0x7C7F) +#define CCMR_TI13Direct_Set ((u16)0x0001) +#define CCMR_TI24Direct_Set ((u16)0x0100) +#define CCMR_OC13FE_Mask ((u16)0x7F7B) +#define CCMR_OC24FE_Mask ((u16)0x7B7F) +#define CCMR_OC13PE_Mask ((u16)0x7F77) +#define CCMR_OC24PE_Mask ((u16)0x777F) +#define CCMR_OCM13_Mask ((u16)0x7F0F) +#define CCMR_OCM24_Mask ((u16)0x0F7F) +#define CCMR_IC13PSC_Mask ((u16)0xFFF3) +#define CCMR_IC24PSC_Mask ((u16)0xF3FF) +#define CCMR_IC13F_Mask ((u16)0xFF0F) +#define CCMR_IC24F_Mask ((u16)0x0FFF) +#define CCER_CC1P_Mask ((u16)0xFFFD) + +#define CCER_CC2P_Mask ((u16)0xFFDF) +#define CCER_CC3P_Mask ((u16)0xFDFF) +#define CCER_CC4P_Mask ((u16)0xDFFF) + +#define CCRE_CC1E_Set ((u16)0x0001) +#define CCRE_CC1E_Reset ((u16)0xFFFE) +#define CCRE_CC1E_Mask ((u16)0xFFFE) + +#define CCRE_CC2E_Set ((u16)0x0010) +#define CCRE_CC2E_Reset ((u16)0xFFEF) +#define CCRE_CC2E_Mask ((u16)0xFFEF) + +#define CCRE_CC3E_Set ((u16)0x0100) +#define CCRE_CC3E_Reset ((u16)0xFEFF) + +#define CCRE_CC4E_Set ((u16)0x1000) +#define CCRE_CC4E_Reset ((u16)0xEFFF) +#define CCRE_CC4E_Mask ((u16)0xEFFF) + +#define DCR_DMA_Mask ((u16)0x0000) + +/* TIM private Masks */ +#define TIM_Period_Reset_Mask ((u16)0x0000) +#define TIM_Prescaler_Reset_Mask ((u16)0x0000) +#define TIM_Pulse_Reset_Mask ((u16)0x0000) +#define TIM_ICFilter_Mask ((u8)0x00) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static uc16 Tab_OCModeMask[4] = {0xFF00, 0x00FF, 0xFF00, 0x00FF}; +static uc16 Tab_PolarityMask[4] = {CCER_CC1P_Mask, CCER_CC2P_Mask, CCER_CC3P_Mask, CCER_CC4P_Mask}; + +/* Private function prototypes -----------------------------------------------*/ +static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, + u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : TIM_DeInit +* Description : Deinitializes the TIMx peripheral registers to their default +* reset values. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + switch (*(u32*)&TIMx) + { + case TIM2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + break; + + case TIM3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + break; + + case TIM4_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_TimeBaseInit +* Description : Initializes the TIMx Time Base Unit peripheral according to +* the specified parameters in the TIM_TimeBaseInitStruct. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef +* structure that contains the configuration information for +* the specified TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + /* Select the Counter Mode and set the clock division */ + TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; + TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision | + TIM_TimeBaseInitStruct->TIM_CounterMode; +} +/******************************************************************************* +* Function Name : TIM_OCInit +* Description : Initializes the TIMx peripheral according to the specified +* parameters in the TIM_OCInitStruct. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + u32 tmpccmrx = 0, tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert(IS_TIM_CHANNEL(TIM_OCInitStruct->TIM_Channel)); + assert(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + if ((TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_1) || + (TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_2)) + { + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Bits */ + tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel]; + + /* Set the Output Polarity level */ + tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel]; + + if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_1) + { + /* Disable the Channel 1: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC1E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC1E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + } + else /* TIM_Channel_2 */ + { + /* Disable the Channel 2: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC2E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC2E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 4; + } + + TIMx->CCMR1 = (u16)tmpccmrx; + } + else + { + if ((TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) || + (TIM_OCInitStruct->TIM_Channel == TIM_Channel_4)) + { + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare Bits */ + tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel]; + + /* Set the Output Polarity level */ + tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel]; + + if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) + { + /* Disable the Channel 3: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC3E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC3E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 8; + } + else /* TIM_Channel_4 */ + { + /* Disable the Channel 4: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC4E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC4E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 12; + } + + TIMx->CCMR2 = (u16)tmpccmrx; + } + } + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_ICInit +* Description : Initializes the TIMx peripheral according to the specified +* parameters in the TIM_ICInitStruct. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM_IC_MODE(TIM_ICInitStruct->TIM_ICMode)); + assert(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_ICMode == TIM_ICMode_ICAP) + { + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else /* TIM_Channel_4 */ + { + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + } + else + { + PWMI_Config(TIMx, TIM_ICInitStruct); + } +} + +/******************************************************************************* +* Function Name : TIM_TimeBaseStructInit +* Description : Fills each TIM_TimeBaseInitStruct member with its default value. +* Input : - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = TIM_Period_Reset_Mask; + TIM_TimeBaseInitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; +} + +/******************************************************************************* +* Function Name : TIM_OCStructInit +* Description : Fills each TIM_OCInitStruct member with its default value. +* Input : - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_Channel = TIM_Channel_1; + TIM_OCInitStruct->TIM_Pulse = TIM_Pulse_Reset_Mask; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; +} + +/******************************************************************************* +* Function Name : TIM_ICStructInit +* Description : Fills each TIM_InitStruct member with its default value. +* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_ICMode = TIM_ICMode_ICAP; + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = TIM_ICFilter_Mask; +} + +/******************************************************************************* +* Function Name : TIM_Cmd +* Description : Enables or disables the specified TIM peripheral. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIMx peripheral. +* - Newstate: new state of the TIMx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= CR1_CEN_Set; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= CR1_CEN_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Enables or disables the TIMx interrupts. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - TIM_IT_Update: Timer update Interrupt +* - TIM_IT_CC1: Capture Compare 1 Interrupt +* - TIM_IT_CC2: Capture Compare 2 Interrupt +* - TIM_IT_CC3: Capture Compare 3 Interrupt +* - TIM_IT_CC4: Capture Compare 4 Interrupt +* - TIM_IT_Trigger: Trigger Interrupt +* - Newstate: new state of the specified TIMx interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_TIM_IT(TIM_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (u16)(~TIM_IT); + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the TIMxs DMA interface. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_DMABase: DMA Base address. +* This parameter can be one of the following values: +* - TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR, +* TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR, +* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, +* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, +* TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, +* TIM_DMABase_CCR4, TIM_DMABase_DCR. +* - TIM_DMABurstLength: DMA Burst length. +* This parameter can be one value between: +* TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength) +{ + u32 tmpdcr = 0; + + /* Check the parameters */ + assert(IS_TIM_DMA_BASE(TIM_DMABase)); + assert(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + + tmpdcr = TIMx->DCR; + + /* Reset the DBA and the DBL Bits */ + tmpdcr &= DCR_DMA_Mask; + + /* Set the DMA Base and the DMA Burst Length */ + tmpdcr |= TIM_DMABase | TIM_DMABurstLength; + + TIMx->DCR = (u16)tmpdcr; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables the TIMxs DMA Requests. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMA_CC1: Capture Compare 1 DMA source +* - TIM_DMA_CC2: Capture Compare 2 DMA source +* - TIM_DMA_CC3: Capture Compare 3 DMA source +* - TIM_DMA_CC4: Capture Compare 4 DMA source +* - TIM_DMA_Trigger: Trigger DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate) +{ + u32 tmpdier = 0; + + /* Check the parameters */ + assert(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpdier = TIMx->DIER; + + if (Newstate != DISABLE) + { + /* Enable the DMA sources */ + tmpdier |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + tmpdier &= (u16)(~TIM_DMASource); + } + TIMx->DIER = (u16)tmpdier; +} + +/******************************************************************************* +* Function Name : TIM_InternalClockConfig +* Description : Configures the TIMx interrnal Clock +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= SMCR_SMS_Mask; +} +/******************************************************************************* +* Function Name : TIM_ITRxExternalClockConfig +* Description : Configures the TIMx Internal Trigger as External Clock +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ITRSource: Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_ITR0: Internal Trigger 0 +* - TIM_TS_ITR1: Internal Trigger 1 +* - TIM_TS_ITR2: Internal Trigger 2 +* - TIM_TS_ITR3: Internal Trigger 3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} +/******************************************************************************* +* Function Name : TIM_TIxExternalClockConfig +* Description : Configures the TIMx Trigger as External Clock +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_TIxExternalCLKSource: Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_TI1F_ED: TI1 Edge Detector +* - TIM_TS_TI1FP1: Filtered Timer Input 1 +* - TIM_TS_TI2FP2: Filtered Timer Input 2 +* - TIM_ICPolarity: specifies the TIx Polarity. +* This parameter can be: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - ICFilter : specifies the filter value. +* This parameter must be a value between 0x0 and 0xF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource, + u16 TIM_ICPolarity, u8 ICFilter) +{ + /* Check the parameters */ + assert(IS_TIM_TIX_TRIGGER_SELECTION(TIM_TIxExternalCLKSource)); + assert(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/******************************************************************************* +* Function Name : TIM_ETRClockMode1Config +* Description : Configures the External clock Mode1 +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8. +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Select the External clock mode1 */ + TIMx->SMCR &= SMCR_SMS_Mask; + TIMx->SMCR |= TIM_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + TIMx->SMCR &= SMCR_TS_Mask; + TIMx->SMCR |= TIM_TS_ETRF; +} + +/******************************************************************************* +* Function Name : TIM_ETRClockMode2Config +* Description : Configures the External clock Mode2 +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8 +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, + u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIMx->SMCR |= SMCR_ECE_Set; +} +/******************************************************************************* +* Function Name : TIM_SelectInputTrigger +* Description : Selects the Input Trigger source +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_InputTriggerSource: The Input Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_ITR0: Internal Trigger 0 +* - TIM_TS_ITR1: Internal Trigger 1 +* - TIM_TS_ITR2: Internal Trigger 2 +* - TIM_TS_ITR3: Internal Trigger 3 +* - TIM_TS_TI1F_ED: TI1 Edge Detector +* - TIM_TS_TI1FP1: Filtered Timer Input 1 +* - TIM_TS_TI2FP2: Filtered Timer Input 2 +* - TIM_TS_ETRF: External Trigger input +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + tmpsmcr = TIMx->SMCR; + + /* Select the Tgigger Source */ + tmpsmcr &= SMCR_TS_Mask; + tmpsmcr |= TIM_InputTriggerSource; + + TIMx->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : Configures the TIMx Prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Prescaler: specifies the Prescaler Register value +* - TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode +* This parameter can be one of the following values: +* - TIM_PSCReloadMode_Update: The Prescaler is loaded at +* the update event. +* - TIM_PSCReloadMode_Immediate: The Prescaler is loaded +* immediatly. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + + /* Set or reset the UG Bit */ + if (TIM_PSCReloadMode == TIM_PSCReloadMode_Immediate) + { + TIMx->EGR |= TIM_EventSource_Update; + } + else + { + TIMx->EGR &= TIM_EventSource_Update; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterModeConfig +* Description : Specifies the TIMx Counter Mode to be used. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - TIM_CounterMode_Up: TIM Up Counting Mode +* - TIM_CounterMode_Down: TIM Down Counting Mode +* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= CR1_CounterMode_Mask; + + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC1Config +* Description : Forces the TIMx output 1 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC1REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC1REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC2Config +* Description : Forces the TIMx output 2 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC2REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC2REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (u16)(TIM_ForcedAction << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC3Config +* Description : Forces the TIMx output 3 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC3REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC3REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC4Config +* Description : Forces the TIMx output 4 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC4REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC4REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (u16)(TIM_ForcedAction << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ARRPreloadConfig +* Description : Enables or disables TIMx peripheral Preload register on ARR. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpcr1 = TIMx->CR1; + + if (Newstate != DISABLE) + { + /* Set the ARR Preload Bit */ + tmpcr1 |= CR1_ARPE_Set; + } + else + { + /* Reset the ARR Preload Bit */ + tmpcr1 &= CR1_ARPE_Reset; + } + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectCCDMA +* Description : Selects the TIMx peripheral Capture Compare DMA source. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the Capture Compare DMA source +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + u32 tmpcr2 = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpcr2 = TIMx->CR2; + + if (Newstate != DISABLE) + { + /* Set the CCDS Bit */ + tmpcr2 |= CR2_CCDS_Set; + } + else + { + /* Reset the CCDS Bit */ + tmpcr2 &= CR2_CCDS_Reset; + } + + TIMx->CR2 = (u16)tmpcr2; +} + +/******************************************************************************* +* Function Name : TIM_OC1PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR1. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCPE Bit */ + tmpccmr1 &= CCMR_OC13PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC2PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR2. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCPE Bit */ + tmpccmr1 &= CCMR_OC24PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (u16)(TIM_OCPreload << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC3PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR3. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCPE Bit */ + tmpccmr2 &= CCMR_OC13PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC4PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR4. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCPE Bit */ + tmpccmr2 &= CCMR_OC24PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (u16)(TIM_OCPreload << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC1FastConfig +* Description : Configures the TIMx Output Compare 1 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCFE Bit */ + tmpccmr1 &= CCMR_OC13FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC2FastConfig +* Description : Configures the TIMx Output Compare 2 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCFE Bit */ + tmpccmr1 &= CCMR_OC24FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (u16)(TIM_OCFast << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC3FastConfig +* Description : Configures the TIMx Output Compare 3 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCFE Bit */ + tmpccmr2 &= CCMR_OC13FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC4FastConfig +* Description : Configures the TIMx Output Compare 4 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCFE Bit */ + tmpccmr2 &= CCMR_OC24FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (u16)(TIM_OCFast << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_UpdateDisableConfig +* Description : Enables or Disables the TIMx Update event. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpcr1 = TIMx->CR1; + + if (Newstate != DISABLE) + { + /* Set the Update Disable Bit */ + tmpcr1 |= CR1_UDIS_Set; + } + else + { + /* Reset the Update Disable Bit */ + tmpcr1 &= CR1_UDIS_Reset; + } + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_EncoderInterfaceConfig +* Description : Configures the TIMx Encoder Interface. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_EncoderMode: specifies the TIMx Encoder Mode. +* This parameter can be one of the following values: +* - TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge +* depending on TI2FP2 level. +* - TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge +* depending on TI1FP1 level. +* - TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and +* TI2FP2 edges depending on the level of the other input. +* - TIM_IC1Polarity: specifies the IC1 Polarity +* This parmeter can be one of the following values: +* - TIM_ICPolarity_Falling +* - TIM_ICPolarity_Rising +* - TIM_IC2Polarity: specifies the IC2 Polarity +* This parmeter can be one of the following values: +* - TIM_ICPolarity_Falling +* - TIM_ICPolarity_Rising +* Output : None +* Return : None +*******************************************************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, + u16 TIM_IC1Polarity, u16 TIM_IC2Polarity) +{ + u32 tmpsmcr = 0; + u32 tmpccmr1 = 0; + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + tmpsmcr = TIMx->SMCR; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= SMCR_SMS_Mask; + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask; + tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= CCER_CC1P_Mask & CCER_CC2P_Mask; + tmpccer |= (TIM_IC1Polarity | (u16)((u16)TIM_IC2Polarity << 4)); + + TIMx->SMCR = (u16)tmpsmcr; + + TIMx->CCMR1 = (u16)tmpccmr1; + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_GenerateEvent +* Description : Configures the TIMx event to be generate by software. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_EventSource: specifies the event source. +* This parameter can be one or more of the following values: +* - TIM_EventSource_Update: Timer update Event source +* - TIM_EventSource_CC1: Timer Capture Compare 1 Event source +* - TIM_EventSource_CC2: Timer Capture Compare 2 Event source +* - TIM_EventSource_CC3: Timer Capture Compare 3 Event source +* - TIM_EventSource_CC4: Timer Capture Compare 4 Event source +* - TIM_EventSource_Trigger: Timer Trigger Event source +* Output : None +* Return : None +*******************************************************************************/ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource) +{ + /* Check the parameters */ + assert(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR |= TIM_EventSource; +} + +/******************************************************************************* +* Function Name : TIM_OC1PolarityConfig +* Description : Configures the TIMx channel 1 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC1 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1P Bit */ + tmpccer &= CCER_CC1P_Mask; + tmpccer |= TIM_OCPolarity; + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC2PolarityConfig +* Description : Configures the TIMx channel 2 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC2 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2P Bit */ + tmpccer &= CCER_CC2P_Mask; + tmpccer |= (u16)((u16)TIM_OCPolarity << 4); + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC3PolarityConfig +* Description : Configures the TIMx channel 3 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC3 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3P Bit */ + tmpccer &= CCER_CC3P_Mask; + tmpccer |= (u16)((u16)TIM_OCPolarity << 8); + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC4PolarityConfig +* Description : Configures the TIMx channel 4 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC4 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC4P Bit */ + tmpccer &= CCER_CC4P_Mask; + tmpccer |= (u16)((u16)TIM_OCPolarity << 12); + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_UpdateRequestConfig +* Description : Configures the TIMx Update Request Interrupt source. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_UpdateSource: specifies the Update source. +* This parameter can be one of the following values: +* - TIM_UpdateSource_Regular +* - TIM_UpdateSource_Global +* Output : None +* Return : None +*******************************************************************************/ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + tmpcr1 = TIMx->CR1; + + if (TIM_UpdateSource == TIM_UpdateSource_Regular) + { + /* Set the URS Bit */ + tmpcr1 |= CR1_URS_Set; + } + else + { + /* Reset the URS Bit */ + tmpcr1 &= CR1_URS_Reset; + } + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectHallSensor +* Description : Enables or disables the TIMxs Hall sensor interface. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the TIMx Hall sensor interface. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + if (Newstate != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= CR2_TI1S_Set; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= CR2_TI1S_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_SelectOnePulseMode +* Description : Selects the TIMxs One Pulse Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OPMode: specifies the OPM Mode to be used. +* This parameter can be one of the following values: +* - TIM_OPMode_Single +* - TIM_OPMode_Repetitive +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OPM_MODE(TIM_OPMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the OPM Bit */ + tmpcr1 &= CR1_OPM_Mask; + + /* Configure the OPM Mode */ + tmpcr1 |= TIM_OPMode; + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectOutputTrigger +* Description : Selects the TIMx Trigger Output Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_TRGOSource: specifies the Trigger Output source. +* This paramter can be one of the following values: +* - TIM_TRGOSource_Reset +* - TIM_TRGOSource_Enable +* - TIM_TRGOSource_Update +* - TIM_TRGOSource_OC1 +* - TIM_TRGOSource_OC1Ref +* - TIM_TRGOSource_OC2Ref +* - TIM_TRGOSource_OC3Ref +* - TIM_TRGOSource_OC4Ref +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource) +{ + u32 tmpcr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + tmpcr2 = TIMx->CR2; + /* Reset the MMS Bits */ + tmpcr2 &= CR2_MMS_Mask; + + /* Select the TRGO source */ + tmpcr2 |= TIM_TRGOSource; + + TIMx->CR2 = (u16)tmpcr2; +} + +/******************************************************************************* +* Function Name : TIM_SelectSlaveMode +* Description : Selects the TIMx Slave Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_SlaveMode: specifies the Timer Slave Mode. +* This paramter can be one of the following values: +* - TIM_SlaveMode_Reset +* - TIM_SlaveMode_Gated +* - TIM_SlaveMode_Trigger +* - TIM_SlaveMode_External1 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + tmpsmcr = TIMx->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= SMCR_SMS_Mask; + + /* Select the Slave Mode */ + tmpsmcr |= TIM_SlaveMode; + + TIMx->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_SelectMasterSlaveMode +* Description : Sets or Resets the TIMx Master/Slave Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. +* This paramter can be one of the following values: +* - TIM_MasterSlaveMode_Enable: synchronization between the +* current timer and its slaves (through TRGO). +* - TIM_MasterSlaveMode_Disable: No action +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + tmpsmcr = TIMx->SMCR; + + /* Set or Reset the MSM Bit */ + tmpsmcr &= SMCR_MSM_Mask; + tmpsmcr |= TIM_MasterSlaveMode; + + TIMx->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_SetAutoreload +* Description : Sets the TIMx Autoreload Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Autoreload: specifies the Autoreload register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload) +{ + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare1 +* Description : Sets the TIMx Capture Compare1 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare1: specifies the Capture Compare1 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1) +{ + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare2 +* Description : Sets the TIMx Capture Compare2 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare2: specifies the Capture Compare2 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2) +{ + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare3 +* Description : Sets the TIMx Capture Compare3 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare3: specifies the Capture Compare3 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3) +{ + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare4 +* Description : Sets the TIMx Capture Compare4 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare4: specifies the Capture Compare4 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4) +{ + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/******************************************************************************* +* Function Name : TIM_SetIC1Prescaler +* Description : Sets the TIMx Input Capture 1 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC1Prescaler: specifies the Input Capture1 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC1Prescaler)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the IC1PSC Bits */ + tmpccmr1 &= CCMR_IC13PSC_Mask; + + /* Set the IC1PSC value */ + tmpccmr1 |= TIM_IC1Prescaler; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_SetIC2Prescaler +* Description : Sets the TIMx Input Capture 2 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC2Prescaler: specifies the Input Capture2 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC2Prescaler)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the IC2PSC Bits */ + tmpccmr1 &= CCMR_IC24PSC_Mask; + + /* Set the IC2PSC value */ + tmpccmr1 |= (u16)((u16)TIM_IC2Prescaler << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_SetIC3Prescaler +* Description : Sets the TIMx Input Capture 3 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC3Prescaler: specifies the Input Capture3 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC3Prescaler)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the IC3PSC Bits */ + tmpccmr2 &= CCMR_IC13PSC_Mask; + + /* Set the IC3PSC value */ + tmpccmr2 |= TIM_IC3Prescaler; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_SetIC4Prescaler +* Description : Sets the TIMx Input Capture 4 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC4Prescaler: specifies the Input Capture4 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC4Prescaler)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the IC4PSC Bits */ + tmpccmr2 &= CCMR_IC24PSC_Mask; + + /* Set the IC4PSC value */ + tmpccmr2 |= (u16)((u16)TIM_IC4Prescaler << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_SetClockDivision +* Description : Sets the TIMx Clock Division value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_CKD: specifies the clock division value. +* This parameter can be one of the following value: +* - TIM_CKD_DIV1: TDTS = Tck_tim +* - TIM_CKD_DIV2: TDTS = 2*Tck_tim +* - TIM_CKD_DIV4: TDTS = 4*Tck_tim +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_CKD_DIV(TIM_CKD)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CKD Bits */ + tmpcr1 &= CR1_CKD_Mask; + + /* Set the CKD value */ + tmpcr1 |= TIM_CKD; + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture1 +* Description : Gets the TIMx Input Capture 1 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 1 Register value. +*******************************************************************************/ +u16 TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture2 +* Description : Gets the TIMx Input Capture 2 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 2 Register value. +*******************************************************************************/ +u16 TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture3 +* Description : Gets the TIMx Input Capture 3 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 3 Register value. +*******************************************************************************/ +u16 TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture4 +* Description : Gets the TIMx Input Capture 4 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 4 Register value. +*******************************************************************************/ +u16 TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/******************************************************************************* +* Function Name : TIM_GetCounter +* Description : Gets the TIMx Counter value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Counter Register value. +*******************************************************************************/ +u16 TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/******************************************************************************* +* Function Name : TIM_GetPrescaler +* Description : Gets the TIMx Prescaler value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Prescaler Register value. +*******************************************************************************/ +u16 TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIMx flag is set or not. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_Update: Timer update Flag +* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag +* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag +* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag +* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag +* - TIM_FLAG_Trigger: Timer Trigger Flag +* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag +* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag +* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag +* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag +* Output : None +* Return : The new state of TIM_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (u16)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIMx's pending flags. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag bit to clear. +* This parameter can be any combination of the following values: +* - TIM_FLAG_Update: Timer update Flag +* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag +* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag +* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag +* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag +* - TIM_FLAG_Trigger: Timer Trigger Flag +* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag +* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag +* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag +* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + /* Check the parameters */ + assert(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR &= (u16)~TIM_FLAG; +} + +/******************************************************************************* +* Function Name : TIM_GetITStatus +* Description : Checks whether the TIMx interrupt has occurred or not. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupt source to check. +* This parameter can be one of the following values: +* - TIM_IT_Update: Timer update Interrupt source +* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source +* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source +* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source +* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source +* - TIM_IT_Trigger: Timer Trigger Interrupt source +* Output : None +* Return : The new state of the TIM_IT(SET or RESET). +*******************************************************************************/ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + ITStatus bitstatus = RESET; + + u16 itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + + if ((itstatus != (u16)RESET) && (itenable != (u16)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM_ClearITPendingBit +* Description : Clears the TIMx's interrupt pending bits. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - TIM_IT_Update: Timer update Interrupt source +* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source +* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source +* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source +* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source +* - TIM_IT_Trigger: Timer Trigger Interrupt source +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + /* Check the parameters */ + assert(IS_TIM_IT(TIM_IT)); + + /* Clear the IT pending Bit */ + TIMx->SR &= (u16)~TIM_IT; +} + +/******************************************************************************* +* Function Name : PWMInput_Config +* Description : Configures the TIM peripheral according to the specified +* parameters in the TIM_ICInitStruct to measure an external PWM +* signal. +* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + u8 ICPolarity = TIM_ICPolarity_Rising; + u8 ICSelection = TIM_ICSelection_DirectTI; + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + ICPolarity = TIM_ICPolarity_Falling; + } + else + { + ICPolarity = TIM_ICPolarity_Rising; + } + + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + ICSelection = TIM_ICSelection_IndirectTI; + } + else + { + ICSelection = TIM_ICSelection_DirectTI; + } + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + + /* TI2 Configuration */ + TI2_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI1 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + + /* TI2 Configuration */ + TI1_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/******************************************************************************* +* Function Name : TI1_Config +* Description : Configure the TI1 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 1 is selected to +* be connected to IC1. +* - TIM_ICSelection_IndirectTI: TIM Input 1 is selected to +* be connected to IC2. +* - TIM_ICSelection_TRGI: TIM Input 1 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr1 = 0, tmpccer = 0; + + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC1E_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr1 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask; + tmpccer |= TIM_ICPolarity | CCRE_CC1E_Set; + + TIMx->CCMR1 = 0x0000; + TIMx->CCMR1 = (u16)tmpccmr1; + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TI2_Config +* Description : Configure the TI2 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 2 is selected to +* be connected to IC2. +* - TIM_ICSelection_IndirectTI: TIM Input 2 is selected to +* be connected to IC1. +* - TIM_ICSelection_TRGI: TIM Input 2 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (u16)((u16)TIM_ICPolarity << 4); + + /* Disable the Channel 2: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC2E_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr1 |= (u16)((u16)TIM_ICFilter << 12); + tmpccmr1 |= (u16)((u16)TIM_ICSelection << 8); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC2P_Mask & CCRE_CC2E_Mask; + tmpccer |= tmp | CCRE_CC2E_Set; + + TIMx->CCMR1 = (u16)tmpccmr1 ; + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TI3_Config +* Description : Configure the TI3 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 3 is selected to +* be connected to IC3. +* - TIM_ICSelection_IndirectTI: TIM Input 3 is selected to +* be connected to IC4. +* - TIM_ICSelection_TRGI: TIM Input 3 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (u16)((u16)TIM_ICPolarity << 8); + + /* Disable the Channel 3: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC3E_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr2 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask; + tmpccer |= tmp | CCRE_CC3E_Set; + + TIMx->CCMR2 = (u16)tmpccmr2; + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TI4_Config +* Description : Configure the TI1 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 4 is selected to +* be connected to IC4. +* - TIM_ICSelection_IndirectTI: TIM Input 4 is selected to +* be connected to IC3. +* - TIM_ICSelection_TRGI: TIM Input 4 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (u16)((u16)TIM_ICPolarity << 12); + + /* Disable the Channel 4: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC4E_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr2 |= (u16)((u16)TIM_ICSelection << 8) | (u16)((u16)TIM_ICFilter << 12); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC4P_Mask & CCRE_CC4E_Mask; + tmpccer |= tmp | CCRE_CC4E_Set; + + TIMx->CCMR2 = (u16)tmpccmr2; + TIMx->CCER = (u16)tmpccer ; +} + +/******************************************************************************* +* Function Name : ETR_Config +* Description : Configure the External Trigger +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8 +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter) +{ + u32 tmpsmcr = 0; + + tmpsmcr = TIMx->SMCR; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr &= SMCR_ETR_Mask; + tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8); + + TIMx->SMCR = (u16)tmpsmcr; +} +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim1.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim1.c new file mode 100644 index 0000000..deac420 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim1.c @@ -0,0 +1,2664 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_tim1.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the TIM1 software functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* mm/dd/yyyy: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim1.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ------------ TIM1 registers bit address in the alias region ----------- */ +#define TIM1_OFFSET (TIM1_BASE - PERIPH_BASE) + +/* --- TIM1 CR1 Register ---*/ +/* Alias word address of CEN bit */ +#define CR1_OFFSET (TIM1_OFFSET + 0x00) +#define CEN_BitNumber 0x00 +#define CR1_CEN_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (CEN_BitNumber * 4)) + +/* Alias word address of UDIS bit */ +#define UDIS_BitNumber 0x01 +#define CR1_UDIS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (UDIS_BitNumber * 4)) + +/* Alias word address of URS bit */ +#define URS_BitNumber 0x02 +#define CR1_URS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (URS_BitNumber * 4)) + +/* Alias word address of OPM bit */ +#define OPM_BitNumber 0x03 +#define CR1_OPM_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (OPM_BitNumber * 4)) + +/* Alias word address of ARPE bit */ +#define ARPE_BitNumber 0x07 +#define CR1_ARPE_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (ARPE_BitNumber * 4)) + +/* --- TIM1 CR2 Register --- */ +/* Alias word address of CCPC bit */ +#define CR2_OFFSET (TIM1_OFFSET + 0x04) +#define CCPC_BitNumber 0x00 +#define CR2_CCPC_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCPC_BitNumber * 4)) + +/* Alias word address of CCUS bit */ +#define CCUS_BitNumber 0x02 +#define CR2_CCUS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCUS_BitNumber * 4)) + +/* Alias word address of CCDS bit */ +#define CCDS_BitNumber 0x03 +#define CR2_CCDS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCDS_BitNumber * 4)) + +/* Alias word address of TI1S bit */ +#define TI1S_BitNumber 0x07 +#define CR2_TI1S_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (TI1S_BitNumber * 4)) + +/* Alias word address of OIS1 bit */ +#define OIS1_BitNumber 0x08 +#define CR2_OIS1_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1_BitNumber * 4)) + +/* Alias word address of OIS1N bit */ +#define OIS1N_BitNumber 0x09 +#define CR2_OIS1N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1N_BitNumber * 4)) + +/* Alias word address of OIS2 bit */ +#define OIS2_BitNumber 0x0A +#define CR2_OIS2_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2_BitNumber * 4)) + +/* Alias word address of OIS2N bit */ +#define OIS2N_BitNumber 0x0B +#define CR2_OIS2N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2N_BitNumber * 4)) + +/* Alias word address of OIS3 bit */ +#define OIS3_BitNumber 0x0C +#define CR2_OIS3_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3_BitNumber * 4)) + +/* Alias word address of OIS3N bit */ +#define OIS3N_BitNumber 0x0D +#define CR2_OIS3N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3N_BitNumber * 4)) + +/* Alias word address of OIS4 bit */ +#define OIS4_BitNumber 0x0E +#define CR2_OIS4_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS4_BitNumber * 4)) + +/* --- TIM1 SMCR Register --- */ +/* Alias word address of MSM bit */ +#define SMCR_OFFSET (TIM1_OFFSET + 0x08) +#define MSM_BitNumber 0x07 +#define SMCR_MSM_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (MSM_BitNumber * 4)) + +/* Alias word address of ECE bit */ +#define ECE_BitNumber 0x0E +#define SMCR_ECE_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (ECE_BitNumber * 4)) + +/* --- TIM1 EGR Register --- */ +/* Alias word address of UG bit */ +#define EGR_OFFSET (TIM1_OFFSET + 0x14) +#define UG_BitNumber 0x00 +#define EGR_UG_BB (PERIPH_BB_BASE + (EGR_OFFSET * 32) + (UG_BitNumber * 4)) + +/* --- TIM1 CCER Register --- */ +/* Alias word address of CC1E bit */ +#define CCER_OFFSET (TIM1_OFFSET + 0x20) +#define CC1E_BitNumber 0x00 +#define CCER_CC1E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1E_BitNumber * 4)) + +/* Alias word address of CC1P bit */ +#define CC1P_BitNumber 0x01 +#define CCER_CC1P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1P_BitNumber * 4)) + +/* Alias word address of CC1NE bit */ +#define CC1NE_BitNumber 0x02 +#define CCER_CC1NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NE_BitNumber * 4)) + +/* Alias word address of CC1NP bit */ +#define CC1NP_BitNumber 0x03 +#define CCER_CC1NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NP_BitNumber * 4)) + +/* Alias word address of CC2E bit */ +#define CC2E_BitNumber 0x04 +#define CCER_CC2E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2E_BitNumber * 4)) + +/* Alias word address of CC2P bit */ +#define CC2P_BitNumber 0x05 +#define CCER_CC2P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2P_BitNumber * 4)) + +/* Alias word address of CC2NE bit */ +#define CC2NE_BitNumber 0x06 +#define CCER_CC2NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NE_BitNumber * 4)) + +/* Alias word address of CC2NP bit */ +#define CC2NP_BitNumber 0x07 +#define CCER_CC2NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NP_BitNumber * 4)) + +/* Alias word address of CC3E bit */ +#define CC3E_BitNumber 0x08 +#define CCER_CC3E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3E_BitNumber * 4)) + +/* Alias word address of CC3P bit */ +#define CC3P_BitNumber 0x09 +#define CCER_CC3P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3P_BitNumber * 4)) + +/* Alias word address of CC3NE bit */ +#define CC3NE_BitNumber 0x0A +#define CCER_CC3NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NE_BitNumber * 4)) + +/* Alias word address of CC3NP bit */ +#define CC3NP_BitNumber 0x0B +#define CCER_CC3NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NP_BitNumber * 4)) + +/* Alias word address of CC4E bit */ +#define CC4E_BitNumber 0x0C +#define CCER_CC4E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4E_BitNumber * 4)) + +/* Alias word address of CC4P bit */ +#define CC4P_BitNumber 0x0D +#define CCER_CC4P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4P_BitNumber * 4)) + +/* --- TIM1 BDTR Register --- */ +/* Alias word address of MOE bit */ +#define BDTR_OFFSET (TIM1_OFFSET + 0x44) +#define MOE_BitNumber 0x0F +#define BDTR_MOE_BB (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4)) + +/* --- TIM1 CCMR1 Register --- */ +/* Alias word address of OC1FE bit */ +#define CCMR1_OFFSET (TIM1_OFFSET + 0x18) +#define OC1FE_BitNumber 0x02 +#define CCMR1_OC1FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4)) + +/* Alias word address of OC1PE bit */ +#define OC1PE_BitNumber 0x03 +#define CCMR1_OC1PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4)) + +/* Alias word address of OC2FE bit */ +#define OC2FE_BitNumber 0x0A +#define CCMR1_OC2FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE_BitNumber * 4)) + +/* Alias word address of OC2PE bit */ +#define OC2PE_BitNumber 0x0B +#define CCMR1_OC2PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2PE_BitNumber * 4)) + +/* --- TIM1 CCMR2 Register ---- */ +/* Alias word address of OC3FE bit */ +#define CCMR2_OFFSET (TIM1_OFFSET + 0x1C) +#define OC3FE_BitNumber 0x02 +#define CCMR2_OC3FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3FE_BitNumber * 4)) + +/* Alias word address of OC3PE bit */ +#define OC3PE_BitNumber 0x03 +#define CCMR2_OC3PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3PE_BitNumber * 4)) + +/* Alias word address of OC4FE bit */ +#define OC4FE_BitNumber 0x0A +#define CCMR2_OC4FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4FE_BitNumber * 4)) + +/* Alias word address of OC4PE bit */ +#define OC4PE_BitNumber 0x0B +#define CCMR2_OC4PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4PE_BitNumber * 4)) + +/* --------------------- TIM1 registers bit mask ------------------------- */ +/* TIM1 CR1 Mask */ +#define CR1_CounterMode_Mask ((u16)0x039F) +#define CR1_CKD_Mask ((u16)0x00FF) + +/* TIM1 CR2 Mask */ +#define CR2_MMS_Mask ((u16)0x0080) + +/* TIM1 SMCR Mask */ +#define SMCR_SMS_Mask ((u16)0xFFF0) +#define SMCR_ETR_Mask ((u16)0x40F7) +#define SMCR_TS_Mask ((u16)0xFF87) +#define SMCR_ECE_Set ((u16)0x0001) + +/* TIM1 CCMRx Mask */ +#define CCMR_CC13S_Mask ((u16)0xFFFC) +#define CCMR_CC24S_Mask ((u16)0xFCFF) +#define CCMR_TI13Direct_Set ((u16)0x0001) +#define CCMR_TI24Direct_Set ((u16)0x0100) +#define CCMR_OCM13_Mask ((u16)0x7F0F) +#define CCMR_OCM24_Mask ((u16)0x0F7F) +#define CCMR_IC13PSC_Mask ((u16)0xFFF3) +#define CCMR_IC24PSC_Mask ((u16)0xF3FF) +#define CCMR_IC13F_Mask ((u16)0xFF0F) +#define CCMR_IC24F_Mask ((u16)0x0FFF) +#define OC13Mode_Mask ((u16)0xFF00) +#define OC24Mode_Mask ((u16)0x00FF) + +/* TIM1 CCER Set/Reset Bit */ +#define CCER_CCE_Set ((u16)0x0001) +#define CCER_CCE_Reset ((u16)0x0000) + +/* TIM1 DMA Mask */ +#define DCR_DMA_Mask ((u16)0x0000) + +/* TIM1 private Masks */ +#define TIM1_Period_Reset_Mask ((u16)0xFFFF) +#define TIM1_Prescaler_Reset_Mask ((u16)0x0000) +#define TIM1_RepetitionCounter_Reset_Mask ((u16)0x0000) +#define TIM1_Pulse_Reset_Mask ((u16)0x0000) +#define TIM1_ICFilter_Mask ((u8)0x00) +#define TIM1_DeadTime_Reset_Mask ((u16)0x0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter); +static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter); +static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter); +static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter); +static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter); + +/******************************************************************************* +* Function Name : TIM1_DeInit +* Description : Deinitializes the TIM1 peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); +} + +/******************************************************************************* +* Function Name : TIM1_TimeBaseInit +* Description : Initializes the TIM1 Time Base Unit according to the specified +* parameters in the TIM1_TimeBaseInitStruct. +* Input : - TIM1_TimeBaseInitStruct: pointer to a TIM1_TimeBaseInitTypeDef +* structure that contains the configuration information for +* the specified TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM1_COUNTER_MODE(TIM1_TimeBaseInitStruct->TIM1_CounterMode)); + assert(IS_TIM1_CKD_DIV(TIM1_TimeBaseInitStruct->TIM1_ClockDivision)); + + /* Set the Autoreload value */ + TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ; + + /* Set the Prescaler value */ + TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler; + + /* Select the Counter Mode and set the clock division */ + TIM1->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; + TIM1->CR1 |= (u32)TIM1_TimeBaseInitStruct->TIM1_ClockDivision | + TIM1_TimeBaseInitStruct->TIM1_CounterMode; + + /* Set the Repetition Counter value */ + TIM1->RCR = TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter; +} + +/******************************************************************************* +* Function Name : TIM1_OC1Init +* Description : Initializes the TIM1 Channel1 according to the specified +* parameters in the TIM1_OCInitStruct. +* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that +* contains the configuration information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + u16 tmpccmr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode)); + assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState)); + assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState)); + assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity)); + assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity)); + assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState)); + assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState)); + + tmpccmr = TIM1->CCMR1; + + /* Disable the Channel 1: Reset the CCE Bit */ + *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + tmpccmr &= OC13Mode_Mask; + + /* Set the Ouput Compare Mode */ + tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode; + + TIM1->CCMR1 = tmpccmr; + + /* Set the Output State */ + *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState; + + /* Set the Output N State */ + *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState; + + /* Set the Output Polarity */ + *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity; + + /* Set the Output N Polarity */ + *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity; + + /* Set the Output Idle state */ + *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState; + + /* Set the Output N Idle state */ + *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState; + + /* Set the Pulse value */ + TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse; +} + +/******************************************************************************* +* Function Name : TIM1_OC2Init +* Description : Initializes the TIM1 Channel2 according to the specified +* parameters in the TIM1_OCInitStruct. +* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that +* contains the configuration information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + u32 tmpccmr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode)); + assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState)); + assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState)); + assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity)); + assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity)); + assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState)); + assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState)); + + tmpccmr = TIM1->CCMR1; + + /* Disable the Channel 2: Reset the CCE Bit */ + *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + tmpccmr &= OC24Mode_Mask; + + /* Set the Ouput Compare Mode */ + tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8; + + TIM1->CCMR1 = (u16)tmpccmr; + + /* Set the Output State */ + *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState; + + /* Set the Output N State */ + *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState; + + /* Set the Output Polarity */ + *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity; + + /* Set the Output N Polarity */ + *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity; + + /* Set the Output Idle state */ + *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState; + + /* Set the Output N Idle state */ + *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState; + + /* Set the Pulse value */ + TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse; +} + +/******************************************************************************* +* Function Name : TIM1_OC3Init +* Description : Initializes the TIM1 Channel3 according to the specified +* parameters in the TIM1_OCInitStruct. +* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that +* contains the configuration information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + u16 tmpccmr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode)); + assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState)); + assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState)); + assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity)); + assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity)); + assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState)); + assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState)); + + tmpccmr = TIM1->CCMR2; + + /* Disable the Channel 3: Reset the CCE Bit */ + *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + tmpccmr &= OC13Mode_Mask; + + /* Set the Ouput Compare Mode */ + tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode; + + TIM1->CCMR2 = tmpccmr; + + /* Set the Output State */ + *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState; + + /* Set the Output N State */ + *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState; + + /* Set the Output Polarity */ + *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity; + + /* Set the Output N Polarity */ + *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity; + + /* Set the Output Idle state */ + *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState; + + /* Set the Output N Idle state */ + *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState; + + /* Set the Pulse value */ + TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse; +} + +/******************************************************************************* +* Function Name : TIM1_OC4Init +* Description : Initializes the TIM1 Channel4 according to the specified +* parameters in the TIM1_OCInitStruct. +* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that +* contains the configuration information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + u32 tmpccmr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode)); + assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState)); + assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity)); + assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState)); + + tmpccmr = TIM1->CCMR2; + + /* Disable the Channel 4: Reset the CCE Bit */ + *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + tmpccmr &= OC24Mode_Mask; + + /* Set the Ouput Compare Mode */ + tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8; + + TIM1->CCMR2 = (u16)tmpccmr; + + /* Set the Output State */ + *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState; + + /* Set the Output Polarity */ + *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity; + + /* Set the Output Idle state */ + *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState; + + /* Set the Pulse value */ + TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse; +} + +/******************************************************************************* +* Function Name : TIM1_BDTRConfig +* Description : Configures the: Break feature, dead time, Lock level, the OSSI, +* the OSSR State and the AOE(automatic output enable). +* Input : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef +* structure that contains the BDTR Register configuration +* information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct) +{ + u16 tmpbdtr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState)); + assert(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState)); + assert(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel)); + assert(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break)); + assert(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity)); + assert(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput)); + + tmpbdtr = TIM1->BDTR; + + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState | + TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime | + TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity | + TIM1_BDTRInitStruct->TIM1_AutomaticOutput; + + TIM1->BDTR = tmpbdtr; +} + +/******************************************************************************* +* Function Name : TIM1_ICInit +* Description : Initializes the TIM1 peripheral according to the specified +* parameters in the TIM1_ICInitStruct. +* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel)); + assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity)); + assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection)); + assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler)); + assert(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter)); + + if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity, + TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } + else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2) + { + /* TI2 Configuration */ + TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity, + TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } + else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_3) + { + /* TI3 Configuration */ + TI3_Config(TIM1_ICInitStruct->TIM1_ICPolarity, + TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC3Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } + else + { + /* TI4 Configuration */ + TI4_Config(TIM1_ICInitStruct->TIM1_ICPolarity, + TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC4Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } +} + +/******************************************************************************* +* Function Name : TIM1_PWMIConfig +* Description : Configures the TIM1 peripheral in PWM Input Mode according +* to the specified parameters in the TIM1_ICInitStruct. +* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct) +{ + u8 ICPolarity = TIM1_ICPolarity_Rising; + u8 ICSelection = TIM1_ICSelection_DirectTI; + + /* Check the parameters */ + assert(IS_TIM1_PWMI_CHANNEL(TIM1_ICInitStruct->TIM1_Channel)); + assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity)); + assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection)); + assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler)); + + /* Select the Opposite Input Polarity */ + if (TIM1_ICInitStruct->TIM1_ICPolarity == TIM1_ICPolarity_Rising) + { + ICPolarity = TIM1_ICPolarity_Falling; + } + else + { + ICPolarity = TIM1_ICPolarity_Rising; + } + + /* Select the Opposite Input */ + if (TIM1_ICInitStruct->TIM1_ICSelection == TIM1_ICSelection_DirectTI) + { + ICSelection = TIM1_ICSelection_IndirectTI; + } + else + { + ICSelection = TIM1_ICSelection_DirectTI; + } + + if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + + /* TI2 Configuration */ + TI2_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + + /* TI1 Configuration */ + TI1_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } +} +/******************************************************************************* +* Function Name : TIM1_OCStructInit +* Description : Fills each TIM1_OCInitStruct member with its default value. +* Input : - TIM1_OCInitStruct : pointer to a TIM1_OCInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + /* Set the default configuration */ + TIM1_OCInitStruct->TIM1_OCMode = TIM1_OCMode_Timing; + TIM1_OCInitStruct->TIM1_OutputState = TIM1_OutputState_Disable; + TIM1_OCInitStruct->TIM1_OutputNState = TIM1_OutputNState_Disable; + TIM1_OCInitStruct->TIM1_Pulse = TIM1_Pulse_Reset_Mask; + TIM1_OCInitStruct->TIM1_OCPolarity = TIM1_OCPolarity_High; + TIM1_OCInitStruct->TIM1_OCNPolarity = TIM1_OCPolarity_High; + TIM1_OCInitStruct->TIM1_OCIdleState = TIM1_OCIdleState_Reset; + TIM1_OCInitStruct->TIM1_OCNIdleState = TIM1_OCNIdleState_Reset; +} + +/******************************************************************************* +* Function Name : TIM1_ICStructInit +* Description : Fills each TIM1_ICInitStruct member with its default value. +* Input : - TIM1_ICInitStruct : pointer to a TIM1_ICInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct) +{ + /* Set the default configuration */ + TIM1_ICInitStruct->TIM1_Channel = TIM1_Channel_1; + TIM1_ICInitStruct->TIM1_ICSelection = TIM1_ICSelection_DirectTI; + TIM1_ICInitStruct->TIM1_ICPolarity = TIM1_ICPolarity_Rising; + TIM1_ICInitStruct->TIM1_ICPrescaler = TIM1_ICPSC_DIV1; + TIM1_ICInitStruct->TIM1_ICFilter = TIM1_ICFilter_Mask; +} + +/******************************************************************************* +* Function Name : TIM1_TimeBaseStructInit +* Description : Fills each TIM1_TimeBaseInitStruct member with its default value. +* Input : - TIM1_TimeBaseInitStruct : pointer to a TIM1_TimeBaseInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM1_TimeBaseInitStruct->TIM1_Period = TIM1_Period_Reset_Mask; + TIM1_TimeBaseInitStruct->TIM1_Prescaler = TIM1_Prescaler_Reset_Mask; + TIM1_TimeBaseInitStruct->TIM1_ClockDivision = TIM1_CKD_DIV1; + TIM1_TimeBaseInitStruct->TIM1_CounterMode = TIM1_CounterMode_Up; + TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter = TIM1_RepetitionCounter_Reset_Mask; +} + +/******************************************************************************* +* Function Name : TIM1_BDTRStructInit +* Description : Fills each TIM1_BDTRInitStruct member with its default value. +* Input : - TIM1_BDTRInitStruct : pointer to a TIM1_BDTRInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM1_BDTRInitStruct->TIM1_OSSRState = TIM1_OSSRState_Disable; + TIM1_BDTRInitStruct->TIM1_OSSIState = TIM1_OSSIState_Disable; + TIM1_BDTRInitStruct->TIM1_LOCKLevel = TIM1_LOCKLevel_OFF; + TIM1_BDTRInitStruct->TIM1_DeadTime = TIM1_DeadTime_Reset_Mask; + TIM1_BDTRInitStruct->TIM1_Break = TIM1_Break_Disable; + TIM1_BDTRInitStruct->TIM1_BreakPolarity = TIM1_BreakPolarity_Low; + TIM1_BDTRInitStruct->TIM1_AutomaticOutput = TIM1_AutomaticOutput_Disable; +} + +/******************************************************************************* +* Function Name : TIM1_Cmd +* Description : Enables or disables the TIM1 peripheral. +* Input : - Newstate: new state of the TIM1 peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + /* set or Reset the CEN Bit */ + *(vu32 *) CR1_CEN_BB = (u16)NewState; +} + +/******************************************************************************* +* Function Name : TIM1_CtrlPWMOutputs +* Description : Enables or disables the TIM1 peripheral Main Outputs. +* Input : - Newstate: new state of the TIM1 peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CtrlPWMOutputs(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the MOE Bit */ + *(vu32 *) BDTR_MOE_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_ITConfig +* Description : Enables or disables the specified TIM1 interrupts. +* Input : - TIM1_IT: specifies the TIM1 interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - TIM1_IT_Update: TIM1 update Interrupt source +* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source +* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source +* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source +* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source +* - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt +* source +* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source +* - TIM1_IT_Break: TIM1 Break Interrupt source +* - Newstate: new state of the TIM1 interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_TIM1_IT(TIM1_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + /* Enable the Interrupt sources */ + TIM1->DIER |= TIM1_IT; + } + else + { + /* Disable the Interrupt sources */ + TIM1->DIER &= (u16)~TIM1_IT; + } +} + +/******************************************************************************* +* Function Name : TIM1_DMAConfig +* Description : Configures the TIM1s DMA interface. +* Input : - TIM1_DMABase: DMA Base address. +* This parameter can be one of the following values: +* - TIM1_DMABase_CR1, TIM1_DMABase_CR2, TIM1_DMABase_SMCR, +* TIM1_DMABase_DIER, TIM1_DMABase_SR, TIM1_DMABase_EGR, +* TIM1_DMABase_CCMR1, TIM1_DMABase_CCMR2, TIM1_DMABase_CCER, +* TIM1_DMABase_CNT, TIM1_DMABase_PSC, TIM1_DMABase_ARR, +* TIM1_DMABase_RCR, TIM1_DMABase_CCR1, TIM1_DMABase_CCR2, +* TIM1_DMABase_CCR3, TIM1_DMABase_CCR4, TIM1_DMABase_BDTR, +* TIM1_DMABase_DCR. +* - TIM1_DMABurstLength: DMA Burst length. +* This parameter can be one value between: +* TIM1_DMABurstLength_1Byte and TIM1_DMABurstLength_18Bytes. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength) +{ + u32 tmpdcr = 0; + + /* Check the parameters */ + assert(IS_TIM1_DMA_BASE(TIM1_DMABase)); + assert(IS_TIM1_DMA_LENGTH(TIM1_DMABurstLength)); + + tmpdcr = TIM1->DCR; + + /* Reset the DBA and the DBL Bits */ + tmpdcr &= DCR_DMA_Mask; + + /* Set the DMA Base and the DMA Burst Length */ + tmpdcr |= TIM1_DMABase | TIM1_DMABurstLength; + + TIM1->DCR = (u16)tmpdcr; +} + +/******************************************************************************* +* Function Name : TIM1_DMACmd +* Description : Enables or disables the TIM1s DMA Requests. +* Input : - TIM1_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM1_DMA_Update: TIM1 update Interrupt source +* - TIM1_DMA_CC1: TIM1 Capture Compare 1 DMA source +* - TIM1_DMA_CC2: TIM1 Capture Compare 2 DMA source +* - TIM1_DMA_CC3: TIM1 Capture Compare 3 DMA source +* - TIM1_DMA_CC4: TIM1 Capture Compare 4 DMA source +* - TIM1_DMA_COM: TIM1 Capture Compare Update DMA +* source +* - TIM1_DMA_Trigger: TIM1 Trigger DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate) +{ + u32 tmpdier = 0; + + /* Check the parameters */ + assert(IS_TIM1_DMA_SOURCE(TIM1_DMASource)); + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpdier = TIM1->DIER; + + if (Newstate == ENABLE) + { + /* Enable the DMA sources */ + tmpdier |= TIM1_DMASource; + } + else + { + /* Disable the DMA sources */ + tmpdier &= (u16)~TIM1_DMASource; + } + TIM1->DIER = (u16)tmpdier; +} + +/******************************************************************************* +* Function Name : TIM1_InternalClockConfig +* Description : Configures the TIM1 interrnal Clock +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_InternalClockConfig(void) +{ + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIM1->SMCR &= SMCR_SMS_Mask; +} +/******************************************************************************* +* Function Name : TIM1_ETRClockMode1Config +* Description : Configures the TIM1 External clock Mode1 +* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM1_ExtTRGPSC_OFF +* - TIM1_ExtTRGPSC_DIV2 +* - TIM1_ExtTRGPSC_DIV4 +* - TIM1_ExtTRGPSC_DIV8. +* - TIM1_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM1_ExtTRGPolarity_Inverted +* - TIM1_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler)); + assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter); + + /* Select the External clock mode1 */ + TIM1->SMCR &= SMCR_SMS_Mask; + TIM1->SMCR |= TIM1_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + TIM1->SMCR &= SMCR_TS_Mask; + TIM1->SMCR |= TIM1_TS_ETRF; +} + +/******************************************************************************* +* Function Name : TIM1_ETRClockMode2Config +* Description : Configures the TIM1 External clock Mode2 +* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM1_ExtTRGPSC_OFF +* - TIM1_ExtTRGPSC_DIV2 +* - TIM1_ExtTRGPSC_DIV4 +* - TIM1_ExtTRGPSC_DIV8 +* - TIM1_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM1_ExtTRGPolarity_Inverted +* - TIM1_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler)); + assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + *(vu32 *) SMCR_ECE_BB = SMCR_ECE_Set; +} + +/******************************************************************************* +* Function Name : TIM1_ITRxExternalClockConfig +* Description : Configures the TIM1 Internal Trigger as External Clock +* Input : - TIM1_ITRSource: Internal Trigger source. +* This parameter can be one of the following values: +* - TIM1_TS_ITR0: Internal Trigger 0 +* - TIM1_TS_ITR1: Internal Trigger 1 +* - TIM1_TS_ITR2: Internal Trigger 2 +* - TIM1_TS_ITR3: Internal Trigger 3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource) +{ + /* Check the parameters */ + assert(IS_TIM1_INTERNAL_TRIGGER_SELECTION(TIM1_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM1_SelectInputTrigger(TIM1_InputTriggerSource); + + /* Select the External clock mode1 */ + TIM1->SMCR |= TIM1_SlaveMode_External1; +} + +/******************************************************************************* +* Function Name : TIM1_TIxExternalClockConfig +* Description : Configures the TIM1 Trigger as External Clock +* Input : - TIM1_TIxExternalCLKSource: Trigger source. +* This parameter can be one of the following values: +* - TIM1_TS_TI1F_ED: TI1 Edge Detector +* - TIM1_TS_TI1FP1: Filtered TIM1 Input 1 +* - TIM1_TS_TI2FP2: Filtered TIM1 Input 2 +* - TIM1_ICPolarity: specifies the TIx Polarity. +* This parameter can be: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - ICFilter : specifies the filter value. +* This parameter must be a value between 0x0 and 0xF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, + u16 TIM1_ICPolarity, u8 ICFilter) +{ + /* Check the parameters */ + assert(IS_TIM1_TIX_TRIGGER_SELECTION(TIM1_TIxExternalCLKSource)); + assert(IS_TIM1_IC_POLARITY(TIM1_ICPolarity)); + assert(IS_TIM1_IC_FILTER(ICFilter)); + + /* Configure the TIM1 Input Clock Source */ + if (TIM1_TIxExternalCLKSource == TIM1_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter); + } + + /* Select the Trigger source */ + TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource); + + /* Select the External clock mode1 */ + TIM1->SMCR |= TIM1_SlaveMode_External1; +} +/******************************************************************************* +* Function Name : TIM1_SelectInputTrigger +* Description : Selects the TIM1 Input Trigger source +* Input : - TIM1_InputTriggerSource: The Trigger source. +* This parameter can be one of the following values: +* - TIM1_TS_ITR0: Internal Trigger 0 +* - TIM1_TS_ITR1: Internal Trigger 1 +* - TIM1_TS_ITR2: Internal Trigger 2 +* - TIM1_TS_ITR3: Internal Trigger 3 +* - TIM1_TS_TI1F_ED: TI1 Edge Detector +* - TIM1_TS_TI1FP1: Filtered Timer Input 1 +* - TIM1_TS_TI2FP2: Filtered Timer Input 2 +* - TIM1_TS_ETRF: External Trigger input +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM1_TRIGGER_SELECTION(TIM1_InputTriggerSource)); + + tmpsmcr = TIM1->SMCR; + + /* Select the Tgigger Source */ + tmpsmcr &= SMCR_TS_Mask; + tmpsmcr |= TIM1_InputTriggerSource; + + TIM1->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM1_UpdateDisableConfig +* Description : Enables or Disables the TIM1 Update event. +* Input : - Newstate: new state of the TIM1 peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_UpdateDisableConfig(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the UDIS Bit */ + *(vu32 *) CR1_UDIS_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_UpdateRequestConfig +* Description : Selects the TIM1 Update Request Interrupt source. +* Input : - TIM1_UpdateSource: specifies the Update source. +* This parameter can be one of the following values: +* - TIM1_UpdateSource_Regular +* - TIM1_UpdateSource_Global +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource) +{ + /* Check the parameters */ + assert(IS_TIM1_UPDATE_SOURCE(TIM1_UpdateSource)); + + /* Set or Reset the URS Bit */ + *(vu32 *) CR1_URS_BB = TIM1_UpdateSource; +} + +/******************************************************************************* +* Function Name : TIM1_SelectHallSensor +* Description : Enables or disables the TIM1s Hall sensor interface. +* Input : - Newstate: new state of the TIM1 Hall sensor interface +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectHallSensor(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the TI1S Bit */ + *(vu32 *) CR2_TI1S_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_SelectOPM +* Description : Enables or disables the TIM1s One Pulse Mode. +* Input : - TIM1_OPMode: specifies the OPM Mode to be used. +* This parameter can be one of the following values: +* - TIM1_OPMode_Single +* - TIM1_OPMode_Repetitive +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectOnePulseMode(u16 TIM1_OPMode) +{ + /* Check the parameters */ + assert(IS_TIM1_OPM_MODE(TIM1_OPMode)); + + /* Set or Reset the OPM Bit */ + *(vu32 *) CR1_OPM_BB = TIM1_OPMode; +} + +/******************************************************************************* +* Function Name : TIM1_SelectOutputTrigger +* Description : Selects the TIM1 Trigger Output Mode. +* Input : - TIM1_TRGOSource: specifies the Trigger Output source. +* This paramter can be one of the following values: +* - TIM1_TRGOSource_Reset +* - TIM1_TRGOSource_Enable +* - TIM1_TRGOSource_Update +* - TIM1_TRGOSource_OC1 +* - TIM1_TRGOSource_OC1Ref +* - TIM1_TRGOSource_OC2Ref +* - TIM1_TRGOSource_OC3Ref +* - TIM1_TRGOSource_OC4Ref +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource) +{ + u32 tmpcr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_TRGO_SOURCE(TIM1_TRGOSource)); + + tmpcr2 = TIM1->CR2; + + /* Reset the MMS Bits */ + tmpcr2 &= CR2_MMS_Mask; + + /* Select the TRGO source */ + tmpcr2 |= TIM1_TRGOSource; + + TIM1->CR2 = (u16)tmpcr2; +} + +/******************************************************************************* +* Function Name : TIM1_SelectSlaveMode +* Description : Selects the TIM1 Slave Mode. +* Input : - TIM1_SlaveMode: specifies the TIM1 Slave Mode. +* This paramter can be one of the following values: +* - TIM1_SlaveMode_Reset +* - TIM1_SlaveMode_Gated +* - TIM1_SlaveMode_Trigger +* - TIM1_SlaveMode_External1 +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM1_SLAVE_MODE(TIM1_SlaveMode)); + + tmpsmcr = TIM1->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= SMCR_SMS_Mask; + + /* Select the Slave Mode */ + tmpsmcr |= TIM1_SlaveMode; + + TIM1->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM1_SelectMasterSlaveMode +* Description : Sets or Resets the TIM1 Master/Slave Mode. +* Input : - TIM1_MasterSlaveMode: specifies the TIM1 Master Slave Mode. +* This paramter can be one of the following values: +* - TIM1_MasterSlaveMode_Enable: synchronization between +* the current timer and its slaves (through TRGO). +* - TIM1_MasterSlaveMode_Disable: No action +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode) +{ + /* Check the parameters */ + assert(IS_TIM1_MSM_STATE(TIM1_MasterSlaveMode)); + + /* Set or Reset the MSM Bit */ + *(vu32 *) SMCR_MSM_BB = TIM1_MasterSlaveMode; +} + +/******************************************************************************* +* Function Name : TIM1_EncoderInterfaceConfig +* Description : Configures the TIM1 Encoder Interface. +* Input : - TIM1_EncoderMode: specifies the TIM1 Encoder Mode. +* This parameter can be one of the following values: +* - TIM1_EncoderMode_TI1: Counter counts on TI1FP1 edge +* depending on TI2FP2 level. +* - TIM1_EncoderMode_TI2: Counter counts on TI2FP2 edge +* depending on TI1FP1 level. +* - TIM1_EncoderMode_TI12: Counter counts on both TI1FP1 and +* TI2FP2 edges depending on the level of the other input. +* - TIM1_IC1Polarity: specifies the IC1 Polarity +* This parmeter can be one of the following values: +* - TIM1_ICPolarity_Falling +* - TIM1_ICPolarity_Rising +* - TIM1_IC2Polarity: specifies the IC2 Polarity +* This parmeter can be one of the following values: +* - TIM1_ICPolarity_Falling +* - TIM1_ICPolarity_Rising +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity, + u16 TIM1_IC2Polarity) +{ + u32 tmpsmcr = 0; + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_ENCODER_MODE(TIM1_EncoderMode)); + assert(IS_TIM1_IC_POLARITY(TIM1_IC1Polarity)); + assert(IS_TIM1_IC_POLARITY(TIM1_IC2Polarity)); + + tmpsmcr = TIM1->SMCR; + tmpccmr1 = TIM1->CCMR1; + + /* Set the encoder Mode */ + tmpsmcr &= SMCR_SMS_Mask; + tmpsmcr |= TIM1_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask; + tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; + + /* Set the TI1 and the TI2 Polarities */ + *(vu32 *) CCER_CC1P_BB = TIM1_IC1Polarity; + *(vu32 *) CCER_CC2P_BB = TIM1_IC2Polarity; + + TIM1->SMCR = (u16)tmpsmcr; + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_PrescalerConfig +* Description : Configures the TIM1 Prescaler. +* Input : - Prescaler: specifies the Prescaler Register value +* - TIM1_PSCReloadMode: specifies the TIM1 Prescaler Reload mode. +* This parmeter can be one of the following values: +* - TIM1_PSCReloadMode_Update: The Prescaler is loaded at +* the update event. +* - TIM1_PSCReloadMode_Immediate: The Prescaler is loaded +* immediatly. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode) +{ + /* Check the parameters */ + assert(IS_TIM1_PRESCALER_RELOAD(TIM1_PSCReloadMode)); + + /* Set the Prescaler value */ + TIM1->PSC = Prescaler; + + /* Set or reset the UG Bit */ + *(vu32 *) EGR_UG_BB = TIM1_PSCReloadMode; +} +/******************************************************************************* +* Function Name : TIM1_CounterModeConfig +* Description : Specifies the TIM1 Counter Mode to be used. +* Input : - TIM1_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - TIM1_CounterMode_Up: TIM1 Up Counting Mode +* - TIM1_CounterMode_Down: TIM1 Down Counting Mode +* - TIM1_CounterMode_CenterAligned1: TIM1 Center Aligned Mode1 +* - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2 +* - TIM1_CounterMode_CenterAligned3: TIM1 Center Aligned Mode3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CounterModeConfig(u16 TIM1_CounterMode) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_COUNTER_MODE(TIM1_CounterMode)); + + tmpcr1 = TIM1->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= CR1_CounterMode_Mask; + + /* Set the Counter Mode */ + tmpcr1 |= TIM1_CounterMode; + + TIM1->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM1_ForcedOC1Config +* Description : Forces the TIM1 Channel1 output waveform to active or inactive +* level. +* Input : - TIM1_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM1_ForcedAction_Active: Force active level on OC1REF +* - TIM1_ForcedAction_InActive: Force inactive level on +* OC1REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); + + tmpccmr1 = TIM1->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM1_ForcedAction; + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_ForcedOC2Config +* Description : Forces the TIM1 Channel2 output waveform to active or inactive +* level. +* Input : - TIM1_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM1_ForcedAction_Active: Force active level on OC2REF +* - TIM1_ForcedAction_InActive: Force inactive level on +* OC2REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); + + tmpccmr1 = TIM1->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (u32)TIM1_ForcedAction << 8; + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_ForcedOC3Config +* Description : Forces the TIM1 Channel3 output waveform to active or inactive +* level. +* Input : - TIM1_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM1_ForcedAction_Active: Force active level on OC3REF +* - TIM1_ForcedAction_InActive: Force inactive level on +* OC3REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); + + tmpccmr2 = TIM1->CCMR2; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM1_ForcedAction; + + TIM1->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM1_ForcedOC4Config +* Description : Forces the TIM1 Channel4 output waveform to active or inactive +* level. +* Input : - TIM1_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM1_ForcedAction_Active: Force active level on OC4REF +* - TIM1_ForcedAction_InActive: Force inactive level on +* OC4REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); + + tmpccmr2 = TIM1->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (u16)((u16)TIM1_ForcedAction << 8); + + TIM1->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM1_ARRPreloadConfig +* Description : Enables or disables TIM1 peripheral Preload register on ARR. +* Input : - Newstate: new state of the TIM1 peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ARRPreloadConfig(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the ARPE Bit */ + *(vu32 *) CR1_ARPE_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_SelectCOM +* Description : Selects the TIM1 peripheral Commutation event. +* Input : - Newstate: new state of the Commutation event. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectCOM(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the CCUS Bit */ + *(vu32 *) CR2_CCUS_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_SelectCCDMA +* Description : Selects the TIM1 peripheral Capture Compare DMA source. +* Input : - Newstate: new state of the Capture Compare DMA source +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectCCDMA(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the CCDS Bit */ + *(vu32 *) CR2_CCDS_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_CCPreloadControl +* Description : Sets or Resets the TIM1 peripheral Capture Compare Preload +* Control bit. +* Input : - Newstate: new state of the Capture Compare Preload Control bit +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CCPreloadControl(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the CCPC Bit */ + *(vu32 *) CR2_CCPC_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_OC1PreloadConfig +* Description : Enables or disables the TIM1 peripheral Preload Register on CCR1. +* Input : - TIM1_OCPreload: new state of the Capture Compare Preload +* register. +* This parameter can be one of the following values: +* - TIM1_OCPreload_Enable +* - TIM1_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload) +{ + /* Check the parameters */ + assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload)); + + /* Set or Reset the OC1PE Bit */ + *(vu32 *) CCMR1_OC1PE_BB = (u16)TIM1_OCPreload; +} + +/******************************************************************************* +* Function Name : TIM1_OC2PreloadConfig +* Description : Enables or disables the TIM1 peripheral Preload Register on CCR2. +* Input : - TIM1_OCPreload: new state of the Capture Compare Preload +* register. +* This parameter can be one of the following values: +* - TIM1_OCPreload_Enable +* - TIM1_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload) +{ + /* Check the parameters */ + assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload)); + + /* Set or Reset the OC2PE Bit */ + *(vu32 *) CCMR1_OC2PE_BB = (u16)TIM1_OCPreload; +} + +/******************************************************************************* +* Function Name : TIM1_OC3PreloadConfig +* Description : Enables or disables the TIM1 peripheral Preload Register on CCR3. +* Input : - TIM1_OCPreload: new state of the Capture Compare Preload +* register. +* This parameter can be one of the following values: +* - TIM1_OCPreload_Enable +* - TIM1_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload) +{ + /* Check the parameters */ + assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload)); + + /* Set or Reset the OC3PE Bit */ + *(vu32 *) CCMR2_OC3PE_BB = (u16)TIM1_OCPreload; +} + +/******************************************************************************* +* Function Name : TIM1_OC4PreloadConfig +* Description : Enables or disables the TIM1 peripheral Preload Register on CCR4. +* Input : - TIM1_OCPreload: new state of the Capture Compare Preload +* register. +* This parameter can be one of the following values: +* - TIM1_OCPreload_Enable +* - TIM1_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload) +{ + /* Check the parameters */ + assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload)); + + /* Set or Reset the OC4PE Bit */ + *(vu32 *) CCMR2_OC4PE_BB = (u16)TIM1_OCPreload; +} + +/******************************************************************************* +* Function Name : TIM1_OC1FastConfig +* Description : Configures the TIM1 Capture Compare 1 Fast feature. +* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit. +* This parameter can be one of the following values: +* - TIM1_OCFast_Enable +* - TIM1_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1FastConfig(u16 TIM1_OCFast) +{ + /* Check the parameters */ + assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast)); + + /* Set or Reset the OC1FE Bit */ + *(vu32 *) CCMR1_OC1FE_BB = (u16)TIM1_OCFast; +} + +/******************************************************************************* +* Function Name : TIM1_OC2FastConfig +* Description : Configures the TIM1 Capture Compare Fast feature. +* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit. +* This parameter can be one of the following values: +* - TIM1_OCFast_Enable +* - TIM1_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2FastConfig(u16 TIM1_OCFast) +{ + /* Check the parameters */ + assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast)); + + /* Set or Reset the OC2FE Bit */ + *(vu32 *) CCMR1_OC2FE_BB = (u16)TIM1_OCFast; +} + +/******************************************************************************* +* Function Name : TIM1_OC3FastConfig +* Description : Configures the TIM1 Capture Compare Fast feature. +* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit. +* This parameter can be one of the following values: +* - TIM1_OCFast_Enable +* - TIM1_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3FastConfig(u16 TIM1_OCFast) +{ + /* Check the parameters */ + assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast)); + + /* Set or Reset the OC3FE Bit */ + *(vu32 *) CCMR2_OC3FE_BB = (u16)TIM1_OCFast; +} + +/******************************************************************************* +* Function Name : TIM1_OC4FastConfig +* Description : Configures the TIM1 Capture Compare Fast feature. +* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit. +* This parameter can be one of the following values: +* - TIM1_OCFast_Enable +* - TIM1_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC4FastConfig(u16 TIM1_OCFast) +{ + /* Check the parameters */ + assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast)); + + /* Set or Reset the OC4FE Bit */ + *(vu32 *) CCMR2_OC4FE_BB = (u16)TIM1_OCFast; +} + +/******************************************************************************* +* Function Name : TIM1_GenerateEvent +* Description : Configures the TIM1 event to be generate by software. +* Input : - TIM1_EventSource: specifies the event source. +* This parameter can be one or more of the following values: +* - TIM1_EventSource_Update: TIM1 update Event source +* - TIM1_EventSource_CC1: TIM1 Capture Compare 1 Event source +* - TIM1_EventSource_CC2: TIM1 Capture Compare 2 Event source +* - TIM1_EventSource_CC3: TIM1 Capture Compare 3 Event source +* - TIM1_EventSource_CC4: TIM1 Capture Compare 4 Event source +* - TIM1_EventSource_COM: TIM1 COM Event source +* - TIM1_EventSource_Trigger: TIM1 Trigger Event source +* - TIM1_EventSourceBreak: TIM1 Break Event source +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_GenerateEvent(u16 TIM1_EventSource) +{ + /* Check the parameters */ + assert(IS_TIM1_EVENT_SOURCE(TIM1_EventSource)); + + /* Set the event sources */ + TIM1->EGR |= TIM1_EventSource; +} + +/******************************************************************************* +* Function Name : TIM1_OC1PolarityConfig +* Description : Configures the TIM1 Channel 1 polarity. +* Input : - TIM1_OCPolarity: specifies the OC1 Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC1P Bit */ + *(vu32 *) CCER_CC1P_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC1NPolarityConfig +* Description : Configures the TIM1 Channel 1N polarity. +* Input : - TIM1_OCPolarity: specifies the OC1N Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC3P Bit */ + *(vu32 *) CCER_CC1NP_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC2PolarityConfig +* Description : Configures the TIM1 Channel 2 polarity. +* Input : - TIM1_OCPolarity: specifies the OC2 Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC2P Bit */ + *(vu32 *) CCER_CC2P_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC2NPolarityConfig +* Description : Configures the TIM1 Channel 2N polarity. +* Input : - TIM1_OCPolarity: specifies the OC2N Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC3P Bit */ + *(vu32 *) CCER_CC2NP_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC3PolarityConfig +* Description : Configures the TIM1 Channel 3 polarity. +* Input : - TIM1_OCPolarity: specifies the OC3 Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC3P Bit */ + *(vu32 *) CCER_CC3P_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC3NPolarityConfig +* Description : Configures the TIM1 Channel 3N polarity. +* Input : - TIM1_OCPolarity: specifies the OC3N Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC3P Bit */ + *(vu32 *) CCER_CC3NP_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC4PolarityConfig +* Description : Configures the TIM1 Channel 4 polarity. +* Input : - TIM1_OCPolarity: specifies the OC4 Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC4P Bit */ + *(vu32 *) CCER_CC4P_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_CCxCmd +* Description : Enables or disables the TIM1 Capture Compare Channel x. +* Input : - TIM1_Channel: specifies the TIM1 Channel +* This parmeter can be one of the following values: +* - TIM1_Channel1: TIM1 Channel1 +* - TIM1_Channel2: TIM1 Channel2 +* - TIM1_Channel3: TIM1 Channel3 +* - TIM1_Channel4: TIM1 Channel4 +* - Newstate: specifies the TIM1 Channel CCxE bit new state. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_TIM1_CHANNEL(TIM1_Channel)); + assert(IS_FUNCTIONAL_STATE(Newstate)); + + if(TIM1_Channel == TIM1_Channel_1) + { + /* Set or Reset the CC1E Bit */ + *(vu32 *) CCER_CC1E_BB = (u16)Newstate; + } + else if(TIM1_Channel == TIM1_Channel_2) + { + /* Set or Reset the CC2E Bit */ + *(vu32 *) CCER_CC2E_BB = (u16)Newstate; + } + else if(TIM1_Channel == TIM1_Channel_3) + { + /* Set or Reset the CC3E Bit */ + *(vu32 *) CCER_CC3E_BB = (u16)Newstate; + } + else + { + /* Set or Reset the CC4E Bit */ + *(vu32 *) CCER_CC4E_BB = (u16)Newstate; + } +} + +/******************************************************************************* +* Function Name : TIM1_CCxNCmd +* Description : Enables or disables the TIM1 Capture Compare Channel xN. +* Input : - TIM1_Channel: specifies the TIM1 Channel +* This parmeter can be one of the following values: +* - TIM1_Channel1: TIM1 Channel1 +* - TIM1_Channel2: TIM1 Channel2 +* - TIM1_Channel3: TIM1 Channel3 +* - Newstate: specifies the TIM1 Channel CCxNE bit new state. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_TIM1_COMPLEMENTARY_CHANNEL(TIM1_Channel)); + assert(IS_FUNCTIONAL_STATE(Newstate)); + + if(TIM1_Channel == TIM1_Channel_1) + { + /* Set or Reset the CC1NE Bit */ + *(vu32 *) CCER_CC1NE_BB = (u16)Newstate; + } + else if(TIM1_Channel == TIM1_Channel_2) + { + /* Set or Reset the CC2NE Bit */ + *(vu32 *) CCER_CC2NE_BB = (u16)Newstate; + } + else + { + /* Set or Reset the CC3NE Bit */ + *(vu32 *) CCER_CC3NE_BB = (u16)Newstate; + } +} + +/******************************************************************************* +* Function Name : TIM1_SelectOCxM +* Description : Selects the TIM1 Ouput Compare Mode. +* This function disables the selected channel before changing +* the Ouput Compare Mode. User has to enable this channel using +* TIM1_CCxCmd and TIM1_CCxNCmd functions. +* Input : - TIM1_Channel: specifies the TIM1 Channel +* This parmeter can be one of the following values: +* - TIM1_Channel1: TIM1 Channel1 +* - TIM1_Channel2: TIM1 Channel2 +* - TIM1_Channel3: TIM1 Channel3 +* - TIM1_Channel4: TIM1 Channel4 +* - TIM1_OCMode: specifies the TIM1 Output Compare Mode. +* This paramter can be one of the following values: +* - TIM1_OCMode_Timing +* - TIM1_OCMode_Active +* - TIM1_OCMode_Toggle +* - TIM1_OCMode_PWM1 +* - TIM1_OCMode_PWM2 +* - TIM1_ForcedAction_Active +* - TIM1_ForcedAction_InActive +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode) +{ + /* Check the parameters */ + assert(IS_TIM1_CHANNEL(TIM1_Channel)); + assert(IS_TIM1_OCM(TIM1_OCMode)); + + if(TIM1_Channel == TIM1_Channel_1) + { + /* Disable the Channel 1: Reset the CCE Bit */ + *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + TIM1->CCMR1 &= OC13Mode_Mask; + + /* Set the Ouput Compare Mode */ + TIM1->CCMR1 |= TIM1_OCMode; + } + else if(TIM1_Channel == TIM1_Channel_2) + { + /* Disable the Channel 2: Reset the CCE Bit */ + *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + TIM1->CCMR1 &= OC24Mode_Mask; + + /* Set the Ouput Compare Mode */ + TIM1->CCMR1 |= (u16)((u16)TIM1_OCMode << 8); + } + else if(TIM1_Channel == TIM1_Channel_3) + { + /* Disable the Channel 3: Reset the CCE Bit */ + *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + TIM1->CCMR2 &= OC13Mode_Mask; + + /* Set the Ouput Compare Mode */ + TIM1->CCMR2 |= TIM1_OCMode; + } + else + { + /* Disable the Channel 4: Reset the CCE Bit */ + *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + TIM1->CCMR2 &= OC24Mode_Mask; + + /* Set the Ouput Compare Mode */ + TIM1->CCMR2 |= (u16)((u16)TIM1_OCMode << 8); + } +} + +/******************************************************************************* +* Function Name : TIM1_SetAutoreload +* Description : Sets the TIM1 Autoreload Register value. +* Input : - Autoreload: specifies the Autoreload register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetAutoreload(u16 Autoreload) +{ + /* Set the Autoreload Register value */ + TIM1->ARR = Autoreload; +} + +/******************************************************************************* +* Function Name : TIM1_SetCompare1 +* Description : Sets the TIM1 Capture Compare1 Register value. +* Input : - Compare1: specifies the Capture Compare1 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetCompare1(u16 Compare1) +{ + /* Set the Capture Compare1 Register value */ + TIM1->CCR1 = Compare1; +} + +/******************************************************************************* +* Function Name : TIM1_SetCompare2 +* Description : Sets the TIM1 Capture Compare2 Register value. +* Input : - Compare2: specifies the Capture Compare2 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetCompare2(u16 Compare2) +{ + /* Set the Capture Compare2 Register value */ + TIM1->CCR2 = Compare2; +} + +/******************************************************************************* +* Function Name : TIM1_SetCompare3 +* Description : Sets the TIM1 Capture Compare3 Register value. +* Input : - Compare3: specifies the Capture Compare3 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetCompare3(u16 Compare3) +{ + /* Set the Capture Compare3 Register value */ + TIM1->CCR3 = Compare3; +} + +/******************************************************************************* +* Function Name : TIM1_SetCompare4 +* Description : Sets the TIM1 Capture Compare4 Register value. +* Input : - Compare4: specifies the Capture Compare4 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetCompare4(u16 Compare4) +{ + /* Set the Capture Compare4 Register value */ + TIM1->CCR4 = Compare4; +} + +/******************************************************************************* +* Function Name : TIM1_SetIC1Prescaler +* Description : Sets the TIM1 Input Capture 1 prescaler. +* Input : - TIM1_IC1Prescaler: specifies the Input Capture prescaler +* new value. +* This parameter can be one of the following values: +* - TIM1_ICPSC_DIV1: no prescaler +* - TIM1_ICPSC_DIV2: capture is done once every 2 events +* - TIM1_ICPSC_DIV4: capture is done once every 4 events +* - TIM1_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_IC_PRESCALER(TIM1_IC1Prescaler)); + + tmpccmr1 = TIM1->CCMR1; + + /* Reset the IC1PSC Bits */ + tmpccmr1 &= CCMR_IC13PSC_Mask; + + /* Set the IC1PSC value */ + tmpccmr1 |= TIM1_IC1Prescaler; + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_SetIC2Prescaler +* Description : Sets the TIM1 Input Capture 2 prescaler. +* Input : - TIM1_IC2Prescaler: specifies the Input Capture prescaler +* new value. +* This parameter can be one of the following values: +* - TIM1_ICPSC_DIV1: no prescaler +* - TIM1_ICPSC_DIV2: capture is done once every 2 events +* - TIM1_ICPSC_DIV4: capture is done once every 4 events +* - TIM1_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_IC_PRESCALER(TIM1_IC2Prescaler)); + + tmpccmr1 = TIM1->CCMR1; + + /* Reset the IC2PSC Bits */ + tmpccmr1 &= CCMR_IC24PSC_Mask; + + /* Set the IC2PSC value */ + tmpccmr1 |= (u16)((u16)TIM1_IC2Prescaler << 8); + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_SetIC3Prescaler +* Description : Sets the TIM1 Input Capture 3 prescaler. +* Input : - TIM1_IC3Prescaler: specifies the Input Capture prescaler +* new value. +* This parameter can be one of the following values: +* - TIM1_ICPSC_DIV1: no prescaler +* - TIM1_ICPSC_DIV2: capture is done once every 2 events +* - TIM1_ICPSC_DIV4: capture is done once every 4 events +* - TIM1_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_IC_PRESCALER(TIM1_IC3Prescaler)); + + tmpccmr2 = TIM1->CCMR2; + + /* Reset the IC3PSC Bits */ + tmpccmr2 &= CCMR_IC13PSC_Mask; + + /* Set the IC3PSC value */ + tmpccmr2 |= TIM1_IC3Prescaler; + + TIM1->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM1_SetIC4Prescaler +* Description : Sets the TIM1 Input Capture 4 prescaler. +* Input : - TIM1_IC4Prescaler: specifies the Input Capture prescaler +* new value. +* This parameter can be one of the following values: +* - TIM1_ICPSC_DIV1: no prescaler +* - TIM1_ICPSC_DIV2: capture is done once every 2 events +* - TIM1_ICPSC_DIV4: capture is done once every 4 events +* - TIM1_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_IC_PRESCALER(TIM1_IC4Prescaler)); + + tmpccmr2 = TIM1->CCMR2; + + /* Reset the IC4PSC Bits */ + tmpccmr2 &= CCMR_IC24PSC_Mask; + + /* Set the IC4PSC value */ + tmpccmr2 |= (u16)((u16)TIM1_IC4Prescaler << 8); + + TIM1->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM1_SetClockDivision +* Description : Sets the TIM1 Clock Division value. +* Input : - TIM1_CKD: specifies the clock division value. +* This parameter can be one of the following value: +* - TIM1_CKD_DIV1: TDTS = Tck_tim +* - TIM1_CKD_DIV2: TDTS = 2*Tck_tim +* - TIM1_CKD_DIV4: TDTS = 4*Tck_tim +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetClockDivision(u16 TIM1_CKD) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_CKD_DIV(TIM1_CKD)); + + tmpcr1 = TIM1->CR1; + + /* Reset the CKD Bits */ + tmpcr1 &= CR1_CKD_Mask; + + /* Set the CKD value */ + tmpcr1 |= TIM1_CKD; + + TIM1->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM1_GetCapture1 +* Description : Gets the TIM1 Input Capture 1 value. +* Input : None +* Output : None +* Return : Capture Compare 1 Register value. +*******************************************************************************/ +u16 TIM1_GetCapture1(void) +{ + /* Get the Capture 1 Register value */ + return TIM1->CCR1; +} + +/******************************************************************************* +* Function Name : TIM1_GetCapture2 +* Description : Gets the TIM1 Input Capture 2 value. +* Input : None +* Output : None +* Return : Capture Compare 2 Register value. +*******************************************************************************/ +u16 TIM1_GetCapture2(void) +{ + /* Get the Capture 2 Register value */ + return TIM1->CCR2; +} + +/******************************************************************************* +* Function Name : TIM1_GetCapture3 +* Description : Gets the TIM1 Input Capture 3 value. +* Input : None +* Output : None +* Return : Capture Compare 3 Register value. +*******************************************************************************/ +u16 TIM1_GetCapture3(void) +{ + /* Get the Capture 3 Register value */ + return TIM1->CCR3; +} + +/******************************************************************************* +* Function Name : TIM1_GetCapture4 +* Description : Gets the TIM1 Input Capture 4 value. +* Input : None +* Output : None +* Return : Capture Compare 4 Register value. +*******************************************************************************/ +u16 TIM1_GetCapture4(void) +{ + /* Get the Capture 4 Register value */ + return TIM1->CCR4; +} + +/******************************************************************************* +* Function Name : TIM1_GetCounter +* Description : Gets the TIM1 Counter value. +* Input : None +* Output : None +* Return : Counter Register value. +*******************************************************************************/ +u16 TIM1_GetCounter(void) +{ + /* Get the Counter Register value */ + return TIM1->CNT; +} + +/******************************************************************************* +* Function Name : TIM1_GetPrescaler +* Description : Gets the TIM1 Prescaler value. +* Input : None +* Output : None +* Return : Prescaler Register value. +*******************************************************************************/ +u16 TIM1_GetPrescaler(void) +{ + /* Get the Prescaler Register value */ + return TIM1->PSC; +} + +/******************************************************************************* +* Function Name : TIM1_GetFlagStatus +* Description : Checks whether the specified TIM1 flag is set or not. +* Input : - TIM1_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM1_FLAG_Update: TIM1 update Flag +* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag +* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag +* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag +* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag +* - TIM1_FLAG_COM: TIM1 Commutation Flag +* - TIM1_FLAG_Trigger: TIM1 Trigger Flag +* - TIM1_FLAG_Break: TIM1 Break Flag +* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag +* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag +* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag +* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag +* Output : None +* Return : The new state of TIM1_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_TIM1_GET_FLAG(TIM1_FLAG)); + + if ((TIM1->SR & TIM1_FLAG) != (u16)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM1_ClearFlag +* Description : Clears the TIM1s pending flags. +* Input : - TIM1_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - TIM1_FLAG_Update: TIM1 update Flag +* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag +* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag +* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag +* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag +* - TIM1_FLAG_COM: TIM1 Commutation Flag +* - TIM1_FLAG_Trigger: TIM1 Trigger Flag +* - TIM1_FLAG_Break: TIM1 Break Flag +* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag +* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag +* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag +* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ClearFlag(u16 TIM1_FLAG) +{ + /* Check the parameters */ + assert(IS_TIM1_CLEAR_FLAG(TIM1_FLAG)); + + /* Clear the flags */ + TIM1->SR &= (u16)~TIM1_FLAG; +} + +/******************************************************************************* +* Function Name : TIM1_GetITStatus +* Description : Checks whether the TIM1 interrupt has occurred or not. +* Input : - TIM1_IT: specifies the TIM1 interrupt source to check. +* This parameter can be one of the following values: +* - TIM1_IT_Update: TIM1 update Interrupt source +* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source +* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source +* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source +* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source +* - TIM1_IT_COM: TIM1 Commutation Interrupt +* source +* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source +* - TIM1_IT_Break: TIM1 Break Interrupt source +* Output : None +* Return : The new state of the TIM1_IT(SET or RESET). +*******************************************************************************/ +ITStatus TIM1_GetITStatus(u16 TIM1_IT) +{ + ITStatus bitstatus = RESET; + + u16 TIM1_itStatus = 0x0, TIM1_itEnable = 0x0; + + /* Check the parameters */ + assert(IS_TIM1_GET_IT(TIM1_IT)); + + TIM1_itStatus = TIM1->SR & TIM1_IT; + + TIM1_itEnable = TIM1->DIER & TIM1_IT; + + if ((TIM1_itStatus != (u16)RESET ) && (TIM1_itEnable != (u16)RESET )) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM1_ClearITPendingBit +* Description : Clears the TIM1's interrupt pending bits. +* Input : - TIM1_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - TIM1_IT_Update: TIM1 update Interrupt source +* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source +* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source +* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source +* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source +* - TIM1_IT_COM: TIM1 Commutation Interrupt +* source +* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source +* - TIM1_IT_Break: TIM1 Break Interrupt source +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ClearITPendingBit(u16 TIM1_IT) +{ + /* Check the parameters */ + assert(IS_TIM1_IT(TIM1_IT)); + + /* Clear the IT pending Bit */ + TIM1->SR &= (u16)~TIM1_IT; +} + +/******************************************************************************* +* Function Name : TI1_Config +* Description : Configure the TI1 as Input. +* Input : - TIM1_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - TIM1_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM1_ICSelection_DirectTI: TIM1 Input 1 is selected to +* be connected to IC1. +* - TIM1_ICSelection_IndirectTI: TIM1 Input 1 is selected to +* be connected to IC2. +* - TIM1_ICSelection_TRGI:TIM1 Input 1 is selected to be +* connected to TRGI. +* - TIM1_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + u32 tmpccmr1 = 0; + + tmpccmr1 = TIM1->CCMR1; + + /* Disable the Channel 1: Reset the CCE Bit */ + *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr1 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4); + + TIM1->CCMR1 = (u16)tmpccmr1; + + /* Select the Polarity */ + *(vu32 *) CCER_CC1P_BB = TIM1_ICPolarity; + + /* Set the CCE Bit */ + *(vu32 *) CCER_CC1E_BB = CCER_CCE_Set; +} + +/******************************************************************************* +* Function Name : TI2_Config +* Description : Configure the TI2 as Input. +* Input : - TIM1_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - TIM1_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM1_ICSelection_DirectTI: TIM1 Input 2 is selected to +* be connected to IC2. +* - TIM1_ICSelection_IndirectTI: TIM1 Input 2 is selected to +* be connected to IC1. +* - TIM1_ICSelection_TRGI: TIM1 Input 2 is selected to be +* connected to TRGI. +* - TIM1_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + u32 tmpccmr1 = 0; + + tmpccmr1 = TIM1->CCMR1; + + /* Disable the Channel 2: Reset the CCE Bit */ + *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr1 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter <<12); + + TIM1->CCMR1 = (u16)tmpccmr1; + + /* Select the Polarity */ + *(vu32 *) CCER_CC2P_BB = TIM1_ICPolarity; + + /* Set the CCE Bit */ + *(vu32 *) CCER_CC2E_BB = CCER_CCE_Set; + +} + +/******************************************************************************* +* Function Name : TI3_Config +* Description : Configure the TI3 as Input. +* Input : - TIM1_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - TIM1_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM1_ICSelection_DirectTI: TIM1 Input 3 is selected to +* be connected to IC3. +* - TIM1_ICSelection_IndirectTI: TIM1 Input 3 is selected to +* be connected to IC4. +* - TIM1_ICSelection_TRGI: TIM1 Input 3 is selected to be +* connected to TRGI. +* - TIM1_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + u32 tmpccmr2 = 0; + + tmpccmr2 = TIM1->CCMR2; + + /* Disable the Channel 3: Reset the CCE Bit */ + *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr2 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4); + + TIM1->CCMR2 = (u16)tmpccmr2; + + /* Select the Polarity */ + *(vu32 *) CCER_CC3P_BB = TIM1_ICPolarity; + + /* Set the CCE Bit */ + *(vu32 *) CCER_CC3E_BB = CCER_CCE_Set; +} + +/******************************************************************************* +* Function Name : TI4_Config +* Description : Configure the TI4 as Input. +* Input : - TIM1_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - TIM1_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM1_ICSelection_DirectTI: TIM1 Input 4 is selected to +* be connected to IC4. +* - TIM1_ICSelection_IndirectTI: TIM1 Input 4 is selected to +* be connected to IC3. +* - TIM1_ICSelection_TRGI: TIM1 Input 4 is selected to be +* connected to TRGI. +* - TIM1_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + u32 tmpccmr2 = 0; + + tmpccmr2 = TIM1->CCMR2; + + /* Disable the Channel 4: Reset the CCE Bit */ + *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr2 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter << 12); + + TIM1->CCMR2 = (u16)tmpccmr2; + + /* Select the Polarity */ + *(vu32 *) CCER_CC4P_BB = TIM1_ICPolarity; + + /* Set the CCE Bit */ + *(vu32 *) CCER_CC4E_BB = CCER_CCE_Set; +} + +/******************************************************************************* +* Function Name : ETR_Config +* Description : Configure the External Trigger +* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* - TIM1_ExtTRGPSC_OFF +* - TIM1_ExtTRGPSC_DIV2 +* - TIM1_ExtTRGPSC_DIV4 +* - TIM1_ExtTRGPSC_DIV8 +* - TIM1_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* - TIM1_ExtTRGPolarity_Inverted +* - TIM1_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter) +{ + u32 tmpsmcr = 0; + + tmpsmcr = TIM1->SMCR; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr &= SMCR_ETR_Mask; + tmpsmcr |= TIM1_ExtTRGPrescaler | TIM1_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8); + + TIM1->SMCR = (u16)tmpsmcr; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_usart.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_usart.c new file mode 100644 index 0000000..7bc288a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_usart.c @@ -0,0 +1,852 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_usart.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the USART firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* USART RUN Mask */ +#define CR1_RUN_Set ((u16)0x2000) /* USART Enable Mask */ +#define CR1_RUN_Reset ((u16)0xDFFF) /* USART Disable Mask */ + +#define CR2_Address_Mask ((u16)0xFFF0) /* USART address Mask */ + +/* USART RWU Mask */ +#define CR1_RWU_Set ((u16)0x0002) /* USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((u16)0xFFFD) /* USART mute mode Enable Mask */ + +#define USART_IT_Mask ((u16)0x001F) /* USART Interrupt Mask */ + +/* USART LIN Mask */ +#define CR2_LINE_Set ((u16)0x4000) /* USART LIN Enable Mask */ +#define CR2_LINE_Reset ((u16)0xBFFF) /* USART LIN Disable Mask */ + +#define CR1_SBK_Set ((u16)0x0001) /* USART Break Character send Mask */ + +/* USART SC Mask */ +#define CR3_SCEN_Set ((u16)0x0020) /* USART SC Enable Mask */ +#define CR3_SCEN_Reset ((u16)0xFFDF) /* USART SC Disable Mask */ + +/* USART SC NACK Mask */ +#define CR3_NACK_Set ((u16)0x0010) /* USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((u16)0xFFEF) /* USART SC NACK Disable Mask */ + +/* USART Half-Duplex Mask */ +#define CR3_HDSEL_Set ((u16)0x0008) /* USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((u16)0xFFF7) /* USART Half-Duplex Disable Mask */ + +/* USART IrDA Mask */ +#define CR3_IRLP_Mask ((u16)0xFFFB) /* USART IrDA LowPower mode Mask */ + +/* USART LIN Break detection */ +#define CR3_LBDL_Mask ((u16)0xFFDF) /* USART LIN Break detection Mask */ + +/* USART WakeUp Method */ +#define CR3_WAKE_Mask ((u16)0xF7FF) /* USART WakeUp Method Mask */ + +/* USART IrDA Mask */ +#define CR3_IREN_Set ((u16)0x0002) /* USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((u16)0xFFFD) /* USART IrDA Disable Mask */ + +#define GTPR_LSB_Mask ((u16)0x00FF) /* Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((u16)0xFF00) /* Guard Time Register MSB Mask */ + +#define CR1_CLEAR_Mask ((u16)0xE9F3) /* USART CR1 Mask */ +#define CR2_CLEAR_Mask ((u16)0xC0FF) /* USART CR2 Mask */ +#define CR3_CLEAR_Mask ((u16)0xFCFF) /* USART CR3 Mask */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : USART_DeInit +* Description : Deinitializes the USARTx peripheral registers to their +* default reset values. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void USART_DeInit(USART_TypeDef* USARTx) +{ + switch (*(u32*)&USARTx) + { + case USART1_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + break; + + case USART2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + break; + + case USART3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : USART_Init +* Description : Initializes the USARTx peripheral according to the specified +* parameters in the USART_InitStruct . +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART peripheral. +* - USART_InitStruct: pointer to a USART_InitTypeDef structure +* that contains the configuration information for the +* specified USART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + u32 tmpreg = 0x00, apbclock = 0x00; + u32 integerdivider = 0x00; + u32 fractionaldivider = 0x00; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + assert(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert(IS_USART_CLOCK(USART_InitStruct->USART_Clock)); + assert(IS_USART_CPOL(USART_InitStruct->USART_CPOL)); + assert(IS_USART_CPHA(USART_InitStruct->USART_CPHA)); + assert(IS_USART_LASTBIT(USART_InitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLEAR_Mask; + + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_Mode value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (u32)USART_InitStruct->USART_StopBits | USART_InitStruct->USART_Clock | + USART_InitStruct->USART_CPOL | USART_InitStruct->USART_CPHA | + USART_InitStruct->USART_LastBit; + + /* Write to USART CR2 */ + USARTx->CR2 = (u16)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = 0x00; + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + /* Write to USART CR1 */ + USARTx->CR1 = (u16)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = 0x00; + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + + /* Write to USART CR3 */ + USARTx->CR3 = (u16)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + tmpreg = 0x00; + + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if ((*(u32*)&USARTx) == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 0x64) << 0x04; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04)); + tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F); + + /* Write to USART BRR */ + USARTx->BRR = (u16)tmpreg; +} + +/******************************************************************************* +* Function Name : USART_StructInit +* Description : Fills each USART_InitStruct member with its default value. +* Input : - USART_InitStruct: pointer to a USART_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 0x2580; /* 9600 Baud */ + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_Clock = USART_Clock_Disable; + USART_InitStruct->USART_CPOL = USART_CPOL_Low; + USART_InitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_InitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/******************************************************************************* +* Function Name : USART_Cmd +* Description : Enables or disables the specified USART peripheral. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* : - NewState: new state of the USARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the RUN bit in the CR1 register */ + USARTx->CR1 |= CR1_RUN_Set; + } + else + { + /* Disable the selected USART by clearing the RUN bit in the CR1 register */ + USARTx->CR1 &= CR1_RUN_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_ITConfig +* Description : Enables or disables the specified USART interrupts. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_IT: specifies the USART interrupt sources to be +* enabled or disabled. +* This parameter can be one of the following values: +* - USART_IT_PE +* - USART_IT_TXE +* - USART_IT_TC +* - USART_IT_RXNE +* - USART_IT_IDLE +* - USART_IT_LBD +* - USART_IT_CTS +* - USART_IT_ERR +* - NewState: new state of the specified USARTx interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState) +{ + u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00; + u32 address = 0x00; + + /* Check the parameters */ + assert(IS_USART_CONFIG_IT(USART_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the USART register index */ + usartreg = (((u8)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & USART_IT_Mask; + + itmask = (((u32)0x01) << itpos); + address = *(u32*)&(USARTx); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + address += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + address += 0x10; + } + else /* The IT is in CR3 register */ + { + address += 0x14; + } + if (NewState != DISABLE) + { + *(u32*)address |= itmask; + } + else + { + *(u32*)address &= ~itmask; + } +} + +/******************************************************************************* +* Function Name : USART_DMACmd +* Description : Enables or disables the USARTs DMA interface. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_DMAReq: specifies the DMA request. +* This parameter can be any combination of the following values: +* - USART_DMAReq_Tx +* - USART_DMAReq_Rx +* - NewState: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_USART_DMAREQ(USART_DMAReq)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (u16)~USART_DMAReq; + } +} + +/******************************************************************************* +* Function Name : USART_SetAddress +* Description : Sets the address of the USART node. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_Address: Indicates the address of the USART node. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address) +{ + /* Check the parameters */ + assert(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/******************************************************************************* +* Function Name : USART_WakeUpConfig +* Description : Selects the USART WakeUp method. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_WakeUp: specifies the USART wakeup method. +* This parameter can be one of the following values: +* - USART_WakeUp_IdleLine +* - USART_WakeUp_AddressMark +* Output : None +* Return : None +*******************************************************************************/ +void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp) +{ + /* Check the parameters */ + assert(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR3_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/******************************************************************************* +* Function Name : USART_ReceiverWakeUpCmd +* Description : Determines if the USART is in mute mode or not. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the USART mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the mute mode USART by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the mute mode USART by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_LINBreakDetectLengthConfig +* Description : Sets the USART LIN Break detection length. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_LINBreakDetectLength: specifies the LIN break +* detection length. +* This parameter can be one of the following values: +* - USART_LINBreakDetectLength_10b +* - USART_LINBreakDetectLength_11b +* Output : None +* Return : None +*******************************************************************************/ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR3_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/******************************************************************************* +* Function Name : USART_LINCmd +* Description : Enables or disables the USARTs LIN mode. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the USART LIN mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINE bit in the CR2 register */ + USARTx->CR2 |= CR2_LINE_Set; + } + else + { + /* Disable the LIN mode by clearing the LINE bit in the CR2 register */ + USARTx->CR2 &= CR2_LINE_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_SendData +* Description : Transmits signle data through the USARTx peripheral. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - Data: the data to transmit. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SendData(USART_TypeDef* USARTx, u16 Data) +{ + /* Check the parameters */ + assert(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (u16)0x01FF); +} + +/******************************************************************************* +* Function Name : USART_ReceiveData +* Description : Returns the most recent received data by the USARTx peripheral. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* Output : None +* Return : The received data. +*******************************************************************************/ +u16 USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Receive Data */ + return (u16)(USARTx->DR & (u16)0x01FF); +} + +/******************************************************************************* +* Function Name : USART_SendBreak +* Description : Transmits break characters. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/******************************************************************************* +* Function Name : USART_SetGuardTime +* Description : Sets the specified USART guard time. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_GuardTime: specifies the guard time. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime) +{ + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (u16)((u16)USART_GuardTime << 0x08); +} + +/******************************************************************************* +* Function Name : USART_SetPrescaler +* Description : Sets the system clock prescaler. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_Prescaler: specifies the prescaler clock. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler) +{ + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/******************************************************************************* +* Function Name : USART_SmartCardCmd +* Description : Enables or disables the USARTs Smart Card mode. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the Smart Card mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_SmartCardNACKCmd +* Description : Enables or disables NACK transmission. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the NACK transmission. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } + +} + +/******************************************************************************* +* Function Name : USART_HalfDuplexCmd +* Description : Enables or disables the USARTs Half Duplex communication. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the USART Communication. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_IrDAConfig +* Description : Configures the USARTs IrDA interface. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_IrDAMode: specifies the IrDA mode. +* This parameter can be one of the following values: +* - USART_IrDAMode_LowPower +* - USART_IrDAMode_Normal +* Output : None +* Return : None +*******************************************************************************/ +void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode) +{ + /* Check the parameters */ + assert(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/******************************************************************************* +* Function Name : USART_IrDACmd +* Description : Enables or disables the USARTs IrDA interface. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the IrDA mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_GetFlagStatus +* Description : Checks whether the specified USART flag is set or not. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - USART_FLAG_CTS +* - USART_FLAG_LBD +* - USART_FLAG_TXE +* - USART_FLAG_TC +* - USART_FLAG_RXNE +* - USART_FLAG_IDLE +* - USART_FLAG_ORE +* - USART_FLAG_NE +* - USART_FLAG_FE +* - USART_FLAG_PE +* Output : None +* Return : The new state of USART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_USART_FLAG(USART_FLAG)); + + if ((USARTx->SR & USART_FLAG) != (u16)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : USART_ClearFlag +* Description : Clears the USARTx's pending flags. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - USART_FLAG_CTS +* - USART_FLAG_LBD +* - USART_FLAG_TXE +* - USART_FLAG_TC +* - USART_FLAG_RXNE +* - USART_FLAG_IDLE +* - USART_FLAG_ORE +* - USART_FLAG_NE +* - USART_FLAG_FE +* - USART_FLAG_PE +* Output : None +* Return : None +*******************************************************************************/ +void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG) +{ + /* Check the parameters */ + assert(IS_USART_CLEAR_FLAG(USART_FLAG)); + + USARTx->SR &= (u16)~USART_FLAG; +} + +/******************************************************************************* +* Function Name : USART_GetITStatus +* Description : Checks whether the specified USART interrupt has occurred or not. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_IT: specifies the USART interrupt source to check. +* This parameter can be one of the following values: +* - USART_IT_PE +* - USART_IT_TXE +* - USART_IT_TC +* - USART_IT_RXNE +* - USART_IT_IDLE +* - USART_IT_LBD +* - USART_IT_CTS +* - USART_IT_ORE +* - USART_IT_NE +* - USART_IT_FE +* Output : None +* Return : The new state of USART_IT (SET or RESET). +*******************************************************************************/ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT) +{ + u32 bitpos = 0x00, itmask = 0x00, usartreg = 0; + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_USART_IT(USART_IT)); + + /* Get the USART register index */ + usartreg = (((u8)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itmask = USART_IT & USART_IT_Mask; + + itmask = (u32)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + + bitpos = (u32)0x01 << bitpos; + bitpos &= USARTx->SR; + + if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : USART_ClearITPendingBit +* Description : Clears the USARTxs interrupt pending bits. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_IT: specifies the interrupt pending bit to clear. +* This parameter can be one of the following values: +* - USART_IT_PE +* - USART_IT_TXE +* - USART_IT_TC +* - USART_IT_RXNE +* - USART_IT_IDLE +* - USART_IT_LBD +* - USART_IT_CTS +* - USART_IT_ORE +* - USART_IT_NE +* - USART_IT_FE +* Output : None +* Return : None +*******************************************************************************/ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT) +{ + u32 bitpos = 0x00, itmask = 0x00; + + /* Check the parameters */ + assert(IS_USART_IT(USART_IT)); + + bitpos = USART_IT >> 0x08; + + itmask = (u32)0x01 << bitpos; + USARTx->SR &= ~itmask; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_wwdg.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_wwdg.c new file mode 100644 index 0000000..e1cb58d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_wwdg.c @@ -0,0 +1,194 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_wwdg.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the WWDG firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* Alias word address of EWIF bit */ +#define SR_OFFSET (WWDG_OFFSET + 0x08) +#define EWIF_BitNumber 0x00 +#define SR_EWIF_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (EWIF_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ +/* CR register bit mask */ +#define CR_WDGA_Set ((u32)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F) +#define CFR_W_Mask ((u32)0xFFFFFF80) + +#define BIT_Mask ((u8)0x7F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : WWDG_DeInit +* Description : Deinitializes the WWDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/******************************************************************************* +* Function Name : WWDG_SetPrescaler +* Description : Sets the WWDG Prescaler. +* Input : - WWDG_Prescaler: specifies the WWDG Prescaler. +* This parameter can be one of the following values: +* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 +* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 +* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 +* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_SetPrescaler(u32 WWDG_Prescaler) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_WWDG_PRESCALER(WWDG_Prescaler)); + + /* Clear WDGTB[8:7] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + + /* Set WDGTB[8:7] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/******************************************************************************* +* Function Name : WWDG_SetWindowValue +* Description : Sets the WWDG window value. +* Input : - WindowValue: specifies the window value to be compared to +* the downcounter. +* This parameter value must be lower than 0x80. +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_SetWindowValue(u8 WindowValue) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_WWDG_WINDOW_VALUE(WindowValue)); + + /* Clear W[6:0] bits */ + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/******************************************************************************* +* Function Name : WWDG_EnableIT +* Description : Enables the WWDG Early Wakeup interrupt(EWI). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_EnableIT(void) +{ + *(vu32 *) CFR_EWI_BB = (u32)ENABLE; +} + +/******************************************************************************* +* Function Name : WWDG_SetCounter +* Description : Sets the WWDG counter value. +* Input : - Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_SetCounter(u8 Counter) +{ + /* Check the parameters */ + assert(IS_WWDG_COUNTER(Counter)); + + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/******************************************************************************* +* Function Name : WWDG_Enable +* Description : Enables WWDG and load the counter value. +* - Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_Enable(u8 Counter) +{ + /* Check the parameters */ + assert(IS_WWDG_COUNTER(Counter)); + + WWDG->CR = CR_WDGA_Set | Counter; +} + +/******************************************************************************* +* Function Name : WWDG_GetFlagStatus +* Description : Checks whether the Early Wakeup interrupt flag is set or not. +* Input : None +* Output : None +* Return : The new state of the Early Wakeup interrupt flag (SET or RESET) +*******************************************************************************/ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(*(vu32 *) SR_EWIF_BB); +} + +/******************************************************************************* +* Function Name : WWDG_ClearFlag +* Description : Clears Early Wakeup interrupt flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (u32)RESET; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth.c new file mode 100644 index 0000000..29d03b8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth.c @@ -0,0 +1,3321 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32fxxx_eth.c +* Author : MCD Application Team +* Version : V1.0.0 +* Date : 12/17/2008 +* Updates : 05/2009 Driver optimization. +* - No copy. DMA directly uses Stack packets. +* Desciption : This file provides all the ETHERNET firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* For the delays. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Includes ------------------------------------------------------------------*/ +#include "stm32fxxx_eth.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; + +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_AddrHighBase (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_AddrLowBase (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_Mask ((u32)0xFFFFFFE3) +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_Mask ((u32)0xFF20810F) +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_Mask ((u32)0x0000FF41) +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_Mask ((u32)0xF8DE3F23) + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WakeupRegisterLength 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RxOverflowMissedFramesCounterShift 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATxDesc_CollisionCountShift 3 +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATxDesc_BufferSize2Shift 16 +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARxDesc_FrameLengthShift 16 +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARxDesc_Buffer2SizeShift 16 + +/* ETHERNET errors */ +#define ETH_ERROR ((u32)0) +#define ETH_SUCCESS ((u32)1) + +#define ethFIVE_SECONDS ( 5000 / portTICK_PERIOD_MS ) +#define ethHUNDRED_MS ( 100 / portTICK_PERIOD_MS ) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ETH_DeInit +* Desciption : Deinitializes the ETHERNET peripheral registers to their +* default reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DeInit(void) +{ +// RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE); +// RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE); +} + +/******************************************************************************* +* Function Name : ETH_Init +* Desciption : Initializes the ETHERNET peripheral according to the specified +* parameters in the ETH_InitStruct . +* Input : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure +* that contains the configuration information for the +* specified ETHERNET peripheral. +* Output : None +* Return : None +*******************************************************************************/ +u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress) +{ + u32 RegValue = 0, tmpreg = 0; + RCC_ClocksTypeDef rcc_clocks; + u32 hclk = 60000000; + u32 timeout = 0; + + /* Check the parameters */ + /* MAC --------------------------*/ + eth_assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); + eth_assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); + eth_assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); + eth_assert_param(IS_ETH_JUMBO_FRAME(ETH_InitStruct->ETH_JumboFrame)); + eth_assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap)); + eth_assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense)); + eth_assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed)); + eth_assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn)); + eth_assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode)); + eth_assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode)); + eth_assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload)); + eth_assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission)); + eth_assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip)); + eth_assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit)); + eth_assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck)); + eth_assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll)); + eth_assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter)); + eth_assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); + eth_assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); + eth_assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); + eth_assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); + eth_assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); + eth_assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); + eth_assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); + eth_assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); + eth_assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold)); + eth_assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect)); + eth_assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl)); + eth_assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl)); + eth_assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison)); + eth_assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier)); + /* DMA --------------------------*/ + eth_assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame)); + eth_assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward)); + eth_assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame)); + eth_assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward)); + eth_assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl)); + eth_assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames)); + eth_assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames)); + eth_assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl)); + eth_assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate)); + eth_assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); + eth_assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); + eth_assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); + eth_assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); + eth_assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); + eth_assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); + +/*--------------------------------- MAC Config -------------------------------*/ +/*----------------------- ETHERNET MACMIIAR Configuration --------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH_MAC->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= MACMIIAR_CR_Mask; + /* Get hclk frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + hclk = rcc_clocks.HCLK_Frequency; + + /* Set CR bits depending on hclk value */ + if((hclk >= 20000000)&&(hclk < 35000000)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (u32)ETH_MACMIIAR_CR_Div16; + } + else if((hclk >= 35000000)&&(hclk < 60000000)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (u32)ETH_MACMIIAR_CR_Div26; + } + else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */ + { + /* CSR Clock Range between 60-72 MHz */ + tmpreg |= (u32)ETH_MACMIIAR_CR_Div42; + } + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + ETH_MAC->MACMIIAR = (u32)tmpreg; + +/*--------------------- PHY initialization and configuration -----------------*/ + /* Put the PHY in reset mode */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Delay to assure PHY reset */ + vTaskDelay( 250 / portTICK_PERIOD_MS ); + + if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) + { + /* We wait for linked satus... */ + timeout = 0; + do + { + /* Wait 100ms before checking for a link again. */ + vTaskDelay( ethHUNDRED_MS ); + timeout++; + + /* Don't wait any longer than 5 seconds. */ + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) ); + + /* Return ERROR in case of timeout */ + if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS )) + { + return ETH_ERROR; + } + + /* Enable Auto-Negotiation */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Reset Timeout counter */ + timeout = 0; + + /* Wait until the autonegotiation will be completed */ + do + { + /* Wait 100ms before checking for negotiation to complete. */ + vTaskDelay( ethHUNDRED_MS ); + timeout++; + + /* Don't wait longer than 5 seconds. */ + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) ); + + /* Return ERROR in case of timeout */ + if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS )) + { + return ETH_ERROR; + } + + /* Reset Timeout counter */ + timeout = 0; + + /* Read the result of the autonegotiation */ + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR); + + /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */ + if((RegValue & PHY_Duplex_Status) != (u32)RESET) + { + /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + + } + else + { + /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + } + /* Configure the MAC with the speed fixed by the autonegotiation process */ + if(RegValue & PHY_Speed_Status) + { + /* Set Ethernet speed to 100M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + } + else + { + /* Set Ethernet speed to 10M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + } + } +// else + { + if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((u16)(ETH_InitStruct->ETH_Mode >> 3) | + (u16)(ETH_InitStruct->ETH_Speed >> 1)))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + vTaskDelay( 250 / portTICK_PERIOD_MS ); + } + +/*------------------------- ETHERNET MACCR Configuration ---------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = ETH_MAC->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= MACCR_CLEAR_Mask; + + /* Set the WD bit according to ETH_Watchdog value */ + /* Set the JD: bit according to ETH_Jabber value */ + /* Set the JE bit according to ETH_JumboFrame value */ + /* Set the IFG bit according to ETH_InterFrameGap value */ + /* Set the DCRS bit according to ETH_CarrierSense value */ + /* Set the FES bit according to ETH_Speed value */ + /* Set the DO bit according to ETH_ReceiveOwn value */ + /* Set the LM bit according to ETH_LoopbackMode value */ + /* Set the DM bit according to ETH_Mode value */ + /* Set the IPC bit according to ETH_ChecksumOffload value */ + /* Set the DR bit according to ETH_RetryTransmission value */ + /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH_BackOffLimit value */ + /* Set the DC bit according to ETH_DeferralCheck value */ + tmpreg |= (u32)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_JumboFrame | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_CarrierSense | + ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_ReceiveOwn | + ETH_InitStruct->ETH_LoopbackMode | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_DeferralCheck); + + /* Write to ETHERNET MACCR */ + ETH_MAC->MACCR = (u32)tmpreg; + +/*------------------------ ETHERNET MACFFR Configuration ---------------------*/ + /* Set the RA bit according to ETH_ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ + /* Set the PCF bit according to ETH_PassControlFrames value */ + /* Set the DBF bit according to ETH_BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH_DestinationAddrFilter value */ + /* Set the PR bit according to ETH_PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + ETH_MAC->MACFFR = (u32)(ETH_InitStruct->ETH_ReceiveAll | + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); + +/*---------------- ETHERNET MACHTHR and MACHTLR Configuration ----------------*/ + /* Write to ETHERNET MACHTHR */ + ETH_MAC->MACHTHR = (u32)ETH_InitStruct->ETH_HashTableHigh; + /* Write to ETHERNET MACHTLR */ + ETH_MAC->MACHTLR = (u32)ETH_InitStruct->ETH_HashTableLow; + +/*------------------------ ETHERNET MACFCR Configuration ---------------------*/ + /* Get the ETHERNET MACFCR value */ + tmpreg = ETH_MAC->MACFCR; + /* Clear xx bits */ + tmpreg &= MACFCR_CLEAR_Mask; + + /* Set the PT bit according to ETH_PauseTime value */ + /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ + /* Set the PLT bit according to ETH_PauseLowThreshold value */ + /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH_ReceiveFlowControl value */ + /* Set the TFE bit according to ETH_TransmitFlowControl value */ + tmpreg |= (u32)((ETH_InitStruct->ETH_PauseTime << 16) | + ETH_InitStruct->ETH_ZeroQuantaPause | + ETH_InitStruct->ETH_PauseLowThreshold | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + ETH_MAC->MACFCR = (u32)tmpreg; + +/*------------------------ ETHERNET MACVLANTR Configuration ------------------*/ + /* Set the ETV bit according to ETH_VLANTagComparison value */ + /* Set the VL bit according to ETH_VLANTagIdentifier value */ + ETH_MAC->MACVLANTR = (u32)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + +#ifdef _ETH_DMA +/*--------------------------------- DMA Config -------------------------------*/ +/*------------------------ ETHERNET DMAOMR Configuration ---------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg = ETH_DMA->DMAOMR; + /* Clear xx bits */ + tmpreg &= DMAOMR_CLEAR_Mask; + + /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH_ReceiveStoreForward value */ + /* Set the DFF bit according to ETH_FlushReceivedFrame value */ + /* Set the TSF bit according to ETH_TransmitStoreForward value */ + /* Set the TTC bit according to ETH_TransmitThresholdControl value */ + /* Set the FEF bit according to ETH_ForwardErrorFrames value */ + /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH_SecondFrameOperate value */ + tmpreg |= (u32)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + ETH_InitStruct->ETH_ReceiveStoreForward | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitThresholdControl | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); + + /* Write to ETHERNET DMAOMR */ + ETH_DMA->DMAOMR = (u32)tmpreg; + +/*------------------------ ETHERNET DMABMR Configuration ---------------------*/ + /* Set the AAL bit according to ETH_AddressAlignedBeats value */ + /* Set the FB bit according to ETH_FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ + /* Set the DSL bit according to ETH_DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH_DMAArbitration value */ + ETH_DMA->DMABMR = (u32)(ETH_InitStruct->ETH_AddressAlignedBeats | + ETH_InitStruct->ETH_FixedBurst | + ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->ETH_TxDMABurstLength | + (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | + ETH_InitStruct->ETH_DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ +#endif /* _ETH_DMA */ + + /* Return Ethernet configuration success */ + return ETH_SUCCESS; +} + +/******************************************************************************* +* Function Name : ETH_StructInit +* Desciption : Fills each ETH_InitStruct member with its default value. +* Input : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) +{ + /* ETH_InitStruct members default value */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_JumboFrame = ETH_JumboFrame_Disable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + +#ifdef _ETH_DMA +/*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; + +#endif /* _ETH_DMA */ +} + +/******************************************************************************* +* Function Name : ETH_Start +* Desciption : Enables ENET MAC and DMA reception/transmission +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_Start(void) +{ + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionCmd(ENABLE); + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(); + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionCmd(ENABLE); + +#ifdef _ETH_DMA + /* Start DMA transmission */ + ETH_DMATransmissionCmd(ENABLE); + /* Start DMA reception */ + ETH_DMAReceptionCmd(ENABLE); +#endif /* _ETH_DMA */ +} + +#ifdef _ETH_DMA +/******************************************************************************* +* Function Name : ETH_HandleTxPkt +* Desciption : Transmits a packet, from application buffer, pointed by ppkt. +* Input : - ppkt: pointer to application packet Buffer. +* - FrameLength: Tx Packet size. +* Output : None +* Return : ETH_ERROR: in case of Tx desc owned by DMA +* ETH_SUCCESS: for correct transmission +*******************************************************************************/ +u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength) +{ + + // Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET) + { + // Return ERROR: OWN bit set + return ETH_ERROR; + } + + //Set the DMA buffer address to send to the Packet we received from stack + DMATxDescToSet->Buffer1Addr = (u32)addr; + + // Setting the Frame Length: bits[12:0] + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + + // Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + + // Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + // When Tx Buffer unavailable flag is set: clear it and resume transmission + if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET) + { + // Clear TBUS ETHERNET DMA flag + ETH_DMA->DMASR = ETH_DMASR_TBUS; + // Resume DMA transmission + ETH_DMA->DMATPDR = 0; + } + + // Update the ETHERNET DMA global Tx descriptor with next Tx decriptor + // Chained Mode + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET) + { + // Selects the next DMA Tx descriptor list for next buffer to send + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + } + else // Ring Mode + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET) + { + // Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR); + } + else + { + // Selects the next DMA Tx descriptor list for next buffer to send + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + + // Return SUCCESS + return ETH_SUCCESS; +} + +/******************************************************************************* +* Function Name : ETH_HandleRxPkt +* Desciption : Receives a packet and copies it to memory pointed by ppkt. +* Input : None +* Output : ppkt: pointer on application receive buffer. +* Return : ETH_ERROR: if there is error in reception +* Received packet size: if packet reception is correct +*******************************************************************************/ +u32 ETH_HandleRxPkt(u32 addr) +{ + // Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET) + { + // Return error: OWN bit set + return ETH_ERROR; + } + + //Set the buffer address to rcv frame for the same descriptor (reserved packet) + DMARxDescToGet->Buffer1Addr = addr; + + if(addr) { + // Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + } + + // Update the ETHERNET DMA global Rx descriptor with next Rx decriptor + // Chained Mode + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET) + { + // Selects the next DMA Rx descriptor list for next buffer to read + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else // Ring Mode + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET) + { + // Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR); + } + else + { + // Selects the next DMA Rx descriptor list for next buffer to read + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return(1); +} + + +/******************************************************************************* +* Function Name : ETH_GetRxPktSize +* Desciption : Get the size of received the received packet. +* Input : None +* Output : None +* Return : Rx packet size +*******************************************************************************/ +u32 ETH_GetRxPktSize(void) +{ + u32 FrameLength = 0; + + //Test DMARxDescToGet is not NULL + if(DMARxDescToGet) + { + /* Get the size of the packet: including 4 bytes of the CRC */ + FrameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + + } + + /* Return Frame Length */ + return FrameLength; +} + +/******************************************************************************* +* Function Name : ETH_DropRxPkt +* Desciption : Drop a Received packet (too small packet, etc...) +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DropRxPkt(void) +{ + + // Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + + // Chained Mode + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET) + { + // Selects the next DMA Rx descriptor list for next buffer read + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else // Ring Mode + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET) + { + // Selects the next DMA Rx descriptor list for next buffer read: this will + // be the first Rx descriptor in this case + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR); + } + else + { + // Selects the next DMA Rx descriptor list for next buffer read + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +#endif /* _ETH_DMA */ +/*--------------------------------- PHY ------------------------------------*/ + +/******************************************************************************* +* Function Name : ETH_ReadPHYRegister +* Desciption : Read a PHY register +* Input : - PHYAddress: PHY device address, is the index of one of supported +* 32 PHY devices. +* This parameter can be one of the following values: 0,..,31 +* - PHYReg: PHY register address, is the index of one of the 32 +* PHY register. +* This parameter can be one of the following values: +* - PHY_BCR : Tranceiver Basic Control Register +* - PHY_BSR : Tranceiver Basic Status Register +* - PHY_SR : Tranceiver Status Register +* - More PHY register could be read depending on the used PHY +* Output : None +* Return : ETH_ERROR: in case of timeout +* Data read from the selected PHY register: for correct read +*******************************************************************************/ +u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg) +{ + u32 tmpreg = 0; + u32 timeout = 0; + + /* Check the parameters */ + eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + eth_assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH_MAC->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + + /* Prepare the MII address register value */ + tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Write the result value into the MII Address register */ + ETH_MAC->MACMIIAR = tmpreg; + + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH_MAC->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_READ_TO)); + + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return (u16)ETH_ERROR; + } + + /* Return data register value */ + return (u16)(ETH_MAC->MACMIIDR); +} + +/******************************************************************************* +* Function Name : ETH_WritePHYRegister +* Desciption : Write to a PHY register +* Input : - PHYAddress: PHY device address, is the index of one of supported +* 32 PHY devices. +* This parameter can be one of the following values: 0,..,31 +* - PHYReg: PHY register address, is the index of one of the 32 +* PHY register. +* This parameter can be one of the following values: +* - PHY_BCR : Tranceiver Control Register +* - More PHY register could be written depending on the used PHY +* - PHYValue: the value to write +* Output : None +* Return : ETH_ERROR: in case of timeout +* ETH_SUCCESS: for correct read +*******************************************************************************/ +u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue) +{ + u32 tmpreg = 0; + u32 timeout = 0; + + /* Check the parameters */ + eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + eth_assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH_MAC->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + + /* Prepare the MII register address value */ + tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Give the value to the MII data register */ + ETH_MAC->MACMIIDR = PHYValue; + + /* Write the result value into the MII Address register */ + ETH_MAC->MACMIIAR = tmpreg; + + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH_MAC->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_WRITE_TO)); + + /* Return ERROR in case of timeout */ + if(timeout == PHY_WRITE_TO) + { + return ETH_ERROR; + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/******************************************************************************* +* Function Name : ETH_PHYLoopBackCmd +* Desciption : Enables or disables the PHY loopBack mode. +* Input : - PHYAddress: PHY device address, is the index of one of supported +* 32 PHY devices. +* This parameter can be one of the following values: +* - NewState: new state of the PHY loopBack mode. +* This parameter can be: ENABLE or DISABLE. +* Note: Don't be confused with ETH_MACLoopBackCmd function +* which enables internal loopback at MII level +* Output : None +* Return : None +*******************************************************************************/ +u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState) +{ + u16 tmpreg = 0; + + /* Check the parameters */ + eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the PHY configuration to update it */ + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if (NewState != DISABLE) + { + /* Enable the PHY loopback mode */ + tmpreg |= PHY_Loopback; + } + else + { + /* Disable the PHY loopback mode: normal mode */ + tmpreg &= (u16)(~(u16)PHY_Loopback); + } + + /* Update the PHY control register with the new configuration */ + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (u32)RESET) + { + return ETH_SUCCESS; + } + else + { + /* Return SUCCESS */ + return ETH_ERROR; + } +} + +/*--------------------------------- MAC ------------------------------------*/ + +/******************************************************************************* +* Function Name : ETH_MACTransmissionCmd +* Desciption : Enables or disables the MAC transmission. +* Input : - NewState: new state of the MAC transmission. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC transmission */ + ETH_MAC->MACCR |= ETH_MACCR_TE; + } + else + { + /* Disable the MAC transmission */ + ETH_MAC->MACCR &= ~ETH_MACCR_TE; + } +} + +/******************************************************************************* +* Function Name : ETH_MACReceptionCmd +* Desciption : Enables or disables the MAC reception. +* Input : - NewState: new state of the MAC reception. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC reception */ + ETH_MAC->MACCR |= ETH_MACCR_RE; + } + else + { + /* Disable the MAC reception */ + ETH_MAC->MACCR &= ~ETH_MACCR_RE; + } +} + +/******************************************************************************* +* Function Name : ETH_GetFlowControlBusyStatus +* Desciption : Checks whether the ETHERNET flow control busy bit is set or not. +* Input : None +* Output : None +* Return : The new state of flow control busy status bit (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + + /* The Flow Control register should not be written to until this bit is cleared */ + if ((ETH_MAC->MACFCR & ETH_MACFCR_FCBBPA) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_InitiatePauseControlFrame +* Desciption : Initiate a Pause Control Frame (Full-duplex only). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_InitiatePauseControlFrame(void) +{ + /* When Set In full duplex MAC initiates pause control frame */ + ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/******************************************************************************* +* Function Name : ETH_BackPressureActivationCmd +* Desciption : Enables or disables the MAC BackPressure operation activation (Half-duplex only). +* Input : - NewState: new state of the MAC BackPressure operation activation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Activate the MAC BackPressure operation */ + /* In Half duplex: during backpressure, when the MAC receives a new frame, + the transmitter starts sending a JAM pattern resulting in a collision */ + ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + /* Desactivate the MAC BackPressure operation */ + ETH_MAC->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/******************************************************************************* +* Function Name : ETH_GetMACFlagStatus +* Desciption : Checks whether the specified ETHERNET MAC flag is set or not. +* Input : - ETH_MAC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - ETH_MAC_FLAG_TST : Time stamp trigger flag +* - ETH_MAC_FLAG_MMCT : MMC transmit flag +* - ETH_MAC_FLAG_MMCR : MMC receive flag +* - ETH_MAC_FLAG_MMC : MMC flag +* - ETH_MAC_FLAG_PMT : PMT flag +* Output : None +* Return : The new state of ETHERNET MAC flag (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); + + if ((ETH_MAC->MACSR & ETH_MAC_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_GetMACITStatus +* Desciption : Checks whether the specified ETHERNET MAC interrupt has occurred or not. +* Input : - ETH_MAC_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - ETH_MAC_IT_TST : Time stamp trigger interrupt +* - ETH_MAC_IT_MMCT : MMC transmit interrupt +* - ETH_MAC_IT_MMCR : MMC receive interrupt +* - ETH_MAC_IT_MMC : MMC interrupt +* - ETH_MAC_IT_PMT : PMT interrupt +* Output : None +* Return : The new state of ETHERNET MAC interrupt (SET or RESET). +*******************************************************************************/ +ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); + + if ((ETH_MAC->MACSR & ETH_MAC_IT) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_MACITConfig +* Desciption : Enables or disables the specified ETHERNET MAC interrupts. +* Input : - ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be +* enabled or disabled. +* This parameter can be any combination of the following values: +* - ETH_MAC_IT_TST : Time stamp trigger interrupt +* - ETH_MAC_IT_PMT : PMT interrupt +* - NewState: new state of the specified ETHERNET MAC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC interrupts */ + ETH_MAC->MACIMR &= (~(u32)ETH_MAC_IT); + } + else + { + /* Disable the selected ETHERNET MAC interrupts */ + ETH_MAC->MACIMR |= ETH_MAC_IT; + } +} + +/******************************************************************************* +* Function Name : ETH_MACAddressConfig +* Desciption : Configures the selected MAC address. +* Input : - MacAddr: The MAC addres to configure. +* This parameter can be one of the following values: +* - ETH_MAC_Address0 : MAC Address0 +* - ETH_MAC_Address1 : MAC Address1 +* - ETH_MAC_Address2 : MAC Address2 +* - ETH_MAC_Address3 : MAC Address3 +* - Addr: Pointer on MAC address buffer data (6 bytes). +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr) +{ + u32 tmpreg; + + /* Check the parameters */ + eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Calculate the selectecd MAC address high register */ + tmpreg = ((u32)Addr[5] << 8) | (u32)Addr[4]; + + /* Load the selectecd MAC address high register */ + (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg; + + /* Calculate the selectecd MAC address low register */ + tmpreg = ((u32)Addr[3] << 24) | ((u32)Addr[2] << 16) | ((u32)Addr[1] << 8) | Addr[0]; + + /* Load the selectecd MAC address low register */ + (*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg; +} + +/******************************************************************************* +* Function Name : ETH_GetMACAddress +* Desciption : Get the selected MAC address. +* Input : - MacAddr: The MAC addres to return. +* This parameter can be one of the following values: +* - ETH_MAC_Address0 : MAC Address0 +* - ETH_MAC_Address1 : MAC Address1 +* - ETH_MAC_Address2 : MAC Address2 +* - ETH_MAC_Address3 : MAC Address3 +* - Addr: Pointer on MAC address buffer data (6 bytes). +* Output : None +* Return : None +*******************************************************************************/ +void ETH_GetMACAddress(u32 MacAddr, u8 *Addr) +{ + u32 tmpreg; + + /* Check the parameters */ + eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Get the selectecd MAC address high register */ + tmpreg =(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)); + + /* Calculate the selectecd MAC address buffer */ + Addr[5] = ((tmpreg >> 8) & (u8)0xFF); + Addr[4] = (tmpreg & (u8)0xFF); + + /* Load the selectecd MAC address low register */ + tmpreg =(*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr)); + + /* Calculate the selectecd MAC address buffer */ + Addr[3] = ((tmpreg >> 24) & (u8)0xFF); + Addr[2] = ((tmpreg >> 16) & (u8)0xFF); + Addr[1] = ((tmpreg >> 8 ) & (u8)0xFF); + Addr[0] = (tmpreg & (u8)0xFF); +} + +/******************************************************************************* +* Function Name : ETH_MACAddressPerfectFilterCmd +* Desciption : Enables or disables the Address filter module uses the specified +* ETHERNET MAC address for perfect filtering +* Input : - MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering. +* This parameter can be one of the following values: +* - ETH_MAC_Address1 : MAC Address1 +* - ETH_MAC_Address2 : MAC Address2 +* - ETH_MAC_Address3 : MAC Address3 +* - NewState: new state of the specified ETHERNET MAC address use. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC address for perfect filtering */ + (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + /* Disable the selected ETHERNET MAC address for perfect filtering */ + (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_AE); + } +} + +/******************************************************************************* +* Function Name : ETH_MACAddressFilterConfig +* Desciption : Set the filter type for the specified ETHERNET MAC address +* Input : - MacAddr: specifies the ETHERNET MAC address +* This parameter can be one of the following values: +* - ETH_MAC_Address1 : MAC Address1 +* - ETH_MAC_Address2 : MAC Address2 +* - ETH_MAC_Address3 : MAC Address3 +* - Filter: specifies the used frame received field for comparaison +* This parameter can be one of the following values: +* - ETH_MAC_AddressFilter_SA : MAC Address is used to compare +* with the SA fields of the received frame. +* - ETH_MAC_AddressFilter_DA : MAC Address is used to compare +* with the DA fields of the received frame. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + eth_assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); + + if (Filter != ETH_MAC_AddressFilter_DA) + { + /* The selected ETHERNET MAC address is used to compare with the SA fields of the + received frame. */ + (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + /* The selected ETHERNET MAC address is used to compare with the DA fields of the + received frame. */ + (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_SA); + } +} + +/******************************************************************************* +* Function Name : ETH_MACAddressMaskBytesFilterConfig +* Desciption : Set the filter type for the specified ETHERNET MAC address +* Input : - MacAddr: specifies the ETHERNET MAC address +* This parameter can be one of the following values: +* - ETH_MAC_Address1 : MAC Address1 +* - ETH_MAC_Address2 : MAC Address2 +* - ETH_MAC_Address3 : MAC Address3 +* - MaskByte: specifies the used address bytes for comparaison +* This parameter can be any combination of the following values: +* - ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. +* - ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. +* - ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. +* - ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16]. +* - ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8]. +* - ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0]. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + eth_assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); + + /* Clear MBC bits in the selected MAC address high register */ + (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_MBC); + + /* Set the selected Filetr mask bytes */ + (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte; +} + +/*------------------------ DMA Tx/Rx Desciptors ----------------------------*/ +#ifdef _ETH_DMA +/******************************************************************************* +* Function Name : ETH_DMATxDescChainInit +* Desciption : Initializes the DMA Tx descriptors in chain mode. +* Input : - DMATxDescTab: Pointer on the first Tx desc list +* - TxBuff: Pointer on the first TxBuffer list +* - TxBuffCount: Number of the used Tx desc in the list +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8* TxBuff, u32 TxBuffCount) +{ + u32 i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + + /* Set Second Address Chained bit */ + DMATxDesc->Status = ETH_DMATxDesc_TCH; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (u32)*((u32*)TxBuff + i); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH_DMA->DMATDLAR = (u32) DMATxDescTab; +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescRingInit +* Desciption : Initializes the DMA Tx descriptors in ring mode. +* Input : - DMATxDescTab: Pointer on the first Tx desc list +* - TxBuff1: Pointer on the first TxBuffer1 list +* - TxBuff2: Pointer on the first TxBuffer2 list +* - TxBuffCount: Number of the used Tx desc in the list +* Note: see decriptor skip length defined in ETH_DMA_InitStruct + for the number of Words to skip between two unchained descriptors. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount) +{ + u32 i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (u32)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMATxDesc->Buffer2NextDescAddr = (u32)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (TxBuffCount-1)) + { + /* Set Transmit End of Ring bit */ + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH_DMA->DMATDLAR = (u32) DMATxDescTab; +} + +/******************************************************************************* +* Function Name : ETH_GetDMATxDescFlagStatus +* Desciption : Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. +* Input : - DMATxDesc: pointer on a DMA Tx descriptor +* - ETH_DMATxDescFlag: specifies the flag to check. +* This parameter can be one of the following values: +* - ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine +* - ETH_DMATxDesc_IC : Interrupt on completetion +* - ETH_DMATxDesc_LS : Last Segment +* - ETH_DMATxDesc_FS : First Segment +* - ETH_DMATxDesc_DC : Disable CRC +* - ETH_DMATxDesc_DP : Disable Pad +* - ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable +* - ETH_DMATxDesc_TER : Transmit End of Ring +* - ETH_DMATxDesc_TCH : Second Address Chained +* - ETH_DMATxDesc_TTSS: Tx Time Stamp Status +* - ETH_DMATxDesc_IHE : IP Header Error +* - ETH_DMATxDesc_ES : Error summary +* - ETH_DMATxDesc_JT : Jabber Timeout +* - ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush +* - ETH_DMATxDesc_PCE : Payload Checksum Error +* - ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission +* - ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver +* - ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision +* - ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions +* - ETH_DMATxDesc_VF : VLAN Frame +* - ETH_DMATxDesc_CC : Collision Count +* - ETH_DMATxDesc_ED : Excessive Deferral +* - ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory +* - ETH_DMATxDesc_DB : Deferred Bit +* Output : None +* Return : The new state of ETH_DMATxDescFlag (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); + + if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_GetDMATxDescCollisionCount +* Desciption : Returns the specified ETHERNET DMA Tx Desc collision count. +* Input : - DMATxDesc: pointer on a DMA Tx descriptor +* Output : None +* Return : The Transmit descriptor collision counter value. +*******************************************************************************/ +u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift); +} + +/******************************************************************************* +* Function Name : ETH_SetDMATxDescOwnBit +* Desciption : Set the specified DMA Tx Desc Own bit. +* Input : - DMATxDesc: Pointer on a Tx desc +* Output : None +* Return : None +*******************************************************************************/ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Set the DMA Tx Desc Own bit */ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescTransmitITConfig +* Desciption : Enables or disables the specified DMA Tx Desc Transmit interrupt. +* Input : - DMATxDesc: Pointer on a Tx desc +* - NewState: new state of the DMA Tx Desc transmit interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + /* Disable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_IC); + } +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescFrameSegmentConfig +* Desciption : Enables or disables the specified DMA Tx Desc Transmit interrupt. +* Input : - DMATxDesc: Pointer on a Tx desc +* - FrameSegment: specifies is the actual Tx desc contain last or first segment. +* This parameter can be one of the following values: +* - ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment +* - ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); + + /* Selects the DMA Tx Desc Frame segment */ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescChecksumInsertionConfig +* Desciption : Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. +* Input : - DMATxDesc: pointer on a DMA Tx descriptor +* - Checksum: specifies is the DMA Tx desc checksum insertion. +* This parameter can be one of the following values: +* - ETH_DMATxDesc_ChecksumByPass : Checksum bypass +* - ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum +* - ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present +* - ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header +* Output : None +* Return : The Transmit descriptor collision. +*******************************************************************************/ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); + + /* Set the selected DMA Tx desc checksum insertion control */ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescCRCCmd +* Desciption : Enables or disables the DMA Tx Desc CRC. +* Input : - DMATxDesc: pointer on a DMA Tx descriptor +* - NewState: new state of the specified DMA Tx Desc CRC. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc CRC */ + DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DC); + } + else + { + /* Disable the selected DMA Tx Desc CRC */ + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescEndOfRingCmd +* Desciption : Enables or disables the DMA Tx Desc end of ring. +* Input : - DMATxDesc: pointer on a DMA Tx descriptor +* - NewState: new state of the specified DMA Tx Desc end of ring. +* This parameter can be: ENABLE or DISABLE. +* Output : NoneH +* Return : None +*******************************************************************************/ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + /* Disable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_TER); + } +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescSecondAddressChainedCmd +* Desciption : Enables or disables the DMA Tx Desc second address chained. +* Input : - DMATxDesc: pointer on a DMA Tx descriptor +* - NewState: new state of the specified DMA Tx Desc second address chained. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + /* Disable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TCH); + } +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescShortFramePaddingCmd +* Desciption : Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. +* Input : - DMATxDesc: pointer on a DMA Tx descriptor +* - NewState: new state of the specified DMA Tx Desc padding for +* frame shorter than 64 bytes. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ + DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DP); + } + else + { + /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescTimeStampCmd +* Desciption : Enables or disables the DMA Tx Desc time stamp. +* Input : - DMATxDesc: pointer on a DMA Tx descriptor +* - NewState: new state of the specified DMA Tx Desc time stamp. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + /* Disable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TTSE); + } +} + +/******************************************************************************* +* Function Name : ETH_DMATxDescBufferSizeConfig +* Desciption : Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. +* Input : - DMATxDesc: Pointer on a Tx desc +* - BufferSize1: specifies the Tx desc buffer1 size. +* - BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used). +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); + eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); + + /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift)); +} + +/******************************************************************************* +* Function Name : ETH_DMARxDescChainInit +* Desciption : Initializes the DMA Rx descriptors in chain mode. +* Input : - DMARxDescTab: Pointer on the first Rx desc list +* - RxBuff: Pointer on the first RxBuffer list +* - RxBuffCount: Number of the used Rx desc in the list +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount) +{ + u32 i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; +// DMARxDesc->Status = 0; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE; + + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (u32)*((u32*)RxBuff + i); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab); + } + } + + /* Set Receive Desciptor List Address Register */ + ETH_DMA->DMARDLAR = (u32) DMARxDescTab; +} + +/******************************************************************************* +* Function Name : ETH_DMARxDescRingInit +* Desciption : Initializes the DMA Rx descriptors in ring mode. +* Input : - DMARxDescTab: Pointer on the first Rx desc list +* - RxBuff1: Pointer on the first RxBuffer1 list +* - RxBuff2: Pointer on the first RxBuffer2 list +* - RxBuffCount: Number of the used Rx desc in the list +* Note: see decriptor skip length defined in ETH_DMA_InitStruct + for the number of Words to skip between two unchained descriptors. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount) +{ + u32 i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size */ + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (u32)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMARxDesc->Buffer2NextDescAddr = (u32)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (RxBuffCount-1)) + { + /* Set Receive End of Ring bit */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + /* Set Receive Desciptor List Address Register */ + ETH_DMA->DMARDLAR = (u32) DMARxDescTab; +} + +/******************************************************************************* +* Function Name : ETH_GetDMARxDescFlagStatus +* Desciption : Checks whether the specified ETHERNET Rx Desc flag is set or not. +* Input : - DMARxDesc: pointer on a DMA Rx descriptor +* - ETH_DMARxDescFlag: specifies the flag to check. +* This parameter can be one of the following values: +* - ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine +* - ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame +* - ETH_DMARxDesc_ES: Error summary +* - ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame +* - ETH_DMARxDesc_SAF: SA Filter Fail for the received frame +* - ETH_DMARxDesc_LE: Frame size not matching with length field +* - ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow +* - ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame +* - ETH_DMARxDesc_FS: First descriptor of the frame +* - ETH_DMARxDesc_LS: Last descriptor of the frame +* - ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error +* - ETH_DMARxDesc_RxLongFrame: (Giant Frame)Rx - frame is longer than 1518/1522 +* - ETH_DMARxDesc_LC: Late collision occurred during reception +* - ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 +* - ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception +* - ETH_DMARxDesc_RE: Receive error: error reported by MII interface +* - ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits +* - ETH_DMARxDesc_CE: CRC error +* - ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error +* Output : None +* Return : The new state of ETH_DMARxDescFlag (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag)); + + if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_SetDMARxDescOwnBit +* Desciption : Set the specified DMA Rx Desc Own bit. +* Input : - DMARxDesc: Pointer on a Rx desc +* Output : None +* Return : None +*******************************************************************************/ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Set the DMA Rx Desc Own bit */ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/******************************************************************************* +* Function Name : ETH_GetDMARxDescFrameLength +* Desciption : Returns the specified DMA Rx Desc frame length. +* Input : - DMARxDesc: pointer on a DMA Rx descriptor +* Output : None +* Return : The Rx descriptor received frame length. +*******************************************************************************/ +u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift); +} + +/******************************************************************************* +* Function Name : ETH_DMARxDescReceiveITConfig +* Desciption : Enables or disables the specified DMA Rx Desc receive interrupt. +* Input : - DMARxDesc: Pointer on a Rx desc +* - NewState: new state of the specified DMA Rx Desc interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_DIC); + } + else + { + /* Disable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/******************************************************************************* +* Function Name : ETH_DMARxDescEndOfRingCmd +* Desciption : Enables or disables the DMA Rx Desc end of ring. +* Input : - DMARxDesc: pointer on a DMA Rx descriptor +* - NewState: new state of the specified DMA Rx Desc end of ring. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + /* Disable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RER); + } +} + +/******************************************************************************* +* Function Name : ETH_DMARxDescSecondAddressChainedCmd +* Desciption : Enables or disables the DMA Rx Desc second address chained. +* Input : - DMARxDesc: pointer on a DMA Rx descriptor +* - NewState: new state of the specified DMA Rx Desc second address chained. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + /* Disable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RCH); + } +} + +/******************************************************************************* +* Function Name : ETH_GetDMARxDescBufferSize +* Desciption : Returns the specified ETHERNET DMA Rx Desc buffer size. +* Input : - DMARxDesc: pointer on a DMA Rx descriptor +* - DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. +* This parameter can be any one of the following values: +* - ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 +* - ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 +* Output : None +* Return : The Receive descriptor frame length. +*******************************************************************************/ +u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); + + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + /* Return the DMA Rx Desc buffer2 size */ + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift); + } + else + { + /* Return the DMA Rx Desc buffer1 size */ + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/*--------------------------------- DMA ------------------------------------*/ +/******************************************************************************* +* Function Name : ETH_SoftwareReset +* Desciption : Resets all MAC subsystem internal registers and logic. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_SoftwareReset(void) +{ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + ETH_DMA->DMABMR |= ETH_DMABMR_SR; +} + +/******************************************************************************* +* Function Name : ETH_GetSoftwareResetStatus +* Desciption : Checks whether the ETHERNET software reset bit is set or not. +* Input : None +* Output : None +* Return : The new state of DMA Bus Mode register SR bit (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH_DMA->DMABMR & ETH_DMABMR_SR) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_GetDMAFlagStatus +* Desciption : Checks whether the specified ETHERNET DMA flag is set or not. +* Input : - ETH_DMA_IT: specifies the flag to check. +* This parameter can be one of the following values: +* - ETH_DMA_FLAG_TST : Time-stamp trigger flag +* - ETH_DMA_FLAG_PMT : PMT flag +* - ETH_DMA_FLAG_MMC : MMC flag +* - ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access +* - ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr +* - ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA +* - ETH_DMA_FLAG_NIS : Normal interrupt summary flag +* - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag +* - ETH_DMA_FLAG_ER : Early receive flag +* - ETH_DMA_FLAG_FBE : Fatal bus error flag +* - ETH_DMA_FLAG_ET : Early transmit flag +* - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag +* - ETH_DMA_FLAG_RPS : Receive process stopped flag +* - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag +* - ETH_DMA_FLAG_R : Receive flag +* - ETH_DMA_FLAG_TU : Underflow flag +* - ETH_DMA_FLAG_RO : Overflow flag +* - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag +* - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag +* - ETH_DMA_FLAG_TPS : Transmit process stopped flag +* - ETH_DMA_FLAG_T : Transmit flag +* Output : None +* Return : The new state of ETH_DMA_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); + + if ((ETH_DMA->DMASR & ETH_DMA_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_DMAClearFlag +* Desciption : Clears the ETHERNET?s DMA pending flag. +* Input : - ETH_DMA_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - ETH_DMA_FLAG_NIS : Normal interrupt summary flag +* - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag +* - ETH_DMA_FLAG_ER : Early receive flag +* - ETH_DMA_FLAG_FBE : Fatal bus error flag +* - ETH_DMA_FLAG_ETI : Early transmit flag +* - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag +* - ETH_DMA_FLAG_RPS : Receive process stopped flag +* - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag +* - ETH_DMA_FLAG_R : Receive flag +* - ETH_DMA_FLAG_TU : Transmit Underflow flag +* - ETH_DMA_FLAG_RO : Receive Overflow flag +* - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag +* - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag +* - ETH_DMA_FLAG_TPS : Transmit process stopped flag +* - ETH_DMA_FLAG_T : Transmit flag +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMAClearFlag(u32 ETH_DMA_FLAG) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); + + /* Clear the selected ETHERNET DMA FLAG */ + ETH_DMA->DMASR = (u32) ETH_DMA_FLAG; +} + +/******************************************************************************* +* Function Name : ETH_GetDMAITStatus +* Desciption : Checks whether the specified ETHERNET DMA interrupt has occured or not. +* Input : - ETH_DMA_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - ETH_DMA_IT_TST : Time-stamp trigger interrupt +* - ETH_DMA_IT_PMT : PMT interrupt +* - ETH_DMA_IT_MMC : MMC interrupt +* - ETH_DMA_IT_NIS : Normal interrupt summary +* - ETH_DMA_IT_AIS : Abnormal interrupt summary +* - ETH_DMA_IT_ER : Early receive interrupt +* - ETH_DMA_IT_FBE : Fatal bus error interrupt +* - ETH_DMA_IT_ET : Early transmit interrupt +* - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt +* - ETH_DMA_IT_RPS : Receive process stopped interrupt +* - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt +* - ETH_DMA_IT_R : Receive interrupt +* - ETH_DMA_IT_TU : Underflow interrupt +* - ETH_DMA_IT_RO : Overflow interrupt +* - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt +* - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt +* - ETH_DMA_IT_TPS : Transmit process stopped interrupt +* - ETH_DMA_IT_T : Transmit interrupt +* Output : None +* Return : The new state of ETH_DMA_IT (SET or RESET). +*******************************************************************************/ +ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); + + if ((ETH_DMA->DMASR & ETH_DMA_IT) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_DMAClearITPendingBit +* Desciption : Clears the ETHERNET?s DMA IT pending bit. +* Input : - ETH_DMA_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - ETH_DMA_IT_NIS : Normal interrupt summary +* - ETH_DMA_IT_AIS : Abnormal interrupt summary +* - ETH_DMA_IT_ER : Early receive interrupt +* - ETH_DMA_IT_FBE : Fatal bus error interrupt +* - ETH_DMA_IT_ETI : Early transmit interrupt +* - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt +* - ETH_DMA_IT_RPS : Receive process stopped interrupt +* - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt +* - ETH_DMA_IT_R : Receive interrupt +* - ETH_DMA_IT_TU : Transmit Underflow interrupt +* - ETH_DMA_IT_RO : Receive Overflow interrupt +* - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt +* - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt +* - ETH_DMA_IT_TPS : Transmit process stopped interrupt +* - ETH_DMA_IT_T : Transmit interrupt +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + + /* Clear the selected ETHERNET DMA IT */ + ETH_DMA->DMASR = (u32) ETH_DMA_IT; +} + +/******************************************************************************* +* Function Name : ETH_GetDMATransmitProcessState +* Desciption : Returns the ETHERNET DMA Transmit Process State. +* Input : None +* Output : None +* Return : The new ETHERNET DMA Transmit Process State: +* This can be one of the following values: +* - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued +* - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor +* - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status +* - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory +* - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe +* - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor +*******************************************************************************/ +u32 ETH_GetTransmitProcessState(void) +{ + return ((u32)(ETH_DMA->DMASR & ETH_DMASR_TS)); +} + +/******************************************************************************* +* Function Name : ETH_GetDMAReceiveProcessState +* Desciption : Returns the ETHERNET DMA Receive Process State. +* Input : None +* Output : None +* Return : The new ETHERNET DMA Receive Process State: +* This can be one of the following values: +* - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued +* - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor +* - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet +* - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable +* - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor +* - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory +*******************************************************************************/ +u32 ETH_GetReceiveProcessState(void) +{ + return ((u32)(ETH_DMA->DMASR & ETH_DMASR_RS)); +} + +/******************************************************************************* +* Function Name : ETH_FlushTransmitFIFO +* Desciption : Clears the ETHERNET transmit FIFO. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_FlushTransmitFIFO(void) +{ + /* Set the Flush Transmit FIFO bit */ + ETH_DMA->DMAOMR |= ETH_DMAOMR_FTF; +} + +/******************************************************************************* +* Function Name : ETH_GetFlushTransmitFIFOStatus +* Desciption : Checks whether the ETHERNET transmit FIFO bit is cleared or not. +* Input : None +* Output : None +* Return : The new state of ETHERNET flush transmit FIFO bit (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((ETH_DMA->DMAOMR & ETH_DMAOMR_FTF) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_DMATransmissionCmd +* Desciption : Enables or disables the DMA transmission. +* Input : - NewState: new state of the DMA transmission. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transmission */ + ETH_DMA->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + /* Disable the DMA transmission */ + ETH_DMA->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/******************************************************************************* +* Function Name : ETH_DMAReceptionCmd +* Desciption : Enables or disables the DMA reception. +* Input : - NewState: new state of the DMA reception. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA reception */ + ETH_DMA->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + /* Disable the DMA reception */ + ETH_DMA->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/******************************************************************************* +* Function Name : ETH_DMAITConfig +* Desciption : Enables or disables the specified ETHERNET DMA interrupts. +* Input : - ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be +* enabled or disabled. +* This parameter can be any combination of the following values: +* - ETH_DMA_IT_NIS : Normal interrupt summary +* - ETH_DMA_IT_AIS : Abnormal interrupt summary +* - ETH_DMA_IT_ER : Early receive interrupt +* - ETH_DMA_IT_FBE : Fatal bus error interrupt +* - ETH_DMA_IT_ET : Early transmit interrupt +* - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt +* - ETH_DMA_IT_RPS : Receive process stopped interrupt +* - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt +* - ETH_DMA_IT_R : Receive interrupt +* - ETH_DMA_IT_TU : Underflow interrupt +* - ETH_DMA_IT_RO : Overflow interrupt +* - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt +* - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt +* - ETH_DMA_IT_TPS : Transmit process stopped interrupt +* - ETH_DMA_IT_T : Transmit interrupt +* - NewState: new state of the specified ETHERNET DMA interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET DMA interrupts */ + ETH_DMA->DMAIER |= ETH_DMA_IT; + } + else + { + /* Disable the selected ETHERNET DMA interrupts */ + ETH_DMA->DMAIER &=(~(u32)ETH_DMA_IT); + } +} + +/******************************************************************************* +* Function Name : ETH_GetDMAOverflowStatus +* Desciption : Checks whether the specified ETHERNET DMA overflow flag is set or not. +* Input : - ETH_DMA_Overflow: specifies the DMA overflow flag to check. +* This parameter can be one of the following values: +* - ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter +* - ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter +* Output : None +* Return : The new state of ETHERNET DMA overflow Flag (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); + + if ((ETH_DMA->DMAMFBOCR & ETH_DMA_Overflow) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_GetRxOverflowMissedFrameCounter +* Desciption : Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. +* Input : None +* Output : None +* Return : The value of Rx overflow Missed Frame Counter. +*******************************************************************************/ +u32 ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((u32)((ETH_DMA->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift)); +} + +/******************************************************************************* +* Function Name : ETH_GetBufferUnavailableMissedFrameCounter +* Desciption : Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. +* Input : None +* Output : None +* Return : The value of Buffer unavailable Missed Frame Counter. +*******************************************************************************/ +u32 ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((u32)(ETH_DMA->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/******************************************************************************* +* Function Name : ETH_GetCurrentTxDescStartAddress +* Desciption : Get the ETHERNET DMA DMACHTDR register value. +* Input : None +* Output : None +* Return : The value of the current Tx desc start address. +*******************************************************************************/ +u32 ETH_GetCurrentTxDescStartAddress(void) +{ + return ((u32)(ETH_DMA->DMACHTDR)); +} + +/******************************************************************************* +* Function Name : ETH_GetCurrentRxDescStartAddress +* Desciption : Get the ETHERNET DMA DMACHRDR register value. +* Input : None +* Output : None +* Return : The value of the current Rx desc start address. +*******************************************************************************/ +u32 ETH_GetCurrentRxDescStartAddress(void) +{ + return ((u32)(ETH_DMA->DMACHRDR)); +} + +/******************************************************************************* +* Function Name : ETH_GetCurrentTxBufferAddress +* Desciption : Get the ETHERNET DMA DMACHTBAR register value. +* Input : None +* Output : None +* Return : The value of the current Tx desc buffer address. +*******************************************************************************/ +u32 ETH_GetCurrentTxBufferAddress(void) +{ + return ((u32)(ETH_DMA->DMACHTBAR)); +} + +/******************************************************************************* +* Function Name : ETH_GetCurrentRxBufferAddress +* Desciption : Get the ETHERNET DMA DMACHRBAR register value. +* Input : None +* Output : None +* Return : The value of the current Rx desc buffer address. +*******************************************************************************/ +u32 ETH_GetCurrentRxBufferAddress(void) +{ + return ((u32)(ETH_DMA->DMACHRBAR)); +} + +/******************************************************************************* +* Function Name : ETH_ResumeDMATransmission +* Desciption : Resumes the DMA Transmission by writing to the DmaTxPollDemand +* register: (the data written could be anything). This forces +* the DMA to resume transmission. +* Input : None +* Output : None +* Return : None. +*******************************************************************************/ +void ETH_ResumeDMATransmission(void) +{ + ETH_DMA->DMATPDR = 0; +} + +/******************************************************************************* +* Function Name : ETH_ResumeDMAReception +* Desciption : Resumes the DMA Transmission by writing to the DmaRxPollDemand +* register: (the data written could be anything). This forces +* the DMA to resume reception. +* Input : None +* Output : None +* Return : None. +*******************************************************************************/ +void ETH_ResumeDMAReception(void) +{ + ETH_DMA->DMARPDR = 0; +} + +#endif /* _ETH_DMA */ +/*--------------------------------- PMT ------------------------------------*/ +/******************************************************************************* +* Function Name : ETH_ResetWakeUpFrameFilterRegisterPointer +* Desciption : Reset Wakeup frame filter register pointer. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ + ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/******************************************************************************* +* Function Name : ETH_SetWakeUpFrameFilterRegister +* Desciption : Populates the remote wakeup frame registers. +* Input : - Buffer: Pointer on remote WakeUp Frame Filter Register buffer +* data (8 words). +* Output : None +* Return : None +*******************************************************************************/ +void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer) +{ + u32 i = 0; + + /* Fill Remote Wake-up Frame Filter register with Buffer data */ + for(i =0; iMACRWUFFR = Buffer[i]; + } +} + +/******************************************************************************* +* Function Name : ETH_GlobalUnicastWakeUpCmd +* Desciption : Enables or disables any unicast packet filtered by the MAC +* (DAF) address recognition to be a wake-up frame. +* Input : - NewState: new state of the MAC Global Unicast Wake-Up. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Global Unicast Wake-Up */ + ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + /* Disable the MAC Global Unicast Wake-Up */ + ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/******************************************************************************* +* Function Name : ETH_GetPMTFlagStatus +* Desciption : Checks whether the specified ETHERNET PMT flag is set or not. +* Input : - ETH_PMT_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset +* - ETH_PMT_FLAG_WUFR : Wake-Up Frame Received +* - ETH_PMT_FLAG_MPR : Magic Packet Received +* Output : None +* Return : The new state of ETHERNET PMT Flag (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); + + if ((ETH_MAC->MACPMTCSR & ETH_PMT_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_WakeUpFrameDetectionCmd +* Desciption : Enables or disables the MAC Wake-Up Frame Detection. +* Input : - NewState: new state of the MAC Wake-Up Frame Detection. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Wake-Up Frame Detection */ + ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + /* Disable the MAC Wake-Up Frame Detection */ + ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/******************************************************************************* +* Function Name : ETH_MagicPacketDetectionCmd +* Desciption : Enables or disables the MAC Magic Packet Detection. +* Input : - NewState: new state of the MAC Magic Packet Detection. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Magic Packet Detection */ + ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + /* Disable the MAC Magic Packet Detection */ + ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/******************************************************************************* +* Function Name : ETH_PowerDownCmd +* Desciption : Enables or disables the MAC Power Down. +* Input : - NewState: new state of the MAC Power Down. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Power Down */ + /* This puts the MAC in power down mode */ + ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + /* Disable the MAC Power Down */ + ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/*--------------------------------- MMC ------------------------------------*/ +#ifdef _ETH_MMC + +/******************************************************************************* +* Function Name : ETH_MMCCounterFreezeCmd +* Desciption : Enables or disables the MMC Counter Freeze. +* Input : - NewState: new state of the MMC Counter Freeze. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter Freeze */ + ETH_MMC->MMCCR |= ETH_MMCCR_MCF; + } + else + { + /* Disable the MMC Counter Freeze */ + ETH_MMC->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/******************************************************************************* +* Function Name : ETH_MMCResetOnReadCmd +* Desciption : Enables or disables the MMC Reset On Read. +* Input : - NewState: new state of the MMC Reset On Read. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter reset on read */ + ETH_MMC->MMCCR |= ETH_MMCCR_ROR; + } + else + { + /* Disable the MMC Counter reset on read */ + ETH_MMC->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/******************************************************************************* +* Function Name : ETH_MMCCounterRolloverCmd +* Desciption : Enables or disables the MMC Counter Stop Rollover. +* Input : - NewState: new state of the MMC Counter Stop Rollover. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Disable the MMC Counter Stop Rollover */ + ETH_MMC->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + /* Enable the MMC Counter Stop Rollover */ + ETH_MMC->MMCCR |= ETH_MMCCR_CSR; + } +} + +/******************************************************************************* +* Function Name : ETH_MMCCountersReset +* Desciption : Resets the MMC Counters. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MMCCountersReset(void) +{ + /* Resets the MMC Counters */ + ETH_MMC->MMCCR |= ETH_MMCCR_CR; +} + +/******************************************************************************* +* Function Name : ETH_MMCITConfig +* Desciption : Enables or disables the specified ETHERNET MMC interrupts. +* Input : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt +* sources to be enabled or disabled. +* This parameter can be any combination of Tx interrupt or +* any combination of Rx interrupt (but not both)of the following values: +* - ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value +* - ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value +* - ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value +* - ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value +* - ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value +* - ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value +* - NewState: new state of the specified ETHERNET MMC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET) + { + /* Remove egister mak from IT */ + ETH_MMC_IT &= 0xEFFFFFFF; + + /* ETHERNET MMC Rx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH_MMC->MMCRIMR &=(~(u32)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH_MMC->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH_MMC->MMCTIMR &=(~(u32)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH_MMC->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/******************************************************************************* +* Function Name : ETH_GetMMCITStatus +* Desciption : Checks whether the specified ETHERNET MMC IT is set or not. +* Input : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt. +* This parameter can be one of the following values: +* - ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value +* - ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value +* - ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value +* - ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value +* - ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value +* - ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value +* Output : None +* Return : The value of ETHERNET MMC IT (SET or RESET). +*******************************************************************************/ +ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); + + if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET) + { + /* ETHERNET MMC Rx interrupts selected */ + /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ + if ((((ETH_MMC->MMCRIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ + if ((((ETH_MMC->MMCTIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_GetMMCRegister +* Desciption : Get the specified ETHERNET MMC register value. +* Input : - ETH_MMCReg: specifies the ETHERNET MMC register. +* This parameter can be one of the following values: +* - ETH_MMCCR : MMC CR register +* - ETH_MMCRIR : MMC RIR register +* - ETH_MMCTIR : MMC TIR register +* - ETH_MMCRIMR : MMC RIMR register +* - ETH_MMCTIMR : MMC TIMR register +* - ETH_MMCTGFSCCR : MMC TGFSCCR register +* - ETH_MMCTGFMSCCR: MMC TGFMSCCR register +* - ETH_MMCTGFCR : MMC TGFCR register +* - ETH_MMCRFCECR : MMC RFCECR register +* - ETH_MMCRFAECR : MMC RFAECR register +* - ETH_MMCRGUFCR : MMC RGUFCRregister +* Output : None +* Return : The value of ETHERNET MMC Register value. +*******************************************************************************/ +u32 ETH_GetMMCRegister(u32 ETH_MMCReg) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); + + /* Return the selected register value */ + return (*(vu32 *)(ETH_MAC_BASE + ETH_MMCReg)); +} +#endif /* _ETH_MMC */ + +/*--------------------------------- PTP ------------------------------------*/ +#ifdef _ETH_PTP + +/******************************************************************************* +* Function Name : ETH_EnablePTPTimeStampAddend +* Desciption : Updated the PTP block for fine correction with the Time Stamp +* Addend register value. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_EnablePTPTimeStampAddend(void) +{ + /* Enable the PTP block update with the Time Stamp Addend register value */ + ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/******************************************************************************* +* Function Name : ETH_EnablePTPTimeStampInterruptTrigger +* Desciption : Enable the PTP Time Stamp interrupt trigger +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + /* Enable the PTP target time interrupt */ + ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/******************************************************************************* +* Function Name : ETH_EnablePTPTimeStampUpdate +* Desciption : Updated the PTP system time with the Time Stamp Update register +* value. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_EnablePTPTimeStampUpdate(void) +{ + /* Enable the PTP system time update with the Time Stamp Update register value */ + ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/******************************************************************************* +* Function Name : ETH_InitializePTPTimeStamp +* Desciption : Initialize the PTP Time Stamp +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ETH_InitializePTPTimeStamp(void) +{ + /* Initialize the PTP Time Stamp */ + ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/******************************************************************************* +* Function Name : ETH_PTPUpdateMethodConfig +* Desciption : Selects the PTP Update method +* Input : - UpdateMethod: the PTP Update method +* This parameter can be one of the following values: +* - ETH_PTP_FineUpdate : Fine Update method +* - ETH_PTP_CoarseUpdate : Coarse Update method +* Output : None +* Return : None +*******************************************************************************/ +void ETH_PTPUpdateMethodConfig(u32 UpdateMethod) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); + + if (UpdateMethod != ETH_PTP_CoarseUpdate) + { + /* Enable the PTP Fine Update method */ + ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + /* Disable the PTP Coarse Update method */ + ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSFCU); + } +} + +/******************************************************************************* +* Function Name : ETH_PTPTimeStampCmd +* Desciption : Enables or disables the PTP time stamp for transmit and receive frames. +* Input : - NewState: new state of the PTP time stamp for transmit and receive frames +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + /* Check the parameters */ + eth_assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PTP time stamp for transmit and receive frames */ + ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + /* Disable the PTP time stamp for transmit and receive frames */ + ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSE); + } +} + +/******************************************************************************* +* Function Name : ETH_GetPTPFlagStatus +* Desciption : Checks whether the specified ETHERNET PTP flag is set or not. +* Input : - ETH_PTP_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - ETH_PTP_FLAG_TSARU : Addend Register Update +* - ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable +* - ETH_PTP_FLAG_TSSTU : Time Stamp Update +* - ETH_PTP_FLAG_TSSTI : Time Stamp Initialize +* Output : None +* Return : The new state of ETHERNET PTP Flag (SET or RESET). +*******************************************************************************/ +FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + eth_assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG)); + + if ((ETH_PTP->PTPTSCR & ETH_PTP_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : ETH_SetPTPSubSecondIncrement +* Desciption : Sets the system time Sub-Second Increment value. +* Input : - SubSecondValue: specifies the PTP Sub-Second Increment Register value. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); + + /* Set the PTP Sub-Second Increment Register */ + ETH_PTP->PTPSSIR = SubSecondValue; +} + +/******************************************************************************* +* Function Name : ETH_SetPTPTimeStampUpdate +* Desciption : Sets the Time Stamp update sign and values. +* Input : - Sign: specifies the PTP Time update value sign. +* This parameter can be one of the following values: +* - ETH_PTP_PositiveTime : positive time value. +* - ETH_PTP_NegativeTime : negative time value. +* - SecondValue: specifies the PTP Time update second value. +* - SubSecondValue: specifies the PTP Time update sub-second value. +* this is a 31 bit value. bit32 correspond to the sign. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); + eth_assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); + + /* Set the PTP Time Update High Register */ + ETH_PTP->PTPTSHUR = SecondValue; + + /* Set the PTP Time Update Low Register with sign */ + ETH_PTP->PTPTSLUR = Sign | SubSecondValue; +} + +/******************************************************************************* +* Function Name : ETH_SetPTPTimeStampAddend +* Desciption : Sets the Time Stamp Addend value. +* Input : - Value: specifies the PTP Time Stamp Addend Register value. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_SetPTPTimeStampAddend(u32 Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH_PTP->PTPTSAR = Value; +} + +/******************************************************************************* +* Function Name : ETH_SetPTPTargetTime +* Desciption : Sets the Target Time registers values. +* Input : - HighValue: specifies the PTP Target Time High Register value. +* - LowValue: specifies the PTP Target Time Low Register value. +* Output : None +* Return : None +*******************************************************************************/ +void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue) +{ + /* Set the PTP Target Time High Register */ + ETH_PTP->PTPTTHR = HighValue; + /* Set the PTP Target Time Low Register */ + ETH_PTP->PTPTTLR = LowValue; +} + +/******************************************************************************* +* Function Name : ETH_GetPTPRegister +* Desciption : Get the specified ETHERNET PTP register value. +* Input : - ETH_PTPReg: specifies the ETHERNET PTP register. +* This parameter can be one of the following values: +* - ETH_PTPTSCR : Sub-Second Increment Register +* - ETH_PTPSSIR : Sub-Second Increment Register +* - ETH_PTPTSHR : Time Stamp High Register +* - ETH_PTPTSLR : Time Stamp Low Register +* - ETH_PTPTSHUR : Time Stamp High Update Register +* - ETH_PTPTSLUR : Time Stamp Low Update Register +* - ETH_PTPTSAR : Time Stamp Addend Register +* - ETH_PTPTTHR : Target Time High Register +* - ETH_PTPTTLR : Target Time Low Register +* Output : None +* Return : The value of ETHERNET PTP Register value. +*******************************************************************************/ +u32 ETH_GetPTPRegister(u32 ETH_PTPReg) +{ + /* Check the parameters */ + eth_assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); + + /* Return the selected register value */ + return (*(vu32 *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/******************************************************************************* +* Function Name : ETH_DMAPTPTxDescChainInit +* Desciption : Initializes the DMA Tx descriptors in chain mode with PTP. +* Input : - DMATxDescTab: Pointer on the first Tx desc list +* - DMAPTPTxDescTab: Pointer on the first PTP Tx desc list +* - TxBuff: Pointer on the first TxBuffer list +* - TxBuffCount: Number of the used Tx desc in the list +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount) +{ + u32 i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab+i; + + /* Set Second Address Chained bit and enable PTP */ + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr =(u32)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab; + } + + /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */ + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + + /* Store on the last DMAPTPTxDescTab desc status record the first list address */ + (&DMAPTPTxDescTab[i-1])->Status = (u32) DMAPTPTxDescTab; + + /* Set Transmit Desciptor List Address Register */ + ETH_DMA->DMATDLAR = (u32) DMATxDescTab; +} + +/******************************************************************************* +* Function Name : ETH_DMAPTPRxDescChainInit +* Desciption : Initializes the DMA Rx descriptors in chain mode. +* Input : - DMARxDescTab: Pointer on the first Rx desc list +* - DMAPTPRxDescTab: Pointer on the first PTP Rx desc list +* - RxBuff: Pointer on the first RxBuffer list +* - RxBuffCount: Number of the used Rx desc in the list +* Output : None +* Return : None +*******************************************************************************/ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount) +{ + u32 i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE; + + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (u32)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab); + } + + /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */ + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + + /* Store on the last DMAPTPRxDescTab desc status record the first list address */ + (&DMAPTPRxDescTab[i-1])->Status = (u32) DMAPTPRxDescTab; + + /* Set Receive Desciptor List Address Register */ + ETH_DMA->DMARDLAR = (u32) DMARxDescTab; +} + +/******************************************************************************* +* Function Name : ETH_HandlePTPTxPkt +* Desciption : Transmits a packet, from application buffer, pointed by ppkt with +* Time Stamp values. +* Input : - ppkt: pointer to application packet Buffer. +* - FrameLength: Tx Packet size. +* - PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values. +* Output : None +* Return : ETH_ERROR: in case of Tx desc owned by DMA +* ETH_SUCCESS: for correct transmission +*******************************************************************************/ +u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab) +{ + u32 offset = 0, timeout = 0; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & (u32)0x1FFF); + + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH_DMA->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH_DMA->DMATPDR = 0; + } + + /* Wait for ETH_DMATxDesc_TTSS flag to be set */ + do + { + timeout++; + } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + + /* Update the ENET DMA current descriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); + + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read: this will + be the first Tx descriptor in this case */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMAPTPTxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/******************************************************************************* +* Function Name : ETH_HandlePTPRxPkt +* Desciption : Receives a packet and copies it to memory pointed by ppkt with +* Time Stamp values. +* Input : - PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values. +* Output : ppkt: pointer on application receive buffer. +* Return : ETH_ERROR: if there is error in reception +* Received packet size: if packet reception is correct +*******************************************************************************/ +u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab) +{ + u32 offset = 0, FrameLength = 0; + + /* Check if the descriptor is owned by the ENET or CPU */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (u32)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (u32)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (u32)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + FrameLength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + FrameLength = ETH_ERROR; + } + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH_DMA->DMASR & ETH_DMASR_RBUS) != (u32)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH_DMA->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH_DMA->DMARPDR = 0; + } + + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); + + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return Frame Length/ERROR */ + return (FrameLength); +} + +#endif /* _ETH_PTP */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth_lib.c b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth_lib.c new file mode 100644 index 0000000..c777fea --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth_lib.c @@ -0,0 +1,58 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32fxxx_eth_lib.c +* Author : MCD Application Team +* Version : V2.0.2 +* Date : 07/11/2008 +* Description : This file provides all peripherals pointers initialization. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#define EXT +#include "stm32f10x_lib.h" +/* Includes ------------------------------------------------------------------*/ +#include "stm32fxxx_eth_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +#ifdef ETH_DEBUG +/******************************************************************************* +* Function Name : ethernet_debug +* Description : This function initialize peripherals pointers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void eth_debug(void) +{ +/********************************** ETHERNET **********************************/ +#ifdef _ETH_MAC + ETH_MAC = ((ETH_MAC_TypeDef *) ETH_MAC_BASE); +#endif /*_ETH_MAC */ + +#ifdef _ETH_MMC + ETH_MMC = ((ETH_MMC_TypeDef *) ETH_MMC_BASE); +#endif /*_ETH_MMC */ + +#ifdef _ETH_PTP + ETH_PTP = ((ETH_PTP_TypeDef *) ETH_PTP_BASE); +#endif /*_ETH_PTP */ + +#ifdef _ETH_DMA + ETH_DMA = ((ETH_DMA_TypeDef *) ETH_DMA_BASE); +#endif /*_ETH_DMA */ +} + +#endif /* ETH_DEBUG*/ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/version.txt b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/version.txt new file mode 100644 index 0000000..72d3001 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/drivers/ST/STM32F10xFWLib/version.txt @@ -0,0 +1,22 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : version.txt +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : Version file for STM32F10x Firmware Library. +******************************************************************************** + +* 04/02/2007: V0.2 +=================== + Updated version + +* 02/05/2007 : V0.1 +=================== + Updated version + +* 09/29/2006 : V0.01 +=================== + Created. + +******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****** + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/Legacy-directory-only-see-FreeRTOS-Plus-TCP.url b/SOFTWARE-FreeRTOS/Common/ethernet/Legacy-directory-only-see-FreeRTOS-Plus-TCP.url new file mode 100644 index 0000000..d9919c9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/Legacy-directory-only-see-FreeRTOS-Plus-TCP.url @@ -0,0 +1,6 @@ +[InternetShortcut] +URL=http://www.freertos.org/tcp +IDList= +HotKey=0 +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/FILES b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/FILES new file mode 100644 index 0000000..2b65731 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/FILES @@ -0,0 +1,13 @@ +api/ - The code for the high-level wrapper API. Not needed if + you use the lowel-level call-back/raw API. + +core/ - The core of the TPC/IP stack; protocol implementations, + memory and buffer management, and the low-level raw API. + +include/ - lwIP include files. + +netif/ - Generic network interface device drivers are kept here, + as well as the ARP module. + +For more information on the various subdirectories, check the FILES +file in each directory. diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/api_lib.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/api_lib.c new file mode 100644 index 0000000..917a2ec --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/api_lib.c @@ -0,0 +1,722 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* This is the part of the API that is linked with + the application */ + +#include "lwip/opt.h" +#include "lwip/api.h" +#include "lwip/api_msg.h" +#include "lwip/memp.h" + + +struct +netbuf *netbuf_new(void) +{ + struct netbuf *buf; + + buf = memp_malloc(MEMP_NETBUF); + if (buf != NULL) { + buf->p = NULL; + buf->ptr = NULL; + return buf; + } else { + return NULL; + } +} + +void +netbuf_delete(struct netbuf *buf) +{ + if (buf != NULL) { + if (buf->p != NULL) { + pbuf_free(buf->p); + buf->p = buf->ptr = NULL; + } + memp_free(MEMP_NETBUF, buf); + } +} + +void * +netbuf_alloc(struct netbuf *buf, u16_t size) +{ + /* Deallocate any previously allocated memory. */ + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM); + if (buf->p == NULL) { + return NULL; + } + buf->ptr = buf->p; + return buf->p->payload; +} + +void +netbuf_free(struct netbuf *buf) +{ + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = buf->ptr = NULL; +} + +void +netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size) +{ + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); + buf->p->payload = dataptr; + buf->p->len = buf->p->tot_len = size; + buf->ptr = buf->p; +} + +void +netbuf_chain(struct netbuf *head, struct netbuf *tail) +{ + pbuf_chain(head->p, tail->p); + head->ptr = head->p; + memp_free(MEMP_NETBUF, tail); +} + +u16_t +netbuf_len(struct netbuf *buf) +{ + return buf->p->tot_len; +} + +err_t +netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len) +{ + if (buf->ptr == NULL) { + return ERR_BUF; + } + *dataptr = buf->ptr->payload; + *len = buf->ptr->len; + return ERR_OK; +} + +s8_t +netbuf_next(struct netbuf *buf) +{ + if (buf->ptr->next == NULL) { + return -1; + } + buf->ptr = buf->ptr->next; + if (buf->ptr->next == NULL) { + return 1; + } + return 0; +} + +void +netbuf_first(struct netbuf *buf) +{ + buf->ptr = buf->p; +} + +void +netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset) +{ + struct pbuf *p; + u16_t i, left; + + left = 0; + + if(buf == NULL || dataptr == NULL) { + return; + } + + /* This implementation is bad. It should use bcopy + instead. */ + for(p = buf->p; left < len && p != NULL; p = p->next) { + if (offset != 0 && offset >= p->len) { + offset -= p->len; + } else { + for(i = offset; i < p->len; ++i) { + ((u8_t *)dataptr)[left] = ((u8_t *)p->payload)[i]; + if (++left >= len) { + return; + } + } + offset = 0; + } + } +} + +void +netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len) +{ + netbuf_copy_partial(buf, dataptr, len, 0); +} + +struct ip_addr * +netbuf_fromaddr(struct netbuf *buf) +{ + return buf->fromaddr; +} + +u16_t +netbuf_fromport(struct netbuf *buf) +{ + return buf->fromport; +} + +struct +netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto, + void (*callback)(struct netconn *, enum netconn_evt, u16_t len)) +{ + struct netconn *conn; + struct api_msg *msg; + + conn = memp_malloc(MEMP_NETCONN); + if (conn == NULL) { + return NULL; + } + + conn->err = ERR_OK; + conn->type = t; + conn->pcb.tcp = NULL; + + if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) { + memp_free(MEMP_NETCONN, conn); + return NULL; + } + conn->recvmbox = SYS_MBOX_NULL; + conn->acceptmbox = SYS_MBOX_NULL; + conn->sem = sys_sem_new(0); + if (conn->sem == SYS_SEM_NULL) { + memp_free(MEMP_NETCONN, conn); + return NULL; + } + conn->state = NETCONN_NONE; + conn->socket = 0; + conn->callback = callback; + conn->recv_avail = 0; + + if((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + memp_free(MEMP_NETCONN, conn); + return NULL; + } + + msg->type = API_MSG_NEWCONN; + msg->msg.msg.bc.port = proto; /* misusing the port field */ + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + + if ( conn->err != ERR_OK ) { + memp_free(MEMP_NETCONN, conn); + return NULL; + } + + return conn; +} + + +struct +netconn *netconn_new(enum netconn_type t) +{ + return netconn_new_with_proto_and_callback(t,0,NULL); +} + +struct +netconn *netconn_new_with_callback(enum netconn_type t, + void (*callback)(struct netconn *, enum netconn_evt, u16_t len)) +{ + return netconn_new_with_proto_and_callback(t,0,callback); +} + + +err_t +netconn_delete(struct netconn *conn) +{ + struct api_msg *msg; + void *mem; + + if (conn == NULL) { + return ERR_OK; + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return ERR_MEM; + } + + msg->type = API_MSG_DELCONN; + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + + /* Drain the recvmbox. */ + if (conn->recvmbox != SYS_MBOX_NULL) { + while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) { + if (conn->type == NETCONN_TCP) { + if(mem != NULL) + pbuf_free((struct pbuf *)mem); + } else { + netbuf_delete((struct netbuf *)mem); + } + } + sys_mbox_free(conn->recvmbox); + conn->recvmbox = SYS_MBOX_NULL; + } + + + /* Drain the acceptmbox. */ + if (conn->acceptmbox != SYS_MBOX_NULL) { + while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) { + netconn_delete((struct netconn *)mem); + } + + sys_mbox_free(conn->acceptmbox); + conn->acceptmbox = SYS_MBOX_NULL; + } + + sys_mbox_free(conn->mbox); + conn->mbox = SYS_MBOX_NULL; + if (conn->sem != SYS_SEM_NULL) { + sys_sem_free(conn->sem); + } + /* conn->sem = SYS_SEM_NULL;*/ + memp_free(MEMP_NETCONN, conn); + return ERR_OK; +} + +enum netconn_type +netconn_type(struct netconn *conn) +{ + return conn->type; +} + +err_t +netconn_peer(struct netconn *conn, struct ip_addr *addr, + u16_t *port) +{ + switch (conn->type) { + case NETCONN_RAW: + /* return an error as connecting is only a helper for upper layers */ + return ERR_CONN; + case NETCONN_UDPLITE: + case NETCONN_UDPNOCHKSUM: + case NETCONN_UDP: + if (conn->pcb.udp == NULL || + ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0)) + return ERR_CONN; + *addr = (conn->pcb.udp->remote_ip); + *port = conn->pcb.udp->remote_port; + break; + case NETCONN_TCP: + if (conn->pcb.tcp == NULL) + return ERR_CONN; + *addr = (conn->pcb.tcp->remote_ip); + *port = conn->pcb.tcp->remote_port; + break; + } + return (conn->err = ERR_OK); +} + +err_t +netconn_addr(struct netconn *conn, struct ip_addr **addr, + u16_t *port) +{ + switch (conn->type) { + case NETCONN_RAW: + *addr = &(conn->pcb.raw->local_ip); + *port = conn->pcb.raw->protocol; + break; + case NETCONN_UDPLITE: + case NETCONN_UDPNOCHKSUM: + case NETCONN_UDP: + *addr = &(conn->pcb.udp->local_ip); + *port = conn->pcb.udp->local_port; + break; + case NETCONN_TCP: + *addr = &(conn->pcb.tcp->local_ip); + *port = conn->pcb.tcp->local_port; + break; + } + return (conn->err = ERR_OK); +} + +err_t +netconn_bind(struct netconn *conn, struct ip_addr *addr, + u16_t port) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + if (conn->type != NETCONN_TCP && + conn->recvmbox == SYS_MBOX_NULL) { + if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) { + return ERR_MEM; + } + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + msg->type = API_MSG_BIND; + msg->msg.conn = conn; + msg->msg.msg.bc.ipaddr = addr; + msg->msg.msg.bc.port = port; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + + +err_t +netconn_connect(struct netconn *conn, struct ip_addr *addr, + u16_t port) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + + if (conn->recvmbox == SYS_MBOX_NULL) { + if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) { + return ERR_MEM; + } + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return ERR_MEM; + } + msg->type = API_MSG_CONNECT; + msg->msg.conn = conn; + msg->msg.msg.bc.ipaddr = addr; + msg->msg.msg.bc.port = port; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + +err_t +netconn_disconnect(struct netconn *conn) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return ERR_MEM; + } + msg->type = API_MSG_DISCONNECT; + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; + +} + +err_t +netconn_listen(struct netconn *conn) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + if (conn->acceptmbox == SYS_MBOX_NULL) { + conn->acceptmbox = sys_mbox_new(); + if (conn->acceptmbox == SYS_MBOX_NULL) { + return ERR_MEM; + } + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + msg->type = API_MSG_LISTEN; + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + +struct netconn * +netconn_accept(struct netconn *conn) +{ + struct netconn *newconn; + + if (conn == NULL) { + return NULL; + } + + sys_mbox_fetch(conn->acceptmbox, (void *)&newconn); + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0); + + return newconn; +} + +struct netbuf * +netconn_recv(struct netconn *conn) +{ + struct api_msg *msg; + struct netbuf *buf; + struct pbuf *p; + u16_t len; + + if (conn == NULL) { + return NULL; + } + + if (conn->recvmbox == SYS_MBOX_NULL) { + conn->err = ERR_CONN; + return NULL; + } + + if (conn->err != ERR_OK) { + return NULL; + } + + if (conn->type == NETCONN_TCP) { + if (conn->pcb.tcp->state == LISTEN) { + conn->err = ERR_CONN; + return NULL; + } + + + buf = memp_malloc(MEMP_NETBUF); + + if (buf == NULL) { + conn->err = ERR_MEM; + return NULL; + } + + sys_mbox_fetch(conn->recvmbox, (void *)&p); + + if (p != NULL) + { + len = p->tot_len; + conn->recv_avail -= len; + } + else + len = 0; + + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len); + + /* If we are closed, we indicate that we no longer wish to receive + data by setting conn->recvmbox to SYS_MBOX_NULL. */ + if (p == NULL) { + memp_free(MEMP_NETBUF, buf); + sys_mbox_free(conn->recvmbox); + conn->recvmbox = SYS_MBOX_NULL; + return NULL; + } + + buf->p = p; + buf->ptr = p; + buf->fromport = 0; + buf->fromaddr = NULL; + + /* Let the stack know that we have taken the data. */ + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + conn->err = ERR_MEM; + return buf; + } + msg->type = API_MSG_RECV; + msg->msg.conn = conn; + if (buf != NULL) { + msg->msg.msg.len = buf->p->tot_len; + } else { + msg->msg.msg.len = 1; + } + api_msg_post(msg); + + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + } else { + sys_mbox_fetch(conn->recvmbox, (void *)&buf); + conn->recv_avail -= buf->p->tot_len; + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len); + } + + + + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err)); + + + return buf; +} + +err_t +netconn_send(struct netconn *conn, struct netbuf *buf) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + if (conn->err != ERR_OK) { + return conn->err; + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len)); + msg->type = API_MSG_SEND; + msg->msg.conn = conn; + msg->msg.msg.p = buf->p; + api_msg_post(msg); + + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + +err_t +netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy) +{ + struct api_msg *msg; + u16_t len; + + if (conn == NULL) { + return ERR_VAL; + } + + if (conn->err != ERR_OK) { + return conn->err; + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + msg->type = API_MSG_WRITE; + msg->msg.conn = conn; + + + conn->state = NETCONN_WRITE; + while (conn->err == ERR_OK && size > 0) { + msg->msg.msg.w.dataptr = dataptr; + msg->msg.msg.w.copy = copy; + + if (conn->type == NETCONN_TCP) { + if (tcp_sndbuf(conn->pcb.tcp) == 0) { + sys_sem_wait(conn->sem); + if (conn->err != ERR_OK) { + goto ret; + } + } + if (size > tcp_sndbuf(conn->pcb.tcp)) { + /* We cannot send more than one send buffer's worth of data at a + time. */ + len = tcp_sndbuf(conn->pcb.tcp); + } else { + len = size; + } + } else { + len = size; + } + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy)); + msg->msg.msg.w.len = len; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + if (conn->err == ERR_OK) { + dataptr = (void *)((u8_t *)dataptr + len); + size -= len; + } else if (conn->err == ERR_MEM) { + conn->err = ERR_OK; + sys_sem_wait(conn->sem); + } else { + goto ret; + } + } + ret: + memp_free(MEMP_API_MSG, msg); + conn->state = NETCONN_NONE; + + return conn->err; +} + +err_t +netconn_close(struct netconn *conn) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + + conn->state = NETCONN_CLOSE; + again: + msg->type = API_MSG_CLOSE; + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + if (conn->err == ERR_MEM && + conn->sem != SYS_SEM_NULL) { + sys_sem_wait(conn->sem); + goto again; + } + conn->state = NETCONN_NONE; + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + +err_t +netconn_err(struct netconn *conn) +{ + return conn->err; +} + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/api_msg.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/api_msg.c new file mode 100644 index 0000000..36a7fc1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/api_msg.c @@ -0,0 +1,807 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" +#include "lwip/arch.h" +#include "lwip/api_msg.h" +#include "lwip/memp.h" +#include "lwip/sys.h" +#include "lwip/tcpip.h" + +#if LWIP_RAW +static u8_t +recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, + struct ip_addr *addr) +{ + struct netbuf *buf; + struct netconn *conn; + + conn = arg; + if (!conn) return 0; + + if (conn->recvmbox != SYS_MBOX_NULL) { + if (!(buf = memp_malloc(MEMP_NETBUF))) { + return 0; + } + pbuf_ref(p); + buf->p = p; + buf->ptr = p; + buf->fromaddr = addr; + buf->fromport = pcb->protocol; + + conn->recv_avail += p->tot_len; + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len); + sys_mbox_post(conn->recvmbox, buf); + } + + return 0; /* do not eat the packet */ +} +#endif +#if LWIP_UDP +static void +recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *addr, u16_t port) +{ + struct netbuf *buf; + struct netconn *conn; + + conn = arg; + + if (conn == NULL) { + pbuf_free(p); + return; + } + if (conn->recvmbox != SYS_MBOX_NULL) { + buf = memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(p); + return; + } else { + buf->p = p; + buf->ptr = p; + buf->fromaddr = addr; + buf->fromport = port; + } + + conn->recv_avail += p->tot_len; + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len); + sys_mbox_post(conn->recvmbox, buf); + } +} +#endif /* LWIP_UDP */ +#if LWIP_TCP + +static err_t +recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + struct netconn *conn; + u16_t len; + + conn = arg; + + if (conn == NULL) { + pbuf_free(p); + return ERR_VAL; + } + + if (conn->recvmbox != SYS_MBOX_NULL) { + + conn->err = err; + if (p != NULL) { + len = p->tot_len; + conn->recv_avail += len; + } + else + len = 0; + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len); + sys_mbox_post(conn->recvmbox, p); + } + return ERR_OK; +} + + +static err_t +poll_tcp(void *arg, struct tcp_pcb *pcb) +{ + struct netconn *conn; + + conn = arg; + if (conn != NULL && + (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) && + conn->sem != SYS_SEM_NULL) { + sys_sem_signal(conn->sem); + } + return ERR_OK; +} + +static err_t +sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) +{ + struct netconn *conn; + + conn = arg; + if (conn != NULL && conn->sem != SYS_SEM_NULL) { + sys_sem_signal(conn->sem); + } + + if (conn && conn->callback) + if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) + (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len); + + return ERR_OK; +} + +static void +err_tcp(void *arg, err_t err) +{ + struct netconn *conn; + + conn = arg; + + conn->pcb.tcp = NULL; + + + conn->err = err; + if (conn->recvmbox != SYS_MBOX_NULL) { + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); + sys_mbox_post(conn->recvmbox, NULL); + } + if (conn->mbox != SYS_MBOX_NULL) { + sys_mbox_post(conn->mbox, NULL); + } + if (conn->acceptmbox != SYS_MBOX_NULL) { + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); + sys_mbox_post(conn->acceptmbox, NULL); + } + if (conn->sem != SYS_SEM_NULL) { + sys_sem_signal(conn->sem); + } +} + +static void +setup_tcp(struct netconn *conn) +{ + struct tcp_pcb *pcb; + + pcb = conn->pcb.tcp; + tcp_arg(pcb, conn); + tcp_recv(pcb, recv_tcp); + tcp_sent(pcb, sent_tcp); + tcp_poll(pcb, poll_tcp, 4); + tcp_err(pcb, err_tcp); +} + +static err_t +accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) +{ + sys_mbox_t mbox; + struct netconn *newconn; + struct netconn *conn; + +#if API_MSG_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(newpcb->state); +#endif /* TCP_DEBUG */ +#endif /* API_MSG_DEBUG */ + conn = (struct netconn *)arg; + mbox = conn->acceptmbox; + newconn = memp_malloc(MEMP_NETCONN); + if (newconn == NULL) { + return ERR_MEM; + } + newconn->recvmbox = sys_mbox_new(); + if (newconn->recvmbox == SYS_MBOX_NULL) { + memp_free(MEMP_NETCONN, newconn); + return ERR_MEM; + } + newconn->mbox = sys_mbox_new(); + if (newconn->mbox == SYS_MBOX_NULL) { + sys_mbox_free(newconn->recvmbox); + memp_free(MEMP_NETCONN, newconn); + return ERR_MEM; + } + newconn->sem = sys_sem_new(0); + if (newconn->sem == SYS_SEM_NULL) { + sys_mbox_free(newconn->recvmbox); + sys_mbox_free(newconn->mbox); + memp_free(MEMP_NETCONN, newconn); + return ERR_MEM; + } + /* Allocations were OK, setup the PCB etc */ + newconn->type = NETCONN_TCP; + newconn->pcb.tcp = newpcb; + setup_tcp(newconn); + newconn->acceptmbox = SYS_MBOX_NULL; + newconn->err = err; + /* Register event with callback */ + if (conn->callback) + { + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); + } + /* We have to set the callback here even though + * the new socket is unknown. Mark the socket as -1. */ + newconn->callback = conn->callback; + newconn->socket = -1; + newconn->recv_avail = 0; + + sys_mbox_post(mbox, newconn); + return ERR_OK; +} +#endif /* LWIP_TCP */ + +static void +do_newconn(struct api_msg_msg *msg) +{ + if(msg->conn->pcb.tcp != NULL) { + /* This "new" connection already has a PCB allocated. */ + /* Is this an error condition? Should it be deleted? + We currently just are happy and return. */ + sys_mbox_post(msg->conn->mbox, NULL); + return; + } + + msg->conn->err = ERR_OK; + + /* Allocate a PCB for this connection */ + switch(msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */ + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + msg->conn->pcb.udp = udp_new(); + if(msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + break; + } + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDPNOCHKSUM: + msg->conn->pcb.udp = udp_new(); + if(msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + break; + } + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new(); + if(msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + break; + } + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new(); + if(msg->conn->pcb.tcp == NULL) { + msg->conn->err = ERR_MEM; + break; + } + setup_tcp(msg->conn); + break; +#endif + } + + + sys_mbox_post(msg->conn->mbox, NULL); +} + + +static void +do_delconn(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + raw_remove(msg->conn->pcb.raw); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + msg->conn->pcb.udp->recv_arg = NULL; + udp_remove(msg->conn->pcb.udp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + if (msg->conn->pcb.tcp->state == LISTEN) { + tcp_arg(msg->conn->pcb.tcp, NULL); + tcp_accept(msg->conn->pcb.tcp, NULL); + tcp_close(msg->conn->pcb.tcp); + } else { + tcp_arg(msg->conn->pcb.tcp, NULL); + tcp_sent(msg->conn->pcb.tcp, NULL); + tcp_recv(msg->conn->pcb.tcp, NULL); + tcp_poll(msg->conn->pcb.tcp, NULL, 0); + tcp_err(msg->conn->pcb.tcp, NULL); + if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) { + tcp_abort(msg->conn->pcb.tcp); + } + } +#endif + default: + break; + } + } + /* Trigger select() in socket layer */ + if (msg->conn->callback) + { + (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0); + (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0); + } + + if (msg->conn->mbox != SYS_MBOX_NULL) { + sys_mbox_post(msg->conn->mbox, NULL); + } +} + +static void +do_bind(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp == NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */ + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + msg->conn->pcb.udp = udp_new(); + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDPNOCHKSUM: + msg->conn->pcb.udp = udp_new(); + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new(); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new(); + setup_tcp(msg->conn); +#endif /* LWIP_TCP */ + default: + break; + } + } + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->err = tcp_bind(msg->conn->pcb.tcp, + msg->msg.bc.ipaddr, msg->msg.bc.port); +#endif /* LWIP_TCP */ + default: + break; + } + sys_mbox_post(msg->conn->mbox, NULL); +} +#if LWIP_TCP + +static err_t +do_connected(void *arg, struct tcp_pcb *pcb, err_t err) +{ + struct netconn *conn; + + conn = arg; + + if (conn == NULL) { + return ERR_VAL; + } + + conn->err = err; + if (conn->type == NETCONN_TCP && err == ERR_OK) { + setup_tcp(conn); + } + sys_mbox_post(conn->mbox, NULL); + return ERR_OK; +} +#endif + +static void +do_connect(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp == NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */ + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + msg->conn->pcb.udp = udp_new(); + if (msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + sys_mbox_post(msg->conn->mbox, NULL); + return; + } + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDPNOCHKSUM: + msg->conn->pcb.udp = udp_new(); + if (msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + sys_mbox_post(msg->conn->mbox, NULL); + return; + } + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new(); + if (msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + sys_mbox_post(msg->conn->mbox, NULL); + return; + } + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new(); + if (msg->conn->pcb.tcp == NULL) { + msg->conn->err = ERR_MEM; + sys_mbox_post(msg->conn->mbox, NULL); + return; + } +#endif + default: + break; + } + } + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr); + sys_mbox_post(msg->conn->mbox, NULL); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); + sys_mbox_post(msg->conn->mbox, NULL); + break; +#endif +#if LWIP_TCP + case NETCONN_TCP: + /* tcp_arg(msg->conn->pcb.tcp, msg->conn);*/ + setup_tcp(msg->conn); + tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port, + do_connected); + /*tcp_output(msg->conn->pcb.tcp);*/ +#endif + + default: + break; + } +} + +static void +do_disconnect(struct api_msg_msg *msg) +{ + + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + /* Do nothing as connecting is only a helper for upper lwip layers */ + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + udp_disconnect(msg->conn->pcb.udp); + break; +#endif + case NETCONN_TCP: + break; + } + sys_mbox_post(msg->conn->mbox, NULL); +} + + +static void +do_listen(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n")); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n")); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp); + if (msg->conn->pcb.tcp == NULL) { + msg->conn->err = ERR_MEM; + } else { + if (msg->conn->acceptmbox == SYS_MBOX_NULL) { + msg->conn->acceptmbox = sys_mbox_new(); + if (msg->conn->acceptmbox == SYS_MBOX_NULL) { + msg->conn->err = ERR_MEM; + break; + } + } + tcp_arg(msg->conn->pcb.tcp, msg->conn); + tcp_accept(msg->conn->pcb.tcp, accept_function); + } +#endif + default: + break; + } + } + sys_mbox_post(msg->conn->mbox, NULL); +} + +static void +do_accept(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n")); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n")); + break; +#endif /* LWIP_UDP */ + case NETCONN_TCP: + break; + } + } +} + +static void +do_send(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + raw_send(msg->conn->pcb.raw, msg->msg.p); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + udp_send(msg->conn->pcb.udp, msg->msg.p); + break; +#endif /* LWIP_UDP */ + case NETCONN_TCP: + break; + } + } + sys_mbox_post(msg->conn->mbox, NULL); +} + +static void +do_recv(struct api_msg_msg *msg) +{ +#if LWIP_TCP + if (msg->conn->pcb.tcp != NULL) { + if (msg->conn->type == NETCONN_TCP) { + tcp_recved(msg->conn->pcb.tcp, msg->msg.len); + } + } +#endif + sys_mbox_post(msg->conn->mbox, NULL); +} + +static void +do_write(struct api_msg_msg *msg) +{ +#if LWIP_TCP + err_t err; +#endif + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->err = ERR_VAL; + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + msg->conn->err = ERR_VAL; + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr, + msg->msg.w.len, msg->msg.w.copy); + /* This is the Nagle algorithm: inhibit the sending of new TCP + segments when new outgoing data arrives from the user if any + previously transmitted data on the connection remains + unacknowledged. */ + if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || + (msg->conn->pcb.tcp->flags & TF_NODELAY) || + (msg->conn->pcb.tcp->snd_queuelen) > 1)) { + tcp_output(msg->conn->pcb.tcp); + } + msg->conn->err = err; + if (msg->conn->callback) + if (err == ERR_OK) + { + if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT) + (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len); + } +#endif + default: + break; + } + } + sys_mbox_post(msg->conn->mbox, NULL); +} + +static void +do_close(struct api_msg_msg *msg) +{ + err_t err; + + err = ERR_OK; + + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + if (msg->conn->pcb.tcp->state == LISTEN) { + err = tcp_close(msg->conn->pcb.tcp); + } + else if (msg->conn->pcb.tcp->state == CLOSE_WAIT) { + err = tcp_output(msg->conn->pcb.tcp); + } + msg->conn->err = err; +#endif + default: + break; + } + } + sys_mbox_post(msg->conn->mbox, NULL); +} + +typedef void (* api_msg_decode)(struct api_msg_msg *msg); +static api_msg_decode decode[API_MSG_MAX] = { + do_newconn, + do_delconn, + do_bind, + do_connect, + do_disconnect, + do_listen, + do_accept, + do_send, + do_recv, + do_write, + do_close + }; +void +api_msg_input(struct api_msg *msg) +{ + decode[msg->type](&(msg->msg)); +} + +void +api_msg_post(struct api_msg *msg) +{ + tcpip_apimsg(msg); +} + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/err.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/err.c new file mode 100644 index 0000000..cc63678 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/err.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/err.h" + +#ifdef LWIP_DEBUG + +static char *err_strerr[] = {"Ok.", + "Out of memory error.", + "Buffer error.", + "Connection aborted.", + "Connection reset.", + "Connection closed.", + "Not connected.", + "Illegal value.", + "Illegal argument.", + "Routing problem.", + "Address in use." +}; + + +char * +lwip_strerr(err_t err) +{ + return err_strerr[-err]; + +} + + +#endif /* LWIP_DEBUG */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/sockets.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/sockets.c new file mode 100644 index 0000000..26e6d86 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/sockets.c @@ -0,0 +1,1362 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * Improved by Marc Boucher and David Haas + * + */ + +#include +#include + +#include "lwip/opt.h" +#include "lwip/api.h" +#include "lwip/arch.h" +#include "lwip/sys.h" + +#include "lwip/sockets.h" + +#define NUM_SOCKETS MEMP_NUM_NETCONN + +struct lwip_socket { + struct netconn *conn; + struct netbuf *lastdata; + u16_t lastoffset; + u16_t rcvevent; + u16_t sendevent; + u16_t flags; + int err; +}; + +struct lwip_select_cb +{ + struct lwip_select_cb *next; + fd_set *readset; + fd_set *writeset; + fd_set *exceptset; + int sem_signalled; + sys_sem_t sem; +}; + +static struct lwip_socket sockets[NUM_SOCKETS]; +static struct lwip_select_cb *select_cb_list = 0; + +static sys_sem_t socksem = 0; +static sys_sem_t selectsem = 0; + +static void +event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); + +static int err_to_errno_table[11] = { + 0, /* ERR_OK 0 No error, everything OK. */ + ENOMEM, /* ERR_MEM -1 Out of memory error. */ + ENOBUFS, /* ERR_BUF -2 Buffer error. */ + ECONNABORTED, /* ERR_ABRT -3 Connection aborted. */ + ECONNRESET, /* ERR_RST -4 Connection reset. */ + ESHUTDOWN, /* ERR_CLSD -5 Connection closed. */ + ENOTCONN, /* ERR_CONN -6 Not connected. */ + EINVAL, /* ERR_VAL -7 Illegal value. */ + EIO, /* ERR_ARG -8 Illegal argument. */ + EHOSTUNREACH, /* ERR_RTE -9 Routing problem. */ + EADDRINUSE /* ERR_USE -10 Address in use. */ +}; + +#define ERR_TO_ERRNO_TABLE_SIZE \ + (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0])) + +#define err_to_errno(err) \ + (-(err) >= 0 && -(err) < ERR_TO_ERRNO_TABLE_SIZE ? \ + err_to_errno_table[-(err)] : EIO) + +#ifdef ERRNO +#define set_errno(err) errno = (err) +#else +#define set_errno(err) +#endif + +#define sock_set_errno(sk, e) do { \ + sk->err = (e); \ + set_errno(sk->err); \ +} while (0) + + +static struct lwip_socket * +get_socket(int s) +{ + struct lwip_socket *sock; + + if ((s < 0) || (s > NUM_SOCKETS)) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s)); + set_errno(EBADF); + return NULL; + } + + sock = &sockets[s]; + + if (!sock->conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s)); + set_errno(EBADF); + return NULL; + } + + return sock; +} + +static int +alloc_socket(struct netconn *newconn) +{ + int i; + + if (!socksem) + socksem = sys_sem_new(1); + + /* Protect socket array */ + sys_sem_wait(socksem); + + /* allocate a new socket identifier */ + for(i = 0; i < NUM_SOCKETS; ++i) { + if (!sockets[i].conn) { + sockets[i].conn = newconn; + sockets[i].lastdata = NULL; + sockets[i].lastoffset = 0; + sockets[i].rcvevent = 0; + sockets[i].sendevent = 1; /* TCP send buf is empty */ + sockets[i].flags = 0; + sockets[i].err = 0; + sys_sem_signal(socksem); + return i; + } + } + sys_sem_signal(socksem); + return -1; +} + +int +lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) +{ + struct lwip_socket *sock; + struct netconn *newconn; + struct ip_addr naddr; + u16_t port; + int newsock; + struct sockaddr_in sin; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + newconn = netconn_accept(sock->conn); + + /* get the IP address and port of the remote host */ + netconn_peer(newconn, &naddr, &port); + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + sin.sin_port = htons(port); + sin.sin_addr.s_addr = naddr.addr; + + if (*addrlen > sizeof(sin)) + *addrlen = sizeof(sin); + + memcpy(addr, &sin, *addrlen); + + newsock = alloc_socket(newconn); + if (newsock == -1) { + netconn_delete(newconn); + sock_set_errno(sock, ENOBUFS); + return -1; + } + newconn->callback = event_callback; + sock = get_socket(newsock); + + sys_sem_wait(socksem); + sock->rcvevent += -1 - newconn->socket; + newconn->socket = newsock; + sys_sem_signal(socksem); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); + ip_addr_debug_print(SOCKETS_DEBUG, &naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port)); + + sock_set_errno(sock, 0); + return newsock; +} + +int +lwip_bind(int s, struct sockaddr *name, socklen_t namelen) +{ + struct lwip_socket *sock; + struct ip_addr local_addr; + u16_t local_port; + err_t err; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr; + local_port = ((struct sockaddr_in *)name)->sin_port; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, &local_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port))); + + err = netconn_bind(sock->conn, &local_addr, ntohs(local_port)); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_close(int s) +{ + struct lwip_socket *sock; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); + if (!socksem) + socksem = sys_sem_new(1); + + /* We cannot allow multiple closes of the same socket. */ + sys_sem_wait(socksem); + + sock = get_socket(s); + if (!sock) { + sys_sem_signal(socksem); + set_errno(EBADF); + return -1; + } + + netconn_delete(sock->conn); + if (sock->lastdata) { + netbuf_delete(sock->lastdata); + } + sock->lastdata = NULL; + sock->lastoffset = 0; + sock->conn = NULL; + sys_sem_signal(socksem); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_connect(int s, struct sockaddr *name, socklen_t namelen) +{ + struct lwip_socket *sock; + err_t err; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); + err = netconn_disconnect(sock->conn); + } else { + struct ip_addr remote_addr; + u16_t remote_port; + + remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr; + remote_port = ((struct sockaddr_in *)name)->sin_port; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port))); + + err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); + } + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_listen(int s, int backlog) +{ + struct lwip_socket *sock; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + err = netconn_listen(sock->conn); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_recvfrom(int s, void *mem, int len, unsigned int flags, + struct sockaddr *from, socklen_t *fromlen) +{ + struct lwip_socket *sock; + struct netbuf *buf; + u16_t buflen, copylen; + struct ip_addr *addr; + u16_t port; + + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags)); + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + /* Check if there is data left from the last recv operation. */ + if (sock->lastdata) { + buf = sock->lastdata; + } else { + /* If this is non-blocking call, then check first */ + if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK)) + && !sock->rcvevent) + { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s)); + sock_set_errno(sock, EWOULDBLOCK); + return -1; + } + + /* No data was left from the previous operation, so we try to get + some from the network. */ + buf = netconn_recv(sock->conn); + + if (!buf) { + /* We should really do some error checking here. */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s)); + sock_set_errno(sock, 0); + return 0; + } + } + + buflen = netbuf_len(buf); + + buflen -= sock->lastoffset; + + if (len > buflen) { + copylen = buflen; + } else { + copylen = len; + } + + /* copy the contents of the received buffer into + the supplied memory pointer mem */ + netbuf_copy_partial(buf, mem, copylen, sock->lastoffset); + + /* Check to see from where the data was. */ + if (from && fromlen) { + struct sockaddr_in sin; + + addr = netbuf_fromaddr(buf); + port = netbuf_fromport(buf); + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + sin.sin_port = htons(port); + sin.sin_addr.s_addr = addr->addr; + + if (*fromlen > sizeof(sin)) + *fromlen = sizeof(sin); + + memcpy(from, &sin, *fromlen); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen)); + } else { +#if SOCKETS_DEBUG + addr = netbuf_fromaddr(buf); + port = netbuf_fromport(buf); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen)); +#endif + + } + + /* If this is a TCP socket, check if there is data left in the + buffer. If so, it should be saved in the sock structure for next + time around. */ + if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) { + sock->lastdata = buf; + sock->lastoffset += copylen; + } else { + sock->lastdata = NULL; + sock->lastoffset = 0; + netbuf_delete(buf); + } + + + sock_set_errno(sock, 0); + return copylen; +} + +int +lwip_read(int s, void *mem, int len) +{ + return lwip_recvfrom(s, mem, len, 0, NULL, NULL); +} + +int +lwip_recv(int s, void *mem, int len, unsigned int flags) +{ + return lwip_recvfrom(s, mem, len, flags, NULL, NULL); +} + +int +lwip_send(int s, void *data, int size, unsigned int flags) +{ + struct lwip_socket *sock; + struct netbuf *buf; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags)); + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + switch (netconn_type(sock->conn)) { + case NETCONN_RAW: + case NETCONN_UDP: + case NETCONN_UDPLITE: + case NETCONN_UDPNOCHKSUM: + /* create a buffer */ + buf = netbuf_new(); + + if (!buf) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s)); + sock_set_errno(sock, ENOBUFS); + return -1; + } + + /* make the buffer point to the data that should + be sent */ + netbuf_ref(buf, data, size); + + /* send the data */ + err = netconn_send(sock->conn, buf); + + /* deallocated the buffer */ + netbuf_delete(buf); + break; + case NETCONN_TCP: + err = netconn_write(sock->conn, data, size, NETCONN_COPY); + break; + default: + err = ERR_ARG; + break; + } + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size)); + sock_set_errno(sock, 0); + return size; +} + +int +lwip_sendto(int s, void *data, int size, unsigned int flags, + struct sockaddr *to, socklen_t tolen) +{ + struct lwip_socket *sock; + struct ip_addr remote_addr, addr; + u16_t remote_port, port; + int ret,connected; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + /* get the peer if currently connected */ + connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK); + + remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr; + remote_port = ((struct sockaddr_in *)to)->sin_port; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags)); + ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port))); + + netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); + + ret = lwip_send(s, data, size, flags); + + /* reset the remote address and port number + of the connection */ + if (connected) + netconn_connect(sock->conn, &addr, port); + else + netconn_disconnect(sock->conn); + return ret; +} + +int +lwip_socket(int domain, int type, int protocol) +{ + struct netconn *conn; + int i; + + /* create a netconn */ + switch (type) { + case SOCK_RAW: + conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_DGRAM: + conn = netconn_new_with_callback(NETCONN_UDP, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_STREAM: + conn = netconn_new_with_callback(NETCONN_TCP, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol)); + set_errno(EINVAL); + return -1; + } + + if (!conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); + set_errno(ENOBUFS); + return -1; + } + + i = alloc_socket(conn); + + if (i == -1) { + netconn_delete(conn); + set_errno(ENOBUFS); + return -1; + } + conn->socket = i; + LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); + set_errno(0); + return i; +} + +int +lwip_write(int s, void *data, int size) +{ + return lwip_send(s, data, size, 0); +} + + +static int +lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset) +{ + int i, nready = 0; + fd_set lreadset, lwriteset, lexceptset; + struct lwip_socket *p_sock; + + FD_ZERO(&lreadset); + FD_ZERO(&lwriteset); + FD_ZERO(&lexceptset); + + /* Go through each socket in each list to count number of sockets which + currently match */ + for(i = 0; i < maxfdp1; i++) + { + if (FD_ISSET(i, readset)) + { + /* See if netconn of this socket is ready for read */ + p_sock = get_socket(i); + if (p_sock && (p_sock->lastdata || p_sock->rcvevent)) + { + FD_SET(i, &lreadset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); + nready++; + } + } + if (FD_ISSET(i, writeset)) + { + /* See if netconn of this socket is ready for write */ + p_sock = get_socket(i); + if (p_sock && p_sock->sendevent) + { + FD_SET(i, &lwriteset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); + nready++; + } + } + } + *readset = lreadset; + *writeset = lwriteset; + FD_ZERO(exceptset); + + return nready; +} + + + +int +lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout) +{ + int i; + int nready; + fd_set lreadset, lwriteset, lexceptset; + u32_t msectimeout; + struct lwip_select_cb select_cb; + struct lwip_select_cb *p_selcb; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L)); + + select_cb.next = 0; + select_cb.readset = readset; + select_cb.writeset = writeset; + select_cb.exceptset = exceptset; + select_cb.sem_signalled = 0; + + /* Protect ourselves searching through the list */ + if (!selectsem) + selectsem = sys_sem_new(1); + sys_sem_wait(selectsem); + + if (readset) + lreadset = *readset; + else + FD_ZERO(&lreadset); + if (writeset) + lwriteset = *writeset; + else + FD_ZERO(&lwriteset); + if (exceptset) + lexceptset = *exceptset; + else + FD_ZERO(&lexceptset); + + /* Go through each socket in each list to count number of sockets which + currently match */ + nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); + + /* If we don't have any current events, then suspend if we are supposed to */ + if (!nready) + { + if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) + { + sys_sem_signal(selectsem); + if (readset) + FD_ZERO(readset); + if (writeset) + FD_ZERO(writeset); + if (exceptset) + FD_ZERO(exceptset); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); + set_errno(0); + + return 0; + } + + /* add our semaphore to list */ + /* We don't actually need any dynamic memory. Our entry on the + * list is only valid while we are in this function, so it's ok + * to use local variables */ + + select_cb.sem = sys_sem_new(0); + /* Note that we are still protected */ + /* Put this select_cb on top of list */ + select_cb.next = select_cb_list; + select_cb_list = &select_cb; + + /* Now we can safely unprotect */ + sys_sem_signal(selectsem); + + /* Now just wait to be woken */ + if (timeout == 0) + /* Wait forever */ + msectimeout = 0; + else + msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000)); + + i = sys_sem_wait_timeout(select_cb.sem, msectimeout); + + /* Take us off the list */ + sys_sem_wait(selectsem); + if (select_cb_list == &select_cb) + select_cb_list = select_cb.next; + else + for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next) + if (p_selcb->next == &select_cb) + { + p_selcb->next = select_cb.next; + break; + } + + sys_sem_signal(selectsem); + + sys_sem_free(select_cb.sem); + if (i == 0) /* Timeout */ + { + if (readset) + FD_ZERO(readset); + if (writeset) + FD_ZERO(writeset); + if (exceptset) + FD_ZERO(exceptset); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); + set_errno(0); + + return 0; + } + + if (readset) + lreadset = *readset; + else + FD_ZERO(&lreadset); + if (writeset) + lwriteset = *writeset; + else + FD_ZERO(&lwriteset); + if (exceptset) + lexceptset = *exceptset; + else + FD_ZERO(&lexceptset); + + /* See what's set */ + nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); + } + else + sys_sem_signal(selectsem); + + if (readset) + *readset = lreadset; + if (writeset) + *writeset = lwriteset; + if (exceptset) + *exceptset = lexceptset; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); + set_errno(0); + + return nready; +} + + +static void +event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) +{ + int s; + struct lwip_socket *sock; + struct lwip_select_cb *scb; + + /* Get socket */ + if (conn) + { + s = conn->socket; + if (s < 0) + { + /* Data comes in right away after an accept, even though + * the server task might not have created a new socket yet. + * Just count down (or up) if that's the case and we + * will use the data later. Note that only receive events + * can happen before the new socket is set up. */ + if (evt == NETCONN_EVT_RCVPLUS) + conn->socket--; + return; + } + + sock = get_socket(s); + if (!sock) + return; + } + else + return; + + if (!selectsem) + selectsem = sys_sem_new(1); + + sys_sem_wait(selectsem); + /* Set event as required */ + switch (evt) + { + case NETCONN_EVT_RCVPLUS: + sock->rcvevent++; + break; + case NETCONN_EVT_RCVMINUS: + sock->rcvevent--; + break; + case NETCONN_EVT_SENDPLUS: + sock->sendevent = 1; + break; + case NETCONN_EVT_SENDMINUS: + sock->sendevent = 0; + break; + } + sys_sem_signal(selectsem); + + /* Now decide if anyone is waiting for this socket */ + /* NOTE: This code is written this way to protect the select link list + but to avoid a deadlock situation by releasing socksem before + signalling for the select. This means we need to go through the list + multiple times ONLY IF a select was actually waiting. We go through + the list the number of waiting select calls + 1. This list is + expected to be small. */ + while (1) + { + sys_sem_wait(selectsem); + for (scb = select_cb_list; scb; scb = scb->next) + { + if (scb->sem_signalled == 0) + { + /* Test this select call for our socket */ + if (scb->readset && FD_ISSET(s, scb->readset)) + if (sock->rcvevent) + break; + if (scb->writeset && FD_ISSET(s, scb->writeset)) + if (sock->sendevent) + break; + } + } + if (scb) + { + scb->sem_signalled = 1; + sys_sem_signal(selectsem); + sys_sem_signal(scb->sem); + } else { + sys_sem_signal(selectsem); + break; + } + } + +} + + + + +int lwip_shutdown(int s, int how) +{ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); + return lwip_close(s); /* XXX temporary hack until proper implementation */ +} + +int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen) +{ + struct lwip_socket *sock; + struct sockaddr_in sin; + struct ip_addr naddr; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + + /* get the IP address and port of the remote host */ + netconn_peer(sock->conn, &naddr, &sin.sin_port); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, &naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port)); + + sin.sin_port = htons(sin.sin_port); + sin.sin_addr.s_addr = naddr.addr; + + if (*namelen > sizeof(sin)) + *namelen = sizeof(sin); + + memcpy(name, &sin, *namelen); + sock_set_errno(sock, 0); + return 0; +} + +int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen) +{ + struct lwip_socket *sock; + struct sockaddr_in sin; + struct ip_addr *naddr; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + + /* get the IP address and port of the remote host */ + netconn_addr(sock->conn, &naddr, &sin.sin_port); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port)); + + sin.sin_port = htons(sin.sin_port); + sin.sin_addr.s_addr = naddr->addr; + + if (*namelen > sizeof(sin)) + *namelen = sizeof(sin); + + memcpy(name, &sin, *namelen); + sock_set_errno(sock, 0); + return 0; +} + +int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen) +{ + int err = 0; + struct lwip_socket *sock = get_socket(s); + + if(!sock) { + set_errno(EBADF); + return -1; + } + + if( NULL == optval || NULL == optlen ) { + sock_set_errno( sock, EFAULT ); + return -1; + } + + /* Do length and type checks for the various options first, to keep it readable. */ + switch( level ) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch(optname) { + + case SO_ACCEPTCONN: + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_ERROR: + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINLINE: */ + /* UNIMPL case SO_RCVBUF: */ + /* UNIMPL case SO_SNDBUF: */ + /* UNIMPL case SO_RCVLOWAT: */ + /* UNIMPL case SO_SNDLOWAT: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + case SO_TYPE: + /* UNIMPL case SO_USELOOPBACK: */ + if( *optlen < sizeof(int) ) { + err = EINVAL; + } + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch(optname) { + /* UNIMPL case IP_HDRINCL: */ + /* UNIMPL case IP_RCVDSTADDR: */ + /* UNIMPL case IP_RCVIF: */ + case IP_TTL: + case IP_TOS: + if( *optlen < sizeof(int) ) { + err = EINVAL; + } + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + if( *optlen < sizeof(int) ) { + err = EINVAL; + break; + } + + /* If this is no TCP socket, ignore any options. */ + if ( sock->conn->type != NETCONN_TCP ) return 0; + + switch( optname ) { + case TCP_NODELAY: + case TCP_KEEPALIVE: + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* UNDEFINED LEVEL */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname)); + err = ENOPROTOOPT; + } /* switch */ + + + if( 0 != err ) { + sock_set_errno(sock, err); + return -1; + } + + + + /* Now do the actual option processing */ + + switch(level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch( optname ) { + + /* The option flags */ + case SO_ACCEPTCONN: + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINCLUDE: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + /*case SO_USELOOPBACK: UNIMPL */ + *(int*)optval = sock->conn->pcb.tcp->so_options & optname; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off"))); + break; + + case SO_TYPE: + switch (sock->conn->type) { + case NETCONN_RAW: + *(int*)optval = SOCK_RAW; + break; + case NETCONN_TCP: + *(int*)optval = SOCK_STREAM; + break; + case NETCONN_UDP: + case NETCONN_UDPLITE: + case NETCONN_UDPNOCHKSUM: + *(int*)optval = SOCK_DGRAM; + break; + default: /* unrecognized socket type */ + *(int*)optval = sock->conn->type; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval)); + } /* switch */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval)); + break; + + case SO_ERROR: + *(int *)optval = sock->err; + sock->err = 0; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval)); + break; + } /* switch */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch( optname ) { + case IP_TTL: + *(int*)optval = sock->conn->pcb.tcp->ttl; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval)); + break; + case IP_TOS: + *(int*)optval = sock->conn->pcb.tcp->tos; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval)); + break; + } /* switch */ + break; + +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + switch( optname ) { + case TCP_NODELAY: + *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + *(int*)optval = (int)sock->conn->pcb.tcp->keepalive; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval)); + break; + } /* switch */ + break; + } + + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen) +{ + struct lwip_socket *sock = get_socket(s); + int err = 0; + + if(!sock) { + set_errno(EBADF); + return -1; + } + + if( NULL == optval ) { + sock_set_errno( sock, EFAULT ); + return -1; + } + + + /* Do length and type checks for the various options first, to keep it readable. */ + switch( level ) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch(optname) { + + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINLINE: */ + /* UNIMPL case SO_RCVBUF: */ + /* UNIMPL case SO_SNDBUF: */ + /* UNIMPL case SO_RCVLOWAT: */ + /* UNIMPL case SO_SNDLOWAT: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + /* UNIMPL case SO_USELOOPBACK: */ + if( optlen < sizeof(int) ) { + err = EINVAL; + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch(optname) { + /* UNIMPL case IP_HDRINCL: */ + /* UNIMPL case IP_RCVDSTADDR: */ + /* UNIMPL case IP_RCVIF: */ + case IP_TTL: + case IP_TOS: + if( optlen < sizeof(int) ) { + err = EINVAL; + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + if( optlen < sizeof(int) ) { + err = EINVAL; + break; + } + + /* If this is no TCP socket, ignore any options. */ + if ( sock->conn->type != NETCONN_TCP ) return 0; + + switch( optname ) { + case TCP_NODELAY: + case TCP_KEEPALIVE: + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* UNDEFINED LEVEL */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname)); + err = ENOPROTOOPT; + } /* switch */ + + + if( 0 != err ) { + sock_set_errno(sock, err); + return -1; + } + + + + /* Now do the actual option processing */ + + switch(level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch(optname) { + + /* The option flags */ + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINCLUDE: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + /* UNIMPL case SO_USELOOPBACK: */ + if ( *(int*)optval ) { + sock->conn->pcb.tcp->so_options |= optname; + } else { + sock->conn->pcb.tcp->so_options &= ~optname; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off"))); + break; + } /* switch */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch( optname ) { + case IP_TTL: + sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl)); + break; + case IP_TOS: + sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos)); + break; + } /* switch */ + break; + +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + switch( optname ) { + case TCP_NODELAY: + if ( *(int*)optval ) { + sock->conn->pcb.tcp->flags |= TF_NODELAY; + } else { + sock->conn->pcb.tcp->flags &= ~TF_NODELAY; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive)); + break; + } /* switch */ + break; + } /* switch */ + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +int lwip_ioctl(int s, long cmd, void *argp) +{ + struct lwip_socket *sock = get_socket(s); + + if(!sock) { + set_errno(EBADF); + return -1; + } + + switch (cmd) { + case FIONREAD: + if (!argp) { + sock_set_errno(sock, EINVAL); + return -1; + } + + *((u16_t*)argp) = sock->conn->recv_avail; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp))); + sock_set_errno(sock, 0); + return 0; + + case FIONBIO: + if (argp && *(u32_t*)argp) + sock->flags |= O_NONBLOCK; + else + sock->flags &= ~O_NONBLOCK; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK))); + sock_set_errno(sock, 0); + return 0; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + return -1; + } +} + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/tcpip.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/tcpip.c new file mode 100644 index 0000000..db86cf4 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/api/tcpip.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/sys.h" + +#include "lwip/memp.h" +#include "lwip/pbuf.h" + +#include "lwip/ip.h" +#include "lwip/ip_frag.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" + +#include "lwip/tcpip.h" + +static void (* tcpip_init_done)(void *arg) = NULL; +static void *tcpip_init_done_arg; +static sys_mbox_t mbox; + +#if LWIP_TCP +static int tcpip_tcp_timer_active = 0; + +static void +tcpip_tcp_timer(void *arg) +{ + (void)arg; + + /* call TCP timer handler */ + tcp_tmr(); + /* timer still needed? */ + if (tcp_active_pcbs || tcp_tw_pcbs) { + /* restart timer */ + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + } else { + /* disable timer */ + tcpip_tcp_timer_active = 0; + } +} + +#if !NO_SYS +void +tcp_timer_needed(void) +{ + /* timer is off but needed again? */ + if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { + /* enable and start timer */ + tcpip_tcp_timer_active = 1; + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + } +} +#endif /* !NO_SYS */ +#endif /* LWIP_TCP */ + +#if IP_REASSEMBLY +static void +ip_timer(void *data) +{ + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n")); + ip_reass_tmr(); + sys_timeout(1000, ip_timer, NULL); +} +#endif + +static void +tcpip_thread(void *arg) +{ + struct tcpip_msg *msg; + + (void)arg; + + ip_init(); +#if LWIP_UDP + udp_init(); +#endif +#if LWIP_TCP + tcp_init(); +#endif +#if IP_REASSEMBLY + sys_timeout(1000, ip_timer, NULL); +#endif + if (tcpip_init_done != NULL) { + tcpip_init_done(tcpip_init_done_arg); + } + + while (1) { /* MAIN Loop */ + sys_mbox_fetch(mbox, (void *)&msg); + switch (msg->type) { + case TCPIP_MSG_API: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg)); + api_msg_input(msg->msg.apimsg); + break; + case TCPIP_MSG_INPUT: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg)); + ip_input(msg->msg.inp.p, msg->msg.inp.netif); + break; + case TCPIP_MSG_CALLBACK: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); + msg->msg.cb.f(msg->msg.cb.ctx); + break; + default: + break; + } + memp_free(MEMP_TCPIP_MSG, msg); + } +} + +err_t +tcpip_input(struct pbuf *p, struct netif *inp) +{ + struct tcpip_msg *msg; + + msg = memp_malloc(MEMP_TCPIP_MSG); + if (msg == NULL) { + pbuf_free(p); + return ERR_MEM; + } + + msg->type = TCPIP_MSG_INPUT; + msg->msg.inp.p = p; + msg->msg.inp.netif = inp; + sys_mbox_post(mbox, msg); + return ERR_OK; +} + +err_t +tcpip_callback(void (*f)(void *ctx), void *ctx) +{ + struct tcpip_msg *msg; + + msg = memp_malloc(MEMP_TCPIP_MSG); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_CALLBACK; + msg->msg.cb.f = f; + msg->msg.cb.ctx = ctx; + sys_mbox_post(mbox, msg); + return ERR_OK; +} + +void +tcpip_apimsg(struct api_msg *apimsg) +{ + struct tcpip_msg *msg; + msg = memp_malloc(MEMP_TCPIP_MSG); + if (msg == NULL) { + memp_free(MEMP_API_MSG, apimsg); + return; + } + msg->type = TCPIP_MSG_API; + msg->msg.apimsg = apimsg; + sys_mbox_post(mbox, msg); +} + +void +tcpip_init(void (* initfunc)(void *), void *arg) +{ + tcpip_init_done = initfunc; + tcpip_init_done_arg = arg; + mbox = sys_mbox_new(); + sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO); +} + + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/dhcp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/dhcp.c new file mode 100644 index 0000000..47f65c2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/dhcp.c @@ -0,0 +1,1464 @@ +/** + * @file + * + * Dynamic Host Configuration Protocol client + */ + +/* + * + * Copyright (c) 2001-2004 Leon Woestenberg + * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. + * + * Author: Leon Woestenberg + * + * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform + * with RFC 2131 and RFC 2132. + * + * TODO: + * - Proper parsing of DHCP messages exploiting file/sname field overloading. + * - Add JavaDoc style documentation (API, internals). + * - Support for interfaces other than Ethernet (SLIP, PPP, ...) + * + * Please coordinate changes and requests with Leon Woestenberg + * + * + * Integration with your code: + * + * In lwip/dhcp.h + * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute) + * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer) + * + * Then have your application call dhcp_coarse_tmr() and + * dhcp_fine_tmr() on the defined intervals. + * + * dhcp_start(struct netif *netif); + * starts a DHCP client instance which configures the interface by + * obtaining an IP address lease and maintaining it. + * + * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif) + * to remove the DHCP client. + * + */ + +#include + +#include "lwip/stats.h" +#include "lwip/mem.h" +#include "lwip/udp.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/inet.h" +#include "netif/etharp.h" + +#include "lwip/sys.h" +#include "lwip/opt.h" +#include "lwip/dhcp.h" + +#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */ + +/** global transaction identifier, must be + * unique for each DHCP request. We simply increment, starting + * with this value (easy to match with a packet analyzer) */ +static u32_t xid = 0xABCD0000; + +/** DHCP client state machine functions */ +static void dhcp_handle_ack(struct netif *netif); +static void dhcp_handle_nak(struct netif *netif); +static void dhcp_handle_offer(struct netif *netif); + +static err_t dhcp_discover(struct netif *netif); +static err_t dhcp_select(struct netif *netif); +static void dhcp_check(struct netif *netif); +static void dhcp_bind(struct netif *netif); +static err_t dhcp_decline(struct netif *netif); +static err_t dhcp_rebind(struct netif *netif); +static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state); + +/** receive, unfold, parse and free incoming messages */ +static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); +static err_t dhcp_unfold_reply(struct dhcp *dhcp); +static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type); +static u8_t dhcp_get_option_byte(u8_t *ptr); +#if 0 +static u16_t dhcp_get_option_short(u8_t *ptr); +#endif +static u32_t dhcp_get_option_long(u8_t *ptr); +static void dhcp_free_reply(struct dhcp *dhcp); + +/** set the DHCP timers */ +static void dhcp_timeout(struct netif *netif); +static void dhcp_t1_timeout(struct netif *netif); +static void dhcp_t2_timeout(struct netif *netif); + +/** build outgoing messages */ +/** create a DHCP request, fill in common headers */ +static err_t dhcp_create_request(struct netif *netif); +/** free a DHCP request */ +static void dhcp_delete_request(struct netif *netif); +/** add a DHCP option (type, then length in bytes) */ +static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len); +/** add option values */ +static void dhcp_option_byte(struct dhcp *dhcp, u8_t value); +static void dhcp_option_short(struct dhcp *dhcp, u16_t value); +static void dhcp_option_long(struct dhcp *dhcp, u32_t value); +/** always add the DHCP options trailer to end and pad */ +static void dhcp_option_trailer(struct dhcp *dhcp); + +/** + * Back-off the DHCP client (because of a received NAK response). + * + * Back-off the DHCP client because of a received NAK. Receiving a + * NAK means the client asked for something non-sensible, for + * example when it tries to renew a lease obtained on another network. + * + * We back-off and will end up restarting a fresh DHCP negotiation later. + * + * @param state pointer to DHCP state structure + */ +static void dhcp_handle_nak(struct netif *netif) { + struct dhcp *dhcp = netif->dhcp; + u16_t msecs = 10 * 1000; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", + (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %"U16_F" msecs\n", msecs)); + dhcp_set_state(dhcp, DHCP_BACKING_OFF); +} + +/** + * Checks if the offered IP address is already in use. + * + * It does so by sending an ARP request for the offered address and + * entering CHECKING state. If no ARP reply is received within a small + * interval, the address is assumed to be free for use by us. + */ +static void dhcp_check(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], + (s16_t)netif->name[1])); + /* create an ARP query for the offered IP address, expecting that no host + responds, as the IP address should not be in use. */ + result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); + if (result != ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n")); + } + dhcp->tries++; + msecs = 500; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); + dhcp_set_state(dhcp, DHCP_CHECKING); +} + +/** + * Remember the configuration offered by a DHCP server. + * + * @param state pointer to DHCP state structure + */ +static void dhcp_handle_offer(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + /* obtain the server address */ + u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", + (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + if (option_ptr != NULL) + { + dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr)); + /* remember offered address */ + ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr); + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); + + dhcp_select(netif); + } +} + +/** + * Select a DHCP server offer out of all offers. + * + * Simply select the first offer received. + * + * @param netif the netif under DHCP control + * @return lwIP specific error (see error.h) + */ +static err_t dhcp_select(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u32_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) + { + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_REQUEST); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + + /* MUST request the offered IP address */ + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); + + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); + + dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); + dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); + dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); + dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); + dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); + + dhcp_option_trailer(dhcp); + /* shrink the pbuf to the actual content length */ + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* TODO: we really should bind to a specific local interface here + but we cannot specify an unconfigured netif as it is addressless */ + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + /* send broadcast to any DHCP server */ + udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + udp_send(dhcp->pcb, dhcp->p_out); + /* reconnect to any (or to server here?!) */ + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n")); + dhcp_set_state(dhcp, DHCP_REQUESTING); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %"U32_F" msecs\n", msecs)); + return result; +} + +/** + * The DHCP timer that checks for lease renewal/rebind timeouts. + * + */ +void dhcp_coarse_tmr() +{ + struct netif *netif = netif_list; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n")); + /* iterate through all network interfaces */ + while (netif != NULL) { + /* only act on DHCP configured interfaces */ + if (netif->dhcp != NULL) { + /* timer is active (non zero), and triggers (zeroes) now? */ + if (netif->dhcp->t2_timeout-- == 1) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n")); + /* this clients' rebind timeout triggered */ + dhcp_t2_timeout(netif); + /* timer is active (non zero), and triggers (zeroes) now */ + } else if (netif->dhcp->t1_timeout-- == 1) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n")); + /* this clients' renewal timeout triggered */ + dhcp_t1_timeout(netif); + } + } + /* proceed to next netif */ + netif = netif->next; + } +} + +/** + * DHCP transaction timeout handling + * + * A DHCP server is expected to respond within a short period of time. + * This timer checks whether an outstanding DHCP request is timed out. + * + */ +void dhcp_fine_tmr() +{ + struct netif *netif = netif_list; + /* loop through netif's */ + while (netif != NULL) { + /* only act on DHCP configured interfaces */ + if (netif->dhcp != NULL) { + /* timer is active (non zero), and is about to trigger now */ + if (netif->dhcp->request_timeout > 1) { + netif->dhcp->request_timeout--; + } + else if (netif->dhcp->request_timeout == 1) { + netif->dhcp->request_timeout--; + /* { netif->dhcp->request_timeout == 0 } */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); + /* this clients' request timeout triggered */ + dhcp_timeout(netif); + } + } + /* proceed to next network interface */ + netif = netif->next; + } +} + +/** + * A DHCP negotiation transaction, or ARP request, has timed out. + * + * The timer that was started with the DHCP or ARP request has + * timed out, indicating no response was received in time. + * + * @param netif the netif under DHCP control + * + */ +static void dhcp_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n")); + /* back-off period has passed, or server selection timed out */ + if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n")); + dhcp_discover(netif); + /* receiving the requested lease timed out */ + } else if (dhcp->state == DHCP_REQUESTING) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n")); + if (dhcp->tries <= 5) { + dhcp_select(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n")); + dhcp_release(netif); + dhcp_discover(netif); + } + /* received no ARP reply for the offered address (which is good) */ + } else if (dhcp->state == DHCP_CHECKING) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n")); + if (dhcp->tries <= 1) { + dhcp_check(netif); + /* no ARP replies on the offered address, + looks like the IP address is indeed free */ + } else { + /* bind the interface to the offered address */ + dhcp_bind(netif); + } + } + /* did not get response to renew request? */ + else if (dhcp->state == DHCP_RENEWING) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n")); + /* just retry renewal */ + /* note that the rebind timer will eventually time-out if renew does not work */ + dhcp_renew(netif); + /* did not get response to rebind request? */ + } else if (dhcp->state == DHCP_REBINDING) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n")); + if (dhcp->tries <= 8) { + dhcp_rebind(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n")); + dhcp_release(netif); + dhcp_discover(netif); + } + } +} + +/** + * The renewal period has timed out. + * + * @param netif the netif under DHCP control + */ +static void dhcp_t1_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n")); + if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { + /* just retry to renew - note that the rebind timer (t2) will + * eventually time-out if renew tries fail. */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n")); + dhcp_renew(netif); + } +} + +/** + * The rebind period has timed out. + * + */ +static void dhcp_t2_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n")); + if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { + /* just retry to rebind */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n")); + dhcp_rebind(netif); + } +} + +/** + * + * @param netif the netif under DHCP control + */ +static void dhcp_handle_ack(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + u8_t *option_ptr; + /* clear options we might not get from the ACK */ + dhcp->offered_sn_mask.addr = 0; + dhcp->offered_gw_addr.addr = 0; + dhcp->offered_bc_addr.addr = 0; + + /* lease time given? */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME); + if (option_ptr != NULL) { + /* remember offered lease time */ + dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2); + } + /* renewal period given? */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1); + if (option_ptr != NULL) { + /* remember given renewal period */ + dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2); + } else { + /* calculate safe periods for renewal */ + dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2; + } + + /* renewal period given? */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2); + if (option_ptr != NULL) { + /* remember given rebind period */ + dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2); + } else { + /* calculate safe periods for rebinding */ + dhcp->offered_t2_rebind = dhcp->offered_t0_lease; + } + + /* (y)our internet address */ + ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr); + +/** + * Patch #1308 + * TODO: we must check if the file field is not overloaded by DHCP options! + */ +#if 0 + /* boot server address */ + ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr); + /* boot file name */ + if (dhcp->msg_in->file[0]) { + dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1); + strcpy(dhcp->boot_file_name, dhcp->msg_in->file); + } +#endif + + /* subnet mask */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK); + /* subnet mask given? */ + if (option_ptr != NULL) { + dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2])); + } + + /* gateway router */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER); + if (option_ptr != NULL) { + dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); + } + + /* broadcast address */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST); + if (option_ptr != NULL) { + dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); + } + + /* DNS servers */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER); + if (option_ptr != NULL) { + u8_t n; + dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]) / (u32_t)sizeof(struct ip_addr); + /* limit to at most DHCP_MAX_DNS DNS servers */ + if (dhcp->dns_count > DHCP_MAX_DNS) + dhcp->dns_count = DHCP_MAX_DNS; + for (n = 0; n < dhcp->dns_count; n++) { + dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2 + n * 4])); + } + } +} + +/** + * Start DHCP negotiation for a network interface. + * + * If no DHCP client instance was attached to this interface, + * a new client is created first. If a DHCP client instance + * was already present, it restarts negotiation. + * + * @param netif The lwIP network interface + * @return lwIP error code + * - ERR_OK - No error + * - ERR_MEM - Out of memory + * + */ +err_t dhcp_start(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result = ERR_OK; + + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + netif->flags &= ~NETIF_FLAG_DHCP; + + /* no DHCP client attached yet? */ + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n")); + dhcp = mem_malloc(sizeof(struct dhcp)); + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); + return ERR_MEM; + } + /* store this dhcp client in the netif */ + netif->dhcp = dhcp; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp")); + /* already has DHCP client attached */ + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n")); + } + + /* clear data structure */ + memset(dhcp, 0, sizeof(struct dhcp)); + /* allocate UDP PCB */ + dhcp->pcb = udp_new(); + if (dhcp->pcb == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n")); + mem_free((void *)dhcp); + netif->dhcp = dhcp = NULL; + return ERR_MEM; + } + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); + /* (re)start the DHCP negotiation */ + result = dhcp_discover(netif); + if (result != ERR_OK) { + /* free resources allocated above */ + dhcp_stop(netif); + return ERR_MEM; + } + netif->flags |= NETIF_FLAG_DHCP; + return result; +} + +/** + * Inform a DHCP server of our manual configuration. + * + * This informs DHCP servers of our fixed IP address configuration + * by sending an INFORM message. It does not involve DHCP address + * configuration, it is just here to be nice to the network. + * + * @param netif The lwIP network interface + * + */ +void dhcp_inform(struct netif *netif) +{ + struct dhcp *dhcp; + err_t result = ERR_OK; + dhcp = mem_malloc(sizeof(struct dhcp)); + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n")); + return; + } + netif->dhcp = dhcp; + memset(dhcp, 0, sizeof(struct dhcp)); + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n")); + dhcp->pcb = udp_new(); + if (dhcp->pcb == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb")); + mem_free((void *)dhcp); + return; + } + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n")); + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) { + + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_INFORM); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + /* TODO: use netif->mtu ?! */ + dhcp_option_short(dhcp, 576); + + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n")); + udp_send(dhcp->pcb, dhcp->p_out); + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + dhcp_delete_request(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n")); + } + + if (dhcp != NULL) + { + if (dhcp->pcb != NULL) udp_remove(dhcp->pcb); + dhcp->pcb = NULL; + mem_free((void *)dhcp); + netif->dhcp = NULL; + } +} + +#if DHCP_DOES_ARP_CHECK +/** + * Match an ARP reply with the offered IP address. + * + * @param addr The IP address we received a reply from + * + */ +void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr) +{ + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n")); + /* is a DHCP client doing an ARP check? */ + if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr)); + /* did a host respond with the address we + were offered by the DHCP server? */ + if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) { + /* we will not accept the offered address */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n")); + dhcp_decline(netif); + } + } +} + +/** + * Decline an offered lease. + * + * Tell the DHCP server we do not accept the offered address. + * One reason to decline the lease is when we find out the address + * is already in use by another host (through ARP). + */ +static err_t dhcp_decline(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result = ERR_OK; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n")); + dhcp_set_state(dhcp, DHCP_BACKING_OFF); + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) + { + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_DECLINE); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); + + dhcp_option_trailer(dhcp); + /* resize pbuf to reflect true size of options */ + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + /* @todo: should we really connect here? we are performing sendto() */ + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + /* per section 4.4.4, broadcast DECLINE messages */ + udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = 10*1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} +#endif + + +/** + * Start the DHCP process, discover a DHCP server. + * + */ +static err_t dhcp_discover(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result = ERR_OK; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n")); + ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY); + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) + { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n")); + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_DISCOVER); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + + dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); + dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); + dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); + dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); + dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); + + dhcp_option_trailer(dhcp); + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n")); + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* set receive callback function with netif as user data */ + udp_recv(dhcp->pcb, dhcp_recv, netif); + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n")); + udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n")); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n")); + dhcp_set_state(dhcp, DHCP_SELECTING); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + + +/** + * Bind the interface to the offered IP address. + * + * @param netif network interface to bind to the offered address + */ +static void dhcp_bind(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + struct ip_addr sn_mask, gw_addr; + LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL); + LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + /* temporary DHCP lease? */ + if (dhcp->offered_t1_renew != 0xffffffffUL) { + /* set renewal period timer */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); + dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000)); + } + /* set renewal period timer */ + if (dhcp->offered_t2_rebind != 0xffffffffUL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); + dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000)); + } + /* copy offered network mask */ + ip_addr_set(&sn_mask, &dhcp->offered_sn_mask); + + /* subnet mask not given? */ + /* TODO: this is not a valid check. what if the network mask is 0? */ + if (sn_mask.addr == 0) { + /* choose a safe subnet mask given the network class */ + u8_t first_octet = ip4_addr1(&sn_mask); + if (first_octet <= 127) sn_mask.addr = htonl(0xff000000); + else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00); + else sn_mask.addr = htonl(0xffff0000); + } + + ip_addr_set(&gw_addr, &dhcp->offered_gw_addr); + /* gateway address not given? */ + if (gw_addr.addr == 0) { + /* copy network address */ + gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr); + /* use first host address on network as gateway */ + gw_addr.addr |= htonl(0x00000001); + } + + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); + netif_set_ipaddr(netif, &dhcp->offered_ip_addr); + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr)); + netif_set_netmask(netif, &sn_mask); + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr)); + netif_set_gw(netif, &gw_addr); + /* bring the interface up */ + netif_set_up(netif); + /* netif is now bound to DHCP leased address */ + dhcp_set_state(dhcp, DHCP_BOUND); +} + +/** + * Renew an existing DHCP lease at the involved DHCP server. + * + * @param netif network interface which must renew its lease + */ +err_t dhcp_renew(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n")); + dhcp_set_state(dhcp, DHCP_RENEWING); + + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) { + + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_REQUEST); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + /* TODO: use netif->mtu in some way */ + dhcp_option_short(dhcp, 576); + +#if 0 + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); +#endif + +#if 0 + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); +#endif + /* append DHCP message trailer */ + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT); + udp_send(dhcp->pcb, dhcp->p_out); + dhcp_delete_request(netif); + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n")); + } + dhcp->tries++; + /* back-off on retries, but to a maximum of 20 seconds */ + msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * Rebind with a DHCP server for an existing DHCP lease. + * + * @param netif network interface which must rebind with a DHCP server + */ +static err_t dhcp_rebind(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n")); + dhcp_set_state(dhcp, DHCP_REBINDING); + + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) + { + + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_REQUEST); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + +#if 0 + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); + + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); +#endif + + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* set remote IP association to any DHCP server */ + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + /* broadcast to server */ + udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * Release a DHCP lease. + * + * @param netif network interface which must release its lease + */ +err_t dhcp_release(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n")); + + /* idle DHCP client */ + dhcp_set_state(dhcp, DHCP_OFF); + /* clean old DHCP offer */ + dhcp->server_ip_addr.addr = 0; + dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0; + dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0; + dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; + dhcp->dns_count = 0; + + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) { + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_RELEASE); + + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT); + udp_send(dhcp->pcb, dhcp->p_out); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs)); + /* bring the interface down */ + netif_set_down(netif); + /* remove IP address from interface */ + netif_set_ipaddr(netif, IP_ADDR_ANY); + netif_set_gw(netif, IP_ADDR_ANY); + netif_set_netmask(netif, IP_ADDR_ANY); + + /* TODO: netif_down(netif); */ + return result; +} +/** + * Remove the DHCP client from the interface. + * + * @param netif The network interface to stop DHCP on + */ +void dhcp_stop(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL); + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n")); + /* netif is DHCP configured? */ + if (dhcp != NULL) + { + if (dhcp->pcb != NULL) + { + udp_remove(dhcp->pcb); + dhcp->pcb = NULL; + } + if (dhcp->p != NULL) + { + pbuf_free(dhcp->p); + dhcp->p = NULL; + } + /* free unfolded reply */ + dhcp_free_reply(dhcp); + mem_free((void *)dhcp); + netif->dhcp = NULL; + } +} + +/* + * Set the DHCP state of a DHCP client. + * + * If the state changed, reset the number of tries. + * + * TODO: we might also want to reset the timeout here? + */ +static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state) +{ + if (new_state != dhcp->state) + { + dhcp->state = new_state; + dhcp->tries = 0; + } +} + +/* + * Concatenate an option type and length field to the outgoing + * DHCP message. + * + */ +static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len) +{ + LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = option_type; + dhcp->msg_out->options[dhcp->options_out_len++] = option_len; +} +/* + * Concatenate a single byte to the outgoing DHCP message. + * + */ +static void dhcp_option_byte(struct dhcp *dhcp, u8_t value) +{ + LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = value; +} +static void dhcp_option_short(struct dhcp *dhcp, u16_t value) +{ + LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8; + dhcp->msg_out->options[dhcp->options_out_len++] = value & 0x00ffU; +} +static void dhcp_option_long(struct dhcp *dhcp, u32_t value) +{ + LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24; + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16; + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8; + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL); +} + +/** + * Extract the DHCP message and the DHCP options. + * + * Extract the DHCP message and the DHCP options, each into a contiguous + * piece of memory. As a DHCP message is variable sized by its options, + * and also allows overriding some fields for options, the easy approach + * is to first unfold the options into a conitguous piece of memory, and + * use that further on. + * + */ +static err_t dhcp_unfold_reply(struct dhcp *dhcp) +{ + struct pbuf *p = dhcp->p; + u8_t *ptr; + u16_t i; + u16_t j = 0; + LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL); + /* free any left-overs from previous unfolds */ + dhcp_free_reply(dhcp); + /* options present? */ + if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN)) + { + dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); + dhcp->options_in = mem_malloc(dhcp->options_in_len); + if (dhcp->options_in == NULL) + { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n")); + return ERR_MEM; + } + } + dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); + if (dhcp->msg_in == NULL) + { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n")); + mem_free((void *)dhcp->options_in); + dhcp->options_in = NULL; + return ERR_MEM; + } + + ptr = (u8_t *)dhcp->msg_in; + /* proceed through struct dhcp_msg */ + for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++) + { + *ptr++ = ((u8_t *)p->payload)[j++]; + /* reached end of pbuf? */ + if (j == p->len) + { + /* proceed to next pbuf in chain */ + p = p->next; + j = 0; + } + } + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n", i)); + if (dhcp->options_in != NULL) { + ptr = (u8_t *)dhcp->options_in; + /* proceed through options */ + for (i = 0; i < dhcp->options_in_len; i++) { + *ptr++ = ((u8_t *)p->payload)[j++]; + /* reached end of pbuf? */ + if (j == p->len) { + /* proceed to next pbuf in chain */ + p = p->next; + j = 0; + } + } + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n", i)); + } + return ERR_OK; +} + +/** + * Free the incoming DHCP message including contiguous copy of + * its DHCP options. + * + */ +static void dhcp_free_reply(struct dhcp *dhcp) +{ + if (dhcp->msg_in != NULL) { + mem_free((void *)dhcp->msg_in); + dhcp->msg_in = NULL; + } + if (dhcp->options_in) { + mem_free((void *)dhcp->options_in); + dhcp->options_in = NULL; + dhcp->options_in_len = 0; + } + LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n")); +} + + +/** + * If an incoming DHCP message is in response to us, then trigger the state machine + */ +static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port) +{ + struct netif *netif = (struct netif *)arg; + struct dhcp *dhcp = netif->dhcp; + struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload; + u8_t *options_ptr; + u8_t msg_type; + u8_t i; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p, + (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff), + (u16_t)(ntohl(addr->addr) >> 8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port)); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); + /* prevent warnings about unused arguments */ + (void)pcb; (void)addr; (void)port; + dhcp->p = p; + /* TODO: check packet length before reading them */ + if (reply_msg->op != DHCP_BOOTREPLY) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); + pbuf_free(p); + dhcp->p = NULL; + return; + } + /* iterate through hardware address and match against DHCP message */ + for (i = 0; i < netif->hwaddr_len; i++) { + if (netif->hwaddr[i] != reply_msg->chaddr[i]) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n", + (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); + pbuf_free(p); + dhcp->p = NULL; + return; + } + } + /* match transaction ID against what we expected */ + if (ntohl(reply_msg->xid) != dhcp->xid) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",ntohl(reply_msg->xid),dhcp->xid)); + pbuf_free(p); + dhcp->p = NULL; + return; + } + /* option fields could be unfold? */ + if (dhcp_unfold_reply(dhcp) != ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n")); + pbuf_free(p); + dhcp->p = NULL; + return; + } + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n")); + /* obtain pointer to DHCP message type */ + options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE); + if (options_ptr == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n")); + pbuf_free(p); + dhcp->p = NULL; + return; + } + + /* read DHCP message type */ + msg_type = dhcp_get_option_byte(options_ptr + 2); + /* message type is DHCP ACK? */ + if (msg_type == DHCP_ACK) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n")); + /* in requesting state? */ + if (dhcp->state == DHCP_REQUESTING) { + dhcp_handle_ack(netif); + dhcp->request_timeout = 0; +#if DHCP_DOES_ARP_CHECK + /* check if the acknowledged lease address is already in use */ + dhcp_check(netif); +#else + /* bind interface to the acknowledged lease address */ + dhcp_bind(netif); +#endif + } + /* already bound to the given lease address? */ + else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) { + dhcp->request_timeout = 0; + dhcp_bind(netif); + } + } + /* received a DHCP_NAK in appropriate state? */ + else if ((msg_type == DHCP_NAK) && + ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) || + (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING ))) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n")); + dhcp->request_timeout = 0; + dhcp_handle_nak(netif); + } + /* received a DHCP_OFFER in DHCP_SELECTING state? */ + else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n")); + dhcp->request_timeout = 0; + /* remember offered lease */ + dhcp_handle_offer(netif); + } + pbuf_free(p); + dhcp->p = NULL; +} + + +static err_t dhcp_create_request(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + u16_t i; + LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL); + LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL); + dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM); + if (dhcp->p_out == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n")); + return ERR_MEM; + } + /* give unique transaction identifier to this request */ + dhcp->xid = xid++; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id xid++(%"X32_F") dhcp->xid(%"U32_F")\n",xid,dhcp->xid)); + + dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload; + + dhcp->msg_out->op = DHCP_BOOTREQUEST; + /* TODO: make link layer independent */ + dhcp->msg_out->htype = DHCP_HTYPE_ETH; + /* TODO: make link layer independent */ + dhcp->msg_out->hlen = DHCP_HLEN_ETH; + dhcp->msg_out->hops = 0; + dhcp->msg_out->xid = htonl(dhcp->xid); + dhcp->msg_out->secs = 0; + dhcp->msg_out->flags = 0; + dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr; + dhcp->msg_out->yiaddr.addr = 0; + dhcp->msg_out->siaddr.addr = 0; + dhcp->msg_out->giaddr.addr = 0; + for (i = 0; i < DHCP_CHADDR_LEN; i++) { + /* copy netif hardware address, pad with zeroes */ + dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/; + } + for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0; + for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0; + dhcp->msg_out->cookie = htonl(0x63825363UL); + dhcp->options_out_len = 0; + /* fill options field with an incrementing array (for debugging purposes) */ + for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i; + return ERR_OK; +} + +static void dhcp_delete_request(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL); + LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL); + pbuf_free(dhcp->p_out); + dhcp->p_out = NULL; + dhcp->msg_out = NULL; +} + +/** + * Add a DHCP message trailer + * + * Adds the END option to the DHCP message, and if + * necessary, up to three padding bytes. + */ + +static void dhcp_option_trailer(struct dhcp *dhcp) +{ + LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL); + LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END; + /* packet is too small, or not 4 byte aligned? */ + while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) { + /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */ + LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); + /* add a fill/padding byte */ + dhcp->msg_out->options[dhcp->options_out_len++] = 0; + } +} + +/** + * Find the offset of a DHCP option inside the DHCP message. + * + * @param client DHCP client + * @param option_type + * + * @return a byte offset into the UDP message where the option was found, or + * zero if the given option was not found. + */ +static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type) +{ + u8_t overload = DHCP_OVERLOAD_NONE; + + /* options available? */ + if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) { + /* start with options field */ + u8_t *options = (u8_t *)dhcp->options_in; + u16_t offset = 0; + /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ + while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) { + /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ + /* are the sname and/or file field overloaded with options? */ + if (options[offset] == DHCP_OPTION_OVERLOAD) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n")); + /* skip option type and length */ + offset += 2; + overload = options[offset++]; + } + /* requested option found */ + else if (options[offset] == option_type) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset)); + return &options[offset]; + /* skip option */ + } else { + LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset])); + /* skip option type */ + offset++; + /* skip option length, and then length bytes */ + offset += 1 + options[offset]; + } + } + /* is this an overloaded message? */ + if (overload != DHCP_OVERLOAD_NONE) { + u16_t field_len; + if (overload == DHCP_OVERLOAD_FILE) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n")); + options = (u8_t *)&dhcp->msg_in->file; + field_len = DHCP_FILE_LEN; + } else if (overload == DHCP_OVERLOAD_SNAME) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n")); + options = (u8_t *)&dhcp->msg_in->sname; + field_len = DHCP_SNAME_LEN; + /* TODO: check if else if () is necessary */ + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n")); + options = (u8_t *)&dhcp->msg_in->sname; + field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN; + } + offset = 0; + + /* at least 1 byte to read and no end marker */ + while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) { + if (options[offset] == option_type) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%"U16_F"\n", offset)); + return &options[offset]; + /* skip option */ + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %"U16_F"\n", options[offset])); + /* skip option type */ + offset++; + offset += 1 + options[offset]; + } + } + } + } + return NULL; +} + +/** + * Return the byte of DHCP option data. + * + * @param client DHCP client. + * @param ptr pointer obtained by dhcp_get_option_ptr(). + * + * @return byte value at the given address. + */ +static u8_t dhcp_get_option_byte(u8_t *ptr) +{ + LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr))); + return *ptr; +} + +#if 0 +/** + * Return the 16-bit value of DHCP option data. + * + * @param client DHCP client. + * @param ptr pointer obtained by dhcp_get_option_ptr(). + * + * @return byte value at the given address. + */ +static u16_t dhcp_get_option_short(u8_t *ptr) +{ + u16_t value; + value = *ptr++ << 8; + value |= *ptr; + LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value)); + return value; +} +#endif + +/** + * Return the 32-bit value of DHCP option data. + * + * @param client DHCP client. + * @param ptr pointer obtained by dhcp_get_option_ptr(). + * + * @return byte value at the given address. + */ +static u32_t dhcp_get_option_long(u8_t *ptr) +{ + u32_t value; + value = (u32_t)(*ptr++) << 24; + value |= (u32_t)(*ptr++) << 16; + value |= (u32_t)(*ptr++) << 8; + value |= (u32_t)(*ptr++); + LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value)); + return value; +} + +#endif /* LWIP_DHCP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/inet.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/inet.c new file mode 100644 index 0000000..d9d52c5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/inet.c @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +/* inet.c + * + * Functions common to all TCP/IP modules, such as the Internet checksum and the + * byte order functions. + * + */ + + +#include "lwip/opt.h" + +#include "lwip/arch.h" + +#include "lwip/def.h" +#include "lwip/inet.h" + +#include "lwip/sys.h" + +/* These are some reference implementations of the checksum algorithm, with the + * aim of being simple, correct and fully portable. Checksumming is the + * first thing you would want to optimize for your platform. If you create + * your own version, link it in and in your sys_arch.h put: + * + * #define LWIP_CHKSUM +*/ +#ifndef LWIP_CHKSUM +#define LWIP_CHKSUM lwip_standard_chksum + +#if 1 /* Version A */ +/** + * lwip checksum + * + * @param dataptr points to start of data to be summed at any boundary + * @param len length of data to be summed + * @return host order (!) lwip checksum (non-inverted Internet sum) + * + * @note accumulator size limits summable length to 64k + * @note host endianess is irrelevant (p3 RFC1071) + */ +static u16_t +lwip_standard_chksum(void *dataptr, u16_t len) +{ + u32_t acc; + u16_t src; + u8_t *octetptr; + + acc = 0; + /* dataptr may be at odd or even addresses */ + octetptr = (u8_t*)dataptr; + while (len > 1) + { + /* declare first octet as most significant + thus assume network order, ignoring host order */ + src = (*octetptr) << 8; + octetptr++; + /* declare second octet as least significant */ + src |= (*octetptr); + octetptr++; + acc += src; + len -= 2; + } + if (len > 0) + { + /* accumulate remaining octet */ + src = (*octetptr) << 8; + acc += src; + } + /* add deferred carry bits */ + acc = (acc >> 16) + (acc & 0x0000ffffUL); + if ((acc & 0xffff0000) != 0) { + acc = (acc >> 16) + (acc & 0x0000ffffUL); + } + /* This maybe a little confusing: reorder sum using htons() + instead of ntohs() since it has a little less call overhead. + The caller must invert bits for Internet sum ! */ + return htons((u16_t)acc); +} +#endif + +#if 0 /* Version B */ +/* + * Curt McDowell + * Broadcom Corp. + * csm@broadcom.com + * + * IP checksum two bytes at a time with support for + * unaligned buffer. + * Works for len up to and including 0x20000. + * by Curt McDowell, Broadcom Corp. 12/08/2005 + */ + +static u16_t +lwip_standard_chksum(void *dataptr, int len) +{ + u8_t *pb = dataptr; + u16_t *ps, t = 0; + u32_t sum = 0; + int odd = ((u32_t)pb & 1); + + /* Get aligned to u16_t */ + if (odd && len > 0) { + ((u8_t *)&t)[1] = *pb++; + len--; + } + + /* Add the bulk of the data */ + ps = (u16_t *)pb; + while (len > 1) { + sum += *ps++; + len -= 2; + } + + /* Consume left-over byte, if any */ + if (len > 0) + ((u8_t *)&t)[0] = *(u8_t *)ps;; + + /* Add end bytes */ + sum += t; + + /* Fold 32-bit sum to 16 bits */ + while (sum >> 16) + sum = (sum & 0xffff) + (sum >> 16); + + /* Swap if alignment was odd */ + if (odd) + sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); + + return sum; +} +#endif + +#if 0 /* Version C */ +/** + * An optimized checksum routine. Basically, it uses loop-unrolling on + * the checksum loop, treating the head and tail bytes specially, whereas + * the inner loop acts on 8 bytes at a time. + * + * @arg start of buffer to be checksummed. May be an odd byte address. + * @len number of bytes in the buffer to be checksummed. + * + * by Curt McDowell, Broadcom Corp. December 8th, 2005 + */ + +static u16_t +lwip_standard_chksum(void *dataptr, int len) +{ + u8_t *pb = dataptr; + u16_t *ps, t = 0; + u32_t *pl; + u32_t sum = 0, tmp; + /* starts at odd byte address? */ + int odd = ((u32_t)pb & 1); + + if (odd && len > 0) { + ((u8_t *)&t)[1] = *pb++; + len--; + } + + ps = (u16_t *)pb; + + if (((u32_t)ps & 3) && len > 1) { + sum += *ps++; + len -= 2; + } + + pl = (u32_t *)ps; + + while (len > 7) { + tmp = sum + *pl++; /* ping */ + if (tmp < sum) + tmp++; /* add back carry */ + + sum = tmp + *pl++; /* pong */ + if (sum < tmp) + sum++; /* add back carry */ + + len -= 8; + } + + /* make room in upper bits */ + sum = (sum >> 16) + (sum & 0xffff); + + ps = (u16_t *)pl; + + /* 16-bit aligned word remaining? */ + while (len > 1) { + sum += *ps++; + len -= 2; + } + + /* dangling tail byte remaining? */ + if (len > 0) /* include odd byte */ + ((u8_t *)&t)[0] = *(u8_t *)ps; + + sum += t; /* add end bytes */ + + while (sum >> 16) /* combine halves */ + sum = (sum >> 16) + (sum & 0xffff); + + if (odd) + sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); + + return sum; +} +#endif + +#endif /* LWIP_CHKSUM */ + +/* inet_chksum_pseudo: + * + * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. + */ + +u16_t +inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u16_t proto_len) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped; + + acc = 0; + swapped = 0; + /* iterate through all pbuf in chain */ + for(q = p; q != NULL; q = q->next) { + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", + (void *)q, (void *)q->next)); + acc += LWIP_CHKSUM(q->payload, q->len); + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ + while (acc >> 16) { + acc = (acc & 0xffffUL) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8); + } + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ + } + + if (swapped) { + acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8); + } + acc += (src->addr & 0xffffUL); + acc += ((src->addr >> 16) & 0xffffUL); + acc += (dest->addr & 0xffffUL); + acc += ((dest->addr >> 16) & 0xffffUL); + acc += (u32_t)htons((u16_t)proto); + acc += (u32_t)htons(proto_len); + + while (acc >> 16) { + acc = (acc & 0xffffUL) + (acc >> 16); + } + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); + return (u16_t)~(acc & 0xffffUL); +} + +/* inet_chksum: + * + * Calculates the Internet checksum over a portion of memory. Used primarily for IP + * and ICMP. + */ + +u16_t +inet_chksum(void *dataptr, u16_t len) +{ + u32_t acc; + + acc = LWIP_CHKSUM(dataptr, len); + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + return (u16_t)~(acc & 0xffff); +} + +u16_t +inet_chksum_pbuf(struct pbuf *p) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped; + + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { + acc += LWIP_CHKSUM(q->payload, q->len); + while (acc >> 16) { + acc = (acc & 0xffffUL) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8); + } + } + + if (swapped) { + acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8); + } + return (u16_t)~(acc & 0xffffUL); +} + +/* Here for now until needed in other places in lwIP */ +#ifndef isprint +#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up) +#define isprint(c) in_range(c, 0x20, 0x7f) +#define isdigit(c) in_range(c, '0', '9') +#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) +#define islower(c) in_range(c, 'a', 'z') +#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v') +#endif + +/* + * Ascii internet address interpretation routine. + * The value returned is in network order. + */ + +u32_t +inet_addr(const char *cp) +{ + struct in_addr val; + + if (inet_aton(cp, &val)) { + return (val.s_addr); + } + return (INADDR_NONE); +} + +/* + * Check whether "cp" is a valid ascii representation + * of an Internet address and convert to a binary address. + * Returns 1 if the address is valid, 0 if not. + * This replaces inet_addr, the return value from which + * cannot distinguish between failure and a local broadcast address. + */ +int +inet_aton(const char *cp, struct in_addr *addr) +{ + u32_t val; + int base, n, c; + u32_t parts[4]; + u32_t *pp = parts; + + c = *cp; + for (;;) { + /* + * Collect number up to ``.''. + * Values are specified as for C: + * 0x=hex, 0=octal, 1-9=decimal. + */ + if (!isdigit(c)) + return (0); + val = 0; + base = 10; + if (c == '0') { + c = *++cp; + if (c == 'x' || c == 'X') { + base = 16; + c = *++cp; + } else + base = 8; + } + for (;;) { + if (isdigit(c)) { + val = (val * base) + (int)(c - '0'); + c = *++cp; + } else if (base == 16 && isxdigit(c)) { + val = (val << 4) | (int)(c + 10 - (islower(c) ? 'a' : 'A')); + c = *++cp; + } else + break; + } + if (c == '.') { + /* + * Internet format: + * a.b.c.d + * a.b.c (with c treated as 16 bits) + * a.b (with b treated as 24 bits) + */ + if (pp >= parts + 3) + return (0); + *pp++ = val; + c = *++cp; + } else + break; + } + /* + * Check for trailing characters. + */ + if (c != '\0' && (!isprint(c) || !isspace(c))) + return (0); + /* + * Concoct the address according to + * the number of parts specified. + */ + n = pp - parts + 1; + switch (n) { + + case 0: + return (0); /* initial nondigit */ + + case 1: /* a -- 32 bits */ + break; + + case 2: /* a.b -- 8.24 bits */ + if (val > 0xffffff) + return (0); + val |= parts[0] << 24; + break; + + case 3: /* a.b.c -- 8.8.16 bits */ + if (val > 0xffff) + return (0); + val |= (parts[0] << 24) | (parts[1] << 16); + break; + + case 4: /* a.b.c.d -- 8.8.8.8 bits */ + if (val > 0xff) + return (0); + val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); + break; + } + if (addr) + addr->s_addr = htonl(val); + return (1); +} + +/* Convert numeric IP address into decimal dotted ASCII representation. + * returns ptr to static buffer; not reentrant! + */ +char * +inet_ntoa(struct in_addr addr) +{ + static char str[16]; + u32_t s_addr = addr.s_addr; + char inv[3]; + char *rp; + u8_t *ap; + u8_t rem; + u8_t n; + u8_t i; + + rp = str; + ap = (u8_t *)&s_addr; + for(n = 0; n < 4; n++) { + i = 0; + do { + rem = *ap % (u8_t)10; + *ap /= (u8_t)10; + inv[i++] = '0' + rem; + } while(*ap); + while(i--) + *rp++ = inv[i]; + *rp++ = '.'; + ap++; + } + *--rp = 0; + return str; +} + +/* + * These are reference implementations of the byte swapping functions. + * Again with the aim of being simple, correct and fully portable. + * Byte swapping is the second thing you would want to optimize. You will + * need to port it to your architecture and in your cc.h: + * + * #define LWIP_PLATFORM_BYTESWAP 1 + * #define LWIP_PLATFORM_HTONS(x) + * #define LWIP_PLATFORM_HTONL(x) + * + * Note ntohs() and ntohl() are merely references to the htonx counterparts. + */ + +#ifndef BYTE_ORDER +#error BYTE_ORDER is not defined +#endif +#if (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) + +u16_t +htons(u16_t n) +{ + return ((n & 0xff) << 8) | ((n & 0xff00) >> 8); +} + +u16_t +ntohs(u16_t n) +{ + return htons(n); +} + +u32_t +htonl(u32_t n) +{ + return ((n & 0xff) << 24) | + ((n & 0xff00) << 8) | + ((n & 0xff0000) >> 8) | + ((n & 0xff000000) >> 24); +} + +u32_t +ntohl(u32_t n) +{ + return htonl(n); +} + +#endif /* (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/inet6.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/inet6.c new file mode 100644 index 0000000..aebc6f3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/inet6.c @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +/* inet6.c + * + * Functions common to all TCP/IP modules, such as the Internet checksum and the + * byte order functions. + * + */ + + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/inet.h" + + + +/* chksum: + * + * Sums up all 16 bit words in a memory portion. Also includes any odd byte. + * This function is used by the other checksum functions. + * + * For now, this is not optimized. Must be optimized for the particular processor + * arcitecture on which it is to run. Preferebly coded in assembler. + */ + +static u32_t +chksum(void *dataptr, u16_t len) +{ + u16_t *sdataptr = dataptr; + u32_t acc; + + + for(acc = 0; len > 1; len -= 2) { + acc += *sdataptr++; + } + + /* add up any odd byte */ + if (len == 1) { + acc += htons((u16_t)(*(u8_t *)dataptr) << 8); + } + + return acc; + +} + +/* inet_chksum_pseudo: + * + * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. + */ + +u16_t +inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u32_t proto_len) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped, i; + + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { + acc += chksum(q->payload, q->len); + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); + } + } + + if (swapped) { + acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); + } + + for(i = 0; i < 8; i++) { + acc += ((u16_t *)src->addr)[i] & 0xffff; + acc += ((u16_t *)dest->addr)[i] & 0xffff; + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + } + acc += (u16_t)htons((u16_t)proto); + acc += ((u16_t *)&proto_len)[0] & 0xffff; + acc += ((u16_t *)&proto_len)[1] & 0xffff; + + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + return ~(acc & 0xffff); +} + +/* inet_chksum: + * + * Calculates the Internet checksum over a portion of memory. Used primarely for IP + * and ICMP. + */ + +u16_t +inet_chksum(void *dataptr, u16_t len) +{ + u32_t acc, sum; + + acc = chksum(dataptr, len); + sum = (acc & 0xffff) + (acc >> 16); + sum += (sum >> 16); + return ~(sum & 0xffff); +} + +u16_t +inet_chksum_pbuf(struct pbuf *p) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped; + + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { + acc += chksum(q->payload, q->len); + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8); + } + } + + if (swapped) { + acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); + } + return ~(acc & 0xffff); +} + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/icmp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/icmp.c new file mode 100644 index 0000000..e4028b1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/icmp.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* Some ICMP messages should be passed to the transport protocols. This + is not implemented. */ + +#include + +#include "lwip/opt.h" +#include "lwip/icmp.h" +#include "lwip/inet.h" +#include "lwip/ip.h" +#include "lwip/def.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +void +icmp_input(struct pbuf *p, struct netif *inp) +{ + u8_t type; + u8_t code; + struct icmp_echo_hdr *iecho; + struct ip_hdr *iphdr; + struct ip_addr tmpaddr; + u16_t hlen; + + ICMP_STATS_INC(icmp.recv); + snmp_inc_icmpinmsgs(); + + + iphdr = p->payload; + hlen = IPH_HL(iphdr) * 4; + if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); + pbuf_free(p); + ICMP_STATS_INC(icmp.lenerr); + snmp_inc_icmpinerrors(); + return; + } + + type = *((u8_t *)p->payload); + code = *(((u8_t *)p->payload)+1); + switch (type) { + case ICMP_ECHO: + /* broadcast or multicast destination address? */ + if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n")); + ICMP_STATS_INC(icmp.err); + pbuf_free(p); + return; + } + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); + if (p->tot_len < sizeof(struct icmp_echo_hdr)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); + pbuf_free(p); + ICMP_STATS_INC(icmp.lenerr); + snmp_inc_icmpinerrors(); + + return; + } + iecho = p->payload; + if (inet_chksum_pbuf(p) != 0) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); + pbuf_free(p); + ICMP_STATS_INC(icmp.chkerr); + snmp_inc_icmpinerrors(); + return; + } + tmpaddr.addr = iphdr->src.addr; + iphdr->src.addr = iphdr->dest.addr; + iphdr->dest.addr = tmpaddr.addr; + ICMPH_TYPE_SET(iecho, ICMP_ER); + /* adjust the checksum */ + if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) { + iecho->chksum += htons(ICMP_ECHO << 8) + 1; + } else { + iecho->chksum += htons(ICMP_ECHO << 8); + } + ICMP_STATS_INC(icmp.xmit); + /* increase number of messages attempted to send */ + snmp_inc_icmpoutmsgs(); + /* increase number of echo replies attempted to send */ + snmp_inc_icmpoutechoreps(); + + pbuf_header(p, hlen); + ip_output_if(p, &(iphdr->src), IP_HDRINCL, + IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp); + break; + default: + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code)); + ICMP_STATS_INC(icmp.proterr); + ICMP_STATS_INC(icmp.drop); + } + pbuf_free(p); +} + +void +icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) +{ + struct pbuf *q; + struct ip_hdr *iphdr; + struct icmp_dur_hdr *idur; + + q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); + /* ICMP header + IP header + 8 bytes of data */ + + iphdr = p->payload; + + idur = q->payload; + ICMPH_TYPE_SET(idur, ICMP_DUR); + ICMPH_CODE_SET(idur, t); + + memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8); + + /* calculate checksum */ + idur->chksum = 0; + idur->chksum = inet_chksum(idur, q->len); + ICMP_STATS_INC(icmp.xmit); + /* increase number of messages attempted to send */ + snmp_inc_icmpoutmsgs(); + /* increase number of destination unreachable messages attempted to send */ + snmp_inc_icmpoutdestunreachs(); + + ip_output(q, NULL, &(iphdr->src), + ICMP_TTL, 0, IP_PROTO_ICMP); + pbuf_free(q); +} + +#if IP_FORWARD +void +icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) +{ + struct pbuf *q; + struct ip_hdr *iphdr; + struct icmp_te_hdr *tehdr; + + q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); + + iphdr = p->payload; + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from ")); + ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src)); + LWIP_DEBUGF(ICMP_DEBUG, (" to ")); + ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest)); + LWIP_DEBUGF(ICMP_DEBUG, ("\n")); + + tehdr = q->payload; + ICMPH_TYPE_SET(tehdr, ICMP_TE); + ICMPH_CODE_SET(tehdr, t); + + /* copy fields from original packet */ + memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8); + + /* calculate checksum */ + tehdr->chksum = 0; + tehdr->chksum = inet_chksum(tehdr, q->len); + ICMP_STATS_INC(icmp.xmit); + /* increase number of messages attempted to send */ + snmp_inc_icmpoutmsgs(); + /* increase number of destination unreachable messages attempted to send */ + snmp_inc_icmpouttimeexcds(); + ip_output(q, NULL, &(iphdr->src), + ICMP_TTL, 0, IP_PROTO_ICMP); + pbuf_free(q); +} + +#endif /* IP_FORWARD */ + + + + + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/ip.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/ip.c new file mode 100644 index 0000000..31d29a9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/ip.c @@ -0,0 +1,515 @@ +/* @file + * + * This is the IP layer implementation for incoming and outgoing IP traffic. + * + * @see ip_frag.c + * + */ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/ip.h" +#include "lwip/ip_frag.h" +#include "lwip/inet.h" +#include "lwip/netif.h" +#include "lwip/icmp.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" + +#include "lwip/stats.h" + +#include "arch/perf.h" + +#include "lwip/snmp.h" +#if LWIP_DHCP +# include "lwip/dhcp.h" +#endif /* LWIP_DHCP */ + +/** + * Initializes the IP layer. + */ + +void +ip_init(void) +{ +#if IP_FRAG + ip_frag_init(); +#endif +} + +/** + * Finds the appropriate network interface for a given IP address. It + * searches the list of network interfaces linearly. A match is found + * if the masked IP address of the network interface equals the masked + * IP address given to the function. + */ + +struct netif * +ip_route(struct ip_addr *dest) +{ + struct netif *netif; + + /* iterate through netifs */ + for(netif = netif_list; netif != NULL; netif = netif->next) { + /* network mask matches? */ + if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { + /* return netif on which to forward IP packet */ + return netif; + } + } + /* no matching netif found, use default netif */ + return netif_default; +} +#if IP_FORWARD + +/** + * Forwards an IP packet. It finds an appropriate route for the + * packet, decrements the TTL value of the packet, adjusts the + * checksum and outputs the packet on the appropriate interface. + */ + +static struct netif * +ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp) +{ + struct netif *netif; + + PERF_START; + /* Find network interface where to forward this IP packet to. */ + netif = ip_route((struct ip_addr *)&(iphdr->dest)); + if (netif == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n", + iphdr->dest.addr)); + snmp_inc_ipoutnoroutes(); + return (struct netif *)NULL; + } + /* Do not forward packets onto the same network interface on which + * they arrived. */ + if (netif == inp) { + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n")); + snmp_inc_ipoutnoroutes(); + return (struct netif *)NULL; + } + + /* decrement TTL */ + IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1); + /* send ICMP if TTL == 0 */ + if (IPH_TTL(iphdr) == 0) { + snmp_inc_ipinhdrerrors(); + /* Don't send ICMP messages in response to ICMP messages */ + if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) { + icmp_time_exceeded(p, ICMP_TE_TTL); + } + return (struct netif *)NULL; + } + + /* Incrementally update the IP checksum. */ + if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) { + IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1); + } else { + IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100)); + } + + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n", + iphdr->dest.addr)); + + IP_STATS_INC(ip.fw); + IP_STATS_INC(ip.xmit); + snmp_inc_ipforwdatagrams(); + + PERF_STOP("ip_forward"); + /* transmit pbuf on chosen interface */ + netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); + return netif; +} +#endif /* IP_FORWARD */ + +/** + * This function is called by the network interface device driver when + * an IP packet is received. The function does the basic checks of the + * IP header such as packet size being at least larger than the header + * size etc. If the packet was not destined for us, the packet is + * forwarded (using ip_forward). The IP checksum is always checked. + * + * Finally, the packet is sent to the upper layer protocol input function. + * + * + * + */ + +err_t +ip_input(struct pbuf *p, struct netif *inp) { + struct ip_hdr *iphdr; + struct netif *netif; + u16_t iphdrlen; + + IP_STATS_INC(ip.recv); + snmp_inc_ipinreceives(); + + /* identify the IP header */ + iphdr = p->payload; + if (IPH_V(iphdr) != 4) { + LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr))); + ip_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.err); + IP_STATS_INC(ip.drop); + snmp_inc_ipinhdrerrors(); + return ERR_OK; + } + /* obtain IP header length in number of 32-bit words */ + iphdrlen = IPH_HL(iphdr); + /* calculate IP header length in bytes */ + iphdrlen *= 4; + + /* header length exceeds first pbuf length? */ + if (iphdrlen > p->len) { + LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet droppped.\n", + iphdrlen, p->len)); + /* free (drop) packet pbufs */ + pbuf_free(p); + IP_STATS_INC(ip.lenerr); + IP_STATS_INC(ip.drop); + snmp_inc_ipindiscards(); + return ERR_OK; + } + + /* verify checksum */ +#if CHECKSUM_CHECK_IP + if (inet_chksum(iphdr, iphdrlen) != 0) { + + LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen))); + ip_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.chkerr); + IP_STATS_INC(ip.drop); + snmp_inc_ipinhdrerrors(); + return ERR_OK; + } +#endif + + /* Trim pbuf. This should have been done at the netif layer, + * but we'll do it anyway just to be sure that its done. */ + pbuf_realloc(p, ntohs(IPH_LEN(iphdr))); + + /* match packet against an interface, i.e. is this packet for us? */ + for (netif = netif_list; netif != NULL; netif = netif->next) { + + LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n", + iphdr->dest.addr, netif->ip_addr.addr, + iphdr->dest.addr & netif->netmask.addr, + netif->ip_addr.addr & netif->netmask.addr, + iphdr->dest.addr & ~(netif->netmask.addr))); + + /* interface is up and configured? */ + if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) + { + /* unicast to this interface address? */ + if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) || + /* or broadcast on this interface network address? */ + ip_addr_isbroadcast(&(iphdr->dest), netif)) { + LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n", + netif->name[0], netif->name[1])); + /* break out of for loop */ + break; + } + } + } +#if LWIP_DHCP + /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed + * using link layer addressing (such as Ethernet MAC) so we must not filter on IP. + * According to RFC 1542 section 3.1.1, referred by RFC 2131). + */ + if (netif == NULL) { + /* remote port is DHCP server? */ + if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { + LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n", + ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest))); + if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) { + LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n")); + netif = inp; + } + } + } +#endif /* LWIP_DHCP */ + /* packet not for us? */ + if (netif == NULL) { + /* packet not for us, route or discard */ + LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n")); +#if IP_FORWARD + /* non-broadcast packet? */ + if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) { + /* try to forward IP packet on (other) interfaces */ + ip_forward(p, iphdr, inp); + } + else +#endif /* IP_FORWARD */ + { + snmp_inc_ipinaddrerrors(); + snmp_inc_ipindiscards(); + } + pbuf_free(p); + return ERR_OK; + } + /* packet consists of multiple fragments? */ + if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) { +#if IP_REASSEMBLY /* packet fragment reassembly code present? */ + LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n", + ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8)); + /* reassemble the packet*/ + p = ip_reass(p); + /* packet not fully reassembled yet? */ + if (p == NULL) { + return ERR_OK; + } + iphdr = p->payload; +#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */ + pbuf_free(p); + LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n", + ntohs(IPH_OFFSET(iphdr)))); + IP_STATS_INC(ip.opterr); + IP_STATS_INC(ip.drop); + /* unsupported protocol feature */ + snmp_inc_ipinunknownprotos(); + return ERR_OK; +#endif /* IP_REASSEMBLY */ + } + +#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */ + if (iphdrlen > IP_HLEN) { + LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n")); + pbuf_free(p); + IP_STATS_INC(ip.opterr); + IP_STATS_INC(ip.drop); + /* unsupported protocol feature */ + snmp_inc_ipinunknownprotos(); + return ERR_OK; + } +#endif /* IP_OPTIONS == 0 */ + + /* send to upper layers */ + LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n")); + ip_debug_print(p); + LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); + +#if LWIP_RAW + /* raw input did not eat the packet? */ + if (raw_input(p, inp) == 0) { +#endif /* LWIP_RAW */ + + switch (IPH_PROTO(iphdr)) { +#if LWIP_UDP + case IP_PROTO_UDP: + case IP_PROTO_UDPLITE: + snmp_inc_ipindelivers(); + udp_input(p, inp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case IP_PROTO_TCP: + snmp_inc_ipindelivers(); + tcp_input(p, inp); + break; +#endif /* LWIP_TCP */ + case IP_PROTO_ICMP: + snmp_inc_ipindelivers(); + icmp_input(p, inp); + break; + default: + /* send ICMP destination protocol unreachable unless is was a broadcast */ + if (!ip_addr_isbroadcast(&(iphdr->dest), inp) && + !ip_addr_ismulticast(&(iphdr->dest))) { + p->payload = iphdr; + icmp_dest_unreach(p, ICMP_DUR_PROTO); + } + pbuf_free(p); + + LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr))); + + IP_STATS_INC(ip.proterr); + IP_STATS_INC(ip.drop); + snmp_inc_ipinunknownprotos(); + } +#if LWIP_RAW + } /* LWIP_RAW */ +#endif + return ERR_OK; +} + +/** + * Sends an IP packet on a network interface. This function constructs + * the IP header and calculates the IP header checksum. If the source + * IP address is NULL, the IP address of the outgoing network + * interface is filled in as source address. + * + * @note ip_id: RFC791 "some host may be able to simply use + * unique identifiers independent of destination" + */ + +err_t +ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) +{ + struct ip_hdr *iphdr; + static u16_t ip_id = 0; + + snmp_inc_ipoutrequests(); + + if (dest != IP_HDRINCL) { + if (pbuf_header(p, IP_HLEN)) { + LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n")); + + IP_STATS_INC(ip.err); + snmp_inc_ipoutdiscards(); + return ERR_BUF; + } + + iphdr = p->payload; + + IPH_TTL_SET(iphdr, ttl); + IPH_PROTO_SET(iphdr, proto); + + ip_addr_set(&(iphdr->dest), dest); + + IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos); + IPH_LEN_SET(iphdr, htons(p->tot_len)); + IPH_OFFSET_SET(iphdr, htons(IP_DF)); + IPH_ID_SET(iphdr, htons(ip_id)); + ++ip_id; + + if (ip_addr_isany(src)) { + ip_addr_set(&(iphdr->src), &(netif->ip_addr)); + } else { + ip_addr_set(&(iphdr->src), src); + } + + IPH_CHKSUM_SET(iphdr, 0); +#if CHECKSUM_GEN_IP + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); +#endif + } else { + iphdr = p->payload; + dest = &(iphdr->dest); + } + +#if IP_FRAG + /* don't fragment if interface has mtu set to 0 [loopif] */ + if (netif->mtu && (p->tot_len > netif->mtu)) + return ip_frag(p,netif,dest); +#endif + + IP_STATS_INC(ip.xmit); + + LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num)); + ip_debug_print(p); + + LWIP_DEBUGF(IP_DEBUG, ("netif->output()")); + + return netif->output(netif, p, dest); +} + +/** + * Simple interface to ip_output_if. It finds the outgoing network + * interface and calls upon ip_output_if to do the actual work. + */ + +err_t +ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto) +{ + struct netif *netif; + + if ((netif = ip_route(dest)) == NULL) { + LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); + + IP_STATS_INC(ip.rterr); + snmp_inc_ipoutnoroutes(); + return ERR_RTE; + } + + return ip_output_if(p, src, dest, ttl, tos, proto, netif); +} + +#if IP_DEBUG +void +ip_debug_print(struct pbuf *p) +{ + struct ip_hdr *iphdr = p->payload; + u8_t *payload; + + payload = (u8_t *)iphdr + IP_HLEN; + + LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n", + IPH_V(iphdr), + IPH_HL(iphdr), + IPH_TOS(iphdr), + ntohs(IPH_LEN(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n", + ntohs(IPH_ID(iphdr)), + ntohs(IPH_OFFSET(iphdr)) >> 15 & 1, + ntohs(IPH_OFFSET(iphdr)) >> 14 & 1, + ntohs(IPH_OFFSET(iphdr)) >> 13 & 1, + ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n", + IPH_TTL(iphdr), + IPH_PROTO(iphdr), + ntohs(IPH_CHKSUM(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n", + ip4_addr1(&iphdr->src), + ip4_addr2(&iphdr->src), + ip4_addr3(&iphdr->src), + ip4_addr4(&iphdr->src))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n", + ip4_addr1(&iphdr->dest), + ip4_addr2(&iphdr->dest), + ip4_addr3(&iphdr->dest), + ip4_addr4(&iphdr->dest))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* IP_DEBUG */ + + + + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/ip_addr.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/ip_addr.c new file mode 100644 index 0000000..56b1cd7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/ip_addr.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/ip_addr.h" +#include "lwip/inet.h" +#include "lwip/netif.h" + +#define IP_ADDR_ANY_VALUE 0x00000000UL +#define IP_ADDR_BROADCAST_VALUE 0xffffffffUL + +/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */ +const struct ip_addr ip_addr_any = { IP_ADDR_ANY_VALUE }; +const struct ip_addr ip_addr_broadcast = { IP_ADDR_BROADCAST_VALUE }; + +/* Determine if an address is a broadcast address on a network interface + * + * @param addr address to be checked + * @param netif the network interface against which the address is checked + * @return returns non-zero if the address is a broadcast address + * + */ + +u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif) +{ + u32_t addr2test; + + addr2test = addr->addr; + /* all ones (broadcast) or all zeroes (old skool broadcast) */ + if ((~addr2test == IP_ADDR_ANY_VALUE) || + (addr2test == IP_ADDR_ANY_VALUE)) + return 1; + /* no broadcast support on this network interface? */ + else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) + /* the given address cannot be a broadcast address + * nor can we check against any broadcast addresses */ + return 0; + /* address matches network interface address exactly? => no broadcast */ + else if (addr2test == netif->ip_addr.addr) + return 0; + /* on the same (sub) network... */ + else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask)) + /* ...and host identifier bits are all ones? =>... */ + && ((addr2test & ~netif->netmask.addr) == + (IP_ADDR_BROADCAST_VALUE & ~netif->netmask.addr))) + /* => network broadcast address */ + return 1; + else + return 0; +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/ip_frag.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/ip_frag.c new file mode 100644 index 0000000..0256a50 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/ipv4/ip_frag.c @@ -0,0 +1,388 @@ +/* @file + * + * This is the IP packet segmentation and reassembly implementation. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * original reassembly code by Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" +#include "lwip/ip.h" +#include "lwip/ip_frag.h" +#include "lwip/netif.h" +#include "lwip/snmp.h" +#include "lwip/stats.h" + +static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE]; +static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8) + 1]; +static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f, + 0x0f, 0x07, 0x03, 0x01 +}; +static u16_t ip_reasslen; +static u8_t ip_reassflags; +#define IP_REASS_FLAG_LASTFRAG 0x01 + +static u8_t ip_reasstmr; + +/* + * Copy len bytes from offset in pbuf to buffer + * + * helper used by both ip_reass and ip_frag + */ +static struct pbuf * +copy_from_pbuf(struct pbuf *p, u16_t * offset, + u8_t * buffer, u16_t len) +{ + u16_t l; + + p->payload = (u8_t *)p->payload + *offset; + p->len -= *offset; + while (len) { + l = len < p->len ? len : p->len; + memcpy(buffer, p->payload, l); + buffer += l; + len -= l; + if (len) + p = p->next; + else + *offset = l; + } + return p; +} + + +/** + * Initializes IP reassembly and fragmentation states. + */ +void +ip_frag_init(void) +{ + ip_reasstmr = 0; + ip_reassflags = 0; + ip_reasslen = 0; + memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap)); +} + +/** + * Reassembly timer base function + * for both NO_SYS == 0 and 1 (!). + * + * Should be called every 1000 msec. + */ +void +ip_reass_tmr(void) +{ + if (ip_reasstmr > 0) { + ip_reasstmr--; + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n",(u16_t)ip_reasstmr)); + if (ip_reasstmr == 0) { + /* reassembly timed out */ + snmp_inc_ipreasmfails(); + } + } +} + +/** + * Reassembles incoming IP fragments into an IP datagram. + * + * @param p points to a pbuf chain of the fragment + * @return NULL if reassembly is incomplete, ? otherwise + */ +struct pbuf * +ip_reass(struct pbuf *p) +{ + struct pbuf *q; + struct ip_hdr *fraghdr, *iphdr; + u16_t offset, len; + u16_t i; + + IPFRAG_STATS_INC(ip_frag.recv); + snmp_inc_ipreasmreqds(); + + iphdr = (struct ip_hdr *) ip_reassbuf; + fraghdr = (struct ip_hdr *) p->payload; + /* If ip_reasstmr is zero, no packet is present in the buffer, so we + write the IP header of the fragment into the reassembly + buffer. The timer is updated with the maximum age. */ + if (ip_reasstmr == 0) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n")); + memcpy(iphdr, fraghdr, IP_HLEN); + ip_reasstmr = IP_REASS_MAXAGE; + ip_reassflags = 0; + /* Clear the bitmap. */ + memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap)); + } + + /* Check if the incoming fragment matches the one currently present + in the reasembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if (ip_addr_cmp(&iphdr->src, &fraghdr->src) && + ip_addr_cmp(&iphdr->dest, &fraghdr->dest) && + IPH_ID(iphdr) == IPH_ID(fraghdr)) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n", + ntohs(IPH_ID(fraghdr)))); + IPFRAG_STATS_INC(ip_frag.cachehit); + /* Find out the offset in the reassembly buffer where we should + copy the fragment. */ + len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4; + offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8; + + /* If the offset or the offset + fragment length overflows the + reassembly buffer, we discard the entire packet. */ + if ((offset > IP_REASS_BUFSIZE) || ((offset + len) > IP_REASS_BUFSIZE)) { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: fragment outside of buffer (%"S16_F":%"S16_F"/%"S16_F").\n", offset, + offset + len, IP_REASS_BUFSIZE)); + ip_reasstmr = 0; + snmp_inc_ipreasmfails(); + goto nullreturn; + } + + /* Copy the fragment into the reassembly buffer, at the right + offset. */ + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: copying with offset %"S16_F" into %"S16_F":%"S16_F"\n", offset, + IP_HLEN + offset, IP_HLEN + offset + len)); + i = IPH_HL(fraghdr) * 4; + copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len); + + /* Update the bitmap. */ + if (offset / (8 * 8) == (offset + len) / (8 * 8)) { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: updating single byte in bitmap.\n")); + /* If the two endpoints are in the same byte, we only update that byte. */ + LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", + offset / (8 * 8) < sizeof(ip_reassbitmap)); + ip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8) & 7] & + ~bitmap_bits[((offset + len) / 8) & 7]; + } else { + /* If the two endpoints are in different bytes, we update the + bytes in the endpoints and fill the stuff inbetween with + 0xff. */ + LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", + offset / (8 * 8) < sizeof(ip_reassbitmap)); + ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7]; + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: updating many bytes in bitmap (%"S16_F":%"S16_F").\n", + 1 + offset / (8 * 8), (offset + len) / (8 * 8))); + for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { + ip_reassbitmap[i] = 0xff; + } + LWIP_ASSERT("(offset + len) / (8 * 8) < sizeof(ip_reassbitmap)", + (offset + len) / (8 * 8) < sizeof(ip_reassbitmap)); + ip_reassbitmap[(offset + len) / (8 * 8)] |= + ~bitmap_bits[((offset + len) / 8) & 7]; + } + + /* If this fragment has the More Fragments flag set to zero, we + know that this is the last fragment, so we can calculate the + size of the entire packet. We also set the + IP_REASS_FLAG_LASTFRAG flag to indicate that we have received + the final fragment. */ + + if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) { + ip_reassflags |= IP_REASS_FLAG_LASTFRAG; + ip_reasslen = offset + len; + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: last fragment seen, total len %"S16_F"\n", + ip_reasslen)); + } + + /* Finally, we check if we have a full packet in the buffer. We do + this by checking if we have the last fragment and if all bits + in the bitmap are set. */ + if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) { + /* Check all bytes up to and including all but the last byte in + the bitmap. */ + LWIP_ASSERT("ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)", + ip_reasslen / (8 * 8) - 1 < ((u16_t) sizeof(ip_reassbitmap))); + for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) { + if (ip_reassbitmap[i] != 0xff) { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: last fragment seen, bitmap %"S16_F"/%"S16_F" failed (%"X16_F")\n", + i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i])); + goto nullreturn; + } + } + /* Check the last byte in the bitmap. It should contain just the + right amount of bits. */ + LWIP_ASSERT("ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)", + ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)); + if (ip_reassbitmap[ip_reasslen / (8 * 8)] != + (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: last fragment seen, bitmap %"S16_F" didn't contain %"X16_F" (%"X16_F")\n", + ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7], + ip_reassbitmap[ip_reasslen / (8 * 8)])); + goto nullreturn; + } + + /* Pretend to be a "normal" (i.e., not fragmented) IP packet + from now on. */ + ip_reasslen += IP_HLEN; + + IPH_LEN_SET(iphdr, htons(ip_reasslen)); + IPH_OFFSET_SET(iphdr, 0); + IPH_CHKSUM_SET(iphdr, 0); + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); + + /* If we have come this far, we have a full packet in the + buffer, so we allocate a pbuf and copy the packet into it. We + also reset the timer. */ + ip_reasstmr = 0; + pbuf_free(p); + p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL); + if (p != NULL) { + i = 0; + for (q = p; q != NULL; q = q->next) { + /* Copy enough bytes to fill this pbuf in the chain. The + available data in the pbuf is given by the q->len variable. */ + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: memcpy from %p (%"S16_F") to %p, %"S16_F" bytes\n", + (void *)&ip_reassbuf[i], i, q->payload, + q->len > ip_reasslen - i ? ip_reasslen - i : q->len)); + memcpy(q->payload, &ip_reassbuf[i], + q->len > ip_reasslen - i ? ip_reasslen - i : q->len); + i += q->len; + } + IPFRAG_STATS_INC(ip_frag.fw); + snmp_inc_ipreasmoks(); + } else { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: pbuf_alloc(PBUF_LINK, ip_reasslen=%"U16_F", PBUF_POOL) failed\n", ip_reasslen)); + IPFRAG_STATS_INC(ip_frag.memerr); + snmp_inc_ipreasmfails(); + } + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p)); + return p; + } + } + +nullreturn: + IPFRAG_STATS_INC(ip_frag.drop); + pbuf_free(p); + return NULL; +} + +static u8_t buf[MEM_ALIGN_SIZE(IP_FRAG_MAX_MTU)]; + +/** + * Fragment an IP datagram if too large for the netif. + * + * Chop the datagram in MTU sized chunks and send them in order + * by using a fixed size static memory buffer (PBUF_ROM) + */ +err_t +ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest) +{ + struct pbuf *rambuf; + struct pbuf *header; + struct ip_hdr *iphdr; + u16_t nfb = 0; + u16_t left, cop; + u16_t mtu = netif->mtu; + u16_t ofo, omf; + u16_t last; + u16_t poff = IP_HLEN; + u16_t tmp; + + /* Get a RAM based MTU sized pbuf */ + rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF); + if (rambuf == NULL) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc(PBUF_LINK, 0, PBUF_REF) failed\n")); + return ERR_MEM; + } + rambuf->tot_len = rambuf->len = mtu; + rambuf->payload = MEM_ALIGN((void *)buf); + + /* Copy the IP header in it */ + iphdr = rambuf->payload; + memcpy(iphdr, p->payload, IP_HLEN); + + /* Save original offset */ + tmp = ntohs(IPH_OFFSET(iphdr)); + ofo = tmp & IP_OFFMASK; + omf = tmp & IP_MF; + + left = p->tot_len - IP_HLEN; + + while (left) { + last = (left <= mtu - IP_HLEN); + + /* Set new offset and MF flag */ + ofo += nfb; + tmp = omf | (IP_OFFMASK & (ofo)); + if (!last) + tmp = tmp | IP_MF; + IPH_OFFSET_SET(iphdr, htons(tmp)); + + /* Fill this fragment */ + nfb = (mtu - IP_HLEN) / 8; + cop = last ? left : nfb * 8; + + p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop); + + /* Correct header */ + IPH_LEN_SET(iphdr, htons(cop + IP_HLEN)); + IPH_CHKSUM_SET(iphdr, 0); + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); + + if (last) + pbuf_realloc(rambuf, left + IP_HLEN); + /* This part is ugly: we alloc a RAM based pbuf for + * the link level header for each chunk and then + * free it.A PBUF_ROM style pbuf for which pbuf_header + * worked would make things simpler. + */ + header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM); + if (header != NULL) { + pbuf_chain(header, rambuf); + netif->output(netif, header, dest); + IPFRAG_STATS_INC(ip_frag.xmit); + snmp_inc_ipfragcreates(); + pbuf_free(header); + } else { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc() for header failed\n")); + pbuf_free(rambuf); + return ERR_MEM; + } + left -= cop; + } + pbuf_free(rambuf); + snmp_inc_ipfragoks(); + return ERR_OK; +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/mem.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/mem.c new file mode 100644 index 0000000..4d4cb1d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/mem.c @@ -0,0 +1,414 @@ +/** @file + * + * Dynamic memory manager + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/arch.h" +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" + +#include "lwip/sys.h" + +#include "lwip/stats.h" + +#if (MEM_LIBC_MALLOC == 0) +/* lwIP replacement for your libc malloc() */ + +struct mem { + mem_size_t next, prev; +#if MEM_ALIGNMENT == 1 + u8_t used; +#elif MEM_ALIGNMENT == 2 + u16_t used; +#elif MEM_ALIGNMENT == 4 + u32_t used; +#elif MEM_ALIGNMENT == 8 + u64_t used; +#else +#error "unhandled MEM_ALIGNMENT size" +#endif /* MEM_ALIGNMENT */ +}; + +static struct mem *ram_end; +#if 1 +/* Adam original */ +static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT]; +#else +/* Christiaan alignment fix */ +static u8_t *ram; +static struct mem ram_heap[1 + ( (MEM_SIZE + sizeof(struct mem) - 1) / sizeof(struct mem))]; +#endif + +#define MIN_SIZE 12 +#if 0 /* this one does not align correctly for some, resulting in crashes */ +#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem)) +#else +#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \ + (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \ + (4 - (sizeof(struct mem) % MEM_ALIGNMENT)))) +#endif + +static struct mem *lfree; /* pointer to the lowest free block */ + +static sys_sem_t mem_sem; + +static void +plug_holes(struct mem *mem) +{ + struct mem *nmem; + struct mem *pmem; + + LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); + LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); + LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); + + /* plug hole forward */ + LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE); + + nmem = (struct mem *)&ram[mem->next]; + if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { + if (lfree == nmem) { + lfree = mem; + } + mem->next = nmem->next; + ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram; + } + + /* plug hole backward */ + pmem = (struct mem *)&ram[mem->prev]; + if (pmem != mem && pmem->used == 0) { + if (lfree == mem) { + lfree = pmem; + } + pmem->next = mem->next; + ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram; + } +} + +void +mem_init(void) +{ + struct mem *mem; + +#if 1 + /* Adam original */ +#else + /* Christiaan alignment fix */ + ram = (u8_t*)ram_heap; +#endif + memset(ram, 0, MEM_SIZE); + mem = (struct mem *)ram; + mem->next = MEM_SIZE; + mem->prev = 0; + mem->used = 0; + ram_end = (struct mem *)&ram[MEM_SIZE]; + ram_end->used = 1; + ram_end->next = MEM_SIZE; + ram_end->prev = MEM_SIZE; + + mem_sem = sys_sem_new(1); + + lfree = (struct mem *)ram; + +#if MEM_STATS + lwip_stats.mem.avail = MEM_SIZE; +#endif /* MEM_STATS */ +} + +void +mem_free(void *rmem) +{ + struct mem *mem; + + if (rmem == NULL) { + LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n")); + return; + } + + sys_sem_wait(mem_sem); + + LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram && + (u8_t *)rmem < (u8_t *)ram_end); + + if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { + LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n")); +#if MEM_STATS + ++lwip_stats.mem.err; +#endif /* MEM_STATS */ + sys_sem_signal(mem_sem); + return; + } + mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); + + LWIP_ASSERT("mem_free: mem->used", mem->used); + + mem->used = 0; + + if (mem < lfree) { + lfree = mem; + } + +#if MEM_STATS + lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram); + +#endif /* MEM_STATS */ + plug_holes(mem); + sys_sem_signal(mem_sem); +} + +void * +mem_realloc(void *rmem, mem_size_t newsize) +{ + mem_size_t size; + mem_size_t ptr, ptr2; + struct mem *mem, *mem2; + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + if ((newsize % MEM_ALIGNMENT) != 0) { + newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); + } + + if (newsize > MEM_SIZE) { + return NULL; + } + + sys_sem_wait(mem_sem); + + LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram && + (u8_t *)rmem < (u8_t *)ram_end); + + if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { + LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n")); + return rmem; + } + mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); + + ptr = (u8_t *)mem - ram; + + size = mem->next - ptr - SIZEOF_STRUCT_MEM; +#if MEM_STATS + lwip_stats.mem.used -= (size - newsize); +#endif /* MEM_STATS */ + + if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) { + ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; + mem2 = (struct mem *)&ram[ptr2]; + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; + mem->next = ptr2; + if (mem2->next != MEM_SIZE) { + ((struct mem *)&ram[mem2->next])->prev = ptr2; + } + + plug_holes(mem2); + } + sys_sem_signal(mem_sem); + return rmem; +} + +#if 1 +/** + * Adam's mem_malloc(), suffers from bug #17922 + * Set if to 0 for alternative mem_malloc(). + */ +void * +mem_malloc(mem_size_t size) +{ + mem_size_t ptr, ptr2; + struct mem *mem, *mem2; + + if (size == 0) { + return NULL; + } + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + if ((size % MEM_ALIGNMENT) != 0) { + size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); + } + + if (size > MEM_SIZE) { + return NULL; + } + + sys_sem_wait(mem_sem); + + for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) { + mem = (struct mem *)&ram[ptr]; + if (!mem->used && + mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) { + ptr2 = ptr + SIZEOF_STRUCT_MEM + size; + mem2 = (struct mem *)&ram[ptr2]; + + mem2->prev = ptr; + mem2->next = mem->next; + mem->next = ptr2; + if (mem2->next != MEM_SIZE) { + ((struct mem *)&ram[mem2->next])->prev = ptr2; + } + + mem2->used = 0; + mem->used = 1; +#if MEM_STATS + lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM); + /* if (lwip_stats.mem.max < lwip_stats.mem.used) { + lwip_stats.mem.max = lwip_stats.mem.used; + } */ + if (lwip_stats.mem.max < ptr2) { + lwip_stats.mem.max = ptr2; + } +#endif /* MEM_STATS */ + + if (mem == lfree) { + /* Find next free block after mem */ + while (lfree->used && lfree != ram_end) { + lfree = (struct mem *)&ram[lfree->next]; + } + LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used); + } + sys_sem_signal(mem_sem); + LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", + (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); + LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", + (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); + return (u8_t *)mem + SIZEOF_STRUCT_MEM; + } + } + LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); +#if MEM_STATS + ++lwip_stats.mem.err; +#endif /* MEM_STATS */ + sys_sem_signal(mem_sem); + return NULL; +} +#else +/** + * Adam's mem_malloc() plus solution for bug #17922 + */ +void * +mem_malloc(mem_size_t size) +{ + mem_size_t ptr, ptr2; + struct mem *mem, *mem2; + + if (size == 0) { + return NULL; + } + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + if ((size % MEM_ALIGNMENT) != 0) { + size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); + } + + if (size > MEM_SIZE) { + return NULL; + } + + sys_sem_wait(mem_sem); + + for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE - size; ptr = ((struct mem *)&ram[ptr])->next) { + mem = (struct mem *)&ram[ptr]; + + if (!mem->used) { + + ptr2 = ptr + SIZEOF_STRUCT_MEM + size; + + if (mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) >= size) { + /* split large block, create empty remainder */ + mem->next = ptr2; + mem->used = 1; + /* create mem2 struct */ + mem2 = (struct mem *)&ram[ptr2]; + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; + + if (mem2->next != MEM_SIZE) { + ((struct mem *)&ram[mem2->next])->prev = ptr2; + } + } + else if (mem->next - (ptr + SIZEOF_STRUCT_MEM) > size) { + /* near fit, no split, no mem2 creation, + round up to mem->next */ + ptr2 = mem->next; + mem->used = 1; + } + else if (mem->next - (ptr + SIZEOF_STRUCT_MEM) == size) { + /* exact fit, do not split, no mem2 creation */ + mem->next = ptr2; + mem->used = 1; + } + + if (mem->used) { +#if MEM_STATS + lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM); + if (lwip_stats.mem.max < ptr2) { + lwip_stats.mem.max = ptr2; + } +#endif /* MEM_STATS */ + if (mem == lfree) { + /* Find next free block after mem */ + while (lfree->used && lfree != ram_end) { + lfree = (struct mem *)&ram[lfree->next]; + } + LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used); + } + sys_sem_signal(mem_sem); + LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", + (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); + LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", + (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); + return (u8_t *)mem + SIZEOF_STRUCT_MEM; + } + } + } + LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); +#if MEM_STATS + ++lwip_stats.mem.err; +#endif /* MEM_STATS */ + sys_sem_signal(mem_sem); + return NULL; +} +#endif + +#endif /* MEM_LIBC_MALLOC == 0 */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/memp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/memp.c new file mode 100644 index 0000000..3912009 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/memp.c @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/memp.h" + +#include "lwip/pbuf.h" +#include "lwip/udp.h" +#include "lwip/raw.h" +#include "lwip/tcp.h" +#include "lwip/api.h" +#include "lwip/api_msg.h" +#include "lwip/tcpip.h" + +#include "lwip/sys.h" +#include "lwip/stats.h" + +struct memp { + struct memp *next; +}; + +#define MEMP_SIZE MEM_ALIGN_SIZE(sizeof(struct memp)) + +static struct memp *memp_tab[MEMP_MAX]; + +static const u16_t memp_sizes[MEMP_MAX] = { + MEM_ALIGN_SIZE(sizeof(struct pbuf)), + MEM_ALIGN_SIZE(sizeof(struct raw_pcb)), + MEM_ALIGN_SIZE(sizeof(struct udp_pcb)), + MEM_ALIGN_SIZE(sizeof(struct tcp_pcb)), + MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen)), + MEM_ALIGN_SIZE(sizeof(struct tcp_seg)), + MEM_ALIGN_SIZE(sizeof(struct netbuf)), + MEM_ALIGN_SIZE(sizeof(struct netconn)), + MEM_ALIGN_SIZE(sizeof(struct api_msg)), + MEM_ALIGN_SIZE(sizeof(struct tcpip_msg)), + MEM_ALIGN_SIZE(sizeof(struct sys_timeo)) +}; + +static const u16_t memp_num[MEMP_MAX] = { + MEMP_NUM_PBUF, + MEMP_NUM_RAW_PCB, + MEMP_NUM_UDP_PCB, + MEMP_NUM_TCP_PCB, + MEMP_NUM_TCP_PCB_LISTEN, + MEMP_NUM_TCP_SEG, + MEMP_NUM_NETBUF, + MEMP_NUM_NETCONN, + MEMP_NUM_API_MSG, + MEMP_NUM_TCPIP_MSG, + MEMP_NUM_SYS_TIMEOUT +}; + +#define MEMP_TYPE_SIZE(qty, type) \ + ((qty) * (MEMP_SIZE + MEM_ALIGN_SIZE(sizeof(type)))) + +static u8_t memp_memory[MEM_ALIGNMENT - 1 + + MEMP_TYPE_SIZE(MEMP_NUM_PBUF, struct pbuf) + + MEMP_TYPE_SIZE(MEMP_NUM_RAW_PCB, struct raw_pcb) + + MEMP_TYPE_SIZE(MEMP_NUM_UDP_PCB, struct udp_pcb) + + MEMP_TYPE_SIZE(MEMP_NUM_TCP_PCB, struct tcp_pcb) + + MEMP_TYPE_SIZE(MEMP_NUM_TCP_PCB_LISTEN, struct tcp_pcb_listen) + + MEMP_TYPE_SIZE(MEMP_NUM_TCP_SEG, struct tcp_seg) + + MEMP_TYPE_SIZE(MEMP_NUM_NETBUF, struct netbuf) + + MEMP_TYPE_SIZE(MEMP_NUM_NETCONN, struct netconn) + + MEMP_TYPE_SIZE(MEMP_NUM_API_MSG, struct api_msg) + + MEMP_TYPE_SIZE(MEMP_NUM_TCPIP_MSG, struct tcpip_msg) + + MEMP_TYPE_SIZE(MEMP_NUM_SYS_TIMEOUT, struct sys_timeo)]; + +#if !SYS_LIGHTWEIGHT_PROT +static sys_sem_t mutex; +#endif + +#if MEMP_SANITY_CHECK +static int +memp_sanity(void) +{ + s16_t i, c; + struct memp *m, *n; + + for (i = 0; i < MEMP_MAX; i++) { + for (m = memp_tab[i]; m != NULL; m = m->next) { + c = 1; + for (n = memp_tab[i]; n != NULL; n = n->next) { + if (n == m && --c < 0) { + return 0; /* LW was: abort(); */ + } + } + } + } + return 1; +} +#endif /* MEMP_SANITY_CHECK*/ + +void +memp_init(void) +{ + struct memp *memp; + u16_t i, j; + +#if MEMP_STATS + for (i = 0; i < MEMP_MAX; ++i) { + lwip_stats.memp[i].used = lwip_stats.memp[i].max = + lwip_stats.memp[i].err = 0; + lwip_stats.memp[i].avail = memp_num[i]; + } +#endif /* MEMP_STATS */ + + memp = MEM_ALIGN(memp_memory); + for (i = 0; i < MEMP_MAX; ++i) { + memp_tab[i] = NULL; + for (j = 0; j < memp_num[i]; ++j) { + memp->next = memp_tab[i]; + memp_tab[i] = memp; + memp = (struct memp *)((u8_t *)memp + MEMP_SIZE + memp_sizes[i]); + } + } + +#if !SYS_LIGHTWEIGHT_PROT + mutex = sys_sem_new(1); +#endif +} + +void * +memp_malloc(memp_t type) +{ + struct memp *memp; + void *mem; +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_DECL_PROTECT(old_level); +#endif + + LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX); + +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_PROTECT(old_level); +#else /* SYS_LIGHTWEIGHT_PROT */ + sys_sem_wait(mutex); +#endif /* SYS_LIGHTWEIGHT_PROT */ + + memp = memp_tab[type]; + + if (memp != NULL) { + memp_tab[type] = memp->next; + memp->next = NULL; +#if MEMP_STATS + ++lwip_stats.memp[type].used; + if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) { + lwip_stats.memp[type].max = lwip_stats.memp[type].used; + } +#endif /* MEMP_STATS */ + mem = (u8_t *)memp + MEMP_SIZE; + LWIP_ASSERT("memp_malloc: memp properly aligned", + ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0); + } else { + LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %"S16_F"\n", type)); +#if MEMP_STATS + ++lwip_stats.memp[type].err; +#endif /* MEMP_STATS */ + mem = NULL; + } + +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_UNPROTECT(old_level); +#else /* SYS_LIGHTWEIGHT_PROT */ + sys_sem_signal(mutex); +#endif /* SYS_LIGHTWEIGHT_PROT */ + + return mem; +} + +void +memp_free(memp_t type, void *mem) +{ + struct memp *memp; +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_DECL_PROTECT(old_level); +#endif /* SYS_LIGHTWEIGHT_PROT */ + + if (mem == NULL) { + return; + } + + memp = (struct memp *)((u8_t *)mem - MEMP_SIZE); + +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_PROTECT(old_level); +#else /* SYS_LIGHTWEIGHT_PROT */ + sys_sem_wait(mutex); +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#if MEMP_STATS + lwip_stats.memp[type].used--; +#endif /* MEMP_STATS */ + + memp->next = memp_tab[type]; + memp_tab[type] = memp; + +#if MEMP_SANITY_CHECK + LWIP_ASSERT("memp sanity", memp_sanity()); +#endif + +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_UNPROTECT(old_level); +#else /* SYS_LIGHTWEIGHT_PROT */ + sys_sem_signal(mutex); +#endif /* SYS_LIGHTWEIGHT_PROT */ +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/netif.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/netif.c new file mode 100644 index 0000000..0a78661 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/netif.c @@ -0,0 +1,325 @@ +/** + * @file + * + * lwIP network interface abstraction + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/tcp.h" +#include "lwip/snmp.h" + +struct netif *netif_list = NULL; +struct netif *netif_default = NULL; + +/** + * Add a network interface to the list of lwIP netifs. + * + * @param netif a pre-allocated netif structure + * @param ipaddr IP address for the new netif + * @param netmask network mask for the new netif + * @param gw default gateway IP address for the new netif + * @param state opaque data passed to the new netif + * @param init callback function that initializes the interface + * @param input callback function that is called to pass + * ingress packets up in the protocol layer stack. + * + * @return netif, or NULL if failed. + */ +struct netif * +netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw, + void *state, + err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif)) +{ + static s16_t netifnum = 0; + + /* reset new interface configuration state */ + netif->ip_addr.addr = 0; + netif->netmask.addr = 0; + netif->gw.addr = 0; + netif->flags = 0; +#if LWIP_DHCP + /* netif not under DHCP control by default */ + netif->dhcp = NULL; +#endif + /* remember netif specific state information data */ + netif->state = state; + netif->num = netifnum++; + netif->input = input; + + netif_set_addr(netif, ipaddr, netmask, gw); + + /* call user specified initialization function for netif */ + if (init(netif) != ERR_OK) { + return NULL; + } + + /* add this netif to the list */ + netif->next = netif_list; + netif_list = netif; + snmp_inc_iflist(); + + LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ", + netif->name[0], netif->name[1])); + ip_addr_debug_print(NETIF_DEBUG, ipaddr); + LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); + ip_addr_debug_print(NETIF_DEBUG, netmask); + LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); + ip_addr_debug_print(NETIF_DEBUG, gw); + LWIP_DEBUGF(NETIF_DEBUG, ("\n")); + return netif; +} + +void +netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw) +{ + netif_set_ipaddr(netif, ipaddr); + netif_set_netmask(netif, netmask); + netif_set_gw(netif, gw); +} + +void netif_remove(struct netif * netif) +{ + if ( netif == NULL ) return; + + snmp_delete_ipaddridx_tree(netif); + + /* is it the first netif? */ + if (netif_list == netif) { + netif_list = netif->next; + snmp_dec_iflist(); + } + else { + /* look for netif further down the list */ + struct netif * tmpNetif; + for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) { + if (tmpNetif->next == netif) { + tmpNetif->next = netif->next; + snmp_dec_iflist(); + break; + } + } + if (tmpNetif == NULL) + return; /* we didn't find any netif today */ + } + /* this netif is default? */ + if (netif_default == netif) + /* reset default netif */ + netif_default = NULL; + LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") ); +} + +struct netif * +netif_find(char *name) +{ + struct netif *netif; + u8_t num; + + if (name == NULL) { + return NULL; + } + + num = name[2] - '0'; + + for(netif = netif_list; netif != NULL; netif = netif->next) { + if (num == netif->num && + name[0] == netif->name[0] && + name[1] == netif->name[1]) { + LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1])); + return netif; + } + } + LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1])); + return NULL; +} + +void +netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr) +{ + /* TODO: Handling of obsolete pcbs */ + /* See: http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */ +#if LWIP_TCP + struct tcp_pcb *pcb; + struct tcp_pcb_listen *lpcb; + + /* address is actually being changed? */ + if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0) + { + /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */ + LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n")); + pcb = tcp_active_pcbs; + while (pcb != NULL) { + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) { + /* this connection must be aborted */ + struct tcp_pcb *next = pcb->next; + LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); + tcp_abort(pcb); + pcb = next; + } else { + pcb = pcb->next; + } + } + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) { + /* The PCB is listening to the old ipaddr and + * is set to listen to the new one instead */ + ip_addr_set(&(lpcb->local_ip), ipaddr); + } + } + } +#endif + snmp_delete_ipaddridx_tree(netif); + snmp_delete_iprteidx_tree(0,netif); + /* set new IP address to netif */ + ip_addr_set(&(netif->ip_addr), ipaddr); + snmp_insert_ipaddridx_tree(netif); + snmp_insert_iprteidx_tree(0,netif); + +#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */ + /** For Ethernet network interfaces, we would like to send a + * "gratuitous ARP"; this is an ARP packet sent by a node in order + * to spontaneously cause other nodes to update an entry in their + * ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6. + */ + etharp_query(netif, ipaddr, NULL); +#endif + LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1(&netif->ip_addr), + ip4_addr2(&netif->ip_addr), + ip4_addr3(&netif->ip_addr), + ip4_addr4(&netif->ip_addr))); +} + +void +netif_set_gw(struct netif *netif, struct ip_addr *gw) +{ + ip_addr_set(&(netif->gw), gw); + LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1(&netif->gw), + ip4_addr2(&netif->gw), + ip4_addr3(&netif->gw), + ip4_addr4(&netif->gw))); +} + +void +netif_set_netmask(struct netif *netif, struct ip_addr *netmask) +{ + snmp_delete_iprteidx_tree(0, netif); + /* set new netmask to netif */ + ip_addr_set(&(netif->netmask), netmask); + snmp_insert_iprteidx_tree(0, netif); + LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1(&netif->netmask), + ip4_addr2(&netif->netmask), + ip4_addr3(&netif->netmask), + ip4_addr4(&netif->netmask))); +} + +void +netif_set_default(struct netif *netif) +{ + if (netif == NULL) + { + /* remove default route */ + snmp_delete_iprteidx_tree(1, netif); + } + else + { + /* install default route */ + snmp_insert_iprteidx_tree(1, netif); + } + netif_default = netif; + LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", + netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); +} + +/** + * Bring an interface up, available for processing + * traffic. + * + * @note: Enabling DHCP on a down interface will make it come + * up once configured. + * + * @see dhcp_start() + */ +void netif_set_up(struct netif *netif) +{ + netif->flags |= NETIF_FLAG_UP; +#if LWIP_SNMP + snmp_get_sysuptime(&netif->ts); +#endif +} + +/** + * Ask if an interface is up + */ +u8_t netif_is_up(struct netif *netif) +{ + return (netif->flags & NETIF_FLAG_UP)?1:0; +} + +/** + * Bring an interface down, disabling any traffic processing. + * + * @note: Enabling DHCP on a down interface will make it come + * up once configured. + * + * @see dhcp_start() + */ +void netif_set_down(struct netif *netif) +{ + netif->flags &= ~NETIF_FLAG_UP; +#if LWIP_SNMP + snmp_get_sysuptime(&netif->ts); +#endif +} + +void +netif_init(void) +{ + netif_list = netif_default = NULL; +} + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/pbuf.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/pbuf.c new file mode 100644 index 0000000..1f6516d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/pbuf.c @@ -0,0 +1,964 @@ +/** + * @file + * Packet buffer management + * + * Packets are built from the pbuf data structure. It supports dynamic + * memory allocation for packet contents or can reference externally + * managed packet contents both in RAM and ROM. Quick allocation for + * incoming packets is provided through pools with fixed sized pbufs. + * + * A packet may span over multiple pbufs, chained as a singly linked + * list. This is called a "pbuf chain". + * + * Multiple packets may be queued, also using this singly linked list. + * This is called a "packet queue". + * + * So, a packet queue consists of one or more pbuf chains, each of + * which consist of one or more pbufs. Currently, queues are only + * supported in a limited section of lwIP, this is the etharp queueing + * code. Outside of this section no packet queues are supported yet. + * + * The differences between a pbuf chain and a packet queue are very + * precise but subtle. + * + * The last pbuf of a packet has a ->tot_len field that equals the + * ->len field. It can be found by traversing the list. If the last + * pbuf of a packet has a ->next field other than NULL, more packets + * are on the queue. + * + * Therefore, looping through a pbuf of a single packet, has an + * loop end condition (tot_len == p->len), NOT (next == NULL). + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" +#include "lwip/stats.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "arch/perf.h" + +static u8_t pbuf_pool_memory[MEM_ALIGNMENT - 1 + PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf))]; + +#if !SYS_LIGHTWEIGHT_PROT +static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock; +static sys_sem_t pbuf_pool_free_sem; +#endif + +static struct pbuf *pbuf_pool = NULL; + +/** + * Initializes the pbuf module. + * + * A large part of memory is allocated for holding the pool of pbufs. + * The size of the individual pbufs in the pool is given by the size + * parameter, and the number of pbufs in the pool by the num parameter. + * + * After the memory has been allocated, the pbufs are set up. The + * ->next pointer in each pbuf is set up to point to the next pbuf in + * the pool. + * + */ +void +pbuf_init(void) +{ + struct pbuf *p, *q = NULL; + u16_t i; + + pbuf_pool = (struct pbuf *)MEM_ALIGN(pbuf_pool_memory); + +#if PBUF_STATS + lwip_stats.pbuf.avail = PBUF_POOL_SIZE; +#endif /* PBUF_STATS */ + + /* Set up ->next pointers to link the pbufs of the pool together */ + p = pbuf_pool; + + for(i = 0; i < PBUF_POOL_SIZE; ++i) { + p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf)); + p->len = p->tot_len = PBUF_POOL_BUFSIZE; + p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf))); + p->flags = PBUF_FLAG_POOL; + q = p; + p = p->next; + } + + /* The ->next pointer of last pbuf is NULL to indicate that there + are no more pbufs in the pool */ + q->next = NULL; + +#if !SYS_LIGHTWEIGHT_PROT + pbuf_pool_alloc_lock = 0; + pbuf_pool_free_lock = 0; + pbuf_pool_free_sem = sys_sem_new(1); +#endif +} + +/** + * @internal only called from pbuf_alloc() + */ +static struct pbuf * +pbuf_pool_alloc(void) +{ + struct pbuf *p = NULL; + + SYS_ARCH_DECL_PROTECT(old_level); + SYS_ARCH_PROTECT(old_level); + +#if !SYS_LIGHTWEIGHT_PROT + /* Next, check the actual pbuf pool, but if the pool is locked, we + pretend to be out of buffers and return NULL. */ + if (pbuf_pool_free_lock) { +#if PBUF_STATS + ++lwip_stats.pbuf.alloc_locked; +#endif /* PBUF_STATS */ + return NULL; + } + pbuf_pool_alloc_lock = 1; + if (!pbuf_pool_free_lock) { +#endif /* SYS_LIGHTWEIGHT_PROT */ + p = pbuf_pool; + if (p) { + pbuf_pool = p->next; + } +#if !SYS_LIGHTWEIGHT_PROT +#if PBUF_STATS + } else { + ++lwip_stats.pbuf.alloc_locked; +#endif /* PBUF_STATS */ + } + pbuf_pool_alloc_lock = 0; +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#if PBUF_STATS + if (p != NULL) { + ++lwip_stats.pbuf.used; + if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) { + lwip_stats.pbuf.max = lwip_stats.pbuf.used; + } + } +#endif /* PBUF_STATS */ + + SYS_ARCH_UNPROTECT(old_level); + return p; +} + + +/** + * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). + * + * The actual memory allocated for the pbuf is determined by the + * layer at which the pbuf is allocated and the requested size + * (from the size parameter). + * + * @param flag this parameter decides how and where the pbuf + * should be allocated as follows: + * + * - PBUF_RAM: buffer memory for pbuf is allocated as one large + * chunk. This includes protocol headers as well. + * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for + * protocol headers. Additional headers must be prepended + * by allocating another pbuf and chain in to the front of + * the ROM pbuf. It is assumed that the memory used is really + * similar to ROM in that it is immutable and will not be + * changed. Memory which is dynamic should generally not + * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. + * - PBUF_REF: no buffer memory is allocated for the pbuf, even for + * protocol headers. It is assumed that the pbuf is only + * being used in a single thread. If the pbuf gets queued, + * then pbuf_take should be called to copy the buffer. + * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from + * the pbuf pool that is allocated during pbuf_init(). + * + * @return the allocated pbuf. If multiple pbufs where allocated, this + * is the first pbuf of a pbuf chain. + */ +struct pbuf * +pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag) +{ + struct pbuf *p, *q, *r; + u16_t offset; + s32_t rem_len; /* remaining length */ + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length)); + + /* determine header offset */ + offset = 0; + switch (l) { + case PBUF_TRANSPORT: + /* add room for transport (often TCP) layer header */ + offset += PBUF_TRANSPORT_HLEN; + /* FALLTHROUGH */ + case PBUF_IP: + /* add room for IP layer header */ + offset += PBUF_IP_HLEN; + /* FALLTHROUGH */ + case PBUF_LINK: + /* add room for link layer header */ + offset += PBUF_LINK_HLEN; + break; + case PBUF_RAW: + break; + default: + LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0); + return NULL; + } + + switch (flag) { + case PBUF_POOL: + /* allocate head of pbuf chain into p */ + p = pbuf_pool_alloc(); + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p)); + if (p == NULL) { +#if PBUF_STATS + ++lwip_stats.pbuf.err; +#endif /* PBUF_STATS */ + return NULL; + } + p->next = NULL; + + /* make the payload pointer point 'offset' bytes into pbuf data memory */ + p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset))); + LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + /* the total length of the pbuf chain is the requested size */ + p->tot_len = length; + /* set the length of the first pbuf in the chain */ + p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length; + /* set reference count (needed here in case we fail) */ + p->ref = 1; + + /* now allocate the tail of the pbuf chain */ + + /* remember first pbuf for linkage in next iteration */ + r = p; + /* remaining length to be allocated */ + rem_len = length - p->len; + /* any remaining pbufs to be allocated? */ + while (rem_len > 0) { + q = pbuf_pool_alloc(); + if (q == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n")); +#if PBUF_STATS + ++lwip_stats.pbuf.err; +#endif /* PBUF_STATS */ + /* free chain so far allocated */ + pbuf_free(p); + /* bail out unsuccesfully */ + return NULL; + } + q->next = NULL; + /* make previous pbuf point to this pbuf */ + r->next = q; + /* set total length of this pbuf and next in chain */ + q->tot_len = rem_len; + /* this pbuf length is pool size, unless smaller sized tail */ + q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len; + q->payload = (void *)((u8_t *)q + sizeof(struct pbuf)); + LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", + ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); + q->ref = 1; + /* calculate remaining length to be allocated */ + rem_len -= q->len; + /* remember this pbuf for linkage in next iteration */ + r = q; + } + /* end of chain */ + /*r->next = NULL;*/ + + break; + case PBUF_RAM: + /* If pbuf is to be allocated in RAM, allocate memory for it. */ + p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length)); + if (p == NULL) { + return NULL; + } + /* Set up internal structure of the pbuf. */ + p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset)); + p->len = p->tot_len = length; + p->next = NULL; + p->flags = PBUF_FLAG_RAM; + + LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + break; + /* pbuf references existing (non-volatile static constant) ROM payload? */ + case PBUF_ROM: + /* pbuf references existing (externally allocated) RAM payload? */ + case PBUF_REF: + /* only allocate memory for the pbuf structure */ + p = memp_malloc(MEMP_PBUF); + if (p == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF")); + + return NULL; + } + /* caller must set this field properly, afterwards */ + p->payload = NULL; + p->len = p->tot_len = length; + p->next = NULL; + p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF); + break; + default: + LWIP_ASSERT("pbuf_alloc: erroneous flag", 0); + return NULL; + } + /* set reference count */ + p->ref = 1; + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); + return p; +} + + +#if PBUF_STATS +#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0) +#else /* PBUF_STATS */ +#define DEC_PBUF_STATS +#endif /* PBUF_STATS */ + +#define PBUF_POOL_FAST_FREE(p) do { \ + p->next = pbuf_pool; \ + pbuf_pool = p; \ + DEC_PBUF_STATS; \ + } while (0) + +#if SYS_LIGHTWEIGHT_PROT +#define PBUF_POOL_FREE(p) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + PBUF_POOL_FAST_FREE(p); \ + SYS_ARCH_UNPROTECT(old_level); \ + } while (0) +#else /* SYS_LIGHTWEIGHT_PROT */ +#define PBUF_POOL_FREE(p) do { \ + sys_sem_wait(pbuf_pool_free_sem); \ + PBUF_POOL_FAST_FREE(p); \ + sys_sem_signal(pbuf_pool_free_sem); \ + } while (0) +#endif /* SYS_LIGHTWEIGHT_PROT */ + +/** + * Shrink a pbuf chain to a desired length. + * + * @param p pbuf to shrink. + * @param new_len desired new length of pbuf chain + * + * Depending on the desired length, the first few pbufs in a chain might + * be skipped and left unchanged. The new last pbuf in the chain will be + * resized, and any remaining pbufs will be freed. + * + * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted. + * @note May not be called on a packet queue. + * + * @bug Cannot grow the size of a pbuf (chain) (yet). + */ +void +pbuf_realloc(struct pbuf *p, u16_t new_len) +{ + struct pbuf *q; + u16_t rem_len; /* remaining length */ + s16_t grow; + + LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL || + p->flags == PBUF_FLAG_ROM || + p->flags == PBUF_FLAG_RAM || + p->flags == PBUF_FLAG_REF); + + /* desired length larger than current length? */ + if (new_len >= p->tot_len) { + /* enlarging not yet supported */ + return; + } + + /* the pbuf chain grows by (new_len - p->tot_len) bytes + * (which may be negative in case of shrinking) */ + grow = new_len - p->tot_len; + + /* first, step over any pbufs that should remain in the chain */ + rem_len = new_len; + q = p; + /* should this pbuf be kept? */ + while (rem_len > q->len) { + /* decrease remaining length by pbuf length */ + rem_len -= q->len; + /* decrease total length indicator */ + q->tot_len += grow; + /* proceed to next pbuf in chain */ + q = q->next; + } + /* we have now reached the new last pbuf (in q) */ + /* rem_len == desired length for pbuf q */ + + /* shrink allocated memory for PBUF_RAM */ + /* (other types merely adjust their length fields */ + if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) { + /* reallocate and adjust the length of the pbuf that will be split */ + mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len); + } + /* adjust length fields for new last pbuf */ + q->len = rem_len; + q->tot_len = q->len; + + /* any remaining pbufs in chain? */ + if (q->next != NULL) { + /* free remaining pbufs in chain */ + pbuf_free(q->next); + } + /* q is last packet in chain */ + q->next = NULL; + +} + +/** + * Adjusts the payload pointer to hide or reveal headers in the payload. + * + * Adjusts the ->payload pointer so that space for a header + * (dis)appears in the pbuf payload. + * + * The ->payload, ->tot_len and ->len fields are adjusted. + * + * @param hdr_size_inc Number of bytes to increment header size which + * increases the size of the pbuf. New space is on the front. + * (Using a negative value decreases the header size.) + * If hdr_size_inc is 0, this function does nothing and returns succesful. + * + * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so + * the call will fail. A check is made that the increase in header size does + * not move the payload pointer in front of the start of the buffer. + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_header(struct pbuf *p, s16_t header_size_increment) +{ + u16_t flags; + void *payload; + + LWIP_ASSERT("p != NULL", p != NULL); + if ((header_size_increment == 0) || (p == NULL)) return 0; + + flags = p->flags; + /* remember current payload pointer */ + payload = p->payload; + + /* pbuf types containing payloads? */ + if (flags == PBUF_FLAG_RAM || flags == PBUF_FLAG_POOL) { + /* set new payload pointer */ + p->payload = (u8_t *)p->payload - header_size_increment; + /* boundary check fails? */ + if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) { + LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n", + (void *)p->payload, + (void *)(p + 1)));\ + /* restore old payload pointer */ + p->payload = payload; + /* bail out unsuccesfully */ + return 1; + } + /* pbuf types refering to external payloads? */ + } else if (flags == PBUF_FLAG_REF || flags == PBUF_FLAG_ROM) { + /* hide a header in the payload? */ + if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) { + /* increase payload pointer */ + p->payload = (u8_t *)p->payload - header_size_increment; + } else { + /* cannot expand payload to front (yet!) + * bail out unsuccesfully */ + return 1; + } + } + /* modify pbuf length fields */ + p->len += header_size_increment; + p->tot_len += header_size_increment; + + LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n", + (void *)payload, (void *)p->payload, header_size_increment)); + + return 0; +} + +/** + * Dereference a pbuf chain or queue and deallocate any no-longer-used + * pbufs at the head of this chain or queue. + * + * Decrements the pbuf reference count. If it reaches zero, the pbuf is + * deallocated. + * + * For a pbuf chain, this is repeated for each pbuf in the chain, + * up to the first pbuf which has a non-zero reference count after + * decrementing. So, when all reference counts are one, the whole + * chain is free'd. + * + * @param pbuf The pbuf (chain) to be dereferenced. + * + * @return the number of pbufs that were de-allocated + * from the head of the chain. + * + * @note MUST NOT be called on a packet queue (Not verified to work yet). + * @note the reference counter of a pbuf equals the number of pointers + * that refer to the pbuf (or into the pbuf). + * + * @internal examples: + * + * Assuming existing chains a->b->c with the following reference + * counts, calling pbuf_free(a) results in: + * + * 1->2->3 becomes ...1->3 + * 3->3->3 becomes 2->3->3 + * 1->1->2 becomes ......1 + * 2->1->1 becomes 1->1->1 + * 1->1->1 becomes ....... + * + */ +u8_t +pbuf_free(struct pbuf *p) +{ + u16_t flags; + struct pbuf *q; + u8_t count; + SYS_ARCH_DECL_PROTECT(old_level); + + LWIP_ASSERT("p != NULL", p != NULL); + + /* if assertions are disabled, proceed with debug output */ + if (p == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n")); + return 0; + } + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p)); + + PERF_START; + + LWIP_ASSERT("pbuf_free: sane flags", + p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM || + p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL); + + count = 0; + /* Since decrementing ref cannot be guaranteed to be a single machine operation + * we must protect it. Also, the later test of ref must be protected. + */ + SYS_ARCH_PROTECT(old_level); + /* de-allocate all consecutive pbufs from the head of the chain that + * obtain a zero reference count after decrementing*/ + while (p != NULL) { + /* all pbufs in a chain are referenced at least once */ + LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); + /* decrease reference count (number of pointers to pbuf) */ + p->ref--; + /* this pbuf is no longer referenced to? */ + if (p->ref == 0) { + /* remember next pbuf in chain for next iteration */ + q = p->next; + LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p)); + flags = p->flags; + /* is this a pbuf from the pool? */ + if (flags == PBUF_FLAG_POOL) { + p->len = p->tot_len = PBUF_POOL_BUFSIZE; + p->payload = (void *)((u8_t *)p + sizeof(struct pbuf)); + PBUF_POOL_FREE(p); + /* is this a ROM or RAM referencing pbuf? */ + } else if (flags == PBUF_FLAG_ROM || flags == PBUF_FLAG_REF) { + memp_free(MEMP_PBUF, p); + /* flags == PBUF_FLAG_RAM */ + } else { + mem_free(p); + } + count++; + /* proceed to next pbuf */ + p = q; + /* p->ref > 0, this pbuf is still referenced to */ + /* (and so the remaining pbufs in chain as well) */ + } else { + LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)p->ref)); + /* stop walking through the chain */ + p = NULL; + } + } + SYS_ARCH_UNPROTECT(old_level); + PERF_STOP("pbuf_free"); + /* return number of de-allocated pbufs */ + + return count; +} + +/** + * Count number of pbufs in a chain + * + * @param p first pbuf of chain + * @return the number of pbufs in a chain + */ + +u8_t +pbuf_clen(struct pbuf *p) +{ + u8_t len; + + len = 0; + while (p != NULL) { + ++len; + p = p->next; + } + return len; +} + +/** + * Increment the reference count of the pbuf. + * + * @param p pbuf to increase reference counter of + * + */ +void +pbuf_ref(struct pbuf *p) +{ + SYS_ARCH_DECL_PROTECT(old_level); + /* pbuf given? */ + if (p != NULL) { + SYS_ARCH_PROTECT(old_level); + ++(p->ref); + SYS_ARCH_UNPROTECT(old_level); + } +} + +/** + * Concatenate two pbufs (each may be a pbuf chain) and take over + * the caller's reference of the tail pbuf. + * + * @note The caller MAY NOT reference the tail pbuf afterwards. + * Use pbuf_chain() for that purpose. + * + * @see pbuf_chain() + */ + +void +pbuf_cat(struct pbuf *h, struct pbuf *t) +{ + struct pbuf *p; + + LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL); + LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL); + if ((h == NULL) || (t == NULL)) return; + + /* proceed to last pbuf of chain */ + for (p = h; p->next != NULL; p = p->next) { + /* add total length of second chain to all totals of first chain */ + p->tot_len += t->tot_len; + } + /* { p is last pbuf of first h chain, p->next == NULL } */ + LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); + LWIP_ASSERT("p->next == NULL", p->next == NULL); + /* add total length of second chain to last pbuf total of first chain */ + p->tot_len += t->tot_len; + /* chain last pbuf of head (p) with first of tail (t) */ + p->next = t; + /* p->next now references t, but the caller will drop its reference to t, + * so netto there is no change to the reference count of t. + */ +} + +/** + * Chain two pbufs (or pbuf chains) together. + * + * The caller MUST call pbuf_free(t) once it has stopped + * using it. Use pbuf_cat() instead if you no longer use t. + * + * @param h head pbuf (chain) + * @param t tail pbuf (chain) + * @note The pbufs MUST belong to the same packet. + * @note MAY NOT be called on a packet queue. + * + * The ->tot_len fields of all pbufs of the head chain are adjusted. + * The ->next field of the last pbuf of the head chain is adjusted. + * The ->ref field of the first pbuf of the tail chain is adjusted. + * + */ +void +pbuf_chain(struct pbuf *h, struct pbuf *t) +{ + pbuf_cat(h, t); + /* t is now referenced by h */ + pbuf_ref(t); + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); +} + +/* For packet queueing. Note that queued packets MUST be dequeued first + * using pbuf_dequeue() before calling other pbuf_() functions. */ +#if ARP_QUEUEING +/** + * Add a packet to the end of a queue. + * + * @param q pointer to first packet on the queue + * @param n packet to be queued + * + * Both packets MUST be given, and must be different. + */ +void +pbuf_queue(struct pbuf *p, struct pbuf *n) +{ +#if PBUF_DEBUG /* remember head of queue */ + struct pbuf *q = p; +#endif + /* programmer stupidity checks */ + LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL); + LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL); + LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n); + if ((p == NULL) || (n == NULL) || (p == n)){ + LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n")); + return; + } + + /* iterate through all packets on queue */ + while (p->next != NULL) { +/* be very picky about pbuf chain correctness */ +#if PBUF_DEBUG + /* iterate through all pbufs in packet */ + while (p->tot_len != p->len) { + /* make sure invariant condition holds */ + LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len); + /* make sure each packet is complete */ + LWIP_ASSERT("p->next != NULL", p->next != NULL); + p = p->next; + /* { p->tot_len == p->len => p is last pbuf of a packet } */ + } + /* { p is last pbuf of a packet } */ + /* proceed to next packet on queue */ +#endif + /* proceed to next pbuf */ + if (p->next != NULL) p = p->next; + } + /* { p->tot_len == p->len and p->next == NULL } ==> + * { p is last pbuf of last packet on queue } */ + /* chain last pbuf of queue with n */ + p->next = n; + /* n is now referenced to by the (packet p in the) queue */ + pbuf_ref(n); +#if PBUF_DEBUG + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, + ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n", + (void *)n, (void *)p, (void *)q)); +#endif +} + +/** + * Remove a packet from the head of a queue. + * + * The caller MUST reference the remainder of the queue (as returned). The + * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference + * from p. + * + * @param p pointer to first packet on the queue which will be dequeued. + * @return first packet on the remaining queue (NULL if no further packets). + * + */ +struct pbuf * +pbuf_dequeue(struct pbuf *p) +{ + struct pbuf *q; + LWIP_ASSERT("p != NULL", p != NULL); + + /* iterate through all pbufs in packet p */ + while (p->tot_len != p->len) { + /* make sure invariant condition holds */ + LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len); + /* make sure each packet is complete */ + LWIP_ASSERT("p->next != NULL", p->next != NULL); + p = p->next; + } + /* { p->tot_len == p->len } => p is the last pbuf of the first packet */ + /* remember next packet on queue in q */ + q = p->next; + /* dequeue packet p from queue */ + p->next = NULL; + /* any next packet on queue? */ + if (q != NULL) { + /* although q is no longer referenced by p, it MUST be referenced by + * the caller, who is maintaining this packet queue. So, we do not call + * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */ + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q)); + } else { + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n")); + } + return q; +} +#endif + +/** + * + * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs. + * + * Used to queue packets on behalf of the lwIP stack, such as + * ARP based queueing. + * + * Go through a pbuf chain and replace any PBUF_REF buffers + * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of + * the referenced data. + * + * @note You MUST explicitly use p = pbuf_take(p); + * The pbuf you give as argument, may have been replaced + * by a (differently located) copy through pbuf_take()! + * + * @note Any replaced pbufs will be freed through pbuf_free(). + * This may deallocate them if they become no longer referenced. + * + * @param p Head of pbuf chain to process + * + * @return Pointer to head of pbuf chain + */ +struct pbuf * +pbuf_take(struct pbuf *p) +{ + struct pbuf *q , *prev, *head; + LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL); + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p)); + + prev = NULL; + head = p; + /* iterate through pbuf chain */ + do + { + /* pbuf is of type PBUF_REF? */ + if (p->flags == PBUF_FLAG_REF) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p)); + /* allocate a pbuf (w/ payload) fully in RAM */ + /* PBUF_POOL buffers are faster if we can use them */ + if (p->len <= PBUF_POOL_BUFSIZE) { + q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL); + if (q == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n")); + } + } else { + /* no replacement pbuf yet */ + q = NULL; + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n")); + } + /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */ + if (q == NULL) { + q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM); + if (q == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n")); + } + } + /* replacement pbuf could be allocated? */ + if (q != NULL) + { + /* copy p to q */ + /* copy successor */ + q->next = p->next; + /* remove linkage from original pbuf */ + p->next = NULL; + /* remove linkage to original pbuf */ + if (prev != NULL) { + /* prev->next == p at this point */ + LWIP_ASSERT("prev->next == p", prev->next == p); + /* break chain and insert new pbuf instead */ + prev->next = q; + /* prev == NULL, so we replaced the head pbuf of the chain */ + } else { + head = q; + } + /* copy pbuf payload */ + memcpy(q->payload, p->payload, p->len); + q->tot_len = p->tot_len; + q->len = p->len; + /* in case p was the first pbuf, it is no longer refered to by + * our caller, as the caller MUST do p = pbuf_take(p); + * in case p was not the first pbuf, it is no longer refered to + * by prev. we can safely free the pbuf here. + * (note that we have set p->next to NULL already so that + * we will not free the rest of the chain by accident.) + */ + pbuf_free(p); + /* do not copy ref, since someone else might be using the old buffer */ + LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q)); + p = q; + } else { + /* deallocate chain */ + pbuf_free(head); + LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p)); + return NULL; + } + /* p->flags != PBUF_FLAG_REF */ + } else { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n")); + } + /* remember this pbuf */ + prev = p; + /* proceed to next pbuf in original chain */ + p = p->next; + } while (p); + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n")); + + return head; +} + +/** + * Dechains the first pbuf from its succeeding pbufs in the chain. + * + * Makes p->tot_len field equal to p->len. + * @param p pbuf to dechain + * @return remainder of the pbuf chain, or NULL if it was de-allocated. + * @note May not be called on a packet queue. + */ +struct pbuf * +pbuf_dechain(struct pbuf *p) +{ + struct pbuf *q; + u8_t tail_gone = 1; + /* tail */ + q = p->next; + /* pbuf has successor in chain? */ + if (q != NULL) { + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len); + /* enforce invariant if assertion is disabled */ + q->tot_len = p->tot_len - p->len; + /* decouple pbuf from remainder */ + p->next = NULL; + /* total length of pbuf p is its own length only */ + p->tot_len = p->len; + /* q is no longer referenced by p, free it */ + LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); + tail_gone = pbuf_free(q); + if (tail_gone > 0) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, + ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); + } + /* return remaining tail or NULL if deallocated */ + } + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len); + return (tail_gone > 0? NULL: q); +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/raw.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/raw.c new file mode 100644 index 0000000..b0e18b0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/raw.c @@ -0,0 +1,326 @@ +/** + * @file + * + * Implementation of raw protocol PCBs for low-level handling of + * different types of protocols besides (or overriding) those + * already available in lwIP. + * + */ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/inet.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/raw.h" + +#include "lwip/stats.h" + +#include "arch/perf.h" +#include "lwip/snmp.h" + +#if LWIP_RAW + +/** The list of RAW PCBs */ +static struct raw_pcb *raw_pcbs = NULL; + +void +raw_init(void) +{ + raw_pcbs = NULL; +} + +/** + * Determine if in incoming IP packet is covered by a RAW PCB + * and if so, pass it to a user-provided receive callback function. + * + * Given an incoming IP datagram (as a chain of pbufs) this function + * finds a corresponding RAW PCB and calls the corresponding receive + * callback function. + * + * @param pbuf pbuf to be demultiplexed to a RAW PCB. + * @param netif network interface on which the datagram was received. + * @Return - 1 if the packet has been eaten by a RAW PCB receive + * callback function. The caller MAY NOT not reference the + * packet any longer, and MAY NOT call pbuf_free(). + * @return - 0 if packet is not eaten (pbuf is still referenced by the + * caller). + * + */ +u8_t +raw_input(struct pbuf *p, struct netif *inp) +{ + struct raw_pcb *pcb; + struct ip_hdr *iphdr; + s16_t proto; + u8_t eaten = 0; + + iphdr = p->payload; + proto = IPH_PROTO(iphdr); + + pcb = raw_pcbs; + /* loop through all raw pcbs until the packet is eaten by one */ + /* this allows multiple pcbs to match against the packet by design */ + while ((eaten == 0) && (pcb != NULL)) { + if (pcb->protocol == proto) { + /* receive callback function available? */ + if (pcb->recv != NULL) { + /* the receive callback function did not eat the packet? */ + if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0) + { + /* receive function ate the packet */ + p = NULL; + eaten = 1; + } + } + /* no receive callback function was set for this raw PCB */ + /* drop the packet */ + } + pcb = pcb->next; + } + return eaten; +} + +/** + * Bind a RAW PCB. + * + * @param pcb RAW PCB to be bound with a local address ipaddr. + * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to + * bind to all local interfaces. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_USE. The specified IP address is already bound to by + * another RAW PCB. + * + * @see raw_disconnect() + */ +err_t +raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr) +{ + ip_addr_set(&pcb->local_ip, ipaddr); + return ERR_OK; +} + +/** + * Connect an RAW PCB. This function is required by upper layers + * of lwip. Using the raw api you could use raw_sendto() instead + * + * This will associate the RAW PCB with the remote address. + * + * @param pcb RAW PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * + * @return lwIP error code + * + * @see raw_disconnect() and raw_sendto() + */ +err_t +raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr) +{ + ip_addr_set(&pcb->remote_ip, ipaddr); + return ERR_OK; +} + + +/** + * Set the callback function for received packets that match the + * raw PCB's protocol and binding. + * + * The callback function MUST either + * - eat the packet by calling pbuf_free() and returning non-zero. The + * packet will not be passed to other raw PCBs or other protocol layers. + * - not free the packet, and return zero. The packet will be matched + * against further PCBs and/or forwarded to another protocol layers. + * + * @return non-zero if the packet was free()d, zero if the packet remains + * available for others. + */ +void +raw_recv(struct raw_pcb *pcb, + u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p, + struct ip_addr *addr), + void *recv_arg) +{ + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * Send the raw IP packet to the given address. Note that actually you cannot + * modify the IP headers (this is inconsistent with the receive callback where + * you actually get the IP headers), you can only specify the IP payload here. + * It requires some more changes in lwIP. (there will be a raw_send() function + * then.) + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * @param ipaddr the destination address of the IP packet + * + */ +err_t +raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr) +{ + err_t err; + struct netif *netif; + struct ip_addr *src_ip; + struct pbuf *q; /* q will be sent down the stack */ + + LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n")); + + /* not enough space to add an IP header to first pbuf in given p chain? */ + if (pbuf_header(p, IP_HLEN)) { + /* allocate header in new pbuf */ + q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n")); + return ERR_MEM; + } + /* chain header q in front of given pbuf p */ + pbuf_chain(q, p); + /* { first pbuf q points to header pbuf } */ + LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* first pbuf q equals given pbuf */ + q = p; + pbuf_header(q, -IP_HLEN); + } + + if ((netif = ip_route(ipaddr)) == NULL) { + LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr)); +#if RAW_STATS + /* ++lwip_stats.raw.rterr;*/ +#endif /* RAW_STATS */ + /* free any temporary header pbuf allocated by pbuf_header() */ + if (q != p) { + pbuf_free(q); + } + return ERR_RTE; + } + + if (ip_addr_isany(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ + src_ip = &(netif->ip_addr); + } else { + /* use RAW PCB local IP address as source address */ + src_ip = &(pcb->local_ip); + } + + err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif); + + /* did we chain a header earlier? */ + if (q != p) { + /* free the header */ + pbuf_free(q); + } + return err; +} + +/** + * Send the raw IP packet to the address given by raw_connect() + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * @param ipaddr the destination address of the IP packet + * + */ +err_t +raw_send(struct raw_pcb *pcb, struct pbuf *p) +{ + return raw_sendto(pcb, p, &pcb->remote_ip); +} + +/** + * Remove an RAW PCB. + * + * @param pcb RAW PCB to be removed. The PCB is removed from the list of + * RAW PCB's and the data structure is freed from memory. + * + * @see raw_new() + */ +void +raw_remove(struct raw_pcb *pcb) +{ + struct raw_pcb *pcb2; + /* pcb to be removed is first in list? */ + if (raw_pcbs == pcb) { + /* make list start at 2nd pcb */ + raw_pcbs = raw_pcbs->next; + /* pcb not 1st in list */ + } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in raw_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + } + } + memp_free(MEMP_RAW_PCB, pcb); +} + +/** + * Create a RAW PCB. + * + * @return The RAW PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP) + * + * @see raw_remove() + */ +struct raw_pcb * +raw_new(u16_t proto) { + struct raw_pcb *pcb; + + LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n")); + + pcb = memp_malloc(MEMP_RAW_PCB); + /* could allocate RAW PCB? */ + if (pcb != NULL) { + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct raw_pcb)); + pcb->protocol = proto; + pcb->ttl = RAW_TTL; + pcb->next = raw_pcbs; + raw_pcbs = pcb; + } + return pcb; +} + +#endif /* LWIP_RAW */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/asn1_dec.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/asn1_dec.c new file mode 100644 index 0000000..a556edd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/asn1_dec.c @@ -0,0 +1,652 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) decoding + * + * @todo not optimised (yet), favor correctness over speed, favor speed over size + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "lwip/snmp_asn1.h" + +/** + * Retrieves type field from incoming pbuf chain. + * + * @param p points to a pbuf holding an ASN1 coded type field + * @param ofs points to the offset within the pbuf chain of the ASN1 coded type field + * @param type return ASN1 type + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + *type = *msg_ptr; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes length field from incoming pbuf chain into host length. + * + * @param p points to a pbuf holding an ASN1 coded length + * @param ofs points to the offset within the pbuf chain of the ASN1 coded length + * @param octets_used returns number of octets used by the length code + * @param length return host order length, upto 64k + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + if (*msg_ptr < 0x80) + { + /* primitive definite length format */ + *octets_used = 1; + *length = *msg_ptr; + return ERR_OK; + } + else if (*msg_ptr == 0x80) + { + /* constructed indefinite length format, termination with two zero octets */ + u8_t zeros; + u8_t i; + + *length = 0; + zeros = 0; + while (zeros != 2) + { + i = 2; + while (i > 0) + { + i--; + (*length) += 1; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + if (*msg_ptr == 0) + { + zeros++; + if (zeros == 2) + { + /* stop while (i > 0) */ + i = 0; + } + } + else + { + zeros = 0; + } + } + } + *octets_used = 1; + return ERR_OK; + } + else if (*msg_ptr == 0x81) + { + /* constructed definite length format, one octet */ + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + *length = *msg_ptr; + *octets_used = 2; + return ERR_OK; + } + else if (*msg_ptr == 0x82) + { + u8_t i; + + /* constructed definite length format, two octets */ + i = 2; + while (i > 0) + { + i--; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + if (i == 0) + { + /* least significant length octet */ + *length |= *msg_ptr; + } + else + { + /* most significant length octet */ + *length = (*msg_ptr) << 8; + } + } + *octets_used = 3; + return ERR_OK; + } + else + { + /* constructed definite length format 3..127 octets, this is too big (>64k) */ + /** @todo: do we need to accept inefficient codings with many leading zero's? */ + *octets_used = 1 + ((*msg_ptr) & 0x7f); + return ERR_ARG; + } + } + p = p->next; + } + + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes positive integer (counter, gauge, timeticks) into u32_t. + * + * @param p points to a pbuf holding an ASN1 coded integer + * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer + * @param len length of the coded integer field + * @param value return host order integer + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + * + * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded + * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value + * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! + */ +err_t +snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + if ((len > 0) && (len < 6)) + { + /* start from zero */ + *value = 0; + if (*msg_ptr & 0x80) + { + /* negative, expecting zero sign bit! */ + return ERR_ARG; + } + else + { + /* positive */ + if ((len > 1) && (*msg_ptr == 0)) + { + /* skip leading "sign byte" octet 0x00 */ + len--; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + } + /* OR octets with value */ + while (len > 1) + { + len--; + *value |= *msg_ptr; + *value <<= 8; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + *value |= *msg_ptr; + return ERR_OK; + } + else + { + return ERR_ARG; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes integer into s32_t. + * + * @param p points to a pbuf holding an ASN1 coded integer + * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer + * @param len length of the coded integer field + * @param value return host order integer + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + * + * @note ASN coded integers are _always_ signed! + */ +err_t +snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value) +{ + u16_t plen, base; + u8_t *msg_ptr; + u8_t *lsb_ptr = (u8_t*)value; + u8_t sign; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + if ((len > 0) && (len < 5)) + { + if (*msg_ptr & 0x80) + { + /* negative, start from -1 */ + *value = -1; + sign = 1; + } + else + { + /* positive, start from 0 */ + *value = 0; + sign = 0; + } + /* OR/AND octets with value */ + while (len > 1) + { + len--; + if (sign) + { + *lsb_ptr &= *msg_ptr; + *value <<= 8; + *lsb_ptr |= 255; + } + else + { + *lsb_ptr |= *msg_ptr; + *value <<= 8; + } + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + if (sign) + { + *lsb_ptr &= *msg_ptr; + } + else + { + *lsb_ptr |= *msg_ptr; + } + return ERR_OK; + } + else + { + return ERR_ARG; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes object identifier from incoming message into array of s32_t. + * + * @param p points to a pbuf holding an ASN1 coded object identifier + * @param ofs points to the offset within the pbuf chain of the ASN1 coded object identifier + * @param len length of the coded object identifier + * @param oid return object identifier struct + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid) +{ + u16_t plen, base; + u8_t *msg_ptr; + s32_t *oid_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + oid->len = 0; + oid_ptr = &oid->id[0]; + if (len > 0) + { + /* first compressed octet */ + if (*msg_ptr == 0x2B) + { + /* (most) common case 1.3 (iso.org) */ + *oid_ptr = 1; + oid_ptr++; + *oid_ptr = 3; + oid_ptr++; + } + else if (*msg_ptr < 40) + { + *oid_ptr = 0; + oid_ptr++; + *oid_ptr = *msg_ptr; + oid_ptr++; + } + else if (*msg_ptr < 80) + { + *oid_ptr = 1; + oid_ptr++; + *oid_ptr = (*msg_ptr) - 40; + oid_ptr++; + } + else + { + *oid_ptr = 2; + oid_ptr++; + *oid_ptr = (*msg_ptr) - 80; + oid_ptr++; + } + oid->len = 2; + } + else + { + /* accepting zero length identifiers e.g. for + getnext operation. uncommon but valid */ + return ERR_OK; + } + len--; + if (len > 0) + { + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + while ((len > 0) && (oid->len < LWIP_SNMP_OBJ_ID_LEN)) + { + /* sub-identifier uses multiple octets */ + if (*msg_ptr & 0x80) + { + s32_t sub_id = 0; + + while ((*msg_ptr & 0x80) && (len > 1)) + { + len--; + sub_id = (sub_id << 7) + (*msg_ptr & ~0x80); + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + if (!(*msg_ptr & 0x80) && (len > 0)) + { + /* last octet sub-identifier */ + len--; + sub_id = (sub_id << 7) + *msg_ptr; + *oid_ptr = sub_id; + } + } + else + { + /* !(*msg_ptr & 0x80) sub-identifier uses single octet */ + len--; + *oid_ptr = *msg_ptr; + } + if (len > 0) + { + /* remaining oid bytes available ... */ + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + oid_ptr++; + oid->len++; + } + if (len == 0) + { + /* len == 0, end of oid */ + return ERR_OK; + } + else + { + /* len > 0, oid->len == LWIP_SNMP_OBJ_ID_LEN or malformed encoding */ + return ERR_ARG; + } + + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding) + * from incoming message into array. + * + * @param p points to a pbuf holding an ASN1 coded raw data + * @param ofs points to the offset within the pbuf chain of the ASN1 coded raw data + * @param len length of the coded raw data (zero is valid, e.g. empty string!) + * @param raw_len length of the raw return value + * @param raw return raw bytes + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw) +{ + u16_t plen, base; + u8_t *msg_ptr; + + if (len > 0) + { + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + if (raw_len >= len) + { + while (len > 1) + { + /* copy len - 1 octets */ + len--; + *raw = *msg_ptr; + raw++; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* copy last octet */ + *raw = *msg_ptr; + return ERR_OK; + } + else + { + /* raw_len < len, not enough dst space */ + return ERR_ARG; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; + } + else + { + /* len == 0, empty string */ + return ERR_OK; + } +} + +#endif /* LWIP_SNMP */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/asn1_enc.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/asn1_enc.c new file mode 100644 index 0000000..80f8d37 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/asn1_enc.c @@ -0,0 +1,610 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) encoding + * + * @todo not optimised (yet), favor correctness over speed, favor speed over size + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "lwip/snmp_asn1.h" + +/** + * Returns octet count for length. + * + * @param length + * @param octets_needed points to the return value + */ +void +snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed) +{ + if (length < 0x80U) + { + *octets_needed = 1; + } + else if (length < 0x100U) + { + *octets_needed = 2; + } + else + { + *octets_needed = 3; + } +} + +/** + * Returns octet count for an u32_t. + * + * @param value + * @param octets_needed points to the return value + * + * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded + * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value + * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! + */ +void +snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed) +{ + if (value < 0x80UL) + { + *octets_needed = 1; + } + else if (value < 0x8000UL) + { + *octets_needed = 2; + } + else if (value < 0x800000UL) + { + *octets_needed = 3; + } + else if (value < 0x80000000UL) + { + *octets_needed = 4; + } + else + { + *octets_needed = 5; + } +} + +/** + * Returns octet count for an s32_t. + * + * @param value + * @param octets_needed points to the return value + * + * @note ASN coded integers are _always_ signed. + */ +void +snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed) +{ + if (value < 0) + { + value = ~value; + } + if (value < 0x80L) + { + *octets_needed = 1; + } + else if (value < 0x8000L) + { + *octets_needed = 2; + } + else if (value < 0x800000L) + { + *octets_needed = 3; + } + else + { + *octets_needed = 4; + } +} + +/** + * Returns octet count for an object identifier. + * + * @param ident_len object identifier array length + * @param ident points to object identifier array + * @param octets_needed points to the return value + */ +void +snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed) +{ + s32_t sub_id; + u8_t cnt; + + cnt = 0; + if (ident_len > 1) + { + /* compressed prefix in one octet */ + cnt++; + ident_len -= 2; + ident += 2; + } + while(ident_len > 0) + { + ident_len--; + sub_id = *ident; + + sub_id >>= 7; + cnt++; + while(sub_id > 0) + { + sub_id >>= 7; + cnt++; + } + ident++; + } + *octets_needed = cnt; +} + +/** + * Encodes ASN type field into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode value into + * @param ofs points to the offset within the pbuf chain + * @param type input ASN1 type + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + *msg_ptr = type; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes host order length field into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode length into + * @param ofs points to the offset within the pbuf chain + * @param length is the host order length to be encoded + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + if (length < 0x80) + { + *msg_ptr = length; + return ERR_OK; + } + else if (length < 0x100) + { + *msg_ptr = 0x81; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + *msg_ptr = length; + return ERR_OK; + } + else + { + u8_t i; + + /* length >= 0x100 && length <= 0xFFFF */ + *msg_ptr = 0x82; + i = 2; + while (i > 0) + { + i--; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + if (i == 0) + { + /* least significant length octet */ + *msg_ptr = length; + } + else + { + /* most significant length octet */ + *msg_ptr = length >> 8; + } + } + return ERR_OK; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes u32_t (counter, gauge, timeticks) into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode value into + * @param ofs points to the offset within the pbuf chain + * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt()) + * @param value is the host order u32_t value to be encoded + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + * + * @see snmp_asn1_enc_u32t_cnt() + */ +err_t +snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + if (octets_needed == 5) + { + /* not enough bits in 'value' add leading 0x00 */ + octets_needed--; + *msg_ptr = 0x00; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + while (octets_needed > 1) + { + octets_needed--; + *msg_ptr = value >> (octets_needed << 3); + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* (only) one least significant octet */ + *msg_ptr = value; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes s32_t integer into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode value into + * @param ofs points to the offset within the pbuf chain + * @param octets_needed encoding length (from snmp_asn1_enc_s32t_cnt()) + * @param value is the host order s32_t value to be encoded + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + * + * @see snmp_asn1_enc_s32t_cnt() + */ +err_t +snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + while (octets_needed > 1) + { + octets_needed--; + *msg_ptr = value >> (octets_needed << 3); + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* (only) one least significant octet */ + *msg_ptr = value; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes object identifier into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode oid into + * @param ofs points to the offset within the pbuf chain + * @param ident_len object identifier array length + * @param ident points to object identifier array + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + if (ident_len > 1) + { + if ((ident[0] == 1) && (ident[1] == 3)) + { + /* compressed (most common) prefix .iso.org */ + *msg_ptr = 0x2b; + } + else + { + /* calculate prefix */ + *msg_ptr = (ident[0] * 40) + ident[1]; + } + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + ident_len -= 2; + ident += 2; + } + else + { +/* @bug: allow empty varbinds for symmetry (we must decode them for getnext), allow partial compression?? */ + /* ident_len <= 1, at least we need zeroDotZero (0.0) (ident_len == 2) */ + return ERR_ARG; + } + while (ident_len > 0) + { + s32_t sub_id; + u8_t shift, tail; + + ident_len--; + sub_id = *ident; + tail = 0; + shift = 28; + while(shift > 0) + { + u8_t code; + + code = sub_id >> shift; + if ((code != 0) || (tail != 0)) + { + tail = 1; + *msg_ptr = code | 0x80; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + shift -= 7; + } + *msg_ptr = (u8_t)sub_id & 0x7F; + if (ident_len > 0) + { + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* proceed to next sub-identifier */ + ident++; + } + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes raw data (octet string, opaque) into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode raw data into + * @param ofs points to the offset within the pbuf chain + * @param raw_len raw data length + * @param raw points raw data + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + while (raw_len > 1) + { + /* copy raw_len - 1 octets */ + raw_len--; + *msg_ptr = *raw; + raw++; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + if (raw_len > 0) + { + /* copy last or single octet */ + *msg_ptr = *raw; + } + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/mib2.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/mib2.c new file mode 100644 index 0000000..035c8b1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/mib2.c @@ -0,0 +1,4021 @@ +/** + * @file + * Management Information Base II (RFC1213) objects and functions. + * + * @note the object identifiers for this MIB-2 and private MIB tree + * must be kept in sorted ascending order. This to ensure correct getnext operation. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "arch/cc.h" +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "lwip/snmp.h" +#include "lwip/netif.h" +#include "netif/etharp.h" +#include "lwip/ip.h" +#include "lwip/ip_frag.h" +#include "lwip/tcp.h" +#include "lwip/udp.h" +#include "lwip/snmp_asn1.h" +#include "lwip/snmp_structs.h" + +/** + * IANA assigned enterprise ID for lwIP is 26381 + * @see http://www.iana.org/assignments/enterprise-numbers + * + * @note this enterprise ID is assigned to the lwIP project, + * all object identifiers living under this ID are assigned + * by the lwIP maintainers (contact Christiaan Simons)! + * @note don't change this define, use snmp_set_sysobjid() + * + * If you need to create your own private MIB you'll need + * to apply for your own enterprise ID with IANA: + * http://www.iana.org/numbers.html + */ +#define SNMP_ENTERPRISE_ID 26381 +#define SNMP_SYSOBJID_LEN 7 +#define SNMP_SYSOBJID {1, 3, 6, 1, 4, 1, SNMP_ENTERPRISE_ID} + +#ifndef SNMP_SYSSERVICES +#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2)) +#endif + +static void system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void system_get_value(struct obj_def *od, u16_t len, void *value); +static u8_t system_set_test(struct obj_def *od, u16_t len, void *value); +static void system_set_value(struct obj_def *od, u16_t len, void *value); +static void interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void interfaces_get_value(struct obj_def *od, u16_t len, void *value); +static void ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ifentry_get_value(struct obj_def *od, u16_t len, void *value); +static void atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void atentry_get_value(struct obj_def *od, u16_t len, void *value); +static void ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_get_value(struct obj_def *od, u16_t len, void *value); +static u8_t ip_set_test(struct obj_def *od, u16_t len, void *value); +static void ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value); +static void ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value); +static void ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value); +static void icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void icmp_get_value(struct obj_def *od, u16_t len, void *value); +#if LWIP_TCP +static void tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void tcp_get_value(struct obj_def *od, u16_t len, void *value); +static void tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value); +#endif +static void udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void udp_get_value(struct obj_def *od, u16_t len, void *value); +static void udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void udpentry_get_value(struct obj_def *od, u16_t len, void *value); +static void snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void snmp_get_value(struct obj_def *od, u16_t len, void *value); +static u8_t snmp_set_test(struct obj_def *od, u16_t len, void *value); +static void snmp_set_value(struct obj_def *od, u16_t len, void *value); + + +/* snmp .1.3.6.1.2.1.11 */ +const mib_scalar_node snmp_scalar = { + &snmp_get_object_def, + &snmp_get_value, + &snmp_set_test, + &snmp_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t snmp_ids[28] = { + 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30 +}; +struct mib_node* const snmp_nodes[28] = { + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar +}; +const struct mib_array_node snmp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 28, + snmp_ids, + snmp_nodes +}; + +/* dot3 and EtherLike MIB not planned. (transmission .1.3.6.1.2.1.10) */ +/* historical (some say hysterical). (cmot .1.3.6.1.2.1.9) */ +/* lwIP has no EGP, thus may not implement it. (egp .1.3.6.1.2.1.8) */ + +/* udp .1.3.6.1.2.1.7 */ +/** index root node for udpTable */ +struct mib_list_rootnode udp_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t udpentry_ids[2] = { 1, 2 }; +struct mib_node* const udpentry_nodes[2] = { + (struct mib_node* const)&udp_root, (struct mib_node* const)&udp_root, +}; +const struct mib_array_node udpentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 2, + udpentry_ids, + udpentry_nodes +}; + +s32_t udptable_id = 1; +struct mib_node* udptable_node = (struct mib_node* const)&udpentry; +struct mib_ram_array_node udptable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &udptable_id, + &udptable_node +}; + +const mib_scalar_node udp_scalar = { + &udp_get_object_def, + &udp_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t udp_ids[5] = { 1, 2, 3, 4, 5 }; +struct mib_node* const udp_nodes[5] = { + (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar, + (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar, + (struct mib_node* const)&udptable +}; +const struct mib_array_node udp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 5, + udp_ids, + udp_nodes +}; + +/* tcp .1.3.6.1.2.1.6 */ +#if LWIP_TCP +/* only if the TCP protocol is available may implement this group */ +/** index root node for tcpConnTable */ +struct mib_list_rootnode tcpconntree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t tcpconnentry_ids[5] = { 1, 2, 3, 4, 5 }; +struct mib_node* const tcpconnentry_nodes[5] = { + (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root, + (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root, + (struct mib_node* const)&tcpconntree_root +}; +const struct mib_array_node tcpconnentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 5, + tcpconnentry_ids, + tcpconnentry_nodes +}; + +s32_t tcpconntable_id = 1; +struct mib_node* tcpconntable_node = (struct mib_node* const)&tcpconnentry; +struct mib_ram_array_node tcpconntable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, +/** @todo update maxlength when inserting / deleting from table + 0 when table is empty, 1 when more than one entry */ + 0, + &tcpconntable_id, + &tcpconntable_node +}; + +const mib_scalar_node tcp_scalar = { + &tcp_get_object_def, + &tcp_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t tcp_ids[15] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; +struct mib_node* const tcp_nodes[15] = { + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcpconntable, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar +}; +const struct mib_array_node tcp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 15, + tcp_ids, + tcp_nodes +}; +#endif + +/* icmp .1.3.6.1.2.1.5 */ +const mib_scalar_node icmp_scalar = { + &icmp_get_object_def, + &icmp_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t icmp_ids[26] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; +struct mib_node* const icmp_nodes[26] = { + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar +}; +const struct mib_array_node icmp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 26, + icmp_ids, + icmp_nodes +}; + +/** index root node for ipNetToMediaTable */ +struct mib_list_rootnode ipntomtree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t ipntomentry_ids[4] = { 1, 2, 3, 4 }; +struct mib_node* const ipntomentry_nodes[4] = { + (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root, + (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root +}; +const struct mib_array_node ipntomentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 4, + ipntomentry_ids, + ipntomentry_nodes +}; + +s32_t ipntomtable_id = 1; +struct mib_node* ipntomtable_node = (struct mib_node* const)&ipntomentry; +struct mib_ram_array_node ipntomtable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &ipntomtable_id, + &ipntomtable_node +}; + +/** index root node for ipRouteTable */ +struct mib_list_rootnode iprtetree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t iprteentry_ids[13] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }; +struct mib_node* const iprteentry_nodes[13] = { + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root +}; +const struct mib_array_node iprteentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 13, + iprteentry_ids, + iprteentry_nodes +}; + +s32_t iprtetable_id = 1; +struct mib_node* iprtetable_node = (struct mib_node* const)&iprteentry; +struct mib_ram_array_node iprtetable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &iprtetable_id, + &iprtetable_node +}; + +/** index root node for ipAddrTable */ +struct mib_list_rootnode ipaddrtree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t ipaddrentry_ids[5] = { 1, 2, 3, 4, 5 }; +struct mib_node* const ipaddrentry_nodes[5] = { + (struct mib_node* const)&ipaddrtree_root, + (struct mib_node* const)&ipaddrtree_root, + (struct mib_node* const)&ipaddrtree_root, + (struct mib_node* const)&ipaddrtree_root, + (struct mib_node* const)&ipaddrtree_root +}; +const struct mib_array_node ipaddrentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 5, + ipaddrentry_ids, + ipaddrentry_nodes +}; + +s32_t ipaddrtable_id = 1; +struct mib_node* ipaddrtable_node = (struct mib_node* const)&ipaddrentry; +struct mib_ram_array_node ipaddrtable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &ipaddrtable_id, + &ipaddrtable_node +}; + +/* ip .1.3.6.1.2.1.4 */ +const mib_scalar_node ip_scalar = { + &ip_get_object_def, + &ip_get_value, + &ip_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t ip_ids[23] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; +struct mib_node* const ip_nodes[23] = { + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ipaddrtable, + (struct mib_node* const)&iprtetable, (struct mib_node* const)&ipntomtable, + (struct mib_node* const)&ip_scalar +}; +const struct mib_array_node ip = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 23, + ip_ids, + ip_nodes +}; + +/** index root node for atTable */ +struct mib_list_rootnode arptree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t atentry_ids[3] = { 1, 2, 3 }; +struct mib_node* const atentry_nodes[3] = { + (struct mib_node* const)&arptree_root, + (struct mib_node* const)&arptree_root, + (struct mib_node* const)&arptree_root +}; +const struct mib_array_node atentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 3, + atentry_ids, + atentry_nodes +}; + +const s32_t attable_id = 1; +struct mib_node* const attable_node = (struct mib_node* const)&atentry; +const struct mib_array_node attable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 1, + &attable_id, + &attable_node +}; + +/* at .1.3.6.1.2.1.3 */ +s32_t at_id = 1; +struct mib_node* at_node = (struct mib_node* const)&attable; +struct mib_ram_array_node at = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &at_id, + &at_node +}; + +/** index root node for ifTable */ +struct mib_list_rootnode iflist_root = { + &ifentry_get_object_def, + &ifentry_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t ifentry_ids[22] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 }; +struct mib_node* const ifentry_nodes[22] = { + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root +}; +const struct mib_array_node ifentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 22, + ifentry_ids, + ifentry_nodes +}; + +s32_t iftable_id = 1; +struct mib_node* iftable_node = (struct mib_node* const)&ifentry; +struct mib_ram_array_node iftable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &iftable_id, + &iftable_node +}; + +/* interfaces .1.3.6.1.2.1.2 */ +const mib_scalar_node interfaces_scalar = { + &interfaces_get_object_def, + &interfaces_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t interfaces_ids[2] = { 1, 2 }; +struct mib_node* const interfaces_nodes[2] = { + (struct mib_node* const)&interfaces_scalar, (struct mib_node* const)&iftable +}; +const struct mib_array_node interfaces = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 2, + interfaces_ids, + interfaces_nodes +}; + + +/* 0 1 2 3 4 5 6 */ +/* system .1.3.6.1.2.1.1 */ +const mib_scalar_node sys_tem_scalar = { + &system_get_object_def, + &system_get_value, + &system_set_test, + &system_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t sys_tem_ids[7] = { 1, 2, 3, 4, 5, 6, 7 }; +struct mib_node* const sys_tem_nodes[7] = { + (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar, + (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar, + (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar, + (struct mib_node* const)&sys_tem_scalar +}; +/* work around name issue with 'sys_tem', some compiler(s?) seem to reserve 'system' */ +const struct mib_array_node sys_tem = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 7, + sys_tem_ids, + sys_tem_nodes +}; + +/* mib-2 .1.3.6.1.2.1 */ +#if LWIP_TCP +#define MIB2_GROUPS 8 +#else +#define MIB2_GROUPS 7 +#endif +const s32_t mib2_ids[MIB2_GROUPS] = +{ + 1, + 2, + 3, + 4, + 5, +#if LWIP_TCP + 6, +#endif + 7, + 11 +}; +struct mib_node* const mib2_nodes[MIB2_GROUPS] = { + (struct mib_node* const)&sys_tem, + (struct mib_node* const)&interfaces, + (struct mib_node* const)&at, + (struct mib_node* const)&ip, + (struct mib_node* const)&icmp, +#if LWIP_TCP + (struct mib_node* const)&tcp, +#endif + (struct mib_node* const)&udp, + (struct mib_node* const)&snmp +}; + +const struct mib_array_node mib2 = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + MIB2_GROUPS, + mib2_ids, + mib2_nodes +}; + +/* mgmt .1.3.6.1.2 */ +const s32_t mgmt_ids[1] = { 1 }; +struct mib_node* const mgmt_nodes[1] = { (struct mib_node* const)&mib2 }; +const struct mib_array_node mgmt = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 1, + mgmt_ids, + mgmt_nodes +}; + +/* internet .1.3.6.1 */ +#if SNMP_PRIVATE_MIB +s32_t internet_ids[2] = { 2, 4 }; +struct mib_node* const internet_nodes[2] = { (struct mib_node* const)&mgmt, (struct mib_node* const)&private }; +const struct mib_array_node internet = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 2, + internet_ids, + internet_nodes +}; +#else +const s32_t internet_ids[1] = { 2 }; +struct mib_node* const internet_nodes[1] = { (struct mib_node* const)&mgmt }; +const struct mib_array_node internet = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 1, + internet_ids, + internet_nodes +}; +#endif + +/** mib-2.system.sysObjectID */ +static struct snmp_obj_id sysobjid = {SNMP_SYSOBJID_LEN, SNMP_SYSOBJID}; +/** enterprise ID for generic TRAPs, .iso.org.dod.internet.mgmt.mib-2.snmp */ +static struct snmp_obj_id snmpgrp_id = {7,{1,3,6,1,2,1,11}}; +/** mib-2.system.sysServices */ +static const s32_t sysservices = SNMP_SYSSERVICES; + +/** mib-2.system.sysDescr */ +static const u8_t sysdescr_len_default = 4; +static const u8_t sysdescr_default[] = "lwIP"; +static u8_t* sysdescr_len_ptr = (u8_t*)&sysdescr_len_default; +static u8_t* sysdescr_ptr = (u8_t*)&sysdescr_default[0]; +/** mib-2.system.sysContact */ +static const u8_t syscontact_len_default = 0; +static const u8_t syscontact_default[] = ""; +static u8_t* syscontact_len_ptr = (u8_t*)&syscontact_len_default; +static u8_t* syscontact_ptr = (u8_t*)&syscontact_default[0]; +/** mib-2.system.sysName */ +static const u8_t sysname_len_default = 8; +static const u8_t sysname_default[] = "FQDN-unk"; +static u8_t* sysname_len_ptr = (u8_t*)&sysname_len_default; +static u8_t* sysname_ptr = (u8_t*)&sysname_default[0]; +/** mib-2.system.sysLocation */ +static const u8_t syslocation_len_default = 0; +static const u8_t syslocation_default[] = ""; +static u8_t* syslocation_len_ptr = (u8_t*)&syslocation_len_default; +static u8_t* syslocation_ptr = (u8_t*)&syslocation_default[0]; +/** mib-2.snmp.snmpEnableAuthenTraps */ +static const u8_t snmpenableauthentraps_default = 2; /* disabled */ +static u8_t* snmpenableauthentraps_ptr = (u8_t*)&snmpenableauthentraps_default; + +/** mib-2.interfaces.ifTable.ifEntry.ifSpecific (zeroDotZero) */ +static const struct snmp_obj_id ifspecific = {2, {0, 0}}; +/** mib-2.ip.ipRouteTable.ipRouteEntry.ipRouteInfo (zeroDotZero) */ +static const struct snmp_obj_id iprouteinfo = {2, {0, 0}}; + + + +/* mib-2.system counter(s) */ +static u32_t sysuptime = 0; + +/* mib-2.ip counter(s) */ +static u32_t ipinreceives = 0, + ipinhdrerrors = 0, + ipinaddrerrors = 0, + ipforwdatagrams = 0, + ipinunknownprotos = 0, + ipindiscards = 0, + ipindelivers = 0, + ipoutrequests = 0, + ipoutdiscards = 0, + ipoutnoroutes = 0, + ipreasmreqds = 0, + ipreasmoks = 0, + ipreasmfails = 0, + ipfragoks = 0, + ipfragfails = 0, + ipfragcreates = 0, + iproutingdiscards = 0; +/* mib-2.icmp counter(s) */ +static u32_t icmpinmsgs = 0, + icmpinerrors = 0, + icmpindestunreachs = 0, + icmpintimeexcds = 0, + icmpinparmprobs = 0, + icmpinsrcquenchs = 0, + icmpinredirects = 0, + icmpinechos = 0, + icmpinechoreps = 0, + icmpintimestamps = 0, + icmpintimestampreps = 0, + icmpinaddrmasks = 0, + icmpinaddrmaskreps = 0, + icmpoutmsgs = 0, + icmpouterrors = 0, + icmpoutdestunreachs = 0, + icmpouttimeexcds = 0, + icmpoutparmprobs = 0, + icmpoutsrcquenchs = 0, + icmpoutredirects = 0, + icmpoutechos = 0, + icmpoutechoreps = 0, + icmpouttimestamps = 0, + icmpouttimestampreps = 0, + icmpoutaddrmasks = 0, + icmpoutaddrmaskreps = 0; +/* mib-2.tcp counter(s) */ +static u32_t tcpactiveopens = 0, + tcppassiveopens = 0, + tcpattemptfails = 0, + tcpestabresets = 0, + tcpinsegs = 0, + tcpoutsegs = 0, + tcpretranssegs = 0, + tcpinerrs = 0, + tcpoutrsts = 0; +/* mib-2.udp counter(s) */ +static u32_t udpindatagrams = 0, + udpnoports = 0, + udpinerrors = 0, + udpoutdatagrams = 0; +/* mib-2.snmp counter(s) */ +static u32_t snmpinpkts = 0, + snmpoutpkts = 0, + snmpinbadversions = 0, + snmpinbadcommunitynames = 0, + snmpinbadcommunityuses = 0, + snmpinasnparseerrs = 0, + snmpintoobigs = 0, + snmpinnosuchnames = 0, + snmpinbadvalues = 0, + snmpinreadonlys = 0, + snmpingenerrs = 0, + snmpintotalreqvars = 0, + snmpintotalsetvars = 0, + snmpingetrequests = 0, + snmpingetnexts = 0, + snmpinsetrequests = 0, + snmpingetresponses = 0, + snmpintraps = 0, + snmpouttoobigs = 0, + snmpoutnosuchnames = 0, + snmpoutbadvalues = 0, + snmpoutgenerrs = 0, + snmpoutgetrequests = 0, + snmpoutgetnexts = 0, + snmpoutsetrequests = 0, + snmpoutgetresponses = 0, + snmpouttraps = 0; + + + +/* prototypes of the following functions are in lwip/src/include/lwip/snmp.h */ +/** + * Copy octet string. + * + * @param dst points to destination + * @param src points to source + * @param n number of octets to copy. + */ +void ocstrncpy(u8_t *dst, u8_t *src, u8_t n) +{ + while (n > 0) + { + n--; + *dst++ = *src++; + } +} + +/** + * Copy object identifier (s32_t) array. + * + * @param dst points to destination + * @param src points to source + * @param n number of sub identifiers to copy. + */ +void objectidncpy(s32_t *dst, s32_t *src, u8_t n) +{ + while(n > 0) + { + n--; + *dst++ = *src++; + } +} + +/** + * Initializes sysDescr pointers. + * + * @param str if non-NULL then copy str pointer + * @param strlen points to string length, excluding zero terminator + */ +void snmp_set_sysdesr(u8_t *str, u8_t *strlen) +{ + if (str != NULL) + { + sysdescr_ptr = str; + sysdescr_len_ptr = strlen; + } +} + +void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid) +{ + *oid = &sysobjid; +} + +/** + * Initializes sysObjectID value. + * + * @param oid points to stuct snmp_obj_id to copy + */ +void snmp_set_sysobjid(struct snmp_obj_id *oid) +{ + sysobjid = *oid; +} + +/** + * Must be called at regular 10 msec interval from a timer interrupt + * or signal handler depending on your runtime environment. + */ +void snmp_inc_sysuptime(void) +{ + sysuptime++; +} + +void snmp_get_sysuptime(u32_t *value) +{ + *value = sysuptime; +} + +/** + * Initializes sysContact pointers, + * e.g. ptrs to non-volatile memory external to lwIP. + * + * @param str if non-NULL then copy str pointer + * @param strlen points to string length, excluding zero terminator + */ +void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen) +{ + if (ocstr != NULL) + { + syscontact_ptr = ocstr; + syscontact_len_ptr = ocstrlen; + } +} + +/** + * Initializes sysName pointers, + * e.g. ptrs to non-volatile memory external to lwIP. + * + * @param str if non-NULL then copy str pointer + * @param strlen points to string length, excluding zero terminator + */ +void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen) +{ + if (ocstr != NULL) + { + sysname_ptr = ocstr; + sysname_len_ptr = ocstrlen; + } +} + +/** + * Initializes sysLocation pointers, + * e.g. ptrs to non-volatile memory external to lwIP. + * + * @param str if non-NULL then copy str pointer + * @param strlen points to string length, excluding zero terminator + */ +void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen) +{ + if (ocstr != NULL) + { + syslocation_ptr = ocstr; + syslocation_len_ptr = ocstrlen; + } +} + + +void snmp_add_ifinoctets(struct netif *ni, u32_t value) +{ + ni->ifinoctets += value; +} + +void snmp_inc_ifinucastpkts(struct netif *ni) +{ + (ni->ifinucastpkts)++; +} + +void snmp_inc_ifinnucastpkts(struct netif *ni) +{ + (ni->ifinnucastpkts)++; +} + +void snmp_inc_ifindiscards(struct netif *ni) +{ + (ni->ifindiscards)++; +} + +void snmp_add_ifoutoctets(struct netif *ni, u32_t value) +{ + ni->ifoutoctets += value; +} + +void snmp_inc_ifoutucastpkts(struct netif *ni) +{ + (ni->ifoutucastpkts)++; +} + +void snmp_inc_ifoutnucastpkts(struct netif *ni) +{ + (ni->ifoutnucastpkts)++; +} + +void snmp_inc_ifoutdiscards(struct netif *ni) +{ + (ni->ifoutdiscards)++; +} + +void snmp_inc_iflist(void) +{ + struct mib_list_node *if_node = NULL; + + snmp_mib_node_insert(&iflist_root, iflist_root.count + 1, &if_node); + /* enable getnext traversal on filled table */ + iftable.maxlength = 1; +} + +void snmp_dec_iflist(void) +{ + snmp_mib_node_delete(&iflist_root, iflist_root.tail); + /* disable getnext traversal on empty table */ + if(iflist_root.count == 0) iftable.maxlength = 0; +} + +/** + * Inserts ARP table indexes (.xIfIndex.xNetAddress) + * into arp table index trees (both atTable and ipNetToMediaTable). + */ +void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip) +{ + struct mib_list_rootnode *at_rn; + struct mib_list_node *at_node; + struct ip_addr hip; + s32_t arpidx[5]; + u8_t level, tree; + + LWIP_ASSERT("ni != NULL", ni != NULL); + snmp_netiftoifindex(ni, &arpidx[0]); + hip.addr = ntohl(ip->addr); + snmp_iptooid(&hip, &arpidx[1]); + + for (tree = 0; tree < 2; tree++) + { + if (tree == 0) + { + at_rn = &arptree_root; + } + else + { + at_rn = &ipntomtree_root; + } + for (level = 0; level < 5; level++) + { + at_node = NULL; + snmp_mib_node_insert(at_rn, arpidx[level], &at_node); + if ((level != 4) && (at_node != NULL)) + { + if (at_node->nptr == NULL) + { + at_rn = snmp_mib_lrn_alloc(); + at_node->nptr = (struct mib_node*)at_rn; + if (at_rn != NULL) + { + if (level == 3) + { + if (tree == 0) + { + at_rn->get_object_def = atentry_get_object_def; + at_rn->get_value = atentry_get_value; + } + else + { + at_rn->get_object_def = ip_ntomentry_get_object_def; + at_rn->get_value = ip_ntomentry_get_value; + } + at_rn->set_test = noleafs_set_test; + at_rn->set_value = noleafs_set_value; + } + } + else + { + /* at_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_arpidx_tree() insert failed, mem full")); + break; + } + } + else + { + at_rn = (struct mib_list_rootnode*)at_node->nptr; + } + } + } + } + /* enable getnext traversal on filled tables */ + at.maxlength = 1; + ipntomtable.maxlength = 1; +} + +/** + * Removes ARP table indexes (.xIfIndex.xNetAddress) + * from arp table index trees. + */ +void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip) +{ + struct mib_list_rootnode *at_rn, *next, *del_rn[5]; + struct mib_list_node *at_n, *del_n[5]; + struct ip_addr hip; + s32_t arpidx[5]; + u8_t fc, tree, level, del_cnt; + + snmp_netiftoifindex(ni, &arpidx[0]); + hip.addr = ntohl(ip->addr); + snmp_iptooid(&hip, &arpidx[1]); + + for (tree = 0; tree < 2; tree++) + { + /* mark nodes for deletion */ + if (tree == 0) + { + at_rn = &arptree_root; + } + else + { + at_rn = &ipntomtree_root; + } + level = 0; + del_cnt = 0; + while ((level < 5) && (at_rn != NULL)) + { + fc = snmp_mib_node_find(at_rn, arpidx[level], &at_n); + if (fc == 0) + { + /* arpidx[level] does not exist */ + del_cnt = 0; + at_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = at_rn; + del_n[del_cnt] = at_n; + del_cnt++; + at_rn = (struct mib_list_rootnode*)(at_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + at_rn = (struct mib_list_rootnode*)(at_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + at_rn = del_rn[del_cnt]; + at_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(at_rn, at_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + } + /* disable getnext traversal on empty tables */ + if(arptree_root.count == 0) at.maxlength = 0; + if(ipntomtree_root.count == 0) ipntomtable.maxlength = 0; +} + +void snmp_inc_ipinreceives(void) +{ + ipinreceives++; +} + +void snmp_inc_ipinhdrerrors(void) +{ + ipinhdrerrors++; +} + +void snmp_inc_ipinaddrerrors(void) +{ + ipinaddrerrors++; +} + +void snmp_inc_ipforwdatagrams(void) +{ + ipforwdatagrams++; +} + +void snmp_inc_ipinunknownprotos(void) +{ + ipinunknownprotos++; +} + +void snmp_inc_ipindiscards(void) +{ + ipindiscards++; +} + +void snmp_inc_ipindelivers(void) +{ + ipindelivers++; +} + +void snmp_inc_ipoutrequests(void) +{ + ipoutrequests++; +} + +void snmp_inc_ipoutdiscards(void) +{ + ipoutdiscards++; +} + +void snmp_inc_ipoutnoroutes(void) +{ + ipoutnoroutes++; +} + +void snmp_inc_ipreasmreqds(void) +{ + ipreasmreqds++; +} + +void snmp_inc_ipreasmoks(void) +{ + ipreasmoks++; +} + +void snmp_inc_ipreasmfails(void) +{ + ipreasmfails++; +} + +void snmp_inc_ipfragoks(void) +{ + ipfragoks++; +} + +void snmp_inc_ipfragfails(void) +{ + ipfragfails++; +} + +void snmp_inc_ipfragcreates(void) +{ + ipfragcreates++; +} + +void snmp_inc_iproutingdiscards(void) +{ + iproutingdiscards++; +} + +/** + * Inserts ipAddrTable indexes (.ipAdEntAddr) + * into index tree. + */ +void snmp_insert_ipaddridx_tree(struct netif *ni) +{ + struct mib_list_rootnode *ipa_rn; + struct mib_list_node *ipa_node; + struct ip_addr ip; + s32_t ipaddridx[4]; + u8_t level; + + LWIP_ASSERT("ni != NULL", ni != NULL); + ip.addr = ntohl(ni->ip_addr.addr); + snmp_iptooid(&ip, &ipaddridx[0]); + + level = 0; + ipa_rn = &ipaddrtree_root; + while (level < 4) + { + ipa_node = NULL; + snmp_mib_node_insert(ipa_rn, ipaddridx[level], &ipa_node); + if ((level != 3) && (ipa_node != NULL)) + { + if (ipa_node->nptr == NULL) + { + ipa_rn = snmp_mib_lrn_alloc(); + ipa_node->nptr = (struct mib_node*)ipa_rn; + if (ipa_rn != NULL) + { + if (level == 2) + { + ipa_rn->get_object_def = ip_addrentry_get_object_def; + ipa_rn->get_value = ip_addrentry_get_value; + ipa_rn->set_test = noleafs_set_test; + ipa_rn->set_value = noleafs_set_value; + } + } + else + { + /* ipa_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_ipaddridx_tree() insert failed, mem full")); + break; + } + } + else + { + ipa_rn = (struct mib_list_rootnode*)ipa_node->nptr; + } + } + level++; + } + /* enable getnext traversal on filled table */ + ipaddrtable.maxlength = 1; +} + +/** + * Removes ipAddrTable indexes (.ipAdEntAddr) + * from index tree. + */ +void snmp_delete_ipaddridx_tree(struct netif *ni) +{ + struct mib_list_rootnode *ipa_rn, *next, *del_rn[4]; + struct mib_list_node *ipa_n, *del_n[4]; + struct ip_addr ip; + s32_t ipaddridx[4]; + u8_t fc, level, del_cnt; + + LWIP_ASSERT("ni != NULL", ni != NULL); + ip.addr = ntohl(ni->ip_addr.addr); + snmp_iptooid(&ip, &ipaddridx[0]); + + /* mark nodes for deletion */ + level = 0; + del_cnt = 0; + ipa_rn = &ipaddrtree_root; + while ((level < 4) && (ipa_rn != NULL)) + { + fc = snmp_mib_node_find(ipa_rn, ipaddridx[level], &ipa_n); + if (fc == 0) + { + /* ipaddridx[level] does not exist */ + del_cnt = 0; + ipa_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = ipa_rn; + del_n[del_cnt] = ipa_n; + del_cnt++; + ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + ipa_rn = del_rn[del_cnt]; + ipa_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(ipa_rn, ipa_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + /* disable getnext traversal on empty table */ + if (ipaddrtree_root.count == 0) ipaddrtable.maxlength = 0; +} + +/** + * Inserts ipRouteTable indexes (.ipRouteDest) + * into index tree. + * + * @param dflt non-zero for the default rte, zero for network rte + * @param netif points to network interface for this rte + * + * @todo record sysuptime for _this_ route when it is installed + * (needed for ipRouteAge) in the netif. + */ +void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni) +{ + u8_t insert = 0; + struct ip_addr dst; + + if (dflt != 0) + { + /* the default route 0.0.0.0 */ + dst.addr = 0; + insert = 1; + } + else + { + /* route to the network address */ + dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr); + /* exclude 0.0.0.0 network (reserved for default rte) */ + if (dst.addr != 0) insert = 1; + } + if (insert) + { + struct mib_list_rootnode *iprte_rn; + struct mib_list_node *iprte_node; + s32_t iprteidx[4]; + u8_t level; + + snmp_iptooid(&dst, &iprteidx[0]); + level = 0; + iprte_rn = &iprtetree_root; + while (level < 4) + { + iprte_node = NULL; + snmp_mib_node_insert(iprte_rn, iprteidx[level], &iprte_node); + if ((level != 3) && (iprte_node != NULL)) + { + if (iprte_node->nptr == NULL) + { + iprte_rn = snmp_mib_lrn_alloc(); + iprte_node->nptr = (struct mib_node*)iprte_rn; + if (iprte_rn != NULL) + { + if (level == 2) + { + iprte_rn->get_object_def = ip_rteentry_get_object_def; + iprte_rn->get_value = ip_rteentry_get_value; + iprte_rn->set_test = noleafs_set_test; + iprte_rn->set_value = noleafs_set_value; + } + } + else + { + /* iprte_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_iprteidx_tree() insert failed, mem full")); + break; + } + } + else + { + iprte_rn = (struct mib_list_rootnode*)iprte_node->nptr; + } + } + level++; + } + } + /* enable getnext traversal on filled table */ + iprtetable.maxlength = 1; +} + +/** + * Removes ipRouteTable indexes (.ipRouteDest) + * from index tree. + * + * @param dflt non-zero for the default rte, zero for network rte + * @param netif points to network interface for this rte or NULL + * for default route to be removed. + */ +void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni) +{ + u8_t delete = 0; + struct ip_addr dst; + + if (dflt != 0) + { + /* the default route 0.0.0.0 */ + dst.addr = 0; + delete = 1; + } + else + { + /* route to the network address */ + dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr); + /* exclude 0.0.0.0 network (reserved for default rte) */ + if (dst.addr != 0) delete = 1; + } + if (delete) + { + struct mib_list_rootnode *iprte_rn, *next, *del_rn[4]; + struct mib_list_node *iprte_n, *del_n[4]; + s32_t iprteidx[4]; + u8_t fc, level, del_cnt; + + snmp_iptooid(&dst, &iprteidx[0]); + /* mark nodes for deletion */ + level = 0; + del_cnt = 0; + iprte_rn = &iprtetree_root; + while ((level < 4) && (iprte_rn != NULL)) + { + fc = snmp_mib_node_find(iprte_rn, iprteidx[level], &iprte_n); + if (fc == 0) + { + /* iprteidx[level] does not exist */ + del_cnt = 0; + iprte_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = iprte_rn; + del_n[del_cnt] = iprte_n; + del_cnt++; + iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + iprte_rn = del_rn[del_cnt]; + iprte_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(iprte_rn, iprte_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + } + /* disable getnext traversal on empty table */ + if (iprtetree_root.count == 0) iprtetable.maxlength = 0; +} + + +void snmp_inc_icmpinmsgs(void) +{ + icmpinmsgs++; +} + +void snmp_inc_icmpinerrors(void) +{ + icmpinerrors++; +} + +void snmp_inc_icmpindestunreachs(void) +{ + icmpindestunreachs++; +} + +void snmp_inc_icmpintimeexcds(void) +{ + icmpintimeexcds++; +} + +void snmp_inc_icmpinparmprobs(void) +{ + icmpinparmprobs++; +} + +void snmp_inc_icmpinsrcquenchs(void) +{ + icmpinsrcquenchs++; +} + +void snmp_inc_icmpinredirects(void) +{ + icmpinredirects++; +} + +void snmp_inc_icmpinechos(void) +{ + icmpinechos++; +} + +void snmp_inc_icmpinechoreps(void) +{ + icmpinechoreps++; +} + +void snmp_inc_icmpintimestamps(void) +{ + icmpintimestamps++; +} + +void snmp_inc_icmpintimestampreps(void) +{ + icmpintimestampreps++; +} + +void snmp_inc_icmpinaddrmasks(void) +{ + icmpinaddrmasks++; +} + +void snmp_inc_icmpinaddrmaskreps(void) +{ + icmpinaddrmaskreps++; +} + +void snmp_inc_icmpoutmsgs(void) +{ + icmpoutmsgs++; +} + +void snmp_inc_icmpouterrors(void) +{ + icmpouterrors++; +} + +void snmp_inc_icmpoutdestunreachs(void) +{ + icmpoutdestunreachs++; +} + +void snmp_inc_icmpouttimeexcds(void) +{ + icmpouttimeexcds++; +} + +void snmp_inc_icmpoutparmprobs(void) +{ + icmpoutparmprobs++; +} + +void snmp_inc_icmpoutsrcquenchs(void) +{ + icmpoutsrcquenchs++; +} + +void snmp_inc_icmpoutredirects(void) +{ + icmpoutredirects++; +} + +void snmp_inc_icmpoutechos(void) +{ + icmpoutechos++; +} + +void snmp_inc_icmpoutechoreps(void) +{ + icmpoutechoreps++; +} + +void snmp_inc_icmpouttimestamps(void) +{ + icmpouttimestamps++; +} + +void snmp_inc_icmpouttimestampreps(void) +{ + icmpouttimestampreps++; +} + +void snmp_inc_icmpoutaddrmasks(void) +{ + icmpoutaddrmasks++; +} + +void snmp_inc_icmpoutaddrmaskreps(void) +{ + icmpoutaddrmaskreps++; +} + +void snmp_inc_tcpactiveopens(void) +{ + tcpactiveopens++; +} + +void snmp_inc_tcppassiveopens(void) +{ + tcppassiveopens++; +} + +void snmp_inc_tcpattemptfails(void) +{ + tcpattemptfails++; +} + +void snmp_inc_tcpestabresets(void) +{ + tcpestabresets++; +} + +void snmp_inc_tcpinsegs(void) +{ + tcpinsegs++; +} + +void snmp_inc_tcpoutsegs(void) +{ + tcpoutsegs++; +} + +void snmp_inc_tcpretranssegs(void) +{ + tcpretranssegs++; +} + +void snmp_inc_tcpinerrs(void) +{ + tcpinerrs++; +} + +void snmp_inc_tcpoutrsts(void) +{ + tcpoutrsts++; +} + +void snmp_inc_udpindatagrams(void) +{ + udpindatagrams++; +} + +void snmp_inc_udpnoports(void) +{ + udpnoports++; +} + +void snmp_inc_udpinerrors(void) +{ + udpinerrors++; +} + +void snmp_inc_udpoutdatagrams(void) +{ + udpoutdatagrams++; +} + +/** + * Inserts udpTable indexes (.udpLocalAddress.udpLocalPort) + * into index tree. + */ +void snmp_insert_udpidx_tree(struct udp_pcb *pcb) +{ + struct mib_list_rootnode *udp_rn; + struct mib_list_node *udp_node; + struct ip_addr ip; + s32_t udpidx[5]; + u8_t level; + + LWIP_ASSERT("pcb != NULL", pcb != NULL); + ip.addr = ntohl(pcb->local_ip.addr); + snmp_iptooid(&ip, &udpidx[0]); + udpidx[4] = pcb->local_port; + + udp_rn = &udp_root; + for (level = 0; level < 5; level++) + { + udp_node = NULL; + snmp_mib_node_insert(udp_rn, udpidx[level], &udp_node); + if ((level != 4) && (udp_node != NULL)) + { + if (udp_node->nptr == NULL) + { + udp_rn = snmp_mib_lrn_alloc(); + udp_node->nptr = (struct mib_node*)udp_rn; + if (udp_rn != NULL) + { + if (level == 3) + { + udp_rn->get_object_def = udpentry_get_object_def; + udp_rn->get_value = udpentry_get_value; + udp_rn->set_test = noleafs_set_test; + udp_rn->set_value = noleafs_set_value; + } + } + else + { + /* udp_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_udpidx_tree() insert failed, mem full")); + break; + } + } + else + { + udp_rn = (struct mib_list_rootnode*)udp_node->nptr; + } + } + } + udptable.maxlength = 1; +} + +/** + * Removes udpTable indexes (.udpLocalAddress.udpLocalPort) + * from index tree. + */ +void snmp_delete_udpidx_tree(struct udp_pcb *pcb) +{ + struct mib_list_rootnode *udp_rn, *next, *del_rn[5]; + struct mib_list_node *udp_n, *del_n[5]; + struct ip_addr ip; + s32_t udpidx[5]; + u8_t bindings, fc, level, del_cnt; + + LWIP_ASSERT("pcb != NULL", pcb != NULL); + ip.addr = ntohl(pcb->local_ip.addr); + snmp_iptooid(&ip, &udpidx[0]); + udpidx[4] = pcb->local_port; + + /* count PCBs for a given binding + (e.g. when reusing ports or for temp output PCBs) */ + bindings = 0; + pcb = udp_pcbs; + while ((pcb != NULL)) + { + if ((pcb->local_ip.addr == ip.addr) && + (pcb->local_port == udpidx[4])) + { + bindings++; + } + pcb = pcb->next; + } + if (bindings == 1) + { + /* selectively remove */ + /* mark nodes for deletion */ + level = 0; + del_cnt = 0; + udp_rn = &udp_root; + while ((level < 5) && (udp_rn != NULL)) + { + fc = snmp_mib_node_find(udp_rn, udpidx[level], &udp_n); + if (fc == 0) + { + /* udpidx[level] does not exist */ + del_cnt = 0; + udp_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = udp_rn; + del_n[del_cnt] = udp_n; + del_cnt++; + udp_rn = (struct mib_list_rootnode*)(udp_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + udp_rn = (struct mib_list_rootnode*)(udp_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + udp_rn = del_rn[del_cnt]; + udp_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(udp_rn, udp_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + } + /* disable getnext traversal on empty table */ + if (udp_root.count == 0) udptable.maxlength = 0; +} + + +void snmp_inc_snmpinpkts(void) +{ + snmpinpkts++; +} + +void snmp_inc_snmpoutpkts(void) +{ + snmpoutpkts++; +} + +void snmp_inc_snmpinbadversions(void) +{ + snmpinbadversions++; +} + +void snmp_inc_snmpinbadcommunitynames(void) +{ + snmpinbadcommunitynames++; +} + +void snmp_inc_snmpinbadcommunityuses(void) +{ + snmpinbadcommunityuses++; +} + +void snmp_inc_snmpinasnparseerrs(void) +{ + snmpinasnparseerrs++; +} + +void snmp_inc_snmpintoobigs(void) +{ + snmpintoobigs++; +} + +void snmp_inc_snmpinnosuchnames(void) +{ + snmpinnosuchnames++; +} + +void snmp_inc_snmpinbadvalues(void) +{ + snmpinbadvalues++; +} + +void snmp_inc_snmpinreadonlys(void) +{ + snmpinreadonlys++; +} + +void snmp_inc_snmpingenerrs(void) +{ + snmpingenerrs++; +} + +void snmp_add_snmpintotalreqvars(u8_t value) +{ + snmpintotalreqvars += value; +} + +void snmp_add_snmpintotalsetvars(u8_t value) +{ + snmpintotalsetvars += value; +} + +void snmp_inc_snmpingetrequests(void) +{ + snmpingetrequests++; +} + +void snmp_inc_snmpingetnexts(void) +{ + snmpingetnexts++; +} + +void snmp_inc_snmpinsetrequests(void) +{ + snmpinsetrequests++; +} + +void snmp_inc_snmpingetresponses(void) +{ + snmpingetresponses++; +} + +void snmp_inc_snmpintraps(void) +{ + snmpintraps++; +} + +void snmp_inc_snmpouttoobigs(void) +{ + snmpouttoobigs++; +} + +void snmp_inc_snmpoutnosuchnames(void) +{ + snmpoutnosuchnames++; +} + +void snmp_inc_snmpoutbadvalues(void) +{ + snmpoutbadvalues++; +} + +void snmp_inc_snmpoutgenerrs(void) +{ + snmpoutgenerrs++; +} + +void snmp_inc_snmpoutgetrequests(void) +{ + snmpoutgetrequests++; +} + +void snmp_inc_snmpoutgetnexts(void) +{ + snmpoutgetnexts++; +} + +void snmp_inc_snmpoutsetrequests(void) +{ + snmpoutsetrequests++; +} + +void snmp_inc_snmpoutgetresponses(void) +{ + snmpoutgetresponses++; +} + +void snmp_inc_snmpouttraps(void) +{ + snmpouttraps++; +} + +void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid) +{ + *oid = &snmpgrp_id; +} + +void snmp_set_snmpenableauthentraps(u8_t *value) +{ + if (value != NULL) + { + snmpenableauthentraps_ptr = value; + } +} + +void snmp_get_snmpenableauthentraps(u8_t *value) +{ + *value = *snmpenableauthentraps_ptr; +} + +void +noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + if (ident_len){} + if (ident){} + od->instance = MIB_OBJECT_NONE; +} + +void +noleafs_get_value(struct obj_def *od, u16_t len, void *value) +{ + if (od){} + if (len){} + if (value){} +} + +u8_t +noleafs_set_test(struct obj_def *od, u16_t len, void *value) +{ + if (od){} + if (len){} + if (value){} + /* can't set */ + return 0; +} + +void +noleafs_set_value(struct obj_def *od, u16_t len, void *value) +{ + if (od){} + if (len){} + if (value){} +} + + +/** + * Returns systems object definitions. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param od points to object definition. + */ +static void +system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def system.%"U16_F".0\n",(u16_t)id)); + switch (id) + { + case 1: /* sysDescr */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *sysdescr_len_ptr; + break; + case 2: /* sysObjectID */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); + od->v_len = sysobjid.len * sizeof(s32_t); + break; + case 3: /* sysUpTime */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS); + od->v_len = sizeof(u32_t); + break; + case 4: /* sysContact */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *syscontact_len_ptr; + break; + case 5: /* sysName */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *sysname_len_ptr; + break; + case 6: /* sysLocation */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *syslocation_len_ptr; + break; + case 7: /* sysServices */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +/** + * Returns system object value. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value into. + */ +static void +system_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* sysDescr */ + ocstrncpy(value,sysdescr_ptr,len); + break; + case 2: /* sysObjectID */ + objectidncpy((s32_t*)value,(s32_t*)sysobjid.id,len / sizeof(s32_t)); + break; + case 3: /* sysUpTime */ + { + u32_t *uint_ptr = value; + *uint_ptr = sysuptime; + } + break; + case 4: /* sysContact */ + ocstrncpy(value,syscontact_ptr,len); + break; + case 5: /* sysName */ + ocstrncpy(value,sysname_ptr,len); + break; + case 6: /* sysLocation */ + ocstrncpy(value,syslocation_ptr,len); + break; + case 7: /* sysServices */ + { + s32_t *sint_ptr = value; + *sint_ptr = sysservices; + } + break; + }; +} + +static u8_t +system_set_test(struct obj_def *od, u16_t len, void *value) +{ + u8_t id, set_ok; + + if (value) {} + set_ok = 0; + id = od->id_inst_ptr[0]; + switch (id) + { + case 4: /* sysContact */ + if ((syscontact_ptr != syscontact_default) && + (len <= 255)) + { + set_ok = 1; + } + break; + case 5: /* sysName */ + if ((sysname_ptr != sysname_default) && + (len <= 255)) + { + set_ok = 1; + } + break; + case 6: /* sysLocation */ + if ((syslocation_ptr != syslocation_default) && + (len <= 255)) + { + set_ok = 1; + } + break; + }; + return set_ok; +} + +static void +system_set_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + id = od->id_inst_ptr[0]; + switch (id) + { + case 4: /* sysContact */ + ocstrncpy(syscontact_ptr,value,len); + *syscontact_len_ptr = len; + break; + case 5: /* sysName */ + ocstrncpy(sysname_ptr,value,len); + *sysname_len_ptr = len; + break; + case 6: /* sysLocation */ + ocstrncpy(syslocation_ptr,value,len); + *syslocation_len_ptr = len; + break; + }; +} + +/** + * Returns interfaces.ifnumber object definition. + * + * @param ident_len the address length (2) + * @param ident points to objectname.index + * @param od points to object definition. + */ +static void +interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("interfaces_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +/** + * Returns interfaces.ifnumber object value. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value into. + */ +static void +interfaces_get_value(struct obj_def *od, u16_t len, void *value) +{ + if (len){} + if (od->id_inst_ptr[0] == 1) + { + s32_t *sint_ptr = value; + *sint_ptr = iflist_root.count; + } +} + +/** + * Returns ifentry object definitions. + * + * @param ident_len the address length (2) + * @param ident points to objectname.index + * @param od points to object definition. + */ +static void +ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ifentry.%"U16_F"\n",(u16_t)id)); + switch (id) + { + case 1: /* ifIndex */ + case 3: /* ifType */ + case 4: /* ifMtu */ + case 8: /* ifOperStatus */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* ifDescr */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + /** @todo this should be some sort of sizeof(struct netif.name) */ + od->v_len = 2; + break; + case 5: /* ifSpeed */ + case 21: /* ifOutQLen */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE); + od->v_len = sizeof(u32_t); + break; + case 6: /* ifPhysAddress */ + { + struct netif *netif; + + snmp_ifindextonetif(ident[1], &netif); + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = netif->hwaddr_len; + } + break; + case 7: /* ifAdminStatus */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 9: /* ifLastChange */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS); + od->v_len = sizeof(u32_t); + break; + case 10: /* ifInOctets */ + case 11: /* ifInUcastPkts */ + case 12: /* ifInNUcastPkts */ + case 13: /* ifInDiscarts */ + case 14: /* ifInErrors */ + case 15: /* ifInUnkownProtos */ + case 16: /* ifOutOctets */ + case 17: /* ifOutUcastPkts */ + case 18: /* ifOutNUcastPkts */ + case 19: /* ifOutDiscarts */ + case 20: /* ifOutErrors */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 22: /* ifSpecific */ + /** @note returning zeroDotZero (0.0) no media specific MIB support */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); + od->v_len = ifspecific.len * sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +/** + * Returns ifentry object value. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value into. + */ +static void +ifentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + struct netif *netif; + u8_t id; + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ifIndex */ + { + s32_t *sint_ptr = value; + *sint_ptr = od->id_inst_ptr[1]; + } + break; + case 2: /* ifDescr */ + ocstrncpy(value,(u8_t*)netif->name,len); + break; + case 3: /* ifType */ + { + s32_t *sint_ptr = value; + *sint_ptr = netif->link_type; + } + break; + case 4: /* ifMtu */ + { + s32_t *sint_ptr = value; + *sint_ptr = netif->mtu; + } + break; + case 5: /* ifSpeed */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->link_speed; + } + break; + case 6: /* ifPhysAddress */ + ocstrncpy(value,netif->hwaddr,len); + break; + case 7: /* ifAdminStatus */ + case 8: /* ifOperStatus */ + { + s32_t *sint_ptr = value; + if (netif_is_up(netif)) + { + *sint_ptr = 1; + } + else + { + *sint_ptr = 2; + } + } + break; + case 9: /* ifLastChange */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ts; + } + break; + case 10: /* ifInOctets */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifinoctets; + } + break; + case 11: /* ifInUcastPkts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifinucastpkts; + } + break; + case 12: /* ifInNUcastPkts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifinnucastpkts; + } + break; + case 13: /* ifInDiscarts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifindiscards; + } + break; + case 14: /* ifInErrors */ + case 15: /* ifInUnkownProtos */ + /** @todo add these counters! */ + { + u32_t *uint_ptr = value; + *uint_ptr = 0; + } + break; + case 16: /* ifOutOctets */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifoutoctets; + } + break; + case 17: /* ifOutUcastPkts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifoutucastpkts; + } + break; + case 18: /* ifOutNUcastPkts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifoutnucastpkts; + } + break; + case 19: /* ifOutDiscarts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifoutdiscards; + } + break; + case 20: /* ifOutErrors */ + /** @todo add this counter! */ + { + u32_t *uint_ptr = value; + *uint_ptr = 0; + } + break; + case 21: /* ifOutQLen */ + /** @todo figure out if this must be 0 (no queue) or 1? */ + { + u32_t *uint_ptr = value; + *uint_ptr = 0; + } + break; + case 22: /* ifSpecific */ + objectidncpy((s32_t*)value,(s32_t*)ifspecific.id,len / sizeof(s32_t)); + break; + }; +} + +/** + * Returns atentry object definitions. + * + * @param ident_len the address length (6) + * @param ident points to objectname.atifindex.atnetaddress + * @param od points to object definition. + */ +static void +atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (5) */ + ident_len += 5; + ident -= 5; + + if (ident_len == 6) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + switch (ident[0]) + { + case 1: /* atIfIndex */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* atPhysAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = sizeof(struct eth_addr); + break; + case 3: /* atNetAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +atentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + struct eth_addr* ethaddr_ret; + struct ip_addr* ipaddr_ret; + struct ip_addr ip; + struct netif *netif; + + if (len) {} + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + snmp_oidtoip(&od->id_inst_ptr[2], &ip); + ip.addr = htonl(ip.addr); + + if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1) + { + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* atIfIndex */ + { + s32_t *sint_ptr = value; + *sint_ptr = od->id_inst_ptr[1]; + } + break; + case 2: /* atPhysAddress */ + { + struct eth_addr *dst = value; + + *dst = *ethaddr_ret; + } + break; + case 3: /* atNetAddress */ + { + struct ip_addr *dst = value; + + *dst = *ipaddr_ret; + } + break; + } + } +} + +static void +ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ip.%"U16_F".0\n",(u16_t)id)); + switch (id) + { + case 1: /* ipForwarding */ + case 2: /* ipDefaultTTL */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 3: /* ipInReceives */ + case 4: /* ipInHdrErrors */ + case 5: /* ipInAddrErrors */ + case 6: /* ipForwDatagrams */ + case 7: /* ipInUnknownProtos */ + case 8: /* ipInDiscards */ + case 9: /* ipInDelivers */ + case 10: /* ipOutRequests */ + case 11: /* ipOutDiscards */ + case 12: /* ipOutNoRoutes */ + case 14: /* ipReasmReqds */ + case 15: /* ipReasmOKs */ + case 16: /* ipReasmFails */ + case 17: /* ipFragOKs */ + case 18: /* ipFragFails */ + case 19: /* ipFragCreates */ + case 23: /* ipRoutingDiscards */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 13: /* ipReasmTimeout */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + if (len) {} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipForwarding */ + { + s32_t *sint_ptr = value; +#if IP_FORWARD + /* forwarding */ + *sint_ptr = 1; +#else + /* not-forwarding */ + *sint_ptr = 2; +#endif + } + break; + case 2: /* ipDefaultTTL */ + { + s32_t *sint_ptr = value; + *sint_ptr = IP_DEFAULT_TTL; + } + break; + case 3: /* ipInReceives */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipinreceives; + } + break; + case 4: /* ipInHdrErrors */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipinhdrerrors; + } + break; + case 5: /* ipInAddrErrors */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipinaddrerrors; + } + break; + case 6: /* ipForwDatagrams */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipforwdatagrams; + } + break; + case 7: /* ipInUnknownProtos */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipinunknownprotos; + } + break; + case 8: /* ipInDiscards */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipindiscards; + } + break; + case 9: /* ipInDelivers */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipindelivers; + } + break; + case 10: /* ipOutRequests */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipoutrequests; + } + break; + case 11: /* ipOutDiscards */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipoutdiscards; + } + break; + case 12: /* ipOutNoRoutes */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipoutnoroutes; + } + break; + case 13: /* ipReasmTimeout */ + { + s32_t *sint_ptr = value; +#if IP_REASSEMBLY + *sint_ptr = IP_REASS_MAXAGE; +#else + *sint_ptr = 0; +#endif + } + break; + case 14: /* ipReasmReqds */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipreasmreqds; + } + break; + case 15: /* ipReasmOKs */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipreasmoks; + } + break; + case 16: /* ipReasmFails */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipreasmfails; + } + break; + case 17: /* ipFragOKs */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipfragoks; + } + break; + case 18: /* ipFragFails */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipfragfails; + } + break; + case 19: /* ipFragCreates */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipfragcreates; + } + break; + case 23: /* ipRoutingDiscards */ + /** @todo can lwIP discard routes at all?? hardwire this to 0?? */ + { + u32_t *uint_ptr = value; + *uint_ptr = iproutingdiscards; + } + break; + }; +} + +/** + * Test ip object value before setting. + * + * @param od is the object definition + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value from. + * + * @note we allow set if the value matches the hardwired value, + * otherwise return badvalue. + */ +static u8_t +ip_set_test(struct obj_def *od, u16_t len, void *value) +{ + u8_t id, set_ok; + s32_t *sint_ptr = value; + + if (len) {} + set_ok = 0; + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipForwarding */ +#if IP_FORWARD + /* forwarding */ + if (*sint_ptr == 1) +#else + /* not-forwarding */ + if (*sint_ptr == 2) +#endif + { + set_ok = 1; + } + break; + case 2: /* ipDefaultTTL */ + if (*sint_ptr == IP_DEFAULT_TTL) + { + set_ok = 1; + } + break; + }; + return set_ok; +} + +static void +ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (4) */ + ident_len += 4; + ident -= 4; + + if (ident_len == 5) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + switch (id) + { + case 1: /* ipAdEntAddr */ + case 3: /* ipAdEntNetMask */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 2: /* ipAdEntIfIndex */ + case 4: /* ipAdEntBcastAddr */ + case 5: /* ipAdEntReasmMaxSize */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + u16_t ifidx; + struct ip_addr ip; + struct netif *netif = netif_list; + + if (len) {} + snmp_oidtoip(&od->id_inst_ptr[1], &ip); + ip.addr = htonl(ip.addr); + ifidx = 0; + while ((netif != NULL) && !ip_addr_cmp(&ip, &netif->ip_addr)) + { + netif = netif->next; + ifidx++; + } + + if (netif != NULL) + { + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipAdEntAddr */ + { + struct ip_addr *dst = value; + *dst = netif->ip_addr; + } + break; + case 2: /* ipAdEntIfIndex */ + { + s32_t *sint_ptr = value; + *sint_ptr = ifidx + 1; + } + break; + case 3: /* ipAdEntNetMask */ + { + struct ip_addr *dst = value; + *dst = netif->netmask; + } + break; + case 4: /* ipAdEntBcastAddr */ + { + s32_t *sint_ptr = value; + + /* lwIP oddity, there's no broadcast + address in the netif we can rely on */ + *sint_ptr = ip_addr_broadcast.addr & 1; + } + break; + case 5: /* ipAdEntReasmMaxSize */ + { + s32_t *sint_ptr = value; +#if IP_REASSEMBLY + *sint_ptr = (IP_HLEN + IP_REASS_BUFSIZE); +#else + /** @todo returning MTU would be a bad thing and + returning a wild guess like '576' isn't good either */ + *sint_ptr = 0; +#endif + } + break; + } + } +} + +/** + * @note + * lwIP IP routing is currently using the network addresses in netif_list. + * if no suitable network IP is found in netif_list, the default_netif is used. + */ +static void +ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (4) */ + ident_len += 4; + ident -= 4; + + if (ident_len == 5) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + switch (id) + { + case 1: /* ipRouteDest */ + case 7: /* ipRouteNextHop */ + case 11: /* ipRouteMask */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 2: /* ipRouteIfIndex */ + case 3: /* ipRouteMetric1 */ + case 4: /* ipRouteMetric2 */ + case 5: /* ipRouteMetric3 */ + case 6: /* ipRouteMetric4 */ + case 8: /* ipRouteType */ + case 10: /* ipRouteAge */ + case 12: /* ipRouteMetric5 */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 9: /* ipRouteProto */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 13: /* ipRouteInfo */ + /** @note returning zeroDotZero (0.0) no routing protocol specific MIB */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); + od->v_len = iprouteinfo.len * sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + struct netif *netif; + struct ip_addr dest; + s32_t *ident; + u8_t id; + + ident = od->id_inst_ptr; + snmp_oidtoip(&ident[1], &dest); + dest.addr = htonl(dest.addr); + + if (dest.addr == 0) + { + /* ip_route() uses default netif for default route */ + netif = netif_default; + } + else + { + /* not using ip_route(), need exact match! */ + netif = netif_list; + while ((netif != NULL) && + !ip_addr_netcmp(&dest, &(netif->ip_addr), &(netif->netmask)) ) + { + netif = netif->next; + } + } + if (netif != NULL) + { + id = ident[0]; + switch (id) + { + case 1: /* ipRouteDest */ + { + struct ip_addr *dst = value; + + if (dest.addr == 0) + { + /* default rte has 0.0.0.0 dest */ + dst->addr = 0; + } + else + { + /* netifs have netaddress dest */ + dst->addr = netif->ip_addr.addr & netif->netmask.addr; + } + } + break; + case 2: /* ipRouteIfIndex */ + { + s32_t *sint_ptr = value; + + snmp_netiftoifindex(netif, sint_ptr); + } + break; + case 3: /* ipRouteMetric1 */ + { + s32_t *sint_ptr = value; + + if (dest.addr == 0) + { + /* default rte has metric 1 */ + *sint_ptr = 1; + } + else + { + /* other rtes have metric 0 */ + *sint_ptr = 0; + } + } + break; + case 4: /* ipRouteMetric2 */ + case 5: /* ipRouteMetric3 */ + case 6: /* ipRouteMetric4 */ + case 12: /* ipRouteMetric5 */ + { + s32_t *sint_ptr = value; + /* not used */ + *sint_ptr = -1; + } + break; + case 7: /* ipRouteNextHop */ + { + struct ip_addr *dst = value; + + if (dest.addr == 0) + { + /* default rte: gateway */ + *dst = netif->gw; + } + else + { + /* other rtes: netif ip_addr */ + *dst = netif->ip_addr; + } + } + break; + case 8: /* ipRouteType */ + { + s32_t *sint_ptr = value; + + if (dest.addr == 0) + { + /* default rte is indirect */ + *sint_ptr = 4; + } + else + { + /* other rtes are direct */ + *sint_ptr = 3; + } + } + break; + case 9: /* ipRouteProto */ + { + s32_t *sint_ptr = value; + /* locally defined routes */ + *sint_ptr = 2; + } + break; + case 10: /* ipRouteAge */ + { + s32_t *sint_ptr = value; + /** @todo (sysuptime - timestamp last change) / 100 + @see snmp_insert_iprteidx_tree() */ + *sint_ptr = 0; + } + break; + case 11: /* ipRouteMask */ + { + struct ip_addr *dst = value; + + if (dest.addr == 0) + { + /* default rte use 0.0.0.0 mask */ + dst->addr = 0; + } + else + { + /* other rtes use netmask */ + *dst = netif->netmask; + } + } + break; + case 13: /* ipRouteInfo */ + objectidncpy((s32_t*)value,(s32_t*)iprouteinfo.id,len / sizeof(s32_t)); + break; + } + } +} + +static void +ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (5) */ + ident_len += 5; + ident -= 5; + + if (ident_len == 6) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + switch (id) + { + case 1: /* ipNetToMediaIfIndex */ + case 4: /* ipNetToMediaType */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* ipNetToMediaPhysAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = sizeof(struct eth_addr); + break; + case 3: /* ipNetToMediaNetAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + struct eth_addr* ethaddr_ret; + struct ip_addr* ipaddr_ret; + struct ip_addr ip; + struct netif *netif; + + if (len) {} + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + snmp_oidtoip(&od->id_inst_ptr[2], &ip); + ip.addr = htonl(ip.addr); + + if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1) + { + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipNetToMediaIfIndex */ + { + s32_t *sint_ptr = value; + *sint_ptr = od->id_inst_ptr[1]; + } + break; + case 2: /* ipNetToMediaPhysAddress */ + { + struct eth_addr *dst = value; + + *dst = *ethaddr_ret; + } + break; + case 3: /* ipNetToMediaNetAddress */ + { + struct ip_addr *dst = value; + + *dst = *ipaddr_ret; + } + break; + case 4: /* ipNetToMediaType */ + { + s32_t *sint_ptr = value; + /* dynamic (?) */ + *sint_ptr = 3; + } + break; + } + } +} + +static void +icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if ((ident_len == 2) && + (ident[0] > 0) && (ident[0] < 27)) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("icmp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +icmp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = value; + u8_t id; + + if (len){} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* icmpInMsgs */ + *uint_ptr = icmpinmsgs; + break; + case 2: /* icmpInErrors */ + *uint_ptr = icmpinerrors; + break; + case 3: /* icmpInDestUnreachs */ + *uint_ptr = icmpindestunreachs; + break; + case 4: /* icmpInTimeExcds */ + *uint_ptr = icmpintimeexcds; + break; + case 5: /* icmpInParmProbs */ + *uint_ptr = icmpinparmprobs; + break; + case 6: /* icmpInSrcQuenchs */ + *uint_ptr = icmpinsrcquenchs; + break; + case 7: /* icmpInRedirects */ + *uint_ptr = icmpinredirects; + break; + case 8: /* icmpInEchos */ + *uint_ptr = icmpinechos; + break; + case 9: /* icmpInEchoReps */ + *uint_ptr = icmpinechoreps; + break; + case 10: /* icmpInTimestamps */ + *uint_ptr = icmpintimestamps; + break; + case 11: /* icmpInTimestampReps */ + *uint_ptr = icmpintimestampreps; + break; + case 12: /* icmpInAddrMasks */ + *uint_ptr = icmpinaddrmasks; + break; + case 13: /* icmpInAddrMaskReps */ + *uint_ptr = icmpinaddrmaskreps; + break; + case 14: /* icmpOutMsgs */ + *uint_ptr = icmpoutmsgs; + break; + case 15: /* icmpOutErrors */ + *uint_ptr = icmpouterrors; + break; + case 16: /* icmpOutDestUnreachs */ + *uint_ptr = icmpoutdestunreachs; + break; + case 17: /* icmpOutTimeExcds */ + *uint_ptr = icmpouttimeexcds; + break; + case 18: /* icmpOutParmProbs */ + *uint_ptr = icmpoutparmprobs; + break; + case 19: /* icmpOutSrcQuenchs */ + *uint_ptr = icmpoutsrcquenchs; + break; + case 20: /* icmpOutRedirects */ + *uint_ptr = icmpoutredirects; + break; + case 21: /* icmpOutEchos */ + *uint_ptr = icmpoutechos; + break; + case 22: /* icmpOutEchoReps */ + *uint_ptr = icmpoutechoreps; + break; + case 23: /* icmpOutTimestamps */ + *uint_ptr = icmpouttimestamps; + break; + case 24: /* icmpOutTimestampReps */ + *uint_ptr = icmpouttimestampreps; + break; + case 25: /* icmpOutAddrMasks */ + *uint_ptr = icmpoutaddrmasks; + break; + case 26: /* icmpOutAddrMaskReps */ + *uint_ptr = icmpoutaddrmaskreps; + break; + } +} + +#if LWIP_TCP +/** @todo tcp grp */ +static void +tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id)); + + switch (id) + { + case 1: /* tcpRtoAlgorithm */ + case 2: /* tcpRtoMin */ + case 3: /* tcpRtoMax */ + case 4: /* tcpMaxConn */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 5: /* tcpActiveOpens */ + case 6: /* tcpPassiveOpens */ + case 7: /* tcpAttemptFails */ + case 8: /* tcpEstabResets */ + case 10: /* tcpInSegs */ + case 11: /* tcpOutSegs */ + case 12: /* tcpRetransSegs */ + case 14: /* tcpInErrs */ + case 15: /* tcpOutRsts */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 9: /* tcpCurrEstab */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE); + od->v_len = sizeof(u32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +tcp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = value; + s32_t *sint_ptr = value; + u8_t id; + + if (len){} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* tcpRtoAlgorithm, vanj(4) */ + *sint_ptr = 4; + break; + case 2: /* tcpRtoMin */ + /* @todo not the actual value, a guess, + needs to be calculated */ + *sint_ptr = 1000; + break; + case 3: /* tcpRtoMax */ + /* @todo not the actual value, a guess, + needs to be calculated */ + *sint_ptr = 60000; + break; + case 4: /* tcpMaxConn */ + *sint_ptr = MEMP_NUM_TCP_PCB; + break; + case 5: /* tcpActiveOpens */ + *uint_ptr = tcpactiveopens; + break; + case 6: /* tcpPassiveOpens */ + *uint_ptr = tcppassiveopens; + break; + case 7: /* tcpAttemptFails */ + *uint_ptr = tcpattemptfails; + break; + case 8: /* tcpEstabResets */ + *uint_ptr = tcpestabresets; + break; + case 9: /* tcpCurrEstab */ + { + u16_t tcpcurrestab = 0; + struct tcp_pcb *pcb = tcp_active_pcbs; + while (pcb != NULL) + { + if ((pcb->state == ESTABLISHED) || + (pcb->state == CLOSE_WAIT)) + { + tcpcurrestab++; + } + pcb = pcb->next; + } + *uint_ptr = tcpcurrestab; + } + break; + case 10: /* tcpInSegs */ + *uint_ptr = tcpinsegs; + break; + case 11: /* tcpOutSegs */ + *uint_ptr = tcpoutsegs; + break; + case 12: /* tcpRetransSegs */ + *uint_ptr = tcpretranssegs; + break; + case 14: /* tcpInErrs */ + *uint_ptr = tcpinerrs; + break; + case 15: /* tcpOutRsts */ + *uint_ptr = tcpoutrsts; + break; + } +} + +static void +tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (10) */ + ident_len += 10; + ident -= 10; + + if (ident_len == 11) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id)); + + switch (id) + { + case 1: /* tcpConnState */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* tcpConnLocalAddress */ + case 4: /* tcpConnRemAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 3: /* tcpConnLocalPort */ + case 5: /* tcpConnRemPort */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + struct ip_addr lip, rip; + u16_t lport, rport; + s32_t *ident; + + ident = od->id_inst_ptr; + snmp_oidtoip(&ident[1], &lip); + lip.addr = htonl(lip.addr); + lport = ident[5]; + snmp_oidtoip(&ident[6], &rip); + rip.addr = htonl(rip.addr); + rport = ident[10]; + + /** @todo find matching PCB */ +} +#endif + +static void +udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if ((ident_len == 2) && + (ident[0] > 0) && (ident[0] < 6)) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("udp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +udp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = value; + u8_t id; + + if (len){} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* udpInDatagrams */ + *uint_ptr = udpindatagrams; + break; + case 2: /* udpNoPorts */ + *uint_ptr = udpnoports; + break; + case 3: /* udpInErrors */ + *uint_ptr = udpinerrors; + break; + case 4: /* udpOutDatagrams */ + *uint_ptr = udpoutdatagrams; + break; + } +} + +static void +udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (5) */ + ident_len += 5; + ident -= 5; + + if (ident_len == 6) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + switch (ident[0]) + { + case 1: /* udpLocalAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 2: /* udpLocalPort */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +udpentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + struct udp_pcb *pcb; + struct ip_addr ip; + u16_t port; + + if (len){} + snmp_oidtoip(&od->id_inst_ptr[1], &ip); + ip.addr = htonl(ip.addr); + port = od->id_inst_ptr[5]; + + pcb = udp_pcbs; + while ((pcb != NULL) && + !((pcb->local_ip.addr == ip.addr) && + (pcb->local_port == port))) + { + pcb = pcb->next; + } + + if (pcb != NULL) + { + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* udpLocalAddress */ + { + struct ip_addr *dst = value; + *dst = pcb->local_ip; + } + break; + case 2: /* udpLocalPort */ + { + s32_t *sint_ptr = value; + *sint_ptr = pcb->local_port; + } + break; + } + } +} + +static void +snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + switch (id) + { + case 1: /* snmpInPkts */ + case 2: /* snmpOutPkts */ + case 3: /* snmpInBadVersions */ + case 4: /* snmpInBadCommunityNames */ + case 5: /* snmpInBadCommunityUses */ + case 6: /* snmpInASNParseErrs */ + case 8: /* snmpInTooBigs */ + case 9: /* snmpInNoSuchNames */ + case 10: /* snmpInBadValues */ + case 11: /* snmpInReadOnlys */ + case 12: /* snmpInGenErrs */ + case 13: /* snmpInTotalReqVars */ + case 14: /* snmpInTotalSetVars */ + case 15: /* snmpInGetRequests */ + case 16: /* snmpInGetNexts */ + case 17: /* snmpInSetRequests */ + case 18: /* snmpInGetResponses */ + case 19: /* snmpInTraps */ + case 20: /* snmpOutTooBigs */ + case 21: /* snmpOutNoSuchNames */ + case 22: /* snmpOutBadValues */ + case 24: /* snmpOutGenErrs */ + case 25: /* snmpOutGetRequests */ + case 26: /* snmpOutGetNexts */ + case 27: /* snmpOutSetRequests */ + case 28: /* snmpOutGetResponses */ + case 29: /* snmpOutTraps */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 30: /* snmpEnableAuthenTraps */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +snmp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = value; + u8_t id; + + if (len){} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* snmpInPkts */ + *uint_ptr = snmpinpkts; + break; + case 2: /* snmpOutPkts */ + *uint_ptr = snmpoutpkts; + break; + case 3: /* snmpInBadVersions */ + *uint_ptr = snmpinbadversions; + break; + case 4: /* snmpInBadCommunityNames */ + *uint_ptr = snmpinbadcommunitynames; + break; + case 5: /* snmpInBadCommunityUses */ + *uint_ptr = snmpinbadcommunityuses; + break; + case 6: /* snmpInASNParseErrs */ + *uint_ptr = snmpinasnparseerrs; + break; + case 8: /* snmpInTooBigs */ + *uint_ptr = snmpintoobigs; + break; + case 9: /* snmpInNoSuchNames */ + *uint_ptr = snmpinnosuchnames; + break; + case 10: /* snmpInBadValues */ + *uint_ptr = snmpinbadvalues; + break; + case 11: /* snmpInReadOnlys */ + *uint_ptr = snmpinreadonlys; + break; + case 12: /* snmpInGenErrs */ + *uint_ptr = snmpingenerrs; + break; + case 13: /* snmpInTotalReqVars */ + *uint_ptr = snmpintotalreqvars; + break; + case 14: /* snmpInTotalSetVars */ + *uint_ptr = snmpintotalsetvars; + break; + case 15: /* snmpInGetRequests */ + *uint_ptr = snmpingetrequests; + break; + case 16: /* snmpInGetNexts */ + *uint_ptr = snmpingetnexts; + break; + case 17: /* snmpInSetRequests */ + *uint_ptr = snmpinsetrequests; + break; + case 18: /* snmpInGetResponses */ + *uint_ptr = snmpingetresponses; + break; + case 19: /* snmpInTraps */ + *uint_ptr = snmpintraps; + break; + case 20: /* snmpOutTooBigs */ + *uint_ptr = snmpouttoobigs; + break; + case 21: /* snmpOutNoSuchNames */ + *uint_ptr = snmpoutnosuchnames; + break; + case 22: /* snmpOutBadValues */ + *uint_ptr = snmpoutbadvalues; + break; + case 24: /* snmpOutGenErrs */ + *uint_ptr = snmpoutgenerrs; + break; + case 25: /* snmpOutGetRequests */ + *uint_ptr = snmpoutgetrequests; + break; + case 26: /* snmpOutGetNexts */ + *uint_ptr = snmpoutgetnexts; + break; + case 27: /* snmpOutSetRequests */ + *uint_ptr = snmpoutsetrequests; + break; + case 28: /* snmpOutGetResponses */ + *uint_ptr = snmpoutgetresponses; + break; + case 29: /* snmpOutTraps */ + *uint_ptr = snmpouttraps; + break; + case 30: /* snmpEnableAuthenTraps */ + *uint_ptr = *snmpenableauthentraps_ptr; + break; + }; +} + +/** + * Test snmp object value before setting. + * + * @param od is the object definition + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value from. + */ +static u8_t +snmp_set_test(struct obj_def *od, u16_t len, void *value) +{ + u8_t id, set_ok; + + if (len) {} + set_ok = 0; + id = od->id_inst_ptr[0]; + if (id == 30) + { + /* snmpEnableAuthenTraps */ + s32_t *sint_ptr = value; + + if (snmpenableauthentraps_ptr != &snmpenableauthentraps_default) + { + /* we should have writable non-volatile mem here */ + if ((*sint_ptr == 1) || (*sint_ptr == 2)) + { + set_ok = 1; + } + } + else + { + /* const or hardwired value */ + if (*sint_ptr == snmpenableauthentraps_default) + { + set_ok = 1; + } + } + } + return set_ok; +} + +static void +snmp_set_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + if (len) {} + id = od->id_inst_ptr[0]; + if (id == 30) + { + /* snmpEnableAuthenTraps */ + s32_t *sint_ptr = value; + *snmpenableauthentraps_ptr = *sint_ptr; + } +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/mib_structs.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/mib_structs.c new file mode 100644 index 0000000..1fad588 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/mib_structs.c @@ -0,0 +1,1185 @@ +/** + * @file + * MIB tree access/construction functions. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "lwip/snmp_structs.h" +#include "lwip/mem.h" + + + +/** .iso.org.dod.internet address prefix, @see snmp_iso_*() */ +const s32_t prefix[4] = {1, 3, 6, 1}; + +#define NODE_STACK_SIZE (LWIP_SNMP_OBJ_ID_LEN) +/** node stack entry (old news?) */ +struct nse +{ + /** right child */ + struct mib_node* r_ptr; + /** right child identifier */ + s32_t r_id; + /** right child next level */ + u8_t r_nl; +}; +static u8_t node_stack_cnt = 0; +static struct nse node_stack[NODE_STACK_SIZE]; + +/** + * Pushes nse struct onto stack. + */ +static void +push_node(struct nse* node) +{ + LWIP_ASSERT("node_stack_cnt < NODE_STACK_SIZE",node_stack_cnt < NODE_STACK_SIZE); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("push_node() node=%p id=%"S32_F"\n",(void*)(node->r_ptr),node->r_id)); + if (node_stack_cnt < NODE_STACK_SIZE) + { + node_stack[node_stack_cnt] = *node; + node_stack_cnt++; + } +} + +/** + * Pops nse struct from stack. + */ +static void +pop_node(struct nse* node) +{ + if (node_stack_cnt > 0) + { + node_stack_cnt--; + *node = node_stack[node_stack_cnt]; + } + LWIP_DEBUGF(SNMP_MIB_DEBUG,("pop_node() node=%p id=%"S32_F"\n",(void *)(node->r_ptr),node->r_id)); +} + +/** + * Conversion from ifIndex to lwIP netif + * @param ifindex is a s32_t object sub-identifier + * @param netif points to returned netif struct pointer + */ +void +snmp_ifindextonetif(s32_t ifindex, struct netif **netif) +{ + struct netif *nif = netif_list; + u16_t i, ifidx; + + ifidx = ifindex - 1; + i = 0; + while ((nif != NULL) && (i < ifidx)) + { + nif = nif->next; + i++; + } + *netif = nif; +} + +/** + * Conversion from lwIP netif to ifIndex + * @param netif points to a netif struct + * @param ifindex points to s32_t object sub-identifier + */ +void +snmp_netiftoifindex(struct netif *netif, s32_t *ifidx) +{ + struct netif *nif = netif_list; + u16_t i; + + i = 0; + while (nif != netif) + { + nif = nif->next; + i++; + } + *ifidx = i+1; +} + +/** + * Conversion from oid to lwIP ip_addr + * @param ident points to s32_t ident[4] input + * @param ip points to output struct + */ +void +snmp_oidtoip(s32_t *ident, struct ip_addr *ip) +{ + u32_t ipa; + + ipa = ident[0]; + ipa <<= 8; + ipa |= ident[1]; + ipa <<= 8; + ipa |= ident[2]; + ipa <<= 8; + ipa |= ident[3]; + ip->addr = ipa; +} + +/** + * Conversion from lwIP ip_addr to oid + * @param ip points to input struct + * @param ident points to s32_t ident[4] output + */ +void +snmp_iptooid(struct ip_addr *ip, s32_t *ident) +{ + u32_t ipa; + + ipa = ip->addr; + ident[0] = (ipa >> 24) & 0xff; + ident[1] = (ipa >> 16) & 0xff; + ident[2] = (ipa >> 8) & 0xff; + ident[3] = ipa & 0xff; +} + +struct mib_list_node * +snmp_mib_ln_alloc(s32_t id) +{ + struct mib_list_node *ln; + + ln = (struct mib_list_node *)mem_malloc(sizeof(struct mib_list_node)); + if (ln != NULL) + { + ln->prev = NULL; + ln->next = NULL; + ln->objid = id; + ln->nptr = NULL; + } + return ln; +} + +void +snmp_mib_ln_free(struct mib_list_node *ln) +{ + mem_free(ln); +} + +struct mib_list_rootnode * +snmp_mib_lrn_alloc(void) +{ + struct mib_list_rootnode *lrn; + + lrn = (struct mib_list_rootnode*)mem_malloc(sizeof(struct mib_list_rootnode)); + if (lrn != NULL) + { + lrn->get_object_def = noleafs_get_object_def; + lrn->get_value = noleafs_get_value; + lrn->set_test = noleafs_set_test; + lrn->set_value = noleafs_set_value; + lrn->node_type = MIB_NODE_LR; + lrn->maxlength = 0; + lrn->head = NULL; + lrn->tail = NULL; + lrn->count = 0; + } + return lrn; +} + +void +snmp_mib_lrn_free(struct mib_list_rootnode *lrn) +{ + mem_free(lrn); +} + +/** + * Inserts node in idx list in a sorted + * (ascending order) fashion and + * allocates the node if needed. + * + * @param rn points to the root node + * @param objid is the object sub identifier + * @param insn points to a pointer to the inserted node + * used for constructing the tree. + * @return -1 if failed, 1 if inserted, 2 if present. + */ +s8_t +snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn) +{ + struct mib_list_node *nn; + s8_t insert; + + LWIP_ASSERT("rn != NULL",rn != NULL); + + /* -1 = malloc failure, 0 = not inserted, 1 = inserted, 2 = was present */ + insert = 0; + if (rn->head == NULL) + { + /* empty list, add first node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc empty list objid==%"S32_F"\n",objid)); + nn = snmp_mib_ln_alloc(objid); + if (nn != NULL) + { + rn->head = nn; + rn->tail = nn; + *insn = nn; + insert = 1; + } + else + { + insert = -1; + } + } + else + { + struct mib_list_node *n; + /* at least one node is present */ + n = rn->head; + while ((n != NULL) && (insert == 0)) + { + if (n->objid == objid) + { + /* node is already there */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("node already there objid==%"S32_F"\n",objid)); + *insn = n; + insert = 2; + } + else if (n->objid < objid) + { + if (n->next == NULL) + { + /* alloc and insert at the tail */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins tail objid==%"S32_F"\n",objid)); + nn = snmp_mib_ln_alloc(objid); + if (nn != NULL) + { + nn->next = NULL; + nn->prev = n; + n->next = nn; + rn->tail = nn; + *insn = nn; + insert = 1; + } + else + { + /* insertion failure */ + insert = -1; + } + } + else + { + /* there's more to explore: traverse list */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("traverse list\n")); + n = n->next; + } + } + else + { + /* n->objid > objid */ + /* alloc and insert between n->prev and n */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins n->prev, objid==%"S32_F", n\n",objid)); + nn = snmp_mib_ln_alloc(objid); + if (nn != NULL) + { + if (n->prev == NULL) + { + /* insert at the head */ + nn->next = n; + nn->prev = NULL; + rn->head = nn; + n->prev = nn; + } + else + { + /* insert in the middle */ + nn->next = n; + nn->prev = n->prev; + n->prev->next = nn; + n->prev = nn; + } + *insn = nn; + insert = 1; + } + else + { + /* insertion failure */ + insert = -1; + } + } + } + } + if (insert == 1) + { + rn->count += 1; + } + LWIP_ASSERT("insert != 0",insert != 0); + return insert; +} + +/** + * Finds node in idx list and returns deletion mark. + * + * @param rn points to the root node + * @param objid is the object sub identifier + * @param fn returns pointer to found node + * @return 0 if not found, 1 if deletable, + * 2 can't delete (2 or more children), 3 not a list_node + */ +s8_t +snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn) +{ + s8_t fc; + struct mib_list_node *n; + + LWIP_ASSERT("rn != NULL",rn != NULL); + n = rn->head; + while ((n != NULL) && (n->objid != objid)) + { + n = n->next; + } + if (n == NULL) + { + fc = 0; + } + else if (n->nptr == NULL) + { + /* leaf, can delete node */ + fc = 1; + } + else + { + struct mib_list_rootnode *rn; + + if (n->nptr->node_type == MIB_NODE_LR) + { + rn = (struct mib_list_rootnode *)n->nptr; + if (rn->count > 1) + { + /* can't delete node */ + fc = 2; + } + else + { + /* count <= 1, can delete node */ + fc = 1; + } + } + else + { + /* other node type */ + fc = 3; + } + } + *fn = n; + return fc; +} + +/** + * Removes node from idx list + * if it has a single child left. + * + * @param rn points to the root node + * @param n points to the node to delete + * @return the nptr to be freed by caller + */ +struct mib_list_rootnode * +snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n) +{ + struct mib_list_rootnode *next; + + LWIP_ASSERT("rn != NULL",rn != NULL); + LWIP_ASSERT("n != NULL",n != NULL); + + /* caller must remove this sub-tree */ + next = (struct mib_list_rootnode*)(n->nptr); + rn->count -= 1; + + if (n == rn->head) + { + rn->head = n->next; + if (n->next != NULL) + { + /* not last node, new list begin */ + n->next->prev = NULL; + } + } + else if (n == rn->tail) + { + rn->tail = n->prev; + if (n->prev != NULL) + { + /* not last node, new list end */ + n->prev->next = NULL; + } + } + else + { + /* node must be in the middle */ + n->prev->next = n->next; + n->next->prev = n->prev; + } + LWIP_DEBUGF(SNMP_MIB_DEBUG,("free list objid==%"S32_F"\n",n->objid)); + snmp_mib_ln_free(n); + if (rn->count == 0) + { + rn->head = NULL; + rn->tail = NULL; + } + return next; +} + + + +/** + * Searches tree for the supplied (scalar?) object identifier. + * + * @param node points to the root of the tree ('.internet') + * @param ident_len the length of the supplied object identifier + * @param ident points to the array of sub identifiers + * @param np points to the found object instance (rerurn) + * @return pointer to the requested parent (!) node if success, NULL otherwise + */ +struct mib_node * +snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np) +{ + u8_t node_type, ext_level; + + ext_level = 0; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("node==%p *ident==%"S32_F"\n",(void*)node,*ident)); + while (node != NULL) + { + node_type = node->node_type; + if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) + { + struct mib_array_node *an; + u16_t i; + + if (ident_len > 0) + { + /* array node (internal ROM or RAM, fixed length) */ + an = (struct mib_array_node *)node; + i = 0; + while ((i < an->maxlength) && (an->objid[i] != *ident)) + { + i++; + } + if (i < an->maxlength) + { + /* found it, if available proceed to child, otherwise inspect leaf */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident)); + if (an->nptr[i] == NULL) + { + /* a scalar leaf OR table, + inspect remaining instance number / table index */ + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)an; + } + else + { + /* follow next child pointer */ + ident++; + ident_len--; + node = an->nptr[i]; + } + } + else + { + /* search failed, identifier mismatch (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed *ident==%"S32_F"\n",*ident)); + return NULL; + } + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed, short object identifier\n")); + return NULL; + } + } + else if(node_type == MIB_NODE_LR) + { + struct mib_list_rootnode *lrn; + struct mib_list_node *ln; + + if (ident_len > 0) + { + /* list root node (internal 'RAM', variable length) */ + lrn = (struct mib_list_rootnode *)node; + ln = lrn->head; + /* iterate over list, head to tail */ + while ((ln != NULL) && (ln->objid != *ident)) + { + ln = ln->next; + } + if (ln != NULL) + { + /* found it, proceed to child */; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident)); + if (ln->nptr == NULL) + { + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)lrn; + } + else + { + /* follow next child pointer */ + ident_len--; + ident++; + node = ln->nptr; + } + } + else + { + /* search failed */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed *ident==%"S32_F"\n",*ident)); + return NULL; + } + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed, short object identifier\n")); + return NULL; + } + } + else if(node_type == MIB_NODE_EX) + { + struct mib_external_node *en; + u16_t i, len; + + if (ident_len > 0) + { + /* external node (addressing and access via functions) */ + en = (struct mib_external_node *)node; + + i = 0; + len = en->level_length(en->addr_inf,ext_level); + while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) != 0)) + { + i++; + } + if (i < len) + { + s32_t debug_id; + + en->get_objid(en->addr_inf,ext_level,i,&debug_id); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid==%"S32_F" *ident==%"S32_F"\n",debug_id,*ident)); + if ((ext_level + 1) == en->tree_levels) + { + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)en; + } + else + { + /* found it, proceed to child */ + ident_len--; + ident++; + ext_level++; + } + } + else + { + /* search failed */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed *ident==%"S32_F"\n",*ident)); + return NULL; + } + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed, short object identifier\n")); + return NULL; + } + } + else if (node_type == MIB_NODE_SC) + { + mib_scalar_node *sn; + + sn = (mib_scalar_node *)node; + if ((ident_len == 1) && (*ident == 0)) + { + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)sn; + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed, invalid object identifier length\n")); + return NULL; + } + } + else + { + /* unknown node_type */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node_type %"U16_F" unkown\n",(u16_t)node_type)); + return NULL; + } + } + /* done, found nothing */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node==%p\n",(void*)node)); + return NULL; +} + +/** + * Test table for presence of at least one table entry. + */ +static u8_t +empty_table(struct mib_node *node) +{ + u8_t node_type; + u8_t empty = 0; + + if (node != NULL) + { + node_type = node->node_type; + if (node_type == MIB_NODE_LR) + { + struct mib_list_rootnode *lrn; + lrn = (struct mib_list_rootnode *)node; + if ((lrn->count == 0) || (lrn->head == NULL)) + { + empty = 1; + } + } + else if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) + { + struct mib_array_node *an; + an = (struct mib_array_node *)node; + if ((an->maxlength == 0) || (an->nptr == NULL)) + { + empty = 1; + } + } + else if (node_type == MIB_NODE_EX) + { + struct mib_external_node *en; + en = (struct mib_external_node *)node; + if (en->tree_levels == 0) + { + empty = 1; + } + } + } + return empty; +} + +/** + * Tree expansion. + */ +struct mib_node * +snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret) +{ + u8_t node_type, ext_level, climb_tree; + + ext_level = 0; + /* reset node stack */ + node_stack_cnt = 0; + while (node != NULL) + { + climb_tree = 0; + node_type = node->node_type; + if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) + { + struct mib_array_node *an; + u16_t i; + + /* array node (internal ROM or RAM, fixed length) */ + an = (struct mib_array_node *)node; + if (ident_len > 0) + { + i = 0; + while ((i < an->maxlength) && (an->objid[i] < *ident)) + { + i++; + } + if (i < an->maxlength) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident)); + /* add identifier to oidret */ + oidret->id[oidret->len] = an->objid[i]; + (oidret->len)++; + + if (an->nptr[i] == NULL) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n")); + /* leaf node (e.g. in a fixed size table) */ + if (an->objid[i] > *ident) + { + return (struct mib_node*)an; + } + else if ((i + 1) < an->maxlength) + { + /* an->objid[i] == *ident */ + (oidret->len)--; + oidret->id[oidret->len] = an->objid[i + 1]; + (oidret->len)++; + return (struct mib_node*)an; + } + else + { + /* (i + 1) == an->maxlength */ + (oidret->len)--; + climb_tree = 1; + } + } + else + { + u8_t j; + struct nse cur_node; + + LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n")); + /* non-leaf, store right child ptr and id */ + j = i + 1; + while ((j < an->maxlength) && (empty_table(an->nptr[j]))) + { + j++; + } + if (j < an->maxlength) + { + cur_node.r_ptr = an->nptr[j]; + cur_node.r_id = an->objid[j]; + cur_node.r_nl = 0; + } + else + { + cur_node.r_ptr = NULL; + } + push_node(&cur_node); + if (an->objid[i] == *ident) + { + ident_len--; + ident++; + } + else + { + /* an->objid[i] < *ident */ + ident_len = 0; + } + /* follow next child pointer */ + node = an->nptr[i]; + } + } + else + { + /* i == an->maxlength */ + climb_tree = 1; + } + } + else + { + u8_t j; + /* ident_len == 0, complete with leftmost '.thing' */ + j = 0; + while ((j < an->maxlength) && empty_table(an->nptr[j])) + { + j++; + } + if (j < an->maxlength) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("left an->objid[j]==%"S32_F"\n",an->objid[j])); + oidret->id[oidret->len] = an->objid[j]; + (oidret->len)++; + if (an->nptr[j] == NULL) + { + /* leaf node */ + return (struct mib_node*)an; + } + else + { + /* no leaf, continue */ + node = an->nptr[j]; + } + } + else + { + /* j == an->maxlength */ + climb_tree = 1; + } + } + } + else if(node_type == MIB_NODE_LR) + { + struct mib_list_rootnode *lrn; + struct mib_list_node *ln; + + /* list root node (internal 'RAM', variable length) */ + lrn = (struct mib_list_rootnode *)node; + if (ident_len > 0) + { + ln = lrn->head; + /* iterate over list, head to tail */ + while ((ln != NULL) && (ln->objid < *ident)) + { + ln = ln->next; + } + if (ln != NULL) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident)); + oidret->id[oidret->len] = ln->objid; + (oidret->len)++; + if (ln->nptr == NULL) + { + /* leaf node */ + if (ln->objid > *ident) + { + return (struct mib_node*)lrn; + } + else if (ln->next != NULL) + { + /* ln->objid == *ident */ + (oidret->len)--; + oidret->id[oidret->len] = ln->next->objid; + (oidret->len)++; + return (struct mib_node*)lrn; + } + else + { + /* ln->next == NULL */ + (oidret->len)--; + climb_tree = 1; + } + } + else + { + struct mib_list_node *jn; + struct nse cur_node; + + /* non-leaf, store right child ptr and id */ + jn = ln->next; + while ((jn != NULL) && empty_table(jn->nptr)) + { + jn = jn->next; + } + if (jn != NULL) + { + cur_node.r_ptr = jn->nptr; + cur_node.r_id = jn->objid; + cur_node.r_nl = 0; + } + else + { + cur_node.r_ptr = NULL; + } + push_node(&cur_node); + if (ln->objid == *ident) + { + ident_len--; + ident++; + } + else + { + /* ln->objid < *ident */ + ident_len = 0; + } + /* follow next child pointer */ + node = ln->nptr; + } + + } + else + { + /* ln == NULL */ + climb_tree = 1; + } + } + else + { + struct mib_list_node *jn; + /* ident_len == 0, complete with leftmost '.thing' */ + jn = lrn->head; + while ((jn != NULL) && empty_table(jn->nptr)) + { + jn = jn->next; + } + if (jn != NULL) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("left jn->objid==%"S32_F"\n",jn->objid)); + oidret->id[oidret->len] = jn->objid; + (oidret->len)++; + if (jn->nptr == NULL) + { + /* leaf node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("jn->nptr == NULL\n")); + return (struct mib_node*)lrn; + } + else + { + /* no leaf, continue */ + node = jn->nptr; + } + } + else + { + /* jn == NULL */ + climb_tree = 1; + } + } + } + else if(node_type == MIB_NODE_EX) + { + struct mib_external_node *en; + s32_t ex_id; + + /* external node (addressing and access via functions) */ + en = (struct mib_external_node *)node; + if (ident_len > 0) + { + u16_t i, len; + + i = 0; + len = en->level_length(en->addr_inf,ext_level); + while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) < 0)) + { + i++; + } + if (i < len) + { + /* add identifier to oidret */ + en->get_objid(en->addr_inf,ext_level,i,&ex_id); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,ex_id,*ident)); + oidret->id[oidret->len] = ex_id; + (oidret->len)++; + + if ((ext_level + 1) == en->tree_levels) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n")); + /* leaf node */ + if (ex_id > *ident) + { + return (struct mib_node*)en; + } + else if ((i + 1) < len) + { + /* ex_id == *ident */ + en->get_objid(en->addr_inf,ext_level,i + 1,&ex_id); + (oidret->len)--; + oidret->id[oidret->len] = ex_id; + (oidret->len)++; + return (struct mib_node*)en; + } + else + { + /* (i + 1) == len */ + (oidret->len)--; + climb_tree = 1; + } + } + else + { + u8_t j; + struct nse cur_node; + + LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n")); + /* non-leaf, store right child ptr and id */ + j = i + 1; + if (j < len) + { + /* right node is the current external node */ + cur_node.r_ptr = node; + en->get_objid(en->addr_inf,ext_level,j,&cur_node.r_id); + cur_node.r_nl = ext_level + 1; + } + else + { + cur_node.r_ptr = NULL; + } + push_node(&cur_node); + if (en->ident_cmp(en->addr_inf,ext_level,i,*ident) == 0) + { + ident_len--; + ident++; + } + else + { + /* external id < *ident */ + ident_len = 0; + } + /* proceed to child */ + ext_level++; + } + } + else + { + /* i == len (en->level_len()) */ + climb_tree = 1; + } + } + else + { + /* ident_len == 0, complete with leftmost '.thing' */ + en->get_objid(en->addr_inf,ext_level,0,&ex_id); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("left en->objid==%"S32_F"\n",ex_id)); + oidret->id[oidret->len] = ex_id; + (oidret->len)++; + if ((ext_level + 1) == en->tree_levels) + { + /* leaf node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("(ext_level + 1) == en->tree_levels\n")); + return (struct mib_node*)en; + } + else + { + /* no leaf, proceed to child */ + ext_level++; + } + } + } + else if(node_type == MIB_NODE_SC) + { + mib_scalar_node *sn; + + /* scalar node */ + sn = (mib_scalar_node *)node; + if (ident_len > 0) + { + /* at .0 */ + climb_tree = 1; + } + else + { + /* ident_len == 0, complete object identifier */ + oidret->id[oidret->len] = 0; + (oidret->len)++; + /* leaf node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("completed scalar leaf\n")); + return (struct mib_node*)sn; + } + } + else + { + /* unknown/unhandled node_type */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node_type %"U16_F" unkown\n",(u16_t)node_type)); + return NULL; + } + + if (climb_tree) + { + struct nse child; + + /* find right child ptr */ + child.r_ptr = NULL; + child.r_id = 0; + child.r_nl = 0; + while ((node_stack_cnt > 0) && (child.r_ptr == NULL)) + { + pop_node(&child); + /* trim returned oid */ + (oidret->len)--; + } + if (child.r_ptr != NULL) + { + /* incoming ident is useless beyond this point */ + ident_len = 0; + oidret->id[oidret->len] = child.r_id; + oidret->len++; + node = child.r_ptr; + ext_level = child.r_nl; + } + else + { + /* tree ends here ... */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed, tree ends here\n")); + return NULL; + } + } + } + /* done, found nothing */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node==%p\n",(void*)node)); + return NULL; +} + +/** + * Test object identifier for the iso.org.dod.internet prefix. + * + * @param ident_len the length of the supplied object identifier + * @param ident points to the array of sub identifiers + * @return 1 if it matches, 0 otherwise + */ +u8_t +snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident) +{ + if ((ident_len > 3) && + (ident[0] == 1) && (ident[1] == 3) && + (ident[2] == 6) && (ident[3] == 1)) + { + return 1; + } + else + { + return 0; + } +} + +/** + * Expands object identifier to the iso.org.dod.internet + * prefix for use in getnext operation. + * + * @param ident_len the length of the supplied object identifier + * @param ident points to the array of sub identifiers + * @param oidret points to returned expanded object identifier + * @return 1 if it matches, 0 otherwise + * + * @note ident_len 0 is allowed, expanding to the first known object id!! + */ +u8_t +snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret) +{ + const s32_t *prefix_ptr; + s32_t *ret_ptr; + u8_t i; + + i = 0; + prefix_ptr = &prefix[0]; + ret_ptr = &oidret->id[0]; + ident_len = ((ident_len < 4)?ident_len:4); + while ((i < ident_len) && ((*ident) <= (*prefix_ptr))) + { + *ret_ptr++ = *prefix_ptr++; + ident++; + i++; + } + if (i == ident_len) + { + /* match, complete missing bits */ + while (i < 4) + { + *ret_ptr++ = *prefix_ptr++; + i++; + } + oidret->len = i; + return 1; + } + else + { + /* i != ident_len */ + return 0; + } +} + +#endif /* LWIP_SNMP */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/msg_in.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/msg_in.c new file mode 100644 index 0000000..1999d13 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/msg_in.c @@ -0,0 +1,1458 @@ +/** + * @file + * SNMP input message processing (RFC1157). + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include +#include "arch/cc.h" +#include "lwip/ip_addr.h" +#include "lwip/mem.h" +#include "lwip/udp.h" +#include "lwip/stats.h" + +#include "lwip/snmp.h" +#include "lwip/snmp_asn1.h" +#include "lwip/snmp_msg.h" +#include "lwip/snmp_structs.h" + + +/* public (non-static) constants */ +/** SNMP v1 == 0 */ +const s32_t snmp_version = 0; +/** default SNMP community string */ +const char snmp_publiccommunity[7] = "public"; + +/* statically allocated buffers for SNMP_CONCURRENT_REQUESTS */ +#if (SNMP_CONCURRENT_REQUESTS == 0) +#error "need at least one snmp_msg_pstat" +#endif +struct snmp_msg_pstat msg_input_list[SNMP_CONCURRENT_REQUESTS]; +/* UDP Protocol Control Block */ +struct udp_pcb *snmp1_pcb = NULL; + +static void snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); +static err_t snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat); +static err_t snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat); + + +/** + * Starts SNMP Agent. + * Allocates UDP pcb and binds it to IP_ADDR_ANY port 161. + */ +void +snmp_init(void) +{ + struct snmp_msg_pstat *msg_ps; + u8_t i; + + snmp1_pcb = udp_new(); + if (snmp1_pcb != NULL) + { + udp_recv(snmp1_pcb, snmp_recv, (void *)SNMP_IN_PORT); + udp_bind(snmp1_pcb, IP_ADDR_ANY, SNMP_IN_PORT); + } + msg_ps = &msg_input_list[0]; + for (i=0; istate = SNMP_MSG_EMPTY; + msg_ps->error_index = 0; + msg_ps->error_status = SNMP_ES_NOERROR; + msg_ps++; + } + trap_msg.pcb = snmp1_pcb; + /* The coldstart trap will only be output + if our outgoing interface is up & configured */ + snmp_coldstart_trap(); +} + +static void +snmp_error_response(struct snmp_msg_pstat *msg_ps, u8_t error) +{ + snmp_varbind_list_free(&msg_ps->outvb); + msg_ps->outvb = msg_ps->invb; + msg_ps->invb.head = NULL; + msg_ps->invb.tail = NULL; + msg_ps->invb.count = 0; + msg_ps->error_status = error; + msg_ps->error_index = 1 + msg_ps->vb_idx; + snmp_send_response(msg_ps); + snmp_varbind_list_free(&msg_ps->outvb); + msg_ps->state = SNMP_MSG_EMPTY; +} + +static void +snmp_ok_response(struct snmp_msg_pstat *msg_ps) +{ + err_t err_ret; + + err_ret = snmp_send_response(msg_ps); + if (err_ret == ERR_MEM) + { + /* serious memory problem, can't return tooBig */ +#if LWIP_STATS + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event pbufs.used = %"U16_F"\n",lwip_stats.pbuf.used)); +#endif + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event = %"S32_F"\n",msg_ps->error_status)); + } + /* free varbinds (if available) */ + snmp_varbind_list_free(&msg_ps->invb); + snmp_varbind_list_free(&msg_ps->outvb); + msg_ps->state = SNMP_MSG_EMPTY; +} + +/** + * Service an internal or external event for SNMP GET. + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + * @param msg_ps points to the assosicated message process state + */ +static void +snmp_msg_get_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) +{ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_get_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); + + if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE; + en->get_value_q(request_id, &msg_ps->ext_object_def); + } + else + { + en->get_object_def_pc(request_id, np.ident_len, np.ident); + /* search failed, object id points to unknown object (nosuchname) */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE) + { + struct mib_external_node *en; + struct snmp_varbind *vb; + + /* get_value() answer */ + en = msg_ps->ext_mib_node; + + /* allocate output varbind */ + vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind)); + LWIP_ASSERT("vb != NULL",vb != NULL); + if (vb != NULL) + { + vb->next = NULL; + vb->prev = NULL; + + /* move name from invb to outvb */ + vb->ident = msg_ps->vb_ptr->ident; + vb->ident_len = msg_ps->vb_ptr->ident_len; + /* ensure this memory is refereced once only */ + msg_ps->vb_ptr->ident = NULL; + msg_ps->vb_ptr->ident_len = 0; + + vb->value_type = msg_ps->ext_object_def.asn_type; + vb->value_len = msg_ps->ext_object_def.v_len; + if (vb->value_len > 0) + { + vb->value = mem_malloc(vb->value_len); + LWIP_ASSERT("vb->value != NULL",vb->value != NULL); + if (vb->value != NULL) + { + en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + /* search again (if vb_idx < msg_ps->invb.count) */ + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + en->get_value_pc(request_id, &msg_ps->ext_object_def); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no variable space\n")); + msg_ps->vb_ptr->ident = vb->ident; + msg_ps->vb_ptr->ident_len = vb->ident_len; + mem_free(vb); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + else + { + /* vb->value_len == 0, empty value (e.g. empty string) */ + en->get_value_a(request_id, &msg_ps->ext_object_def, 0, NULL); + vb->value = NULL; + snmp_varbind_tail_add(&msg_ps->outvb, vb); + /* search again (if vb_idx < msg_ps->invb.count) */ + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + } + else + { + en->get_value_pc(request_id, &msg_ps->ext_object_def); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + + while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_name_ptr np; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + /** test object identifier for .iso.org.dod.internet prefix */ + if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident)) + { + mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &np); + } + else + { + mn = NULL; + } + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_name_ptr = np; + + en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); + } + else + { + /* internal object */ + struct obj_def object_def; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; + mn->get_object_def(np.ident_len, np.ident, &object_def); + if (object_def.instance != MIB_OBJECT_NONE) + { + mn = mn; + } + else + { + /* search failed, object id points to unknown object (nosuchname) */ + mn = NULL; + } + if (mn != NULL) + { + struct snmp_varbind *vb; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE; + /* allocate output varbind */ + vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind)); + LWIP_ASSERT("vb != NULL",vb != NULL); + if (vb != NULL) + { + vb->next = NULL; + vb->prev = NULL; + + /* move name from invb to outvb */ + vb->ident = msg_ps->vb_ptr->ident; + vb->ident_len = msg_ps->vb_ptr->ident_len; + /* ensure this memory is refereced once only */ + msg_ps->vb_ptr->ident = NULL; + msg_ps->vb_ptr->ident_len = 0; + + vb->value_type = object_def.asn_type; + vb->value_len = object_def.v_len; + if (vb->value_len > 0) + { + vb->value = mem_malloc(vb->value_len); + LWIP_ASSERT("vb->value != NULL",vb->value != NULL); + if (vb->value != NULL) + { + mn->get_value(&object_def, vb->value_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate variable space\n")); + msg_ps->vb_ptr->ident = vb->ident; + msg_ps->vb_ptr->ident_len = vb->ident_len; + mem_free(vb); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + else + { + /* vb->value_len == 0, empty value (e.g. empty string) */ + vb->value = NULL; + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + } + } + if (mn == NULL) + { + /* mn == NULL, noSuchName */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + snmp_ok_response(msg_ps); + } +} + +/** + * Service an internal or external event for SNMP GETNEXT. + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + * @param msg_ps points to the assosicated message process state + */ +static void +snmp_msg_getnext_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) +{ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); + + if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) + { + struct mib_external_node *en; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1], &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE; + en->get_value_q(request_id, &msg_ps->ext_object_def); + } + else + { + en->get_object_def_pc(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1]); + /* search failed, object id points to unknown object (nosuchname) */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE) + { + struct mib_external_node *en; + struct snmp_varbind *vb; + + /* get_value() answer */ + en = msg_ps->ext_mib_node; + + vb = snmp_varbind_alloc(&msg_ps->ext_oid, + msg_ps->ext_object_def.asn_type, + msg_ps->ext_object_def.v_len); + if (vb != NULL) + { + en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + en->get_value_pc(request_id, &msg_ps->ext_object_def); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: couldn't allocate outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + + while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_obj_id oid; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + if (snmp_iso_prefix_expand(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident, &oid)) + { + if (msg_ps->vb_ptr->ident_len > 3) + { + /* can offset ident_len and ident */ + mn = snmp_expand_tree((struct mib_node*)&internet, + msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &oid); + } + else + { + /* can't offset ident_len -4, ident + 4 */ + mn = snmp_expand_tree((struct mib_node*)&internet, 0, NULL, &oid); + } + } + else + { + mn = NULL; + } + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_oid = oid; + + en->get_object_def_q(en->addr_inf, request_id, 1, &oid.id[oid.len - 1]); + } + else + { + /* internal object */ + struct obj_def object_def; + struct snmp_varbind *vb; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; + mn->get_object_def(1, &oid.id[oid.len - 1], &object_def); + + vb = snmp_varbind_alloc(&oid, object_def.asn_type, object_def.v_len); + if (vb != NULL) + { + msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE; + mn->get_value(&object_def, object_def.v_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv couldn't allocate outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + } + if (mn == NULL) + { + /* mn == NULL, noSuchName */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + snmp_ok_response(msg_ps); + } +} + +/** + * Service an internal or external event for SNMP SET. + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + * @param msg_ps points to the assosicated message process state + */ +static void +snmp_msg_set_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) +{ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_set_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); + + if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_SET_TEST; + en->set_test_q(request_id, &msg_ps->ext_object_def); + } + else + { + en->get_object_def_pc(request_id, np.ident_len, np.ident); + /* search failed, object id points to unknown object (nosuchname) */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_TEST) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* set_test() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + if (msg_ps->ext_object_def.access == MIB_OBJECT_READ_WRITE) + { + if ((msg_ps->ext_object_def.asn_type == msg_ps->vb_ptr->value_type) && + (en->set_test_a(request_id,&msg_ps->ext_object_def, + msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0)) + { + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + en->set_test_pc(request_id,&msg_ps->ext_object_def); + /* bad value */ + snmp_error_response(msg_ps,SNMP_ES_BADVALUE); + } + } + else + { + en->set_test_pc(request_id,&msg_ps->ext_object_def); + /* object not available for set */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF_S) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_SET_VALUE; + en->set_value_q(request_id, &msg_ps->ext_object_def, + msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value); + } + else + { + en->get_object_def_pc(request_id, np.ident_len, np.ident); + /* set_value failed, object has disappeared for some odd reason?? */ + snmp_error_response(msg_ps,SNMP_ES_GENERROR); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_VALUE) + { + struct mib_external_node *en; + + /** set_value_a() @todo: use reply value?? */ + en = msg_ps->ext_mib_node; + en->set_value_a(request_id, &msg_ps->ext_object_def, 0, NULL); + + /** @todo use set_value_pc() if toobig */ + msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; + msg_ps->vb_idx += 1; + } + + /* test all values before setting */ + while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_name_ptr np; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + /** test object identifier for .iso.org.dod.internet prefix */ + if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident)) + { + mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &np); + } + else + { + mn = NULL; + } + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_name_ptr = np; + + en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); + } + else + { + /* internal object */ + struct obj_def object_def; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; + mn->get_object_def(np.ident_len, np.ident, &object_def); + if (object_def.instance != MIB_OBJECT_NONE) + { + mn = mn; + } + else + { + /* search failed, object id points to unknown object (nosuchname) */ + mn = NULL; + } + if (mn != NULL) + { + msg_ps->state = SNMP_MSG_INTERNAL_SET_TEST; + + if (object_def.access == MIB_OBJECT_READ_WRITE) + { + if ((object_def.asn_type == msg_ps->vb_ptr->value_type) && + (mn->set_test(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0)) + { + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + /* bad value */ + snmp_error_response(msg_ps,SNMP_ES_BADVALUE); + } + } + else + { + /* object not available for set */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + } + } + if (mn == NULL) + { + /* mn == NULL, noSuchName */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + + if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + msg_ps->vb_idx = 0; + msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; + } + + /* set all values "atomically" (be as "atomic" as possible) */ + while ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_name_ptr np; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + /* skip iso prefix test, was done previously while settesting() */ + mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &np); + /* check if object is still available + (e.g. external hot-plug thingy present?) */ + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF_S; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_name_ptr = np; + + en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); + } + else + { + /* internal object */ + struct obj_def object_def; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF_S; + mn->get_object_def(np.ident_len, np.ident, &object_def); + msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; + mn->set_value(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value); + msg_ps->vb_idx += 1; + } + } + } + if ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + /* simply echo the input if we can set it + @todo do we need to return the actual value? + e.g. if value is silently modified or behaves sticky? */ + msg_ps->outvb = msg_ps->invb; + msg_ps->invb.head = NULL; + msg_ps->invb.tail = NULL; + msg_ps->invb.count = 0; + snmp_ok_response(msg_ps); + } +} + + +/** + * Handle one internal or external event. + * Called for one async event. (recv external/private answer) + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + */ +void +snmp_msg_event(u8_t request_id) +{ + struct snmp_msg_pstat *msg_ps; + + if (request_id < SNMP_CONCURRENT_REQUESTS) + { + msg_ps = &msg_input_list[request_id]; + if (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) + { + snmp_msg_getnext_event(request_id, msg_ps); + } + else if (msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) + { + snmp_msg_get_event(request_id, msg_ps); + } + else if(msg_ps->rt == SNMP_ASN1_PDU_SET_REQ) + { + snmp_msg_set_event(request_id, msg_ps); + } + } +} + + +/* lwIP UDP receive callback function */ +static void +snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port) +{ + struct udp_hdr *udphdr; + + /* suppress unused argument warning */ + if (arg); + /* peek in the UDP header (goto IP payload) */ + pbuf_header(p, UDP_HLEN); + udphdr = p->payload; + + /* check if datagram is really directed at us (including broadcast requests) */ + if ((pcb == snmp1_pcb) && (ntohs(udphdr->dest) == 161)) + { + struct snmp_msg_pstat *msg_ps; + u8_t req_idx; + + /* traverse input message process list, look for SNMP_MSG_EMPTY */ + msg_ps = &msg_input_list[0]; + req_idx = 0; + while ((req_idxstate != SNMP_MSG_EMPTY)) + { + req_idx++; + msg_ps++; + } + if (req_idx != SNMP_CONCURRENT_REQUESTS) + { + err_t err_ret; + u16_t payload_len; + u16_t payload_ofs; + u16_t varbind_ofs = 0; + + /* accepting request */ + snmp_inc_snmpinpkts(); + /* record used 'protocol control block' */ + msg_ps->pcb = pcb; + /* source address (network order) */ + msg_ps->sip = *addr; + /* source port (host order (lwIP oddity)) */ + msg_ps->sp = port; + /* read UDP payload length from UDP header */ + payload_len = ntohs(udphdr->len) - UDP_HLEN; + + /* adjust to UDP payload */ + payload_ofs = UDP_HLEN; + + /* check total length, version, community, pdu type */ + err_ret = snmp_pdu_header_check(p, payload_ofs, payload_len, &varbind_ofs, msg_ps); + if (((msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) || + (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) || + (msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)) && + ((msg_ps->error_status == SNMP_ES_NOERROR) && + (msg_ps->error_index == 0)) ) + { + /* Only accept requests and requests without error (be robust) */ + err_ret = err_ret; + } + else + { + /* Reject response and trap headers or error requests as input! */ + err_ret = ERR_ARG; + } + if (err_ret == ERR_OK) + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv ok, community %s\n", msg_ps->community)); + + /* Builds a list of variable bindings. Copy the varbinds from the pbuf + chain to glue them when these are divided over two or more pbuf's. */ + err_ret = snmp_pdu_dec_varbindlist(p, varbind_ofs, &varbind_ofs, msg_ps); + if ((err_ret == ERR_OK) && (msg_ps->invb.count > 0)) + { + /* we've decoded the incoming message, release input msg now */ + pbuf_free(p); + + msg_ps->error_status = SNMP_ES_NOERROR; + msg_ps->error_index = 0; + /* find object for each variable binding */ + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + /* first variable binding from list to inspect */ + msg_ps->vb_idx = 0; + + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv varbind cnt=%"U16_F"\n",(u16_t)msg_ps->invb.count)); + + /* handle input event and as much objects as possible in one go */ + snmp_msg_event(req_idx); + } + else + { + /* varbind-list decode failed, or varbind list empty. + drop request silently, do not return error! + (errors are only returned for a specific varbind failure) */ + pbuf_free(p); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_dec_varbindlist() failed\n")); + } + } + else + { + /* header check failed + drop request silently, do not return error! */ + pbuf_free(p); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_header_check() failed\n")); + } + } + else + { + /* exceeding number of concurrent requests */ + pbuf_free(p); + } + } + else + { + /* datagram not for us */ + pbuf_free(p); + } +} + +/** + * Checks and decodes incoming SNMP message header, logs header errors. + * + * @param p points to pbuf chain of SNMP message (UDP payload) + * @param ofs points to first octet of SNMP message + * @param pdu_len the length of the UDP payload + * @param ofs_ret returns the ofset of the variable bindings + * @param m_stat points to the current message request state return + * @return + * - ERR_OK SNMP header is sane and accepted + * - ERR_ARG SNMP header is either malformed or rejected + */ +static err_t +snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat) +{ + err_t derr; + u16_t len, ofs_base; + u8_t len_octets; + u8_t type; + s32_t version; + + ofs_base = ofs; + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || + (pdu_len != (1 + len_octets + len)) || + (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ))) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (version) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &version); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + if (version != 0) + { + /* not version 1 */ + snmp_inc_snmpinbadversions(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR))) + { + /* can't decode or no octet string (community) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, SNMP_COMMUNITY_STR_LEN, m_stat->community); + if (derr != ERR_OK) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + /* add zero terminator */ + len = ((len < (SNMP_COMMUNITY_STR_LEN))?(len):(SNMP_COMMUNITY_STR_LEN)); + m_stat->community[len] = 0; + m_stat->com_strlen = len; + if (strncmp(snmp_publiccommunity, (const char*)m_stat->community, SNMP_COMMUNITY_STR_LEN) != 0) + { + /** @todo: move this if we need to check more names */ + snmp_inc_snmpinbadcommunitynames(); + snmp_authfail_trap(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if (derr != ERR_OK) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + switch(type) + { + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_REQ): + /* GetRequest PDU */ + snmp_inc_snmpingetrequests(); + derr = ERR_OK; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_NEXT_REQ): + /* GetNextRequest PDU */ + snmp_inc_snmpingetnexts(); + derr = ERR_OK; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP): + /* GetResponse PDU */ + snmp_inc_snmpingetresponses(); + derr = ERR_ARG; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_SET_REQ): + /* SetRequest PDU */ + snmp_inc_snmpinsetrequests(); + derr = ERR_OK; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP): + /* Trap PDU */ + snmp_inc_snmpintraps(); + derr = ERR_ARG; + break; + default: + snmp_inc_snmpinasnparseerrs(); + derr = ERR_ARG; + break; + } + if (derr != ERR_OK) + { + /* unsupported input PDU for this agent (no parse error) */ + return ERR_ARG; + } + m_stat->rt = type & 0x1F; + ofs += (1 + len_octets); + if (len != (pdu_len - (ofs - ofs_base))) + { + /* decoded PDU length does not equal actual payload length */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (request ID) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->rid); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (error-status) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + /* must be noError (0) for incoming requests. + log errors for mib-2 completeness and for debug purposes */ + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_status); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + switch (m_stat->error_status) + { + case SNMP_ES_TOOBIG: + snmp_inc_snmpintoobigs(); + break; + case SNMP_ES_NOSUCHNAME: + snmp_inc_snmpinnosuchnames(); + break; + case SNMP_ES_BADVALUE: + snmp_inc_snmpinbadvalues(); + break; + case SNMP_ES_READONLY: + snmp_inc_snmpinreadonlys(); + break; + case SNMP_ES_GENERROR: + snmp_inc_snmpingenerrs(); + break; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (error-index) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + /* must be 0 for incoming requests. + decode anyway to catch bad integers (and dirty tricks) */ + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_index); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + *ofs_ret = ofs; + return ERR_OK; +} + +static err_t +snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat) +{ + err_t derr; + u16_t len, vb_len; + u8_t len_octets; + u8_t type; + + /* variable binding list */ + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &vb_len); + if ((derr != ERR_OK) || + (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ))) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets); + + /* start with empty list */ + m_stat->invb.count = 0; + m_stat->invb.head = NULL; + m_stat->invb.tail = NULL; + + while (vb_len > 0) + { + struct snmp_obj_id oid, oid_value; + struct snmp_varbind *vb; + + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || + (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)) || + (len <= 0) || (len > vb_len)) + { + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + ofs += (1 + len_octets); + vb_len -= (1 + len_octets); + + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID))) + { + /* can't decode object name length */ + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid); + if (derr != ERR_OK) + { + /* can't decode object name */ + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + vb_len -= (1 + len_octets + len); + + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if (derr != ERR_OK) + { + /* can't decode object value length */ + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + + switch (type) + { + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): + vb = snmp_varbind_alloc(&oid, type, sizeof(s32_t)); + if (vb != NULL) + { + s32_t *vptr = vb->value; + + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, vptr); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): + vb = snmp_varbind_alloc(&oid, type, sizeof(u32_t)); + if (vb != NULL) + { + u32_t *vptr = vb->value; + + derr = snmp_asn1_dec_u32t(p, ofs + 1 + len_octets, len, vptr); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): + vb = snmp_varbind_alloc(&oid, type, len); + if (vb != NULL) + { + derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): + vb = snmp_varbind_alloc(&oid, type, 0); + if (vb != NULL) + { + snmp_varbind_tail_add(&m_stat->invb, vb); + derr = ERR_OK; + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): + derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid_value); + if (derr == ERR_OK) + { + vb = snmp_varbind_alloc(&oid, type, oid_value.len * sizeof(s32_t)); + if (vb != NULL) + { + u8_t i = oid_value.len; + s32_t *vptr = vb->value; + + while(i > 0) + { + i--; + vptr[i] = oid_value.id[i]; + } + snmp_varbind_tail_add(&m_stat->invb, vb); + derr = ERR_OK; + } + else + { + derr = ERR_ARG; + } + } + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): + if (len == 4) + { + /* must be exactly 4 octets! */ + vb = snmp_varbind_alloc(&oid, type, 4); + if (vb != NULL) + { + derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + } + else + { + derr = ERR_ARG; + } + break; + default: + derr = ERR_ARG; + break; + } + if (derr != ERR_OK) + { + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + vb_len -= (1 + len_octets + len); + } + + if (m_stat->rt == SNMP_ASN1_PDU_SET_REQ) + { + snmp_add_snmpintotalsetvars(m_stat->invb.count); + } + else + { + snmp_add_snmpintotalreqvars(m_stat->invb.count); + } + + *ofs_ret = ofs; + return ERR_OK; +} + +struct snmp_varbind* +snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len) +{ + struct snmp_varbind *vb; + + vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind)); + LWIP_ASSERT("vb != NULL",vb != NULL); + if (vb != NULL) + { + u8_t i; + + vb->next = NULL; + vb->prev = NULL; + i = oid->len; + vb->ident_len = i; + if (i > 0) + { + /* allocate array of s32_t for our object identifier */ + vb->ident = (s32_t*)mem_malloc(sizeof(s32_t) * i); + LWIP_ASSERT("vb->ident != NULL",vb->ident != NULL); + if (vb->ident == NULL) + { + mem_free(vb); + return NULL; + } + while(i > 0) + { + i--; + vb->ident[i] = oid->id[i]; + } + } + else + { + /* i == 0, pass zero length object identifier */ + vb->ident = NULL; + } + vb->value_type = type; + vb->value_len = len; + if (len > 0) + { + /* allocate raw bytes for our object value */ + vb->value = mem_malloc(len); + LWIP_ASSERT("vb->value != NULL",vb->value != NULL); + if (vb->value == NULL) + { + if (vb->ident != NULL) + { + mem_free(vb->ident); + } + mem_free(vb); + return NULL; + } + } + else + { + /* ASN1_NUL type, or zero length ASN1_OC_STR */ + vb->value = NULL; + } + } + return vb; +} + +void +snmp_varbind_free(struct snmp_varbind *vb) +{ + if (vb->value != NULL ) + { + mem_free(vb->value); + } + if (vb->ident != NULL ) + { + mem_free(vb->ident); + } + mem_free(vb); +} + +void +snmp_varbind_list_free(struct snmp_varbind_root *root) +{ + struct snmp_varbind *vb, *prev; + + vb = root->tail; + while ( vb != NULL ) + { + prev = vb->prev; + snmp_varbind_free(vb); + vb = prev; + } + root->count = 0; + root->head = NULL; + root->tail = NULL; +} + +void +snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb) +{ + if (root->count == 0) + { + /* add first varbind to list */ + root->head = vb; + root->tail = vb; + } + else + { + /* add nth varbind to list tail */ + root->tail->next = vb; + vb->prev = root->tail; + root->tail = vb; + } + root->count += 1; +} + +struct snmp_varbind* +snmp_varbind_tail_remove(struct snmp_varbind_root *root) +{ + struct snmp_varbind* vb; + + if (root->count > 0) + { + /* remove tail varbind */ + vb = root->tail; + root->tail = vb->prev; + vb->prev->next = NULL; + root->count -= 1; + } + else + { + /* nothing to remove */ + vb = NULL; + } + return vb; +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/msg_out.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/msg_out.c new file mode 100644 index 0000000..0da70de --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/snmp/msg_out.c @@ -0,0 +1,687 @@ +/** + * @file + * SNMP output message processing (RFC1157). + * + * Output responses and traps are build in two passes: + * + * Pass 0: iterate over the output message backwards to determine encoding lengths + * Pass 1: the actual forward encoding of internal form into ASN1 + * + * The single-pass encoding method described by Comer & Stevens + * requires extra buffer space and copying for reversal of the packet. + * The buffer requirement can be prohibitively large for big payloads + * (>= 484) therefore we use the two encoding passes. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "arch/cc.h" +#include "lwip/udp.h" +#include "lwip/netif.h" + +#include "lwip/snmp.h" +#include "lwip/snmp_asn1.h" +#include "lwip/snmp_msg.h" + +struct snmp_trap_dst +{ + /* destination IP address in network order */ + struct ip_addr dip; + /* set to 0 when disabled, >0 when enabled */ + u8_t enable; +}; +#if (SNMP_TRAP_DESTINATIONS == 0) +#error "need at least one trap destination" +#endif +struct snmp_trap_dst trap_dst[SNMP_TRAP_DESTINATIONS]; + +/** TRAP message structure */ +struct snmp_msg_trap trap_msg; + +static u16_t snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len); +static u16_t snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len); +static u16_t snmp_varbind_list_sum(struct snmp_varbind_root *root); + +static u16_t snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p); +static u16_t snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p); +static u16_t snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs); + +/** + * Sets enable switch for this trap destination. + * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 + * @param enable switch if 0 destination is disabled >0 enabled. + */ +void +snmp_trap_dst_enable(u8_t dst_idx, u8_t enable) +{ + if (dst_idx < SNMP_TRAP_DESTINATIONS) + { + trap_dst[dst_idx].enable = enable; + } +} + +/** + * Sets IPv4 address for this trap destination. + * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 + * @param dst IPv4 address in host order. + */ +void +snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst) +{ + if (dst_idx < SNMP_TRAP_DESTINATIONS) + { + trap_dst[dst_idx].dip.addr = htonl(dst->addr); + } +} + +/** + * Sends a 'getresponse' message to the request originator. + * + * @param m_stat points to the current message request state source + * @return ERR_OK when success, ERR_MEM if we're out of memory + * + * @note the caller is responsible for filling in outvb in the m_stat + * and provide error-status and index (except for tooBig errors) ... + */ +err_t +snmp_send_response(struct snmp_msg_pstat *m_stat) +{ + struct snmp_varbind_root emptyvb = {NULL, NULL, 0, 0, 0}; + struct pbuf *p; + u16_t tot_len; + err_t err; + + /* pass 0, calculate length fields */ + tot_len = snmp_varbind_list_sum(&m_stat->outvb); + tot_len = snmp_resp_header_sum(m_stat, tot_len); + + /* try allocating pbuf(s) for complete response */ + p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); + if (p == NULL) + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() tooBig\n")); + + /* can't construct reply, return error-status tooBig */ + m_stat->error_status = SNMP_ES_TOOBIG; + m_stat->error_index = 0; + /* pass 0, recalculate lengths, for empty varbind-list */ + tot_len = snmp_varbind_list_sum(&emptyvb); + tot_len = snmp_resp_header_sum(m_stat, tot_len); + /* retry allocation once for header and empty varbind-list */ + p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); + } + if (p != NULL) + { + /* first pbuf alloc try or retry alloc success */ + u16_t ofs; + + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() p != NULL\n")); + + /* pass 1, size error, encode packet ino the pbuf(s) */ + ofs = snmp_resp_header_enc(m_stat, p); + if (m_stat->error_status == SNMP_ES_TOOBIG) + { + snmp_varbind_list_enc(&emptyvb, p, ofs); + } + else + { + snmp_varbind_list_enc(&m_stat->outvb, p, ofs); + } + + switch (m_stat->error_status) + { + case SNMP_ES_TOOBIG: + snmp_inc_snmpouttoobigs(); + break; + case SNMP_ES_NOSUCHNAME: + snmp_inc_snmpoutnosuchnames(); + break; + case SNMP_ES_BADVALUE: + snmp_inc_snmpoutbadvalues(); + break; + case SNMP_ES_GENERROR: + snmp_inc_snmpoutgenerrs(); + break; + } + snmp_inc_snmpoutgetresponses(); + snmp_inc_snmpoutpkts(); + + /** @todo do we need separate rx and tx pcbs for threaded case? */ + /** connect to the originating source */ + udp_connect(m_stat->pcb, &m_stat->sip, m_stat->sp); + err = udp_send(m_stat->pcb, p); + if (err == ERR_MEM) + { + /** @todo release some memory, retry and return tooBig? tooMuchHassle? */ + err = ERR_MEM; + } + else + { + err = ERR_OK; + } + /** disassociate remote address and port with this pcb */ + udp_disconnect(m_stat->pcb); + + pbuf_free(p); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() done\n")); + return err; + } + else + { + /* first pbuf alloc try or retry alloc failed + very low on memory, couldn't return tooBig */ + return ERR_MEM; + } +} + + +/** + * Sends an generic or enterprise specific trap message. + * + * @param generic_trap is the trap code + * @param eoid points to enterprise object identifier + * @param specific_trap used for enterprise traps when generic_trap == 6 + * @return ERR_OK when success, ERR_MEM if we're out of memory + * + * @note the caller is responsible for filling in outvb in the trap_msg + * @note the use of the enterpise identifier field + * is per RFC1215. + * Use .iso.org.dod.internet.mgmt.mib-2.snmp for generic traps + * and .iso.org.dod.internet.private.enterprises.yourenterprise + * (sysObjectID) for specific traps. + */ +err_t +snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap) +{ + struct snmp_trap_dst *td; + struct netif *dst_if; + struct ip_addr dst_ip; + struct pbuf *p; + u16_t i,tot_len; + + for (i=0, td = &trap_dst[0]; ienable != 0) && (td->dip.addr != 0)) + { + /* network order trap destination */ + trap_msg.dip.addr = td->dip.addr; + /* lookup current source address for this dst */ + dst_if = ip_route(&td->dip); + dst_ip.addr = ntohl(dst_if->ip_addr.addr); + trap_msg.sip_raw[0] = dst_ip.addr >> 24; + trap_msg.sip_raw[1] = dst_ip.addr >> 16; + trap_msg.sip_raw[2] = dst_ip.addr >> 8; + trap_msg.sip_raw[3] = dst_ip.addr; + trap_msg.gen_trap = generic_trap; + trap_msg.spc_trap = specific_trap; + if (generic_trap == SNMP_GENTRAP_ENTERPRISESPC) + { + /* enterprise-Specific trap */ + trap_msg.enterprise = eoid; + } + else + { + /* generic (MIB-II) trap */ + snmp_get_snmpgrpid_ptr(&trap_msg.enterprise); + } + snmp_get_sysuptime(&trap_msg.ts); + + /* pass 0, calculate length fields */ + tot_len = snmp_varbind_list_sum(&trap_msg.outvb); + tot_len = snmp_trap_header_sum(&trap_msg, tot_len); + + /* allocate pbuf(s) */ + p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); + if (p != NULL) + { + u16_t ofs; + + /* pass 1, encode packet ino the pbuf(s) */ + ofs = snmp_trap_header_enc(&trap_msg, p); + snmp_varbind_list_enc(&trap_msg.outvb, p, ofs); + + snmp_inc_snmpouttraps(); + snmp_inc_snmpoutpkts(); + + /** connect to the TRAP destination */ + udp_connect(trap_msg.pcb, &trap_msg.dip, SNMP_TRAP_PORT); + udp_send(trap_msg.pcb, p); + /** disassociate remote address and port with this pcb */ + udp_disconnect(trap_msg.pcb); + + pbuf_free(p); + } + else + { + return ERR_MEM; + } + } + } + return ERR_OK; +} + +void +snmp_coldstart_trap(void) +{ + trap_msg.outvb.head = NULL; + trap_msg.outvb.tail = NULL; + trap_msg.outvb.count = 0; + snmp_send_trap(SNMP_GENTRAP_COLDSTART, NULL, 0); +} + +void +snmp_authfail_trap(void) +{ + u8_t enable; + snmp_get_snmpenableauthentraps(&enable); + if (enable == 1) + { + trap_msg.outvb.head = NULL; + trap_msg.outvb.tail = NULL; + trap_msg.outvb.count = 0; + snmp_send_trap(SNMP_GENTRAP_AUTHFAIL, NULL, 0); + } +} + +/** + * Sums response header field lengths from tail to head and + * returns resp_header_lengths for second encoding pass. + * + * @param vb_len varbind-list length + * @param rhl points to returned header lengths + * @return the required lenght for encoding the response header + */ +static u16_t +snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len) +{ + u16_t tot_len; + struct snmp_resp_header_lengths *rhl; + + rhl = &m_stat->rhl; + tot_len = vb_len; + snmp_asn1_enc_s32t_cnt(m_stat->error_index, &rhl->erridxlen); + snmp_asn1_enc_length_cnt(rhl->erridxlen, &rhl->erridxlenlen); + tot_len += 1 + rhl->erridxlenlen + rhl->erridxlen; + + snmp_asn1_enc_s32t_cnt(m_stat->error_status, &rhl->errstatlen); + snmp_asn1_enc_length_cnt(rhl->errstatlen, &rhl->errstatlenlen); + tot_len += 1 + rhl->errstatlenlen + rhl->errstatlen; + + snmp_asn1_enc_s32t_cnt(m_stat->rid, &rhl->ridlen); + snmp_asn1_enc_length_cnt(rhl->ridlen, &rhl->ridlenlen); + tot_len += 1 + rhl->ridlenlen + rhl->ridlen; + + rhl->pdulen = tot_len; + snmp_asn1_enc_length_cnt(rhl->pdulen, &rhl->pdulenlen); + tot_len += 1 + rhl->pdulenlen; + + rhl->comlen = m_stat->com_strlen; + snmp_asn1_enc_length_cnt(rhl->comlen, &rhl->comlenlen); + tot_len += 1 + rhl->comlenlen + rhl->comlen; + + snmp_asn1_enc_s32t_cnt(snmp_version, &rhl->verlen); + snmp_asn1_enc_length_cnt(rhl->verlen, &rhl->verlenlen); + tot_len += 1 + rhl->verlen + rhl->verlenlen; + + rhl->seqlen = tot_len; + snmp_asn1_enc_length_cnt(rhl->seqlen, &rhl->seqlenlen); + tot_len += 1 + rhl->seqlenlen; + + return tot_len; +} + +/** + * Sums trap header field lengths from tail to head and + * returns trap_header_lengths for second encoding pass. + * + * @param vb_len varbind-list length + * @param thl points to returned header lengths + * @return the required lenght for encoding the trap header + */ +static u16_t +snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len) +{ + u16_t tot_len; + struct snmp_trap_header_lengths *thl; + + thl = &m_trap->thl; + tot_len = vb_len; + + snmp_asn1_enc_u32t_cnt(m_trap->ts, &thl->tslen); + snmp_asn1_enc_length_cnt(thl->tslen, &thl->tslenlen); + tot_len += 1 + thl->tslen + thl->tslenlen; + + snmp_asn1_enc_s32t_cnt(m_trap->spc_trap, &thl->strplen); + snmp_asn1_enc_length_cnt(thl->strplen, &thl->strplenlen); + tot_len += 1 + thl->strplen + thl->strplenlen; + + snmp_asn1_enc_s32t_cnt(m_trap->gen_trap, &thl->gtrplen); + snmp_asn1_enc_length_cnt(thl->gtrplen, &thl->gtrplenlen); + tot_len += 1 + thl->gtrplen + thl->gtrplenlen; + + thl->aaddrlen = 4; + snmp_asn1_enc_length_cnt(thl->aaddrlen, &thl->aaddrlenlen); + tot_len += 1 + thl->aaddrlen + thl->aaddrlenlen; + + snmp_asn1_enc_oid_cnt(m_trap->enterprise->len, &m_trap->enterprise->id[0], &thl->eidlen); + snmp_asn1_enc_length_cnt(thl->eidlen, &thl->eidlenlen); + tot_len += 1 + thl->eidlen + thl->eidlenlen; + + thl->pdulen = tot_len; + snmp_asn1_enc_length_cnt(thl->pdulen, &thl->pdulenlen); + tot_len += 1 + thl->pdulenlen; + + thl->comlen = sizeof(snmp_publiccommunity) - 1; + snmp_asn1_enc_length_cnt(thl->comlen, &thl->comlenlen); + tot_len += 1 + thl->comlenlen + thl->comlen; + + snmp_asn1_enc_s32t_cnt(snmp_version, &thl->verlen); + snmp_asn1_enc_length_cnt(thl->verlen, &thl->verlenlen); + tot_len += 1 + thl->verlen + thl->verlenlen; + + thl->seqlen = tot_len; + snmp_asn1_enc_length_cnt(thl->seqlen, &thl->seqlenlen); + tot_len += 1 + thl->seqlenlen; + + return tot_len; +} + +/** + * Sums varbind lengths from tail to head and + * annotates lengths in varbind for second encoding pass. + * + * @param root points to the root of the variable binding list + * @return the required lenght for encoding the variable bindings + */ +static u16_t +snmp_varbind_list_sum(struct snmp_varbind_root *root) +{ + struct snmp_varbind *vb; + u32_t *uint_ptr; + s32_t *sint_ptr; + u16_t tot_len; + + tot_len = 0; + vb = root->tail; + while ( vb != NULL ) + { + /* encoded value lenght depends on type */ + switch (vb->value_type) + { + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): + sint_ptr = vb->value; + snmp_asn1_enc_s32t_cnt(*sint_ptr, &vb->vlen); + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): + uint_ptr = vb->value; + snmp_asn1_enc_u32t_cnt(*uint_ptr, &vb->vlen); + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): + vb->vlen = vb->value_len; + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): + sint_ptr = vb->value; + snmp_asn1_enc_oid_cnt(vb->value_len / sizeof(s32_t), sint_ptr, &vb->vlen); + break; + default: + /* unsupported type */ + vb->vlen = 0; + break; + }; + /* encoding length of value length field */ + snmp_asn1_enc_length_cnt(vb->vlen, &vb->vlenlen); + snmp_asn1_enc_oid_cnt(vb->ident_len, vb->ident, &vb->olen); + snmp_asn1_enc_length_cnt(vb->olen, &vb->olenlen); + + vb->seqlen = 1 + vb->vlenlen + vb->vlen; + vb->seqlen += 1 + vb->olenlen + vb->olen; + snmp_asn1_enc_length_cnt(vb->seqlen, &vb->seqlenlen); + + /* varbind seq */ + tot_len += 1 + vb->seqlenlen + vb->seqlen; + + vb = vb->prev; + } + + /* varbind-list seq */ + root->seqlen = tot_len; + snmp_asn1_enc_length_cnt(root->seqlen, &root->seqlenlen); + tot_len += 1 + root->seqlenlen; + + return tot_len; +} + +/** + * Encodes response header from head to tail. + */ +static u16_t +snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p) +{ + u16_t ofs; + + ofs = 0; + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.seqlen); + ofs += m_stat->rhl.seqlenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.verlen); + ofs += m_stat->rhl.verlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.verlen, snmp_version); + ofs += m_stat->rhl.verlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.comlen); + ofs += m_stat->rhl.comlenlen; + snmp_asn1_enc_raw(p, ofs, m_stat->rhl.comlen, m_stat->community); + ofs += m_stat->rhl.comlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.pdulen); + ofs += m_stat->rhl.pdulenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.ridlen); + ofs += m_stat->rhl.ridlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.ridlen, m_stat->rid); + ofs += m_stat->rhl.ridlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.errstatlen); + ofs += m_stat->rhl.errstatlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.errstatlen, m_stat->error_status); + ofs += m_stat->rhl.errstatlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.erridxlen); + ofs += m_stat->rhl.erridxlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.erridxlen, m_stat->error_index); + ofs += m_stat->rhl.erridxlen; + + return ofs; +} + +/** + * Encodes trap header from head to tail. + */ +static u16_t +snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p) +{ + u16_t ofs; + + ofs = 0; + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.seqlen); + ofs += m_trap->thl.seqlenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.verlen); + ofs += m_trap->thl.verlenlen; + snmp_asn1_enc_s32t(p, ofs, m_trap->thl.verlen, snmp_version); + ofs += m_trap->thl.verlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.comlen); + ofs += m_trap->thl.comlenlen; + snmp_asn1_enc_raw(p, ofs, m_trap->thl.comlen, (u8_t *)&snmp_publiccommunity[0]); + ofs += m_trap->thl.comlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.pdulen); + ofs += m_trap->thl.pdulenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.eidlen); + ofs += m_trap->thl.eidlenlen; + snmp_asn1_enc_oid(p, ofs, m_trap->enterprise->len, &m_trap->enterprise->id[0]); + ofs += m_trap->thl.eidlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.aaddrlen); + ofs += m_trap->thl.aaddrlenlen; + snmp_asn1_enc_raw(p, ofs, m_trap->thl.aaddrlen, &m_trap->sip_raw[0]); + ofs += m_trap->thl.aaddrlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.gtrplen); + ofs += m_trap->thl.gtrplenlen; + snmp_asn1_enc_u32t(p, ofs, m_trap->thl.gtrplen, m_trap->gen_trap); + ofs += m_trap->thl.gtrplen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.strplen); + ofs += m_trap->thl.strplenlen; + snmp_asn1_enc_u32t(p, ofs, m_trap->thl.strplen, m_trap->spc_trap); + ofs += m_trap->thl.strplen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.tslen); + ofs += m_trap->thl.tslenlen; + snmp_asn1_enc_u32t(p, ofs, m_trap->thl.tslen, m_trap->ts); + ofs += m_trap->thl.tslen; + + return ofs; +} + +/** + * Encodes varbind list from head to tail. + */ +static u16_t +snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs) +{ + struct snmp_varbind *vb; + s32_t *sint_ptr; + u32_t *uint_ptr; + u8_t *raw_ptr; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, root->seqlen); + ofs += root->seqlenlen; + + vb = root->head; + while ( vb != NULL ) + { + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, vb->seqlen); + ofs += vb->seqlenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, vb->olen); + ofs += vb->olenlen; + snmp_asn1_enc_oid(p, ofs, vb->ident_len, &vb->ident[0]); + ofs += vb->olen; + + snmp_asn1_enc_type(p, ofs, vb->value_type); + ofs += 1; + snmp_asn1_enc_length(p, ofs, vb->vlen); + ofs += vb->vlenlen; + + switch (vb->value_type) + { + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): + sint_ptr = vb->value; + snmp_asn1_enc_s32t(p, ofs, vb->vlen, *sint_ptr); + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): + uint_ptr = vb->value; + snmp_asn1_enc_u32t(p, ofs, vb->vlen, *uint_ptr); + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): + raw_ptr = vb->value; + snmp_asn1_enc_raw(p, ofs, vb->vlen, raw_ptr); + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): + sint_ptr = vb->value; + snmp_asn1_enc_oid(p, ofs, vb->value_len / sizeof(s32_t), sint_ptr); + break; + default: + /* unsupported type */ + break; + }; + ofs += vb->vlen; + vb = vb->next; + } + return ofs; +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/stats.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/stats.c new file mode 100644 index 0000000..e3cf4a3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/stats.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" + +#include "lwip/def.h" + +#include "lwip/stats.h" +#include "lwip/mem.h" + + +#if LWIP_STATS +struct stats_ lwip_stats; + +void +stats_init(void) +{ + memset(&lwip_stats, 0, sizeof(struct stats_)); +} +#if LWIP_STATS_DISPLAY +void +stats_display_proto(struct stats_proto *proto, char *name) +{ + LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); + LWIP_PLATFORM_DIAG(("xmit: %"S16_F"\n\t", proto->xmit)); + LWIP_PLATFORM_DIAG(("rexmit: %"S16_F"\n\t", proto->rexmit)); + LWIP_PLATFORM_DIAG(("recv: %"S16_F"\n\t", proto->recv)); + LWIP_PLATFORM_DIAG(("fw: %"S16_F"\n\t", proto->fw)); + LWIP_PLATFORM_DIAG(("drop: %"S16_F"\n\t", proto->drop)); + LWIP_PLATFORM_DIAG(("chkerr: %"S16_F"\n\t", proto->chkerr)); + LWIP_PLATFORM_DIAG(("lenerr: %"S16_F"\n\t", proto->lenerr)); + LWIP_PLATFORM_DIAG(("memerr: %"S16_F"\n\t", proto->memerr)); + LWIP_PLATFORM_DIAG(("rterr: %"S16_F"\n\t", proto->rterr)); + LWIP_PLATFORM_DIAG(("proterr: %"S16_F"\n\t", proto->proterr)); + LWIP_PLATFORM_DIAG(("opterr: %"S16_F"\n\t", proto->opterr)); + LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", proto->err)); + LWIP_PLATFORM_DIAG(("cachehit: %"S16_F"\n", proto->cachehit)); +} + +void +stats_display_pbuf(struct stats_pbuf *pbuf) +{ + LWIP_PLATFORM_DIAG(("\nPBUF\n\t")); + LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", pbuf->avail)); + LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", pbuf->used)); + LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", pbuf->max)); + LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", pbuf->err)); + LWIP_PLATFORM_DIAG(("alloc_locked: %"S16_F"\n\t", pbuf->alloc_locked)); + LWIP_PLATFORM_DIAG(("refresh_locked: %"S16_F"\n", pbuf->refresh_locked)); +} + +void +stats_display_mem(struct stats_mem *mem, char *name) +{ + LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name)); + LWIP_PLATFORM_DIAG(("avail: %"MEM_SIZE_F"\n\t", mem->avail)); + LWIP_PLATFORM_DIAG(("used: %"MEM_SIZE_F"\n\t", mem->used)); + LWIP_PLATFORM_DIAG(("max: %"MEM_SIZE_F"\n\t", mem->max)); + LWIP_PLATFORM_DIAG(("err: %"MEM_SIZE_F"\n", mem->err)); + +} + +void +stats_display(void) +{ + s16_t i; + char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN", + "TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"}; + stats_display_proto(&lwip_stats.link, "LINK"); + stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG"); + stats_display_proto(&lwip_stats.ip, "IP"); + stats_display_proto(&lwip_stats.icmp, "ICMP"); + stats_display_proto(&lwip_stats.udp, "UDP"); + stats_display_proto(&lwip_stats.tcp, "TCP"); + stats_display_pbuf(&lwip_stats.pbuf); + stats_display_mem(&lwip_stats.mem, "HEAP"); + for (i = 0; i < MEMP_MAX; i++) { + stats_display_mem(&lwip_stats.memp[i], memp_names[i]); + } + +} +#endif /* LWIP_STATS_DISPLAY */ +#endif /* LWIP_STATS */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/sys.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/sys.c new file mode 100644 index 0000000..2ecb880 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/sys.c @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/sys.h" +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/memp.h" + +#if (NO_SYS == 0) + +struct sswt_cb +{ + s16_t timeflag; + sys_sem_t *psem; +}; + + + +void +sys_mbox_fetch(sys_mbox_t mbox, void **msg) +{ + u32_t time; + struct sys_timeouts *timeouts; + struct sys_timeo *tmptimeout; + sys_timeout_handler h; + void *arg; + + + again: + timeouts = sys_arch_timeouts(); + + if (!timeouts || !timeouts->next) { + sys_arch_mbox_fetch(mbox, msg, 0); + } else { + if (timeouts->next->time > 0) { + time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time); + } else { + time = SYS_ARCH_TIMEOUT; + } + + if (time == SYS_ARCH_TIMEOUT) { + /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message + could be fetched. We should now call the timeout handler and + deallocate the memory allocated for the timeout. */ + tmptimeout = timeouts->next; + timeouts->next = tmptimeout->next; + h = tmptimeout->h; + arg = tmptimeout->arg; + memp_free(MEMP_SYS_TIMEOUT, tmptimeout); + if (h != NULL) { + LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg)); + h(arg); + } + + /* We try again to fetch a message from the mbox. */ + goto again; + } else { + /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout + occured. The time variable is set to the number of + milliseconds we waited for the message. */ + if (time <= timeouts->next->time) { + timeouts->next->time -= time; + } else { + timeouts->next->time = 0; + } + } + + } +} + +void +sys_sem_wait(sys_sem_t sem) +{ + u32_t time; + struct sys_timeouts *timeouts; + struct sys_timeo *tmptimeout; + sys_timeout_handler h; + void *arg; + + /* while (sys_arch_sem_wait(sem, 1000) == 0); + return;*/ + + again: + + timeouts = sys_arch_timeouts(); + + if (!timeouts || !timeouts->next) { + sys_arch_sem_wait(sem, 0); + } else { + if (timeouts->next->time > 0) { + time = sys_arch_sem_wait(sem, timeouts->next->time); + } else { + time = SYS_ARCH_TIMEOUT; + } + + if (time == SYS_ARCH_TIMEOUT) { + /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message + could be fetched. We should now call the timeout handler and + deallocate the memory allocated for the timeout. */ + tmptimeout = timeouts->next; + timeouts->next = tmptimeout->next; + h = tmptimeout->h; + arg = tmptimeout->arg; + memp_free(MEMP_SYS_TIMEOUT, tmptimeout); + if (h != NULL) { + LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg)); + h(arg); + } + + + /* We try again to fetch a message from the mbox. */ + goto again; + } else { + /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout + occured. The time variable is set to the number of + milliseconds we waited for the message. */ + if (time <= timeouts->next->time) { + timeouts->next->time -= time; + } else { + timeouts->next->time = 0; + } + } + + } +} + +void +sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg) +{ + struct sys_timeouts *timeouts; + struct sys_timeo *timeout, *t; + + timeout = memp_malloc(MEMP_SYS_TIMEOUT); + if (timeout == NULL) { + return; + } + timeout->next = NULL; + timeout->h = h; + timeout->arg = arg; + timeout->time = msecs; + + timeouts = sys_arch_timeouts(); + + LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n", + (void *)timeout, msecs, (void *)h, (void *)arg)); + + LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL); + + if (timeouts->next == NULL) { + timeouts->next = timeout; + return; + } + + if (timeouts->next->time > msecs) { + timeouts->next->time -= msecs; + timeout->next = timeouts->next; + timeouts->next = timeout; + } else { + for(t = timeouts->next; t != NULL; t = t->next) { + timeout->time -= t->time; + if (t->next == NULL || t->next->time > timeout->time) { + if (t->next != NULL) { + t->next->time -= timeout->time; + } + timeout->next = t->next; + t->next = timeout; + break; + } + } + } + +} + +/* Go through timeout list (for this task only) and remove the first matching entry, + even though the timeout has not triggered yet. +*/ + +void +sys_untimeout(sys_timeout_handler h, void *arg) +{ + struct sys_timeouts *timeouts; + struct sys_timeo *prev_t, *t; + + timeouts = sys_arch_timeouts(); + + if (timeouts->next == NULL) + return; + + for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next) + { + if ((t->h == h) && (t->arg == arg)) + { + /* We have a match */ + /* Unlink from previous in list */ + if (prev_t == NULL) + timeouts->next = t->next; + else + prev_t->next = t->next; + /* If not the last one, add time of this one back to next */ + if (t->next != NULL) + t->next->time += t->time; + memp_free(MEMP_SYS_TIMEOUT, t); + return; + } + } + return; +} + + + + + +static void +sswt_handler(void *arg) +{ + struct sswt_cb *sswt_cb = (struct sswt_cb *) arg; + + /* Timeout. Set flag to TRUE and signal semaphore */ + sswt_cb->timeflag = 1; + sys_sem_signal(*(sswt_cb->psem)); +} + +/* Wait for a semaphore with timeout (specified in ms) */ +/* timeout = 0: wait forever */ +/* Returns 0 on timeout. 1 otherwise */ + +int +sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout) +{ + struct sswt_cb sswt_cb; + + sswt_cb.psem = &sem; + sswt_cb.timeflag = 0; + + /* If timeout is zero, then just wait forever */ + if (timeout > 0) + /* Create a timer and pass it the address of our flag */ + sys_timeout(timeout, sswt_handler, &sswt_cb); + sys_sem_wait(sem); + /* Was it a timeout? */ + if (sswt_cb.timeflag) + { + /* timeout */ + return 0; + } else { + /* Not a timeout. Remove timeout entry */ + sys_untimeout(sswt_handler, &sswt_cb); + return 1; + } + +} + + +void +sys_msleep(u32_t ms) +{ + sys_sem_t delaysem = sys_sem_new(0); + + sys_sem_wait_timeout(delaysem, ms); + + sys_sem_free(delaysem); +} + + +#endif /* NO_SYS */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/tcp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/tcp.c new file mode 100644 index 0000000..5b69ee7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/tcp.c @@ -0,0 +1,1182 @@ +/** + * @file + * + * Transmission Control Protocol for IP + * + * This file contains common functions for the TCP implementation, such as functinos + * for manipulating the data structures and the TCP timer functions. TCP functions + * related to input and output is found in tcp_in.c and tcp_out.c respectively. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/snmp.h" + +#include "lwip/tcp.h" +#if LWIP_TCP + +/* Incremented every coarse grained timer shot (typically every 500 ms). */ +u32_t tcp_ticks; +const u8_t tcp_backoff[13] = + { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7}; + +/* The TCP PCB lists. */ + +/** List of all TCP PCBs in LISTEN state */ +union tcp_listen_pcbs_t tcp_listen_pcbs; +/** List of all TCP PCBs that are in a state in which + * they accept or send data. */ +struct tcp_pcb *tcp_active_pcbs; +/** List of all TCP PCBs in TIME-WAIT state */ +struct tcp_pcb *tcp_tw_pcbs; + +struct tcp_pcb *tcp_tmp_pcb; + +static u8_t tcp_timer; +static u16_t tcp_new_port(void); + +/** + * Initializes the TCP layer. + */ +void +tcp_init(void) +{ + /* Clear globals. */ + tcp_listen_pcbs.listen_pcbs = NULL; + tcp_active_pcbs = NULL; + tcp_tw_pcbs = NULL; + tcp_tmp_pcb = NULL; + + /* initialize timer */ + tcp_ticks = 0; + tcp_timer = 0; + +} + +/** + * Called periodically to dispatch TCP timers. + * + */ +void +tcp_tmr(void) +{ + /* Call tcp_fasttmr() every 250 ms */ + tcp_fasttmr(); + + if (++tcp_timer & 1) { + /* Call tcp_tmr() every 500 ms, i.e., every other timer + tcp_tmr() is called. */ + tcp_slowtmr(); + } +} + +/** + * Closes the connection held by the PCB. + * + */ +err_t +tcp_close(struct tcp_pcb *pcb) +{ + err_t err; + +#if TCP_DEBUG + LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ + + switch (pcb->state) { + case CLOSED: + /* Closing a pcb in the CLOSED state might seem erroneous, + * however, it is in this state once allocated and as yet unused + * and the user needs some way to free it should the need arise. + * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) + * or for a pcb that has been used and then entered the CLOSED state + * is erroneous, but this should never happen as the pcb has in those cases + * been freed, and so any remaining handles are bogus. */ + err = ERR_OK; + memp_free(MEMP_TCP_PCB, pcb); + pcb = NULL; + break; + case LISTEN: + err = ERR_OK; + tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb); + memp_free(MEMP_TCP_PCB_LISTEN, pcb); + pcb = NULL; + break; + case SYN_SENT: + err = ERR_OK; + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + pcb = NULL; + snmp_inc_tcpattemptfails(); + break; + case SYN_RCVD: + err = tcp_send_ctrl(pcb, TCP_FIN); + if (err == ERR_OK) { + snmp_inc_tcpattemptfails(); + pcb->state = FIN_WAIT_1; + } + break; + case ESTABLISHED: + err = tcp_send_ctrl(pcb, TCP_FIN); + if (err == ERR_OK) { + snmp_inc_tcpestabresets(); + pcb->state = FIN_WAIT_1; + } + break; + case CLOSE_WAIT: + err = tcp_send_ctrl(pcb, TCP_FIN); + if (err == ERR_OK) { + snmp_inc_tcpestabresets(); + pcb->state = LAST_ACK; + } + break; + default: + /* Has already been closed, do nothing. */ + err = ERR_OK; + pcb = NULL; + break; + } + + if (pcb != NULL && err == ERR_OK) { + err = tcp_output(pcb); + } + return err; +} + +/** + * Aborts a connection by sending a RST to the remote host and deletes + * the local protocol control block. This is done when a connection is + * killed because of shortage of memory. + * + */ +void +tcp_abort(struct tcp_pcb *pcb) +{ + u32_t seqno, ackno; + u16_t remote_port, local_port; + struct ip_addr remote_ip, local_ip; +#if LWIP_CALLBACK_API + void (* errf)(void *arg, err_t err); +#endif /* LWIP_CALLBACK_API */ + void *errf_arg; + + + /* Figure out on which TCP PCB list we are, and remove us. If we + are in an active state, call the receive function associated with + the PCB with a NULL argument, and send an RST to the remote end. */ + if (pcb->state == TIME_WAIT) { + tcp_pcb_remove(&tcp_tw_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else { + seqno = pcb->snd_nxt; + ackno = pcb->rcv_nxt; + ip_addr_set(&local_ip, &(pcb->local_ip)); + ip_addr_set(&remote_ip, &(pcb->remote_ip)); + local_port = pcb->local_port; + remote_port = pcb->remote_port; +#if LWIP_CALLBACK_API + errf = pcb->errf; +#endif /* LWIP_CALLBACK_API */ + errf_arg = pcb->callback_arg; + tcp_pcb_remove(&tcp_active_pcbs, pcb); + if (pcb->unacked != NULL) { + tcp_segs_free(pcb->unacked); + } + if (pcb->unsent != NULL) { + tcp_segs_free(pcb->unsent); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + tcp_segs_free(pcb->ooseq); + } +#endif /* TCP_QUEUE_OOSEQ */ + memp_free(MEMP_TCP_PCB, pcb); + TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT); + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n")); + tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port); + } +} + +/** + * Binds the connection to a local portnumber and IP address. If the + * IP address is not given (i.e., ipaddr == NULL), the IP address of + * the outgoing network interface is used instead. + * + */ + +err_t +tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) +{ + struct tcp_pcb *cpcb; + + if (port == 0) { + port = tcp_new_port(); + } + /* Check if the address already is in use. */ + for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; + cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { + if (ip_addr_isany(&(cpcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { + return ERR_USE; + } + } + } + for(cpcb = tcp_active_pcbs; + cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { + if (ip_addr_isany(&(cpcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { + return ERR_USE; + } + } + } + + if (!ip_addr_isany(ipaddr)) { + pcb->local_ip = *ipaddr; + } + pcb->local_port = port; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); + return ERR_OK; +} +#if LWIP_CALLBACK_API +static err_t +tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err) +{ + (void)arg; + (void)pcb; + (void)err; + + return ERR_ABRT; +} +#endif /* LWIP_CALLBACK_API */ + +/** + * Set the state of the connection to be LISTEN, which means that it + * is able to accept incoming connections. The protocol control block + * is reallocated in order to consume less memory. Setting the + * connection to LISTEN is an irreversible process. + * + */ +struct tcp_pcb * +tcp_listen(struct tcp_pcb *pcb) +{ + struct tcp_pcb_listen *lpcb; + + /* already listening? */ + if (pcb->state == LISTEN) { + return pcb; + } + lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN); + if (lpcb == NULL) { + return NULL; + } + lpcb->callback_arg = pcb->callback_arg; + lpcb->local_port = pcb->local_port; + lpcb->state = LISTEN; + lpcb->so_options = pcb->so_options; + lpcb->so_options |= SOF_ACCEPTCONN; + lpcb->ttl = pcb->ttl; + lpcb->tos = pcb->tos; + ip_addr_set(&lpcb->local_ip, &pcb->local_ip); + memp_free(MEMP_TCP_PCB, pcb); +#if LWIP_CALLBACK_API + lpcb->accept = tcp_accept_null; +#endif /* LWIP_CALLBACK_API */ + TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb); + return (struct tcp_pcb *)lpcb; +} + +/** + * This function should be called by the application when it has + * processed the data. The purpose is to advertise a larger window + * when the data has been processed. + * + */ +void +tcp_recved(struct tcp_pcb *pcb, u16_t len) +{ + if ((u32_t)pcb->rcv_wnd + len > TCP_WND) { + pcb->rcv_wnd = TCP_WND; + } else { + pcb->rcv_wnd += len; + } + if (!(pcb->flags & TF_ACK_DELAY) && + !(pcb->flags & TF_ACK_NOW)) { + /* + * We send an ACK here (if one is not already pending, hence + * the above tests) as tcp_recved() implies that the application + * has processed some data, and so we can open the receiver's + * window to allow more to be transmitted. This could result in + * two ACKs being sent for each received packet in some limited cases + * (where the application is only receiving data, and is slow to + * process it) but it is necessary to guarantee that the sender can + * continue to transmit. + */ + tcp_ack(pcb); + } + else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) { + /* If we can send a window update such that there is a full + * segment available in the window, do so now. This is sort of + * nagle-like in its goals, and tries to hit a compromise between + * sending acks each time the window is updated, and only sending + * window updates when a timer expires. The "threshold" used + * above (currently TCP_WND/2) can be tuned to be more or less + * aggressive */ + tcp_ack_now(pcb); + } + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n", + len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd)); +} + +/** + * A nastly hack featuring 'goto' statements that allocates a + * new TCP local port. + */ +static u16_t +tcp_new_port(void) +{ + struct tcp_pcb *pcb; +#ifndef TCP_LOCAL_PORT_RANGE_START +#define TCP_LOCAL_PORT_RANGE_START 4096 +#define TCP_LOCAL_PORT_RANGE_END 0x7fff +#endif + static u16_t port = TCP_LOCAL_PORT_RANGE_START; + + again: + if (++port > TCP_LOCAL_PORT_RANGE_END) { + port = TCP_LOCAL_PORT_RANGE_START; + } + + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + return port; +} + +/** + * Connects to another host. The function given as the "connected" + * argument will be called when the connection has been established. + * + */ +err_t +tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port, + err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err)) +{ + u32_t optdata; + err_t ret; + u32_t iss; + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); + if (ipaddr != NULL) { + pcb->remote_ip = *ipaddr; + } else { + return ERR_VAL; + } + pcb->remote_port = port; + if (pcb->local_port == 0) { + pcb->local_port = tcp_new_port(); + } + iss = tcp_next_iss(); + pcb->rcv_nxt = 0; + pcb->snd_nxt = iss; + pcb->lastack = iss - 1; + pcb->snd_lbb = iss - 1; + pcb->rcv_wnd = TCP_WND; + pcb->snd_wnd = TCP_WND; + pcb->mss = TCP_MSS; + pcb->cwnd = 1; + pcb->ssthresh = pcb->mss * 10; + pcb->state = SYN_SENT; +#if LWIP_CALLBACK_API + pcb->connected = connected; +#endif /* LWIP_CALLBACK_API */ + TCP_REG(&tcp_active_pcbs, pcb); + + snmp_inc_tcpactiveopens(); + + /* Build an MSS option */ + optdata = htonl(((u32_t)2 << 24) | + ((u32_t)4 << 16) | + (((u32_t)pcb->mss / 256) << 8) | + (pcb->mss & 255)); + + ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4); + if (ret == ERR_OK) { + tcp_output(pcb); + } + return ret; +} + +/** + * Called every 500 ms and implements the retransmission timer and the timer that + * removes PCBs that have been in TIME-WAIT for enough time. It also increments + * various timers such as the inactivity timer in each PCB. + */ +void +tcp_slowtmr(void) +{ + struct tcp_pcb *pcb, *pcb2, *prev; + u32_t eff_wnd; + u8_t pcb_remove; /* flag if a PCB should be removed */ + err_t err; + + err = ERR_OK; + + ++tcp_ticks; + + /* Steps through all of the active PCBs. */ + prev = NULL; + pcb = tcp_active_pcbs; + if (pcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); + } + while (pcb != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); + + pcb_remove = 0; + + if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); + } + else if (pcb->nrtx == TCP_MAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); + } else { + ++pcb->rtime; + if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) { + + /* Time for a retransmission. */ + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"U16_F" pcb->rto %"U16_F"\n", + pcb->rtime, pcb->rto)); + + /* Double retransmission time-out unless we are trying to + * connect to somebody (i.e., we are in SYN_SENT). */ + if (pcb->state != SYN_SENT) { + pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx]; + } + /* Reduce congestion window and ssthresh. */ + eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); + pcb->ssthresh = eff_wnd >> 1; + if (pcb->ssthresh < pcb->mss) { + pcb->ssthresh = pcb->mss * 2; + } + pcb->cwnd = pcb->mss; + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F" ssthresh %"U16_F"\n", + pcb->cwnd, pcb->ssthresh)); + + /* The following needs to be called AFTER cwnd is set to one mss - STJ */ + tcp_rexmit_rto(pcb); + } + } + /* Check if this PCB has stayed too long in FIN-WAIT-2 */ + if (pcb->state == FIN_WAIT_2) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n")); + } + } + + /* Check if KEEPALIVE should be sent */ + if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { + if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n", + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); + + tcp_abort(pcb); + } + else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) { + tcp_keepalive(pcb); + pcb->keep_cnt++; + } + } + + /* If this PCB has queued out of sequence data, but has been + inactive for too long, will drop the data (it will eventually + be retransmitted). */ +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL && + (u32_t)tcp_ticks - pcb->tmr >= + pcb->rto * TCP_OOSEQ_TIMEOUT) { + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Check if this PCB has stayed too long in SYN-RCVD */ + if (pcb->state == SYN_RCVD) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); + } + } + + /* Check if this PCB has stayed too long in LAST-ACK */ + if (pcb->state == LAST_ACK) { + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); + } + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_active_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); + tcp_active_pcbs = pcb->next; + } + + TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT); + + pcb2 = pcb->next; + memp_free(MEMP_TCP_PCB, pcb); + pcb = pcb2; + } else { + + /* We check if we should poll the connection. */ + ++pcb->polltmr; + if (pcb->polltmr >= pcb->pollinterval) { + pcb->polltmr = 0; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); + TCP_EVENT_POLL(pcb, err); + if (err == ERR_OK) { + tcp_output(pcb); + } + } + + prev = pcb; + pcb = pcb->next; + } + } + + + /* Steps through all of the TIME-WAIT PCBs. */ + prev = NULL; + pcb = tcp_tw_pcbs; + while (pcb != NULL) { + LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + pcb_remove = 0; + + /* Check if this PCB has stayed long enough in TIME-WAIT */ + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + } + + + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_tw_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); + tcp_tw_pcbs = pcb->next; + } + pcb2 = pcb->next; + memp_free(MEMP_TCP_PCB, pcb); + pcb = pcb2; + } else { + prev = pcb; + pcb = pcb->next; + } + } +} + +/** + * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs. + */ +void +tcp_fasttmr(void) +{ + struct tcp_pcb *pcb; + + /* send delayed ACKs */ + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->flags & TF_ACK_DELAY) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); + tcp_ack_now(pcb); + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + } + } +} + +/** + * Deallocates a list of TCP segments (tcp_seg structures). + * + */ +u8_t +tcp_segs_free(struct tcp_seg *seg) +{ + u8_t count = 0; + struct tcp_seg *next; + while (seg != NULL) { + next = seg->next; + count += tcp_seg_free(seg); + seg = next; + } + return count; +} + +/** + * Frees a TCP segment. + * + */ +u8_t +tcp_seg_free(struct tcp_seg *seg) +{ + u8_t count = 0; + + if (seg != NULL) { + if (seg->p != NULL) { + count = pbuf_free(seg->p); +#if TCP_DEBUG + seg->p = NULL; +#endif /* TCP_DEBUG */ + } + memp_free(MEMP_TCP_SEG, seg); + } + return count; +} + +/** + * Sets the priority of a connection. + * + */ +void +tcp_setprio(struct tcp_pcb *pcb, u8_t prio) +{ + pcb->prio = prio; +} +#if TCP_QUEUE_OOSEQ + +/** + * Returns a copy of the given TCP segment. + * + */ +struct tcp_seg * +tcp_seg_copy(struct tcp_seg *seg) +{ + struct tcp_seg *cseg; + + cseg = memp_malloc(MEMP_TCP_SEG); + if (cseg == NULL) { + return NULL; + } + memcpy((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); + pbuf_ref(cseg->p); + return cseg; +} +#endif + +#if LWIP_CALLBACK_API +static err_t +tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + arg = arg; + if (p != NULL) { + pbuf_free(p); + } else if (err == ERR_OK) { + return tcp_close(pcb); + } + return ERR_OK; +} +#endif /* LWIP_CALLBACK_API */ + +static void +tcp_kill_prio(u8_t prio) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + u8_t mprio; + + + mprio = TCP_PRIO_MAX; + + /* We kill the oldest active connection that has lower priority than + prio. */ + inactivity = 0; + inactive = NULL; + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->prio <= prio && + pcb->prio <= mprio && + (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + mprio = pcb->prio; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + + +static void +tcp_kill_timewait(void) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + inactivity = 0; + inactive = NULL; + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + + + +struct tcp_pcb * +tcp_alloc(u8_t prio) +{ + struct tcp_pcb *pcb; + u32_t iss; + + pcb = memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try killing oldest connection in TIME-WAIT. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); + tcp_kill_timewait(); + pcb = memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + tcp_kill_prio(prio); + pcb = memp_malloc(MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + memset(pcb, 0, sizeof(struct tcp_pcb)); + pcb->prio = TCP_PRIO_NORMAL; + pcb->snd_buf = TCP_SND_BUF; + pcb->snd_queuelen = 0; + pcb->rcv_wnd = TCP_WND; + pcb->tos = 0; + pcb->ttl = TCP_TTL; + pcb->mss = TCP_MSS; + pcb->rto = 3000 / TCP_SLOW_INTERVAL; + pcb->sa = 0; + pcb->sv = 3000 / TCP_SLOW_INTERVAL; + pcb->rtime = 0; + pcb->cwnd = 1; + iss = tcp_next_iss(); + pcb->snd_wl2 = iss; + pcb->snd_nxt = iss; + pcb->snd_max = iss; + pcb->lastack = iss; + pcb->snd_lbb = iss; + pcb->tmr = tcp_ticks; + + pcb->polltmr = 0; + +#if LWIP_CALLBACK_API + pcb->recv = tcp_recv_null; +#endif /* LWIP_CALLBACK_API */ + + /* Init KEEPALIVE timer */ + pcb->keepalive = TCP_KEEPDEFAULT; + pcb->keep_cnt = 0; + } + return pcb; +} + +/** + * Creates a new TCP protocol control block but doesn't place it on + * any of the TCP PCB lists. + * + * @internal: Maybe there should be a idle TCP PCB list where these + * PCBs are put on. We can then implement port reservation using + * tcp_bind(). Currently, we lack this (BSD socket type of) feature. + */ + +struct tcp_pcb * +tcp_new(void) +{ + return tcp_alloc(TCP_PRIO_NORMAL); +} + +/* + * tcp_arg(): + * + * Used to specify the argument that should be passed callback + * functions. + * + */ + +void +tcp_arg(struct tcp_pcb *pcb, void *arg) +{ + pcb->callback_arg = arg; +} +#if LWIP_CALLBACK_API + +/** + * Used to specify the function that should be called when a TCP + * connection receives data. + * + */ +void +tcp_recv(struct tcp_pcb *pcb, + err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err)) +{ + pcb->recv = recv; +} + +/** + * Used to specify the function that should be called when TCP data + * has been successfully delivered to the remote host. + * + */ + +void +tcp_sent(struct tcp_pcb *pcb, + err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len)) +{ + pcb->sent = sent; +} + +/** + * Used to specify the function that should be called when a fatal error + * has occured on the connection. + * + */ +void +tcp_err(struct tcp_pcb *pcb, + void (* errf)(void *arg, err_t err)) +{ + pcb->errf = errf; +} + +/** + * Used for specifying the function that should be called when a + * LISTENing connection has been connected to another host. + * + */ +void +tcp_accept(struct tcp_pcb *pcb, + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err)) +{ + ((struct tcp_pcb_listen *)pcb)->accept = accept; +} +#endif /* LWIP_CALLBACK_API */ + + +/** + * Used to specify the function that should be called periodically + * from TCP. The interval is specified in terms of the TCP coarse + * timer interval, which is called twice a second. + * + */ +void +tcp_poll(struct tcp_pcb *pcb, + err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval) +{ +#if LWIP_CALLBACK_API + pcb->poll = poll; +#endif /* LWIP_CALLBACK_API */ + pcb->pollinterval = interval; +} + +/** + * Purges a TCP PCB. Removes any buffered data and frees the buffer memory. + * + */ +void +tcp_pcb_purge(struct tcp_pcb *pcb) +{ + if (pcb->state != CLOSED && + pcb->state != TIME_WAIT && + pcb->state != LISTEN) { + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); + + if (pcb->unsent != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n")); + } + if (pcb->unacked != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); + } +#if TCP_QUEUE_OOSEQ /* LW */ + if (pcb->ooseq != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); + } + + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; +#endif /* TCP_QUEUE_OOSEQ */ + tcp_segs_free(pcb->unsent); + tcp_segs_free(pcb->unacked); + pcb->unacked = pcb->unsent = NULL; + } +} + +/** + * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first. + * + */ +void +tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) +{ + TCP_RMV(pcblist, pcb); + + tcp_pcb_purge(pcb); + + /* if there is an outstanding delayed ACKs, send it */ + if (pcb->state != TIME_WAIT && + pcb->state != LISTEN && + pcb->flags & TF_ACK_DELAY) { + pcb->flags |= TF_ACK_NOW; + tcp_output(pcb); + } + pcb->state = CLOSED; + + LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); +} + +/** + * Calculates a new initial sequence number for new connections. + * + */ +u32_t +tcp_next_iss(void) +{ + static u32_t iss = 6510; + + iss += tcp_ticks; /* XXX */ + return iss; +} + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +void +tcp_debug_print(struct tcp_hdr *tcphdr) +{ + LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + ntohs(tcphdr->src), ntohs(tcphdr->dest))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", + ntohl(tcphdr->seqno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", + ntohl(tcphdr->ackno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", + TCPH_HDRLEN(tcphdr), + TCPH_FLAGS(tcphdr) >> 5 & 1, + TCPH_FLAGS(tcphdr) >> 4 & 1, + TCPH_FLAGS(tcphdr) >> 3 & 1, + TCPH_FLAGS(tcphdr) >> 2 & 1, + TCPH_FLAGS(tcphdr) >> 1 & 1, + TCPH_FLAGS(tcphdr) & 1, + ntohs(tcphdr->wnd))); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", + ntohs(tcphdr->chksum), ntohs(tcphdr->urgp))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +} + +void +tcp_debug_print_state(enum tcp_state s) +{ + LWIP_DEBUGF(TCP_DEBUG, ("State: ")); + switch (s) { + case CLOSED: + LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n")); + break; + case LISTEN: + LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n")); + break; + case SYN_SENT: + LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n")); + break; + case SYN_RCVD: + LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n")); + break; + case ESTABLISHED: + LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n")); + break; + case FIN_WAIT_1: + LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n")); + break; + case FIN_WAIT_2: + LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n")); + break; + case CLOSE_WAIT: + LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n")); + break; + case CLOSING: + LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n")); + break; + case LAST_ACK: + LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n")); + break; + case TIME_WAIT: + LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n")); + break; + } +} + +void +tcp_debug_print_flags(u8_t flags) +{ + if (flags & TCP_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("FIN ")); + } + if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("SYN ")); + } + if (flags & TCP_RST) { + LWIP_DEBUGF(TCP_DEBUG, ("RST ")); + } + if (flags & TCP_PSH) { + LWIP_DEBUGF(TCP_DEBUG, ("PSH ")); + } + if (flags & TCP_ACK) { + LWIP_DEBUGF(TCP_DEBUG, ("ACK ")); + } + if (flags & TCP_URG) { + LWIP_DEBUGF(TCP_DEBUG, ("URG ")); + } + if (flags & TCP_ECE) { + LWIP_DEBUGF(TCP_DEBUG, ("ECE ")); + } + if (flags & TCP_CWR) { + LWIP_DEBUGF(TCP_DEBUG, ("CWR ")); + } +} + +void +tcp_debug_print_pcbs(void) +{ + struct tcp_pcb *pcb; + LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); + for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } +} + +s16_t +tcp_pcbs_sane(void) +{ + struct tcp_pcb *pcb; + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + } + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + } + return 1; +} +#endif /* TCP_DEBUG */ +#endif /* LWIP_TCP */ + + + + + + + + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/tcp_in.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/tcp_in.c new file mode 100644 index 0000000..f711266 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/tcp_in.c @@ -0,0 +1,1211 @@ +/** + * @file + * + * Transmission Control Protocol, incoming traffic + * + * The input processing functions of the TCP layer. + * + * These functions are generally called in the order (ip_input() ->) + * tcp_input() -> * tcp_process() -> tcp_receive() (-> application). + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/def.h" +#include "lwip/opt.h" + +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/mem.h" +#include "lwip/memp.h" + +#include "lwip/inet.h" +#include "lwip/tcp.h" + +#include "lwip/stats.h" +#include "arch/perf.h" +#include "lwip/snmp.h" + +#if LWIP_TCP +/* These variables are global to all functions involved in the input + processing of TCP segments. They are set by the tcp_input() + function. */ +static struct tcp_seg inseg; +static struct tcp_hdr *tcphdr; +static struct ip_hdr *iphdr; +static u32_t seqno, ackno; +static u8_t flags; +static u16_t tcplen; + +static u8_t recv_flags; +static struct pbuf *recv_data; + +struct tcp_pcb *tcp_input_pcb; + +/* Forward declarations. */ +static err_t tcp_process(struct tcp_pcb *pcb); +static u8_t tcp_receive(struct tcp_pcb *pcb); +static void tcp_parseopt(struct tcp_pcb *pcb); + +static err_t tcp_listen_input(struct tcp_pcb_listen *pcb); +static err_t tcp_timewait_input(struct tcp_pcb *pcb); + +/* tcp_input: + * + * The initial input processing of TCP. It verifies the TCP header, demultiplexes + * the segment between the PCBs and passes it on to tcp_process(), which implements + * the TCP finite state machine. This function is called by the IP layer (in + * ip_input()). + */ + +void +tcp_input(struct pbuf *p, struct netif *inp) +{ + struct tcp_pcb *pcb, *prev; + struct tcp_pcb_listen *lpcb; + u8_t hdrlen; + err_t err; + + PERF_START; + + TCP_STATS_INC(tcp.recv); + snmp_inc_tcpinsegs(); + + iphdr = p->payload; + tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4); + +#if TCP_INPUT_DEBUG + tcp_debug_print(tcphdr); +#endif + + /* remove header from payload */ + if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) { + /* drop short packets */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); + TCP_STATS_INC(tcp.lenerr); + TCP_STATS_INC(tcp.drop); + pbuf_free(p); + return; + } + + /* Don't even process incoming broadcasts/multicasts. */ + if (ip_addr_isbroadcast(&(iphdr->dest), inp) || + ip_addr_ismulticast(&(iphdr->dest))) { + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + +#if CHECKSUM_CHECK_TCP + /* Verify TCP checksum. */ + if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_TCP, p->tot_len) != 0) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", + inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest), + IP_PROTO_TCP, p->tot_len))); +#if TCP_DEBUG + tcp_debug_print(tcphdr); +#endif /* TCP_DEBUG */ + TCP_STATS_INC(tcp.chkerr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } +#endif + + /* Move the payload pointer in the pbuf so that it points to the + TCP data instead of the TCP header. */ + hdrlen = TCPH_HDRLEN(tcphdr); + pbuf_header(p, -(hdrlen * 4)); + + /* Convert fields in TCP header to host byte order. */ + tcphdr->src = ntohs(tcphdr->src); + tcphdr->dest = ntohs(tcphdr->dest); + seqno = tcphdr->seqno = ntohl(tcphdr->seqno); + ackno = tcphdr->ackno = ntohl(tcphdr->ackno); + tcphdr->wnd = ntohs(tcphdr->wnd); + + flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS; + tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0); + + /* Demultiplex an incoming segment. First, we check if it is destined + for an active connection. */ + prev = NULL; + + + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { + + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); + if (prev != NULL) { + prev->next = pcb->next; + pcb->next = tcp_active_pcbs; + tcp_active_pcbs = pcb; + } + LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); + break; + } + prev = pcb; + } + + if (pcb == NULL) { + /* If it did not go to an active connection, we check the connections + in the TIME-WAIT state. */ + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { + /* We don't really care enough to move this PCB to the front + of the list since we are not very likely to receive that + many segments for connections in TIME-WAIT. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n")); + tcp_timewait_input(pcb); + pbuf_free(p); + return; + } + } + + /* Finally, if we still did not get a match, we check all PCBs that + are LISTENing for incoming connections. */ + prev = NULL; + for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + if ((ip_addr_isany(&(lpcb->local_ip)) || + ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) && + lpcb->local_port == tcphdr->dest) { + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + if (prev != NULL) { + ((struct tcp_pcb_listen *)prev)->next = lpcb->next; + /* our successor is the remainder of the listening list */ + lpcb->next = tcp_listen_pcbs.listen_pcbs; + /* put this listening pcb at the head of the listening list */ + tcp_listen_pcbs.listen_pcbs = lpcb; + } + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n")); + tcp_listen_input(lpcb); + pbuf_free(p); + return; + } + prev = (struct tcp_pcb *)lpcb; + } + } + +#if TCP_INPUT_DEBUG + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags ")); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n")); +#endif /* TCP_INPUT_DEBUG */ + + + if (pcb != NULL) { + /* The incoming segment belongs to a connection. */ +#if TCP_INPUT_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ +#endif /* TCP_INPUT_DEBUG */ + + /* Set up a tcp_seg structure. */ + inseg.next = NULL; + inseg.len = p->tot_len; + inseg.dataptr = p->payload; + inseg.p = p; + inseg.tcphdr = tcphdr; + + recv_data = NULL; + recv_flags = 0; + + tcp_input_pcb = pcb; + err = tcp_process(pcb); + tcp_input_pcb = NULL; + /* A return value of ERR_ABRT means that tcp_abort() was called + and that the pcb has been freed. If so, we don't do anything. */ + if (err != ERR_ABRT) { + if (recv_flags & TF_RESET) { + /* TF_RESET means that the connection was reset by the other + end. We then call the error callback to inform the + application that the connection is dead before we + deallocate the PCB. */ + TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST); + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else if (recv_flags & TF_CLOSED) { + /* The connection has been closed and we will deallocate the + PCB. */ + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else { + err = ERR_OK; + /* If the application has registered a "sent" function to be + called when new send buffer space is available, we call it + now. */ + if (pcb->acked > 0) { + TCP_EVENT_SENT(pcb, pcb->acked, err); + } + + if (recv_data != NULL) { + /* Notify application that data has been received. */ + TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); + } + + /* If a FIN segment was received, we call the callback + function with a NULL buffer to indicate EOF. */ + if (recv_flags & TF_GOT_FIN) { + TCP_EVENT_RECV(pcb, NULL, ERR_OK, err); + } + /* If there were no errors, we try to send something out. */ + if (err == ERR_OK) { + tcp_output(pcb); + } + } + } + + + /* give up our reference to inseg.p */ + if (inseg.p != NULL) + { + pbuf_free(inseg.p); + inseg.p = NULL; + } +#if TCP_INPUT_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ +#endif /* TCP_INPUT_DEBUG */ + + } else { + + /* If no matching PCB was found, send a TCP RST (reset) to the + sender. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); + if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { + TCP_STATS_INC(tcp.proterr); + TCP_STATS_INC(tcp.drop); + tcp_rst(ackno, seqno + tcplen, + &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } + pbuf_free(p); + } + + LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); + PERF_STOP("tcp_input"); +} + +/* tcp_listen_input(): + * + * Called by tcp_input() when a segment arrives for a listening + * connection. + */ + +static err_t +tcp_listen_input(struct tcp_pcb_listen *pcb) +{ + struct tcp_pcb *npcb; + u32_t optdata; + + /* In the LISTEN state, we check for incoming SYN segments, + creates a new PCB, and responds with a SYN|ACK. */ + if (flags & TCP_ACK) { + /* For incoming segments with the ACK flag set, respond with a + RST. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); + tcp_rst(ackno + 1, seqno + tcplen, + &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } else if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); + npcb = tcp_alloc(pcb->prio); + /* If a new PCB could not be created (probably due to lack of memory), + we don't do anything, but rely on the sender will retransmit the + SYN at a time when we have more memory available. */ + if (npcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n")); + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } + /* Set up the new PCB. */ + ip_addr_set(&(npcb->local_ip), &(iphdr->dest)); + npcb->local_port = pcb->local_port; + ip_addr_set(&(npcb->remote_ip), &(iphdr->src)); + npcb->remote_port = tcphdr->src; + npcb->state = SYN_RCVD; + npcb->rcv_nxt = seqno + 1; + npcb->snd_wnd = tcphdr->wnd; + npcb->ssthresh = npcb->snd_wnd; + npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ + npcb->callback_arg = pcb->callback_arg; +#if LWIP_CALLBACK_API + npcb->accept = pcb->accept; +#endif /* LWIP_CALLBACK_API */ + /* inherit socket options */ + npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER); + /* Register the new PCB so that we can begin receiving segments + for it. */ + TCP_REG(&tcp_active_pcbs, npcb); + + /* Parse any options in the SYN. */ + tcp_parseopt(npcb); + + snmp_inc_tcppassiveopens(); + + /* Build an MSS option. */ + optdata = htonl(((u32_t)2 << 24) | + ((u32_t)4 << 16) | + (((u32_t)npcb->mss / 256) << 8) | + (npcb->mss & 255)); + /* Send a SYN|ACK together with the MSS option. */ + tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4); + return tcp_output(npcb); + } + return ERR_OK; +} + +/* tcp_timewait_input(): + * + * Called by tcp_input() when a segment arrives for a connection in + * TIME_WAIT. + */ + +static err_t +tcp_timewait_input(struct tcp_pcb *pcb) +{ + if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) { + pcb->rcv_nxt = seqno + tcplen; + } + if (tcplen > 0) { + tcp_ack_now(pcb); + } + return tcp_output(pcb); +} + +/* tcp_process + * + * Implements the TCP state machine. Called by tcp_input. In some + * states tcp_receive() is called to receive data. The tcp_seg + * argument will be freed by the caller (tcp_input()) unless the + * recv_data pointer in the pcb is set. + */ + +static err_t +tcp_process(struct tcp_pcb *pcb) +{ + struct tcp_seg *rseg; + u8_t acceptable = 0; + err_t err; + u8_t accepted_inseq; + + err = ERR_OK; + + /* Process incoming RST segments. */ + if (flags & TCP_RST) { + /* First, determine if the reset is acceptable. */ + if (pcb->state == SYN_SENT) { + if (ackno == pcb->snd_nxt) { + acceptable = 1; + } + } else { + /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && + TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) { + */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) { + acceptable = 1; + } + } + + if (acceptable) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); + LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); + recv_flags = TF_RESET; + pcb->flags &= ~TF_ACK_DELAY; + return ERR_RST; + } else { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + return ERR_OK; + } + } + + /* Update the PCB (in)activity timer. */ + pcb->tmr = tcp_ticks; + pcb->keep_cnt = 0; + + /* Do different things depending on the TCP state. */ + switch (pcb->state) { + case SYN_SENT: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, + pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno))); + /* received SYN ACK with expected sequence number? */ + if ((flags & TCP_ACK) && (flags & TCP_SYN) + && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) { + pcb->snd_buf++; + pcb->rcv_nxt = seqno + 1; + pcb->lastack = ackno; + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ + pcb->state = ESTABLISHED; + pcb->cwnd = ((pcb->cwnd == 1) ? (pcb->mss * 2) : pcb->mss); + --pcb->snd_queuelen; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + rseg = pcb->unacked; + pcb->unacked = rseg->next; + tcp_seg_free(rseg); + + /* Parse any options in the SYNACK. */ + tcp_parseopt(pcb); + + /* Call the user specified function to call when sucessfully + * connected. */ + TCP_EVENT_CONNECTED(pcb, ERR_OK, err); + tcp_ack(pcb); + } + /* received ACK? possibly a half-open connection */ + else if (flags & TCP_ACK) { + /* send a RST to bring the other side in a non-synchronized state. */ + tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } + break; + case SYN_RCVD: + if (flags & TCP_ACK && + !(flags & TCP_RST)) { + /* expected ACK number? */ + if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { + u16_t old_cwnd; + pcb->state = ESTABLISHED; + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); +#if LWIP_CALLBACK_API + LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL); +#endif + /* Call the accept function. */ + TCP_EVENT_ACCEPT(pcb, ERR_OK, err); + if (err != ERR_OK) { + /* If the accept function returns with an error, we abort + * the connection. */ + tcp_abort(pcb); + return ERR_ABRT; + } + old_cwnd = pcb->cwnd; + /* If there was any data contained within this ACK, + * we'd better pass it on to the application as well. */ + tcp_receive(pcb); + pcb->cwnd = ((old_cwnd == 1) ? (pcb->mss * 2) : pcb->mss); + } + /* incorrect ACK number */ + else { + /* send RST */ + tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } + } + break; + case CLOSE_WAIT: + /* FALLTHROUGH */ + case ESTABLISHED: + accepted_inseq = tcp_receive(pcb); + if ((flags & TCP_FIN) && accepted_inseq) { /* passive close */ + tcp_ack_now(pcb); + pcb->state = CLOSE_WAIT; + } + break; + case FIN_WAIT_1: + tcp_receive(pcb); + if (flags & TCP_FIN) { + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, + ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } else { + tcp_ack_now(pcb); + pcb->state = CLOSING; + } + } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + pcb->state = FIN_WAIT_2; + } + break; + case FIN_WAIT_2: + tcp_receive(pcb); + if (flags & TCP_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case CLOSING: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case LAST_ACK: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + pcb->state = CLOSED; + recv_flags = TF_CLOSED; + } + break; + default: + break; + } + return ERR_OK; +} + +/* tcp_receive: + * + * Called by tcp_process. Checks if the given segment is an ACK for outstanding + * data, and if so frees the memory of the buffered data. Next, is places the + * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment + * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until + * i it has been removed from the buffer. + * + * If the incoming segment constitutes an ACK for a segment that was used for RTT + * estimation, the RTT is estimated here as well. + * + * @return 1 if + */ + +static u8_t +tcp_receive(struct tcp_pcb *pcb) +{ + struct tcp_seg *next; +#if TCP_QUEUE_OOSEQ + struct tcp_seg *prev, *cseg; +#endif + struct pbuf *p; + s32_t off; + s16_t m; + u32_t right_wnd_edge; + u16_t new_tot_len; + u8_t accepted_inseq = 0; + + if (flags & TCP_ACK) { + right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1; + + /* Update window. */ + if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) { + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wl1 = seqno; + pcb->snd_wl2 = ackno; + LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U32_F"\n", pcb->snd_wnd)); +#if TCP_WND_DEBUG + } else { + if (pcb->snd_wnd != tcphdr->wnd) { + LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %"U32_F" snd_max %"U32_F" ackno %"U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", + pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); + } +#endif /* TCP_WND_DEBUG */ + } + + if (pcb->lastack == ackno) { + pcb->acked = 0; + + if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){ + ++pcb->dupacks; + if (pcb->dupacks >= 3 && pcb->unacked != NULL) { + if (!(pcb->flags & TF_INFR)) { + /* This is fast retransmit. Retransmit the first unacked segment. */ + LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F"), fast retransmit %"U32_F"\n", + (u16_t)pcb->dupacks, pcb->lastack, + ntohl(pcb->unacked->tcphdr->seqno))); + tcp_rexmit(pcb); + /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */ + /*pcb->ssthresh = LWIP_MAX((pcb->snd_max - + pcb->lastack) / 2, + 2 * pcb->mss);*/ + /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */ + if (pcb->cwnd > pcb->snd_wnd) + pcb->ssthresh = pcb->snd_wnd / 2; + else + pcb->ssthresh = pcb->cwnd / 2; + + pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; + pcb->flags |= TF_INFR; + } else { + /* Inflate the congestion window, but not if it means that + the value overflows. */ + if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { + pcb->cwnd += pcb->mss; + } + } + } + } else { + LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %"U32_F" %"U32_F"\n", + pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge)); + } + } else + /*if (TCP_SEQ_LT(pcb->lastack, ackno) && + TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */ + if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){ + /* We come here when the ACK acknowledges new data. */ + + /* Reset the "IN Fast Retransmit" flag, since we are no longer + in fast retransmit. Also reset the congestion window to the + slow start threshold. */ + if (pcb->flags & TF_INFR) { + pcb->flags &= ~TF_INFR; + pcb->cwnd = pcb->ssthresh; + } + + /* Reset the number of retransmissions. */ + pcb->nrtx = 0; + + /* Reset the retransmission time-out. */ + pcb->rto = (pcb->sa >> 3) + pcb->sv; + + /* Update the send buffer space. */ + pcb->acked = ackno - pcb->lastack; + + pcb->snd_buf += pcb->acked; + + /* Reset the fast retransmit variables. */ + pcb->dupacks = 0; + pcb->lastack = ackno; + + /* Update the congestion control variables (cwnd and + ssthresh). */ + if (pcb->state >= ESTABLISHED) { + if (pcb->cwnd < pcb->ssthresh) { + if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { + pcb->cwnd += pcb->mss; + } + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd)); + } else { + u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); + if (new_cwnd > pcb->cwnd) { + pcb->cwnd = new_cwnd; + } + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd)); + } + } + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", + ackno, + pcb->unacked != NULL? + ntohl(pcb->unacked->tcphdr->seqno): 0, + pcb->unacked != NULL? + ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); + + /* Remove segment from the unacknowledged list if the incoming + ACK acknowlegdes them. */ + while (pcb->unacked != NULL && + TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) + + TCP_TCPLEN(pcb->unacked), ackno)) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n", + ntohl(pcb->unacked->tcphdr->seqno), + ntohl(pcb->unacked->tcphdr->seqno) + + TCP_TCPLEN(pcb->unacked))); + + next = pcb->unacked; + pcb->unacked = pcb->unacked->next; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); + pcb->snd_queuelen -= pbuf_clen(next->p); + tcp_seg_free(next); + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); + } + } + pcb->polltmr = 0; + } + + /* We go through the ->unsent list to see if any of the segments + on the list are acknowledged by the ACK. This may seem + strange since an "unsent" segment shouldn't be acked. The + rationale is that lwIP puts all outstanding segments on the + ->unsent list after a retransmission, so these segments may + in fact have been sent once. */ + while (pcb->unsent != NULL && + /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) && + TCP_SEQ_LEQ(ackno, pcb->snd_max)*/ + TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max) + ) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n", + ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) + + TCP_TCPLEN(pcb->unsent))); + + next = pcb->unsent; + pcb->unsent = pcb->unsent->next; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); + pcb->snd_queuelen -= pbuf_clen(next->p); + tcp_seg_free(next); + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_receive: valid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + + if (pcb->unsent != NULL) { + pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno); + } + } + /* End of ACK for new data processing. */ + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", + pcb->rttest, pcb->rtseq, ackno)); + + /* RTT estimation calculations. This is done by checking if the + incoming segment acknowledges the segment we use to take a + round-trip time measurement. */ + if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { + m = tcp_ticks - pcb->rttest; + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", + m, m * TCP_SLOW_INTERVAL)); + + /* This is taken directly from VJs original code in his paper */ + m = m - (pcb->sa >> 3); + pcb->sa += m; + if (m < 0) { + m = -m; + } + m = m - (pcb->sv >> 2); + pcb->sv += m; + pcb->rto = (pcb->sa >> 3) + pcb->sv; + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" miliseconds)\n", + pcb->rto, pcb->rto * TCP_SLOW_INTERVAL)); + + pcb->rttest = 0; + } + } + + /* If the incoming segment contains data, we must process it + further. */ + if (tcplen > 0) { + /* This code basically does three things: + + +) If the incoming segment contains data that is the next + in-sequence data, this data is passed to the application. This + might involve trimming the first edge of the data. The rcv_nxt + variable and the advertised window are adjusted. + + +) If the incoming segment has data that is above the next + sequence number expected (->rcv_nxt), the segment is placed on + the ->ooseq queue. This is done by finding the appropriate + place in the ->ooseq queue (which is ordered by sequence + number) and trim the segment in both ends if needed. An + immediate ACK is sent to indicate that we received an + out-of-sequence segment. + + +) Finally, we check if the first segment on the ->ooseq queue + now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If + rcv_nxt > ooseq->seqno, we must trim the first edge of the + segment on ->ooseq before we adjust rcv_nxt. The data in the + segments that are now on sequence are chained onto the + incoming segment so that we only need to call the application + once. + */ + + /* First, we check if we must trim the first edge. We have to do + this if the sequence number of the incoming segment is less + than rcv_nxt, and the sequence number plus the length of the + segment is larger than rcv_nxt. */ + /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ + if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ + if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)){ + /* Trimming the first edge is done by pushing the payload + pointer in the pbuf downwards. This is somewhat tricky since + we do not want to discard the full contents of the pbuf up to + the new starting point of the data since we have to keep the + TCP header which is present in the first pbuf in the chain. + + What is done is really quite a nasty hack: the first pbuf in + the pbuf chain is pointed to by inseg.p. Since we need to be + able to deallocate the whole pbuf, we cannot change this + inseg.p pointer to point to any of the later pbufs in the + chain. Instead, we point the ->payload pointer in the first + pbuf to data in one of the later pbufs. We also set the + inseg.data pointer to point to the right place. This way, the + ->p pointer will still point to the first pbuf, but the + ->p->payload pointer will point to data in another pbuf. + + After we are done with adjusting the pbuf pointers we must + adjust the ->data pointer in the seg and the segment + length.*/ + + off = pcb->rcv_nxt - seqno; + p = inseg.p; + LWIP_ASSERT("inseg.p != NULL", inseg.p); + if (inseg.p->len < off) { + new_tot_len = inseg.p->tot_len - off; + while (p->len < off) { + off -= p->len; + /* KJM following line changed (with addition of new_tot_len var) + to fix bug #9076 + inseg.p->tot_len -= p->len; */ + p->tot_len = new_tot_len; + p->len = 0; + p = p->next; + } + pbuf_header(p, -off); + } else { + pbuf_header(inseg.p, -off); + } + /* KJM following line changed to use p->payload rather than inseg->p->payload + to fix bug #9076 */ + inseg.dataptr = p->payload; + inseg.len -= pcb->rcv_nxt - seqno; + inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; + } + else { + if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ + /* the whole segment is < rcv_nxt */ + /* must be a duplicate of a packet that has already been correctly handled */ + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); + tcp_ack_now(pcb); + } + } + + /* The sequence number must be within the window (above rcv_nxt + and below rcv_nxt + rcv_wnd) in order to be further + processed. */ + /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && + TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){ + if (pcb->rcv_nxt == seqno) { + accepted_inseq = 1; + /* The incoming segment is the next in sequence. We check if + we have to trim the end of the segment and update rcv_nxt + and pass the data to the application. */ +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL && + TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) { + /* We have to trim the second edge of the incoming + segment. */ + inseg.len = pcb->ooseq->tcphdr->seqno - seqno; + pbuf_realloc(inseg.p, inseg.len); + } +#endif /* TCP_QUEUE_OOSEQ */ + + tcplen = TCP_TCPLEN(&inseg); + + /* First received FIN will be ACKed +1, on any successive (duplicate) + * FINs we are already in CLOSE_WAIT and have already done +1. + */ + if (pcb->state != CLOSE_WAIT) { + pcb->rcv_nxt += tcplen; + } + + /* Update the receiver's (our) window. */ + if (pcb->rcv_wnd < tcplen) { + pcb->rcv_wnd = 0; + } else { + pcb->rcv_wnd -= tcplen; + } + + /* If there is data in the segment, we make preparations to + pass this up to the application. The ->recv_data variable + is used for holding the pbuf that goes to the + application. The code for reassembling out-of-sequence data + chains its data on this pbuf as well. + + If the segment was a FIN, we set the TF_GOT_FIN flag that will + be used to indicate to the application that the remote side has + closed its end of the connection. */ + if (inseg.p->tot_len > 0) { + recv_data = inseg.p; + /* Since this pbuf now is the responsibility of the + application, we delete our reference to it so that we won't + (mistakingly) deallocate it. */ + inseg.p = NULL; + } + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); + recv_flags = TF_GOT_FIN; + } + +#if TCP_QUEUE_OOSEQ + /* We now check if we have segments on the ->ooseq queue that + is now in sequence. */ + while (pcb->ooseq != NULL && + pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + + cseg = pcb->ooseq; + seqno = pcb->ooseq->tcphdr->seqno; + + pcb->rcv_nxt += TCP_TCPLEN(cseg); + if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) { + pcb->rcv_wnd = 0; + } else { + pcb->rcv_wnd -= TCP_TCPLEN(cseg); + } + if (cseg->p->tot_len > 0) { + /* Chain this pbuf onto the pbuf that we will pass to + the application. */ + if (recv_data) { + pbuf_cat(recv_data, cseg->p); + } else { + recv_data = cseg->p; + } + cseg->p = NULL; + } + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); + recv_flags = TF_GOT_FIN; + if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ + pcb->state = CLOSE_WAIT; + } + } + + + pcb->ooseq = cseg->next; + tcp_seg_free(cseg); + } +#endif /* TCP_QUEUE_OOSEQ */ + + + /* Acknowledge the segment(s). */ + tcp_ack(pcb); + + } else { + /* We get here if the incoming segment is out-of-sequence. */ + tcp_ack_now(pcb); +#if TCP_QUEUE_OOSEQ + /* We queue the segment on the ->ooseq queue. */ + if (pcb->ooseq == NULL) { + pcb->ooseq = tcp_seg_copy(&inseg); + } else { + /* If the queue is not empty, we walk through the queue and + try to find a place where the sequence number of the + incoming segment is between the sequence numbers of the + previous and the next segment on the ->ooseq queue. That is + the place where we put the incoming segment. If needed, we + trim the second edges of the previous and the incoming + segment so that it will fit into the sequence. + + If the incoming segment has the same sequence number as a + segment on the ->ooseq queue, we discard the segment that + contains less data. */ + + prev = NULL; + for(next = pcb->ooseq; next != NULL; next = next->next) { + if (seqno == next->tcphdr->seqno) { + /* The sequence number of the incoming segment is the + same as the sequence number of the segment on + ->ooseq. We check the lengths to see which one to + discard. */ + if (inseg.len > next->len) { + /* The incoming segment is larger than the old + segment. We replace the old segment with the new + one. */ + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + cseg->next = next->next; + if (prev != NULL) { + prev->next = cseg; + } else { + pcb->ooseq = cseg; + } + } + break; + } else { + /* Either the lenghts are the same or the incoming + segment was smaller than the old one; in either + case, we ditch the incoming segment. */ + break; + } + } else { + if (prev == NULL) { + if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { + /* The sequence number of the incoming segment is lower + than the sequence number of the first segment on the + queue. We put the incoming segment first on the + queue. */ + + if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { + /* We need to trim the incoming segment. */ + inseg.len = next->tcphdr->seqno - seqno; + pbuf_realloc(inseg.p, inseg.len); + } + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + cseg->next = next; + pcb->ooseq = cseg; + } + break; + } + } else + /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && + TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ + if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){ + /* The sequence number of the incoming segment is in + between the sequence numbers of the previous and + the next segment on ->ooseq. We trim and insert the + incoming segment and trim the previous segment, if + needed. */ + if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { + /* We need to trim the incoming segment. */ + inseg.len = next->tcphdr->seqno - seqno; + pbuf_realloc(inseg.p, inseg.len); + } + + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + cseg->next = next; + prev->next = cseg; + if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { + /* We need to trim the prev segment. */ + prev->len = seqno - prev->tcphdr->seqno; + pbuf_realloc(prev->p, prev->len); + } + } + break; + } + /* If the "next" segment is the last segment on the + ooseq queue, we add the incoming segment to the end + of the list. */ + if (next->next == NULL && + TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { + next->next = tcp_seg_copy(&inseg); + if (next->next != NULL) { + if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { + /* We need to trim the last segment. */ + next->len = seqno - next->tcphdr->seqno; + pbuf_realloc(next->p, next->len); + } + } + break; + } + } + prev = next; + } + } +#endif /* TCP_QUEUE_OOSEQ */ + + } + } else { + /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || + TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ + if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ + tcp_ack_now(pcb); + } + } + } else { + /* Segments with length 0 is taken care of here. Segments that + fall out of the window are ACKed. */ + /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || + TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ + if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ + tcp_ack_now(pcb); + } + } + return accepted_inseq; +} + +/* + * tcp_parseopt: + * + * Parses the options contained in the incoming segment. (Code taken + * from uIP with only small changes.) + * + */ + +static void +tcp_parseopt(struct tcp_pcb *pcb) +{ + u8_t c; + u8_t *opts, opt; + u16_t mss; + + opts = (u8_t *)tcphdr + TCP_HLEN; + + /* Parse the TCP MSS option, if present. */ + if(TCPH_HDRLEN(tcphdr) > 0x5) { + for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) { + opt = opts[c]; + if (opt == 0x00) { + /* End of options. */ + break; + } else if (opt == 0x01) { + ++c; + /* NOP option. */ + } else if (opt == 0x02 && + opts[c + 1] == 0x04) { + /* An MSS option with the right option length. */ + mss = (opts[c + 2] << 8) | opts[c + 3]; + pcb->mss = mss > TCP_MSS? TCP_MSS: mss; + + /* And we are done processing options. */ + break; + } else { + if (opts[c + 1] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + /* All other options have a length field, so that we easily + can skip past them. */ + c += opts[c + 1]; + } + } + } +} +#endif /* LWIP_TCP */ + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/tcp_out.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/tcp_out.c new file mode 100644 index 0000000..8802fea --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/tcp_out.c @@ -0,0 +1,727 @@ +/** + * @file + * + * Transmission Control Protocol, outgoing traffic + * + * The output functions of TCP. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/def.h" +#include "lwip/opt.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/sys.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/inet.h" +#include "lwip/tcp.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +#if LWIP_TCP + +/* Forward declarations.*/ +static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb); + +err_t +tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags) +{ + /* no data, no length, flags, copy=1, no optdata, no optdatalen */ + return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0); +} + +/** + * Write data for sending (but does not send it immediately). + * + * It waits in the expectation of more data being sent soon (as + * it can send them more efficiently by combining them together). + * To prompt the system to send data now, call tcp_output() after + * calling tcp_write(). + * + * @arg pcb Protocol control block of the TCP connection to enqueue data for. + * + * @see tcp_write() + */ + +err_t +tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy) +{ + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%"U16_F", copy=%"U16_F")\n", (void *)pcb, + arg, len, (u16_t)copy)); + /* connection is in valid state for data transmission? */ + if (pcb->state == ESTABLISHED || + pcb->state == CLOSE_WAIT || + pcb->state == SYN_SENT || + pcb->state == SYN_RCVD) { + if (len > 0) { + return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0); + } + return ERR_OK; + } else { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n")); + return ERR_CONN; + } +} + +/** + * Enqueue either data or TCP options (but not both) for tranmission + * + * + * + * @arg pcb Protocol control block for the TCP connection to enqueue data for. + * @arg arg Pointer to the data to be enqueued for sending. + * @arg len Data length in bytes + * @arg flags + * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be + * referenced. + * @arg optdata + * @arg optlen + */ +err_t +tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len, + u8_t flags, u8_t copy, + u8_t *optdata, u8_t optlen) +{ + struct pbuf *p; + struct tcp_seg *seg, *useg, *queue; + u32_t left, seqno; + u16_t seglen; + void *ptr; + u8_t queuelen; + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", copy=%"U16_F")\n", + (void *)pcb, arg, len, (u16_t)flags, (u16_t)copy)); + LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)", + len == 0 || optlen == 0); + LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)", + arg == NULL || optdata == NULL); + /* fail on too much data */ + if (len > pcb->snd_buf) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf)); + return ERR_MEM; + } + left = len; + ptr = arg; + + /* seqno will be the sequence number of the first segment enqueued + * by the call to this function. */ + seqno = pcb->snd_lbb; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + + /* If total number of pbufs on the unsent/unacked queues exceeds the + * configured maximum, return an error */ + queuelen = pcb->snd_queuelen; + if (queuelen >= TCP_SND_QUEUELEN) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } + if (queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty", + pcb->unacked != NULL || pcb->unsent != NULL); + } else { + LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty", + pcb->unacked == NULL && pcb->unsent == NULL); + } + + /* First, break up the data into segments and tuck them together in + * the local "queue" variable. */ + useg = queue = seg = NULL; + seglen = 0; + while (queue == NULL || left > 0) { + + /* The segment length should be the MSS if the data to be enqueued + * is larger than the MSS. */ + seglen = left > pcb->mss? pcb->mss: left; + + /* Allocate memory for tcp_seg, and fill in fields. */ + seg = memp_malloc(MEMP_TCP_SEG); + if (seg == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n")); + goto memerr; + } + seg->next = NULL; + seg->p = NULL; + + /* first segment of to-be-queued data? */ + if (queue == NULL) { + queue = seg; + } + /* subsequent segments of to-be-queued data */ + else { + /* Attach the segment to the end of the queued segments */ + LWIP_ASSERT("useg != NULL", useg != NULL); + useg->next = seg; + } + /* remember last segment of to-be-queued data for next iteration */ + useg = seg; + + /* If copy is set, memory should be allocated + * and data copied into pbuf, otherwise data comes from + * ROM or other static memory, and need not be copied. If + * optdata is != NULL, we have options instead of data. */ + + /* options? */ + if (optdata != NULL) { + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + goto memerr; + } + ++queuelen; + seg->dataptr = seg->p->payload; + } + /* copy from volatile memory? */ + else if (copy) { + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); + goto memerr; + } + ++queuelen; + if (arg != NULL) { + memcpy(seg->p->payload, ptr, seglen); + } + seg->dataptr = seg->p->payload; + } + /* do not copy data */ + else { + /* First, allocate a pbuf for holding the data. + * since the referenced data is available at least until it is sent out on the + * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM + * instead of PBUF_REF here. + */ + if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n")); + goto memerr; + } + ++queuelen; + /* reference the non-volatile payload data */ + p->payload = ptr; + seg->dataptr = ptr; + + /* Second, allocate a pbuf for the headers. */ + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) { + /* If allocation fails, we have to deallocate the data pbuf as + * well. */ + pbuf_free(p); + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n")); + goto memerr; + } + ++queuelen; + + /* Concatenate the headers and data pbufs together. */ + pbuf_cat(seg->p/*header*/, p/*data*/); + p = NULL; + } + + /* Now that there are more segments queued, we check again if the + length of the queue exceeds the configured maximum. */ + if (queuelen > TCP_SND_QUEUELEN) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); + goto memerr; + } + + seg->len = seglen; + + /* build TCP header */ + if (pbuf_header(seg->p, TCP_HLEN)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n")); + TCP_STATS_INC(tcp.err); + goto memerr; + } + seg->tcphdr = seg->p->payload; + seg->tcphdr->src = htons(pcb->local_port); + seg->tcphdr->dest = htons(pcb->remote_port); + seg->tcphdr->seqno = htonl(seqno); + seg->tcphdr->urgp = 0; + TCPH_FLAGS_SET(seg->tcphdr, flags); + /* don't fill in tcphdr->ackno and tcphdr->wnd until later */ + + /* Copy the options into the header, if they are present. */ + if (optdata == NULL) { + TCPH_HDRLEN_SET(seg->tcphdr, 5); + } + else { + TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4)); + /* Copy options into data portion of segment. + Options can thus only be sent in non data carrying + segments such as SYN|ACK. */ + memcpy(seg->dataptr, optdata, optlen); + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", + ntohl(seg->tcphdr->seqno), + ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), + (u16_t)flags)); + + left -= seglen; + seqno += seglen; + ptr = (void *)((u8_t *)ptr + seglen); + } + + /* Now that the data to be enqueued has been broken up into TCP + segments in the queue variable, we add them to the end of the + pcb->unsent queue. */ + if (pcb->unsent == NULL) { + useg = NULL; + } + else { + for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); + } + /* { useg is last segment on the unsent queue, NULL if list is empty } */ + + /* If there is room in the last pbuf on the unsent queue, + chain the first pbuf on the queue together with that. */ + if (useg != NULL && + TCP_TCPLEN(useg) != 0 && + !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) && + !(flags & (TCP_SYN | TCP_FIN)) && + /* fit within max seg size */ + useg->len + queue->len <= pcb->mss) { + /* Remove TCP header from first segment of our to-be-queued list */ + pbuf_header(queue->p, -TCP_HLEN); + pbuf_cat(useg->p, queue->p); + useg->len += queue->len; + useg->next = queue->next; + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len)); + if (seg == queue) { + seg = NULL; + } + memp_free(MEMP_TCP_SEG, queue); + } + else { + /* empty list */ + if (useg == NULL) { + /* initialize list with this segment */ + pcb->unsent = queue; + } + /* enqueue segment */ + else { + useg->next = queue; + } + } + if ((flags & TCP_SYN) || (flags & TCP_FIN)) { + ++len; + } + pcb->snd_lbb += len; + + pcb->snd_buf -= len; + + /* update number of segments on the queues */ + pcb->snd_queuelen = queuelen; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: valid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + + /* Set the PSH flag in the last segment that we enqueued, but only + if the segment has data (indicated by seglen > 0). */ + if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) { + TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); + } + + return ERR_OK; +memerr: + TCP_STATS_INC(tcp.memerr); + + if (queue != NULL) { + tcp_segs_free(queue); + } + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); + } + LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); + return ERR_MEM; +} + +/* find out what we can send and send it */ +err_t +tcp_output(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + struct tcp_seg *seg, *useg; + u32_t wnd; +#if TCP_CWND_DEBUG + s16_t i = 0; +#endif /* TCP_CWND_DEBUG */ + + /* First, check if we are invoked by the TCP input processing + code. If so, we do not output anything. Instead, we rely on the + input processing code to call us when input processing is done + with. */ + if (tcp_input_pcb == pcb) { + return ERR_OK; + } + + wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); + + seg = pcb->unsent; + + /* useg should point to last segment on unacked queue */ + useg = pcb->unacked; + if (useg != NULL) { + for (; useg->next != NULL; useg = useg->next); + } + + /* If the TF_ACK_NOW flag is set and no data will be sent (either + * because the ->unsent queue is empty or because the window does + * not allow it), construct an empty ACK segment and send it. + * + * If data is to be sent, we will just piggyback the ACK (see below). + */ + if (pcb->flags & TF_ACK_NOW && + (seg == NULL || + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) { + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); + return ERR_BUF; + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); + /* remove ACK flags from the PCB, as we send an empty ACK now */ + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + + tcphdr = p->payload; + tcphdr->src = htons(pcb->local_port); + tcphdr->dest = htons(pcb->remote_port); + tcphdr->seqno = htonl(pcb->snd_nxt); + tcphdr->ackno = htonl(pcb->rcv_nxt); + TCPH_FLAGS_SET(tcphdr, TCP_ACK); + tcphdr->wnd = htons(pcb->rcv_wnd); + tcphdr->urgp = 0; + TCPH_HDRLEN_SET(tcphdr, 5); + + tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip), + IP_PROTO_TCP, p->tot_len); +#endif + ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP); + pbuf_free(p); + + return ERR_OK; + } + +#if TCP_OUTPUT_DEBUG + if (seg == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", (void*)pcb->unsent)); + } +#endif /* TCP_OUTPUT_DEBUG */ +#if TCP_CWND_DEBUG + if (seg == NULL) { + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", seg == NULL, ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + pcb->lastack)); + } else { + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, + ntohl(seg->tcphdr->seqno), pcb->lastack)); + } +#endif /* TCP_CWND_DEBUG */ + /* data available and window allows it to be sent? */ + while (seg != NULL && + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { +#if TCP_CWND_DEBUG + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) + seg->len - + pcb->lastack, + ntohl(seg->tcphdr->seqno), pcb->lastack, i)); + ++i; +#endif /* TCP_CWND_DEBUG */ + + pcb->unsent = seg->next; + + if (pcb->state != SYN_SENT) { + TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + } + + tcp_output_segment(seg, pcb); + pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) { + pcb->snd_max = pcb->snd_nxt; + } + /* put segment on unacknowledged list if length > 0 */ + if (TCP_TCPLEN(seg) > 0) { + seg->next = NULL; + /* unacked list is empty? */ + if (pcb->unacked == NULL) { + pcb->unacked = seg; + useg = seg; + /* unacked list is not empty? */ + } else { + /* In the case of fast retransmit, the packet should not go to the tail + * of the unacked queue, but rather at the head. We need to check for + * this case. -STJ Jul 27, 2004 */ + if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){ + /* add segment to head of unacked list */ + seg->next = pcb->unacked; + pcb->unacked = seg; + } else { + /* add segment to tail of unacked list */ + useg->next = seg; + useg = useg->next; + } + } + /* do not queue empty segments on the unacked list */ + } else { + tcp_seg_free(seg); + } + seg = pcb->unsent; + } + return ERR_OK; +} + +/** + * Actually send a TCP segment over IP + */ +static void +tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb) +{ + u16_t len; + struct netif *netif; + + /** @bug Exclude retransmitted segments from this count. */ + snmp_inc_tcpoutsegs(); + + /* The TCP header has already been constructed, but the ackno and + wnd fields remain. */ + seg->tcphdr->ackno = htonl(pcb->rcv_nxt); + + /* silly window avoidance */ + if (pcb->rcv_wnd < pcb->mss) { + seg->tcphdr->wnd = 0; + } else { + /* advertise our receive window size in this TCP segment */ + seg->tcphdr->wnd = htons(pcb->rcv_wnd); + } + + /* If we don't have a local IP address, we get one by + calling ip_route(). */ + if (ip_addr_isany(&(pcb->local_ip))) { + netif = ip_route(&(pcb->remote_ip)); + if (netif == NULL) { + return; + } + ip_addr_set(&(pcb->local_ip), &(netif->ip_addr)); + } + + pcb->rtime = 0; + + if (pcb->rttest == 0) { + pcb->rttest = tcp_ticks; + pcb->rtseq = ntohl(seg->tcphdr->seqno); + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", + htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) + + seg->len)); + + len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); + + seg->p->len -= len; + seg->p->tot_len -= len; + + seg->p->payload = seg->tcphdr; + + seg->tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + seg->tcphdr->chksum = inet_chksum_pseudo(seg->p, + &(pcb->local_ip), + &(pcb->remote_ip), + IP_PROTO_TCP, seg->p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + + ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP); +} + +void +tcp_rst(u32_t seqno, u32_t ackno, + struct ip_addr *local_ip, struct ip_addr *remote_ip, + u16_t local_port, u16_t remote_port) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); + return; + } + + tcphdr = p->payload; + tcphdr->src = htons(local_port); + tcphdr->dest = htons(remote_port); + tcphdr->seqno = htonl(seqno); + tcphdr->ackno = htonl(ackno); + TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK); + tcphdr->wnd = htons(TCP_WND); + tcphdr->urgp = 0; + TCPH_HDRLEN_SET(tcphdr, 5); + + tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip, + IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + snmp_inc_tcpoutrsts(); + /* Send output with hardcoded TTL since we have no access to the pcb */ + ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP); + pbuf_free(p); + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); +} + +/* requeue all unacked segments for retransmission */ +void +tcp_rexmit_rto(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + + if (pcb->unacked == NULL) { + return; + } + + /* Move all unacked segments to the head of the unsent queue */ + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next); + /* concatenate unsent queue after unacked queue */ + seg->next = pcb->unsent; + /* unsent queue is the concatenated queue (of unacked, unsent) */ + pcb->unsent = pcb->unacked; + /* unacked queue is now empty */ + pcb->unacked = NULL; + + pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); + /* increment number of retransmissions */ + ++pcb->nrtx; + + /* Don't take any RTT measurements after retransmitting. */ + pcb->rttest = 0; + + /* Do the actual retransmission */ + tcp_output(pcb); +} + +void +tcp_rexmit(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + + if (pcb->unacked == NULL) { + return; + } + + /* Move the first unacked segment to the unsent queue */ + seg = pcb->unacked->next; + pcb->unacked->next = pcb->unsent; + pcb->unsent = pcb->unacked; + pcb->unacked = seg; + + pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); + + ++pcb->nrtx; + + /* Don't take any rtt measurements after retransmitting. */ + pcb->rttest = 0; + + /* Do the actual retransmission. */ + snmp_inc_tcpretranssegs(); + tcp_output(pcb); + +} + + +void +tcp_keepalive(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt %"U16_F"\n", tcp_ticks, pcb->tmr, pcb->keep_cnt)); + + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + + if(p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n")); + return; + } + + tcphdr = p->payload; + tcphdr->src = htons(pcb->local_port); + tcphdr->dest = htons(pcb->remote_port); + tcphdr->seqno = htonl(pcb->snd_nxt - 1); + tcphdr->ackno = htonl(pcb->rcv_nxt); + tcphdr->wnd = htons(pcb->rcv_wnd); + tcphdr->urgp = 0; + TCPH_HDRLEN_SET(tcphdr, 5); + + tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + + /* Send output to IP */ + ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); + + pbuf_free(p); + + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", pcb->snd_nxt - 1, pcb->rcv_nxt)); +} + +#endif /* LWIP_TCP */ + + + + + + + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/udp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/udp.c new file mode 100644 index 0000000..3d5980f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/core/udp.c @@ -0,0 +1,665 @@ +/** + * @file + * User Datagram Protocol module + * + */ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +/* udp.c + * + * The code for the User Datagram Protocol UDP. + * + */ + +#include + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/inet.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/udp.h" +#include "lwip/icmp.h" + +#include "lwip/stats.h" + +#include "arch/perf.h" +#include "lwip/snmp.h" + +/* The list of UDP PCBs */ +#if LWIP_UDP +/* exported in udp.h (was static) */ +struct udp_pcb *udp_pcbs = NULL; + +static struct udp_pcb *pcb_cache = NULL; + +void +udp_init(void) +{ + udp_pcbs = pcb_cache = NULL; +} + +/** + * Process an incoming UDP datagram. + * + * Given an incoming UDP datagram (as a chain of pbufs) this function + * finds a corresponding UDP PCB and + * + * @param pbuf pbuf to be demultiplexed to a UDP PCB. + * @param netif network interface on which the datagram was received. + * + */ +void +udp_input(struct pbuf *p, struct netif *inp) +{ + struct udp_hdr *udphdr; + struct udp_pcb *pcb; + struct udp_pcb *uncon_pcb; + struct ip_hdr *iphdr; + u16_t src, dest; + u8_t local_match; + + PERF_START; + + UDP_STATS_INC(udp.recv); + + iphdr = p->payload; + + if (p->tot_len < (IPH_HL(iphdr) * 4 + UDP_HLEN)) { + /* drop short packets */ +// LWIP_DEBUGF(UDP_DEBUG, +// ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); + + LWIP_DEBUGF(UDP_DEBUG, + ("udp_input: short UDP datagram (%u bytes) discarded\n", p->tot_len)); + + UDP_STATS_INC(udp.lenerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + + pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))); + + udphdr = (struct udp_hdr *)p->payload; + + LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); + + src = ntohs(udphdr->src); + dest = ntohs(udphdr->dest); + + udp_debug_print(udphdr); + + /* print the UDP source and destination */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- " + "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", + ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest), + ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest), + ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src), + ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src))); + + local_match = 0; + uncon_pcb = NULL; + /* Iterate through the UDP pcb list for a matching pcb */ + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + /* print the PCB local and remote address */ + LWIP_DEBUGF(UDP_DEBUG, + ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- " + "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", + ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip), + ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port, + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port)); + + /* compare PCB local addr+port to UDP destination addr+port */ + if ((pcb->local_port == dest) && + (ip_addr_isany(&pcb->local_ip) || + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)) || + ip_addr_isbroadcast(&(iphdr->dest), inp))) { + local_match = 1; + if ((uncon_pcb == NULL) && + ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) { + /* the first unconnected matching PCB */ + uncon_pcb = pcb; + } + } + /* compare PCB remote addr+port to UDP source addr+port */ + if ((local_match != 0) && + (pcb->remote_port == src) && + (ip_addr_isany(&pcb->remote_ip) || + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) { + /* the first fully matching PCB */ + break; + } + } + /* no fully matching pcb found? then look for an unconnected pcb */ + if (pcb == NULL) { + pcb = uncon_pcb; + } + + /* Check checksum if this is a match or if it was directed at us. */ + if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest)) { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n")); +#ifdef IPv6 + if (iphdr->nexthdr == IP_PROTO_UDPLITE) { +#else + if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) { +#endif /* IPv4 */ + /* Do the UDP Lite checksum */ +#if CHECKSUM_CHECK_UDP + if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) { + LWIP_DEBUGF(UDP_DEBUG | 2, + ("udp_input: UDP Lite datagram discarded due to failing checksum\n")); + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } +#endif + } else { +#if CHECKSUM_CHECK_UDP + if (udphdr->chksum != 0) { + if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_UDP, p->tot_len) != 0) { + LWIP_DEBUGF(UDP_DEBUG | 2, + ("udp_input: UDP datagram discarded due to failing checksum\n")); + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + } +#endif + } + pbuf_header(p, -UDP_HLEN); + if (pcb != NULL) { + snmp_inc_udpindatagrams(); + /* callback */ + if (pcb->recv != NULL) + pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src); + } else { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n")); + + /* No match was found, send ICMP destination port unreachable unless + destination address was broadcast/multicast. */ + + if (!ip_addr_isbroadcast(&iphdr->dest, inp) && + !ip_addr_ismulticast(&iphdr->dest)) { + + /* restore pbuf pointer */ + p->payload = iphdr; + icmp_dest_unreach(p, ICMP_DUR_PORT); + } + UDP_STATS_INC(udp.proterr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpnoports(); + pbuf_free(p); + } + } else { + pbuf_free(p); + } +end: + PERF_STOP("udp_input"); +} + +/** + * Send data to a specified address using UDP. + * + * @param pcb UDP PCB used to send the data. + * @param pbuf chain of pbuf's to be sent. + * @param dst_ip Destination IP address. + * @param dst_port Destination UDP port. + * + * If the PCB already has a remote address association, it will + * be restored after the data is sent. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_MEM. Out of memory. + * - ERR_RTE. Could not find route to destination address. + * + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto(struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *dst_ip, u16_t dst_port) +{ + err_t err; + /* temporary space for current PCB remote address */ + struct ip_addr pcb_remote_ip; + u16_t pcb_remote_port; + /* remember current remote peer address of PCB */ + pcb_remote_ip.addr = pcb->remote_ip.addr; + pcb_remote_port = pcb->remote_port; + /* copy packet destination address to PCB remote peer address */ + pcb->remote_ip.addr = dst_ip->addr; + pcb->remote_port = dst_port; + /* send to the packet destination address */ + err = udp_send(pcb, p); + /* restore PCB remote peer address */ + pcb->remote_ip.addr = pcb_remote_ip.addr; + pcb->remote_port = pcb_remote_port; + return err; +} + +/** + * Send data using UDP. + * + * @param pcb UDP PCB used to send the data. + * @param pbuf chain of pbuf's to be sent. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_MEM. Out of memory. + * - ERR_RTE. Could not find route to destination address. + * + * @see udp_disconnect() udp_sendto() + */ +err_t +udp_send(struct udp_pcb *pcb, struct pbuf *p) +{ + struct udp_hdr *udphdr; + struct netif *netif; + struct ip_addr *src_ip; + err_t err; + struct pbuf *q; /* q will be sent down the stack */ + + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n")); + + /* if the PCB is not yet bound to a port, bind it here */ + if (pcb->local_port == 0) { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n")); + err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n")); + return err; + } + } + /* find the outgoing network interface for this packet */ + netif = ip_route(&(pcb->remote_ip)); + /* no outgoing network interface could be found? */ + if (netif == NULL) { + LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%"X32_F"\n", pcb->remote_ip.addr)); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + } + + /* not enough space to add an UDP header to first pbuf in given p chain? */ + if (pbuf_header(p, UDP_HLEN)) { + /* allocate header in a seperate new pbuf */ + q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n")); + return ERR_MEM; + } + /* chain header q in front of given pbuf p */ + pbuf_chain(q, p); + /* first pbuf q points to header pbuf */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + /* adding a header within p succeeded */ + } else { + /* first pbuf q equals given pbuf */ + q = p; + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); + } + /* q now represents the packet to be sent */ + udphdr = q->payload; + udphdr->src = htons(pcb->local_port); + udphdr->dest = htons(pcb->remote_port); + /* in UDP, 0 checksum means 'no checksum' */ + udphdr->chksum = 0x0000; + + /* PCB local address is IP_ANY_ADDR? */ + if (ip_addr_isany(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ + src_ip = &(netif->ip_addr); + } else { + /* use UDP PCB local IP address as source address */ + src_ip = &(pcb->local_ip); + } + + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); + + /* UDP Lite protocol? */ + if (pcb->flags & UDP_FLAGS_UDPLITE) { + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); + /* set UDP message length in UDP header */ + udphdr->len = htons(pcb->chksum_len); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip), + IP_PROTO_UDP, pcb->chksum_len); + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udphdr->chksum == 0x0000) + udphdr->chksum = 0xffff; +#else + udphdr->chksum = 0x0000; +#endif + /* output to IP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n")); + err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif); + } else { /* UDP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); + udphdr->len = htons(q->tot_len); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) { + udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len); + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff; + } +#else + udphdr->chksum = 0x0000; +#endif + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n")); + /* output to IP */ + err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif); + } + /* TODO: must this be increased even if error occured? */ + snmp_inc_udpoutdatagrams(); + + /* did we chain a seperate header pbuf earlier? */ + if (q != p) { + /* free the header pbuf */ + pbuf_free(q); + q = NULL; + /* p is still referenced by the caller, and will live on */ + } + + UDP_STATS_INC(udp.xmit); + return err; +} + +/** + * Bind an UDP PCB. + * + * @param pcb UDP PCB to be bound with a local address ipaddr and port. + * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to + * bind to all local interfaces. + * @param port local UDP port to bind with. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_USE. The specified ipaddr and port are already bound to by + * another UDP PCB. + * + * @see udp_disconnect() + */ +err_t +udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + u8_t rebind; + + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = ")); + ip_addr_debug_print(UDP_DEBUG, ipaddr); + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %"U16_F")\n", port)); + + rebind = 0; + /* Check for double bind and rebind of the same pcb */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + /* is this UDP PCB already on active list? */ + if (pcb == ipcb) { + /* pcb may occur at most once in active list */ + LWIP_ASSERT("rebind == 0", rebind == 0); + /* pcb already in list, just rebind */ + rebind = 1; + } + + /* this code does not allow upper layer to share a UDP port for + listening to broadcast or multicast traffic (See SO_REUSE_ADDR and + SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR + combine with implementation of UDP PCB flags. Leon Woestenberg. */ +#ifdef LWIP_UDP_TODO + /* port matches that of PCB in list? */ + else + if ((ipcb->local_port == port) && + /* IP address matches, or one is IP_ADDR_ANY? */ + (ip_addr_isany(&(ipcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(ipcb->local_ip), ipaddr))) { + /* other PCB already binds to this local IP and port */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); + return ERR_USE; + } +#endif + } + + ip_addr_set(&pcb->local_ip, ipaddr); + + /* no port specified? */ + if (port == 0) { +#ifndef UDP_LOCAL_PORT_RANGE_START +#define UDP_LOCAL_PORT_RANGE_START 4096 +#define UDP_LOCAL_PORT_RANGE_END 0x7fff +#endif + port = UDP_LOCAL_PORT_RANGE_START; + ipcb = udp_pcbs; + while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) { + if (ipcb->local_port == port) { + port++; + ipcb = udp_pcbs; + } else + ipcb = ipcb->next; + } + if (ipcb != NULL) { + /* no more ports available in local range */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); + return ERR_USE; + } + } + pcb->local_port = port; + snmp_insert_udpidx_tree(pcb); + /* pcb not active yet? */ + if (rebind == 0) { + /* place the PCB on the active list if not already there */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + } + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, + ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n", + (u16_t)(ntohl(pcb->local_ip.addr) >> 24 & 0xff), + (u16_t)(ntohl(pcb->local_ip.addr) >> 16 & 0xff), + (u16_t)(ntohl(pcb->local_ip.addr) >> 8 & 0xff), + (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port)); + return ERR_OK; +} +/** + * Connect an UDP PCB. + * + * This will associate the UDP PCB with the remote address. + * + * @param pcb UDP PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * @param port remote UDP port to connect with. + * + * @return lwIP error code + * + * @see udp_disconnect() + */ +err_t +udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + + if (pcb->local_port == 0) { + err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) + return err; + } + + ip_addr_set(&pcb->remote_ip, ipaddr); + pcb->remote_port = port; + pcb->flags |= UDP_FLAGS_CONNECTED; +/** TODO: this functionality belongs in upper layers */ +#ifdef LWIP_UDP_TODO + /* Nail down local IP for netconn_addr()/getsockname() */ + if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) { + struct netif *netif; + + if ((netif = ip_route(&(pcb->remote_ip))) == NULL) { + LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr)); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + } + /** TODO: this will bind the udp pcb locally, to the interface which + is used to route output packets to the remote address. However, we + might want to accept incoming packets on any interface! */ + pcb->local_ip = netif->ip_addr; + } else if (ip_addr_isany(&pcb->remote_ip)) { + pcb->local_ip.addr = 0; + } +#endif + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, + ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n", + (u16_t)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff), + (u16_t)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff), + (u16_t)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff), + (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port)); + + /* Insert UDP PCB into the list of active UDP PCBs. */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + if (pcb == ipcb) { + /* already on the list, just return */ + return ERR_OK; + } + } + /* PCB not yet on the list, add PCB now */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + return ERR_OK; +} + +void +udp_disconnect(struct udp_pcb *pcb) +{ + /* reset remote address association */ + ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY); + pcb->remote_port = 0; + /* mark PCB as unconnected */ + pcb->flags &= ~UDP_FLAGS_CONNECTED; +} + +void +udp_recv(struct udp_pcb *pcb, + void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p, + struct ip_addr *addr, u16_t port), + void *recv_arg) +{ + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * Remove an UDP PCB. + * + * @param pcb UDP PCB to be removed. The PCB is removed from the list of + * UDP PCB's and the data structure is freed from memory. + * + * @see udp_new() + */ +void +udp_remove(struct udp_pcb *pcb) +{ + struct udp_pcb *pcb2; + + snmp_delete_udpidx_tree(pcb); + /* pcb to be removed is first in list? */ + if (udp_pcbs == pcb) { + /* make list start at 2nd pcb */ + udp_pcbs = udp_pcbs->next; + /* pcb not 1st in list */ + } else + for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in udp_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + } + } + memp_free(MEMP_UDP_PCB, pcb); +} + +/** + * Create a UDP PCB. + * + * @return The UDP PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @see udp_remove() + */ +struct udp_pcb * +udp_new(void) +{ + struct udp_pcb *pcb; + pcb = memp_malloc(MEMP_UDP_PCB); + /* could allocate UDP PCB? */ + if (pcb != NULL) { + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct udp_pcb)); + pcb->ttl = UDP_TTL; + } + return pcb; +} + +#if UDP_DEBUG +void +udp_debug_print(struct udp_hdr *udphdr) +{ + LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + ntohs(udphdr->src), ntohs(udphdr->dest))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", + ntohs(udphdr->len), ntohs(udphdr->chksum))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* UDP_DEBUG */ + +#endif /* LWIP_UDP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/icmp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/icmp.h new file mode 100644 index 0000000..04307e7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/icmp.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ICMP_H__ +#define __LWIP_ICMP_H__ + +#include "lwip/arch.h" + +#include "lwip/opt.h" +#include "lwip/pbuf.h" + +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +#define ICMP_ER 0 /* echo reply */ +#define ICMP_DUR 3 /* destination unreachable */ +#define ICMP_SQ 4 /* source quench */ +#define ICMP_RD 5 /* redirect */ +#define ICMP_ECHO 8 /* echo */ +#define ICMP_TE 11 /* time exceeded */ +#define ICMP_PP 12 /* parameter problem */ +#define ICMP_TS 13 /* timestamp */ +#define ICMP_TSR 14 /* timestamp reply */ +#define ICMP_IRQ 15 /* information request */ +#define ICMP_IR 16 /* information reply */ + +enum icmp_dur_type { + ICMP_DUR_NET = 0, /* net unreachable */ + ICMP_DUR_HOST = 1, /* host unreachable */ + ICMP_DUR_PROTO = 2, /* protocol unreachable */ + ICMP_DUR_PORT = 3, /* port unreachable */ + ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ + ICMP_DUR_SR = 5 /* source route failed */ +}; + +enum icmp_te_type { + ICMP_TE_TTL = 0, /* time to live exceeded in transit */ + ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ +}; + +void icmp_input(struct pbuf *p, struct netif *inp); + +void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); +void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct icmp_echo_hdr { + PACK_STRUCT_FIELD(u16_t _type_code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FIELD(u16_t seqno); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END + +PACK_STRUCT_BEGIN +struct icmp_dur_hdr { + PACK_STRUCT_FIELD(u16_t _type_code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u32_t unused); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END + +PACK_STRUCT_BEGIN +struct icmp_te_hdr { + PACK_STRUCT_FIELD(u16_t _type_code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u32_t unused); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8) +#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff) + +#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8))) +#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8))) + +#endif /* __LWIP_ICMP_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/inet.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/inet.h new file mode 100644 index 0000000..9e77b74 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/inet.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_H__ +#define __LWIP_INET_H__ + +#include "lwip/arch.h" + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +u16_t inet_chksum(void *dataptr, u16_t len); +#if 0 /* optimized routine */ +u16_t inet_chksum4(u8_t *dataptr, u16_t len); +#endif +u16_t inet_chksum_pbuf(struct pbuf *p); +u16_t inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u16_t proto_len); + +u32_t inet_addr(const char *cp); +int inet_aton(const char *cp, struct in_addr *addr); +char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */ + +#ifdef htons +#undef htons +#endif /* htons */ +#ifdef htonl +#undef htonl +#endif /* htonl */ +#ifdef ntohs +#undef ntohs +#endif /* ntohs */ +#ifdef ntohl +#undef ntohl +#endif /* ntohl */ + +#ifndef LWIP_PLATFORM_BYTESWAP +#define LWIP_PLATFORM_BYTESWAP 0 +#endif + +#if BYTE_ORDER == BIG_ENDIAN +#define htons(x) (x) +#define ntohs(x) (x) +#define htonl(x) (x) +#define ntohl(x) (x) +#else /* BYTE_ORDER != BIG_ENDIAN */ +#ifdef LWIP_PREFIX_BYTEORDER_FUNCS +/* workaround for naming collisions on some platforms */ +#define htons lwip_htons +#define ntohs lwip_ntohs +#define htonl lwip_htonl +#define ntohl lwip_ntohl +#endif +#if LWIP_PLATFORM_BYTESWAP +#define htons(x) LWIP_PLATFORM_HTONS(x) +#define ntohs(x) LWIP_PLATFORM_HTONS(x) +#define htonl(x) LWIP_PLATFORM_HTONL(x) +#define ntohl(x) LWIP_PLATFORM_HTONL(x) +#else +u16_t htons(u16_t x); +u16_t ntohs(u16_t x); +u32_t htonl(u32_t x); +u32_t ntohl(u32_t x); +#endif + +#endif + +#endif /* __LWIP_INET_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/ip.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/ip.h new file mode 100644 index 0000000..e5a8da0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/ip.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_H__ +#define __LWIP_IP_H__ + +#include "lwip/arch.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#include "lwip/err.h" + + +void ip_init(void); +struct netif *ip_route(struct ip_addr *dest); +err_t ip_input(struct pbuf *p, struct netif *inp); +err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto); +err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto, + struct netif *netif); + +#define IP_HLEN 20 + +#define IP_PROTO_ICMP 1 +#define IP_PROTO_UDP 17 +#define IP_PROTO_UDPLITE 136 +#define IP_PROTO_TCP 6 + +/* This is passed as the destination address to ip_output_if (not + to ip_output), meaning that an IP header already is constructed + in the pbuf. This is used when TCP retransmits. */ +#ifdef IP_HDRINCL +#undef IP_HDRINCL +#endif /* IP_HDRINCL */ +#define IP_HDRINCL NULL + + +/* This is the common part of all PCB types. It needs to be at the + beginning of a PCB type definition. It is located here so that + changes to this common part are made in one location instead of + having to change all PCB structs. */ +#define IP_PCB struct ip_addr local_ip; \ + struct ip_addr remote_ip; \ + /* Socket options */ \ + u16_t so_options; \ + /* Type Of Service */ \ + u8_t tos; \ + /* Time To Live */ \ + u8_t ttl + +/* + * Option flags per-socket. These are the same like SO_XXX. + */ +#define SOF_DEBUG (u16_t)0x0001U /* turn on debugging info recording */ +#define SOF_ACCEPTCONN (u16_t)0x0002U /* socket has had listen() */ +#define SOF_REUSEADDR (u16_t)0x0004U /* allow local address reuse */ +#define SOF_KEEPALIVE (u16_t)0x0008U /* keep connections alive */ +#define SOF_DONTROUTE (u16_t)0x0010U /* just use interface addresses */ +#define SOF_BROADCAST (u16_t)0x0020U /* permit sending of broadcast msgs */ +#define SOF_USELOOPBACK (u16_t)0x0040U /* bypass hardware when possible */ +#define SOF_LINGER (u16_t)0x0080U /* linger on close if data present */ +#define SOF_OOBINLINE (u16_t)0x0100U /* leave received OOB data in line */ +#define SOF_REUSEPORT (u16_t)0x0200U /* allow local address & port reuse */ + + + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_hdr { + /* version / header length / type of service */ + PACK_STRUCT_FIELD(u16_t _v_hl_tos); + /* total length */ + PACK_STRUCT_FIELD(u16_t _len); + /* identification */ + PACK_STRUCT_FIELD(u16_t _id); + /* fragment offset field */ + PACK_STRUCT_FIELD(u16_t _offset); +#define IP_RF 0x8000 /* reserved fragment flag */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + /* time to live / protocol*/ + PACK_STRUCT_FIELD(u16_t _ttl_proto); + /* checksum */ + PACK_STRUCT_FIELD(u16_t _chksum); + /* source and destination IP addresses */ + PACK_STRUCT_FIELD(struct ip_addr src); + PACK_STRUCT_FIELD(struct ip_addr dest); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12) +#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f) +#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff) +#define IPH_LEN(hdr) ((hdr)->_len) +#define IPH_ID(hdr) ((hdr)->_id) +#define IPH_OFFSET(hdr) ((hdr)->_offset) +#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8) +#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff) +#define IPH_CHKSUM(hdr) ((hdr)->_chksum) + +#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos))) +#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) +#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) +#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) +#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((u16_t)(ttl) << 8))) +#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8))) +#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) + +#if IP_DEBUG +void ip_debug_print(struct pbuf *p); +#else +#define ip_debug_print(p) +#endif /* IP_DEBUG */ + +#endif /* __LWIP_IP_H__ */ + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/ip_addr.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/ip_addr.h new file mode 100644 index 0000000..1f0f754 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/ip_addr.h @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_ADDR_H__ +#define __LWIP_IP_ADDR_H__ + +#include "lwip/arch.h" + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr { + PACK_STRUCT_FIELD(u32_t addr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* + * struct ipaddr2 is used in the definition of the ARP packet format in + * order to support compilers that don't have structure packing. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr2 { + PACK_STRUCT_FIELD(u16_t addrw[2]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* For compatibility with BSD code */ +struct in_addr { + u32_t s_addr; +}; + +struct netif; + +extern const struct ip_addr ip_addr_any; +extern const struct ip_addr ip_addr_broadcast; + +/** IP_ADDR_ can be used as a fixed IP address + * for the wildcard and the broadcast address + */ +#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any) +#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast) + +#define INADDR_NONE ((u32_t)0xffffffff) /* 255.255.255.255 */ +#define INADDR_LOOPBACK ((u32_t)0x7f000001) /* 127.0.0.1 */ + +/* Definitions of the bits in an Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ + +#define IN_CLASSA(a) ((((u32_t)(a)) & 0x80000000) == 0) +#define IN_CLASSA_NET 0xff000000 +#define IN_CLASSA_NSHIFT 24 +#define IN_CLASSA_HOST (0xffffffff & ~IN_CLASSA_NET) +#define IN_CLASSA_MAX 128 + +#define IN_CLASSB(a) ((((u32_t)(a)) & 0xc0000000) == 0x80000000) +#define IN_CLASSB_NET 0xffff0000 +#define IN_CLASSB_NSHIFT 16 +#define IN_CLASSB_HOST (0xffffffff & ~IN_CLASSB_NET) +#define IN_CLASSB_MAX 65536 + +#define IN_CLASSC(a) ((((u32_t)(a)) & 0xe0000000) == 0xc0000000) +#define IN_CLASSC_NET 0xffffff00 +#define IN_CLASSC_NSHIFT 8 +#define IN_CLASSC_HOST (0xffffffff & ~IN_CLASSC_NET) + +#define IN_CLASSD(a) (((u32_t)(a) & 0xf0000000) == 0xe0000000) +#define IN_CLASSD_NET 0xf0000000 /* These ones aren't really */ +#define IN_CLASSD_NSHIFT 28 /* net and host fields, but */ +#define IN_CLASSD_HOST 0x0fffffff /* routing needn't know. */ +#define IN_MULTICAST(a) IN_CLASSD(a) + +#define IN_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000) +#define IN_BADCLASS(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000) + +#define IN_LOOPBACKNET 127 /* official! */ + +#define IP4_ADDR(ipaddr, a,b,c,d) \ + (ipaddr)->addr = htonl(((u32_t)((a) & 0xff) << 24) | \ + ((u32_t)((b) & 0xff) << 16) | \ + ((u32_t)((c) & 0xff) << 8) | \ + (u32_t)((d) & 0xff)) + +#define ip_addr_set(dest, src) (dest)->addr = \ + ((src) == NULL? 0:\ + (src)->addr) +/** + * Determine if two address are on the same network. + * + * @arg addr1 IP address 1 + * @arg addr2 IP address 2 + * @arg mask network identifier mask + * @return !0 if the network identifiers of both address match + */ +#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ + (mask)->addr) == \ + ((addr2)->addr & \ + (mask)->addr)) +#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) + +#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0) + +u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *); + +#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000)) + +#define ip_addr_debug_print(debug, ipaddr) \ + LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \ + ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff : 0, \ + ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff : 0, \ + ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff : 0, \ + ipaddr ? (u16_t)ntohl((ipaddr)->addr) & 0xff : 0)) + +/* These are cast to u16_t, with the intent that they are often arguments + * to printf using the U16_F format from cc.h. */ +#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff) +#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff) +#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff) +#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff) + +#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/ip_frag.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/ip_frag.h new file mode 100644 index 0000000..30be1a8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/ipv4/lwip/ip_frag.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * + */ + +#ifndef __LWIP_IP_FRAG_H__ +#define __LWIP_IP_FRAG_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" + +void ip_frag_init(void); +void ip_reass_tmr(void); +struct pbuf * ip_reass(struct pbuf *p); +err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest); + +#endif /* __LWIP_IP_FRAG_H__ */ + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/api.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/api.h new file mode 100644 index 0000000..1059eca --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/api.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_H__ +#define __LWIP_API_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" + +#include "lwip/ip.h" + +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" + +#include "lwip/err.h" + +#define NETCONN_NOCOPY 0x00 +#define NETCONN_COPY 0x01 + +enum netconn_type { + NETCONN_TCP, + NETCONN_UDP, + NETCONN_UDPLITE, + NETCONN_UDPNOCHKSUM, + NETCONN_RAW +}; + +enum netconn_state { + NETCONN_NONE, + NETCONN_WRITE, + NETCONN_ACCEPT, + NETCONN_RECV, + NETCONN_CONNECT, + NETCONN_CLOSE +}; + +enum netconn_evt { + NETCONN_EVT_RCVPLUS, + NETCONN_EVT_RCVMINUS, + NETCONN_EVT_SENDPLUS, + NETCONN_EVT_SENDMINUS +}; + +struct netbuf { + struct pbuf *p, *ptr; + struct ip_addr *fromaddr; + u16_t fromport; + err_t err; +}; + +struct netconn { + enum netconn_type type; + enum netconn_state state; + union { + struct tcp_pcb *tcp; + struct udp_pcb *udp; + struct raw_pcb *raw; + } pcb; + err_t err; + sys_mbox_t mbox; + sys_mbox_t recvmbox; + sys_mbox_t acceptmbox; + sys_sem_t sem; + int socket; + u16_t recv_avail; + void (* callback)(struct netconn *, enum netconn_evt, u16_t len); +}; + +/* Network buffer functions: */ +struct netbuf * netbuf_new (void); +void netbuf_delete (struct netbuf *buf); +void * netbuf_alloc (struct netbuf *buf, u16_t size); +void netbuf_free (struct netbuf *buf); +void netbuf_ref (struct netbuf *buf, + void *dataptr, u16_t size); +void netbuf_chain (struct netbuf *head, + struct netbuf *tail); + +u16_t netbuf_len (struct netbuf *buf); +err_t netbuf_data (struct netbuf *buf, + void **dataptr, u16_t *len); +s8_t netbuf_next (struct netbuf *buf); +void netbuf_first (struct netbuf *buf); + +void netbuf_copy (struct netbuf *buf, + void *dataptr, u16_t len); +void netbuf_copy_partial(struct netbuf *buf, void *dataptr, + u16_t len, u16_t offset); +struct ip_addr * netbuf_fromaddr (struct netbuf *buf); +u16_t netbuf_fromport (struct netbuf *buf); + +/* Network connection functions: */ +struct netconn * netconn_new (enum netconn_type type); +struct +netconn *netconn_new_with_callback(enum netconn_type t, + void (*callback)(struct netconn *, enum netconn_evt, u16_t len)); +struct +netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto, + void (*callback)(struct netconn *, enum netconn_evt, u16_t len)); +err_t netconn_delete (struct netconn *conn); +enum netconn_type netconn_type (struct netconn *conn); +err_t netconn_peer (struct netconn *conn, + struct ip_addr *addr, + u16_t *port); +err_t netconn_addr (struct netconn *conn, + struct ip_addr **addr, + u16_t *port); +err_t netconn_bind (struct netconn *conn, + struct ip_addr *addr, + u16_t port); +err_t netconn_connect (struct netconn *conn, + struct ip_addr *addr, + u16_t port); +err_t netconn_disconnect (struct netconn *conn); +err_t netconn_listen (struct netconn *conn); +struct netconn * netconn_accept (struct netconn *conn); +struct netbuf * netconn_recv (struct netconn *conn); +err_t netconn_send (struct netconn *conn, + struct netbuf *buf); +err_t netconn_write (struct netconn *conn, + void *dataptr, u16_t size, + u8_t copy); +err_t netconn_close (struct netconn *conn); + +err_t netconn_err (struct netconn *conn); + +#endif /* __LWIP_API_H__ */ + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/api_msg.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/api_msg.h new file mode 100644 index 0000000..87f3db5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/api_msg.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_MSG_H__ +#define __LWIP_API_MSG_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" + +#include "lwip/ip.h" + +#include "lwip/udp.h" +#include "lwip/tcp.h" + +#include "lwip/api.h" + +enum api_msg_type { + API_MSG_NEWCONN, + API_MSG_DELCONN, + + API_MSG_BIND, + API_MSG_CONNECT, + API_MSG_DISCONNECT, + + API_MSG_LISTEN, + API_MSG_ACCEPT, + + API_MSG_SEND, + API_MSG_RECV, + API_MSG_WRITE, + + API_MSG_CLOSE, + + API_MSG_MAX +}; + +struct api_msg_msg { + struct netconn *conn; + enum netconn_type conntype; + union { + struct pbuf *p; + struct { + struct ip_addr *ipaddr; + u16_t port; + } bc; + struct { + void *dataptr; + u16_t len; + u8_t copy; + } w; + sys_mbox_t mbox; + u16_t len; + } msg; +}; + +struct api_msg { + enum api_msg_type type; + struct api_msg_msg msg; +}; + +void api_msg_input(struct api_msg *msg); +void api_msg_post(struct api_msg *msg); + +#endif /* __LWIP_API_MSG_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/arch.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/arch.h new file mode 100644 index 0000000..b43dd64 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/arch.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ARCH_H__ +#define __LWIP_ARCH_H__ + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 1234 +#endif + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 4321 +#endif + +#include "arch/cc.h" + +#ifndef PACK_STRUCT_BEGIN +#define PACK_STRUCT_BEGIN +#endif /* PACK_STRUCT_BEGIN */ + +#ifndef PACK_STRUCT_END +#define PACK_STRUCT_END +#endif /* PACK_STRUCT_END */ + +#ifndef PACK_STRUCT_FIELD +#define PACK_STRUCT_FIELD(x) x +#endif /* PACK_STRUCT_FIELD */ + +#ifndef PACK_STRUCT_STRUCT +#define PACK_STRUCT_STRUCT +#endif /* PACK_STRUCT_STRUCT */ + +#ifdef LWIP_PROVIDE_ERRNO + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + + +#define ENSROK 0 /* DNS server returned answer with no data */ +#define ENSRNODATA 160 /* DNS server returned answer with no data */ +#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ +#define ENSRSERVFAIL 162 /* DNS server returned general failure */ +#define ENSRNOTFOUND 163 /* Domain name not found */ +#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ +#define ENSRREFUSED 165 /* DNS server refused query */ +#define ENSRBADQUERY 166 /* Misformatted DNS query */ +#define ENSRBADNAME 167 /* Misformatted domain name */ +#define ENSRBADFAMILY 168 /* Unsupported address family */ +#define ENSRBADRESP 169 /* Misformatted DNS reply */ +#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ +#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ +#define ENSROF 172 /* End of file */ +#define ENSRFILE 173 /* Error reading file */ +#define ENSRNOMEM 174 /* Out of memory */ +#define ENSRDESTRUCTION 175 /* Application terminated lookup */ +#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ +#define ENSRCNAMELOOP 177 /* Domain name is too long */ + +#ifndef errno +extern int errno; +#endif + +#endif /* LWIP_PROVIDE_ERRNO */ + +#endif /* __LWIP_ARCH_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/debug.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/debug.h new file mode 100644 index 0000000..3649cbd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/debug.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEBUG_H__ +#define __LWIP_DEBUG_H__ + +#include "arch/cc.h" + +/** lower two bits indicate debug level + * - 0 off + * - 1 warning + * - 2 serious + * - 3 severe + */ + +#define DBG_LEVEL_OFF 0 +#define DBG_LEVEL_WARNING 1 /* bad checksums, dropped packets, ... */ +#define DBG_LEVEL_SERIOUS 2 /* memory allocation failures, ... */ +#define DBG_LEVEL_SEVERE 3 /* */ +#define DBG_MASK_LEVEL 3 + +/** flag for LWIP_DEBUGF to enable that debug message */ +#define DBG_ON 0x80U +/** flag for LWIP_DEBUGF to disable that debug message */ +#define DBG_OFF 0x00U + +/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ +#define DBG_TRACE 0x40U +/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ +#define DBG_STATE 0x20U +/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ +#define DBG_FRESH 0x10U +/** flag for LWIP_DEBUGF to halt after printing this debug message */ +#define DBG_HALT 0x08U + +#ifndef LWIP_NOASSERT +# define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0) +#else +# define LWIP_ASSERT(x,y) +#endif + +#ifdef LWIP_DEBUG +/** print debug message only if debug message type is enabled... + * AND is of correct type AND is at least DBG_LEVEL + */ +# define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((s16_t)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0) +# define LWIP_ERROR(x) do { LWIP_PLATFORM_DIAG(x); } while(0) +#else /* LWIP_DEBUG */ +# define LWIP_DEBUGF(debug,x) +# define LWIP_ERROR(x) +#endif /* LWIP_DEBUG */ + +#endif /* __LWIP_DEBUG_H__ */ + + + + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/def.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/def.h new file mode 100644 index 0000000..f26bdd0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/def.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEF_H__ +#define __LWIP_DEF_H__ + +/* this might define NULL already */ +#include "arch/cc.h" + +#define LWIP_MAX(x , y) (x) > (y) ? (x) : (y) +#define LWIP_MIN(x , y) (x) < (y) ? (x) : (y) + +#ifndef NULL +#define NULL ((void *)0) +#endif + + +#endif /* __LWIP_DEF_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/dhcp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/dhcp.h new file mode 100644 index 0000000..df51bdc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/dhcp.h @@ -0,0 +1,223 @@ +/** @file + */ + +#ifndef __LWIP_DHCP_H__ +#define __LWIP_DHCP_H__ + +#include "lwip/opt.h" +#include "lwip/netif.h" +#include "lwip/udp.h" + +/** period (in seconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_SECS 60 +/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ +#define DHCP_FINE_TIMER_MSECS 500 + +struct dhcp +{ + /** current DHCP state machine state */ + u8_t state; + /** retries of current request */ + u8_t tries; + /** transaction identifier of last sent request */ + u32_t xid; + /** our connection to the DHCP server */ + struct udp_pcb *pcb; + /** (first) pbuf of incoming msg */ + struct pbuf *p; + /** incoming msg */ + struct dhcp_msg *msg_in; + /** incoming msg options */ + struct dhcp_msg *options_in; + /** ingoing msg options length */ + u16_t options_in_len; + + struct pbuf *p_out; /* pbuf of outcoming msg */ + struct dhcp_msg *msg_out; /* outgoing msg */ + u16_t options_out_len; /* outgoing msg options length */ + u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ + u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ + u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ + struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */ + struct ip_addr offered_ip_addr; + struct ip_addr offered_sn_mask; + struct ip_addr offered_gw_addr; + struct ip_addr offered_bc_addr; +#define DHCP_MAX_DNS 2 + u32_t dns_count; /* actual number of DNS servers obtained */ + struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */ + + u32_t offered_t0_lease; /* lease period (in seconds) */ + u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ + u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */ +/** Patch #1308 + * TODO: See dhcp.c "TODO"s + */ +#if 0 + struct ip_addr offered_si_addr; + u8_t *boot_file_name; +#endif +}; + +/* MUST be compiled with "pack structs" or equivalent! */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** minimum set of fields of any DHCP message */ +struct dhcp_msg +{ + PACK_STRUCT_FIELD(u8_t op); + PACK_STRUCT_FIELD(u8_t htype); + PACK_STRUCT_FIELD(u8_t hlen); + PACK_STRUCT_FIELD(u8_t hops); + PACK_STRUCT_FIELD(u32_t xid); + PACK_STRUCT_FIELD(u16_t secs); + PACK_STRUCT_FIELD(u16_t flags); + PACK_STRUCT_FIELD(struct ip_addr ciaddr); + PACK_STRUCT_FIELD(struct ip_addr yiaddr); + PACK_STRUCT_FIELD(struct ip_addr siaddr); + PACK_STRUCT_FIELD(struct ip_addr giaddr); +#define DHCP_CHADDR_LEN 16U + PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]); +#define DHCP_SNAME_LEN 64U + PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]); +#define DHCP_FILE_LEN 128U + PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]); + PACK_STRUCT_FIELD(u32_t cookie); +#define DHCP_MIN_OPTIONS_LEN 68U +/** make sure user does not configure this too small */ +#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) +# undef DHCP_OPTIONS_LEN +#endif +/** allow this to be configured in lwipopts.h, but not too small */ +#if (!defined(DHCP_OPTIONS_LEN)) +/** set this to be sufficient for your options in outgoing DHCP msgs */ +# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN +#endif + PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** start DHCP configuration */ +err_t dhcp_start(struct netif *netif); +/** enforce early lease renewal (not needed normally)*/ +err_t dhcp_renew(struct netif *netif); +/** release the DHCP lease, usually called before dhcp_stop()*/ +err_t dhcp_release(struct netif *netif); +/** stop DHCP configuration */ +void dhcp_stop(struct netif *netif); +/** inform server of our manual IP address */ +void dhcp_inform(struct netif *netif); + +/** if enabled, check whether the offered IP address is not in use, using ARP */ +#if DHCP_DOES_ARP_CHECK +void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr); +#endif + +/** to be called every minute */ +void dhcp_coarse_tmr(void); +/** to be called every half second */ +void dhcp_fine_tmr(void); + +/** DHCP message item offsets and length */ +#define DHCP_MSG_OFS (UDP_DATA_OFS) + #define DHCP_OP_OFS (DHCP_MSG_OFS + 0) + #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1) + #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2) + #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3) + #define DHCP_XID_OFS (DHCP_MSG_OFS + 4) + #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8) + #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10) + #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12) + #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16) + #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20) + #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24) + #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28) + #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44) + #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108) +#define DHCP_MSG_LEN 236 + +#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN) +#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4) + +#define DHCP_CLIENT_PORT 68 +#define DHCP_SERVER_PORT 67 + +/** DHCP client states */ +#define DHCP_REQUESTING 1 +#define DHCP_INIT 2 +#define DHCP_REBOOTING 3 +#define DHCP_REBINDING 4 +#define DHCP_RENEWING 5 +#define DHCP_SELECTING 6 +#define DHCP_INFORMING 7 +#define DHCP_CHECKING 8 +#define DHCP_PERMANENT 9 +#define DHCP_BOUND 10 +/** not yet implemented #define DHCP_RELEASING 11 */ +#define DHCP_BACKING_OFF 12 +#define DHCP_OFF 13 + +#define DHCP_BOOTREQUEST 1 +#define DHCP_BOOTREPLY 2 + +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 +#define DHCP_INFORM 8 + +#define DHCP_HTYPE_ETH 1 + +#define DHCP_HLEN_ETH 6 + +#define DHCP_BROADCAST_FLAG 15 +#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST) + +/** BootP options */ +#define DHCP_OPTION_PAD 0 +#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ +#define DHCP_OPTION_ROUTER 3 +#define DHCP_OPTION_DNS_SERVER 6 +#define DHCP_OPTION_HOSTNAME 12 +#define DHCP_OPTION_IP_TTL 23 +#define DHCP_OPTION_MTU 26 +#define DHCP_OPTION_BROADCAST 28 +#define DHCP_OPTION_TCP_TTL 37 +#define DHCP_OPTION_END 255 + +/** DHCP options */ +#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ +#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ +#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ + +#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ +#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 + + +#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ +#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ + +#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ +#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 + +#define DHCP_OPTION_T1 58 /* T1 renewal time */ +#define DHCP_OPTION_T2 59 /* T2 rebinding time */ +#define DHCP_OPTION_CLIENT_ID 61 +#define DHCP_OPTION_TFTP_SERVERNAME 66 +#define DHCP_OPTION_BOOTFILE 67 + +/** possible combinations of overloading the file and sname fields with options */ +#define DHCP_OVERLOAD_NONE 0 +#define DHCP_OVERLOAD_FILE 1 +#define DHCP_OVERLOAD_SNAME 2 +#define DHCP_OVERLOAD_SNAME_FILE 3 + +#endif /*__LWIP_DHCP_H__*/ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/err.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/err.h new file mode 100644 index 0000000..fc90f2e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/err.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ERR_H__ +#define __LWIP_ERR_H__ + +#include "lwip/opt.h" + +#include "arch/cc.h" + +typedef s8_t err_t; + +/* Definitions for error constants. */ + +#define ERR_OK 0 /* No error, everything OK. */ +#define ERR_MEM -1 /* Out of memory error. */ +#define ERR_BUF -2 /* Buffer error. */ + + +#define ERR_ABRT -3 /* Connection aborted. */ +#define ERR_RST -4 /* Connection reset. */ +#define ERR_CLSD -5 /* Connection closed. */ +#define ERR_CONN -6 /* Not connected. */ + +#define ERR_VAL -7 /* Illegal value. */ + +#define ERR_ARG -8 /* Illegal argument. */ + +#define ERR_RTE -9 /* Routing problem. */ + +#define ERR_USE -10 /* Address in use. */ + +#define ERR_IF -11 /* Low-level netif error */ +#define ERR_ISCONN -12 /* Already connected. */ + + +#ifdef LWIP_DEBUG +extern char *lwip_strerr(err_t err); +#else +#define lwip_strerr(x) "" +#endif /* LWIP_DEBUG */ +#endif /* __LWIP_ERR_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/mem.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/mem.h new file mode 100644 index 0000000..3d57389 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/mem.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_MEM_H__ +#define __LWIP_MEM_H__ + +#include "lwip/opt.h" +#include "lwip/arch.h" + +#if MEM_SIZE > 64000l +typedef u32_t mem_size_t; +#define MEM_SIZE_F U32_F +#else +typedef u16_t mem_size_t; +#define MEM_SIZE_F U16_F +#endif /* MEM_SIZE > 64000 */ + +#if MEM_LIBC_MALLOC +/* aliases for C library malloc() */ +#define mem_init() +#define mem_free(x) free(x) +#define mem_malloc(x) malloc(x) +#define mem_realloc(x, size) realloc(x,size) +#else +/* lwIP alternative malloc */ +void mem_init(void); +void *mem_malloc(mem_size_t size); +void mem_free(void *mem); +void *mem_realloc(void *mem, mem_size_t size); +#endif + +#ifndef MEM_ALIGN_SIZE +#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1)) +#endif + +#ifndef MEM_ALIGN +#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) +#endif + +#endif /* __LWIP_MEM_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/memp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/memp.h new file mode 100644 index 0000000..6da033f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/memp.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_MEMP_H__ +#define __LWIP_MEMP_H__ + +#include "lwip/opt.h" + +typedef enum { + MEMP_PBUF, + MEMP_RAW_PCB, + MEMP_UDP_PCB, + MEMP_TCP_PCB, + MEMP_TCP_PCB_LISTEN, + MEMP_TCP_SEG, + + MEMP_NETBUF, + MEMP_NETCONN, + MEMP_API_MSG, + MEMP_TCPIP_MSG, + + MEMP_SYS_TIMEOUT, + + MEMP_MAX +} memp_t; + +void memp_init(void); + +void *memp_malloc(memp_t type); +void *memp_realloc(memp_t fromtype, memp_t totype, void *mem); +void memp_free(memp_t type, void *mem); + +#endif /* __LWIP_MEMP_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/netif.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/netif.h new file mode 100644 index 0000000..efc59fd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/netif.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_NETIF_H__ +#define __LWIP_NETIF_H__ + +#include "lwip/opt.h" + +#include "lwip/err.h" + +#include "lwip/ip_addr.h" + +#include "lwip/inet.h" +#include "lwip/pbuf.h" +#if LWIP_DHCP +# include "lwip/dhcp.h" +#endif + +/** must be the maximum of all used hardware address lengths + across all types of interfaces in use */ +#define NETIF_MAX_HWADDR_LEN 6U + +/** TODO: define the use (where, when, whom) of netif flags */ + +/** whether the network interface is 'up'. this is + * a software flag used to control whether this network + * interface is enabled and processes traffic. + */ +#define NETIF_FLAG_UP 0x1U +/** if set, the netif has broadcast capability */ +#define NETIF_FLAG_BROADCAST 0x2U +/** if set, the netif is one end of a point-to-point connection */ +#define NETIF_FLAG_POINTTOPOINT 0x4U +/** if set, the interface is configured using DHCP */ +#define NETIF_FLAG_DHCP 0x08U +/** if set, the interface has an active link + * (set by the network interface driver) */ +#define NETIF_FLAG_LINK_UP 0x10U + +/** Generic data structure used for all lwIP network interfaces. + * The following fields should be filled in by the initialization + * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ + +struct netif { + /** pointer to next in linked list */ + struct netif *next; + + /** IP address configuration in network byte order */ + struct ip_addr ip_addr; + struct ip_addr netmask; + struct ip_addr gw; + + /** This function is called by the network device driver + * to pass a packet up the TCP/IP stack. */ + err_t (* input)(struct pbuf *p, struct netif *inp); + /** This function is called by the IP module when it wants + * to send a packet on the interface. This function typically + * first resolves the hardware address, then sends the packet. */ + err_t (* output)(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr); + /** This function is called by the ARP module when it wants + * to send a packet on the interface. This function outputs + * the pbuf as-is on the link medium. */ + err_t (* linkoutput)(struct netif *netif, struct pbuf *p); + /** This field can be set by the device driver and could point + * to state information for the device. */ + void *state; +#if LWIP_DHCP + /** the DHCP client state information for this netif */ + struct dhcp *dhcp; +#endif + /** number of bytes used in hwaddr */ + u8_t hwaddr_len; + /** link level hardware address of this interface */ + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + /** maximum transfer unit (in bytes) */ + u16_t mtu; + /** flags (see NETIF_FLAG_ above) */ + u8_t flags; + /** descriptive abbreviation */ + char name[2]; + /** number of this interface */ + u8_t num; +#if LWIP_SNMP + /** link type (ifType values per RFC1213) */ + u8_t link_type; + /** (estimate) link speed */ + u32_t link_speed; + /** timestamp at last change made (up/down) */ + u32_t ts; + /** counters */ + u32_t ifinoctets; + u32_t ifinucastpkts; + u32_t ifinnucastpkts; + u32_t ifindiscards; + u32_t ifoutoctets; + u32_t ifoutucastpkts; + u32_t ifoutnucastpkts; + u32_t ifoutdiscards; +#endif +}; + +/** The list of network interfaces. */ +extern struct netif *netif_list; +/** The default network interface. */ +extern struct netif *netif_default; + +/* netif_init() must be called first. */ +void netif_init(void); + +struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw, + void *state, + err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif)); + +void +netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw); +void netif_remove(struct netif * netif); + +/* Returns a network interface given its name. The name is of the form + "et0", where the first two letters are the "name" field in the + netif structure, and the digit is in the num field in the same + structure. */ +struct netif *netif_find(char *name); + +void netif_set_default(struct netif *netif); + +void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr); +void netif_set_netmask(struct netif *netif, struct ip_addr *netmast); +void netif_set_gw(struct netif *netif, struct ip_addr *gw); +void netif_set_up(struct netif *netif); +void netif_set_down(struct netif *netif); +u8_t netif_is_up(struct netif *netif); + +#endif /* __LWIP_NETIF_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/pbuf.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/pbuf.h new file mode 100644 index 0000000..0b187e1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/pbuf.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_PBUF_H__ +#define __LWIP_PBUF_H__ + +#include "arch/cc.h" + + +#define PBUF_TRANSPORT_HLEN 20 +#define PBUF_IP_HLEN 20 + +typedef enum { + PBUF_TRANSPORT, + PBUF_IP, + PBUF_LINK, + PBUF_RAW +} pbuf_layer; + +typedef enum { + PBUF_RAM, + PBUF_ROM, + PBUF_REF, + PBUF_POOL +} pbuf_flag; + +/* Definitions for the pbuf flag field. These are NOT the flags that + * are passed to pbuf_alloc(). */ +#define PBUF_FLAG_RAM 0x00U /* Flags that pbuf data is stored in RAM */ +#define PBUF_FLAG_ROM 0x01U /* Flags that pbuf data is stored in ROM */ +#define PBUF_FLAG_POOL 0x02U /* Flags that the pbuf comes from the pbuf pool */ +#define PBUF_FLAG_REF 0x04U /* Flags thet the pbuf payload refers to RAM */ + +/** indicates this packet was broadcast on the link */ +#define PBUF_FLAG_LINK_BROADCAST 0x80U + +struct pbuf { + /** next pbuf in singly linked pbuf chain */ + struct pbuf *next; + + /** pointer to the actual data in the buffer */ + void *payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + u16_t tot_len; + + /** length of this buffer */ + u16_t len; + + /** flags telling the type of pbuf, see PBUF_FLAG_ */ + u16_t flags; + + /** + * the reference count always equals the number of pointers + * that refer to this pbuf. This can be pointers from an application, + * the stack itself, or pbuf->next pointers from a chain. + */ + u16_t ref; + +}; + +void pbuf_init(void); + +struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag); +void pbuf_realloc(struct pbuf *p, u16_t size); +u8_t pbuf_header(struct pbuf *p, s16_t header_size); +void pbuf_ref(struct pbuf *p); +void pbuf_ref_chain(struct pbuf *p); +u8_t pbuf_free(struct pbuf *p); +u8_t pbuf_clen(struct pbuf *p); +void pbuf_cat(struct pbuf *h, struct pbuf *t); +void pbuf_chain(struct pbuf *h, struct pbuf *t); +struct pbuf *pbuf_take(struct pbuf *f); +struct pbuf *pbuf_dechain(struct pbuf *p); +void pbuf_queue(struct pbuf *p, struct pbuf *n); +struct pbuf * pbuf_dequeue(struct pbuf *p); + +#endif /* __LWIP_PBUF_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/raw.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/raw.h new file mode 100644 index 0000000..83b32da --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/raw.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_RAW_H__ +#define __LWIP_RAW_H__ + +#include "lwip/arch.h" + +#include "lwip/pbuf.h" +#include "lwip/inet.h" +#include "lwip/ip.h" + +struct raw_pcb { +/* Common members of all PCB types */ + IP_PCB; + + struct raw_pcb *next; + + u16_t protocol; + + u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p, + struct ip_addr *addr); + void *recv_arg; +}; + +/* The following functions is the application layer interface to the + RAW code. */ +struct raw_pcb * raw_new (u16_t proto); +void raw_remove (struct raw_pcb *pcb); +err_t raw_bind (struct raw_pcb *pcb, struct ip_addr *ipaddr); +err_t raw_connect (struct raw_pcb *pcb, struct ip_addr *ipaddr); + +void raw_recv (struct raw_pcb *pcb, + u8_t (* recv)(void *arg, struct raw_pcb *pcb, + struct pbuf *p, + struct ip_addr *addr), + void *recv_arg); +err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr); +err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); + +/* The following functions are the lower layer interface to RAW. */ +u8_t raw_input (struct pbuf *p, struct netif *inp); +void raw_init (void); + + +#endif /* __LWIP_RAW_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/sio.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/sio.h new file mode 100644 index 0000000..5fc28a4 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/sio.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + */ + +/* + * This is the interface to the platform specific serial IO module + * It needs to be implemented by those platforms which need SLIP or PPP + */ + +#include "arch/cc.h" + +#ifndef __sio_fd_t_defined +typedef void * sio_fd_t; +#endif + +#ifndef sio_open +sio_fd_t sio_open(u8_t); +#endif + +#ifndef sio_send +void sio_send(u8_t, sio_fd_t); +#endif + +#ifndef sio_recv +u8_t sio_recv(sio_fd_t); +#endif + +#ifndef sio_read +u32_t sio_read(sio_fd_t, u8_t *, u32_t); +#endif + +#ifndef sio_write +u32_t sio_write(sio_fd_t, u8_t *, u32_t); +#endif + +#ifndef sio_read_abort +void sio_read_abort(sio_fd_t); +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp.h new file mode 100644 index 0000000..987ebd9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2001, 2002 Leon Woestenberg + * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Leon Woestenberg + * + */ +#ifndef __LWIP_SNMP_H__ +#define __LWIP_SNMP_H__ + +#include "lwip/opt.h" +#include "lwip/netif.h" +#include "lwip/udp.h" + +/* SNMP support available? */ +#if defined(LWIP_SNMP) && (LWIP_SNMP > 0) + +/** fixed maximum length for object identifier type */ +#define LWIP_SNMP_OBJ_ID_LEN 32 +/** internal object identifier representation */ +struct snmp_obj_id +{ + u8_t len; + s32_t id[LWIP_SNMP_OBJ_ID_LEN]; +}; + +/* system */ +void snmp_set_sysdesr(u8_t* str, u8_t* strlen); +void snmp_set_sysobjid(struct snmp_obj_id *oid); +void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid); +void snmp_inc_sysuptime(void); +void snmp_get_sysuptime(u32_t *value); +void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen); + +/* network interface */ +void snmp_add_ifinoctets(struct netif *ni, u32_t value); +void snmp_inc_ifinucastpkts(struct netif *ni); +void snmp_inc_ifinnucastpkts(struct netif *ni); +void snmp_inc_ifindiscards(struct netif *ni); +void snmp_add_ifoutoctets(struct netif *ni, u32_t value); +void snmp_inc_ifoutucastpkts(struct netif *ni); +void snmp_inc_ifoutnucastpkts(struct netif *ni); +void snmp_inc_ifoutdiscards(struct netif *ni); +void snmp_inc_iflist(void); +void snmp_dec_iflist(void); + +/* ARP (for atTable and ipNetToMediaTable) */ +void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip); +void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip); + +/* IP */ +void snmp_inc_ipinreceives(void); +void snmp_inc_ipinhdrerrors(void); +void snmp_inc_ipinaddrerrors(void); +void snmp_inc_ipforwdatagrams(void); +void snmp_inc_ipinunknownprotos(void); +void snmp_inc_ipindiscards(void); +void snmp_inc_ipindelivers(void); +void snmp_inc_ipoutrequests(void); +void snmp_inc_ipoutdiscards(void); +void snmp_inc_ipoutnoroutes(void); +void snmp_inc_ipreasmreqds(void); +void snmp_inc_ipreasmoks(void); +void snmp_inc_ipreasmfails(void); +void snmp_inc_ipfragoks(void); +void snmp_inc_ipfragfails(void); +void snmp_inc_ipfragcreates(void); +void snmp_inc_iproutingdiscards(void); +void snmp_insert_ipaddridx_tree(struct netif *ni); +void snmp_delete_ipaddridx_tree(struct netif *ni); +void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni); +void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni); + +/* ICMP */ +void snmp_inc_icmpinmsgs(void); +void snmp_inc_icmpinerrors(void); +void snmp_inc_icmpindestunreachs(void); +void snmp_inc_icmpintimeexcds(void); +void snmp_inc_icmpinparmprobs(void); +void snmp_inc_icmpinsrcquenchs(void); +void snmp_inc_icmpinredirects(void); +void snmp_inc_icmpinechos(void); +void snmp_inc_icmpinechoreps(void); +void snmp_inc_icmpintimestamps(void); +void snmp_inc_icmpintimestampreps(void); +void snmp_inc_icmpinaddrmasks(void); +void snmp_inc_icmpinaddrmaskreps(void); +void snmp_inc_icmpoutmsgs(void); +void snmp_inc_icmpouterrors(void); +void snmp_inc_icmpoutdestunreachs(void); +void snmp_inc_icmpouttimeexcds(void); +void snmp_inc_icmpoutparmprobs(void); +void snmp_inc_icmpoutsrcquenchs(void); +void snmp_inc_icmpoutredirects(void); +void snmp_inc_icmpoutechos(void); +void snmp_inc_icmpoutechoreps(void); +void snmp_inc_icmpouttimestamps(void); +void snmp_inc_icmpouttimestampreps(void); +void snmp_inc_icmpoutaddrmasks(void); +void snmp_inc_icmpoutaddrmaskreps(void); + +/* TCP */ +void snmp_inc_tcpactiveopens(void); +void snmp_inc_tcppassiveopens(void); +void snmp_inc_tcpattemptfails(void); +void snmp_inc_tcpestabresets(void); +void snmp_inc_tcpinsegs(void); +void snmp_inc_tcpoutsegs(void); +void snmp_inc_tcpretranssegs(void); +void snmp_inc_tcpinerrs(void); +void snmp_inc_tcpoutrsts(void); + +/* UDP */ +void snmp_inc_udpindatagrams(void); +void snmp_inc_udpnoports(void); +void snmp_inc_udpinerrors(void); +void snmp_inc_udpoutdatagrams(void); +void snmp_insert_udpidx_tree(struct udp_pcb *pcb); +void snmp_delete_udpidx_tree(struct udp_pcb *pcb); + +/* SNMP */ +void snmp_inc_snmpinpkts(void); +void snmp_inc_snmpoutpkts(void); +void snmp_inc_snmpinbadversions(void); +void snmp_inc_snmpinbadcommunitynames(void); +void snmp_inc_snmpinbadcommunityuses(void); +void snmp_inc_snmpinasnparseerrs(void); +void snmp_inc_snmpintoobigs(void); +void snmp_inc_snmpinnosuchnames(void); +void snmp_inc_snmpinbadvalues(void); +void snmp_inc_snmpinreadonlys(void); +void snmp_inc_snmpingenerrs(void); +void snmp_add_snmpintotalreqvars(u8_t value); +void snmp_add_snmpintotalsetvars(u8_t value); +void snmp_inc_snmpingetrequests(void); +void snmp_inc_snmpingetnexts(void); +void snmp_inc_snmpinsetrequests(void); +void snmp_inc_snmpingetresponses(void); +void snmp_inc_snmpintraps(void); +void snmp_inc_snmpouttoobigs(void); +void snmp_inc_snmpoutnosuchnames(void); +void snmp_inc_snmpoutbadvalues(void); +void snmp_inc_snmpoutgenerrs(void); +void snmp_inc_snmpoutgetrequests(void); +void snmp_inc_snmpoutgetnexts(void); +void snmp_inc_snmpoutsetrequests(void); +void snmp_inc_snmpoutgetresponses(void); +void snmp_inc_snmpouttraps(void); +void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid); +void snmp_set_snmpenableauthentraps(u8_t *value); +void snmp_get_snmpenableauthentraps(u8_t *value); + +/* LWIP_SNMP support not available */ +/* define everything to be empty */ +#else + +/* system */ +#define snmp_set_sysdesr(str, strlen) +#define snmp_get_sysobjid_ptr(oid) +#define snmp_inc_sysuptime() +#define snmp_get_sysuptime(value) + +/* network interface */ +#define snmp_add_ifinoctets(ni,value) +#define snmp_inc_ifinucastpkts(ni) +#define snmp_inc_ifinnucastpkts(ni) +#define snmp_inc_ifindiscards(ni) +#define snmp_add_ifoutoctets(ni,value) +#define snmp_inc_ifoutucastpkts(ni) +#define snmp_inc_ifoutnucastpkts(ni) +#define snmp_inc_ifoutdiscards(ni) +#define snmp_inc_iflist() +#define snmp_dec_iflist() + +/* ARP */ +#define snmp_insert_arpidx_tree(ni,ip) +#define snmp_delete_arpidx_tree(ni,ip) + +/* IP */ +#define snmp_inc_ipinreceives() +#define snmp_inc_ipinhdrerrors() +#define snmp_inc_ipinaddrerrors() +#define snmp_inc_ipforwdatagrams() +#define snmp_inc_ipinunknownprotos() +#define snmp_inc_ipindiscards() +#define snmp_inc_ipindelivers() +#define snmp_inc_ipoutrequests() +#define snmp_inc_ipoutdiscards() +#define snmp_inc_ipoutnoroutes() +#define snmp_inc_ipreasmreqds() +#define snmp_inc_ipreasmoks() +#define snmp_inc_ipreasmfails() +#define snmp_inc_ipfragoks() +#define snmp_inc_ipfragfails() +#define snmp_inc_ipfragcreates() +#define snmp_inc_iproutingdiscards() +#define snmp_insert_ipaddridx_tree(ni) +#define snmp_delete_ipaddridx_tree(ni) +#define snmp_insert_iprteidx_tree(dflt, ni) +#define snmp_delete_iprteidx_tree(dflt, ni) + +/* ICMP */ +#define snmp_inc_icmpinmsgs() +#define snmp_inc_icmpinerrors() +#define snmp_inc_icmpindestunreachs() +#define snmp_inc_icmpintimeexcds() +#define snmp_inc_icmpinparmprobs() +#define snmp_inc_icmpinsrcquenchs() +#define snmp_inc_icmpinredirects() +#define snmp_inc_icmpinechos() +#define snmp_inc_icmpinechoreps() +#define snmp_inc_icmpintimestamps() +#define snmp_inc_icmpintimestampreps() +#define snmp_inc_icmpinaddrmasks() +#define snmp_inc_icmpinaddrmaskreps() +#define snmp_inc_icmpoutmsgs() +#define snmp_inc_icmpouterrors() +#define snmp_inc_icmpoutdestunreachs() +#define snmp_inc_icmpouttimeexcds() +#define snmp_inc_icmpoutparmprobs() +#define snmp_inc_icmpoutsrcquenchs() +#define snmp_inc_icmpoutredirects() +#define snmp_inc_icmpoutechos() +#define snmp_inc_icmpoutechoreps() +#define snmp_inc_icmpouttimestamps() +#define snmp_inc_icmpouttimestampreps() +#define snmp_inc_icmpoutaddrmasks() +#define snmp_inc_icmpoutaddrmaskreps() +/* TCP */ +#define snmp_inc_tcpactiveopens() +#define snmp_inc_tcppassiveopens() +#define snmp_inc_tcpattemptfails() +#define snmp_inc_tcpestabresets() +#define snmp_inc_tcpinsegs() +#define snmp_inc_tcpoutsegs() +#define snmp_inc_tcpretranssegs() +#define snmp_inc_tcpinerrs() +#define snmp_inc_tcpoutrsts() + +/* UDP */ +#define snmp_inc_udpindatagrams() +#define snmp_inc_udpnoports() +#define snmp_inc_udpinerrors() +#define snmp_inc_udpoutdatagrams() +#define snmp_insert_udpidx_tree(pcb) +#define snmp_delete_udpidx_tree(pcb) + +/* SNMP */ +#define snmp_inc_snmpinpkts() +#define snmp_inc_snmpoutpkts() +#define snmp_inc_snmpinbadversions() +#define snmp_inc_snmpinbadcommunitynames() +#define snmp_inc_snmpinbadcommunityuses() +#define snmp_inc_snmpinasnparseerrs() +#define snmp_inc_snmpintoobigs() +#define snmp_inc_snmpinnosuchnames() +#define snmp_inc_snmpinbadvalues() +#define snmp_inc_snmpinreadonlys() +#define snmp_inc_snmpingenerrs() +#define snmp_add_snmpintotalreqvars(value) +#define snmp_add_snmpintotalsetvars(value) +#define snmp_inc_snmpingetrequests() +#define snmp_inc_snmpingetnexts() +#define snmp_inc_snmpinsetrequests() +#define snmp_inc_snmpingetresponses() +#define snmp_inc_snmpintraps() +#define snmp_inc_snmpouttoobigs() +#define snmp_inc_snmpoutnosuchnames() +#define snmp_inc_snmpoutbadvalues() +#define snmp_inc_snmpoutgenerrs() +#define snmp_inc_snmpoutgetrequests() +#define snmp_inc_snmpoutgetnexts() +#define snmp_inc_snmpoutsetrequests() +#define snmp_inc_snmpoutgetresponses() +#define snmp_inc_snmpouttraps() +#define snmp_get_snmpgrpid_ptr(oid) +#define snmp_set_snmpenableauthentraps(value) +#define snmp_get_snmpenableauthentraps(value) + +#endif + +#endif /* __LWIP_SNMP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp_asn1.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp_asn1.h new file mode 100644 index 0000000..d83d41d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp_asn1.h @@ -0,0 +1,90 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) codec. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_ASN1_H__ +#define __LWIP_SNMP_ASN1_H__ + +#include "lwip/opt.h" +#include "arch/cc.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/snmp.h" + +#define SNMP_ASN1_UNIV (!0x80 | !0x40) +#define SNMP_ASN1_APPLIC (!0x80 | 0x40) +#define SNMP_ASN1_CONTXT ( 0x80 | !0x40) + +#define SNMP_ASN1_CONSTR (0x20) +#define SNMP_ASN1_PRIMIT (!0x20) + +/* universal tags */ +#define SNMP_ASN1_INTEG 2 +#define SNMP_ASN1_OC_STR 4 +#define SNMP_ASN1_NUL 5 +#define SNMP_ASN1_OBJ_ID 6 +#define SNMP_ASN1_SEQ 16 + +/* application specific (SNMP) tags */ +#define SNMP_ASN1_IPADDR 0 /* octet string size(4) */ +#define SNMP_ASN1_COUNTER 1 /* u32_t */ +#define SNMP_ASN1_GAUGE 2 /* u32_t */ +#define SNMP_ASN1_TIMETICKS 3 /* u32_t */ +#define SNMP_ASN1_OPAQUE 4 /* octet string */ + +/* context specific (SNMP) tags */ +#define SNMP_ASN1_PDU_GET_REQ 0 +#define SNMP_ASN1_PDU_GET_NEXT_REQ 1 +#define SNMP_ASN1_PDU_GET_RESP 2 +#define SNMP_ASN1_PDU_SET_REQ 3 +#define SNMP_ASN1_PDU_TRAP 4 + +err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type); +err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length); +err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value); +err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value); +err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid); +err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw); + +void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed); +void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed); +void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed); +void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed); +err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type); +err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length); +err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value); +err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value); +err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident); +err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp_msg.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp_msg.h new file mode 100644 index 0000000..4d91d30 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp_msg.h @@ -0,0 +1,292 @@ +/** + * @file + * SNMP Agent message handling structures. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_MSG_H__ +#define __LWIP_SNMP_MSG_H__ + +#include "lwip/opt.h" +#include "arch/cc.h" +#include "lwip/snmp.h" +#include "lwip/snmp_structs.h" + +#if SNMP_PRIVATE_MIB +#include "private_mib.h" +#endif + +#define SNMP_IN_PORT 161 +#define SNMP_TRAP_PORT 162 + +#define SNMP_ES_NOERROR 0 +#define SNMP_ES_TOOBIG 1 +#define SNMP_ES_NOSUCHNAME 2 +#define SNMP_ES_BADVALUE 3 +#define SNMP_ES_READONLY 4 +#define SNMP_ES_GENERROR 5 + +#define SNMP_GENTRAP_COLDSTART 0 +#define SNMP_GENTRAP_WARMSTART 1 +#define SNMP_GENTRAP_AUTHFAIL 4 +#define SNMP_GENTRAP_ENTERPRISESPC 6 + +struct snmp_varbind +{ + /* next pointer, NULL for last in list */ + struct snmp_varbind *next; + /* previous pointer, NULL for first in list */ + struct snmp_varbind *prev; + + /* object identifier length (in s32_t) */ + u8_t ident_len; + /* object identifier array */ + s32_t *ident; + + /* object value ASN1 type */ + u8_t value_type; + /* object value length (in u8_t) */ + u8_t value_len; + /* object value */ + void *value; + + /* encoding varbind seq length length */ + u8_t seqlenlen; + /* encoding object identifier length length */ + u8_t olenlen; + /* encoding object value length length */ + u8_t vlenlen; + /* encoding varbind seq length */ + u16_t seqlen; + /* encoding object identifier length */ + u16_t olen; + /* encoding object value length */ + u16_t vlen; +}; + +struct snmp_varbind_root +{ + struct snmp_varbind *head; + struct snmp_varbind *tail; + /* number of variable bindings in list */ + u8_t count; + /* encoding varbind-list seq length length */ + u8_t seqlenlen; + /* encoding varbind-list seq length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_resp_header_lengths +{ + /* encoding error-index length length */ + u8_t erridxlenlen; + /* encoding error-status length length */ + u8_t errstatlenlen; + /* encoding request id length length */ + u8_t ridlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding error-index length */ + u16_t erridxlen; + /* encoding error-status length */ + u16_t errstatlen; + /* encoding request id length */ + u16_t ridlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_trap_header_lengths +{ + /* encoding timestamp length length */ + u8_t tslenlen; + /* encoding specific-trap length length */ + u8_t strplenlen; + /* encoding generic-trap length length */ + u8_t gtrplenlen; + /* encoding agent-addr length length */ + u8_t aaddrlenlen; + /* encoding enterprise-id length length */ + u8_t eidlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding timestamp length */ + u16_t tslen; + /* encoding specific-trap length */ + u16_t strplen; + /* encoding generic-trap length */ + u16_t gtrplen; + /* encoding agent-addr length */ + u16_t aaddrlen; + /* encoding enterprise-id length */ + u16_t eidlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/* Accepting new SNMP messages. */ +#define SNMP_MSG_EMPTY 0 +/* Search for matching object for variable binding. */ +#define SNMP_MSG_SEARCH_OBJ 1 +/* Perform SNMP operation on in-memory object. + Pass-through states, for symmetry only. */ +#define SNMP_MSG_INTERNAL_GET_OBJDEF 2 +#define SNMP_MSG_INTERNAL_GET_VALUE 3 +#define SNMP_MSG_INTERNAL_SET_TEST 4 +#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5 +#define SNMP_MSG_INTERNAL_SET_VALUE 6 +/* Perform SNMP operation on object located externally. + In theory this could be used for building a proxy agent. + Practical use is for an enterprise spc. app. gateway. */ +#define SNMP_MSG_EXTERNAL_GET_OBJDEF 7 +#define SNMP_MSG_EXTERNAL_GET_VALUE 8 +#define SNMP_MSG_EXTERNAL_SET_TEST 9 +#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10 +#define SNMP_MSG_EXTERNAL_SET_VALUE 11 + +#define SNMP_COMMUNITY_STR_LEN 64 +struct snmp_msg_pstat +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* source IP address */ + struct ip_addr sip; + /* source UDP port */ + u16_t sp; + /* request type */ + u8_t rt; + /* request ID */ + s32_t rid; + /* error status */ + s32_t error_status; + /* error index */ + s32_t error_index; + /* community name (zero terminated) */ + u8_t community[SNMP_COMMUNITY_STR_LEN + 1]; + /* community string length (exclusive zero term) */ + u8_t com_strlen; + /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */ + u8_t state; + /* saved arguments for MSG_EXTERNAL_x */ + struct mib_external_node *ext_mib_node; + struct snmp_name_ptr ext_name_ptr; + struct obj_def ext_object_def; + struct snmp_obj_id ext_oid; + /* index into input variable binding list */ + u8_t vb_idx; + /* ptr into input variable binding list */ + struct snmp_varbind *vb_ptr; + /* list of variable bindings from input */ + struct snmp_varbind_root invb; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output response lengths used in ASN encoding */ + struct snmp_resp_header_lengths rhl; +}; + +struct snmp_msg_trap +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* destination IP address in network order */ + struct ip_addr dip; + + /* source enterprise ID (sysObjectID) */ + struct snmp_obj_id *enterprise; + /* source IP address, raw network order format */ + u8_t sip_raw[4]; + /* generic trap code */ + u32_t gen_trap; + /* specific trap code */ + u32_t spc_trap; + /* timestamp */ + u32_t ts; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output trap lengths used in ASN encoding */ + struct snmp_trap_header_lengths thl; +}; + +/** Agent Version constant, 0 = v1 oddity */ +extern const s32_t snmp_version; +/** Agent default "public" community string */ +extern const char snmp_publiccommunity[7]; + +extern struct snmp_msg_trap trap_msg; + +/** Agent setup, start listening to port 161. */ +void snmp_init(void); +void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable); +void snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst); + +/** Varbind-list functions. */ +struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len); +void snmp_varbind_free(struct snmp_varbind *vb); +void snmp_varbind_list_free(struct snmp_varbind_root *root); +void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb); +struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root); + +/** Handle an internal (recv) or external (private response) event. */ +void snmp_msg_event(u8_t request_id); +err_t snmp_send_response(struct snmp_msg_pstat *m_stat); +err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap); +void snmp_coldstart_trap(void); +void snmp_authfail_trap(void); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp_structs.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp_structs.h new file mode 100644 index 0000000..f76632e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/snmp_structs.h @@ -0,0 +1,253 @@ +/** + * @file + * Generic MIB tree structures. + * + * @todo namespace prefixes + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_STRUCTS_H__ +#define __LWIP_SNMP_STRUCTS_H__ + +#include "lwip/opt.h" +#if LWIP_SNMP + +#include "arch/cc.h" +#include "lwip/snmp.h" + +#if SNMP_PRIVATE_MIB +#include "private_mib.h" +#endif + +/* MIB object instance */ +#define MIB_OBJECT_NONE 0 +#define MIB_OBJECT_SCALAR 1 +#define MIB_OBJECT_TAB 2 + +/* MIB object access */ +#define MIB_OBJECT_READ_ONLY 0 +#define MIB_OBJECT_READ_WRITE 1 +#define MIB_OBJECT_WRITE_ONLY 2 +#define MIB_OBJECT_NOT_ACCESSIBLE 3 + +/** object definition returned by (get_object_def)() */ +struct obj_def +{ + /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */ + u8_t instance; + /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */ + u8_t access; + /* ASN type for this object */ + u8_t asn_type; + /* value length (host length) */ + u16_t v_len; + /* length of instance part of supplied object identifier */ + u8_t id_inst_len; + /* instance part of supplied object identifier */ + s32_t *id_inst_ptr; +}; + +struct snmp_name_ptr +{ + u8_t ident_len; + s32_t *ident; +}; + +/** MIB const scalar (.0) node */ +#define MIB_NODE_SC 0x01 +/** MIB const array node */ +#define MIB_NODE_AR 0x02 +/** MIB array node (mem_malloced from RAM) */ +#define MIB_NODE_RA 0x03 +/** MIB list root node (mem_malloced from RAM) */ +#define MIB_NODE_LR 0x04 +/** MIB node for external objects */ +#define MIB_NODE_EX 0x05 + +/** node "base class" layout, the mandatory fields for a node */ +struct mib_node +{ + /** returns struct obj_def for the given object identifier */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + /** returns object value for the given object identifier, + @note the caller must allocate at least len bytes for the value */ + void (*get_value)(struct obj_def *od, u16_t len, void *value); + /** tests length and/or range BEFORE setting */ + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + /** sets object value, only to be called when set_test() */ + void (*set_value)(struct obj_def *od, u16_t len, void *value); + /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */ + const u8_t node_type; + /* array or max list length */ + const u16_t maxlength; +}; + +/** derived node for scalars .0 index */ +typedef struct mib_node mib_scalar_node; + +/** derived node, points to a fixed size const array + of sub-identifiers plus a 'child' pointer */ +struct mib_array_node +{ + /* inherited "base class" members */ + void (* const get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (* const get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + const u8_t node_type; + const u16_t maxlength; + + /* aditional struct members */ + const s32_t *objid; + struct mib_node* const *nptr; +}; + +/** derived node, points to a fixed size mem_malloced array + of sub-identifiers plus a 'child' pointer */ +struct mib_ram_array_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + s32_t *objid; + struct mib_node **nptr; +}; + +struct mib_list_node +{ + struct mib_list_node *prev; + struct mib_list_node *next; + s32_t objid; + struct mib_node *nptr; +}; + +/** derived node, points to a doubly linked list + of sub-identifiers plus a 'child' pointer */ +struct mib_list_rootnode +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + struct mib_list_node *head; + struct mib_list_node *tail; + /* counts list nodes in list */ + u16_t count; +}; + +/** derived node, has access functions for mib object in external memory or device + using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */ +struct mib_external_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + /** points to an extenal (in memory) record of some sort of addressing + information, passed to and interpreted by the funtions below */ + void* addr_inf; + /** tree levels under this node */ + u8_t tree_levels; + /** number of objects at this level */ + u16_t (*level_length)(void* addr_inf, u8_t level); + /** compares object sub identifier with external id + return zero when equal, nonzero when unequal */ + s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id); + void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id); + + /** async Questions */ + void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_q)(u8_t rid, struct obj_def *od); + void (*set_test_q)(u8_t rid, struct obj_def *od); + void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Answers */ + void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Panic Close (agent returns error reply, + e.g. used for external transaction cleanup) */ + void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_pc)(u8_t rid, struct obj_def *od); + void (*set_test_pc)(u8_t rid, struct obj_def *od); + void (*set_value_pc)(u8_t rid, struct obj_def *od); +}; + +/** export MIB tree from mib2.c */ +extern const struct mib_array_node internet; + +/** dummy function pointers for non-leaf MIB nodes from mib2.c */ +void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +void noleafs_get_value(struct obj_def *od, u16_t len, void *value); +u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value); +void noleafs_set_value(struct obj_def *od, u16_t len, void *value); + +void snmp_oidtoip(s32_t *ident, struct ip_addr *ip); +void snmp_iptooid(struct ip_addr *ip, s32_t *ident); +void snmp_ifindextonetif(s32_t ifindex, struct netif **netif); +void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx); + +struct mib_list_node* snmp_mib_ln_alloc(s32_t id); +void snmp_mib_ln_free(struct mib_list_node *ln); +struct mib_list_rootnode* snmp_mib_lrn_alloc(void); +void snmp_mib_lrn_free(struct mib_list_rootnode *lrn); + +s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn); +s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn); +struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n); + +struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np); +struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); +u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident); +u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); + +#endif /* LWIP_SNMP */ +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/sockets.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/sockets.h new file mode 100644 index 0000000..9c25035 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/sockets.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +#ifndef __LWIP_SOCKETS_H__ +#define __LWIP_SOCKETS_H__ +#include "lwip/ip_addr.h" + +struct sockaddr_in { + u8_t sin_len; + u8_t sin_family; + u16_t sin_port; + struct in_addr sin_addr; + char sin_zero[8]; +}; + +struct sockaddr { + u8_t sa_len; + u8_t sa_family; + char sa_data[14]; +}; + +#ifndef socklen_t +# define socklen_t int +#endif + + +#define SOCK_STREAM 1 +#define SOCK_DGRAM 2 +#define SOCK_RAW 3 + +/* + * Option flags per-socket. + */ +#define SO_DEBUG 0x0001 /* turn on debugging info recording */ +#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ +#define SO_REUSEADDR 0x0004 /* allow local address reuse */ +#define SO_KEEPALIVE 0x0008 /* keep connections alive */ +#define SO_DONTROUTE 0x0010 /* just use interface addresses */ +#define SO_BROADCAST 0x0020 /* permit sending of broadcast msgs */ +#define SO_USELOOPBACK 0x0040 /* bypass hardware when possible */ +#define SO_LINGER 0x0080 /* linger on close if data present */ +#define SO_OOBINLINE 0x0100 /* leave received OOB data in line */ +#define SO_REUSEPORT 0x0200 /* allow local address & port reuse */ + +#define SO_DONTLINGER (int)(~SO_LINGER) + +/* + * Additional options, not kept in so_options. + */ +#define SO_SNDBUF 0x1001 /* send buffer size */ +#define SO_RCVBUF 0x1002 /* receive buffer size */ +#define SO_SNDLOWAT 0x1003 /* send low-water mark */ +#define SO_RCVLOWAT 0x1004 /* receive low-water mark */ +#define SO_SNDTIMEO 0x1005 /* send timeout */ +#define SO_RCVTIMEO 0x1006 /* receive timeout */ +#define SO_ERROR 0x1007 /* get error status and clear */ +#define SO_TYPE 0x1008 /* get socket type */ + + + +/* + * Structure used for manipulating linger option. + */ +struct linger { + int l_onoff; /* option on/off */ + int l_linger; /* linger time */ +}; + +/* + * Level number for (get/set)sockopt() to apply to socket itself. + */ +#define SOL_SOCKET 0xfff /* options for socket level */ + + +#define AF_UNSPEC 0 +#define AF_INET 2 +#define PF_INET AF_INET +#define PF_UNSPEC AF_UNSPEC + +#define IPPROTO_IP 0 +#define IPPROTO_TCP 6 +#define IPPROTO_UDP 17 + +#define INADDR_ANY 0 +#define INADDR_BROADCAST 0xffffffff + +/* Flags we can use with send and recv. */ +#define MSG_DONTWAIT 0x40 /* Nonblocking i/o for this operation only */ + + +/* + * Options for level IPPROTO_IP + */ +#define IP_TOS 1 +#define IP_TTL 2 + + +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_LOWCOST 0x02 +#define IPTOS_MINCOST IPTOS_LOWCOST + +/* + * Definitions for IP precedence (also in ip_tos) (hopefully unused) + */ +#define IPTOS_PREC_MASK 0xe0 +#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + + +/* + * Commands for ioctlsocket(), taken from the BSD file fcntl.h. + * + * + * Ioctl's have the command encoded in the lower word, + * and the size of any in or out parameters in the upper + * word. The high 2 bits of the upper word are used + * to encode the in/out status of the parameter; for now + * we restrict parameters to at most 128 bytes. + */ +#if !defined(FIONREAD) || !defined(FIONBIO) +#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */ +#define IOC_VOID 0x20000000 /* no parameters */ +#define IOC_OUT 0x40000000 /* copy out parameters */ +#define IOC_IN 0x80000000 /* copy in parameters */ +#define IOC_INOUT (IOC_IN|IOC_OUT) + /* 0x20000000 distinguishes new & + old ioctl's */ +#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) + +#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) + +#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) +#endif + +#ifndef FIONREAD +#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ +#endif +#ifndef FIONBIO +#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ +#endif + +/* Socket I/O Controls */ +#ifndef SIOCSHIWAT +#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ +#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ +#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ +#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ +#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ +#endif + +#ifndef O_NONBLOCK +#define O_NONBLOCK 04000U +#endif + +#ifndef FD_SET + #undef FD_SETSIZE + #define FD_SETSIZE 16 + #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7))) + #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7))) + #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7))) + #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p))) + + typedef struct fd_set { + unsigned char fd_bits [(FD_SETSIZE+7)/8]; + } fd_set; + +/* + * only define this in sockets.c so it does not interfere + * with other projects namespaces where timeval is present + */ +#ifndef LWIP_TIMEVAL_PRIVATE +#define LWIP_TIMEVAL_PRIVATE 1 +#endif + +#if LWIP_TIMEVAL_PRIVATE + struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ + }; +#endif + +#endif + +int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); +int lwip_bind(int s, struct sockaddr *name, socklen_t namelen); +int lwip_shutdown(int s, int how); +int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); +int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); +int lwip_close(int s); +int lwip_connect(int s, struct sockaddr *name, socklen_t namelen); +int lwip_listen(int s, int backlog); +int lwip_recv(int s, void *mem, int len, unsigned int flags); +int lwip_read(int s, void *mem, int len); +int lwip_recvfrom(int s, void *mem, int len, unsigned int flags, + struct sockaddr *from, socklen_t *fromlen); +int lwip_send(int s, void *dataptr, int size, unsigned int flags); +int lwip_sendto(int s, void *dataptr, int size, unsigned int flags, + struct sockaddr *to, socklen_t tolen); +int lwip_socket(int domain, int type, int protocol); +int lwip_write(int s, void *dataptr, int size); +int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout); +int lwip_ioctl(int s, long cmd, void *argp); + +#if LWIP_COMPAT_SOCKETS +#define accept(a,b,c) lwip_accept(a,b,c) +#define bind(a,b,c) lwip_bind(a,b,c) +#define shutdown(a,b) lwip_shutdown(a,b) +#define close(s) lwip_close(s) +#define connect(a,b,c) lwip_connect(a,b,c) +#define getsockname(a,b,c) lwip_getsockname(a,b,c) +#define getpeername(a,b,c) lwip_getpeername(a,b,c) +#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e) +#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e) +#define listen(a,b) lwip_listen(a,b) +#define recv(a,b,c,d) lwip_recv(a,b,c,d) +#define read(a,b,c) lwip_read(a,b,c) +#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f) +#define send(a,b,c,d) lwip_send(a,b,c,d) +#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f) +#define socket(a,b,c) lwip_socket(a,b,c) +#define write(a,b,c) lwip_write(a,b,c) +#define select(a,b,c,d,e) lwip_select(a,b,c,d,e) +#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c) +#endif /* LWIP_COMPAT_SOCKETS */ + +#endif /* __LWIP_SOCKETS_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/stats.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/stats.h new file mode 100644 index 0000000..29dfd57 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/stats.h @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_STATS_H__ +#define __LWIP_STATS_H__ + +#include "lwip/opt.h" +#include "arch/cc.h" + +#include "lwip/mem.h" +#include "lwip/memp.h" + +#if LWIP_STATS + +struct stats_proto { + u16_t xmit; /* Transmitted packets. */ + u16_t rexmit; /* Retransmitted packets. */ + u16_t recv; /* Received packets. */ + u16_t fw; /* Forwarded packets. */ + u16_t drop; /* Dropped packets. */ + u16_t chkerr; /* Checksum error. */ + u16_t lenerr; /* Invalid length error. */ + u16_t memerr; /* Out of memory error. */ + u16_t rterr; /* Routing error. */ + u16_t proterr; /* Protocol error. */ + u16_t opterr; /* Error in options. */ + u16_t err; /* Misc error. */ + u16_t cachehit; +}; + +struct stats_mem { + mem_size_t avail; + mem_size_t used; + mem_size_t max; + mem_size_t err; +}; + +struct stats_pbuf { + u16_t avail; + u16_t used; + u16_t max; + u16_t err; + + u16_t alloc_locked; + u16_t refresh_locked; +}; + +struct stats_syselem { + u16_t used; + u16_t max; + u16_t err; +}; + +struct stats_sys { + struct stats_syselem sem; + struct stats_syselem mbox; +}; + +struct stats_ { + struct stats_proto link; + struct stats_proto ip_frag; + struct stats_proto ip; + struct stats_proto icmp; + struct stats_proto udp; + struct stats_proto tcp; + struct stats_pbuf pbuf; + struct stats_mem mem; + struct stats_mem memp[MEMP_MAX]; + struct stats_sys sys; +}; + +extern struct stats_ lwip_stats; + + +void stats_init(void); + +#define STATS_INC(x) ++lwip_stats.x +#else +#define stats_init() +#define STATS_INC(x) +#endif /* LWIP_STATS */ + +#if TCP_STATS +#define TCP_STATS_INC(x) STATS_INC(x) +#else +#define TCP_STATS_INC(x) +#endif + +#if UDP_STATS +#define UDP_STATS_INC(x) STATS_INC(x) +#else +#define UDP_STATS_INC(x) +#endif + +#if ICMP_STATS +#define ICMP_STATS_INC(x) STATS_INC(x) +#else +#define ICMP_STATS_INC(x) +#endif + +#if IP_STATS +#define IP_STATS_INC(x) STATS_INC(x) +#else +#define IP_STATS_INC(x) +#endif + +#if IPFRAG_STATS +#define IPFRAG_STATS_INC(x) STATS_INC(x) +#else +#define IPFRAG_STATS_INC(x) +#endif + +#if LINK_STATS +#define LINK_STATS_INC(x) STATS_INC(x) +#else +#define LINK_STATS_INC(x) +#endif + +/* Display of statistics */ +#if LWIP_STATS_DISPLAY +void stats_display(void); +#else +#define stats_display() +#endif + +#endif /* __LWIP_STATS_H__ */ + + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/sys.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/sys.h new file mode 100644 index 0000000..ce8d5ff --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/sys.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_SYS_H__ +#define __LWIP_SYS_H__ + +#include "arch/cc.h" + +#include "lwip/opt.h" + + +#if NO_SYS + +/* For a totally minimal and standalone system, we provide null + definitions of the sys_ functions. */ +typedef u8_t sys_sem_t; +typedef u8_t sys_mbox_t; +struct sys_timeo {u8_t dummy;}; + +#define sys_init() +#define sys_timeout(m,h,a) +#define sys_untimeout(m,a) +#define sys_sem_new(c) c +#define sys_sem_signal(s) +#define sys_sem_wait(s) +#define sys_sem_free(s) +#define sys_mbox_new() 0 +#define sys_mbox_fetch(m,d) +#define sys_mbox_post(m,d) +#define sys_mbox_free(m) + +#define sys_thread_new(t,a,p) + +#else /* NO_SYS */ + +#include "arch/sys_arch.h" + +/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ +#define SYS_ARCH_TIMEOUT 0xffffffff + +typedef void (* sys_timeout_handler)(void *arg); + +struct sys_timeo { + struct sys_timeo *next; + u32_t time; + sys_timeout_handler h; + void *arg; +}; + +struct sys_timeouts { + struct sys_timeo *next; +}; + +/* sys_init() must be called before anthing else. */ +void sys_init(void); + +/* + * sys_timeout(): + * + * Schedule a timeout a specified amount of milliseconds in the + * future. When the timeout occurs, the specified timeout handler will + * be called. The handler will be passed the "arg" argument when + * called. + * + */ +void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg); +void sys_untimeout(sys_timeout_handler h, void *arg); +struct sys_timeouts *sys_arch_timeouts(void); + +/* Semaphore functions. */ +sys_sem_t sys_sem_new(u8_t count); +void sys_sem_signal(sys_sem_t sem); +u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout); +void sys_sem_free(sys_sem_t sem); +void sys_sem_wait(sys_sem_t sem); +int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout); + +/* Time functions. */ +#ifndef sys_msleep +void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */ +#endif +#ifndef sys_jiffies +u32_t sys_jiffies(void); /* since power up. */ +#endif + +/* Mailbox functions. */ +sys_mbox_t sys_mbox_new(void); +void sys_mbox_post(sys_mbox_t mbox, void *msg); +u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout); +void sys_mbox_free(sys_mbox_t mbox); +void sys_mbox_fetch(sys_mbox_t mbox, void **msg); + + +/* Thread functions. */ +sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio); + +/* The following functions are used only in Unix code, and + can be omitted when porting the stack. */ +/* Returns the current time in microseconds. */ +unsigned long sys_now(void); + +#endif /* NO_SYS */ + +/* Critical Region Protection */ +/* These functions must be implemented in the sys_arch.c file. + In some implementations they can provide a more light-weight protection + mechanism than using semaphores. Otherwise semaphores can be used for + implementation */ +#ifndef SYS_ARCH_PROTECT +/** SYS_LIGHTWEIGHT_PROT + * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#if SYS_LIGHTWEIGHT_PROT + +/** SYS_ARCH_DECL_PROTECT + * declare a protection variable. This macro will default to defining a variable of + * type sys_prot_t. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h. + */ +#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev +/** SYS_ARCH_PROTECT + * Perform a "fast" protect. This could be implemented by + * disabling interrupts for an embedded system or by using a semaphore or + * mutex. The implementation should allow calling SYS_ARCH_PROTECT when + * already protected. The old protection level is returned in the variable + * "lev". This macro will default to calling the sys_arch_protect() function + * which should be implemented in sys_arch.c. If a particular port needs a + * different implementation, then this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() +/** SYS_ARCH_UNPROTECT + * Perform a "fast" set of the protection level to "lev". This could be + * implemented by setting the interrupt level to "lev" within the MACRO or by + * using a semaphore or mutex. This macro will default to calling the + * sys_arch_unprotect() function which should be implemented in + * sys_arch.c. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) +sys_prot_t sys_arch_protect(void); +void sys_arch_unprotect(sys_prot_t pval); + +#else + +#define SYS_ARCH_DECL_PROTECT(lev) +#define SYS_ARCH_PROTECT(lev) +#define SYS_ARCH_UNPROTECT(lev) + +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#endif /* SYS_ARCH_PROTECT */ + +#endif /* __LWIP_SYS_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/tcp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/tcp.h new file mode 100644 index 0000000..b4f78bf --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/tcp.h @@ -0,0 +1,531 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCP_H__ +#define __LWIP_TCP_H__ + +#include "lwip/sys.h" +#include "lwip/mem.h" + +#include "lwip/pbuf.h" +#include "lwip/opt.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" + +#include "lwip/err.h" + +struct tcp_pcb; + +/* Functions for interfacing with TCP: */ + +/* Lower layer interface to TCP: */ +void tcp_init (void); /* Must be called first to + initialize TCP. */ +void tcp_tmr (void); /* Must be called every + TCP_TMR_INTERVAL + ms. (Typically 250 ms). */ +/* Application program's interface: */ +struct tcp_pcb * tcp_new (void); +struct tcp_pcb * tcp_alloc (u8_t prio); + +void tcp_arg (struct tcp_pcb *pcb, void *arg); +void tcp_accept (struct tcp_pcb *pcb, + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, + err_t err)); +void tcp_recv (struct tcp_pcb *pcb, + err_t (* recv)(void *arg, struct tcp_pcb *tpcb, + struct pbuf *p, err_t err)); +void tcp_sent (struct tcp_pcb *pcb, + err_t (* sent)(void *arg, struct tcp_pcb *tpcb, + u16_t len)); +void tcp_poll (struct tcp_pcb *pcb, + err_t (* poll)(void *arg, struct tcp_pcb *tpcb), + u8_t interval); +void tcp_err (struct tcp_pcb *pcb, + void (* err)(void *arg, err_t err)); + +#define tcp_mss(pcb) ((pcb)->mss) +#define tcp_sndbuf(pcb) ((pcb)->snd_buf) + +void tcp_recved (struct tcp_pcb *pcb, u16_t len); +err_t tcp_bind (struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +err_t tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port, err_t (* connected)(void *arg, + struct tcp_pcb *tpcb, + err_t err)); +struct tcp_pcb * tcp_listen (struct tcp_pcb *pcb); +void tcp_abort (struct tcp_pcb *pcb); +err_t tcp_close (struct tcp_pcb *pcb); +err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, + u8_t copy); + +void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); + +#define TCP_PRIO_MIN 1 +#define TCP_PRIO_NORMAL 64 +#define TCP_PRIO_MAX 127 + +/* It is also possible to call these two functions at the right + intervals (instead of calling tcp_tmr()). */ +void tcp_slowtmr (void); +void tcp_fasttmr (void); + + +/* Only used by IP to pass a TCP segment to TCP: */ +void tcp_input (struct pbuf *p, struct netif *inp); +/* Used within the TCP code only: */ +err_t tcp_output (struct tcp_pcb *pcb); +void tcp_rexmit (struct tcp_pcb *pcb); +void tcp_rexmit_rto (struct tcp_pcb *pcb); + + + +#define TCP_SEQ_LT(a,b) ((s32_t)((a)-(b)) < 0) +#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0) +#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0) +#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0) +/* is b<=a<=c? */ +#if 0 /* see bug #10548 */ +#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) +#endif +#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) +#define TCP_FIN 0x01U +#define TCP_SYN 0x02U +#define TCP_RST 0x04U +#define TCP_PSH 0x08U +#define TCP_ACK 0x10U +#define TCP_URG 0x20U +#define TCP_ECE 0x40U +#define TCP_CWR 0x80U + +#define TCP_FLAGS 0x3fU + +/* Length of the TCP header, excluding options. */ +#define TCP_HLEN 20 + +#ifndef TCP_TMR_INTERVAL +#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in + milliseconds. */ +#endif /* TCP_TMR_INTERVAL */ + +#ifndef TCP_FAST_INTERVAL +#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in + milliseconds */ +#endif /* TCP_FAST_INTERVAL */ + +#ifndef TCP_SLOW_INTERVAL +#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in + milliseconds */ +#endif /* TCP_SLOW_INTERVAL */ + +#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ +#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ + +#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */ + +#define TCP_MSL 60000 /* The maximum segment lifetime in microseconds */ + +/* + * User-settable options (used with setsockopt). + */ +#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ +#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */ + +/* Keepalive values */ +#define TCP_KEEPDEFAULT 7200000 /* KEEPALIVE timer in miliseconds */ +#define TCP_KEEPINTVL 75000 /* Time between KEEPALIVE probes in miliseconds */ +#define TCP_KEEPCNT 9 /* Counter for KEEPALIVE probes */ +#define TCP_MAXIDLE TCP_KEEPCNT * TCP_KEEPINTVL /* Maximum KEEPALIVE probe time */ + + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct tcp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); + PACK_STRUCT_FIELD(u32_t seqno); + PACK_STRUCT_FIELD(u32_t ackno); + PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); + PACK_STRUCT_FIELD(u16_t wnd); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t urgp); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8) +#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) +#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) + +#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr)) +#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) +#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags)) +#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags)) +#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) + +#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \ + TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0)) + +enum tcp_state { + CLOSED = 0, + LISTEN = 1, + SYN_SENT = 2, + SYN_RCVD = 3, + ESTABLISHED = 4, + FIN_WAIT_1 = 5, + FIN_WAIT_2 = 6, + CLOSE_WAIT = 7, + CLOSING = 8, + LAST_ACK = 9, + TIME_WAIT = 10 +}; + +/* the TCP protocol control block */ +struct tcp_pcb { +/** common PCB members */ + IP_PCB; +/** protocol specific PCB members */ + struct tcp_pcb *next; /* for the linked list */ + enum tcp_state state; /* TCP state */ + u8_t prio; + void *callback_arg; + + u16_t local_port; + u16_t remote_port; + + u8_t flags; +#define TF_ACK_DELAY (u8_t)0x01U /* Delayed ACK. */ +#define TF_ACK_NOW (u8_t)0x02U /* Immediate ACK. */ +#define TF_INFR (u8_t)0x04U /* In fast recovery. */ +#define TF_RESET (u8_t)0x08U /* Connection was reset. */ +#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */ +#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ +#define TF_NODELAY (u8_t)0x40U /* Disable Nagle algorithm */ + + /* receiver variables */ + u32_t rcv_nxt; /* next seqno expected */ + u16_t rcv_wnd; /* receiver window */ + + /* Timers */ + u32_t tmr; + u8_t polltmr, pollinterval; + + /* Retransmission timer. */ + u16_t rtime; + + u16_t mss; /* maximum segment size */ + + /* RTT (round trip time) estimation variables */ + u32_t rttest; /* RTT estimate in 500ms ticks */ + u32_t rtseq; /* sequence number being timed */ + s16_t sa, sv; /* @todo document this */ + + u16_t rto; /* retransmission time-out */ + u8_t nrtx; /* number of retransmissions */ + + /* fast retransmit/recovery */ + u32_t lastack; /* Highest acknowledged seqno. */ + u8_t dupacks; + + /* congestion avoidance/control variables */ + u16_t cwnd; + u16_t ssthresh; + + /* sender variables */ + u32_t snd_nxt, /* next seqno to be sent */ + snd_max, /* Highest seqno sent. */ + snd_wnd, /* sender window */ + snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last + window update. */ + snd_lbb; /* Sequence number of next byte to be buffered. */ + + u16_t acked; + + u16_t snd_buf; /* Available buffer space for sending (in bytes). */ + u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */ + + + /* These are ordered by sequence number: */ + struct tcp_seg *unsent; /* Unsent (queued) segments. */ + struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ +#if TCP_QUEUE_OOSEQ + struct tcp_seg *ooseq; /* Received out of sequence segments. */ +#endif /* TCP_QUEUE_OOSEQ */ + +#if LWIP_CALLBACK_API + /* Function to be called when more send buffer space is available. */ + err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space); + + /* Function to be called when (in-sequence) data has arrived. */ + err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); + + /* Function to be called when a connection has been set up. */ + err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err); + + /* Function to call when a listener has been connected. */ + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err); + + /* Function which is called periodically. */ + err_t (* poll)(void *arg, struct tcp_pcb *pcb); + + /* Function to be called whenever a fatal error occurs. */ + void (* errf)(void *arg, err_t err); +#endif /* LWIP_CALLBACK_API */ + + /* idle time before KEEPALIVE is sent */ + u32_t keepalive; + + /* KEEPALIVE counter */ + u8_t keep_cnt; +}; + +struct tcp_pcb_listen { +/* Common members of all PCB types */ + IP_PCB; + +/* Protocol specific PCB members */ + struct tcp_pcb_listen *next; /* for the linked list */ + + /* Even if state is obviously LISTEN this is here for + * field compatibility with tpc_pcb to which it is cast sometimes + * Until a cleaner solution emerges this is here.FIXME + */ + enum tcp_state state; /* TCP state */ + + u8_t prio; + void *callback_arg; + + u16_t local_port; + +#if LWIP_CALLBACK_API + /* Function to call when a listener has been connected. */ + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err); +#endif /* LWIP_CALLBACK_API */ +}; + +#if LWIP_EVENT_API + +enum lwip_event { + LWIP_EVENT_ACCEPT, + LWIP_EVENT_SENT, + LWIP_EVENT_RECV, + LWIP_EVENT_CONNECTED, + LWIP_EVENT_POLL, + LWIP_EVENT_ERR +}; + +err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, + enum lwip_event, + struct pbuf *p, + u16_t size, + err_t err); + +#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_ACCEPT, NULL, 0, err) +#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_SENT, NULL, space, ERR_OK) +#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, (p), 0, (err)) +#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_CONNECTED, NULL, 0, (err)) +#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_POLL, NULL, 0, ERR_OK) +#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \ + LWIP_EVENT_ERR, NULL, 0, (err)) +#else /* LWIP_EVENT_API */ +#define TCP_EVENT_ACCEPT(pcb,err,ret) \ + if((pcb)->accept != NULL) \ + (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err))) +#define TCP_EVENT_SENT(pcb,space,ret) \ + if((pcb)->sent != NULL) \ + (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space))) +#define TCP_EVENT_RECV(pcb,p,err,ret) \ + if((pcb)->recv != NULL) \ + { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \ + if (p) pbuf_free(p); } +#define TCP_EVENT_CONNECTED(pcb,err,ret) \ + if((pcb)->connected != NULL) \ + (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err))) +#define TCP_EVENT_POLL(pcb,ret) \ + if((pcb)->poll != NULL) \ + (ret = (pcb)->poll((pcb)->callback_arg,(pcb))) +#define TCP_EVENT_ERR(errf,arg,err) \ + if((errf) != NULL) \ + (errf)((arg),(err)) +#endif /* LWIP_EVENT_API */ + +/* This structure represents a TCP segment on the unsent and unacked queues */ +struct tcp_seg { + struct tcp_seg *next; /* used when putting segements on a queue */ + struct pbuf *p; /* buffer containing data + TCP header */ + void *dataptr; /* pointer to the TCP data in the pbuf */ + u16_t len; /* the TCP length of this segment */ + struct tcp_hdr *tcphdr; /* the TCP header */ +}; + +/* Internal functions and global variables: */ +struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); +void tcp_pcb_purge(struct tcp_pcb *pcb); +void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); + +u8_t tcp_segs_free(struct tcp_seg *seg); +u8_t tcp_seg_free(struct tcp_seg *seg); +struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); + +#define tcp_ack(pcb) if((pcb)->flags & TF_ACK_DELAY) { \ + (pcb)->flags &= ~TF_ACK_DELAY; \ + (pcb)->flags |= TF_ACK_NOW; \ + tcp_output(pcb); \ + } else { \ + (pcb)->flags |= TF_ACK_DELAY; \ + } + +#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \ + tcp_output(pcb) + +err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags); +err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len, + u8_t flags, u8_t copy, + u8_t *optdata, u8_t optlen); + +void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); + +void tcp_rst(u32_t seqno, u32_t ackno, + struct ip_addr *local_ip, struct ip_addr *remote_ip, + u16_t local_port, u16_t remote_port); + +u32_t tcp_next_iss(void); + +void tcp_keepalive(struct tcp_pcb *pcb); + +extern struct tcp_pcb *tcp_input_pcb; +extern u32_t tcp_ticks; + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +void tcp_debug_print(struct tcp_hdr *tcphdr); +void tcp_debug_print_flags(u8_t flags); +void tcp_debug_print_state(enum tcp_state s); +void tcp_debug_print_pcbs(void); +s16_t tcp_pcbs_sane(void); +#else +# define tcp_debug_print(tcphdr) +# define tcp_debug_print_flags(flags) +# define tcp_debug_print_state(s) +# define tcp_debug_print_pcbs() +# define tcp_pcbs_sane() 1 +#endif /* TCP_DEBUG */ + +#if NO_SYS +#define tcp_timer_needed() +#else +void tcp_timer_needed(void); +#endif + +/* The TCP PCB lists. */ +union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ + struct tcp_pcb_listen *listen_pcbs; + struct tcp_pcb *pcbs; +}; +extern union tcp_listen_pcbs_t tcp_listen_pcbs; +extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a + state in which they accept or send + data. */ +extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ + +extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */ + +/* Axioms about the above lists: + 1) Every TCP PCB that is not CLOSED is in one of the lists. + 2) A PCB is only in one of the lists. + 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. + 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. +*/ + +/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB + with a PCB list or removes a PCB from a list, respectively. */ +#if 0 +#define TCP_REG(pcbs, npcb) do {\ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \ + for(tcp_tmp_pcb = *pcbs; \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \ + } \ + LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \ + npcb->next = *pcbs; \ + LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \ + *(pcbs) = npcb; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + tcp_timer_needed(); \ + } while(0) +#define TCP_RMV(pcbs, npcb) do { \ + LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \ + if(*pcbs == npcb) { \ + *pcbs = (*pcbs)->next; \ + } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ + tcp_tmp_pcb->next = npcb->next; \ + break; \ + } \ + } \ + npcb->next = NULL; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \ + } while(0) + +#else /* LWIP_DEBUG */ +#define TCP_REG(pcbs, npcb) do { \ + npcb->next = *pcbs; \ + *(pcbs) = npcb; \ + tcp_timer_needed(); \ + } while(0) +#define TCP_RMV(pcbs, npcb) do { \ + if(*(pcbs) == npcb) { \ + (*(pcbs)) = (*pcbs)->next; \ + } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ + tcp_tmp_pcb->next = npcb->next; \ + break; \ + } \ + } \ + npcb->next = NULL; \ + } while(0) +#endif /* LWIP_DEBUG */ +#endif /* __LWIP_TCP_H__ */ + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/tcpip.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/tcpip.h new file mode 100644 index 0000000..242664e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/tcpip.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCPIP_H__ +#define __LWIP_TCPIP_H__ + +#include "lwip/api_msg.h" +#include "lwip/pbuf.h" + +void tcpip_init(void (* tcpip_init_done)(void *), void *arg); +void tcpip_apimsg(struct api_msg *apimsg); +err_t tcpip_input(struct pbuf *p, struct netif *inp); +err_t tcpip_callback(void (*f)(void *ctx), void *ctx); + +void tcpip_tcp_timer_needed(void); + +enum tcpip_msg_type { + TCPIP_MSG_API, + TCPIP_MSG_INPUT, + TCPIP_MSG_CALLBACK +}; + +struct tcpip_msg { + enum tcpip_msg_type type; + sys_sem_t *sem; + union { + struct api_msg *apimsg; + struct { + struct pbuf *p; + struct netif *netif; + } inp; + struct { + void (*f)(void *ctx); + void *ctx; + } cb; + } msg; +}; + + +#endif /* __LWIP_TCPIP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/udp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/udp.h new file mode 100644 index 0000000..adefdc9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/lwip/udp.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_UDP_H__ +#define __LWIP_UDP_H__ + +#include "lwip/arch.h" + +#include "lwip/pbuf.h" +#include "lwip/inet.h" +#include "lwip/ip.h" + +#define UDP_HLEN 8 + +struct udp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ + PACK_STRUCT_FIELD(u16_t len); + PACK_STRUCT_FIELD(u16_t chksum); +} PACK_STRUCT_STRUCT; + +#define UDP_FLAGS_NOCHKSUM 0x01U +#define UDP_FLAGS_UDPLITE 0x02U +#define UDP_FLAGS_CONNECTED 0x04U + +struct udp_pcb { +/* Common members of all PCB types */ + IP_PCB; + +/* Protocol specific PCB members */ + + struct udp_pcb *next; + + u8_t flags; + u16_t local_port, remote_port; + + u16_t chksum_len; + + void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *addr, u16_t port); + void *recv_arg; +}; +/* udp_pcbs export for exernal reference (e.g. SNMP agent) */ +extern struct udp_pcb *udp_pcbs; + +/* The following functions is the application layer interface to the + UDP code. */ +struct udp_pcb * udp_new (void); +void udp_remove (struct udp_pcb *pcb); +err_t udp_bind (struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +err_t udp_connect (struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +void udp_disconnect (struct udp_pcb *pcb); +void udp_recv (struct udp_pcb *pcb, + void (* recv)(void *arg, struct udp_pcb *upcb, + struct pbuf *p, + struct ip_addr *addr, + u16_t port), + void *recv_arg); +err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port); +err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); + +#define udp_flags(pcb) ((pcb)->flags) +#define udp_setflags(pcb, f) ((pcb)->flags = (f)) + +/* The following functions are the lower layer interface to UDP. */ +void udp_input (struct pbuf *p, struct netif *inp); +void udp_init (void); + +#if UDP_DEBUG +void udp_debug_print(struct udp_hdr *udphdr); +#else +#define udp_debug_print(udphdr) +#endif +#endif /* __LWIP_UDP_H__ */ + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/netif/etharp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/netif/etharp.h new file mode 100644 index 0000000..cc0a35f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/netif/etharp.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __NETIF_ETHARP_H__ +#define __NETIF_ETHARP_H__ + +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/ip.h" + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct eth_addr { + PACK_STRUCT_FIELD(u8_t addr[6]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct eth_hdr { +#if ETH_PAD_SIZE + PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]); +#endif + PACK_STRUCT_FIELD(struct eth_addr dest); + PACK_STRUCT_FIELD(struct eth_addr src); + PACK_STRUCT_FIELD(u16_t type); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** the ARP message */ +struct etharp_hdr { + PACK_STRUCT_FIELD(struct eth_hdr ethhdr); + PACK_STRUCT_FIELD(u16_t hwtype); + PACK_STRUCT_FIELD(u16_t proto); + PACK_STRUCT_FIELD(u16_t _hwlen_protolen); + PACK_STRUCT_FIELD(u16_t opcode); + PACK_STRUCT_FIELD(struct eth_addr shwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 sipaddr); + PACK_STRUCT_FIELD(struct eth_addr dhwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 dipaddr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ethip_hdr { + PACK_STRUCT_FIELD(struct eth_hdr eth); + PACK_STRUCT_FIELD(struct ip_hdr ip); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** 5 seconds period */ +#define ARP_TMR_INTERVAL 5000 + +#define ETHTYPE_ARP 0x0806 +#define ETHTYPE_IP 0x0800 + + +void etharp_init(void); +void etharp_tmr(void); +s8_t etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr, + struct eth_addr **eth_ret, struct ip_addr **ip_ret); +void etharp_ip_input(struct netif *netif, struct pbuf *p); +void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, + struct pbuf *p); +err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr, + struct pbuf *q); +err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q); +err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr); + +#endif /* __NETIF_ARP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/netif/loopif.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/netif/loopif.h new file mode 100644 index 0000000..7fd5487 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/netif/loopif.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __NETIF_LOOPIF_H__ +#define __NETIF_LOOPIF_H__ + +#include "lwip/netif.h" + +err_t loopif_init(struct netif *netif); + +#endif /* __NETIF_LOOPIF_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/netif/slipif.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/netif/slipif.h new file mode 100644 index 0000000..d9060fc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/include/netif/slipif.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __NETIF_SLIPIF_H__ +#define __NETIF_SLIPIF_H__ + +#include "lwip/netif.h" + +err_t slipif_init(struct netif * netif); + +#endif + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/FILES b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/FILES new file mode 100644 index 0000000..825d407 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/FILES @@ -0,0 +1,27 @@ +This directory contains generic network interface device drivers that +do not contain any hardware or architecture specific code. The files +are: + +etharp.c + Implements the ARP (Address Resolution Protocol) over + Ethernet. The code in this file should be used together with + Ethernet device drivers. Note that this module has been + largely made Ethernet independent so you should be able to + adapt this for other link layers (such as Firewire). + +ethernetif.c + An example of how an Ethernet device driver could look. This + file can be used as a "skeleton" for developing new Ethernet + network device drivers. It uses the etharp.c ARP code. + +loopif.c + An example network interface that shows how a "loopback" + interface would work. This is not really intended for actual + use, but as a very basic example of how initialization and + output functions work. + +slipif.c + A generic implementation of the SLIP (Serial Line IP) + protocol. It requires a sio (serial I/O) module to work. + +ppp/ Point-to-Point Protocol stack diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/etharp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/etharp.c new file mode 100644 index 0000000..22eeb9a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/etharp.c @@ -0,0 +1,892 @@ +/** + * @file + * Address Resolution Protocol module for IP over Ethernet + * + * Functionally, ARP is divided into two parts. The first maps an IP address + * to a physical address when sending a packet, and the second part answers + * requests from other machines for our physical address. + * + * This implementation complies with RFC 826 (Ethernet ARP). It supports + * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6 + * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon + * address change. + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ +#include +#include "lwip/opt.h" +#include "lwip/inet.h" +#include "netif/etharp.h" +#include "lwip/ip.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +/* ARP needs to inform DHCP of any ARP replies? */ +#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) +# include "lwip/dhcp.h" +#endif + +/** the time an ARP entry stays valid after its last update, + * (240 * 5) seconds = 20 minutes. + */ +#define ARP_MAXAGE 240 +/** the time an ARP entry stays pending after first request, + * (2 * 5) seconds = 10 seconds. + * + * @internal Keep this number at least 2, otherwise it might + * run out instantly if the timeout occurs directly after a request. + */ +#define ARP_MAXPENDING 2 + +#define HWTYPE_ETHERNET 1 + +/** ARP message types */ +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8) +#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff) + +#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8)) +#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8)) + +enum etharp_state { + ETHARP_STATE_EMPTY, + ETHARP_STATE_PENDING, + ETHARP_STATE_STABLE, + /** @internal transitional state used in etharp_tmr() for convenience*/ + ETHARP_STATE_EXPIRED +}; + +struct etharp_entry { +#if ARP_QUEUEING + /** + * Pointer to queue of pending outgoing packets on this ARP entry. + */ + struct pbuf *p; +#endif + struct ip_addr ipaddr; + struct eth_addr ethaddr; + enum etharp_state state; + u8_t ctime; + struct netif *netif; +}; + +static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; +static struct etharp_entry arp_table[ARP_TABLE_SIZE]; + +/** + * Try hard to create a new entry - we want the IP address to appear in + * the cache (even if this means removing an active entry or so). */ +#define ETHARP_TRY_HARD 1 + +static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags); +static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags); +/** + * Initializes ARP module. + */ +void +etharp_init(void) +{ + u8_t i; + /* clear ARP entries */ + for(i = 0; i < ARP_TABLE_SIZE; ++i) { + arp_table[i].state = ETHARP_STATE_EMPTY; +#if ARP_QUEUEING + arp_table[i].p = NULL; +#endif + arp_table[i].ctime = 0; + arp_table[i].netif = NULL; + } +} + +/** + * Clears expired entries in the ARP table. + * + * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds), + * in order to expire entries in the ARP table. + */ +void +etharp_tmr(void) +{ + u8_t i; + + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); + /* remove expired entries from the ARP table */ + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + arp_table[i].ctime++; + /* stable entry? */ + if ((arp_table[i].state == ETHARP_STATE_STABLE) && + /* entry has become old? */ + (arp_table[i].ctime >= ARP_MAXAGE)) { + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %"U16_F".\n", (u16_t)i)); + arp_table[i].state = ETHARP_STATE_EXPIRED; + /* pending entry? */ + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* entry unresolved/pending for too long? */ + if (arp_table[i].ctime >= ARP_MAXPENDING) { + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %"U16_F".\n", (u16_t)i)); + arp_table[i].state = ETHARP_STATE_EXPIRED; +#if ARP_QUEUEING + } else if (arp_table[i].p != NULL) { + /* resend an ARP query here */ +#endif + } + } + /* clean up entries that have just been expired */ + if (arp_table[i].state == ETHARP_STATE_EXPIRED) { + /* remove from SNMP ARP index tree */ + snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr); +#if ARP_QUEUEING + /* and empty packet queue */ + if (arp_table[i].p != NULL) { + /* remove all queued packets */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].p))); + pbuf_free(arp_table[i].p); + arp_table[i].p = NULL; + } +#endif + /* recycle entry for re-use */ + arp_table[i].state = ETHARP_STATE_EMPTY; + } + } +} + +/** + * Search the ARP table for a matching or new entry. + * + * If an IP address is given, return a pending or stable ARP entry that matches + * the address. If no match is found, create a new entry with this address set, + * but in state ETHARP_EMPTY. The caller must check and possibly change the + * state of the returned entry. + * + * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY. + * + * In all cases, attempt to create new entries from an empty entry. If no + * empty entries are available and ETHARP_TRY_HARD flag is set, recycle + * old entries. Heuristic choose the least important entry for recycling. + * + * @param ipaddr IP address to find in ARP cache, or to add if not found. + * @param flags + * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of + * active (stable or pending) entries. + * + * @return The ARP entry index that matched or is created, ERR_MEM if no + * entry is found or could be recycled. + */ +static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags) +{ + s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; + s8_t empty = ARP_TABLE_SIZE; + u8_t i = 0, age_pending = 0, age_stable = 0; +#if ARP_QUEUEING + /* oldest entry with packets on queue */ + s8_t old_queue = ARP_TABLE_SIZE; + /* its age */ + u8_t age_queue = 0; +#endif + + /** + * a) do a search through the cache, remember candidates + * b) select candidate entry + * c) create new entry + */ + + /* a) in a single search sweep, do all of this + * 1) remember the first empty entry (if any) + * 2) remember the oldest stable entry (if any) + * 3) remember the oldest pending entry without queued packets (if any) + * 4) remember the oldest pending entry with queued packets (if any) + * 5) search for a matching IP entry, either pending or stable + * until 5 matches, or all entries are searched for. + */ + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + /* no empty entry found yet and now we do find one? */ + if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) { + LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i)); + /* remember first empty entry */ + empty = i; + } + /* pending entry? */ + else if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i)); + /* found exact IP address match, simply bail out */ + return i; +#if ARP_QUEUEING + /* pending with queued packets? */ + } else if (arp_table[i].p != NULL) { + if (arp_table[i].ctime >= age_queue) { + old_queue = i; + age_queue = arp_table[i].ctime; + } +#endif + /* pending without queued packets? */ + } else { + if (arp_table[i].ctime >= age_pending) { + old_pending = i; + age_pending = arp_table[i].ctime; + } + } + } + /* stable entry? */ + else if (arp_table[i].state == ETHARP_STATE_STABLE) { + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i)); + /* found exact IP address match, simply bail out */ + return i; + /* remember entry with oldest stable entry in oldest, its age in maxtime */ + } else if (arp_table[i].ctime >= age_stable) { + old_stable = i; + age_stable = arp_table[i].ctime; + } + } + } + /* { we have no match } => try to create a new entry */ + + /* no empty entry found and not allowed to recycle? */ + if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0)) + { + return (s8_t)ERR_MEM; + } + + /* b) choose the least destructive entry to recycle: + * 1) empty entry + * 2) oldest stable entry + * 3) oldest pending entry without queued packets + * 4) oldest pending entry without queued packets + * + * { ETHARP_TRY_HARD is set at this point } + */ + + /* 1) empty entry available? */ + if (empty < ARP_TABLE_SIZE) { + i = empty; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i)); + } + /* 2) found recyclable stable entry? */ + else if (old_stable < ARP_TABLE_SIZE) { + /* recycle oldest stable*/ + i = old_stable; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i)); +#if ARP_QUEUEING + /* no queued packets should exist on stable entries */ + LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL); +#endif + /* 3) found recyclable pending entry without queued packets? */ + } else if (old_pending < ARP_TABLE_SIZE) { + /* recycle oldest pending */ + i = old_pending; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i)); +#if ARP_QUEUEING + /* 4) found recyclable pending entry with queued packets? */ + } else if (old_queue < ARP_TABLE_SIZE) { + /* recycle oldest pending */ + i = old_queue; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].p))); + pbuf_free(arp_table[i].p); + arp_table[i].p = NULL; +#endif + /* no empty or recyclable entries found */ + } else { + return (s8_t)ERR_MEM; + } + + /* { empty or recyclable entry found } */ + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + + if (arp_table[i].state != ETHARP_STATE_EMPTY) + { + snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr); + } + /* recycle entry (no-op for an already empty entry) */ + arp_table[i].state = ETHARP_STATE_EMPTY; + + /* IP address given? */ + if (ipaddr != NULL) { + /* set IP address */ + ip_addr_set(&arp_table[i].ipaddr, ipaddr); + } + arp_table[i].ctime = 0; + return (err_t)i; +} + +/** + * Update (or insert) a IP/MAC address pair in the ARP cache. + * + * If a pending entry is resolved, any queued packets will be sent + * at this point. + * + * @param ipaddr IP address of the inserted ARP entry. + * @param ethaddr Ethernet address of the inserted ARP entry. + * @param flags Defines behaviour: + * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified, + * only existing ARP entries will be updated. + * + * @return + * - ERR_OK Succesfully updated ARP cache. + * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set. + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + * @see pbuf_free() + */ +static err_t +update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags) +{ + s8_t i; + u8_t k; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n")); + LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0); + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", + ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), + ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2], + ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5])); + /* non-unicast address? */ + if (ip_addr_isany(ipaddr) || + ip_addr_isbroadcast(ipaddr, netif) || + ip_addr_ismulticast(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + /* find or create ARP entry */ + i = find_entry(ipaddr, flags); + /* bail out if no entry could be found */ + if (i < 0) return (err_t)i; + + /* mark it stable */ + arp_table[i].state = ETHARP_STATE_STABLE; + /* record network interface */ + arp_table[i].netif = netif; + + /* insert in SNMP ARP index tree */ + snmp_insert_arpidx_tree(netif, &arp_table[i].ipaddr); + + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i)); + /* update address */ + k = netif->hwaddr_len; + while (k > 0) { + k--; + arp_table[i].ethaddr.addr[k] = ethaddr->addr[k]; + } + /* reset time stamp */ + arp_table[i].ctime = 0; +/* this is where we will send out queued packets! */ +#if ARP_QUEUEING + while (arp_table[i].p != NULL) { + /* get the first packet on the queue */ + struct pbuf *p = arp_table[i].p; + /* Ethernet header */ + struct eth_hdr *ethhdr = p->payload; + /* remember (and reference) remainder of queue */ + /* note: this will also terminate the p pbuf chain */ + arp_table[i].p = pbuf_dequeue(p); + /* fill-in Ethernet header */ + k = netif->hwaddr_len; + while(k > 0) { + k--; + ethhdr->dest.addr[k] = ethaddr->addr[k]; + ethhdr->src.addr[k] = netif->hwaddr[k]; + } + ethhdr->type = htons(ETHTYPE_IP); + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p)); + /* send the queued IP packet */ + netif->linkoutput(netif, p); + /* free the queued IP packet */ + pbuf_free(p); + } +#endif + return ERR_OK; +} + +/** + * Finds (stable) ethernet/IP address pair from ARP table + * using interface and IP address index. + * @note the addresses in the ARP table are in network order! + * + * @param netif points to interface index + * @param ipaddr points to the (network order) IP address index + * @param eth_ret points to return pointer + * @param ip_ret points to return pointer + * @return table index if found, -1 otherwise + */ +s8_t +etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr, + struct eth_addr **eth_ret, struct ip_addr **ip_ret) +{ + s8_t i; + + i = 0; + while (i < ARP_TABLE_SIZE) + { + if ((arp_table[i].state == ETHARP_STATE_STABLE) && + (arp_table[i].netif == netif) && + ip_addr_cmp(ipaddr, &arp_table[i].ipaddr) ) + { + *eth_ret = &arp_table[i].ethaddr; + *ip_ret = &arp_table[i].ipaddr; + return i; + } + i++; + } + return -1; +} + +/** + * Updates the ARP table using the given IP packet. + * + * Uses the incoming IP packet's source address to update the + * ARP cache for the local network. The function does not alter + * or free the packet. This function must be called before the + * packet p is passed to the IP layer. + * + * @param netif The lwIP network interface on which the IP packet pbuf arrived. + * @param pbuf The IP packet that arrived on netif. + * + * @return NULL + * + * @see pbuf_free() + */ +void +etharp_ip_input(struct netif *netif, struct pbuf *p) +{ + struct ethip_hdr *hdr; + LWIP_ASSERT("netif != NULL", netif != NULL); + /* Only insert an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + hdr = p->payload; + /* source is not on the local network? */ + if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) { + /* do nothing */ + return; + } + + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n")); + /* update ARP table */ + /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk + * back soon (for example, if the destination IP address is ours. */ + update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0); +} + + +/** + * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache + * send out queued IP packets. Updates cache with snooped address pairs. + * + * Should be called for incoming ARP packets. The pbuf in the argument + * is freed by this function. + * + * @param netif The lwIP network interface on which the ARP packet pbuf arrived. + * @param pbuf The ARP packet that arrived on netif. Is freed by this function. + * @param ethaddr Ethernet address of netif. + * + * @return NULL + * + * @see pbuf_free() + */ +void +etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p) +{ + struct etharp_hdr *hdr; + /* these are aligned properly, whereas the ARP header fields might not be */ + struct ip_addr sipaddr, dipaddr; + u8_t i; + u8_t for_us; + + LWIP_ASSERT("netif != NULL", netif != NULL); + + /* drop short ARP packets */ + if (p->tot_len < sizeof(struct etharp_hdr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, (s16_t)sizeof(struct etharp_hdr))); + pbuf_free(p); + return; + } + + hdr = p->payload; + + /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without + * structure packing (not using structure copy which breaks strict-aliasing rules). */ + memcpy(&sipaddr, &hdr->sipaddr, sizeof(sipaddr)); + memcpy(&dipaddr, &hdr->dipaddr, sizeof(dipaddr)); + + /* this interface is not configured? */ + if (netif->ip_addr.addr == 0) { + for_us = 0; + } else { + /* ARP packet directed to us? */ + for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr)); + } + + /* ARP message directed to us? */ + if (for_us) { + /* add IP address in ARP cache; assume requester wants to talk to us. + * can result in directly sending the queued packets for this host. */ + update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD); + /* ARP message not directed to us? */ + } else { + /* update the source IP address in the cache, if present */ + update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0); + } + + /* now act on the message itself */ + switch (htons(hdr->opcode)) { + /* ARP request? */ + case ARP_REQUEST: + /* ARP request. If it asked for our address, we send out a + * reply. In any case, we time-stamp any existing ARP entry, + * and possiby send out an IP packet that was queued on it. */ + + LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n")); + /* ARP request for our address? */ + if (for_us) { + + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n")); + /* re-use pbuf to send ARP reply */ + hdr->opcode = htons(ARP_REPLY); + + hdr->dipaddr = hdr->sipaddr; + hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr; + + i = netif->hwaddr_len; + while(i > 0) { + i--; + hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i]; + hdr->shwaddr.addr[i] = ethaddr->addr[i]; + hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i]; + hdr->ethhdr.src.addr[i] = ethaddr->addr[i]; + } + + hdr->hwtype = htons(HWTYPE_ETHERNET); + ARPH_HWLEN_SET(hdr, netif->hwaddr_len); + + hdr->proto = htons(ETHTYPE_IP); + ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr)); + + hdr->ethhdr.type = htons(ETHTYPE_ARP); + /* return ARP reply */ + netif->linkoutput(netif, p); + /* we are not configured? */ + } else if (netif->ip_addr.addr == 0) { + /* { for_us == 0 and netif->ip_addr.addr == 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n")); + /* request was not directed to us */ + } else { + /* { for_us == 0 and netif->ip_addr.addr != 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n")); + } + break; + case ARP_REPLY: + /* ARP reply. We already updated the ARP cache earlier. */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n")); +#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) + /* DHCP wants to know about ARP replies from any host with an + * IP address also offered to us by the DHCP server. We do not + * want to take a duplicate IP address on a single network. + * @todo How should we handle redundant (fail-over) interfaces? + * */ + dhcp_arp_reply(netif, &sipaddr); +#endif + break; + default: + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode))); + break; + } + /* free ARP packet */ + pbuf_free(p); +} + +/** + * Resolve and fill-in Ethernet address header for outgoing packet. + * + * For IP multicast and broadcast, corresponding Ethernet addresses + * are selected and the packet is transmitted on the link. + * + * For unicast addresses, the packet is submitted to etharp_query(). In + * case the IP address is outside the local network, the IP address of + * the gateway is used. + * + * @param netif The lwIP network interface which the IP packet will be sent on. + * @param ipaddr The IP address of the packet destination. + * @param pbuf The pbuf(s) containing the IP packet to be sent. + * + * @return + * - ERR_RTE No route to destination (no gateway to external networks), + * or the return type of either etharp_query() or netif->linkoutput(). + */ +err_t +etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) +{ + struct eth_addr *dest, *srcaddr, mcastaddr; + struct eth_hdr *ethhdr; + u8_t i; + + /* make room for Ethernet header - should not fail */ + if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) { + /* bail out */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n")); + LINK_STATS_INC(link.lenerr); + return ERR_BUF; + } + + /* assume unresolved Ethernet address */ + dest = NULL; + /* Determine on destination hardware address. Broadcasts and multicasts + * are special, other IP addresses are looked up in the ARP table. */ + + /* broadcast destination IP address? */ + if (ip_addr_isbroadcast(ipaddr, netif)) { + /* broadcast on Ethernet also */ + dest = (struct eth_addr *)ðbroadcast; + /* multicast destination IP address? */ + } else if (ip_addr_ismulticast(ipaddr)) { + /* Hash IP multicast address to MAC address.*/ + mcastaddr.addr[0] = 0x01; + mcastaddr.addr[1] = 0x00; + mcastaddr.addr[2] = 0x5e; + mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; + mcastaddr.addr[4] = ip4_addr3(ipaddr); + mcastaddr.addr[5] = ip4_addr4(ipaddr); + /* destination Ethernet address is multicast */ + dest = &mcastaddr; + /* unicast destination IP address? */ + } else { + /* outside local network? */ + if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) { + /* interface has default gateway? */ + if (netif->gw.addr != 0) { + /* send to hardware address of default gateway IP address */ + ipaddr = &(netif->gw); + /* no default gateway available */ + } else { + /* no route to destination error (default gateway missing) */ + return ERR_RTE; + } + } + /* queue on destination Ethernet address belonging to ipaddr */ + return etharp_query(netif, ipaddr, q); + } + + /* continuation for multicast/broadcast destinations */ + /* obtain source Ethernet address of the given interface */ + srcaddr = (struct eth_addr *)netif->hwaddr; + ethhdr = q->payload; + i = netif->hwaddr_len; + while(i > 0) { + i--; + ethhdr->dest.addr[i] = dest->addr[i]; + ethhdr->src.addr[i] = srcaddr->addr[i]; + } + ethhdr->type = htons(ETHTYPE_IP); + /* send packet directly on the link */ + return netif->linkoutput(netif, q); +} + +/** + * Send an ARP request for the given IP address and/or queue a packet. + * + * If the IP address was not yet in the cache, a pending ARP cache entry + * is added and an ARP request is sent for the given address. The packet + * is queued on this entry. + * + * If the IP address was already pending in the cache, a new ARP request + * is sent for the given address. The packet is queued on this entry. + * + * If the IP address was already stable in the cache, and a packet is + * given, it is directly sent and no ARP request is sent out. + * + * If the IP address was already stable in the cache, and no packet is + * given, an ARP request is sent out. + * + * @param netif The lwIP network interface on which ipaddr + * must be queried for. + * @param ipaddr The IP address to be resolved. + * @param q If non-NULL, a pbuf that must be delivered to the IP address. + * q is not freed by this function. + * + * @return + * - ERR_BUF Could not make room for Ethernet header. + * - ERR_MEM Hardware address unknown, and no more ARP entries available + * to query for address or queue the packet. + * - ERR_MEM Could not queue packet due to memory shortage. + * - ERR_RTE No route to destination (no gateway to external networks). + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + */ +err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) +{ + struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; + err_t result = ERR_MEM; + s8_t i; /* ARP entry index */ + u8_t k; /* Ethernet address octet index */ + + /* non-unicast address? */ + if (ip_addr_isbroadcast(ipaddr, netif) || + ip_addr_ismulticast(ipaddr) || + ip_addr_isany(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + + /* find entry in ARP cache, ask to create entry if queueing packet */ + i = find_entry(ipaddr, ETHARP_TRY_HARD); + + /* could not find or create entry? */ + if (i < 0) + { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n")); + if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n")); + return (err_t)i; + } + + /* mark a fresh entry as pending (we just sent a request) */ + if (arp_table[i].state == ETHARP_STATE_EMPTY) { + arp_table[i].state = ETHARP_STATE_PENDING; + } + + /* { i is either a STABLE or (new or existing) PENDING entry } */ + LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", + ((arp_table[i].state == ETHARP_STATE_PENDING) || + (arp_table[i].state == ETHARP_STATE_STABLE))); + + /* do we have a pending entry? or an implicit query request? */ + if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) { + /* try to resolve it; send out ARP request */ + result = etharp_request(netif, ipaddr); + } + + /* packet given? */ + if (q != NULL) { + /* stable entry? */ + if (arp_table[i].state == ETHARP_STATE_STABLE) { + /* we have a valid IP->Ethernet address mapping, + * fill in the Ethernet header for the outgoing packet */ + struct eth_hdr *ethhdr = q->payload; + k = netif->hwaddr_len; + while(k > 0) { + k--; + ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k]; + ethhdr->src.addr[k] = srcaddr->addr[k]; + } + ethhdr->type = htons(ETHTYPE_IP); + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q)); + /* send the packet */ + result = netif->linkoutput(netif, q); + /* pending entry? (either just created or already pending */ + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { +#if ARP_QUEUEING /* queue the given q packet */ + struct pbuf *p; + /* copy any PBUF_REF referenced payloads into PBUF_RAM */ + /* (the caller of lwIP assumes the referenced payload can be + * freed after it returns from the lwIP call that brought us here) */ + p = pbuf_take(q); + /* packet could be taken over? */ + if (p != NULL) { + /* queue packet ... */ + if (arp_table[i].p == NULL) { + /* ... in the empty queue */ + pbuf_ref(p); + arp_table[i].p = p; +#if 0 /* multi-packet-queueing disabled, see bug #11400 */ + } else { + /* ... at tail of non-empty queue */ + pbuf_queue(arp_table[i].p, p); +#endif + } + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); + result = ERR_OK; + } else { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + /* { result == ERR_MEM } through initialization */ + } +#else /* ARP_QUEUEING == 0 */ + /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */ + /* { result == ERR_MEM } through initialization */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q)); +#endif + } + } + return result; +} + +err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr) +{ + struct pbuf *p; + struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; + err_t result = ERR_OK; + u8_t k; /* ARP entry index */ + + /* allocate a pbuf for the outgoing ARP request packet */ + p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM); + /* could allocate a pbuf for an ARP request? */ + if (p != NULL) { + struct etharp_hdr *hdr = p->payload; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n")); + hdr->opcode = htons(ARP_REQUEST); + k = netif->hwaddr_len; + while(k > 0) { + k--; + hdr->shwaddr.addr[k] = srcaddr->addr[k]; + /* the hardware address is what we ask for, in + * a request it is a don't-care value, we use zeroes */ + hdr->dhwaddr.addr[k] = 0x00; + } + hdr->dipaddr = *(struct ip_addr2 *)ipaddr; + hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr; + + hdr->hwtype = htons(HWTYPE_ETHERNET); + ARPH_HWLEN_SET(hdr, netif->hwaddr_len); + + hdr->proto = htons(ETHTYPE_IP); + ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr)); + k = netif->hwaddr_len; + while(k > 0) { + k--; + /* broadcast to all network interfaces on the local network */ + hdr->ethhdr.dest.addr[k] = 0xff; + hdr->ethhdr.src.addr[k] = srcaddr->addr[k]; + } + hdr->ethhdr.type = htons(ETHTYPE_ARP); + /* send ARP query */ + result = netif->linkoutput(netif, p); + /* free ARP query packet */ + pbuf_free(p); + p = NULL; + /* could not allocate pbuf for ARP request */ + } else { + result = ERR_MEM; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n")); + } + return result; +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ethernetif.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ethernetif.c new file mode 100644 index 0000000..300775f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ethernetif.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * This file is a skeleton for developing Ethernet network interface + * drivers for lwIP. Add code to the low_level functions and do a + * search-and-replace for the word "ethernetif" to replace it with + * something that better describes your network interface. + */ + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include + +#include "netif/etharp.h" + +/* Define those to better describe your network interface. */ +#define IFNAME0 'e' +#define IFNAME1 'n' + +struct ethernetif { + struct eth_addr *ethaddr; + /* Add whatever per-interface state that is needed here. */ +}; + +static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; + +/* Forward declarations. */ +static void ethernetif_input(struct netif *netif); +static err_t ethernetif_output(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr); + +static void +low_level_init(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + + /* set MAC hardware address length */ + netif->hwaddr_len = 6; + + /* set MAC hardware address */ + netif->hwaddr[0] = ; + ... + netif->hwaddr[5] = ; + + /* maximum transfer unit */ + netif->mtu = 1500; + + /* broadcast capability */ + netif->flags = NETIF_FLAG_BROADCAST; + + /* Do whatever else is needed to initialize interface. */ +} + +/* + * low_level_output(): + * + * Should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + */ + +static err_t +low_level_output(struct netif *netif, struct pbuf *p) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *q; + + initiate transfer(); + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + for(q = p; q != NULL; q = q->next) { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + send data from(q->payload, q->len); + } + + signal that packet should be sent(); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + +#if LINK_STATS + lwip_stats.link.xmit++; +#endif /* LINK_STATS */ + + return ERR_OK; +} + +/* + * low_level_input(): + * + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + */ + +static struct pbuf * +low_level_input(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *p, *q; + u16_t len; + + /* Obtain the size of the packet and put it into the "len" + variable. */ + len = ; + +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (p != NULL) { + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + for(q = p; q != NULL; q = q->next) { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. */ + read data into(q->payload, q->len); + } + acknowledge that packet has been read(); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + +#if LINK_STATS + lwip_stats.link.recv++; +#endif /* LINK_STATS */ + } else { + drop packet(); +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif /* LINK_STATS */ + } + + return p; +} + +/* + * ethernetif_output(): + * + * This function is called by the TCP/IP stack when an IP packet + * should be sent. It calls the function called low_level_output() to + * do the actual transmission of the packet. + * + */ + +static err_t +ethernetif_output(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr) +{ + + /* resolve hardware address, then send (or queue) packet */ + return etharp_output(netif, ipaddr, p); + +} + +/* + * ethernetif_input(): + * + * This function should be called when a packet is ready to be read + * from the interface. It uses the function low_level_input() that + * should handle the actual reception of bytes from the network + * interface. + * + */ + +static void +ethernetif_input(struct netif *netif) +{ + struct ethernetif *ethernetif; + struct eth_hdr *ethhdr; + struct pbuf *p; + + ethernetif = netif->state; + + /* move received packet into a new pbuf */ + p = low_level_input(netif); + /* no packet could be read, silently ignore this */ + if (p == NULL) return; + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = p->payload; + +#if LINK_STATS + lwip_stats.link.recv++; +#endif /* LINK_STATS */ + + ethhdr = p->payload; + + switch (htons(ethhdr->type)) { + /* IP packet? */ + case ETHTYPE_IP: +#if 0 +/* CSi disabled ARP table update on ingress IP packets. + This seems to work but needs thorough testing. */ + /* update ARP table */ + etharp_ip_input(netif, p); +#endif + /* skip Ethernet header */ + pbuf_header(p, -sizeof(struct eth_hdr)); + /* pass to network layer */ + netif->input(p, netif); + break; + + case ETHTYPE_ARP: + /* pass p to ARP module */ + etharp_arp_input(netif, ethernetif->ethaddr, p); + break; + default: + pbuf_free(p); + p = NULL; + break; + } +} + +static void +arp_timer(void *arg) +{ + etharp_tmr(); + sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); +} + +/* + * ethernetif_init(): + * + * Should be called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + */ + +err_t +ethernetif_init(struct netif *netif) +{ + struct ethernetif *ethernetif; + + ethernetif = mem_malloc(sizeof(struct ethernetif)); + + if (ethernetif == NULL) + { + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); + return ERR_MEM; + } + +#if LWIP_SNMP + /* ifType ethernetCsmacd(6) @see RFC1213 */ + netif->link_type = 6; + /* your link speed here */ + netif->link_speed = ; + netif->ts = 0; + netif->ifinoctets = 0; + netif->ifinucastpkts = 0; + netif->ifinnucastpkts = 0; + netif->ifindiscards = 0; + netif->ifoutoctets = 0; + netif->ifoutucastpkts = 0; + netif->ifoutnucastpkts = 0; + netif->ifoutdiscards = 0; +#endif + + netif->state = ethernetif; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + netif->output = ethernetif_output; + netif->linkoutput = low_level_output; + + ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); + + low_level_init(netif); + + etharp_init(); + + sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); + + return ERR_OK; +} + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/loopif.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/loopif.c new file mode 100644 index 0000000..cd523fb --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/loopif.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#include "lwip/opt.h" + +#if LWIP_HAVE_LOOPIF + +#include "netif/loopif.h" +#include "lwip/mem.h" + +#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP) +#include "netif/tcpdump.h" +#endif /* LWIP_DEBUG && LWIP_TCPDUMP */ + +#include "lwip/tcp.h" +#include "lwip/ip.h" + +static void +loopif_input( void * arg ) +{ + struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] ); + struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] ); + + mem_free( arg ); + netif -> input( r, netif ); +} + +static err_t +loopif_output(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr) +{ + struct pbuf *q, *r; + u8_t *ptr; + void **arg; + +#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP) + tcpdump(p); +#endif /* LWIP_DEBUG && LWIP_TCPDUMP */ + + r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if (r != NULL) { + ptr = r->payload; + + for(q = p; q != NULL; q = q->next) { + memcpy(ptr, q->payload, q->len); + ptr += q->len; + } + + arg = mem_malloc( sizeof( void *[2])); + if( NULL == arg ) { + return ERR_MEM; + } + + arg[0] = netif; + arg[1] = r; + /** + * workaround (patch #1779) to try to prevent bug #2595: + * When connecting to "localhost" with the loopif interface, + * tcp_output doesn't get the opportunity to finnish sending the + * segment before tcp_process gets it, resulting in tcp_process + * referencing pcb->unacked-> which still is NULL. + * + * TODO: Is there still a race condition here? Leon + */ + sys_timeout( 1, loopif_input, arg ); + + return ERR_OK; + } + return ERR_MEM; +} + +err_t +loopif_init(struct netif *netif) +{ + netif->name[0] = 'l'; + netif->name[1] = 'o'; +#if 0 /** TODO: I think this should be enabled, or not? Leon */ + netif->input = loopif_input; +#endif + netif->output = loopif_output; + return ERR_OK; +} + +#endif /* LWIP_HAVE_LOOPIF */ + + + + + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/auth.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/auth.c new file mode 100644 index 0000000..0786a2e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/auth.c @@ -0,0 +1,927 @@ +/***************************************************************************** +* auth.c - Network Authentication and Phase Control program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-08 Guy Lancaster , Global Election Systems Inc. +* Ported from public pppd code. +*****************************************************************************/ +/* + * auth.c - PPP authentication and phase control. + * + * Copyright (c) 1993 The Australian National University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the Australian National University. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "fsm.h" +#include "lcp.h" +#include "pap.h" +#include "chap.h" +#include "auth.h" +#include "ipcp.h" + +#if CBCP_SUPPORT > 0 +#include "cbcp.h" +#endif + +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + +/* Bits in auth_pending[] */ +#define PAP_WITHPEER 1 +#define PAP_PEER 2 +#define CHAP_WITHPEER 4 +#define CHAP_PEER 8 + + + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ +/* Used for storing a sequence of words. Usually malloced. */ +struct wordlist { + struct wordlist *next; + char word[1]; +}; + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +extern char *crypt (const char *, const char *); + +/* Prototypes for procedures local to this file. */ + +static void network_phase (int); +static void check_idle (void *); +static void connect_time_expired (void *); +#if 0 +static int login (char *, char *, char **, int *); +#endif +static void logout (void); +static int null_login (int); +static int get_pap_passwd (int, char *, char *); +static int have_pap_secret (void); +static int have_chap_secret (char *, char *, u32_t); +static int ip_addr_check (u32_t, struct wordlist *); +#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */ +static void set_allowed_addrs(int unit, struct wordlist *addrs); +static void free_wordlist (struct wordlist *); +#endif +#if CBCP_SUPPORT > 0 +static void callback_phase (int); +#endif + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 +/* The name by which the peer authenticated itself to us. */ +static char peer_authname[MAXNAMELEN]; +#endif + +/* Records which authentication operations haven't completed yet. */ +static int auth_pending[NUM_PPP]; + +/* Set if we have successfully called login() */ +static int logged_in; + +/* Set if we have run the /etc/ppp/auth-up script. */ +static int did_authup; + +/* List of addresses which the peer may use. */ +static struct wordlist *addresses[NUM_PPP]; + +/* Number of network protocols which we have opened. */ +static int num_np_open; + +/* Number of network protocols which have come up. */ +static int num_np_up; + +#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 +/* Set if we got the contents of passwd[] from the pap-secrets file. */ +static int passwd_from_file; +#endif + + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * An Open on LCP has requested a change from Dead to Establish phase. + * Do what's necessary to bring the physical layer up. + */ +void link_required(int unit) +{ + AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit)); +} + +/* + * LCP has terminated the link; go to the Dead phase and take the + * physical layer down. + */ +void link_terminated(int unit) +{ + AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit)); + + if (lcp_phase[unit] == PHASE_DEAD) + return; + if (logged_in) + logout(); + lcp_phase[unit] = PHASE_DEAD; + AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n")); + pppMainWakeup(unit); +} + +/* + * LCP has gone down; it will either die or try to re-establish. + */ +void link_down(int unit) +{ + int i; + struct protent *protp; + + AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit)); + if (did_authup) { + /* XXX Do link down processing. */ + did_authup = 0; + } + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { + if (!protp->enabled_flag) + continue; + if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) + (*protp->lowerdown)(unit); + if (protp->protocol < 0xC000 && protp->close != NULL) + (*protp->close)(unit, "LCP down"); + } + num_np_open = 0; + num_np_up = 0; + if (lcp_phase[unit] != PHASE_DEAD) + lcp_phase[unit] = PHASE_TERMINATE; + pppMainWakeup(unit); +} + +/* + * The link is established. + * Proceed to the Dead, Authenticate or Network phase as appropriate. + */ +void link_established(int unit) +{ + int auth; + int i; + struct protent *protp; + lcp_options *wo = &lcp_wantoptions[unit]; + lcp_options *go = &lcp_gotoptions[unit]; +#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 + lcp_options *ho = &lcp_hisoptions[unit]; +#endif + + AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit)); + /* + * Tell higher-level protocols that LCP is up. + */ + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) + if (protp->protocol != PPP_LCP && protp->enabled_flag + && protp->lowerup != NULL) + (*protp->lowerup)(unit); + + if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) { + /* + * We wanted the peer to authenticate itself, and it refused: + * treat it as though it authenticated with PAP using a username + * of "" and a password of "". If that's not OK, boot it out. + */ + if (!wo->neg_upap || !null_login(unit)) { + AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n")); + lcp_close(unit, "peer refused to authenticate"); + return; + } + } + + lcp_phase[unit] = PHASE_AUTHENTICATE; + auth = 0; +#if CHAP_SUPPORT > 0 + if (go->neg_chap) { + ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype); + auth |= CHAP_PEER; + } +#endif +#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0 + else +#endif +#if PAP_SUPPORT > 0 + if (go->neg_upap) { + upap_authpeer(unit); + auth |= PAP_PEER; + } +#endif +#if CHAP_SUPPORT > 0 + if (ho->neg_chap) { + ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype); + auth |= CHAP_WITHPEER; + } +#endif +#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0 + else +#endif +#if PAP_SUPPORT > 0 + if (ho->neg_upap) { + if (ppp_settings.passwd[0] == 0) { + passwd_from_file = 1; + if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd)) + AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n")); + } + upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd); + auth |= PAP_WITHPEER; + } +#endif + auth_pending[unit] = auth; + + if (!auth) + network_phase(unit); +} + + +/* + * The peer has failed to authenticate himself using `protocol'. + */ +void auth_peer_fail(int unit, u16_t protocol) +{ + AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol)); + /* + * Authentication failure: take the link down + */ + lcp_close(unit, "Authentication failed"); +} + + +#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 +/* + * The peer has been successfully authenticated using `protocol'. + */ +void auth_peer_success(int unit, u16_t protocol, char *name, int namelen) +{ + int pbit; + + AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol)); + switch (protocol) { + case PPP_CHAP: + pbit = CHAP_PEER; + break; + case PPP_PAP: + pbit = PAP_PEER; + break; + default: + AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", + protocol)); + return; + } + + /* + * Save the authenticated name of the peer for later. + */ + if (namelen > sizeof(peer_authname) - 1) + namelen = sizeof(peer_authname) - 1; + BCOPY(name, peer_authname, namelen); + peer_authname[namelen] = 0; + + /* + * If there is no more authentication still to be done, + * proceed to the network (or callback) phase. + */ + if ((auth_pending[unit] &= ~pbit) == 0) + network_phase(unit); +} + +/* + * We have failed to authenticate ourselves to the peer using `protocol'. + */ +void auth_withpeer_fail(int unit, u16_t protocol) +{ + int errCode = PPPERR_AUTHFAIL; + + AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol)); + if (passwd_from_file) + BZERO(ppp_settings.passwd, MAXSECRETLEN); + /* + * XXX Warning: the unit number indicates the interface which is + * not necessarily the PPP connection. It works here as long + * as we are only supporting PPP interfaces. + */ + pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode); + + /* + * We've failed to authenticate ourselves to our peer. + * He'll probably take the link down, and there's not much + * we can do except wait for that. + */ +} + +/* + * We have successfully authenticated ourselves with the peer using `protocol'. + */ +void auth_withpeer_success(int unit, u16_t protocol) +{ + int pbit; + + AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol)); + switch (protocol) { + case PPP_CHAP: + pbit = CHAP_WITHPEER; + break; + case PPP_PAP: + if (passwd_from_file) + BZERO(ppp_settings.passwd, MAXSECRETLEN); + pbit = PAP_WITHPEER; + break; + default: + AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", + protocol)); + pbit = 0; + } + + /* + * If there is no more authentication still being done, + * proceed to the network (or callback) phase. + */ + if ((auth_pending[unit] &= ~pbit) == 0) + network_phase(unit); +} +#endif + + +/* + * np_up - a network protocol has come up. + */ +void np_up(int unit, u16_t proto) +{ + AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto)); + if (num_np_up == 0) { + AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit)); + /* + * At this point we consider that the link has come up successfully. + */ + if (ppp_settings.idle_time_limit > 0) + TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit); + + /* + * Set a timeout to close the connection once the maximum + * connect time has expired. + */ + if (ppp_settings.maxconnect > 0) + TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect); + } + ++num_np_up; +} + +/* + * np_down - a network protocol has gone down. + */ +void np_down(int unit, u16_t proto) +{ + AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto)); + if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) { + UNTIMEOUT(check_idle, NULL); + } +} + +/* + * np_finished - a network protocol has finished using the link. + */ +void np_finished(int unit, u16_t proto) +{ + AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto)); + if (--num_np_open <= 0) { + /* no further use for the link: shut up shop. */ + lcp_close(0, "No network protocols running"); + } +} + +/* + * auth_reset - called when LCP is starting negotiations to recheck + * authentication options, i.e. whether we have appropriate secrets + * to use for authenticating ourselves and/or the peer. + */ +void auth_reset(int unit) +{ + lcp_options *go = &lcp_gotoptions[unit]; + lcp_options *ao = &lcp_allowoptions[0]; + ipcp_options *ipwo = &ipcp_wantoptions[0]; + u32_t remote; + + AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit)); + ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL)); + ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/; + + if (go->neg_upap && !have_pap_secret()) + go->neg_upap = 0; + if (go->neg_chap) { + remote = ipwo->accept_remote? 0: ipwo->hisaddr; + if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote)) + go->neg_chap = 0; + } +} + + +#if PAP_SUPPORT > 0 +/* + * check_passwd - Check the user name and passwd against the PAP secrets + * file. If requested, also check against the system password database, + * and login the user if OK. + * + * returns: + * UPAP_AUTHNAK: Authentication failed. + * UPAP_AUTHACK: Authentication succeeded. + * In either case, msg points to an appropriate message. + */ +int check_passwd( + int unit, + char *auser, + int userlen, + char *apasswd, + int passwdlen, + char **msg, + int *msglen +) +{ +#if 1 + *msg = (char *) 0; + return UPAP_AUTHACK; /* XXX Assume all entries OK. */ +#else + int ret = 0; + struct wordlist *addrs = NULL; + char passwd[256], user[256]; + char secret[MAXWORDLEN]; + static u_short attempts = 0; + + /* + * Make copies of apasswd and auser, then null-terminate them. + */ + BCOPY(apasswd, passwd, passwdlen); + passwd[passwdlen] = '\0'; + BCOPY(auser, user, userlen); + user[userlen] = '\0'; + *msg = (char *) 0; + + /* XXX Validate user name and password. */ + ret = UPAP_AUTHACK; /* XXX Assume all entries OK. */ + + if (ret == UPAP_AUTHNAK) { + if (*msg == (char *) 0) + *msg = "Login incorrect"; + *msglen = strlen(*msg); + /* + * Frustrate passwd stealer programs. + * Allow 10 tries, but start backing off after 3 (stolen from login). + * On 10'th, drop the connection. + */ + if (attempts++ >= 10) { + AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user)); + /*ppp_panic("Excess Bad Logins");*/ + } + if (attempts > 3) { + sys_msleep((attempts - 3) * 5); + } + if (addrs != NULL) { + free_wordlist(addrs); + } + } else { + attempts = 0; /* Reset count */ + if (*msg == (char *) 0) + *msg = "Login ok"; + *msglen = strlen(*msg); + set_allowed_addrs(unit, addrs); + } + + BZERO(passwd, sizeof(passwd)); + BZERO(secret, sizeof(secret)); + + return ret; +#endif +} +#endif + + +/* + * auth_ip_addr - check whether the peer is authorized to use + * a given IP address. Returns 1 if authorized, 0 otherwise. + */ +int auth_ip_addr(int unit, u32_t addr) +{ + return ip_addr_check(addr, addresses[unit]); +} + +/* + * bad_ip_adrs - return 1 if the IP address is one we don't want + * to use, such as an address in the loopback net or a multicast address. + * addr is in network byte order. + */ +int bad_ip_adrs(u32_t addr) +{ + addr = ntohl(addr); + return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET + || IN_MULTICAST(addr) || IN_BADCLASS(addr); +} + + +#if CHAP_SUPPORT > 0 +/* + * get_secret - open the CHAP secret file and return the secret + * for authenticating the given client on the given server. + * (We could be either client or server). + */ +int get_secret( + int unit, + char *client, + char *server, + char *secret, + int *secret_len, + int save_addrs +) +{ +#if 1 + int len; + struct wordlist *addrs; + + addrs = NULL; + + if(!client || !client[0] || strcmp(client, ppp_settings.user)) { + return 0; + } + + len = strlen(ppp_settings.passwd); + if (len > MAXSECRETLEN) { + AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); + len = MAXSECRETLEN; + } + BCOPY(ppp_settings.passwd, secret, len); + *secret_len = len; + + return 1; +#else + int ret = 0, len; + struct wordlist *addrs; + char secbuf[MAXWORDLEN]; + + addrs = NULL; + secbuf[0] = 0; + + /* XXX Find secret. */ + if (ret < 0) + return 0; + + if (save_addrs) + set_allowed_addrs(unit, addrs); + + len = strlen(secbuf); + if (len > MAXSECRETLEN) { + AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); + len = MAXSECRETLEN; + } + BCOPY(secbuf, secret, len); + BZERO(secbuf, sizeof(secbuf)); + *secret_len = len; + + return 1; +#endif +} +#endif + + +#if 0 /* UNUSED */ +/* + * auth_check_options - called to check authentication options. + */ +void auth_check_options(void) +{ + lcp_options *wo = &lcp_wantoptions[0]; + int can_auth; + ipcp_options *ipwo = &ipcp_wantoptions[0]; + u32_t remote; + + /* Default our_name to hostname, and user to our_name */ + if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname) + strcpy(ppp_settings.our_name, ppp_settings.hostname); + if (ppp_settings.user[0] == 0) + strcpy(ppp_settings.user, ppp_settings.our_name); + + /* If authentication is required, ask peer for CHAP or PAP. */ + if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) { + wo->neg_chap = 1; + wo->neg_upap = 1; + } + + /* + * Check whether we have appropriate secrets to use + * to authenticate the peer. + */ + can_auth = wo->neg_upap && have_pap_secret(); + if (!can_auth && wo->neg_chap) { + remote = ipwo->accept_remote? 0: ipwo->hisaddr; + can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote); + } + + if (ppp_settings.auth_required && !can_auth) { + ppp_panic("No auth secret"); + } +} +#endif + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* + * Proceed to the network phase. + */ +static void network_phase(int unit) +{ + int i; + struct protent *protp; + lcp_options *go = &lcp_gotoptions[unit]; + + /* + * If the peer had to authenticate, run the auth-up script now. + */ + if ((go->neg_chap || go->neg_upap) && !did_authup) { + /* XXX Do setup for peer authentication. */ + did_authup = 1; + } + +#if CBCP_SUPPORT > 0 + /* + * If we negotiated callback, do it now. + */ + if (go->neg_cbcp) { + lcp_phase[unit] = PHASE_CALLBACK; + (*cbcp_protent.open)(unit); + return; + } +#endif + + lcp_phase[unit] = PHASE_NETWORK; + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) + if (protp->protocol < 0xC000 && protp->enabled_flag + && protp->open != NULL) { + (*protp->open)(unit); + if (protp->protocol != PPP_CCP) + ++num_np_open; + } + + if (num_np_open == 0) + /* nothing to do */ + lcp_close(0, "No network protocols running"); +} + +/* + * check_idle - check whether the link has been idle for long + * enough that we can shut it down. + */ +static void check_idle(void *arg) +{ + struct ppp_idle idle; + u_short itime; + + (void)arg; + if (!get_idle_time(0, &idle)) + return; + itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle); + if (itime >= ppp_settings.idle_time_limit) { + /* link is idle: shut it down. */ + AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n")); + lcp_close(0, "Link inactive"); + } else { + TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime); + } +} + +/* + * connect_time_expired - log a message and close the connection. + */ +static void connect_time_expired(void *arg) +{ + (void)arg; + + AUTHDEBUG((LOG_INFO, "Connect time expired\n")); + lcp_close(0, "Connect time expired"); /* Close connection */ +} + +#if 0 +/* + * login - Check the user name and password against the system + * password database, and login the user if OK. + * + * returns: + * UPAP_AUTHNAK: Login failed. + * UPAP_AUTHACK: Login succeeded. + * In either case, msg points to an appropriate message. + */ +static int login(char *user, char *passwd, char **msg, int *msglen) +{ + /* XXX Fail until we decide that we want to support logins. */ + return (UPAP_AUTHNAK); +} +#endif + +/* + * logout - Logout the user. + */ +static void logout(void) +{ + logged_in = 0; +} + + +/* + * null_login - Check if a username of "" and a password of "" are + * acceptable, and iff so, set the list of acceptable IP addresses + * and return 1. + */ +static int null_login(int unit) +{ + (void)unit; + /* XXX Fail until we decide that we want to support logins. */ + return 0; +} + + +/* + * get_pap_passwd - get a password for authenticating ourselves with + * our peer using PAP. Returns 1 on success, 0 if no suitable password + * could be found. + */ +static int get_pap_passwd(int unit, char *user, char *passwd) +{ +/* normally we would reject PAP if no password is provided, + but this causes problems with some providers (like CHT in Taiwan) + who incorrectly request PAP and expect a bogus/empty password, so + always provide a default user/passwd of "none"/"none" +*/ + if(user) + strcpy(user, "none"); + if(passwd) + strcpy(passwd, "none"); + + return 1; +} + + +/* + * have_pap_secret - check whether we have a PAP file with any + * secrets that we could possibly use for authenticating the peer. + */ +static int have_pap_secret(void) +{ + /* XXX Fail until we set up our passwords. */ + return 0; +} + + +/* + * have_chap_secret - check whether we have a CHAP file with a + * secret that we could possibly use for authenticating `client' + * on `server'. Either can be the null string, meaning we don't + * know the identity yet. + */ +static int have_chap_secret(char *client, char *server, u32_t remote) +{ + (void)client; + (void)server; + (void)remote; + /* XXX Fail until we set up our passwords. */ + return 0; +} + + +#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */ +/* + * set_allowed_addrs() - set the list of allowed addresses. + */ +static void set_allowed_addrs(int unit, struct wordlist *addrs) +{ + if (addresses[unit] != NULL) + free_wordlist(addresses[unit]); + addresses[unit] = addrs; + +#if 0 + /* + * If there's only one authorized address we might as well + * ask our peer for that one right away + */ + if (addrs != NULL && addrs->next == NULL) { + char *p = addrs->word; + struct ipcp_options *wo = &ipcp_wantoptions[unit]; + u32_t a; + struct hostent *hp; + + if (wo->hisaddr == 0 && *p != '!' && *p != '-' + && strchr(p, '/') == NULL) { + hp = gethostbyname(p); + if (hp != NULL && hp->h_addrtype == AF_INET) + a = *(u32_t *)hp->h_addr; + else + a = inet_addr(p); + if (a != (u32_t) -1) + wo->hisaddr = a; + } + } +#endif +} +#endif + +static int ip_addr_check(u32_t addr, struct wordlist *addrs) +{ + + /* don't allow loopback or multicast address */ + if (bad_ip_adrs(addr)) + return 0; + + if (addrs == NULL) + return !ppp_settings.auth_required; /* no addresses authorized */ + + /* XXX All other addresses allowed. */ + return 1; +} + +#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */ +/* + * free_wordlist - release memory allocated for a wordlist. + */ +static void free_wordlist(struct wordlist *wp) +{ + struct wordlist *next; + + while (wp != NULL) { + next = wp->next; + free(wp); + wp = next; + } +} +#endif + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/auth.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/auth.h new file mode 100644 index 0000000..5817405 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/auth.h @@ -0,0 +1,94 @@ +/***************************************************************************** +* auth.h - PPP Authentication and phase control header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD pppd.h. +*****************************************************************************/ +/* + * pppd.h - PPP daemon global declarations. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef AUTH_H +#define AUTH_H + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ +void link_required (int); /* we are starting to use the link */ +void link_terminated (int); /* we are finished with the link */ +void link_down (int); /* the LCP layer has left the Opened state */ +void link_established (int); /* the link is up; authenticate now */ +void np_up (int, u16_t); /* a network protocol has come up */ +void np_down (int, u16_t); /* a network protocol has gone down */ +void np_finished (int, u16_t); /* a network protocol no longer needs link */ +void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */ + +/* peer successfully authenticated itself */ +void auth_peer_success (int, u16_t, char *, int); + +/* we failed to authenticate ourselves */ +void auth_withpeer_fail (int, u16_t); + +/* we successfully authenticated ourselves */ +void auth_withpeer_success (int, u16_t); + +/* check authentication options supplied */ +void auth_check_options (void); +void auth_reset (int); /* check what secrets we have */ + +/* Check peer-supplied username/password */ +int check_passwd (int, char *, int, char *, int, char **, int *); + +/* get "secret" for chap */ +int get_secret (int, char *, char *, char *, int *, int); + +/* check if IP address is authorized */ +int auth_ip_addr (int, u32_t); + +/* check if IP address is unreasonable */ +int bad_ip_adrs (u32_t); + + +#endif /* AUTH_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chap.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chap.c new file mode 100644 index 0000000..30441bd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chap.c @@ -0,0 +1,872 @@ +/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/ +/***************************************************************************** +* chap.c - Network Challenge Handshake Authentication Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD chap.c. +*****************************************************************************/ +/* + * chap.c - Challenge Handshake Authentication Protocol. + * + * Copyright (c) 1993 The Australian National University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the Australian National University. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Copyright (c) 1991 Gregory M. Christy. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Gregory M. Christy. The name of the author may not be used to + * endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "magic.h" + +#if CHAP_SUPPORT > 0 + +#include "randm.h" +#include "auth.h" +#include "md5.h" +#include "chap.h" +#include "chpms.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +/* + * Protocol entry points. + */ +static void ChapInit (int); +static void ChapLowerUp (int); +static void ChapLowerDown (int); +static void ChapInput (int, u_char *, int); +static void ChapProtocolReject (int); +static int ChapPrintPkt (u_char *, int, + void (*) (void *, char *, ...), void *); + +static void ChapChallengeTimeout (void *); +static void ChapResponseTimeout (void *); +static void ChapReceiveChallenge (chap_state *, u_char *, int, int); +static void ChapRechallenge (void *); +static void ChapReceiveResponse (chap_state *, u_char *, int, int); +static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len); +static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len); +static void ChapSendStatus (chap_state *, int); +static void ChapSendChallenge (chap_state *); +static void ChapSendResponse (chap_state *); +static void ChapGenChallenge (chap_state *); + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */ + +struct protent chap_protent = { + PPP_CHAP, + ChapInit, + ChapInput, + ChapProtocolReject, + ChapLowerUp, + ChapLowerDown, + NULL, + NULL, +#if 0 + ChapPrintPkt, + NULL, +#endif + 1, + "CHAP", +#if 0 + NULL, + NULL, + NULL +#endif +}; + + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static char *ChapCodenames[] = { + "Challenge", "Response", "Success", "Failure" +}; + + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * ChapAuthWithPeer - Authenticate us with our peer (start client). + * + */ +void ChapAuthWithPeer(int unit, char *our_name, int digest) +{ + chap_state *cstate = &chap[unit]; + + cstate->resp_name = our_name; + cstate->resp_type = digest; + + if (cstate->clientstate == CHAPCS_INITIAL || + cstate->clientstate == CHAPCS_PENDING) { + /* lower layer isn't up - wait until later */ + cstate->clientstate = CHAPCS_PENDING; + return; + } + + /* + * We get here as a result of LCP coming up. + * So even if CHAP was open before, we will + * have to re-authenticate ourselves. + */ + cstate->clientstate = CHAPCS_LISTEN; +} + + +/* + * ChapAuthPeer - Authenticate our peer (start server). + */ +void ChapAuthPeer(int unit, char *our_name, int digest) +{ + chap_state *cstate = &chap[unit]; + + cstate->chal_name = our_name; + cstate->chal_type = digest; + + if (cstate->serverstate == CHAPSS_INITIAL || + cstate->serverstate == CHAPSS_PENDING) { + /* lower layer isn't up - wait until later */ + cstate->serverstate = CHAPSS_PENDING; + return; + } + + ChapGenChallenge(cstate); + ChapSendChallenge(cstate); /* crank it up dude! */ + cstate->serverstate = CHAPSS_INITIAL_CHAL; +} + + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* + * ChapInit - Initialize a CHAP unit. + */ +static void ChapInit(int unit) +{ + chap_state *cstate = &chap[unit]; + + BZERO(cstate, sizeof(*cstate)); + cstate->unit = unit; + cstate->clientstate = CHAPCS_INITIAL; + cstate->serverstate = CHAPSS_INITIAL; + cstate->timeouttime = CHAP_DEFTIMEOUT; + cstate->max_transmits = CHAP_DEFTRANSMITS; + /* random number generator is initialized in magic_init */ +} + + +/* + * ChapChallengeTimeout - Timeout expired on sending challenge. + */ +static void ChapChallengeTimeout(void *arg) +{ + chap_state *cstate = (chap_state *) arg; + + /* if we aren't sending challenges, don't worry. then again we */ + /* probably shouldn't be here either */ + if (cstate->serverstate != CHAPSS_INITIAL_CHAL && + cstate->serverstate != CHAPSS_RECHALLENGE) + return; + + if (cstate->chal_transmits >= cstate->max_transmits) { + /* give up on peer */ + CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n")); + cstate->serverstate = CHAPSS_BADAUTH; + auth_peer_fail(cstate->unit, PPP_CHAP); + return; + } + + ChapSendChallenge(cstate); /* Re-send challenge */ +} + + +/* + * ChapResponseTimeout - Timeout expired on sending response. + */ +static void ChapResponseTimeout(void *arg) +{ + chap_state *cstate = (chap_state *) arg; + + /* if we aren't sending a response, don't worry. */ + if (cstate->clientstate != CHAPCS_RESPONSE) + return; + + ChapSendResponse(cstate); /* re-send response */ +} + + +/* + * ChapRechallenge - Time to challenge the peer again. + */ +static void ChapRechallenge(void *arg) +{ + chap_state *cstate = (chap_state *) arg; + + /* if we aren't sending a response, don't worry. */ + if (cstate->serverstate != CHAPSS_OPEN) + return; + + ChapGenChallenge(cstate); + ChapSendChallenge(cstate); + cstate->serverstate = CHAPSS_RECHALLENGE; +} + + +/* + * ChapLowerUp - The lower layer is up. + * + * Start up if we have pending requests. + */ +static void ChapLowerUp(int unit) +{ + chap_state *cstate = &chap[unit]; + + if (cstate->clientstate == CHAPCS_INITIAL) + cstate->clientstate = CHAPCS_CLOSED; + else if (cstate->clientstate == CHAPCS_PENDING) + cstate->clientstate = CHAPCS_LISTEN; + + if (cstate->serverstate == CHAPSS_INITIAL) + cstate->serverstate = CHAPSS_CLOSED; + else if (cstate->serverstate == CHAPSS_PENDING) { + ChapGenChallenge(cstate); + ChapSendChallenge(cstate); + cstate->serverstate = CHAPSS_INITIAL_CHAL; + } +} + + +/* + * ChapLowerDown - The lower layer is down. + * + * Cancel all timeouts. + */ +static void ChapLowerDown(int unit) +{ + chap_state *cstate = &chap[unit]; + + /* Timeout(s) pending? Cancel if so. */ + if (cstate->serverstate == CHAPSS_INITIAL_CHAL || + cstate->serverstate == CHAPSS_RECHALLENGE) + UNTIMEOUT(ChapChallengeTimeout, cstate); + else if (cstate->serverstate == CHAPSS_OPEN + && cstate->chal_interval != 0) + UNTIMEOUT(ChapRechallenge, cstate); + if (cstate->clientstate == CHAPCS_RESPONSE) + UNTIMEOUT(ChapResponseTimeout, cstate); + + cstate->clientstate = CHAPCS_INITIAL; + cstate->serverstate = CHAPSS_INITIAL; +} + + +/* + * ChapProtocolReject - Peer doesn't grok CHAP. + */ +static void ChapProtocolReject(int unit) +{ + chap_state *cstate = &chap[unit]; + + if (cstate->serverstate != CHAPSS_INITIAL && + cstate->serverstate != CHAPSS_CLOSED) + auth_peer_fail(unit, PPP_CHAP); + if (cstate->clientstate != CHAPCS_INITIAL && + cstate->clientstate != CHAPCS_CLOSED) + auth_withpeer_fail(unit, PPP_CHAP); + ChapLowerDown(unit); /* shutdown chap */ +} + + +/* + * ChapInput - Input CHAP packet. + */ +static void ChapInput(int unit, u_char *inpacket, int packet_len) +{ + chap_state *cstate = &chap[unit]; + u_char *inp; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + inp = inpacket; + if (packet_len < CHAP_HEADERLEN) { + CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < CHAP_HEADERLEN) { + CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n")); + return; + } + if (len > packet_len) { + CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n")); + return; + } + len -= CHAP_HEADERLEN; + + /* + * Action depends on code (as in fact it usually does :-). + */ + switch (code) { + case CHAP_CHALLENGE: + ChapReceiveChallenge(cstate, inp, id, len); + break; + + case CHAP_RESPONSE: + ChapReceiveResponse(cstate, inp, id, len); + break; + + case CHAP_FAILURE: + ChapReceiveFailure(cstate, inp, id, len); + break; + + case CHAP_SUCCESS: + ChapReceiveSuccess(cstate, inp, id, len); + break; + + default: /* Need code reject? */ + CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code)); + break; + } +} + + +/* + * ChapReceiveChallenge - Receive Challenge and send Response. + */ +static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len) +{ + int rchallenge_len; + u_char *rchallenge; + int secret_len; + char secret[MAXSECRETLEN]; + char rhostname[256]; + MD5_CTX mdContext; + u_char hash[MD5_SIGNATURE_SIZE]; + + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id)); + if (cstate->clientstate == CHAPCS_CLOSED || + cstate->clientstate == CHAPCS_PENDING) { + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n", + cstate->clientstate)); + return; + } + + if (len < 2) { + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); + return; + } + + GETCHAR(rchallenge_len, inp); + len -= sizeof (u_char) + rchallenge_len; /* now name field length */ + if (len < 0) { + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); + return; + } + rchallenge = inp; + INCPTR(rchallenge_len, inp); + + if (len >= sizeof(rhostname)) + len = sizeof(rhostname) - 1; + BCOPY(inp, rhostname, len); + rhostname[len] = '\000'; + + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n", + rhostname)); + + /* Microsoft doesn't send their name back in the PPP packet */ + if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) { + strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname)); + rhostname[sizeof(rhostname) - 1] = 0; + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n", + rhostname)); + } + + /* get secret for authenticating ourselves with the specified host */ + if (!get_secret(cstate->unit, cstate->resp_name, rhostname, + secret, &secret_len, 0)) { + secret_len = 0; /* assume null secret if can't find one */ + CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname)); + } + + /* cancel response send timeout if necessary */ + if (cstate->clientstate == CHAPCS_RESPONSE) + UNTIMEOUT(ChapResponseTimeout, cstate); + + cstate->resp_id = id; + cstate->resp_transmits = 0; + + /* generate MD based on negotiated type */ + switch (cstate->resp_type) { + + case CHAP_DIGEST_MD5: + MD5Init(&mdContext); + MD5Update(&mdContext, &cstate->resp_id, 1); + MD5Update(&mdContext, (u_char*)secret, secret_len); + MD5Update(&mdContext, rchallenge, rchallenge_len); + MD5Final(hash, &mdContext); + BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE); + cstate->resp_length = MD5_SIGNATURE_SIZE; + break; + +#ifdef CHAPMS + case CHAP_MICROSOFT: + ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len); + break; +#endif + + default: + CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type)); + return; + } + + BZERO(secret, sizeof(secret)); + ChapSendResponse(cstate); +} + + +/* + * ChapReceiveResponse - Receive and process response. + */ +static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len) +{ + u_char *remmd, remmd_len; + int secret_len, old_state; + int code; + char rhostname[256]; + MD5_CTX mdContext; + char secret[MAXSECRETLEN]; + u_char hash[MD5_SIGNATURE_SIZE]; + + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id)); + + if (cstate->serverstate == CHAPSS_CLOSED || + cstate->serverstate == CHAPSS_PENDING) { + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n", + cstate->serverstate)); + return; + } + + if (id != cstate->chal_id) + return; /* doesn't match ID of last challenge */ + + /* + * If we have received a duplicate or bogus Response, + * we have to send the same answer (Success/Failure) + * as we did for the first Response we saw. + */ + if (cstate->serverstate == CHAPSS_OPEN) { + ChapSendStatus(cstate, CHAP_SUCCESS); + return; + } + if (cstate->serverstate == CHAPSS_BADAUTH) { + ChapSendStatus(cstate, CHAP_FAILURE); + return; + } + + if (len < 2) { + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); + return; + } + GETCHAR(remmd_len, inp); /* get length of MD */ + remmd = inp; /* get pointer to MD */ + INCPTR(remmd_len, inp); + + len -= sizeof (u_char) + remmd_len; + if (len < 0) { + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); + return; + } + + UNTIMEOUT(ChapChallengeTimeout, cstate); + + if (len >= sizeof(rhostname)) + len = sizeof(rhostname) - 1; + BCOPY(inp, rhostname, len); + rhostname[len] = '\000'; + + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n", + rhostname)); + + /* + * Get secret for authenticating them with us, + * do the hash ourselves, and compare the result. + */ + code = CHAP_FAILURE; + if (!get_secret(cstate->unit, rhostname, cstate->chal_name, + secret, &secret_len, 1)) { +/* CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */ + CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n", + rhostname)); + } else { + + /* generate MD based on negotiated type */ + switch (cstate->chal_type) { + + case CHAP_DIGEST_MD5: /* only MD5 is defined for now */ + if (remmd_len != MD5_SIGNATURE_SIZE) + break; /* it's not even the right length */ + MD5Init(&mdContext); + MD5Update(&mdContext, &cstate->chal_id, 1); + MD5Update(&mdContext, (u_char*)secret, secret_len); + MD5Update(&mdContext, cstate->challenge, cstate->chal_len); + MD5Final(hash, &mdContext); + + /* compare local and remote MDs and send the appropriate status */ + if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0) + code = CHAP_SUCCESS; /* they are the same! */ + break; + + default: + CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type)); + } + } + + BZERO(secret, sizeof(secret)); + ChapSendStatus(cstate, code); + + if (code == CHAP_SUCCESS) { + old_state = cstate->serverstate; + cstate->serverstate = CHAPSS_OPEN; + if (old_state == CHAPSS_INITIAL_CHAL) { + auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len); + } + if (cstate->chal_interval != 0) + TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval); + } else { + CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n")); + cstate->serverstate = CHAPSS_BADAUTH; + auth_peer_fail(cstate->unit, PPP_CHAP); + } +} + +/* + * ChapReceiveSuccess - Receive Success + */ +static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len) +{ + + CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id)); + + if (cstate->clientstate == CHAPCS_OPEN) + /* presumably an answer to a duplicate response */ + return; + + if (cstate->clientstate != CHAPCS_RESPONSE) { + /* don't know what this is */ + CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n", + cstate->clientstate)); + return; + } + + UNTIMEOUT(ChapResponseTimeout, cstate); + + /* + * Print message. + */ + if (len > 0) + PRINTMSG(inp, len); + + cstate->clientstate = CHAPCS_OPEN; + + auth_withpeer_success(cstate->unit, PPP_CHAP); +} + + +/* + * ChapReceiveFailure - Receive failure. + */ +static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len) +{ + CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id)); + + if (cstate->clientstate != CHAPCS_RESPONSE) { + /* don't know what this is */ + CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n", + cstate->clientstate)); + return; + } + + UNTIMEOUT(ChapResponseTimeout, cstate); + + /* + * Print message. + */ + if (len > 0) + PRINTMSG(inp, len); + + CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n")); + auth_withpeer_fail(cstate->unit, PPP_CHAP); +} + + +/* + * ChapSendChallenge - Send an Authenticate challenge. + */ +static void ChapSendChallenge(chap_state *cstate) +{ + u_char *outp; + int chal_len, name_len; + int outlen; + + chal_len = cstate->chal_len; + name_len = strlen(cstate->chal_name); + outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len; + outp = outpacket_buf[cstate->unit]; + + MAKEHEADER(outp, PPP_CHAP); /* paste in a CHAP header */ + + PUTCHAR(CHAP_CHALLENGE, outp); + PUTCHAR(cstate->chal_id, outp); + PUTSHORT(outlen, outp); + + PUTCHAR(chal_len, outp); /* put length of challenge */ + BCOPY(cstate->challenge, outp, chal_len); + INCPTR(chal_len, outp); + + BCOPY(cstate->chal_name, outp, name_len); /* append hostname */ + + pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); + + CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id)); + + TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime); + ++cstate->chal_transmits; +} + + +/* + * ChapSendStatus - Send a status response (ack or nak). + */ +static void ChapSendStatus(chap_state *cstate, int code) +{ + u_char *outp; + int outlen, msglen; + char msg[256]; + + if (code == CHAP_SUCCESS) + strcpy(msg, "Welcome!"); + else + strcpy(msg, "I don't like you. Go 'way."); + msglen = strlen(msg); + + outlen = CHAP_HEADERLEN + msglen; + outp = outpacket_buf[cstate->unit]; + + MAKEHEADER(outp, PPP_CHAP); /* paste in a header */ + + PUTCHAR(code, outp); + PUTCHAR(cstate->chal_id, outp); + PUTSHORT(outlen, outp); + BCOPY(msg, outp, msglen); + pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); + + CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code, + cstate->chal_id)); +} + +/* + * ChapGenChallenge is used to generate a pseudo-random challenge string of + * a pseudo-random length between min_len and max_len. The challenge + * string and its length are stored in *cstate, and various other fields of + * *cstate are initialized. + */ + +static void ChapGenChallenge(chap_state *cstate) +{ + int chal_len; + u_char *ptr = cstate->challenge; + int i; + + /* pick a random challenge length between MIN_CHALLENGE_LENGTH and + MAX_CHALLENGE_LENGTH */ + chal_len = (unsigned) + ((((magic() >> 16) * + (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16) + + MIN_CHALLENGE_LENGTH); + cstate->chal_len = chal_len; + cstate->chal_id = ++cstate->id; + cstate->chal_transmits = 0; + + /* generate a random string */ + for (i = 0; i < chal_len; i++ ) + *ptr++ = (char) (magic() & 0xff); +} + +/* + * ChapSendResponse - send a response packet with values as specified + * in *cstate. + */ +/* ARGSUSED */ +static void ChapSendResponse(chap_state *cstate) +{ + u_char *outp; + int outlen, md_len, name_len; + + md_len = cstate->resp_length; + name_len = strlen(cstate->resp_name); + outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len; + outp = outpacket_buf[cstate->unit]; + + MAKEHEADER(outp, PPP_CHAP); + + PUTCHAR(CHAP_RESPONSE, outp); /* we are a response */ + PUTCHAR(cstate->resp_id, outp); /* copy id from challenge packet */ + PUTSHORT(outlen, outp); /* packet length */ + + PUTCHAR(md_len, outp); /* length of MD */ + BCOPY(cstate->response, outp, md_len); /* copy MD to buffer */ + INCPTR(md_len, outp); + + BCOPY(cstate->resp_name, outp, name_len); /* append our name */ + + /* send the packet */ + pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); + + cstate->clientstate = CHAPCS_RESPONSE; + TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime); + ++cstate->resp_transmits; +} + +/* + * ChapPrintPkt - print the contents of a CHAP packet. + */ +static int ChapPrintPkt( + u_char *p, + int plen, + void (*printer) (void *, char *, ...), + void *arg +) +{ + int code, id, len; + int clen, nlen; + u_char x; + + if (plen < CHAP_HEADERLEN) + return 0; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < CHAP_HEADERLEN || len > plen) + return 0; + + if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *)) + printer(arg, " %s", ChapCodenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= CHAP_HEADERLEN; + switch (code) { + case CHAP_CHALLENGE: + case CHAP_RESPONSE: + if (len < 1) + break; + clen = p[0]; + if (len < clen + 1) + break; + ++p; + nlen = len - clen - 1; + printer(arg, " <"); + for (; clen > 0; --clen) { + GETCHAR(x, p); + printer(arg, "%.2x", x); + } + printer(arg, ">, name = %.*Z", nlen, p); + break; + case CHAP_FAILURE: + case CHAP_SUCCESS: + printer(arg, " %.*Z", len, p); + break; + default: + for (clen = len; clen > 0; --clen) { + GETCHAR(x, p); + printer(arg, " %.2x", x); + } + } + + return len + CHAP_HEADERLEN; +} + +#endif + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chap.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chap.h new file mode 100644 index 0000000..1aca134 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chap.h @@ -0,0 +1,167 @@ +/***************************************************************************** +* chap.h - Network Challenge Handshake Authentication Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-03 Guy Lancaster , Global Election Systems Inc. +* Original built from BSD network code. +******************************************************************************/ +/* + * chap.h - Challenge Handshake Authentication Protocol definitions. + * + * Copyright (c) 1993 The Australian National University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the Australian National University. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Copyright (c) 1991 Gregory M. Christy + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the author. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: chap.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef CHAP_H +#define CHAP_H + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ + +/* Code + ID + length */ +#define CHAP_HEADERLEN 4 + +/* + * CHAP codes. + */ + +#define CHAP_DIGEST_MD5 5 /* use MD5 algorithm */ +#define MD5_SIGNATURE_SIZE 16 /* 16 bytes in a MD5 message digest */ +#define CHAP_MICROSOFT 0x80 /* use Microsoft-compatible alg. */ +#define MS_CHAP_RESPONSE_LEN 49 /* Response length for MS-CHAP */ + +#define CHAP_CHALLENGE 1 +#define CHAP_RESPONSE 2 +#define CHAP_SUCCESS 3 +#define CHAP_FAILURE 4 + +/* + * Challenge lengths (for challenges we send) and other limits. + */ +#define MIN_CHALLENGE_LENGTH 32 +#define MAX_CHALLENGE_LENGTH 64 +#define MAX_RESPONSE_LENGTH 64 /* sufficient for MD5 or MS-CHAP */ + +/* + * Client (peer) states. + */ +#define CHAPCS_INITIAL 0 /* Lower layer down, not opened */ +#define CHAPCS_CLOSED 1 /* Lower layer up, not opened */ +#define CHAPCS_PENDING 2 /* Auth us to peer when lower up */ +#define CHAPCS_LISTEN 3 /* Listening for a challenge */ +#define CHAPCS_RESPONSE 4 /* Sent response, waiting for status */ +#define CHAPCS_OPEN 5 /* We've received Success */ + +/* + * Server (authenticator) states. + */ +#define CHAPSS_INITIAL 0 /* Lower layer down, not opened */ +#define CHAPSS_CLOSED 1 /* Lower layer up, not opened */ +#define CHAPSS_PENDING 2 /* Auth peer when lower up */ +#define CHAPSS_INITIAL_CHAL 3 /* We've sent the first challenge */ +#define CHAPSS_OPEN 4 /* We've sent a Success msg */ +#define CHAPSS_RECHALLENGE 5 /* We've sent another challenge */ +#define CHAPSS_BADAUTH 6 /* We've sent a Failure msg */ + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * Each interface is described by a chap structure. + */ + +typedef struct chap_state { + int unit; /* Interface unit number */ + int clientstate; /* Client state */ + int serverstate; /* Server state */ + u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */ + u_char chal_len; /* challenge length */ + u_char chal_id; /* ID of last challenge */ + u_char chal_type; /* hash algorithm for challenges */ + u_char id; /* Current id */ + char *chal_name; /* Our name to use with challenge */ + int chal_interval; /* Time until we challenge peer again */ + int timeouttime; /* Timeout time in seconds */ + int max_transmits; /* Maximum # of challenge transmissions */ + int chal_transmits; /* Number of transmissions of challenge */ + int resp_transmits; /* Number of transmissions of response */ + u_char response[MAX_RESPONSE_LENGTH]; /* Response to send */ + u_char resp_length; /* length of response */ + u_char resp_id; /* ID for response messages */ + u_char resp_type; /* hash algorithm for responses */ + char *resp_name; /* Our name to send with response */ +} chap_state; + + +/****************** +*** PUBLIC DATA *** +******************/ +extern chap_state chap[]; + +extern struct protent chap_protent; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +void ChapAuthWithPeer (int, char *, int); +void ChapAuthPeer (int, char *, int); + +#endif /* CHAP_H */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chpms.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chpms.c new file mode 100644 index 0000000..3064344 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chpms.c @@ -0,0 +1,398 @@ +/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/ +/***************************************************************************** +* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-08 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD chap_ms.c. +*****************************************************************************/ +/* + * chap_ms.c - Microsoft MS-CHAP compatible implementation. + * + * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. + * http://www.strataware.com/ + * + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Eric Rosenquist. The name of the author may not be used to + * endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* + * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997 + * + * Implemented LANManager type password response to MS-CHAP challenges. + * Now pppd provides both NT style and LANMan style blocks, and the + * prefered is set by option "ms-lanman". Default is to use NT. + * The hash text (StdText) was taken from Win95 RASAPI32.DLL. + * + * You should also use DOMAIN\\USERNAME as described in README.MSCHAP80 + */ + +#define USE_CRYPT + + +#include "ppp.h" + +#if MSCHAP_SUPPORT > 0 + +#include "md4.h" +#ifndef USE_CRYPT +#include "des.h" +#endif +#include "chap.h" +#include "chpms.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ +typedef struct { + u_char LANManResp[24]; + u_char NTResp[24]; + u_char UseNT; /* If 1, ignore the LANMan response field */ +} MS_ChapResponse; +/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse), + in case this struct gets padded. */ + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ + +/* XXX Don't know what to do with these. */ +extern void setkey(const char *); +extern void encrypt(char *, int); + +static void DesEncrypt (u_char *, u_char *, u_char *); +static void MakeKey (u_char *, u_char *); + +#ifdef USE_CRYPT +static void Expand (u_char *, u_char *); +static void Collapse (u_char *, u_char *); +#endif + +static void ChallengeResponse( + u_char *challenge, /* IN 8 octets */ + u_char *pwHash, /* IN 16 octets */ + u_char *response /* OUT 24 octets */ +); +static void ChapMS_NT( + char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len, + MS_ChapResponse *response +); +static u_char Get7Bits( + u_char *input, + int startBit +); + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +void ChapMS( + chap_state *cstate, + char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len +) +{ + MS_ChapResponse response; +#ifdef MSLANMAN + extern int ms_lanman; +#endif + +#if 0 + CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret)); +#endif + BZERO(&response, sizeof(response)); + + /* Calculate both always */ + ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response); + +#ifdef MSLANMAN + ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response); + + /* prefered method is set by option */ + response.UseNT = !ms_lanman; +#else + response.UseNT = 1; +#endif + + BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN); + cstate->resp_length = MS_CHAP_RESPONSE_LEN; +} + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +static void ChallengeResponse( + u_char *challenge, /* IN 8 octets */ + u_char *pwHash, /* IN 16 octets */ + u_char *response /* OUT 24 octets */ +) +{ + char ZPasswordHash[21]; + + BZERO(ZPasswordHash, sizeof(ZPasswordHash)); + BCOPY(pwHash, ZPasswordHash, 16); + +#if 0 + log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG); +#endif + + DesEncrypt(challenge, ZPasswordHash + 0, response + 0); + DesEncrypt(challenge, ZPasswordHash + 7, response + 8); + DesEncrypt(challenge, ZPasswordHash + 14, response + 16); + +#if 0 + log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG); +#endif +} + + +#ifdef USE_CRYPT +static void DesEncrypt( + u_char *clear, /* IN 8 octets */ + u_char *key, /* IN 7 octets */ + u_char *cipher /* OUT 8 octets */ +) +{ + u_char des_key[8]; + u_char crypt_key[66]; + u_char des_input[66]; + + MakeKey(key, des_key); + + Expand(des_key, crypt_key); + setkey(crypt_key); + +#if 0 + CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", + clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); +#endif + + Expand(clear, des_input); + encrypt(des_input, 0); + Collapse(des_input, cipher); + +#if 0 + CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", + cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); +#endif +} + +#else /* USE_CRYPT */ + +static void DesEncrypt( + u_char *clear, /* IN 8 octets */ + u_char *key, /* IN 7 octets */ + u_char *cipher /* OUT 8 octets */ +) +{ + des_cblock des_key; + des_key_schedule key_schedule; + + MakeKey(key, des_key); + + des_set_key(&des_key, key_schedule); + +#if 0 + CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", + clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); +#endif + + des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1); + +#if 0 + CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", + cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); +#endif +} + +#endif /* USE_CRYPT */ + + +static u_char Get7Bits( + u_char *input, + int startBit +) +{ + register unsigned int word; + + word = (unsigned)input[startBit / 8] << 8; + word |= (unsigned)input[startBit / 8 + 1]; + + word >>= 15 - (startBit % 8 + 7); + + return word & 0xFE; +} + +#ifdef USE_CRYPT + +/* in == 8-byte string (expanded version of the 56-bit key) + * out == 64-byte string where each byte is either 1 or 0 + * Note that the low-order "bit" is always ignored by by setkey() + */ +static void Expand(u_char *in, u_char *out) +{ + int j, c; + int i; + + for(i = 0; i < 64; in++){ + c = *in; + for(j = 7; j >= 0; j--) + *out++ = (c >> j) & 01; + i += 8; + } +} + +/* The inverse of Expand + */ +static void Collapse(u_char *in, u_char *out) +{ + int j; + int i; + unsigned int c; + + for (i = 0; i < 64; i += 8, out++) { + c = 0; + for (j = 7; j >= 0; j--, in++) + c |= *in << j; + *out = c & 0xff; + } +} +#endif + +static void MakeKey( + u_char *key, /* IN 56 bit DES key missing parity bits */ + u_char *des_key /* OUT 64 bit DES key with parity bits added */ +) +{ + des_key[0] = Get7Bits(key, 0); + des_key[1] = Get7Bits(key, 7); + des_key[2] = Get7Bits(key, 14); + des_key[3] = Get7Bits(key, 21); + des_key[4] = Get7Bits(key, 28); + des_key[5] = Get7Bits(key, 35); + des_key[6] = Get7Bits(key, 42); + des_key[7] = Get7Bits(key, 49); + +#ifndef USE_CRYPT + des_set_odd_parity((des_cblock *)des_key); +#endif + +#if 0 + CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n", + key[0], key[1], key[2], key[3], key[4], key[5], key[6])); + CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n", + des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7])); +#endif +} + +static void ChapMS_NT( + char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len, + MS_ChapResponse *response +) +{ + int i; + MDstruct md4Context; + u_char unicodePassword[MAX_NT_PASSWORD * 2]; + static int low_byte_first = -1; + + /* Initialize the Unicode version of the secret (== password). */ + /* This implicitly supports 8-bit ISO8859/1 characters. */ + BZERO(unicodePassword, sizeof(unicodePassword)); + for (i = 0; i < secret_len; i++) + unicodePassword[i * 2] = (u_char)secret[i]; + + MDbegin(&md4Context); + MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8); /* Unicode is 2 bytes/char, *8 for bit count */ + + if (low_byte_first == -1) + low_byte_first = (htons((unsigned short int)1) != 1); + if (low_byte_first == 0) + MDreverse((u_long *)&md4Context); /* sfb 961105 */ + + MDupdate(&md4Context, NULL, 0); /* Tell MD4 we're done */ + + ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp); +} + +#ifdef MSLANMAN +static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */ + +static ChapMS_LANMan( + char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len, + MS_ChapResponse *response +) +{ + int i; + u_char UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */ + u_char PasswordHash[16]; + + /* LANMan password is case insensitive */ + BZERO(UcasePassword, sizeof(UcasePassword)); + for (i = 0; i < secret_len; i++) + UcasePassword[i] = (u_char)toupper(secret[i]); + DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 ); + DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 ); + ChallengeResponse(rchallenge, PasswordHash, response->LANManResp); +} +#endif + +#endif /* MSCHAP_SUPPORT */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chpms.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chpms.h new file mode 100644 index 0000000..0b30c65 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/chpms.h @@ -0,0 +1,64 @@ +/***************************************************************************** +* chpms.h - Network Microsoft Challenge Handshake Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-01-30 Guy Lancaster , Global Election Systems Inc. +* Original built from BSD network code. +******************************************************************************/ +/* + * chap.h - Challenge Handshake Authentication Protocol definitions. + * + * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. + * http://www.strataware.com/ + * + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Eric Rosenquist. The name of the author may not be used to + * endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: chpms.h,v 1.3 2004/02/07 00:30:03 likewise Exp $ + */ + +#ifndef CHPMS_H +#define CHPMS_H + +#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */ + +void ChapMS (chap_state *, char *, int, char *, int); + +#endif /* CHPMS_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/fsm.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/fsm.c new file mode 100644 index 0000000..6cad715 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/fsm.c @@ -0,0 +1,838 @@ +/***************************************************************************** +* fsm.c - Network Control Protocol Finite State Machine program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-01 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD fsm.c. +*****************************************************************************/ +/* + * fsm.c - {Link, IP} Control Protocol Finite State Machine. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +/* + * TODO: + * Randomize fsm id on link/init. + * Deal with variable outgoing MTU. + */ + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "fsm.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +static void fsm_timeout (void *); +static void fsm_rconfreq (fsm *, u_char, u_char *, int); +static void fsm_rconfack (fsm *, int, u_char *, int); +static void fsm_rconfnakrej (fsm *, int, int, u_char *, int); +static void fsm_rtermreq (fsm *, int, u_char *, int); +static void fsm_rtermack (fsm *); +static void fsm_rcoderej (fsm *, u_char *, int); +static void fsm_sconfreq (fsm *, int); + +#define PROTO_NAME(f) ((f)->callbacks->proto_name) + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +int peer_mru[NUM_PPP]; + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ + +/* + * fsm_init - Initialize fsm. + * + * Initialize fsm state. + */ +void fsm_init(fsm *f) +{ + f->state = INITIAL; + f->flags = 0; + f->id = 0; /* XXX Start with random id? */ + f->timeouttime = FSM_DEFTIMEOUT; + f->maxconfreqtransmits = FSM_DEFMAXCONFREQS; + f->maxtermtransmits = FSM_DEFMAXTERMREQS; + f->maxnakloops = FSM_DEFMAXNAKLOOPS; + f->term_reason_len = 0; +} + + +/* + * fsm_lowerup - The lower layer is up. + */ +void fsm_lowerup(fsm *f) +{ + int oldState = f->state; + + switch( f->state ){ + case INITIAL: + f->state = CLOSED; + break; + + case STARTING: + if( f->flags & OPT_SILENT ) + f->state = STOPPED; + else { + /* Send an initial configure-request */ + fsm_sconfreq(f, 0); + f->state = REQSENT; + } + break; + + default: + FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n", + PROTO_NAME(f), f->state)); + } + + FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n", + PROTO_NAME(f), oldState, f->state)); +} + + +/* + * fsm_lowerdown - The lower layer is down. + * + * Cancel all timeouts and inform upper layers. + */ +void fsm_lowerdown(fsm *f) +{ + int oldState = f->state; + + switch( f->state ){ + case CLOSED: + f->state = INITIAL; + break; + + case STOPPED: + f->state = STARTING; + if( f->callbacks->starting ) + (*f->callbacks->starting)(f); + break; + + case CLOSING: + f->state = INITIAL; + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + break; + + case STOPPING: + case REQSENT: + case ACKRCVD: + case ACKSENT: + f->state = STARTING; + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + break; + + case OPENED: + if( f->callbacks->down ) + (*f->callbacks->down)(f); + f->state = STARTING; + break; + + default: + FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n", + PROTO_NAME(f), f->state)); + } + + FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n", + PROTO_NAME(f), oldState, f->state)); +} + + +/* + * fsm_open - Link is allowed to come up. + */ +void fsm_open(fsm *f) +{ + int oldState = f->state; + + switch( f->state ){ + case INITIAL: + f->state = STARTING; + if( f->callbacks->starting ) + (*f->callbacks->starting)(f); + break; + + case CLOSED: + if( f->flags & OPT_SILENT ) + f->state = STOPPED; + else { + /* Send an initial configure-request */ + fsm_sconfreq(f, 0); + f->state = REQSENT; + } + break; + + case CLOSING: + f->state = STOPPING; + /* fall through */ + case STOPPED: + case OPENED: + if( f->flags & OPT_RESTART ){ + fsm_lowerdown(f); + fsm_lowerup(f); + } + break; + } + + FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n", + PROTO_NAME(f), oldState, f->state)); +} + + +/* + * fsm_close - Start closing connection. + * + * Cancel timeouts and either initiate close or possibly go directly to + * the CLOSED state. + */ +void fsm_close(fsm *f, char *reason) +{ + int oldState = f->state; + + f->term_reason = reason; + f->term_reason_len = (reason == NULL? 0: strlen(reason)); + switch( f->state ){ + case STARTING: + f->state = INITIAL; + break; + case STOPPED: + f->state = CLOSED; + break; + case STOPPING: + f->state = CLOSING; + break; + + case REQSENT: + case ACKRCVD: + case ACKSENT: + case OPENED: + if( f->state != OPENED ) + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + else if( f->callbacks->down ) + (*f->callbacks->down)(f); /* Inform upper layers we're down */ + + /* Init restart counter, send Terminate-Request */ + f->retransmits = f->maxtermtransmits; + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, f->timeouttime); + --f->retransmits; + + f->state = CLOSING; + break; + } + + FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n", + PROTO_NAME(f), reason, oldState, f->state)); +} + + +/* + * fsm_sdata - Send some data. + * + * Used for all packets sent to our peer by this module. + */ +void fsm_sdata( + fsm *f, + u_char code, + u_char id, + u_char *data, + int datalen +) +{ + u_char *outp; + int outlen; + + /* Adjust length to be smaller than MTU */ + outp = outpacket_buf[f->unit]; + if (datalen > peer_mru[f->unit] - (int)HEADERLEN) + datalen = peer_mru[f->unit] - HEADERLEN; + if (datalen && data != outp + PPP_HDRLEN + HEADERLEN) + BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen); + outlen = datalen + HEADERLEN; + MAKEHEADER(outp, f->protocol); + PUTCHAR(code, outp); + PUTCHAR(id, outp); + PUTSHORT(outlen, outp); + pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN); + FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n", + PROTO_NAME(f), code, id, outlen)); +} + + +/* + * fsm_input - Input packet. + */ +void fsm_input(fsm *f, u_char *inpacket, int l) +{ + u_char *inp = inpacket; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + if (l < HEADERLEN) { + FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n", + f->protocol)); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < HEADERLEN) { + FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n", + f->protocol)); + return; + } + if (len > l) { + FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n", + f->protocol)); + return; + } + len -= HEADERLEN; /* subtract header length */ + + if( f->state == INITIAL || f->state == STARTING ){ + FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n", + f->protocol, f->state)); + return; + } + FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l)); + /* + * Action depends on code. + */ + switch (code) { + case CONFREQ: + fsm_rconfreq(f, id, inp, len); + break; + + case CONFACK: + fsm_rconfack(f, id, inp, len); + break; + + case CONFNAK: + case CONFREJ: + fsm_rconfnakrej(f, code, id, inp, len); + break; + + case TERMREQ: + fsm_rtermreq(f, id, inp, len); + break; + + case TERMACK: + fsm_rtermack(f); + break; + + case CODEREJ: + fsm_rcoderej(f, inp, len); + break; + + default: + if( !f->callbacks->extcode + || !(*f->callbacks->extcode)(f, code, id, inp, len) ) + fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN); + break; + } +} + + +/* + * fsm_protreject - Peer doesn't speak this protocol. + * + * Treat this as a catastrophic error (RXJ-). + */ +void fsm_protreject(fsm *f) +{ + switch( f->state ){ + case CLOSING: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + /* fall through */ + case CLOSED: + f->state = CLOSED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + + case STOPPING: + case REQSENT: + case ACKRCVD: + case ACKSENT: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + /* fall through */ + case STOPPED: + f->state = STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + + case OPENED: + if( f->callbacks->down ) + (*f->callbacks->down)(f); + + /* Init restart counter, send Terminate-Request */ + f->retransmits = f->maxtermtransmits; + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, f->timeouttime); + --f->retransmits; + + f->state = STOPPING; + break; + + default: + FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n", + PROTO_NAME(f), f->state)); + } +} + + + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ + +/* + * fsm_timeout - Timeout expired. + */ +static void fsm_timeout(void *arg) +{ + fsm *f = (fsm *) arg; + + switch (f->state) { + case CLOSING: + case STOPPING: + if( f->retransmits <= 0 ){ + FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n", + PROTO_NAME(f), f->state)); + /* + * We've waited for an ack long enough. Peer probably heard us. + */ + f->state = (f->state == CLOSING)? CLOSED: STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + } else { + FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n", + PROTO_NAME(f), f->state)); + /* Send Terminate-Request */ + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, f->timeouttime); + --f->retransmits; + } + break; + + case REQSENT: + case ACKRCVD: + case ACKSENT: + if (f->retransmits <= 0) { + FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n", + PROTO_NAME(f), f->state)); + f->state = STOPPED; + if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) + (*f->callbacks->finished)(f); + + } else { + FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n", + PROTO_NAME(f), f->state)); + /* Retransmit the configure-request */ + if (f->callbacks->retransmit) + (*f->callbacks->retransmit)(f); + fsm_sconfreq(f, 1); /* Re-send Configure-Request */ + if( f->state == ACKRCVD ) + f->state = REQSENT; + } + break; + + default: + FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n", + PROTO_NAME(f), f->state)); + } +} + + +/* + * fsm_rconfreq - Receive Configure-Request. + */ +static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len) +{ + int code, reject_if_disagree; + + FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", + PROTO_NAME(f), id, f->state)); + switch( f->state ){ + case CLOSED: + /* Go away, we're closed */ + fsm_sdata(f, TERMACK, id, NULL, 0); + return; + case CLOSING: + case STOPPING: + return; + + case OPENED: + /* Go down and restart negotiation */ + if( f->callbacks->down ) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + break; + + case STOPPED: + /* Negotiation started by our peer */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = REQSENT; + break; + } + + /* + * Pass the requested configuration options + * to protocol-specific code for checking. + */ + if (f->callbacks->reqci){ /* Check CI */ + reject_if_disagree = (f->nakloops >= f->maxnakloops); + code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree); + } + else if (len) + code = CONFREJ; /* Reject all CI */ + else + code = CONFACK; + + /* send the Ack, Nak or Rej to the peer */ + fsm_sdata(f, (u_char)code, id, inp, len); + + if (code == CONFACK) { + if (f->state == ACKRCVD) { + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + f->state = OPENED; + if (f->callbacks->up) + (*f->callbacks->up)(f); /* Inform upper layers */ + } + else + f->state = ACKSENT; + f->nakloops = 0; + } + else { + /* we sent CONFACK or CONFREJ */ + if (f->state != ACKRCVD) + f->state = REQSENT; + if( code == CONFNAK ) + ++f->nakloops; + } +} + + +/* + * fsm_rconfack - Receive Configure-Ack. + */ +static void fsm_rconfack(fsm *f, int id, u_char *inp, int len) +{ + FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n", + PROTO_NAME(f), id, f->state)); + + if (id != f->reqid || f->seen_ack) /* Expected id? */ + return; /* Nope, toss... */ + if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): + (len == 0)) ){ + /* Ack is bad - ignore it */ + FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n", + PROTO_NAME(f), len)); + return; + } + f->seen_ack = 1; + + switch (f->state) { + case CLOSED: + case STOPPED: + fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); + break; + + case REQSENT: + f->state = ACKRCVD; + f->retransmits = f->maxconfreqtransmits; + break; + + case ACKRCVD: + /* Huh? an extra valid Ack? oh well... */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + fsm_sconfreq(f, 0); + f->state = REQSENT; + break; + + case ACKSENT: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + f->state = OPENED; + f->retransmits = f->maxconfreqtransmits; + if (f->callbacks->up) + (*f->callbacks->up)(f); /* Inform upper layers */ + break; + + case OPENED: + /* Go down and restart negotiation */ + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = REQSENT; + break; + } +} + + +/* + * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject. + */ +static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len) +{ + int (*proc) (fsm *, u_char *, int); + int ret; + + FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n", + PROTO_NAME(f), id, f->state)); + + if (id != f->reqid || f->seen_ack) /* Expected id? */ + return; /* Nope, toss... */ + proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci; + if (!proc || !(ret = proc(f, inp, len))) { + /* Nak/reject is bad - ignore it */ + FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n", + PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len)); + return; + } + f->seen_ack = 1; + + switch (f->state) { + case CLOSED: + case STOPPED: + fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); + break; + + case REQSENT: + case ACKSENT: + /* They didn't agree to what we wanted - try another request */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + if (ret < 0) + f->state = STOPPED; /* kludge for stopping CCP */ + else + fsm_sconfreq(f, 0); /* Send Configure-Request */ + break; + + case ACKRCVD: + /* Got a Nak/reject when we had already had an Ack?? oh well... */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + fsm_sconfreq(f, 0); + f->state = REQSENT; + break; + + case OPENED: + /* Go down and restart negotiation */ + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = REQSENT; + break; + } +} + + +/* + * fsm_rtermreq - Receive Terminate-Req. + */ +static void fsm_rtermreq(fsm *f, int id, u_char *p, int len) +{ + FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n", + PROTO_NAME(f), id, f->state)); + + switch (f->state) { + case ACKRCVD: + case ACKSENT: + f->state = REQSENT; /* Start over but keep trying */ + break; + + case OPENED: + if (len > 0) { + FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p)); + } else { + FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f))); + } + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + f->retransmits = 0; + f->state = STOPPING; + TIMEOUT(fsm_timeout, f, f->timeouttime); + break; + } + + fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); +} + + +/* + * fsm_rtermack - Receive Terminate-Ack. + */ +static void fsm_rtermack(fsm *f) +{ + FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", + PROTO_NAME(f), f->state)); + + switch (f->state) { + case CLOSING: + UNTIMEOUT(fsm_timeout, f); + f->state = CLOSED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + case STOPPING: + UNTIMEOUT(fsm_timeout, f); + f->state = STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + + case ACKRCVD: + f->state = REQSENT; + break; + + case OPENED: + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); + break; + } +} + + +/* + * fsm_rcoderej - Receive an Code-Reject. + */ +static void fsm_rcoderej(fsm *f, u_char *inp, int len) +{ + u_char code, id; + + FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", + PROTO_NAME(f), f->state)); + + if (len < HEADERLEN) { + FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n", + PROTO_NAME(f), code, id)); + + if( f->state == ACKRCVD ) + f->state = REQSENT; +} + + +/* + * fsm_sconfreq - Send a Configure-Request. + */ +static void fsm_sconfreq(fsm *f, int retransmit) +{ + u_char *outp; + int cilen; + + if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){ + /* Not currently negotiating - reset options */ + if( f->callbacks->resetci ) + (*f->callbacks->resetci)(f); + f->nakloops = 0; + } + + if( !retransmit ){ + /* New request - reset retransmission counter, use new ID */ + f->retransmits = f->maxconfreqtransmits; + f->reqid = ++f->id; + } + + f->seen_ack = 0; + + /* + * Make up the request packet + */ + outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN; + if( f->callbacks->cilen && f->callbacks->addci ){ + cilen = (*f->callbacks->cilen)(f); + if( cilen > peer_mru[f->unit] - (int)HEADERLEN ) + cilen = peer_mru[f->unit] - HEADERLEN; + if (f->callbacks->addci) + (*f->callbacks->addci)(f, outp, &cilen); + } else + cilen = 0; + + /* send the request to our peer */ + fsm_sdata(f, CONFREQ, f->reqid, outp, cilen); + + /* start the retransmit timer */ + --f->retransmits; + TIMEOUT(fsm_timeout, f, f->timeouttime); + + FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n", + PROTO_NAME(f), f->reqid)); +} + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/fsm.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/fsm.h new file mode 100644 index 0000000..4cca402 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/fsm.h @@ -0,0 +1,187 @@ +/***************************************************************************** +* fsm.h - Network Control Protocol Finite State Machine header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD code. +*****************************************************************************/ +/* + * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: fsm.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef FSM_H +#define FSM_H + + +/***************************************************************************** +************************* PUBLIC DEFINITIONS ********************************* +*****************************************************************************/ +/* + * LCP Packet header = Code, id, length. + */ +#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) + + +/* + * CP (LCP, IPCP, etc.) codes. + */ +#define CONFREQ 1 /* Configuration Request */ +#define CONFACK 2 /* Configuration Ack */ +#define CONFNAK 3 /* Configuration Nak */ +#define CONFREJ 4 /* Configuration Reject */ +#define TERMREQ 5 /* Termination Request */ +#define TERMACK 6 /* Termination Ack */ +#define CODEREJ 7 /* Code Reject */ + +/* + * Link states. + */ +#define INITIAL 0 /* Down, hasn't been opened */ +#define STARTING 1 /* Down, been opened */ +#define CLOSED 2 /* Up, hasn't been opened */ +#define STOPPED 3 /* Open, waiting for down event */ +#define CLOSING 4 /* Terminating the connection, not open */ +#define STOPPING 5 /* Terminating, but open */ +#define REQSENT 6 /* We've sent a Config Request */ +#define ACKRCVD 7 /* We've received a Config Ack */ +#define ACKSENT 8 /* We've sent a Config Ack */ +#define OPENED 9 /* Connection available */ + + +/* + * Flags - indicate options controlling FSM operation + */ +#define OPT_PASSIVE 1 /* Don't die if we don't get a response */ +#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */ +#define OPT_SILENT 4 /* Wait for peer to speak first */ + + +/***************************************************************************** +************************* PUBLIC DATA TYPES ********************************** +*****************************************************************************/ +/* + * Each FSM is described by an fsm structure and fsm callbacks. + */ +typedef struct fsm { + int unit; /* Interface unit number */ + u_short protocol; /* Data Link Layer Protocol field value */ + int state; /* State */ + int flags; /* Contains option bits */ + u_char id; /* Current id */ + u_char reqid; /* Current request id */ + u_char seen_ack; /* Have received valid Ack/Nak/Rej to Req */ + int timeouttime; /* Timeout time in milliseconds */ + int maxconfreqtransmits;/* Maximum Configure-Request transmissions */ + int retransmits; /* Number of retransmissions left */ + int maxtermtransmits; /* Maximum Terminate-Request transmissions */ + int nakloops; /* Number of nak loops since last ack */ + int maxnakloops; /* Maximum number of nak loops tolerated */ + struct fsm_callbacks* callbacks;/* Callback routines */ + char* term_reason; /* Reason for closing protocol */ + int term_reason_len; /* Length of term_reason */ +} fsm; + + +typedef struct fsm_callbacks { + void (*resetci) /* Reset our Configuration Information */ + (fsm*); + int (*cilen) /* Length of our Configuration Information */ + (fsm*); + void (*addci) /* Add our Configuration Information */ + (fsm*, u_char*, int*); + int (*ackci) /* ACK our Configuration Information */ + (fsm*, u_char*, int); + int (*nakci) /* NAK our Configuration Information */ + (fsm*, u_char*, int); + int (*rejci) /* Reject our Configuration Information */ + (fsm*, u_char*, int); + int (*reqci) /* Request peer's Configuration Information */ + (fsm*, u_char*, int*, int); + void (*up) /* Called when fsm reaches OPENED state */ + (fsm*); + void (*down) /* Called when fsm leaves OPENED state */ + (fsm*); + void (*starting) /* Called when we want the lower layer */ + (fsm*); + void (*finished) /* Called when we don't want the lower layer */ + (fsm*); + void (*protreject) /* Called when Protocol-Reject received */ + (int); + void (*retransmit) /* Retransmission is necessary */ + (fsm*); + int (*extcode) /* Called when unknown code received */ + (fsm*, int, u_char, u_char*, int); + char *proto_name; /* String name for protocol (for messages) */ +} fsm_callbacks; + + +/***************************************************************************** +*********************** PUBLIC DATA STRUCTURES ******************************* +*****************************************************************************/ +/* + * Variables + */ +extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */ + + +/***************************************************************************** +************************** PUBLIC FUNCTIONS ********************************** +*****************************************************************************/ + +/* + * Prototypes + */ +void fsm_init (fsm*); +void fsm_lowerup (fsm*); +void fsm_lowerdown (fsm*); +void fsm_open (fsm*); +void fsm_close (fsm*, char*); +void fsm_input (fsm*, u_char*, int); +void fsm_protreject (fsm*); +void fsm_sdata (fsm*, u_char, u_char, u_char*, int); + + +#endif /* FSM_H */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ipcp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ipcp.c new file mode 100644 index 0000000..ec3207a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ipcp.c @@ -0,0 +1,1377 @@ +/***************************************************************************** +* ipcp.c - Network PPP IP Control Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-08 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ +/* + * ipcp.c - PPP IP Control Protocol. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "auth.h" +#include "fsm.h" +#include "vj.h" +#include "ipcp.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ +/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */ + +/* + * Lengths of configuration options. + */ +#define CILEN_VOID 2 +#define CILEN_COMPRESS 4 /* min length for compression protocol opt. */ +#define CILEN_VJ 6 /* length for RFC1332 Van-Jacobson opt. */ +#define CILEN_ADDR 6 /* new-style single address option */ +#define CILEN_ADDRS 10 /* old-style dual address option */ + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +/* + * Callbacks for fsm code. (CI = Configuration Information) + */ +static void ipcp_resetci (fsm *); /* Reset our CI */ +static int ipcp_cilen (fsm *); /* Return length of our CI */ +static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */ +static int ipcp_ackci (fsm *, u_char *, int); /* Peer ack'd our CI */ +static int ipcp_nakci (fsm *, u_char *, int); /* Peer nak'd our CI */ +static int ipcp_rejci (fsm *, u_char *, int); /* Peer rej'd our CI */ +static int ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */ +static void ipcp_up (fsm *); /* We're UP */ +static void ipcp_down (fsm *); /* We're DOWN */ +#if 0 +static void ipcp_script (fsm *, char *); /* Run an up/down script */ +#endif +static void ipcp_finished (fsm *); /* Don't need lower layer */ + +/* + * Protocol entry points from main code. + */ +static void ipcp_init (int); +static void ipcp_open (int); +static void ipcp_close (int, char *); +static void ipcp_lowerup (int); +static void ipcp_lowerdown (int); +static void ipcp_input (int, u_char *, int); +static void ipcp_protrej (int); + +static void ipcp_clear_addrs (int); + +#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ + (x) == CONFNAK ? "NAK" : "REJ") + + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +/* global vars */ +ipcp_options ipcp_wantoptions[NUM_PPP]; /* Options that we want to request */ +ipcp_options ipcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ +ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ +ipcp_options ipcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ + +fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */ + +struct protent ipcp_protent = { + PPP_IPCP, + ipcp_init, + ipcp_input, + ipcp_protrej, + ipcp_lowerup, + ipcp_lowerdown, + ipcp_open, + ipcp_close, +#if 0 + ipcp_printpkt, + NULL, +#endif + 1, + "IPCP", +#if 0 + ip_check_options, + NULL, + ip_active_pkt +#endif +}; + + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +/* local vars */ +static int cis_received[NUM_PPP]; /* # Conf-Reqs received */ +static int default_route_set[NUM_PPP]; /* Have set up a default route */ + +static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */ + ipcp_resetci, /* Reset our Configuration Information */ + ipcp_cilen, /* Length of our Configuration Information */ + ipcp_addci, /* Add our Configuration Information */ + ipcp_ackci, /* ACK our Configuration Information */ + ipcp_nakci, /* NAK our Configuration Information */ + ipcp_rejci, /* Reject our Configuration Information */ + ipcp_reqci, /* Request peer's Configuration Information */ + ipcp_up, /* Called when fsm reaches OPENED state */ + ipcp_down, /* Called when fsm leaves OPENED state */ + NULL, /* Called when we want the lower layer up */ + ipcp_finished, /* Called when we want the lower layer down */ + NULL, /* Called when Protocol-Reject received */ + NULL, /* Retransmission is necessary */ + NULL, /* Called to handle protocol-specific codes */ + "IPCP" /* String name of protocol */ +}; + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ + +/* + * Non-standard inet_ntoa left here for compat with original ppp + * sources. Assumes u32_t instead of struct in_addr. + */ + +char * _inet_ntoa(u32_t n) +{ + struct in_addr ia; + ia.s_addr = n; + return inet_ntoa(ia); +} + +#define inet_ntoa _inet_ntoa + +/* + * ipcp_init - Initialize IPCP. + */ +static void ipcp_init(int unit) +{ + fsm *f = &ipcp_fsm[unit]; + ipcp_options *wo = &ipcp_wantoptions[unit]; + ipcp_options *ao = &ipcp_allowoptions[unit]; + + f->unit = unit; + f->protocol = PPP_IPCP; + f->callbacks = &ipcp_callbacks; + fsm_init(&ipcp_fsm[unit]); + + memset(wo, 0, sizeof(*wo)); + memset(ao, 0, sizeof(*ao)); + + wo->neg_addr = 1; + wo->ouraddr = 0; +#if VJ_SUPPORT > 0 + wo->neg_vj = 1; +#else + wo->neg_vj = 0; +#endif + wo->vj_protocol = IPCP_VJ_COMP; + wo->maxslotindex = MAX_SLOTS - 1; + wo->cflag = 0; + + wo->default_route = 1; + + ao->neg_addr = 1; +#if VJ_SUPPORT > 0 + ao->neg_vj = 1; +#else + ao->neg_vj = 0; +#endif + ao->maxslotindex = MAX_SLOTS - 1; + ao->cflag = 1; + + ao->default_route = 1; +} + + +/* + * ipcp_open - IPCP is allowed to come up. + */ +static void ipcp_open(int unit) +{ + fsm_open(&ipcp_fsm[unit]); +} + + +/* + * ipcp_close - Take IPCP down. + */ +static void ipcp_close(int unit, char *reason) +{ + fsm_close(&ipcp_fsm[unit], reason); +} + + +/* + * ipcp_lowerup - The lower layer is up. + */ +static void ipcp_lowerup(int unit) +{ + fsm_lowerup(&ipcp_fsm[unit]); +} + + +/* + * ipcp_lowerdown - The lower layer is down. + */ +static void ipcp_lowerdown(int unit) +{ + fsm_lowerdown(&ipcp_fsm[unit]); +} + + +/* + * ipcp_input - Input IPCP packet. + */ +static void ipcp_input(int unit, u_char *p, int len) +{ + fsm_input(&ipcp_fsm[unit], p, len); +} + + +/* + * ipcp_protrej - A Protocol-Reject was received for IPCP. + * + * Pretend the lower layer went down, so we shut up. + */ +static void ipcp_protrej(int unit) +{ + fsm_lowerdown(&ipcp_fsm[unit]); +} + + +/* + * ipcp_resetci - Reset our CI. + */ +static void ipcp_resetci(fsm *f) +{ + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + + wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr; + if (wo->ouraddr == 0) + wo->accept_local = 1; + if (wo->hisaddr == 0) + wo->accept_remote = 1; + /* Request DNS addresses from the peer */ + wo->req_dns1 = ppp_settings.usepeerdns; + wo->req_dns2 = ppp_settings.usepeerdns; + ipcp_gotoptions[f->unit] = *wo; + cis_received[f->unit] = 0; +} + + +/* + * ipcp_cilen - Return length of our CI. + */ +static int ipcp_cilen(fsm *f) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + ipcp_options *ho = &ipcp_hisoptions[f->unit]; + +#define LENCIVJ(neg, old) (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0) +#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0) +#define LENCIDNS(neg) (neg ? (CILEN_ADDR) : 0) + + /* + * First see if we want to change our options to the old + * forms because we have received old forms from the peer. + */ + if (wo->neg_addr && !go->neg_addr && !go->old_addrs) { + /* use the old style of address negotiation */ + go->neg_addr = 1; + go->old_addrs = 1; + } + if (wo->neg_vj && !go->neg_vj && !go->old_vj) { + /* try an older style of VJ negotiation */ + if (cis_received[f->unit] == 0) { + /* keep trying the new style until we see some CI from the peer */ + go->neg_vj = 1; + } else { + /* use the old style only if the peer did */ + if (ho->neg_vj && ho->old_vj) { + go->neg_vj = 1; + go->old_vj = 1; + go->vj_protocol = ho->vj_protocol; + } + } + } + + return (LENCIADDR(go->neg_addr, go->old_addrs) + + LENCIVJ(go->neg_vj, go->old_vj) + + LENCIDNS(go->req_dns1) + + LENCIDNS(go->req_dns2)); +} + + +/* + * ipcp_addci - Add our desired CIs to a packet. + */ +static void ipcp_addci(fsm *f, u_char *ucp, int *lenp) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + int len = *lenp; + +#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \ + if (neg) { \ + int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ + if (len >= vjlen) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(vjlen, ucp); \ + PUTSHORT(val, ucp); \ + if (!old) { \ + PUTCHAR(maxslotindex, ucp); \ + PUTCHAR(cflag, ucp); \ + } \ + len -= vjlen; \ + } else \ + neg = 0; \ + } + +#define ADDCIADDR(opt, neg, old, val1, val2) \ + if (neg) { \ + int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ + if (len >= addrlen) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(addrlen, ucp); \ + l = ntohl(val1); \ + PUTLONG(l, ucp); \ + if (old) { \ + l = ntohl(val2); \ + PUTLONG(l, ucp); \ + } \ + len -= addrlen; \ + } else \ + neg = 0; \ + } + +#define ADDCIDNS(opt, neg, addr) \ + if (neg) { \ + if (len >= CILEN_ADDR) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_ADDR, ucp); \ + l = ntohl(addr); \ + PUTLONG(l, ucp); \ + len -= CILEN_ADDR; \ + } else \ + neg = 0; \ + } + + ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, + go->old_addrs, go->ouraddr, go->hisaddr); + + ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); + + ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); + + ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); + + *lenp -= len; +} + + +/* + * ipcp_ackci - Ack our CIs. + * + * Returns: + * 0 - Ack was bad. + * 1 - Ack was good. + */ +static int ipcp_ackci(fsm *f, u_char *p, int len) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + u_short cilen, citype, cishort; + u32_t cilong; + u_char cimaxslotindex, cicflag; + + /* + * CIs must be in exactly the same order that we sent... + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ + +#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \ + if (neg) { \ + int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ + if ((len -= vjlen) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != vjlen || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + if (!old) { \ + GETCHAR(cimaxslotindex, p); \ + if (cimaxslotindex != maxslotindex) \ + goto bad; \ + GETCHAR(cicflag, p); \ + if (cicflag != cflag) \ + goto bad; \ + } \ + } + +#define ACKCIADDR(opt, neg, old, val1, val2) \ + if (neg) { \ + int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ + u32_t l; \ + if ((len -= addrlen) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != addrlen || \ + citype != opt) \ + goto bad; \ + GETLONG(l, p); \ + cilong = htonl(l); \ + if (val1 != cilong) \ + goto bad; \ + if (old) { \ + GETLONG(l, p); \ + cilong = htonl(l); \ + if (val2 != cilong) \ + goto bad; \ + } \ + } + +#define ACKCIDNS(opt, neg, addr) \ + if (neg) { \ + u32_t l; \ + if ((len -= CILEN_ADDR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_ADDR || \ + citype != opt) \ + goto bad; \ + GETLONG(l, p); \ + cilong = htonl(l); \ + if (addr != cilong) \ + goto bad; \ + } + + ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, + go->old_addrs, go->ouraddr, go->hisaddr); + + ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); + + ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); + + ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + return (1); + +bad: + IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n")); + return (0); +} + +/* + * ipcp_nakci - Peer has sent a NAK for some of our CIs. + * This should not modify any state if the Nak is bad + * or if IPCP is in the OPENED state. + * + * Returns: + * 0 - Nak was bad. + * 1 - Nak was good. + */ +static int ipcp_nakci(fsm *f, u_char *p, int len) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + u_char cimaxslotindex, cicflag; + u_char citype, cilen, *next; + u_short cishort; + u32_t ciaddr1, ciaddr2, l, cidnsaddr; + ipcp_options no; /* options we've seen Naks for */ + ipcp_options try; /* options to request next time */ + + BZERO(&no, sizeof(no)); + try = *go; + + /* + * Any Nak'd CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define NAKCIADDR(opt, neg, old, code) \ + if (go->neg && \ + len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \ + p[1] == cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + ciaddr1 = htonl(l); \ + if (old) { \ + GETLONG(l, p); \ + ciaddr2 = htonl(l); \ + no.old_addrs = 1; \ + } else \ + ciaddr2 = 0; \ + no.neg = 1; \ + code \ + } + +#define NAKCIVJ(opt, neg, code) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + no.neg = 1; \ + code \ + } + +#define NAKCIDNS(opt, neg, code) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_ADDR) && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cidnsaddr = htonl(l); \ + no.neg = 1; \ + code \ + } + + /* + * Accept the peer's idea of {our,his} address, if different + * from our idea, only if the accept_{local,remote} flag is set. + */ + NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs, + if (go->accept_local && ciaddr1) { /* Do we know our address? */ + try.ouraddr = ciaddr1; + IPCPDEBUG((LOG_INFO, "local IP address %s\n", + inet_ntoa(ciaddr1))); + } + if (go->accept_remote && ciaddr2) { /* Does he know his? */ + try.hisaddr = ciaddr2; + IPCPDEBUG((LOG_INFO, "remote IP address %s\n", + inet_ntoa(ciaddr2))); + } + ); + + /* + * Accept the peer's value of maxslotindex provided that it + * is less than what we asked for. Turn off slot-ID compression + * if the peer wants. Send old-style compress-type option if + * the peer wants. + */ + NAKCIVJ(CI_COMPRESSTYPE, neg_vj, + if (cilen == CILEN_VJ) { + GETCHAR(cimaxslotindex, p); + GETCHAR(cicflag, p); + if (cishort == IPCP_VJ_COMP) { + try.old_vj = 0; + if (cimaxslotindex < go->maxslotindex) + try.maxslotindex = cimaxslotindex; + if (!cicflag) + try.cflag = 0; + } else { + try.neg_vj = 0; + } + } else { + if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) { + try.old_vj = 1; + try.vj_protocol = cishort; + } else { + try.neg_vj = 0; + } + } + ); + + NAKCIDNS(CI_MS_DNS1, req_dns1, + try.dnsaddr[0] = cidnsaddr; + IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr))); + ); + + NAKCIDNS(CI_MS_DNS2, req_dns2, + try.dnsaddr[1] = cidnsaddr; + IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr))); + ); + + /* + * There may be remaining CIs, if the peer is requesting negotiation + * on an option that we didn't include in our request packet. + * If they want to negotiate about IP addresses, we comply. + * If they want us to ask for compression, we refuse. + */ + while (len > CILEN_VOID) { + GETCHAR(citype, p); + GETCHAR(cilen, p); + if( (len -= cilen) < 0 ) + goto bad; + next = p + cilen - 2; + + switch (citype) { + case CI_COMPRESSTYPE: + if (go->neg_vj || no.neg_vj || + (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) + goto bad; + no.neg_vj = 1; + break; + case CI_ADDRS: + if ((go->neg_addr && go->old_addrs) || no.old_addrs + || cilen != CILEN_ADDRS) + goto bad; + try.neg_addr = 1; + try.old_addrs = 1; + GETLONG(l, p); + ciaddr1 = htonl(l); + if (ciaddr1 && go->accept_local) + try.ouraddr = ciaddr1; + GETLONG(l, p); + ciaddr2 = htonl(l); + if (ciaddr2 && go->accept_remote) + try.hisaddr = ciaddr2; + no.old_addrs = 1; + break; + case CI_ADDR: + if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) + goto bad; + try.old_addrs = 0; + GETLONG(l, p); + ciaddr1 = htonl(l); + if (ciaddr1 && go->accept_local) + try.ouraddr = ciaddr1; + if (try.ouraddr != 0) + try.neg_addr = 1; + no.neg_addr = 1; + break; + } + p = next; + } + + /* If there is still anything left, this packet is bad. */ + if (len != 0) + goto bad; + + /* + * OK, the Nak is good. Now we can update state. + */ + if (f->state != OPENED) + *go = try; + + return 1; + +bad: + IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n")); + return 0; +} + + +/* + * ipcp_rejci - Reject some of our CIs. + */ +static int ipcp_rejci(fsm *f, u_char *p, int len) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + u_char cimaxslotindex, ciflag, cilen; + u_short cishort; + u32_t cilong; + ipcp_options try; /* options to request next time */ + + try = *go; + /* + * Any Rejected CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define REJCIADDR(opt, neg, old, val1, val2) \ + if (go->neg && \ + len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \ + p[1] == cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = htonl(l); \ + /* Check rejected value. */ \ + if (cilong != val1) \ + goto bad; \ + if (old) { \ + GETLONG(l, p); \ + cilong = htonl(l); \ + /* Check rejected value. */ \ + if (cilong != val2) \ + goto bad; \ + } \ + try.neg = 0; \ + } + +#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \ + if (go->neg && \ + p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \ + len >= p[1] && \ + p[0] == opt) { \ + len -= p[1]; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + /* Check rejected value. */ \ + if (cishort != val) \ + goto bad; \ + if (!old) { \ + GETCHAR(cimaxslotindex, p); \ + if (cimaxslotindex != maxslot) \ + goto bad; \ + GETCHAR(ciflag, p); \ + if (ciflag != cflag) \ + goto bad; \ + } \ + try.neg = 0; \ + } + +#define REJCIDNS(opt, neg, dnsaddr) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_ADDR) && \ + len >= cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = htonl(l); \ + /* Check rejected value. */ \ + if (cilong != dnsaddr) \ + goto bad; \ + try.neg = 0; \ + } + + REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, + go->old_addrs, go->ouraddr, go->hisaddr); + + REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); + + REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]); + + REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + /* + * Now we can update state. + */ + if (f->state != OPENED) + *go = try; + return 1; + +bad: + IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n")); + return 0; +} + + +/* + * ipcp_reqci - Check the peer's requested CIs and send appropriate response. + * + * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified + * appropriately. If reject_if_disagree is non-zero, doesn't return + * CONFNAK; returns CONFREJ if it can't return CONFACK. + */ +static int ipcp_reqci( + fsm *f, + u_char *inp, /* Requested CIs */ + int *len, /* Length of requested CIs */ + int reject_if_disagree +) +{ + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + ipcp_options *ho = &ipcp_hisoptions[f->unit]; + ipcp_options *ao = &ipcp_allowoptions[f->unit]; +#ifdef OLD_CI_ADDRS + ipcp_options *go = &ipcp_gotoptions[f->unit]; +#endif + u_char *cip, *next; /* Pointer to current and next CIs */ + u_short cilen, citype; /* Parsed len, type */ + u_short cishort; /* Parsed short value */ + u32_t tl, ciaddr1; /* Parsed address values */ +#ifdef OLD_CI_ADDRS + u32_t ciaddr2; /* Parsed address values */ +#endif + int rc = CONFACK; /* Final packet return code */ + int orc; /* Individual option return code */ + u_char *p; /* Pointer to next char to parse */ + u_char *ucp = inp; /* Pointer to current output char */ + int l = *len; /* Length left */ + u_char maxslotindex, cflag; + int d; + + cis_received[f->unit] = 1; + + /* + * Reset all his options. + */ + BZERO(ho, sizeof(*ho)); + + /* + * Process all his options. + */ + next = inp; + while (l) { + orc = CONFACK; /* Assume success */ + cip = p = next; /* Remember begining of CI */ + if (l < 2 || /* Not enough data for CI header or */ + p[1] < 2 || /* CI length too small or */ + p[1] > l) { /* CI length too big? */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n")); + orc = CONFREJ; /* Reject bad CI */ + cilen = l; /* Reject till end of packet */ + l = 0; /* Don't loop again */ + goto endswitch; + } + GETCHAR(citype, p); /* Parse CI type */ + GETCHAR(cilen, p); /* Parse CI length */ + l -= cilen; /* Adjust remaining length */ + next += cilen; /* Step to next CI */ + + switch (citype) { /* Check CI type */ +#ifdef OLD_CI_ADDRS /* Need to save space... */ + case CI_ADDRS: + IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n")); + if (!ao->neg_addr || + cilen != CILEN_ADDRS) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + + /* + * If he has no address, or if we both have his address but + * disagree about it, then NAK it with our idea. + * In particular, if we don't know his address, but he does, + * then accept it. + */ + GETLONG(tl, p); /* Parse source address (his) */ + ciaddr1 = htonl(tl); + IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1))); + if (ciaddr1 != wo->hisaddr + && (ciaddr1 == 0 || !wo->accept_remote)) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(wo->hisaddr); + PUTLONG(tl, p); + } + } else if (ciaddr1 == 0 && wo->hisaddr == 0) { + /* + * If neither we nor he knows his address, reject the option. + */ + orc = CONFREJ; + wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ + break; + } + + /* + * If he doesn't know our address, or if we both have our address + * but disagree about it, then NAK it with our idea. + */ + GETLONG(tl, p); /* Parse desination address (ours) */ + ciaddr2 = htonl(tl); + IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2))); + if (ciaddr2 != wo->ouraddr) { + if (ciaddr2 == 0 || !wo->accept_local) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(wo->ouraddr); + PUTLONG(tl, p); + } + } else { + go->ouraddr = ciaddr2; /* accept peer's idea */ + } + } + + ho->neg_addr = 1; + ho->old_addrs = 1; + ho->hisaddr = ciaddr1; + ho->ouraddr = ciaddr2; + break; +#endif + + case CI_ADDR: + if (!ao->neg_addr) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n")); + orc = CONFREJ; /* Reject CI */ + break; + } else if (cilen != CILEN_ADDR) { /* Check CI length */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n")); + orc = CONFREJ; /* Reject CI */ + break; + } + + /* + * If he has no address, or if we both have his address but + * disagree about it, then NAK it with our idea. + * In particular, if we don't know his address, but he does, + * then accept it. + */ + GETLONG(tl, p); /* Parse source address (his) */ + ciaddr1 = htonl(tl); + if (ciaddr1 != wo->hisaddr + && (ciaddr1 == 0 || !wo->accept_remote)) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(wo->hisaddr); + PUTLONG(tl, p); + } + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1))); + } else if (ciaddr1 == 0 && wo->hisaddr == 0) { + /* + * Don't ACK an address of 0.0.0.0 - reject it instead. + */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1))); + orc = CONFREJ; + wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ + break; + } + + ho->neg_addr = 1; + ho->hisaddr = ciaddr1; + IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1))); + break; + + case CI_MS_DNS1: + case CI_MS_DNS2: + /* Microsoft primary or secondary DNS request */ + d = citype == CI_MS_DNS2; + + /* If we do not have a DNS address then we cannot send it */ + if (ao->dnsaddr[d] == 0 || + cilen != CILEN_ADDR) { /* Check CI length */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1)); + orc = CONFREJ; /* Reject CI */ + break; + } + GETLONG(tl, p); + if (htonl(tl) != ao->dnsaddr[d]) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n", + d+1, inet_ntoa(tl))); + DECPTR(sizeof(u32_t), p); + tl = ntohl(ao->dnsaddr[d]); + PUTLONG(tl, p); + orc = CONFNAK; + } + IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1)); + break; + + case CI_MS_WINS1: + case CI_MS_WINS2: + /* Microsoft primary or secondary WINS request */ + d = citype == CI_MS_WINS2; + IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1)); + + /* If we do not have a DNS address then we cannot send it */ + if (ao->winsaddr[d] == 0 || + cilen != CILEN_ADDR) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + GETLONG(tl, p); + if (htonl(tl) != ao->winsaddr[d]) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(ao->winsaddr[d]); + PUTLONG(tl, p); + orc = CONFNAK; + } + break; + + case CI_COMPRESSTYPE: + if (!ao->neg_vj) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen)); + orc = CONFREJ; + break; + } + GETSHORT(cishort, p); + + if (!(cishort == IPCP_VJ_COMP || + (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort)); + orc = CONFREJ; + break; + } + + ho->neg_vj = 1; + ho->vj_protocol = cishort; + if (cilen == CILEN_VJ) { + GETCHAR(maxslotindex, p); + if (maxslotindex > ao->maxslotindex) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex)); + orc = CONFNAK; + if (!reject_if_disagree){ + DECPTR(1, p); + PUTCHAR(ao->maxslotindex, p); + } + } + GETCHAR(cflag, p); + if (cflag && !ao->cflag) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag)); + orc = CONFNAK; + if (!reject_if_disagree){ + DECPTR(1, p); + PUTCHAR(wo->cflag, p); + } + } + ho->maxslotindex = maxslotindex; + ho->cflag = cflag; + } else { + ho->old_vj = 1; + ho->maxslotindex = MAX_SLOTS - 1; + ho->cflag = 1; + } + IPCPDEBUG((LOG_INFO, + "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n", + ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag)); + break; + + default: + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype)); + orc = CONFREJ; + break; + } + +endswitch: + if (orc == CONFACK && /* Good CI */ + rc != CONFACK) /* but prior CI wasnt? */ + continue; /* Don't send this one */ + + if (orc == CONFNAK) { /* Nak this CI? */ + if (reject_if_disagree) { /* Getting fed up with sending NAKs? */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n")); + orc = CONFREJ; /* Get tough if so */ + } else { + if (rc == CONFREJ) /* Rejecting prior CI? */ + continue; /* Don't send this one */ + if (rc == CONFACK) { /* Ack'd all prior CIs? */ + rc = CONFNAK; /* Not anymore... */ + ucp = inp; /* Backup */ + } + } + } + + if (orc == CONFREJ && /* Reject this CI */ + rc != CONFREJ) { /* but no prior ones? */ + rc = CONFREJ; + ucp = inp; /* Backup */ + } + + /* Need to move CI? */ + if (ucp != cip) + BCOPY(cip, ucp, cilen); /* Move it */ + + /* Update output pointer */ + INCPTR(cilen, ucp); + } + + /* + * If we aren't rejecting this packet, and we want to negotiate + * their address, and they didn't send their address, then we + * send a NAK with a CI_ADDR option appended. We assume the + * input buffer is long enough that we can append the extra + * option safely. + */ + if (rc != CONFREJ && !ho->neg_addr && + wo->req_addr && !reject_if_disagree) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n")); + if (rc == CONFACK) { + rc = CONFNAK; + ucp = inp; /* reset pointer */ + wo->req_addr = 0; /* don't ask again */ + } + PUTCHAR(CI_ADDR, ucp); + PUTCHAR(CILEN_ADDR, ucp); + tl = ntohl(wo->hisaddr); + PUTLONG(tl, ucp); + } + + *len = (int)(ucp - inp); /* Compute output length */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc))); + return (rc); /* Return final code */ +} + + +#if 0 +/* + * ip_check_options - check that any IP-related options are OK, + * and assign appropriate defaults. + */ +static void ip_check_options(u_long localAddr) +{ + ipcp_options *wo = &ipcp_wantoptions[0]; + + /* + * Load our default IP address but allow the remote host to give us + * a new address. + */ + if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) { + wo->accept_local = 1; /* don't insist on this default value */ + wo->ouraddr = htonl(localAddr); + } +} +#endif + + +/* + * ipcp_up - IPCP has come UP. + * + * Configure the IP network interface appropriately and bring it up. + */ +static void ipcp_up(fsm *f) +{ + u32_t mask; + ipcp_options *ho = &ipcp_hisoptions[f->unit]; + ipcp_options *go = &ipcp_gotoptions[f->unit]; + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + + np_up(f->unit, PPP_IP); + IPCPDEBUG((LOG_INFO, "ipcp: up\n")); + + /* + * We must have a non-zero IP address for both ends of the link. + */ + if (!ho->neg_addr) + ho->hisaddr = wo->hisaddr; + + if (ho->hisaddr == 0) { + IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n")); + ipcp_close(f->unit, "Could not determine remote IP address"); + return; + } + if (go->ouraddr == 0) { + IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n")); + ipcp_close(f->unit, "Could not determine local IP address"); + return; + } + + if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) { + /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/ + } + + /* + * Check that the peer is allowed to use the IP address it wants. + */ + if (!auth_ip_addr(f->unit, ho->hisaddr)) { + IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n", + inet_ntoa(ho->hisaddr))); + ipcp_close(f->unit, "Unauthorized remote IP address"); + return; + } + + /* set tcp compression */ + sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex); + + /* + * Set IP addresses and (if specified) netmask. + */ + mask = GetMask(go->ouraddr); + + if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) { + IPCPDEBUG((LOG_WARNING, "sifaddr failed\n")); + ipcp_close(f->unit, "Interface configuration failed"); + return; + } + + /* bring the interface up for IP */ + if (!sifup(f->unit)) { + IPCPDEBUG((LOG_WARNING, "sifup failed\n")); + ipcp_close(f->unit, "Interface configuration failed"); + return; + } + + sifnpmode(f->unit, PPP_IP, NPMODE_PASS); + + /* assign a default route through the interface if required */ + if (ipcp_wantoptions[f->unit].default_route) + if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) + default_route_set[f->unit] = 1; + + IPCPDEBUG((LOG_NOTICE, "local IP address %s\n", inet_ntoa(go->ouraddr))); + IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr))); + if (go->dnsaddr[0]) { + IPCPDEBUG((LOG_NOTICE, "primary DNS address %s\n", inet_ntoa(go->dnsaddr[0]))); + } + if (go->dnsaddr[1]) { + IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1]))); + } +} + + +/* + * ipcp_down - IPCP has gone DOWN. + * + * Take the IP network interface down, clear its addresses + * and delete routes through it. + */ +static void ipcp_down(fsm *f) +{ + IPCPDEBUG((LOG_INFO, "ipcp: down\n")); + np_down(f->unit, PPP_IP); + sifvjcomp(f->unit, 0, 0, 0); + + sifdown(f->unit); + ipcp_clear_addrs(f->unit); +} + + +/* + * ipcp_clear_addrs() - clear the interface addresses, routes, etc. + */ +static void ipcp_clear_addrs(int unit) +{ + u32_t ouraddr, hisaddr; + + ouraddr = ipcp_gotoptions[unit].ouraddr; + hisaddr = ipcp_hisoptions[unit].hisaddr; + if (default_route_set[unit]) { + cifdefaultroute(unit, ouraddr, hisaddr); + default_route_set[unit] = 0; + } + cifaddr(unit, ouraddr, hisaddr); +} + + +/* + * ipcp_finished - possibly shut down the lower layers. + */ +static void ipcp_finished(fsm *f) +{ + np_finished(f->unit, PPP_IP); +} + +#if 0 +static int ipcp_printpkt( + u_char *p, + int plen, + void (*printer) (void *, char *, ...), + void *arg +) +{ + (void)p; + (void)plen; + (void)printer; + (void)arg; + return 0; +} + +/* + * ip_active_pkt - see if this IP packet is worth bringing the link up for. + * We don't bring the link up for IP fragments or for TCP FIN packets + * with no data. + */ +#define IP_HDRLEN 20 /* bytes */ +#define IP_OFFMASK 0x1fff +#define IPPROTO_TCP 6 +#define TCP_HDRLEN 20 +#define TH_FIN 0x01 + +/* + * We use these macros because the IP header may be at an odd address, + * and some compilers might use word loads to get th_off or ip_hl. + */ + +#define net_short(x) (((x)[0] << 8) + (x)[1]) +#define get_iphl(x) (((unsigned char *)(x))[0] & 0xF) +#define get_ipoff(x) net_short((unsigned char *)(x) + 6) +#define get_ipproto(x) (((unsigned char *)(x))[9]) +#define get_tcpoff(x) (((unsigned char *)(x))[12] >> 4) +#define get_tcpflags(x) (((unsigned char *)(x))[13]) + +static int ip_active_pkt(u_char *pkt, int len) +{ + u_char *tcp; + int hlen; + + len -= PPP_HDRLEN; + pkt += PPP_HDRLEN; + if (len < IP_HDRLEN) + return 0; + if ((get_ipoff(pkt) & IP_OFFMASK) != 0) + return 0; + if (get_ipproto(pkt) != IPPROTO_TCP) + return 1; + hlen = get_iphl(pkt) * 4; + if (len < hlen + TCP_HDRLEN) + return 0; + tcp = pkt + hlen; + if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) + return 0; + return 1; +} +#endif + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ipcp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ipcp.h new file mode 100644 index 0000000..28fc36e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ipcp.h @@ -0,0 +1,126 @@ +/***************************************************************************** +* ipcp.h - PPP IP NCP: Internet Protocol Network Control Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * ipcp.h - IP Control Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: ipcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef IPCP_H +#define IPCP_H + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ +/* + * Options. + */ +#define CI_ADDRS 1 /* IP Addresses */ +#define CI_COMPRESSTYPE 2 /* Compression Type */ +#define CI_ADDR 3 + +#define CI_MS_WINS1 128 /* Primary WINS value */ +#define CI_MS_DNS1 129 /* Primary DNS value */ +#define CI_MS_WINS2 130 /* Secondary WINS value */ +#define CI_MS_DNS2 131 /* Secondary DNS value */ + +#define IPCP_VJMODE_OLD 1 /* "old" mode (option # = 0x0037) */ +#define IPCP_VJMODE_RFC1172 2 /* "old-rfc"mode (option # = 0x002d) */ +#define IPCP_VJMODE_RFC1332 3 /* "new-rfc"mode (option # = 0x002d, */ + /* maxslot and slot number compression) */ + +#define IPCP_VJ_COMP 0x002d /* current value for VJ compression option*/ +#define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */ + /* compression option*/ + + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +typedef struct ipcp_options { + u_int neg_addr : 1; /* Negotiate IP Address? */ + u_int old_addrs : 1; /* Use old (IP-Addresses) option? */ + u_int req_addr : 1; /* Ask peer to send IP address? */ + u_int default_route : 1; /* Assign default route through interface? */ + u_int proxy_arp : 1; /* Make proxy ARP entry for peer? */ + u_int neg_vj : 1; /* Van Jacobson Compression? */ + u_int old_vj : 1; /* use old (short) form of VJ option? */ + u_int accept_local : 1; /* accept peer's value for ouraddr */ + u_int accept_remote : 1; /* accept peer's value for hisaddr */ + u_int req_dns1 : 1; /* Ask peer to send primary DNS address? */ + u_int req_dns2 : 1; /* Ask peer to send secondary DNS address? */ + u_short vj_protocol; /* protocol value to use in VJ option */ + u_char maxslotindex; /* VJ slots - 1. */ + u_char cflag; /* VJ slot compression flag. */ + u32_t ouraddr, hisaddr; /* Addresses in NETWORK BYTE ORDER */ + u32_t dnsaddr[2]; /* Primary and secondary MS DNS entries */ + u32_t winsaddr[2]; /* Primary and secondary MS WINS entries */ +} ipcp_options; + + +/***************************** +*** PUBLIC DATA STRUCTURES *** +*****************************/ + +extern fsm ipcp_fsm[]; +extern ipcp_options ipcp_wantoptions[]; +extern ipcp_options ipcp_gotoptions[]; +extern ipcp_options ipcp_allowoptions[]; +extern ipcp_options ipcp_hisoptions[]; + +extern struct protent ipcp_protent; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + + +#endif /* IPCP_H */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/lcp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/lcp.c new file mode 100644 index 0000000..41dbc5d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/lcp.c @@ -0,0 +1,1991 @@ +/***************************************************************************** +* lcp.c - Network Link Control Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-01 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ + +/* + * lcp.c - PPP Link Control Protocol. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "fsm.h" +#include "chap.h" +#include "magic.h" +#include "auth.h" +#include "lcp.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ +/* + * Length of each type of configuration option (in octets) + */ +#define CILEN_VOID 2 +#define CILEN_CHAR 3 +#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */ +#define CILEN_CHAP 5 /* CILEN_VOID + sizeof(short) + 1 */ +#define CILEN_LONG 6 /* CILEN_VOID + sizeof(long) */ +#define CILEN_LQR 8 /* CILEN_VOID + sizeof(short) + sizeof(long) */ +#define CILEN_CBCP 3 + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +/* + * Callbacks for fsm code. (CI = Configuration Information) + */ +static void lcp_resetci (fsm*); /* Reset our CI */ +static int lcp_cilen (fsm*); /* Return length of our CI */ +static void lcp_addci (fsm*, u_char*, int*); /* Add our CI to pkt */ +static int lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */ +static int lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */ +static int lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */ +static int lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */ +static void lcp_up (fsm*); /* We're UP */ +static void lcp_down (fsm*); /* We're DOWN */ +static void lcp_starting (fsm*); /* We need lower layer up */ +static void lcp_finished (fsm*); /* We need lower layer down */ +static int lcp_extcode (fsm*, int, u_char, u_char*, int); + +static void lcp_rprotrej (fsm*, u_char*, int); + +/* + * routines to send LCP echos to peer + */ +static void lcp_echo_lowerup (int); +static void lcp_echo_lowerdown (int); +static void LcpEchoTimeout (void*); +static void lcp_received_echo_reply (fsm*, int, u_char*, int); +static void LcpSendEchoRequest (fsm*); +static void LcpLinkFailure (fsm*); +static void LcpEchoCheck (fsm*); + +/* + * Protocol entry points. + * Some of these are called directly. + */ +static void lcp_input (int, u_char *, int); +static void lcp_protrej (int); + +#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ + (x) == CONFNAK ? "NAK" : "REJ") + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +/* global vars */ +LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ +lcp_options lcp_wantoptions[NUM_PPP]; /* Options that we want to request */ +lcp_options lcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ +lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ +lcp_options lcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ +ext_accm xmit_accm[NUM_PPP]; /* extended transmit ACCM */ + + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static fsm lcp_fsm[NUM_PPP]; /* LCP fsm structure (global)*/ +static u_int lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */ +static u_int lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */ +static u32_t lcp_echos_pending = 0; /* Number of outstanding echo msgs */ +static u32_t lcp_echo_number = 0; /* ID number of next echo frame */ +static u32_t lcp_echo_timer_running = 0; /* TRUE if a timer is running */ + +static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */ + +static fsm_callbacks lcp_callbacks = { /* LCP callback routines */ + lcp_resetci, /* Reset our Configuration Information */ + lcp_cilen, /* Length of our Configuration Information */ + lcp_addci, /* Add our Configuration Information */ + lcp_ackci, /* ACK our Configuration Information */ + lcp_nakci, /* NAK our Configuration Information */ + lcp_rejci, /* Reject our Configuration Information */ + lcp_reqci, /* Request peer's Configuration Information */ + lcp_up, /* Called when fsm reaches OPENED state */ + lcp_down, /* Called when fsm leaves OPENED state */ + lcp_starting, /* Called when we want the lower layer up */ + lcp_finished, /* Called when we want the lower layer down */ + NULL, /* Called when Protocol-Reject received */ + NULL, /* Retransmission is necessary */ + lcp_extcode, /* Called to handle LCP-specific codes */ + "LCP" /* String name of protocol */ +}; + +struct protent lcp_protent = { + PPP_LCP, + lcp_init, + lcp_input, + lcp_protrej, + lcp_lowerup, + lcp_lowerdown, + lcp_open, + lcp_close, +#if 0 + lcp_printpkt, + NULL, +#endif + 1, + "LCP", +#if 0 + NULL, + NULL, + NULL +#endif +}; + +int lcp_loopbackfail = DEFLOOPBACKFAIL; + + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * lcp_init - Initialize LCP. + */ +void lcp_init(int unit) +{ + fsm *f = &lcp_fsm[unit]; + lcp_options *wo = &lcp_wantoptions[unit]; + lcp_options *ao = &lcp_allowoptions[unit]; + + f->unit = unit; + f->protocol = PPP_LCP; + f->callbacks = &lcp_callbacks; + + fsm_init(f); + + wo->passive = 0; + wo->silent = 0; + wo->restart = 0; /* Set to 1 in kernels or multi-line + * implementations */ + wo->neg_mru = 1; + wo->mru = PPP_DEFMRU; + wo->neg_asyncmap = 1; + wo->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ + wo->neg_chap = 0; /* Set to 1 on server */ + wo->neg_upap = 0; /* Set to 1 on server */ + wo->chap_mdtype = CHAP_DIGEST_MD5; + wo->neg_magicnumber = 1; + wo->neg_pcompression = 1; + wo->neg_accompression = 1; + wo->neg_lqr = 0; /* no LQR implementation yet */ + wo->neg_cbcp = 0; + + ao->neg_mru = 1; + ao->mru = PPP_MAXMRU; + ao->neg_asyncmap = 1; + ao->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ + ao->neg_chap = (CHAP_SUPPORT != 0); + ao->chap_mdtype = CHAP_DIGEST_MD5; + ao->neg_upap = (PAP_SUPPORT != 0); + ao->neg_magicnumber = 1; + ao->neg_pcompression = 1; + ao->neg_accompression = 1; + ao->neg_lqr = 0; /* no LQR implementation yet */ + ao->neg_cbcp = (CBCP_SUPPORT != 0); + + /* + * Set transmit escape for the flag and escape characters plus anything + * set for the allowable options. + */ + memset(xmit_accm[unit], 0, sizeof(xmit_accm[0])); + xmit_accm[unit][15] = 0x60; + xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF); + xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF); + xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF); + xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF); + LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n", + xmit_accm[unit][0], + xmit_accm[unit][1], + xmit_accm[unit][2], + xmit_accm[unit][3])); + + lcp_phase[unit] = PHASE_INITIALIZE; +} + + +/* + * lcp_open - LCP is allowed to come up. + */ +void lcp_open(int unit) +{ + fsm *f = &lcp_fsm[unit]; + lcp_options *wo = &lcp_wantoptions[unit]; + + f->flags = 0; + if (wo->passive) + f->flags |= OPT_PASSIVE; + if (wo->silent) + f->flags |= OPT_SILENT; + fsm_open(f); + + lcp_phase[unit] = PHASE_ESTABLISH; +} + + +/* + * lcp_close - Take LCP down. + */ +void lcp_close(int unit, char *reason) +{ + fsm *f = &lcp_fsm[unit]; + + if (lcp_phase[unit] != PHASE_DEAD) + lcp_phase[unit] = PHASE_TERMINATE; + if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) { + /* + * This action is not strictly according to the FSM in RFC1548, + * but it does mean that the program terminates if you do an + * lcp_close() in passive/silent mode when a connection hasn't + * been established. + */ + f->state = CLOSED; + lcp_finished(f); + } + else + fsm_close(&lcp_fsm[unit], reason); +} + + +/* + * lcp_lowerup - The lower layer is up. + */ +void lcp_lowerup(int unit) +{ + lcp_options *wo = &lcp_wantoptions[unit]; + + /* + * Don't use A/C or protocol compression on transmission, + * but accept A/C and protocol compressed packets + * if we are going to ask for A/C and protocol compression. + */ + ppp_set_xaccm(unit, &xmit_accm[unit]); + ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0); + ppp_recv_config(unit, PPP_MRU, 0x00000000l, + wo->neg_pcompression, wo->neg_accompression); + peer_mru[unit] = PPP_MRU; + lcp_allowoptions[unit].asyncmap + = (u_long)xmit_accm[unit][0] + | ((u_long)xmit_accm[unit][1] << 8) + | ((u_long)xmit_accm[unit][2] << 16) + | ((u_long)xmit_accm[unit][3] << 24); + LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n", + xmit_accm[unit][3], + xmit_accm[unit][2], + xmit_accm[unit][1], + xmit_accm[unit][0])); + + fsm_lowerup(&lcp_fsm[unit]); +} + + +/* + * lcp_lowerdown - The lower layer is down. + */ +void lcp_lowerdown(int unit) +{ + fsm_lowerdown(&lcp_fsm[unit]); +} + +/* + * lcp_sprotrej - Send a Protocol-Reject for some protocol. + */ +void lcp_sprotrej(int unit, u_char *p, int len) +{ + /* + * Send back the protocol and the information field of the + * rejected packet. We only get here if LCP is in the OPENED state. + */ + + fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id, + p, len); +} + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* + * lcp_input - Input LCP packet. + */ +static void lcp_input(int unit, u_char *p, int len) +{ + fsm *f = &lcp_fsm[unit]; + + fsm_input(f, p, len); +} + + +/* + * lcp_extcode - Handle a LCP-specific code. + */ +static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len) +{ + u_char *magp; + + switch( code ){ + case PROTREJ: + lcp_rprotrej(f, inp, len); + break; + + case ECHOREQ: + if (f->state != OPENED) + break; + LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id)); + magp = inp; + PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp); + fsm_sdata(f, ECHOREP, id, inp, len); + break; + + case ECHOREP: + lcp_received_echo_reply(f, id, inp, len); + break; + + case DISCREQ: + break; + + default: + return 0; + } + return 1; +} + + +/* + * lcp_rprotrej - Receive an Protocol-Reject. + * + * Figure out which protocol is rejected and inform it. + */ +static void lcp_rprotrej(fsm *f, u_char *inp, int len) +{ + int i; + struct protent *protp; + u_short prot; + + if (len < sizeof (u_short)) { + LCPDEBUG((LOG_INFO, + "lcp_rprotrej: Rcvd short Protocol-Reject packet!\n")); + return; + } + + GETSHORT(prot, inp); + + LCPDEBUG((LOG_INFO, + "lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n", + prot)); + + /* + * Protocol-Reject packets received in any state other than the LCP + * OPENED state SHOULD be silently discarded. + */ + if( f->state != OPENED ){ + LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n", + f->state)); + return; + } + + /* + * Upcall the proper Protocol-Reject routine. + */ + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) + if (protp->protocol == prot && protp->enabled_flag) { + (*protp->protrej)(f->unit); + return; + } + + LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n", + prot)); +} + + +/* + * lcp_protrej - A Protocol-Reject was received. + */ +static void lcp_protrej(int unit) +{ + (void)unit; + /* + * Can't reject LCP! + */ + LCPDEBUG((LOG_WARNING, + "lcp_protrej: Received Protocol-Reject for LCP!\n")); + fsm_protreject(&lcp_fsm[unit]); +} + + +/* + * lcp_resetci - Reset our CI. + */ +static void lcp_resetci(fsm *f) +{ + lcp_wantoptions[f->unit].magicnumber = magic(); + lcp_wantoptions[f->unit].numloops = 0; + lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit]; + peer_mru[f->unit] = PPP_MRU; + auth_reset(f->unit); +} + + +/* + * lcp_cilen - Return length of our CI. + */ +static int lcp_cilen(fsm *f) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + +#define LENCIVOID(neg) ((neg) ? CILEN_VOID : 0) +#define LENCICHAP(neg) ((neg) ? CILEN_CHAP : 0) +#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0) +#define LENCILONG(neg) ((neg) ? CILEN_LONG : 0) +#define LENCILQR(neg) ((neg) ? CILEN_LQR: 0) +#define LENCICBCP(neg) ((neg) ? CILEN_CBCP: 0) + /* + * NB: we only ask for one of CHAP and UPAP, even if we will + * accept either. + */ + return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) + + LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) + + LENCICHAP(go->neg_chap) + + LENCISHORT(!go->neg_chap && go->neg_upap) + + LENCILQR(go->neg_lqr) + + LENCICBCP(go->neg_cbcp) + + LENCILONG(go->neg_magicnumber) + + LENCIVOID(go->neg_pcompression) + + LENCIVOID(go->neg_accompression)); +} + + +/* + * lcp_addci - Add our desired CIs to a packet. + */ +static void lcp_addci(fsm *f, u_char *ucp, int *lenp) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + u_char *start_ucp = ucp; + +#define ADDCIVOID(opt, neg) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_VOID, ucp); \ + } +#define ADDCISHORT(opt, neg, val) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_SHORT, ucp); \ + PUTSHORT(val, ucp); \ + } +#define ADDCICHAP(opt, neg, val, digest) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_CHAP, ucp); \ + PUTSHORT(val, ucp); \ + PUTCHAR(digest, ucp); \ + } +#define ADDCILONG(opt, neg, val) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_LONG, ucp); \ + PUTLONG(val, ucp); \ + } +#define ADDCILQR(opt, neg, val) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_LQR, ucp); \ + PUTSHORT(PPP_LQR, ucp); \ + PUTLONG(val, ucp); \ + } +#define ADDCICHAR(opt, neg, val) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_CHAR, ucp); \ + PUTCHAR(val, ucp); \ + } + + ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); + ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, + go->asyncmap); + ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); + ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); + ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); + ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); + ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); + ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression); + ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression); + + if (ucp - start_ucp != *lenp) { + /* this should never happen, because peer_mtu should be 1500 */ + LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n")); + } +} + + +/* + * lcp_ackci - Ack our CIs. + * This should not modify any state if the Ack is bad. + * + * Returns: + * 0 - Ack was bad. + * 1 - Ack was good. + */ +static int lcp_ackci(fsm *f, u_char *p, int len) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + u_char cilen, citype, cichar; + u_short cishort; + u32_t cilong; + + /* + * CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define ACKCIVOID(opt, neg) \ + if (neg) { \ + if ((len -= CILEN_VOID) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_VOID || \ + citype != opt) \ + goto bad; \ + } +#define ACKCISHORT(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_SHORT) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_SHORT || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + } +#define ACKCICHAR(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_CHAR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_CHAR || \ + citype != opt) \ + goto bad; \ + GETCHAR(cichar, p); \ + if (cichar != val) \ + goto bad; \ + } +#define ACKCICHAP(opt, neg, val, digest) \ + if (neg) { \ + if ((len -= CILEN_CHAP) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_CHAP || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + GETCHAR(cichar, p); \ + if (cichar != digest) \ + goto bad; \ + } +#define ACKCILONG(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_LONG) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_LONG || \ + citype != opt) \ + goto bad; \ + GETLONG(cilong, p); \ + if (cilong != val) \ + goto bad; \ + } +#define ACKCILQR(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_LQR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_LQR || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != PPP_LQR) \ + goto bad; \ + GETLONG(cilong, p); \ + if (cilong != val) \ + goto bad; \ + } + + ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); + ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, + go->asyncmap); + ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); + ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); + ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); + ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); + ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); + ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression); + ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n")); + return (1); +bad: + LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n")); + return (0); +} + + +/* + * lcp_nakci - Peer has sent a NAK for some of our CIs. + * This should not modify any state if the Nak is bad + * or if LCP is in the OPENED state. + * + * Returns: + * 0 - Nak was bad. + * 1 - Nak was good. + */ +static int lcp_nakci(fsm *f, u_char *p, int len) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + lcp_options *wo = &lcp_wantoptions[f->unit]; + u_char citype, cichar, *next; + u_short cishort; + u32_t cilong; + lcp_options no; /* options we've seen Naks for */ + lcp_options try; /* options to request next time */ + int looped_back = 0; + int cilen; + + BZERO(&no, sizeof(no)); + try = *go; + + /* + * Any Nak'd CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define NAKCIVOID(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_VOID && \ + p[1] == CILEN_VOID && \ + p[0] == opt) { \ + len -= CILEN_VOID; \ + INCPTR(CILEN_VOID, p); \ + no.neg = 1; \ + code \ + } +#define NAKCICHAP(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + no.neg = 1; \ + code \ + } +#define NAKCICHAR(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_CHAR && \ + p[1] == CILEN_CHAR && \ + p[0] == opt) { \ + len -= CILEN_CHAR; \ + INCPTR(2, p); \ + GETCHAR(cichar, p); \ + no.neg = 1; \ + code \ + } +#define NAKCISHORT(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_SHORT && \ + p[1] == CILEN_SHORT && \ + p[0] == opt) { \ + len -= CILEN_SHORT; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + no.neg = 1; \ + code \ + } +#define NAKCILONG(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_LONG && \ + p[1] == CILEN_LONG && \ + p[0] == opt) { \ + len -= CILEN_LONG; \ + INCPTR(2, p); \ + GETLONG(cilong, p); \ + no.neg = 1; \ + code \ + } +#define NAKCILQR(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_LQR && \ + p[1] == CILEN_LQR && \ + p[0] == opt) { \ + len -= CILEN_LQR; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETLONG(cilong, p); \ + no.neg = 1; \ + code \ + } + + /* + * We don't care if they want to send us smaller packets than + * we want. Therefore, accept any MRU less than what we asked for, + * but then ignore the new value when setting the MRU in the kernel. + * If they send us a bigger MRU than what we asked, accept it, up to + * the limit of the default MRU we'd get if we didn't negotiate. + */ + if (go->neg_mru && go->mru != PPP_DEFMRU) { + NAKCISHORT(CI_MRU, neg_mru, + if (cishort <= wo->mru || cishort < PPP_DEFMRU) + try.mru = cishort; + ); + } + + /* + * Add any characters they want to our (receive-side) asyncmap. + */ + if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) { + NAKCILONG(CI_ASYNCMAP, neg_asyncmap, + try.asyncmap = go->asyncmap | cilong; + ); + } + + /* + * If they've nak'd our authentication-protocol, check whether + * they are proposing a different protocol, or a different + * hash algorithm for CHAP. + */ + if ((go->neg_chap || go->neg_upap) + && len >= CILEN_SHORT + && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) { + cilen = p[1]; + len -= cilen; + no.neg_chap = go->neg_chap; + no.neg_upap = go->neg_upap; + INCPTR(2, p); + GETSHORT(cishort, p); + if (cishort == PPP_PAP && cilen == CILEN_SHORT) { + /* + * If we were asking for CHAP, they obviously don't want to do it. + * If we weren't asking for CHAP, then we were asking for PAP, + * in which case this Nak is bad. + */ + if (!go->neg_chap) + goto bad; + try.neg_chap = 0; + + } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) { + GETCHAR(cichar, p); + if (go->neg_chap) { + /* + * We were asking for CHAP/MD5; they must want a different + * algorithm. If they can't do MD5, we'll have to stop + * asking for CHAP. + */ + if (cichar != go->chap_mdtype) + try.neg_chap = 0; + } else { + /* + * Stop asking for PAP if we were asking for it. + */ + try.neg_upap = 0; + } + + } else { + /* + * We don't recognize what they're suggesting. + * Stop asking for what we were asking for. + */ + if (go->neg_chap) + try.neg_chap = 0; + else + try.neg_upap = 0; + p += cilen - CILEN_SHORT; + } + } + + /* + * If they can't cope with our link quality protocol, we'll have + * to stop asking for LQR. We haven't got any other protocol. + * If they Nak the reporting period, take their value XXX ? + */ + NAKCILQR(CI_QUALITY, neg_lqr, + if (cishort != PPP_LQR) + try.neg_lqr = 0; + else + try.lqr_period = cilong; + ); + + /* + * Only implementing CBCP...not the rest of the callback options + */ + NAKCICHAR(CI_CALLBACK, neg_cbcp, + try.neg_cbcp = 0; + ); + + /* + * Check for a looped-back line. + */ + NAKCILONG(CI_MAGICNUMBER, neg_magicnumber, + try.magicnumber = magic(); + looped_back = 1; + ); + + /* + * Peer shouldn't send Nak for protocol compression or + * address/control compression requests; they should send + * a Reject instead. If they send a Nak, treat it as a Reject. + */ + NAKCIVOID(CI_PCOMPRESSION, neg_pcompression, + try.neg_pcompression = 0; + ); + NAKCIVOID(CI_ACCOMPRESSION, neg_accompression, + try.neg_accompression = 0; + ); + + /* + * There may be remaining CIs, if the peer is requesting negotiation + * on an option that we didn't include in our request packet. + * If we see an option that we requested, or one we've already seen + * in this packet, then this packet is bad. + * If we wanted to respond by starting to negotiate on the requested + * option(s), we could, but we don't, because except for the + * authentication type and quality protocol, if we are not negotiating + * an option, it is because we were told not to. + * For the authentication type, the Nak from the peer means + * `let me authenticate myself with you' which is a bit pointless. + * For the quality protocol, the Nak means `ask me to send you quality + * reports', but if we didn't ask for them, we don't want them. + * An option we don't recognize represents the peer asking to + * negotiate some option we don't support, so ignore it. + */ + while (len > CILEN_VOID) { + GETCHAR(citype, p); + GETCHAR(cilen, p); + if (cilen < CILEN_VOID || (len -= cilen) < 0) + goto bad; + next = p + cilen - 2; + + switch (citype) { + case CI_MRU: + if ((go->neg_mru && go->mru != PPP_DEFMRU) + || no.neg_mru || cilen != CILEN_SHORT) + goto bad; + GETSHORT(cishort, p); + if (cishort < PPP_DEFMRU) + try.mru = cishort; + break; + case CI_ASYNCMAP: + if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) + || no.neg_asyncmap || cilen != CILEN_LONG) + goto bad; + break; + case CI_AUTHTYPE: + if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap) + goto bad; + break; + case CI_MAGICNUMBER: + if (go->neg_magicnumber || no.neg_magicnumber || + cilen != CILEN_LONG) + goto bad; + break; + case CI_PCOMPRESSION: + if (go->neg_pcompression || no.neg_pcompression + || cilen != CILEN_VOID) + goto bad; + break; + case CI_ACCOMPRESSION: + if (go->neg_accompression || no.neg_accompression + || cilen != CILEN_VOID) + goto bad; + break; + case CI_QUALITY: + if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) + goto bad; + break; + } + p = next; + } + + /* If there is still anything left, this packet is bad. */ + if (len != 0) + goto bad; + + /* + * OK, the Nak is good. Now we can update state. + */ + if (f->state != OPENED) { + if (looped_back) { + if (++try.numloops >= lcp_loopbackfail) { + LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n")); + lcp_close(f->unit, "Loopback detected"); + } + } + else + try.numloops = 0; + *go = try; + } + + return 1; + +bad: + LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n")); + return 0; +} + + +/* + * lcp_rejci - Peer has Rejected some of our CIs. + * This should not modify any state if the Reject is bad + * or if LCP is in the OPENED state. + * + * Returns: + * 0 - Reject was bad. + * 1 - Reject was good. + */ +static int lcp_rejci(fsm *f, u_char *p, int len) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + u_char cichar; + u_short cishort; + u32_t cilong; + lcp_options try; /* options to request next time */ + + try = *go; + + /* + * Any Rejected CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define REJCIVOID(opt, neg) \ + if (go->neg && \ + len >= CILEN_VOID && \ + p[1] == CILEN_VOID && \ + p[0] == opt) { \ + len -= CILEN_VOID; \ + INCPTR(CILEN_VOID, p); \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \ + } +#define REJCISHORT(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_SHORT && \ + p[1] == CILEN_SHORT && \ + p[0] == opt) { \ + len -= CILEN_SHORT; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + /* Check rejected value. */ \ + if (cishort != val) \ + goto bad; \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \ + } +#define REJCICHAP(opt, neg, val, digest) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if (cishort != val || cichar != digest) \ + goto bad; \ + try.neg = 0; \ + try.neg_upap = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \ + } +#define REJCILONG(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_LONG && \ + p[1] == CILEN_LONG && \ + p[0] == opt) { \ + len -= CILEN_LONG; \ + INCPTR(2, p); \ + GETLONG(cilong, p); \ + /* Check rejected value. */ \ + if (cilong != val) \ + goto bad; \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \ + } +#define REJCILQR(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_LQR && \ + p[1] == CILEN_LQR && \ + p[0] == opt) { \ + len -= CILEN_LQR; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETLONG(cilong, p); \ + /* Check rejected value. */ \ + if (cishort != PPP_LQR || cilong != val) \ + goto bad; \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \ + } +#define REJCICBCP(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_CBCP && \ + p[1] == CILEN_CBCP && \ + p[0] == opt) { \ + len -= CILEN_CBCP; \ + INCPTR(2, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if (cichar != val) \ + goto bad; \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \ + } + + REJCISHORT(CI_MRU, neg_mru, go->mru); + REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap); + REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype); + if (!go->neg_chap) { + REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP); + } + REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period); + REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT); + REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber); + REJCIVOID(CI_PCOMPRESSION, neg_pcompression); + REJCIVOID(CI_ACCOMPRESSION, neg_accompression); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + /* + * Now we can update state. + */ + if (f->state != OPENED) + *go = try; + return 1; + +bad: + LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n")); + return 0; +} + + +/* + * lcp_reqci - Check the peer's requested CIs and send appropriate response. + * + * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified + * appropriately. If reject_if_disagree is non-zero, doesn't return + * CONFNAK; returns CONFREJ if it can't return CONFACK. + */ +static int lcp_reqci(fsm *f, + u_char *inp, /* Requested CIs */ + int *lenp, /* Length of requested CIs */ + int reject_if_disagree) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + lcp_options *ho = &lcp_hisoptions[f->unit]; + lcp_options *ao = &lcp_allowoptions[f->unit]; + u_char *cip, *next; /* Pointer to current and next CIs */ + int cilen, citype, cichar; /* Parsed len, type, char value */ + u_short cishort; /* Parsed short value */ + u32_t cilong; /* Parse long value */ + int rc = CONFACK; /* Final packet return code */ + int orc; /* Individual option return code */ + u_char *p; /* Pointer to next char to parse */ + u_char *rejp; /* Pointer to next char in reject frame */ + u_char *nakp; /* Pointer to next char in Nak frame */ + int l = *lenp; /* Length left */ +#if TRACELCP > 0 + char traceBuf[80]; + int traceNdx = 0; +#endif + + /* + * Reset all his options. + */ + BZERO(ho, sizeof(*ho)); + + /* + * Process all his options. + */ + next = inp; + nakp = nak_buffer; + rejp = inp; + while (l) { + orc = CONFACK; /* Assume success */ + cip = p = next; /* Remember begining of CI */ + if (l < 2 || /* Not enough data for CI header or */ + p[1] < 2 || /* CI length too small or */ + p[1] > l) { /* CI length too big? */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n")); + orc = CONFREJ; /* Reject bad CI */ + cilen = l; /* Reject till end of packet */ + l = 0; /* Don't loop again */ + citype = 0; + goto endswitch; + } + GETCHAR(citype, p); /* Parse CI type */ + GETCHAR(cilen, p); /* Parse CI length */ + l -= cilen; /* Adjust remaining length */ + next += cilen; /* Step to next CI */ + + switch (citype) { /* Check CI type */ + case CI_MRU: + if (!ao->neg_mru) { /* Allow option? */ + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n")); + orc = CONFREJ; /* Reject CI */ + break; + } else if (cilen != CILEN_SHORT) { /* Check CI length */ + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n")); + orc = CONFREJ; /* Reject CI */ + break; + } + GETSHORT(cishort, p); /* Parse MRU */ + + /* + * He must be able to receive at least our minimum. + * No need to check a maximum. If he sends a large number, + * we'll just ignore it. + */ + if (cishort < PPP_MINMRU) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n")); + orc = CONFNAK; /* Nak CI */ + PUTCHAR(CI_MRU, nakp); + PUTCHAR(CILEN_SHORT, nakp); + PUTSHORT(PPP_MINMRU, nakp); /* Give him a hint */ + break; + } + ho->neg_mru = 1; /* Remember he sent MRU */ + ho->mru = cishort; /* And remember value */ +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort); + traceNdx = strlen(traceBuf); +#endif + break; + + case CI_ASYNCMAP: + if (!ao->neg_asyncmap) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_LONG) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n")); + orc = CONFREJ; + break; + } + GETLONG(cilong, p); + + /* + * Asyncmap must have set at least the bits + * which are set in lcp_allowoptions[unit].asyncmap. + */ + if ((ao->asyncmap & ~cilong) != 0) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", + cilong, ao->asyncmap)); + orc = CONFNAK; + PUTCHAR(CI_ASYNCMAP, nakp); + PUTCHAR(CILEN_LONG, nakp); + PUTLONG(ao->asyncmap | cilong, nakp); + break; + } + ho->neg_asyncmap = 1; + ho->asyncmap = cilong; +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong); + traceNdx = strlen(traceBuf); +#endif + break; + + case CI_AUTHTYPE: + if (cilen < CILEN_SHORT) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n")); + orc = CONFREJ; + break; + } else if (!(ao->neg_upap || ao->neg_chap)) { + /* + * Reject the option if we're not willing to authenticate. + */ + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n")); + orc = CONFREJ; + break; + } + GETSHORT(cishort, p); + + /* + * Authtype must be UPAP or CHAP. + * + * Note: if both ao->neg_upap and ao->neg_chap are set, + * and the peer sends a Configure-Request with two + * authenticate-protocol requests, one for CHAP and one + * for UPAP, then we will reject the second request. + * Whether we end up doing CHAP or UPAP depends then on + * the ordering of the CIs in the peer's Configure-Request. + */ + + if (cishort == PPP_PAP) { + if (ho->neg_chap) { /* we've already accepted CHAP */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_SHORT) { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n")); + orc = CONFREJ; + break; + } + if (!ao->neg_upap) { /* we don't want to do PAP */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n")); + orc = CONFNAK; /* NAK it and suggest CHAP */ + PUTCHAR(CI_AUTHTYPE, nakp); + PUTCHAR(CILEN_CHAP, nakp); + PUTSHORT(PPP_CHAP, nakp); + PUTCHAR(ao->chap_mdtype, nakp); + break; + } + ho->neg_upap = 1; +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort); + traceNdx = strlen(traceBuf); +#endif + break; + } + if (cishort == PPP_CHAP) { + if (ho->neg_upap) { /* we've already accepted PAP */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_CHAP) { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n")); + orc = CONFREJ; + break; + } + if (!ao->neg_chap) { /* we don't want to do CHAP */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n")); + orc = CONFNAK; /* NAK it and suggest PAP */ + PUTCHAR(CI_AUTHTYPE, nakp); + PUTCHAR(CILEN_SHORT, nakp); + PUTSHORT(PPP_PAP, nakp); + break; + } + GETCHAR(cichar, p); /* get digest type*/ + if (cichar != CHAP_DIGEST_MD5 +#ifdef CHAPMS + && cichar != CHAP_MICROSOFT +#endif + ) { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar)); + orc = CONFNAK; + PUTCHAR(CI_AUTHTYPE, nakp); + PUTCHAR(CILEN_CHAP, nakp); + PUTSHORT(PPP_CHAP, nakp); + PUTCHAR(ao->chap_mdtype, nakp); + break; + } +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar); + traceNdx = strlen(traceBuf); +#endif + ho->chap_mdtype = cichar; /* save md type */ + ho->neg_chap = 1; + break; + } + + /* + * We don't recognize the protocol they're asking for. + * Nak it with something we're willing to do. + * (At this point we know ao->neg_upap || ao->neg_chap.) + */ + orc = CONFNAK; + PUTCHAR(CI_AUTHTYPE, nakp); + if (ao->neg_chap) { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort)); + PUTCHAR(CILEN_CHAP, nakp); + PUTSHORT(PPP_CHAP, nakp); + PUTCHAR(ao->chap_mdtype, nakp); + } + else { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort)); + PUTCHAR(CILEN_SHORT, nakp); + PUTSHORT(PPP_PAP, nakp); + } + break; + + case CI_QUALITY: + GETSHORT(cishort, p); + GETLONG(cilong, p); +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong); + traceNdx = strlen(traceBuf); +#endif + + if (!ao->neg_lqr || + cilen != CILEN_LQR) { + orc = CONFREJ; + break; + } + + /* + * Check the protocol and the reporting period. + * XXX When should we Nak this, and what with? + */ + if (cishort != PPP_LQR) { + orc = CONFNAK; + PUTCHAR(CI_QUALITY, nakp); + PUTCHAR(CILEN_LQR, nakp); + PUTSHORT(PPP_LQR, nakp); + PUTLONG(ao->lqr_period, nakp); + break; + } + break; + + case CI_MAGICNUMBER: + if (!(ao->neg_magicnumber || go->neg_magicnumber) || + cilen != CILEN_LONG) { + orc = CONFREJ; + break; + } + GETLONG(cilong, p); +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong); + traceNdx = strlen(traceBuf); +#endif + + /* + * He must have a different magic number. + */ + if (go->neg_magicnumber && + cilong == go->magicnumber) { + cilong = magic(); /* Don't put magic() inside macro! */ + orc = CONFNAK; + PUTCHAR(CI_MAGICNUMBER, nakp); + PUTCHAR(CILEN_LONG, nakp); + PUTLONG(cilong, nakp); + break; + } + ho->neg_magicnumber = 1; + ho->magicnumber = cilong; + break; + + + case CI_PCOMPRESSION: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION"); + traceNdx = strlen(traceBuf); +#endif + if (!ao->neg_pcompression || + cilen != CILEN_VOID) { + orc = CONFREJ; + break; + } + ho->neg_pcompression = 1; + break; + + case CI_ACCOMPRESSION: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION"); + traceNdx = strlen(traceBuf); +#endif + if (!ao->neg_accompression || + cilen != CILEN_VOID) { + orc = CONFREJ; + break; + } + ho->neg_accompression = 1; + break; + + case CI_MRRU: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU"); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + + case CI_SSNHF: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF"); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + + case CI_EPDISC: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC"); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + + default: +#if TRACELCP + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + } + + endswitch: +#if TRACELCP + if (traceNdx >= 80 - 32) { + LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf)); + traceNdx = 0; + } +#endif + if (orc == CONFACK && /* Good CI */ + rc != CONFACK) /* but prior CI wasnt? */ + continue; /* Don't send this one */ + + if (orc == CONFNAK) { /* Nak this CI? */ + if (reject_if_disagree /* Getting fed up with sending NAKs? */ + && citype != CI_MAGICNUMBER) { + orc = CONFREJ; /* Get tough if so */ + } + else { + if (rc == CONFREJ) /* Rejecting prior CI? */ + continue; /* Don't send this one */ + rc = CONFNAK; + } + } + if (orc == CONFREJ) { /* Reject this CI */ + rc = CONFREJ; + if (cip != rejp) /* Need to move rejected CI? */ + BCOPY(cip, rejp, cilen); /* Move it */ + INCPTR(cilen, rejp); /* Update output pointer */ + } + } + + /* + * If we wanted to send additional NAKs (for unsent CIs), the + * code would go here. The extra NAKs would go at *nakp. + * At present there are no cases where we want to ask the + * peer to negotiate an option. + */ + + switch (rc) { + case CONFACK: + *lenp = (int)(next - inp); + break; + case CONFNAK: + /* + * Copy the Nak'd options from the nak_buffer to the caller's buffer. + */ + *lenp = (int)(nakp - nak_buffer); + BCOPY(nak_buffer, inp, *lenp); + break; + case CONFREJ: + *lenp = (int)(rejp - inp); + break; + } + +#if TRACELCP > 0 + if (traceNdx > 0) { + LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf)); + } +#endif + LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc))); + return (rc); /* Return final code */ +} + + +/* + * lcp_up - LCP has come UP. + */ +static void lcp_up(fsm *f) +{ + lcp_options *wo = &lcp_wantoptions[f->unit]; + lcp_options *ho = &lcp_hisoptions[f->unit]; + lcp_options *go = &lcp_gotoptions[f->unit]; + lcp_options *ao = &lcp_allowoptions[f->unit]; + + if (!go->neg_magicnumber) + go->magicnumber = 0; + if (!ho->neg_magicnumber) + ho->magicnumber = 0; + + /* + * Set our MTU to the smaller of the MTU we wanted and + * the MRU our peer wanted. If we negotiated an MRU, + * set our MRU to the larger of value we wanted and + * the value we got in the negotiation. + */ + ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)), + (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl), + ho->neg_pcompression, ho->neg_accompression); + /* + * If the asyncmap hasn't been negotiated, we really should + * set the receive asyncmap to ffffffff, but we set it to 0 + * for backwards contemptibility. + */ + ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU), + (go->neg_asyncmap? go->asyncmap: 0x00000000), + go->neg_pcompression, go->neg_accompression); + + if (ho->neg_mru) + peer_mru[f->unit] = ho->mru; + + lcp_echo_lowerup(f->unit); /* Enable echo messages */ + + link_established(f->unit); +} + + +/* + * lcp_down - LCP has gone DOWN. + * + * Alert other protocols. + */ +static void lcp_down(fsm *f) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + + lcp_echo_lowerdown(f->unit); + + link_down(f->unit); + + ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0); + ppp_recv_config(f->unit, PPP_MRU, + (go->neg_asyncmap? go->asyncmap: 0x00000000), + go->neg_pcompression, go->neg_accompression); + peer_mru[f->unit] = PPP_MRU; +} + + +/* + * lcp_starting - LCP needs the lower layer up. + */ +static void lcp_starting(fsm *f) +{ + link_required(f->unit); +} + + +/* + * lcp_finished - LCP has finished with the lower layer. + */ +static void lcp_finished(fsm *f) +{ + link_terminated(f->unit); +} + + +#if 0 +/* + * print_string - print a readable representation of a string using + * printer. + */ +static void print_string( + char *p, + int len, + void (*printer) (void *, char *, ...), + void *arg +) +{ + int c; + + printer(arg, "\""); + for (; len > 0; --len) { + c = *p++; + if (' ' <= c && c <= '~') { + if (c == '\\' || c == '"') + printer(arg, "\\"); + printer(arg, "%c", c); + } else { + switch (c) { + case '\n': + printer(arg, "\\n"); + break; + case '\r': + printer(arg, "\\r"); + break; + case '\t': + printer(arg, "\\t"); + break; + default: + printer(arg, "\\%.3o", c); + } + } + } + printer(arg, "\""); +} + + +/* + * lcp_printpkt - print the contents of an LCP packet. + */ +static char *lcp_codenames[] = { + "ConfReq", "ConfAck", "ConfNak", "ConfRej", + "TermReq", "TermAck", "CodeRej", "ProtRej", + "EchoReq", "EchoRep", "DiscReq" +}; + +static int lcp_printpkt( + u_char *p, + int plen, + void (*printer) (void *, char *, ...), + void *arg +) +{ + int code, id, len, olen; + u_char *pstart, *optend; + u_short cishort; + u32_t cilong; + + if (plen < HEADERLEN) + return 0; + pstart = p; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < HEADERLEN || len > plen) + return 0; + + if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *)) + printer(arg, " %s", lcp_codenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= HEADERLEN; + switch (code) { + case CONFREQ: + case CONFACK: + case CONFNAK: + case CONFREJ: + /* print option list */ + while (len >= 2) { + GETCHAR(code, p); + GETCHAR(olen, p); + p -= 2; + if (olen < 2 || olen > len) { + break; + } + printer(arg, " <"); + len -= olen; + optend = p + olen; + switch (code) { + case CI_MRU: + if (olen == CILEN_SHORT) { + p += 2; + GETSHORT(cishort, p); + printer(arg, "mru %d", cishort); + } + break; + case CI_ASYNCMAP: + if (olen == CILEN_LONG) { + p += 2; + GETLONG(cilong, p); + printer(arg, "asyncmap 0x%lx", cilong); + } + break; + case CI_AUTHTYPE: + if (olen >= CILEN_SHORT) { + p += 2; + printer(arg, "auth "); + GETSHORT(cishort, p); + switch (cishort) { + case PPP_PAP: + printer(arg, "pap"); + break; + case PPP_CHAP: + printer(arg, "chap"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_QUALITY: + if (olen >= CILEN_SHORT) { + p += 2; + printer(arg, "quality "); + GETSHORT(cishort, p); + switch (cishort) { + case PPP_LQR: + printer(arg, "lqr"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_CALLBACK: + if (olen >= CILEN_CHAR) { + p += 2; + printer(arg, "callback "); + GETSHORT(cishort, p); + switch (cishort) { + case CBCP_OPT: + printer(arg, "CBCP"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_MAGICNUMBER: + if (olen == CILEN_LONG) { + p += 2; + GETLONG(cilong, p); + printer(arg, "magic 0x%x", cilong); + } + break; + case CI_PCOMPRESSION: + if (olen == CILEN_VOID) { + p += 2; + printer(arg, "pcomp"); + } + break; + case CI_ACCOMPRESSION: + if (olen == CILEN_VOID) { + p += 2; + printer(arg, "accomp"); + } + break; + } + while (p < optend) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + printer(arg, ">"); + } + break; + + case TERMACK: + case TERMREQ: + if (len > 0 && *p >= ' ' && *p < 0x7f) { + printer(arg, " "); + print_string((char*)p, len, printer, arg); + p += len; + len = 0; + } + break; + + case ECHOREQ: + case ECHOREP: + case DISCREQ: + if (len >= 4) { + GETLONG(cilong, p); + printer(arg, " magic=0x%x", cilong); + p += 4; + len -= 4; + } + break; + } + + /* print the rest of the bytes in the packet */ + for (; len > 0; --len) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + + return (int)(p - pstart); +} +#endif + +/* + * Time to shut down the link because there is nothing out there. + */ + +static void LcpLinkFailure (fsm *f) +{ + if (f->state == OPENED) { + LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending)); + LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n")); + lcp_close(f->unit, "Peer not responding"); + } +} + +/* + * Timer expired for the LCP echo requests from this process. + */ + +static void LcpEchoCheck (fsm *f) +{ + LcpSendEchoRequest (f); + + /* + * Start the timer for the next interval. + */ + LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0); + + TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval); + lcp_echo_timer_running = 1; +} + +/* + * LcpEchoTimeout - Timer expired on the LCP echo + */ + +static void LcpEchoTimeout (void *arg) +{ + if (lcp_echo_timer_running != 0) { + lcp_echo_timer_running = 0; + LcpEchoCheck ((fsm *) arg); + } +} + +/* + * LcpEchoReply - LCP has received a reply to the echo + */ +static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len) +{ + u32_t magic; + + (void)id; + + /* Check the magic number - don't count replies from ourselves. */ + if (len < 4) { + LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len)); + return; + } + GETLONG(magic, inp); + if (lcp_gotoptions[f->unit].neg_magicnumber + && magic == lcp_gotoptions[f->unit].magicnumber) { + LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n")); + return; + } + + /* Reset the number of outstanding echo frames */ + lcp_echos_pending = 0; +} + +/* + * LcpSendEchoRequest - Send an echo request frame to the peer + */ + +static void LcpSendEchoRequest (fsm *f) +{ + u32_t lcp_magic; + u_char pkt[4], *pktp; + + /* + * Detect the failure of the peer at this point. + */ + if (lcp_echo_fails != 0) { + if (lcp_echos_pending++ >= lcp_echo_fails) { + LcpLinkFailure(f); + lcp_echos_pending = 0; + } + } + + /* + * Make and send the echo request frame. + */ + if (f->state == OPENED) { + lcp_magic = lcp_gotoptions[f->unit].magicnumber; + pktp = pkt; + PUTLONG(lcp_magic, pktp); + fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt)); + } +} + +/* + * lcp_echo_lowerup - Start the timer for the LCP frame + */ + +static void lcp_echo_lowerup (int unit) +{ + fsm *f = &lcp_fsm[unit]; + + /* Clear the parameters for generating echo frames */ + lcp_echos_pending = 0; + lcp_echo_number = 0; + lcp_echo_timer_running = 0; + + /* If a timeout interval is specified then start the timer */ + if (lcp_echo_interval != 0) + LcpEchoCheck (f); +} + +/* + * lcp_echo_lowerdown - Stop the timer for the LCP frame + */ + +static void lcp_echo_lowerdown (int unit) +{ + fsm *f = &lcp_fsm[unit]; + + if (lcp_echo_timer_running != 0) { + UNTIMEOUT (LcpEchoTimeout, f); + lcp_echo_timer_running = 0; + } +} + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/lcp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/lcp.h new file mode 100644 index 0000000..2c0c340 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/lcp.h @@ -0,0 +1,169 @@ +/***************************************************************************** +* lcp.h - Network Link Control Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * lcp.h - Link Control Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: lcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef LCP_H +#define LCP_H + + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ +/* + * Options. + */ +#define CI_MRU 1 /* Maximum Receive Unit */ +#define CI_ASYNCMAP 2 /* Async Control Character Map */ +#define CI_AUTHTYPE 3 /* Authentication Type */ +#define CI_QUALITY 4 /* Quality Protocol */ +#define CI_MAGICNUMBER 5 /* Magic Number */ +#define CI_PCOMPRESSION 7 /* Protocol Field Compression */ +#define CI_ACCOMPRESSION 8 /* Address/Control Field Compression */ +#define CI_CALLBACK 13 /* callback */ +#define CI_MRRU 17 /* max reconstructed receive unit; multilink */ +#define CI_SSNHF 18 /* short sequence numbers for multilink */ +#define CI_EPDISC 19 /* endpoint discriminator */ + +/* + * LCP-specific packet types. + */ +#define PROTREJ 8 /* Protocol Reject */ +#define ECHOREQ 9 /* Echo Request */ +#define ECHOREP 10 /* Echo Reply */ +#define DISCREQ 11 /* Discard Request */ +#define CBCP_OPT 6 /* Use callback control protocol */ + + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * The state of options is described by an lcp_options structure. + */ +typedef struct lcp_options { + u_int passive : 1; /* Don't die if we don't get a response */ + u_int silent : 1; /* Wait for the other end to start first */ + u_int restart : 1; /* Restart vs. exit after close */ + u_int neg_mru : 1; /* Negotiate the MRU? */ + u_int neg_asyncmap : 1; /* Negotiate the async map? */ + u_int neg_upap : 1; /* Ask for UPAP authentication? */ + u_int neg_chap : 1; /* Ask for CHAP authentication? */ + u_int neg_magicnumber : 1; /* Ask for magic number? */ + u_int neg_pcompression : 1; /* HDLC Protocol Field Compression? */ + u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */ + u_int neg_lqr : 1; /* Negotiate use of Link Quality Reports */ + u_int neg_cbcp : 1; /* Negotiate use of CBCP */ +#ifdef PPP_MULTILINK + u_int neg_mrru : 1; /* Negotiate multilink MRRU */ + u_int neg_ssnhf : 1; /* Negotiate short sequence numbers */ + u_int neg_endpoint : 1; /* Negotiate endpoint discriminator */ +#endif + u_short mru; /* Value of MRU */ +#ifdef PPP_MULTILINK + u_short mrru; /* Value of MRRU, and multilink enable */ +#endif + u_char chap_mdtype; /* which MD type (hashing algorithm) */ + u32_t asyncmap; /* Value of async map */ + u32_t magicnumber; + int numloops; /* Number of loops during magic number neg. */ + u32_t lqr_period; /* Reporting period for LQR 1/100ths second */ +#ifdef PPP_MULTILINK + struct epdisc endpoint; /* endpoint discriminator */ +#endif +} lcp_options; + +/* + * Values for phase from BSD pppd.h based on RFC 1661. + */ +typedef enum { + PHASE_DEAD = 0, + PHASE_INITIALIZE, + PHASE_ESTABLISH, + PHASE_AUTHENTICATE, + PHASE_CALLBACK, + PHASE_NETWORK, + PHASE_TERMINATE +} LinkPhase; + + +/***************************** +*** PUBLIC DATA STRUCTURES *** +*****************************/ + +extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ +extern lcp_options lcp_wantoptions[]; +extern lcp_options lcp_gotoptions[]; +extern lcp_options lcp_allowoptions[]; +extern lcp_options lcp_hisoptions[]; +extern ext_accm xmit_accm[]; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +void lcp_init (int); +void lcp_open (int); +void lcp_close (int, char *); +void lcp_lowerup (int); +void lcp_lowerdown (int); +void lcp_sprotrej (int, u_char *, int); /* send protocol reject */ + +extern struct protent lcp_protent; + +/* Default number of times we receive our magic number from the peer + before deciding the link is looped-back. */ +#define DEFLOOPBACKFAIL 10 + +#endif /* LCP_H */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/magic.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/magic.c new file mode 100644 index 0000000..6e9d475 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/magic.c @@ -0,0 +1,79 @@ +/***************************************************************************** +* magic.c - Network Random Number Generator program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD magic.c. +*****************************************************************************/ +/* + * magic.c - PPP Magic Number routines. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "ppp.h" +#include "randm.h" +#include "magic.h" + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * magicInit - Initialize the magic number generator. + * + * Since we use another random number generator that has its own + * initialization, we do nothing here. + */ +void magicInit() +{ + return; +} + +/* + * magic - Returns the next magic number. + */ +u32_t magic() +{ + return avRandom(); +} + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/magic.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/magic.h new file mode 100644 index 0000000..6e9b10b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/magic.h @@ -0,0 +1,64 @@ +/***************************************************************************** +* magic.h - Network Random Number Generator header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * magic.h - PPP Magic Number definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: magic.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef MAGIC_H +#define MAGIC_H + +/***************************************************************************** +************************** PUBLIC FUNCTIONS ********************************** +*****************************************************************************/ + +void magicInit(void); /* Initialize the magic number generator */ +u32_t magic(void); /* Returns the next magic number */ + +#endif /* MAGIC_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/md5.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/md5.c new file mode 100644 index 0000000..488d64a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/md5.c @@ -0,0 +1,306 @@ +/* + *********************************************************************** + ** md5.c -- the source code for MD5 routines ** + ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** + ** Created: 2/17/90 RLR ** + ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. ** + *********************************************************************** + */ + +/* + *********************************************************************** + ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** + ** ** + ** License to copy and use this software is granted provided that ** + ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** + ** Digest Algorithm" in all material mentioning or referencing this ** + ** software or this function. ** + ** ** + ** License is also granted to make and use derivative works ** + ** provided that such works are identified as "derived from the RSA ** + ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** + ** material mentioning or referencing the derived work. ** + ** ** + ** RSA Data Security, Inc. makes no representations concerning ** + ** either the merchantability of this software or the suitability ** + ** of this software for any particular purpose. It is provided "as ** + ** is" without express or implied warranty of any kind. ** + ** ** + ** These notices must be retained in any copies of any part of this ** + ** documentation and/or software. ** + *********************************************************************** + */ + +#include "ppp.h" +#include "md5.h" +#include "pppdebug.h" + +#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0 + +/* + *********************************************************************** + ** Message-digest routines: ** + ** To form the message digest for a message M ** + ** (1) Initialize a context buffer mdContext using MD5Init ** + ** (2) Call MD5Update on mdContext and M ** + ** (3) Call MD5Final on mdContext ** + ** The message digest is now in mdContext->digest[0...15] ** + *********************************************************************** + */ + +/* forward declaration */ +static void Transform (u32_t *buf, u32_t *in); + +static unsigned char PADDING[64] = { + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +/* F, G, H and I are basic MD5 functions */ +#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) +#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) +#define H(x, y, z) ((x) ^ (y) ^ (z)) +#define I(x, y, z) ((y) ^ ((x) | (~z))) + +/* ROTATE_LEFT rotates x left n bits */ +#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n)))) + +/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */ +/* Rotation is separate from addition to prevent recomputation */ +#define FF(a, b, c, d, x, s, ac) \ + {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define GG(a, b, c, d, x, s, ac) \ + {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define HH(a, b, c, d, x, s, ac) \ + {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define II(a, b, c, d, x, s, ac) \ + {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } + +#ifdef __STDC__ +#define UL(x) x##UL +#else +#ifdef WIN32 +#define UL(x) x##UL +#else +#define UL(x) x +#endif +#endif + +/* The routine MD5Init initializes the message-digest context + mdContext. All fields are set to zero. + */ +void MD5Init (MD5_CTX *mdContext) +{ + mdContext->i[0] = mdContext->i[1] = (u32_t)0; + + /* Load magic initialization constants. + */ + mdContext->buf[0] = (u32_t)0x67452301UL; + mdContext->buf[1] = (u32_t)0xefcdab89UL; + mdContext->buf[2] = (u32_t)0x98badcfeUL; + mdContext->buf[3] = (u32_t)0x10325476UL; +} + +/* The routine MD5Update updates the message-digest context to + account for the presence of each of the characters inBuf[0..inLen-1] + in the message whose digest is being computed. + */ +void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen) +{ + u32_t in[16]; + int mdi; + unsigned int i, ii; + +#if 0 + ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf); + ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf); +#endif + + /* compute number of bytes mod 64 */ + mdi = (int)((mdContext->i[0] >> 3) & 0x3F); + + /* update number of bits */ + if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0]) + mdContext->i[1]++; + mdContext->i[0] += ((u32_t)inLen << 3); + mdContext->i[1] += ((u32_t)inLen >> 29); + + while (inLen--) { + /* add new character to buffer, increment mdi */ + mdContext->in[mdi++] = *inBuf++; + + /* transform if necessary */ + if (mdi == 0x40) { + for (i = 0, ii = 0; i < 16; i++, ii += 4) + in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | + (((u32_t)mdContext->in[ii+2]) << 16) | + (((u32_t)mdContext->in[ii+1]) << 8) | + ((u32_t)mdContext->in[ii]); + Transform (mdContext->buf, in); + mdi = 0; + } + } +} + +/* The routine MD5Final terminates the message-digest computation and + ends with the desired message digest in mdContext->digest[0...15]. + */ +void MD5Final (unsigned char hash[], MD5_CTX *mdContext) +{ + u32_t in[16]; + int mdi; + unsigned int i, ii; + unsigned int padLen; + + /* save number of bits */ + in[14] = mdContext->i[0]; + in[15] = mdContext->i[1]; + + /* compute number of bytes mod 64 */ + mdi = (int)((mdContext->i[0] >> 3) & 0x3F); + + /* pad out to 56 mod 64 */ + padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi); + MD5Update (mdContext, PADDING, padLen); + + /* append length in bits and transform */ + for (i = 0, ii = 0; i < 14; i++, ii += 4) + in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | + (((u32_t)mdContext->in[ii+2]) << 16) | + (((u32_t)mdContext->in[ii+1]) << 8) | + ((u32_t)mdContext->in[ii]); + Transform (mdContext->buf, in); + + /* store buffer in digest */ + for (i = 0, ii = 0; i < 4; i++, ii += 4) { + mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF); + mdContext->digest[ii+1] = + (unsigned char)((mdContext->buf[i] >> 8) & 0xFF); + mdContext->digest[ii+2] = + (unsigned char)((mdContext->buf[i] >> 16) & 0xFF); + mdContext->digest[ii+3] = + (unsigned char)((mdContext->buf[i] >> 24) & 0xFF); + } + memcpy(hash, mdContext->digest, 16); +} + +/* Basic MD5 step. Transforms buf based on in. + */ +static void Transform (u32_t *buf, u32_t *in) +{ + u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3]; + + /* Round 1 */ +#define S11 7 +#define S12 12 +#define S13 17 +#define S14 22 + FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */ + FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */ + FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */ + FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */ + FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */ + FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */ + FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */ + FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */ + FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */ + FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */ + FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */ + FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */ + FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */ + FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */ + FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */ + FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */ + + /* Round 2 */ +#define S21 5 +#define S22 9 +#define S23 14 +#define S24 20 + GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */ + GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */ + GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */ + GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */ + GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */ + GG ( d, a, b, c, in[10], S22, UL( 38016083)); /* 22 */ + GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */ + GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */ + GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */ + GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */ + GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */ + GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */ + GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */ + GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */ + GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */ + GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */ + + /* Round 3 */ +#define S31 4 +#define S32 11 +#define S33 16 +#define S34 23 + HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */ + HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */ + HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */ + HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */ + HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */ + HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */ + HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */ + HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */ + HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */ + HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */ + HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */ + HH ( b, c, d, a, in[ 6], S34, UL( 76029189)); /* 44 */ + HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */ + HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */ + HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */ + HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */ + + /* Round 4 */ +#define S41 6 +#define S42 10 +#define S43 15 +#define S44 21 + II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */ + II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */ + II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */ + II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */ + II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */ + II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */ + II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */ + II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */ + II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */ + II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */ + II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */ + II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */ + II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */ + II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */ + II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */ + II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */ + + buf[0] += a; + buf[1] += b; + buf[2] += c; + buf[3] += d; +} + +#endif + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/md5.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/md5.h new file mode 100644 index 0000000..83d318c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/md5.h @@ -0,0 +1,55 @@ +/* + *********************************************************************** + ** md5.h -- header file for implementation of MD5 ** + ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** + ** Created: 2/17/90 RLR ** + ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version ** + ** Revised (for MD5): RLR 4/27/91 ** + ** -- G modified to have y&~z instead of y&z ** + ** -- FF, GG, HH modified to add in last register done ** + ** -- Access pattern: round 2 works mod 5, round 3 works mod 3 ** + ** -- distinct additive constant for each step ** + ** -- round 4 added, working mod 7 ** + *********************************************************************** + */ + +/* + *********************************************************************** + ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** + ** ** + ** License to copy and use this software is granted provided that ** + ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** + ** Digest Algorithm" in all material mentioning or referencing this ** + ** software or this function. ** + ** ** + ** License is also granted to make and use derivative works ** + ** provided that such works are identified as "derived from the RSA ** + ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** + ** material mentioning or referencing the derived work. ** + ** ** + ** RSA Data Security, Inc. makes no representations concerning ** + ** either the merchantability of this software or the suitability ** + ** of this software for any particular purpose. It is provided "as ** + ** is" without express or implied warranty of any kind. ** + ** ** + ** These notices must be retained in any copies of any part of this ** + ** documentation and/or software. ** + *********************************************************************** + */ + +#ifndef MD5_H +#define MD5_H + +/* Data structure for MD5 (Message-Digest) computation */ +typedef struct { + u32_t i[2]; /* number of _bits_ handled mod 2^64 */ + u32_t buf[4]; /* scratch buffer */ + unsigned char in[64]; /* input buffer */ + unsigned char digest[16]; /* actual digest after MD5Final call */ +} MD5_CTX; + +void MD5Init (MD5_CTX *mdContext); +void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen); +void MD5Final (unsigned char hash[], MD5_CTX *mdContext); + +#endif /* MD5_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/pap.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/pap.c new file mode 100644 index 0000000..4b105ef --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/pap.c @@ -0,0 +1,608 @@ +/***************************************************************************** +* pap.c - Network Password Authentication Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-12 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ +/* + * upap.c - User/Password Authentication Protocol. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "ppp.h" +#include "auth.h" +#include "pap.h" +#include "pppdebug.h" + + +#if PAP_SUPPORT > 0 + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +/* + * Protocol entry points. + */ +static void upap_init (int); +static void upap_lowerup (int); +static void upap_lowerdown (int); +static void upap_input (int, u_char *, int); +static void upap_protrej (int); + +static void upap_timeout (void *); +static void upap_reqtimeout (void *); +static void upap_rauthreq (upap_state *, u_char *, int, int); +static void upap_rauthack (upap_state *, u_char *, int, int); +static void upap_rauthnak (upap_state *, u_char *, int, int); +static void upap_sauthreq (upap_state *); +static void upap_sresp (upap_state *, u_char, u_char, char *, int); + + + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +struct protent pap_protent = { + PPP_PAP, + upap_init, + upap_input, + upap_protrej, + upap_lowerup, + upap_lowerdown, + NULL, + NULL, +#if 0 + upap_printpkt, + NULL, +#endif + 1, + "PAP", +#if 0 + NULL, + NULL, + NULL +#endif +}; + +upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */ + + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * Set the default login name and password for the pap sessions + */ +void upap_setloginpasswd(int unit, const char *luser, const char *lpassword) +{ + upap_state *u = &upap[unit]; + + /* Save the username and password we're given */ + u->us_user = luser; + u->us_userlen = strlen(luser); + u->us_passwd = lpassword; + u->us_passwdlen = strlen(lpassword); +} + + +/* + * upap_authwithpeer - Authenticate us with our peer (start client). + * + * Set new state and send authenticate's. + */ +void upap_authwithpeer(int unit, char *user, char *password) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n", + unit, user, password, u->us_clientstate)); + + upap_setloginpasswd(unit, user, password); + + u->us_transmits = 0; + + /* Lower layer up yet? */ + if (u->us_clientstate == UPAPCS_INITIAL || + u->us_clientstate == UPAPCS_PENDING) { + u->us_clientstate = UPAPCS_PENDING; + return; + } + + upap_sauthreq(u); /* Start protocol */ +} + + +/* + * upap_authpeer - Authenticate our peer (start server). + * + * Set new state. + */ +void upap_authpeer(int unit) +{ + upap_state *u = &upap[unit]; + + /* Lower layer up yet? */ + if (u->us_serverstate == UPAPSS_INITIAL || + u->us_serverstate == UPAPSS_PENDING) { + u->us_serverstate = UPAPSS_PENDING; + return; + } + + u->us_serverstate = UPAPSS_LISTEN; + if (u->us_reqtimeout > 0) + TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); +} + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* + * upap_init - Initialize a UPAP unit. + */ +static void upap_init(int unit) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit)); + u->us_unit = unit; + u->us_user = NULL; + u->us_userlen = 0; + u->us_passwd = NULL; + u->us_passwdlen = 0; + u->us_clientstate = UPAPCS_INITIAL; + u->us_serverstate = UPAPSS_INITIAL; + u->us_id = 0; + u->us_timeouttime = UPAP_DEFTIMEOUT; + u->us_maxtransmits = 10; + u->us_reqtimeout = UPAP_DEFREQTIME; +} + +/* + * upap_timeout - Retransmission timer for sending auth-reqs expired. + */ +static void upap_timeout(void *arg) +{ + upap_state *u = (upap_state *) arg; + + UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", + u->us_unit, u->us_timeouttime, u->us_clientstate)); + + if (u->us_clientstate != UPAPCS_AUTHREQ) + return; + + if (u->us_transmits >= u->us_maxtransmits) { + /* give up in disgust */ + UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n")); + u->us_clientstate = UPAPCS_BADAUTH; + auth_withpeer_fail(u->us_unit, PPP_PAP); + return; + } + + upap_sauthreq(u); /* Send Authenticate-Request */ +} + + +/* + * upap_reqtimeout - Give up waiting for the peer to send an auth-req. + */ +static void upap_reqtimeout(void *arg) +{ + upap_state *u = (upap_state *) arg; + + if (u->us_serverstate != UPAPSS_LISTEN) + return; /* huh?? */ + + auth_peer_fail(u->us_unit, PPP_PAP); + u->us_serverstate = UPAPSS_BADAUTH; +} + + +/* + * upap_lowerup - The lower layer is up. + * + * Start authenticating if pending. + */ +static void upap_lowerup(int unit) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate)); + + if (u->us_clientstate == UPAPCS_INITIAL) + u->us_clientstate = UPAPCS_CLOSED; + else if (u->us_clientstate == UPAPCS_PENDING) { + upap_sauthreq(u); /* send an auth-request */ + } + + if (u->us_serverstate == UPAPSS_INITIAL) + u->us_serverstate = UPAPSS_CLOSED; + else if (u->us_serverstate == UPAPSS_PENDING) { + u->us_serverstate = UPAPSS_LISTEN; + if (u->us_reqtimeout > 0) + TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); + } +} + + +/* + * upap_lowerdown - The lower layer is down. + * + * Cancel all timeouts. + */ +static void upap_lowerdown(int unit) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate)); + + if (u->us_clientstate == UPAPCS_AUTHREQ) /* Timeout pending? */ + UNTIMEOUT(upap_timeout, u); /* Cancel timeout */ + if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0) + UNTIMEOUT(upap_reqtimeout, u); + + u->us_clientstate = UPAPCS_INITIAL; + u->us_serverstate = UPAPSS_INITIAL; +} + + +/* + * upap_protrej - Peer doesn't speak this protocol. + * + * This shouldn't happen. In any case, pretend lower layer went down. + */ +static void upap_protrej(int unit) +{ + upap_state *u = &upap[unit]; + + if (u->us_clientstate == UPAPCS_AUTHREQ) { + UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n")); + auth_withpeer_fail(unit, PPP_PAP); + } + if (u->us_serverstate == UPAPSS_LISTEN) { + UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n")); + auth_peer_fail(unit, PPP_PAP); + } + upap_lowerdown(unit); +} + + +/* + * upap_input - Input UPAP packet. + */ +static void upap_input(int unit, u_char *inpacket, int l) +{ + upap_state *u = &upap[unit]; + u_char *inp; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + inp = inpacket; + if (l < UPAP_HEADERLEN) { + UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < UPAP_HEADERLEN) { + UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n")); + return; + } + if (len > l) { + UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n")); + return; + } + len -= UPAP_HEADERLEN; + + /* + * Action depends on code. + */ + switch (code) { + case UPAP_AUTHREQ: + upap_rauthreq(u, inp, id, len); + break; + + case UPAP_AUTHACK: + upap_rauthack(u, inp, id, len); + break; + + case UPAP_AUTHNAK: + upap_rauthnak(u, inp, id, len); + break; + + default: /* XXX Need code reject */ + break; + } +} + + +/* + * upap_rauth - Receive Authenticate. + */ +static void upap_rauthreq( + upap_state *u, + u_char *inp, + int id, + int len +) +{ + u_char ruserlen, rpasswdlen; + char *ruser, *rpasswd; + int retcode; + char *msg; + int msglen; + + UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id)); + + if (u->us_serverstate < UPAPSS_LISTEN) + return; + + /* + * If we receive a duplicate authenticate-request, we are + * supposed to return the same status as for the first request. + */ + if (u->us_serverstate == UPAPSS_OPEN) { + upap_sresp(u, UPAP_AUTHACK, id, "", 0); /* return auth-ack */ + return; + } + if (u->us_serverstate == UPAPSS_BADAUTH) { + upap_sresp(u, UPAP_AUTHNAK, id, "", 0); /* return auth-nak */ + return; + } + + /* + * Parse user/passwd. + */ + if (len < sizeof (u_char)) { + UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); + return; + } + GETCHAR(ruserlen, inp); + len -= sizeof (u_char) + ruserlen + sizeof (u_char); + if (len < 0) { + UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); + return; + } + ruser = (char *) inp; + INCPTR(ruserlen, inp); + GETCHAR(rpasswdlen, inp); + if (len < rpasswdlen) { + UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); + return; + } + rpasswd = (char *) inp; + + /* + * Check the username and password given. + */ + retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd, + rpasswdlen, &msg, &msglen); + BZERO(rpasswd, rpasswdlen); + + upap_sresp(u, retcode, id, msg, msglen); + + if (retcode == UPAP_AUTHACK) { + u->us_serverstate = UPAPSS_OPEN; + auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen); + } else { + u->us_serverstate = UPAPSS_BADAUTH; + auth_peer_fail(u->us_unit, PPP_PAP); + } + + if (u->us_reqtimeout > 0) + UNTIMEOUT(upap_reqtimeout, u); +} + + +/* + * upap_rauthack - Receive Authenticate-Ack. + */ +static void upap_rauthack( + upap_state *u, + u_char *inp, + int id, + int len +) +{ + u_char msglen; + char *msg; + + UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate)); + + if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */ + return; + + /* + * Parse message. + */ + if (len < sizeof (u_char)) { + UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); + return; + } + GETCHAR(msglen, inp); + len -= sizeof (u_char); + if (len < msglen) { + UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); + return; + } + msg = (char *) inp; + PRINTMSG(msg, msglen); + + u->us_clientstate = UPAPCS_OPEN; + + auth_withpeer_success(u->us_unit, PPP_PAP); +} + + +/* + * upap_rauthnak - Receive Authenticate-Nakk. + */ +static void upap_rauthnak( + upap_state *u, + u_char *inp, + int id, + int len +) +{ + u_char msglen; + char *msg; + + UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate)); + + if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */ + return; + + /* + * Parse message. + */ + if (len < sizeof (u_char)) { + UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); + return; + } + GETCHAR(msglen, inp); + len -= sizeof (u_char); + if (len < msglen) { + UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); + return; + } + msg = (char *) inp; + PRINTMSG(msg, msglen); + + u->us_clientstate = UPAPCS_BADAUTH; + + UPAPDEBUG((LOG_ERR, "PAP authentication failed\n")); + auth_withpeer_fail(u->us_unit, PPP_PAP); +} + + +/* + * upap_sauthreq - Send an Authenticate-Request. + */ +static void upap_sauthreq(upap_state *u) +{ + u_char *outp; + int outlen; + + outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) + + u->us_userlen + u->us_passwdlen; + outp = outpacket_buf[u->us_unit]; + + MAKEHEADER(outp, PPP_PAP); + + PUTCHAR(UPAP_AUTHREQ, outp); + PUTCHAR(++u->us_id, outp); + PUTSHORT(outlen, outp); + PUTCHAR(u->us_userlen, outp); + BCOPY(u->us_user, outp, u->us_userlen); + INCPTR(u->us_userlen, outp); + PUTCHAR(u->us_passwdlen, outp); + BCOPY(u->us_passwd, outp, u->us_passwdlen); + + pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); + + UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id)); + + TIMEOUT(upap_timeout, u, u->us_timeouttime); + ++u->us_transmits; + u->us_clientstate = UPAPCS_AUTHREQ; +} + + +/* + * upap_sresp - Send a response (ack or nak). + */ +static void upap_sresp( + upap_state *u, + u_char code, + u_char id, + char *msg, + int msglen +) +{ + u_char *outp; + int outlen; + + outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen; + outp = outpacket_buf[u->us_unit]; + MAKEHEADER(outp, PPP_PAP); + + PUTCHAR(code, outp); + PUTCHAR(id, outp); + PUTSHORT(outlen, outp); + PUTCHAR(msglen, outp); + BCOPY(msg, outp, msglen); + pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); + + UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", + code, id, u->us_clientstate)); +} + +#if 0 +/* + * upap_printpkt - print the contents of a PAP packet. + */ +static int upap_printpkt( + u_char *p, + int plen, + void (*printer) (void *, char *, ...), + void *arg +) +{ + (void)p; + (void)plen; + (void)printer; + (void)arg; + return 0; +} +#endif + +#endif /* PAP_SUPPORT */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/pap.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/pap.h new file mode 100644 index 0000000..59eb2c7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/pap.h @@ -0,0 +1,129 @@ +/***************************************************************************** +* pap.h - PPP Password Authentication Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * upap.h - User/Password Authentication Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#ifndef PAP_H +#define PAP_H + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ +/* + * Packet header = Code, id, length. + */ +#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) + + +/* + * UPAP codes. + */ +#define UPAP_AUTHREQ 1 /* Authenticate-Request */ +#define UPAP_AUTHACK 2 /* Authenticate-Ack */ +#define UPAP_AUTHNAK 3 /* Authenticate-Nak */ + +/* + * Client states. + */ +#define UPAPCS_INITIAL 0 /* Connection down */ +#define UPAPCS_CLOSED 1 /* Connection up, haven't requested auth */ +#define UPAPCS_PENDING 2 /* Connection down, have requested auth */ +#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */ +#define UPAPCS_OPEN 4 /* We've received an Ack */ +#define UPAPCS_BADAUTH 5 /* We've received a Nak */ + +/* + * Server states. + */ +#define UPAPSS_INITIAL 0 /* Connection down */ +#define UPAPSS_CLOSED 1 /* Connection up, haven't requested auth */ +#define UPAPSS_PENDING 2 /* Connection down, have requested auth */ +#define UPAPSS_LISTEN 3 /* Listening for an Authenticate */ +#define UPAPSS_OPEN 4 /* We've sent an Ack */ +#define UPAPSS_BADAUTH 5 /* We've sent a Nak */ + + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * Each interface is described by upap structure. + */ +typedef struct upap_state { + int us_unit; /* Interface unit number */ + const char *us_user; /* User */ + int us_userlen; /* User length */ + const char *us_passwd; /* Password */ + int us_passwdlen; /* Password length */ + int us_clientstate; /* Client state */ + int us_serverstate; /* Server state */ + u_char us_id; /* Current id */ + int us_timeouttime; /* Timeout (seconds) for auth-req retrans. */ + int us_transmits; /* Number of auth-reqs sent */ + int us_maxtransmits; /* Maximum number of auth-reqs to send */ + int us_reqtimeout; /* Time to wait for auth-req from peer */ +} upap_state; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +extern upap_state upap[]; + +void upap_setloginpasswd(int unit, const char *luser, const char *lpassword); +void upap_authwithpeer (int, char *, char *); +void upap_authpeer (int); + +extern struct protent pap_protent; + +#endif /* PAP_H */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ppp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ppp.c new file mode 100644 index 0000000..afd4116 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ppp.c @@ -0,0 +1,1631 @@ +/***************************************************************************** +* ppp.c - Network Point to Point Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ + +/* + * ppp_defs.h - PPP definitions. + * + * if_pppvar.h - private structures and declarations for PPP. + * + * Copyright (c) 1994 The Australian National University. + * All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, provided that the above copyright + * notice appears in all copies. This software is provided without any + * warranty, express or implied. The Australian National University + * makes no representations about the suitability of this software for + * any purpose. + * + * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY + * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES + * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, + * OR MODIFICATIONS. + */ + +/* + * if_ppp.h - Point-to-Point Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "randm.h" +#include "fsm.h" +#if PAP_SUPPORT > 0 +#include "pap.h" +#endif +#if CHAP_SUPPORT > 0 +#include "chap.h" +#endif +#include "ipcp.h" +#include "lcp.h" +#include "magic.h" +#include "auth.h" +#if VJ_SUPPORT > 0 +#include "vj.h" +#endif + +#include "pppdebug.h" + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + +/* + * The basic PPP frame. + */ +#define PPP_ADDRESS(p) (((u_char *)(p))[0]) +#define PPP_CONTROL(p) (((u_char *)(p))[1]) +#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3]) + +/* PPP packet parser states. Current state indicates operation yet to be + * completed. */ +typedef enum { + PDIDLE = 0, /* Idle state - waiting. */ + PDSTART, /* Process start flag. */ + PDADDRESS, /* Process address field. */ + PDCONTROL, /* Process control field. */ + PDPROTOCOL1, /* Process protocol field 1. */ + PDPROTOCOL2, /* Process protocol field 2. */ + PDDATA /* Process data byte. */ +} PPPDevStates; + +#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07]) + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ +/* + * PPP interface control block. + */ +typedef struct PPPControl_s { + char openFlag; /* True when in use. */ + char oldFrame; /* Old framing character for fd. */ + sio_fd_t fd; /* File device ID of port. */ + int kill_link; /* Shut the link down. */ + int sig_hup; /* Carrier lost. */ + int if_up; /* True when the interface is up. */ + int errCode; /* Code indicating why interface is down. */ + struct pbuf *inHead, *inTail; /* The input packet. */ + PPPDevStates inState; /* The input process state. */ + char inEscaped; /* Escape next character. */ + u16_t inProtocol; /* The input protocol code. */ + u16_t inFCS; /* Input Frame Check Sequence value. */ + int mtu; /* Peer's mru */ + int pcomp; /* Does peer accept protocol compression? */ + int accomp; /* Does peer accept addr/ctl compression? */ + u_long lastXMit; /* Time of last transmission. */ + ext_accm inACCM; /* Async-Ctl-Char-Map for input. */ + ext_accm outACCM; /* Async-Ctl-Char-Map for output. */ +#if VJ_SUPPORT > 0 + int vjEnabled; /* Flag indicating VJ compression enabled. */ + struct vjcompress vjComp; /* Van Jabobsen compression header. */ +#endif + + struct netif netif; + + struct ppp_addrs addrs; + + void (*linkStatusCB)(void *ctx, int errCode, void *arg); + void *linkStatusCtx; + +} PPPControl; + + +/* + * Ioctl definitions. + */ + +struct npioctl { + int protocol; /* PPP procotol, e.g. PPP_IP */ + enum NPmode mode; +}; + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +static void pppMain(void *pd); +static void pppDrop(PPPControl *pc); +static void pppInProc(int pd, u_char *s, int l); + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +u_long subnetMask; + +static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */ + +/* + * PPP Data Link Layer "protocol" table. + * One entry per supported protocol. + * The last entry must be NULL. + */ +struct protent *ppp_protocols[] = { + &lcp_protent, +#if PAP_SUPPORT > 0 + &pap_protent, +#endif +#if CHAP_SUPPORT > 0 + &chap_protent, +#endif +#if CBCP_SUPPORT > 0 + &cbcp_protent, +#endif + &ipcp_protent, +#if CCP_SUPPORT > 0 + &ccp_protent, +#endif + NULL +}; + + +/* + * Buffers for outgoing packets. This must be accessed only from the appropriate + * PPP task so that it doesn't need to be protected to avoid collisions. + */ +u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ + +/* + * FCS lookup table as calculated by genfcstab. + */ +static const u_short fcstab[256] = { + 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, + 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, + 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, + 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, + 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, + 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, + 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, + 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, + 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, + 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, + 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, + 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, + 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, + 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, + 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, + 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, + 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, + 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, + 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, + 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, + 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, + 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, + 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, + 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, + 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, + 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, + 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, + 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, + 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, + 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, + 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, + 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 +}; + +/* PPP's Asynchronous-Control-Character-Map. The mask array is used + * to select the specific bit for a character. */ +static u_char pppACCMMask[] = { + 0x01, + 0x02, + 0x04, + 0x08, + 0x10, + 0x20, + 0x40, + 0x80 +}; + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* Initialize the PPP subsystem. */ + +struct ppp_settings ppp_settings; + +void pppInit(void) +{ + struct protent *protp; + int i, j; + + memset(&ppp_settings, 0, sizeof(ppp_settings)); + ppp_settings.usepeerdns = 1; + pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL); + + magicInit(); + + for (i = 0; i < NUM_PPP; i++) { + pppControl[i].openFlag = 0; + + subnetMask = htonl(0xffffff00); + + /* + * Initialize to the standard option set. + */ + for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j) + (*protp->init)(i); + } + +#if LINK_STATS + /* Clear the statistics. */ + memset(&lwip_stats.link, 0, sizeof(lwip_stats.link)); +#endif +} + +void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd) +{ + switch(authType) { + case PPPAUTHTYPE_NONE: + default: +#ifdef LWIP_PPP_STRICT_PAP_REJECT + ppp_settings.refuse_pap = 1; +#else + /* some providers request pap and accept an empty login/pw */ + ppp_settings.refuse_pap = 0; +#endif + ppp_settings.refuse_chap = 1; + break; + case PPPAUTHTYPE_ANY: +/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. + * RFC 1994 says: + * + * In practice, within or associated with each PPP server, there is a + * database which associates "user" names with authentication + * information ("secrets"). It is not anticipated that a particular + * named user would be authenticated by multiple methods. This would + * make the user vulnerable to attacks which negotiate the least secure + * method from among a set (such as PAP rather than CHAP). If the same + * secret was used, PAP would reveal the secret to be used later with + * CHAP. + * + * Instead, for each user name there should be an indication of exactly + * one method used to authenticate that user name. If a user needs to + * make use of different authentication methods under different + * circumstances, then distinct user names SHOULD be employed, each of + * which identifies exactly one authentication method. + * + */ + ppp_settings.refuse_pap = 0; + ppp_settings.refuse_chap = 0; + break; + case PPPAUTHTYPE_PAP: + ppp_settings.refuse_pap = 0; + ppp_settings.refuse_chap = 1; + break; + case PPPAUTHTYPE_CHAP: + ppp_settings.refuse_pap = 1; + ppp_settings.refuse_chap = 0; + break; + } + + if(user) { + strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1); + ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0'; + } else + ppp_settings.user[0] = '\0'; + + if(passwd) { + strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1); + ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0'; + } else + ppp_settings.passwd[0] = '\0'; +} + +/* Open a new PPP connection using the given I/O device. + * This initializes the PPP control block but does not + * attempt to negotiate the LCP session. If this port + * connects to a modem, the modem connection must be + * established before calling this. + * Return a new PPP connection descriptor on success or + * an error code (negative) on failure. */ +int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx) +{ + PPPControl *pc; + int pd; + + /* Find a free PPP session descriptor. Critical region? */ + for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++); + if (pd >= NUM_PPP) + pd = PPPERR_OPEN; + else + pppControl[pd].openFlag = !0; + + /* Launch a deamon thread. */ + if (pd >= 0) { + + pppControl[pd].openFlag = 1; + + lcp_init(pd); + pc = &pppControl[pd]; + pc->fd = fd; + pc->kill_link = 0; + pc->sig_hup = 0; + pc->if_up = 0; + pc->errCode = 0; + pc->inState = PDIDLE; + pc->inHead = NULL; + pc->inTail = NULL; + pc->inEscaped = 0; + pc->lastXMit = 0; + +#if VJ_SUPPORT > 0 + pc->vjEnabled = 0; + vj_compress_init(&pc->vjComp); +#endif + + /* + * Default the in and out accm so that escape and flag characters + * are always escaped. + */ + memset(pc->inACCM, 0, sizeof(ext_accm)); + pc->inACCM[15] = 0x60; + memset(pc->outACCM, 0, sizeof(ext_accm)); + pc->outACCM[15] = 0x60; + + pc->linkStatusCB = linkStatusCB; + pc->linkStatusCtx = linkStatusCtx; + + sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO); + if(!linkStatusCB) { + while(pd >= 0 && !pc->if_up) { + sys_msleep(500); + if (lcp_phase[pd] == PHASE_DEAD) { + pppClose(pd); + if (pc->errCode) + pd = pc->errCode; + else + pd = PPPERR_CONNECT; + } + } + } + } + return pd; +} + +/* Close a PPP connection and release the descriptor. + * Any outstanding packets in the queues are dropped. + * Return 0 on success, an error code on failure. */ +int pppClose(int pd) +{ + PPPControl *pc = &pppControl[pd]; + int st = 0; + + /* Disconnect */ + pc->kill_link = !0; + pppMainWakeup(pd); + + if(!pc->linkStatusCB) { + while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) { + sys_msleep(500); + break; + } + } + return st; +} + +/* This function is called when carrier is lost on the PPP channel. */ +void pppSigHUP(int pd) +{ + PPPControl *pc = &pppControl[pd]; + + pc->sig_hup = 1; + pppMainWakeup(pd); +} + +static void nPut(PPPControl *pc, struct pbuf *nb) +{ + struct pbuf *b; + int c; + + for(b = nb; b != NULL; b = b->next) { + if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) { + PPPDEBUG((LOG_WARNING, + "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c)); +#if LINK_STATS + lwip_stats.link.err++; +#endif /* LINK_STATS */ + pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */ + break; + } + } + pbuf_free(nb); + +#if LINK_STATS + lwip_stats.link.xmit++; +#endif /* LINK_STATS */ +} + +/* + * pppAppend - append given character to end of given pbuf. If outACCM + * is not NULL and the character needs to be escaped, do so. + * If pbuf is full, append another. + * Return the current pbuf. + */ +static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM) +{ + struct pbuf *tb = nb; + + /* Make sure there is room for the character and an escape code. + * Sure we don't quite fill the buffer if the character doesn't + * get escaped but is one character worth complicating this? */ + /* Note: We assume no packet header. */ + if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) { + tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (tb) { + nb->next = tb; + } +#if LINK_STATS + else { + lwip_stats.link.memerr++; + } +#endif /* LINK_STATS */ + nb = tb; + } + if (nb) { + if (outACCM && ESCAPE_P(*outACCM, c)) { + *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE; + *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS; + } + else + *((u_char*)nb->payload + nb->len++) = c; + } + + return tb; +} + +/* Send a packet on the given connection. */ +static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr) +{ + int pd = (int)netif->state; + u_short protocol = PPP_IP; + PPPControl *pc = &pppControl[pd]; + u_int fcsOut = PPP_INITFCS; + struct pbuf *headMB = NULL, *tailMB = NULL, *p; + u_char c; + + (void)ipaddr; + + /* Validate parameters. */ + /* We let any protocol value go through - it can't hurt us + * and the peer will just drop it if it's not accepting it. */ + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) { + PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n", + pd, protocol, pb)); +#if LINK_STATS + lwip_stats.link.opterr++; + lwip_stats.link.drop++; +#endif + return ERR_ARG; + } + + /* Check that the link is up. */ + if (lcp_phase[pd] == PHASE_DEAD) { + PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd)); +#if LINK_STATS + lwip_stats.link.rterr++; + lwip_stats.link.drop++; +#endif + return ERR_RTE; + } + + /* Grab an output buffer. */ + headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (headMB == NULL) { + PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd)); +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif /* LINK_STATS */ + return ERR_MEM; + } + +#if VJ_SUPPORT > 0 + /* + * Attempt Van Jacobson header compression if VJ is configured and + * this is an IP packet. + */ + if (protocol == PPP_IP && pc->vjEnabled) { + switch (vj_compress_tcp(&pc->vjComp, pb)) { + case TYPE_IP: + /* No change... + protocol = PPP_IP_PROTOCOL; + */ + break; + case TYPE_COMPRESSED_TCP: + protocol = PPP_VJC_COMP; + break; + case TYPE_UNCOMPRESSED_TCP: + protocol = PPP_VJC_UNCOMP; + break; + default: + PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd)); +#if LINK_STATS + lwip_stats.link.proterr++; + lwip_stats.link.drop++; +#endif + pbuf_free(headMB); + return ERR_VAL; + } + } +#endif + + tailMB = headMB; + + /* Build the PPP header. */ + if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + pc->lastXMit = sys_jiffies(); + if (!pc->accomp) { + fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS); + tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM); + fcsOut = PPP_FCS(fcsOut, PPP_UI); + tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM); + } + if (!pc->pcomp || protocol > 0xFF) { + c = (protocol >> 8) & 0xFF; + fcsOut = PPP_FCS(fcsOut, c); + tailMB = pppAppend(c, tailMB, &pc->outACCM); + } + c = protocol & 0xFF; + fcsOut = PPP_FCS(fcsOut, c); + tailMB = pppAppend(c, tailMB, &pc->outACCM); + + /* Load packet. */ + for(p = pb; p; p = p->next) { + int n; + u_char *sPtr; + + sPtr = (u_char*)p->payload; + n = p->len; + while (n-- > 0) { + c = *sPtr++; + + /* Update FCS before checking for special characters. */ + fcsOut = PPP_FCS(fcsOut, c); + + /* Copy to output buffer escaping special characters. */ + tailMB = pppAppend(c, tailMB, &pc->outACCM); + } + } + + /* Add FCS and trailing flag. */ + c = ~fcsOut & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + c = (~fcsOut >> 8) & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + + /* If we failed to complete the packet, throw it away. */ + if (!tailMB) { + PPPDEBUG((LOG_WARNING, + "pppifOutput[%d]: Alloc err - dropping proto=%d\n", + pd, protocol)); + pbuf_free(headMB); +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + return ERR_MEM; + } + + /* Send it. */ + PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol)); + + nPut(pc, headMB); + + return ERR_OK; +} + +/* Get and set parameters for the given connection. + * Return 0 on success, an error code on failure. */ +int pppIOCtl(int pd, int cmd, void *arg) +{ + PPPControl *pc = &pppControl[pd]; + int st = 0; + + if (pd < 0 || pd >= NUM_PPP) + st = PPPERR_PARAM; + else { + switch(cmd) { + case PPPCTLG_UPSTATUS: /* Get the PPP up status. */ + if (arg) + *(int *)arg = (int)(pc->if_up); + else + st = PPPERR_PARAM; + break; + case PPPCTLS_ERRCODE: /* Set the PPP error code. */ + if (arg) + pc->errCode = *(int *)arg; + else + st = PPPERR_PARAM; + break; + case PPPCTLG_ERRCODE: /* Get the PPP error code. */ + if (arg) + *(int *)arg = (int)(pc->errCode); + else + st = PPPERR_PARAM; + break; + case PPPCTLG_FD: + if (arg) + *(sio_fd_t *)arg = pc->fd; + else + st = PPPERR_PARAM; + break; + default: + st = PPPERR_PARAM; + break; + } + } + + return st; +} + +/* + * Return the Maximum Transmission Unit for the given PPP connection. + */ +u_int pppMTU(int pd) +{ + PPPControl *pc = &pppControl[pd]; + u_int st; + + /* Validate parameters. */ + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) + st = 0; + else + st = pc->mtu; + + return st; +} + +/* + * Write n characters to a ppp link. + * RETURN: >= 0 Number of characters written + * -1 Failed to write to device + */ +int pppWrite(int pd, const u_char *s, int n) +{ + PPPControl *pc = &pppControl[pd]; + u_char c; + u_int fcsOut = PPP_INITFCS; + struct pbuf *headMB = NULL, *tailMB; + headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (headMB == NULL) { +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.proterr++; +#endif /* LINK_STATS */ + return PPPERR_ALLOC; + } + + tailMB = headMB; + + /* If the link has been idle, we'll send a fresh flag character to + * flush any noise. */ + if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + pc->lastXMit = sys_jiffies(); + + /* Load output buffer. */ + while (n-- > 0) { + c = *s++; + + /* Update FCS before checking for special characters. */ + fcsOut = PPP_FCS(fcsOut, c); + + /* Copy to output buffer escaping special characters. */ + tailMB = pppAppend(c, tailMB, &pc->outACCM); + } + + /* Add FCS and trailing flag. */ + c = ~fcsOut & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + c = (~fcsOut >> 8) & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + + /* If we failed to complete the packet, throw it away. + * Otherwise send it. */ + if (!tailMB) { + PPPDEBUG((LOG_WARNING, + "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len)); +/* "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ + pbuf_free(headMB); +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.proterr++; +#endif /* LINK_STATS */ + return PPPERR_ALLOC; + } + + PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len)); +/* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ + nPut(pc, headMB); + + return PPPERR_NONE; +} + +/* + * ppp_send_config - configure the transmit characteristics of + * the ppp interface. + */ +void ppp_send_config( + int unit, + int mtu, + u32_t asyncmap, + int pcomp, + int accomp +) +{ + PPPControl *pc = &pppControl[unit]; + int i; + + pc->mtu = mtu; + pc->pcomp = pcomp; + pc->accomp = accomp; + + /* Load the ACCM bits for the 32 control codes. */ + for (i = 0; i < 32/8; i++) + pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF); + PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n", + unit, + pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3])); +} + + +/* + * ppp_set_xaccm - set the extended transmit ACCM for the interface. + */ +void ppp_set_xaccm(int unit, ext_accm *accm) +{ + memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm)); + PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n", + unit, + pppControl[unit].outACCM[0], + pppControl[unit].outACCM[1], + pppControl[unit].outACCM[2], + pppControl[unit].outACCM[3])); +} + + +/* + * ppp_recv_config - configure the receive-side characteristics of + * the ppp interface. + */ +void ppp_recv_config( + int unit, + int mru, + u32_t asyncmap, + int pcomp, + int accomp +) +{ + PPPControl *pc = &pppControl[unit]; + int i; + + (void)accomp; + (void)pcomp; + (void)mru; + + /* Load the ACCM bits for the 32 control codes. */ + for (i = 0; i < 32 / 8; i++) + pc->inACCM[i] = (u_char)(asyncmap >> (i * 8)); + PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n", + unit, + pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3])); +} + +#if 0 +/* + * ccp_test - ask kernel whether a given compression method + * is acceptable for use. Returns 1 if the method and parameters + * are OK, 0 if the method is known but the parameters are not OK + * (e.g. code size should be reduced), or -1 if the method is unknown. + */ +int ccp_test( + int unit, + int opt_len, + int for_transmit, + u_char *opt_ptr +) +{ + return 0; /* XXX Currently no compression. */ +} + +/* + * ccp_flags_set - inform kernel about the current state of CCP. + */ +void ccp_flags_set(int unit, int isopen, int isup) +{ + /* XXX */ +} + +/* + * ccp_fatal_error - returns 1 if decompression was disabled as a + * result of an error detected after decompression of a packet, + * 0 otherwise. This is necessary because of patent nonsense. + */ +int ccp_fatal_error(int unit) +{ + /* XXX */ + return 0; +} +#endif + +/* + * get_idle_time - return how long the link has been idle. + */ +int get_idle_time(int u, struct ppp_idle *ip) +{ + /* XXX */ + (void)u; + (void)ip; + + return 0; +} + + +/* + * Return user specified netmask, modified by any mask we might determine + * for address `addr' (in network byte order). + * Here we scan through the system's list of interfaces, looking for + * any non-point-to-point interfaces which might appear to be on the same + * network as `addr'. If we find any, we OR in their netmask to the + * user-specified netmask. + */ +u32_t GetMask(u32_t addr) +{ + u32_t mask, nmask; + + htonl(addr); + if (IN_CLASSA(addr)) /* determine network mask for address class */ + nmask = IN_CLASSA_NET; + else if (IN_CLASSB(addr)) + nmask = IN_CLASSB_NET; + else + nmask = IN_CLASSC_NET; + /* class D nets are disallowed by bad_ip_adrs */ + mask = subnetMask | htonl(nmask); + + /* XXX + * Scan through the system's network interfaces. + * Get each netmask and OR them into our mask. + */ + + return mask; +} + +/* + * sifvjcomp - config tcp header compression + */ +int sifvjcomp( + int pd, + int vjcomp, + int cidcomp, + int maxcid +) +{ +#if VJ_SUPPORT > 0 + PPPControl *pc = &pppControl[pd]; + + pc->vjEnabled = vjcomp; + pc->vjComp.compressSlot = cidcomp; + pc->vjComp.maxSlotIndex = maxcid; + PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n", + vjcomp, cidcomp, maxcid)); +#endif + + return 0; +} + +/* + * pppifNetifInit - netif init callback + */ +static err_t pppifNetifInit(struct netif *netif) +{ + netif->name[0] = 'p'; + netif->name[1] = 'p'; + netif->output = pppifOutput; + netif->mtu = pppMTU((int)netif->state); + return ERR_OK; +} + + +/* + * sifup - Config the interface up and enable IP packets to pass. + */ +int sifup(int pd) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + netif_remove(&pc->netif); + if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) { + + netif_set_up(&pc->netif); + pc->if_up = 1; + pc->errCode = PPPERR_NONE; + + PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); + if(pc->linkStatusCB) + pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs); + } else { + st = 0; + PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd)); + } + } + + return st; +} + +/* + * sifnpmode - Set the mode for handling packets for a given NP. + */ +int sifnpmode(int u, int proto, enum NPmode mode) +{ + (void)u; + (void)proto; + (void)mode; + return 0; +} + +/* + * sifdown - Config the interface down and disable IP. + */ +int sifdown(int pd) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd)); + } else { + pc->if_up = 0; + netif_remove(&pc->netif); + PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); + if(pc->linkStatusCB) + pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL); + } + return st; +} + +/* + * sifaddr - Config the interface IP addresses and netmask. + */ +int sifaddr( + int pd, /* Interface unit ??? */ + u32_t o, /* Our IP address ??? */ + u32_t h, /* His IP address ??? */ + u32_t m, /* IP subnet mask ??? */ + u32_t ns1, /* Primary DNS */ + u32_t ns2 /* Secondary DNS */ +) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o)); + memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h)); + memcpy(&pc->addrs.netmask, &m, sizeof(m)); + memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1)); + memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2)); + } + return st; +} + +/* + * cifaddr - Clear the interface IP addresses, and delete routes + * through the interface if possible. + */ +int cifaddr( + int pd, /* Interface unit ??? */ + u32_t o, /* Our IP address ??? */ + u32_t h /* IP broadcast address ??? */ +) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + (void)o; + (void)h; + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0); + IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0); + IP4_ADDR(&pc->addrs.netmask, 255,255,255,0); + IP4_ADDR(&pc->addrs.dns1, 0,0,0,0); + IP4_ADDR(&pc->addrs.dns2, 0,0,0,0); + } + return st; +} + +/* + * sifdefaultroute - assign a default route through the address given. + */ +int sifdefaultroute(int pd, u32_t l, u32_t g) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + (void)l; + (void)g; + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + netif_set_default(&pc->netif); + } + + /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */ + + return st; +} + +/* + * cifdefaultroute - delete a default route through the address given. + */ +int cifdefaultroute(int pd, u32_t l, u32_t g) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + (void)l; + (void)g; + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + netif_set_default(NULL); + } + + return st; +} + +void +pppMainWakeup(int pd) +{ + PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd)); + sio_read_abort(pppControl[pd].fd); +} + +/* these callbacks are necessary because lcp_* functions + must be called in the same context as pppInput(), + namely the tcpip_thread(), essentially because + they manipulate timeouts which are thread-private +*/ + +static void +pppStartCB(void *arg) +{ + int pd = (int)arg; + + PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd)); + lcp_lowerup(pd); + lcp_open(pd); /* Start protocol */ +} + +static void +pppStopCB(void *arg) +{ + int pd = (int)arg; + + PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd)); + lcp_close(pd, "User request"); +} + +static void +pppHupCB(void *arg) +{ + int pd = (int)arg; + + PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd)); + lcp_lowerdown(pd); + link_terminated(pd); +} +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* The main PPP process function. This implements the state machine according + * to section 4 of RFC 1661: The Point-To-Point Protocol. */ +static void pppMain(void *arg) +{ + int pd = (int)arg; + struct pbuf *p; + PPPControl* pc; + + pc = &pppControl[pd]; + + p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM); + if(!p) { + LWIP_ASSERT("p != NULL", p); + pc->errCode = PPPERR_ALLOC; + goto out; + } + + /* + * Start the connection and handle incoming events (packet or timeout). + */ + PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd)); + tcpip_callback(pppStartCB, arg); + while (lcp_phase[pd] != PHASE_DEAD) { + if (pc->kill_link) { + PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd)); + pc->errCode = PPPERR_USER; + /* This will leave us at PHASE_DEAD. */ + tcpip_callback(pppStopCB, arg); + pc->kill_link = 0; + } + else if (pc->sig_hup) { + PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd)); + pc->sig_hup = 0; + tcpip_callback(pppHupCB, arg); + } else { + int c = sio_read(pc->fd, p->payload, p->len); + if(c > 0) { + pppInProc(pd, p->payload, c); + } else { + PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c)); + sys_msleep(1); /* give other tasks a chance to run */ + } + } + } + PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd)); + pbuf_free(p); + +out: + PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); + if(pc->linkStatusCB) + pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL); + + pc->openFlag = 0; +} + +static struct pbuf *pppSingleBuf(struct pbuf *p) +{ + struct pbuf *q, *b; + u_char *pl; + + if(p->tot_len == p->len) + return p; + + q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if(!q) { + PPPDEBUG((LOG_ERR, + "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len)); + return p; /* live dangerously */ + } + + for(b = p, pl = q->payload; b != NULL; b = b->next) { + memcpy(pl, b->payload, b->len); + pl += b->len; + } + + pbuf_free(p); + + return q; +} + +struct pppInputHeader { + int unit; + u16_t proto; +}; + +/* + * Pass the processed input packet to the appropriate handler. + * This function and all handlers run in the context of the tcpip_thread + */ +static void pppInput(void *arg) +{ + struct pbuf *nb = (struct pbuf *)arg; + u16_t protocol; + int pd; + + pd = ((struct pppInputHeader *)nb->payload)->unit; + protocol = ((struct pppInputHeader *)nb->payload)->proto; + + pbuf_header(nb, -(int)sizeof(struct pppInputHeader)); + +#if LINK_STATS + lwip_stats.link.recv++; +#endif /* LINK_STATS */ + + /* + * Toss all non-LCP packets unless LCP is OPEN. + * Until we get past the authentication phase, toss all packets + * except LCP, LQR and authentication packets. + */ + if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) { + if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) || + (lcp_phase[pd] != PHASE_AUTHENTICATE)) { + PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd])); + goto drop; + } + } + + switch(protocol) { + case PPP_VJC_COMP: /* VJ compressed TCP */ +#if VJ_SUPPORT > 0 + PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len)); + /* + * Clip off the VJ header and prepend the rebuilt TCP/IP header and + * pass the result to IP. + */ + if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) { + if (pppControl[pd].netif.input != NULL) { + pppControl[pd].netif.input(nb, &pppControl[pd].netif); + } + return; + } + /* Something's wrong so drop it. */ + PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd)); +#else + /* No handler for this protocol so drop the packet. */ + PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload)); +#endif /* VJ_SUPPORT > 0 */ + break; + case PPP_VJC_UNCOMP: /* VJ uncompressed TCP */ +#if VJ_SUPPORT > 0 + PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len)); + /* + * Process the TCP/IP header for VJ header compression and then pass + * the packet to IP. + */ + if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) { + if (pppControl[pd].netif.input != NULL) { + pppControl[pd].netif.input(nb, &pppControl[pd].netif); + } + return; + } + /* Something's wrong so drop it. */ + PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd)); +#else + /* No handler for this protocol so drop the packet. */ + PPPDEBUG((LOG_INFO, + "pppInput[%d]: drop VJ UnComp in %d:.*H\n", + pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload)); +#endif /* VJ_SUPPORT > 0 */ + break; + case PPP_IP: /* Internet Protocol */ + PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len)); + if (pppControl[pd].netif.input != NULL) { + pppControl[pd].netif.input(nb, &pppControl[pd].netif); + } + return; + default: + { + struct protent *protp; + int i; + + /* + * Upcall the proper protocol input routine. + */ + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { + if (protp->protocol == protocol && protp->enabled_flag) { + PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len)); + nb = pppSingleBuf(nb); + (*protp->input)(pd, nb->payload, nb->len); + goto out; + } + } + + /* No handler for this protocol so reject the packet. */ + PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len)); + pbuf_header(nb, sizeof(protocol)); +#if BYTE_ORDER == LITTLE_ENDIAN + protocol = htons(protocol); + memcpy(nb->payload, &protocol, sizeof(protocol)); +#endif + lcp_sprotrej(pd, nb->payload, nb->len); + } + break; + } + +drop: +#if LINK_STATS + lwip_stats.link.drop++; +#endif + +out: + pbuf_free(nb); + return; +} + + +/* + * Drop the input packet. + */ +static void pppDrop(PPPControl *pc) +{ + if (pc->inHead != NULL) { +#if 0 + PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload)); +#endif + PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len)); + if (pc->inTail && (pc->inTail != pc->inHead)) + pbuf_free(pc->inTail); + pbuf_free(pc->inHead); + pc->inHead = NULL; + pc->inTail = NULL; + } +#if VJ_SUPPORT > 0 + vj_uncompress_err(&pc->vjComp); +#endif + +#if LINK_STATS + lwip_stats.link.drop++; +#endif /* LINK_STATS */ +} + + +/* + * Process a received octet string. + */ +static void pppInProc(int pd, u_char *s, int l) +{ + PPPControl *pc = &pppControl[pd]; + struct pbuf *nextNBuf; + u_char curChar; + + PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l)); + while (l-- > 0) { + curChar = *s++; + + /* Handle special characters. */ + if (ESCAPE_P(pc->inACCM, curChar)) { + /* Check for escape sequences. */ + /* XXX Note that this does not handle an escaped 0x5d character which + * would appear as an escape character. Since this is an ASCII ']' + * and there is no reason that I know of to escape it, I won't complicate + * the code to handle this case. GLL */ + if (curChar == PPP_ESCAPE) + pc->inEscaped = 1; + /* Check for the flag character. */ + else if (curChar == PPP_FLAG) { + /* If this is just an extra flag character, ignore it. */ + if (pc->inState <= PDADDRESS) + ; + /* If we haven't received the packet header, drop what has come in. */ + else if (pc->inState < PDDATA) { + PPPDEBUG((LOG_WARNING, + "pppInProc[%d]: Dropping incomplete packet %d\n", + pd, pc->inState)); +#if LINK_STATS + lwip_stats.link.lenerr++; +#endif + pppDrop(pc); + } + /* If the fcs is invalid, drop the packet. */ + else if (pc->inFCS != PPP_GOODFCS) { + PPPDEBUG((LOG_INFO, + "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", + pd, pc->inFCS, pc->inProtocol)); +#if LINK_STATS + lwip_stats.link.chkerr++; +#endif + pppDrop(pc); + } + /* Otherwise it's a good packet so pass it on. */ + else { + + /* Trim off the checksum. */ + if(pc->inTail->len >= 2) { + pc->inTail->len -= 2; + + pc->inTail->tot_len = pc->inTail->len; + if (pc->inTail != pc->inHead) { + pbuf_cat(pc->inHead, pc->inTail); + } + } else { + pc->inTail->tot_len = pc->inTail->len; + if (pc->inTail != pc->inHead) { + pbuf_cat(pc->inHead, pc->inTail); + } + + pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2); + } + + /* Dispatch the packet thereby consuming it. */ + if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) { + PPPDEBUG((LOG_ERR, + "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd)); + pbuf_free(pc->inHead); +#if LINK_STATS + lwip_stats.link.drop++; +#endif + } + pc->inHead = NULL; + pc->inTail = NULL; + } + + /* Prepare for a new packet. */ + pc->inFCS = PPP_INITFCS; + pc->inState = PDADDRESS; + pc->inEscaped = 0; + } + /* Other characters are usually control characters that may have + * been inserted by the physical layer so here we just drop them. */ + else { + PPPDEBUG((LOG_WARNING, + "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar)); + } + } + /* Process other characters. */ + else { + /* Unencode escaped characters. */ + if (pc->inEscaped) { + pc->inEscaped = 0; + curChar ^= PPP_TRANS; + } + + /* Process character relative to current state. */ + switch(pc->inState) { + case PDIDLE: /* Idle state - waiting. */ + /* Drop the character if it's not 0xff + * we would have processed a flag character above. */ + if (curChar != PPP_ALLSTATIONS) { + break; + } + + /* Fall through */ + case PDSTART: /* Process start flag. */ + /* Prepare for a new packet. */ + pc->inFCS = PPP_INITFCS; + + /* Fall through */ + case PDADDRESS: /* Process address field. */ + if (curChar == PPP_ALLSTATIONS) { + pc->inState = PDCONTROL; + break; + } + /* Else assume compressed address and control fields so + * fall through to get the protocol... */ + case PDCONTROL: /* Process control field. */ + /* If we don't get a valid control code, restart. */ + if (curChar == PPP_UI) { + pc->inState = PDPROTOCOL1; + break; + } +#if 0 + else { + PPPDEBUG((LOG_WARNING, + "pppInProc[%d]: Invalid control <%d>\n", pd, curChar)); + pc->inState = PDSTART; + } +#endif + case PDPROTOCOL1: /* Process protocol field 1. */ + /* If the lower bit is set, this is the end of the protocol + * field. */ + if (curChar & 1) { + pc->inProtocol = curChar; + pc->inState = PDDATA; + } + else { + pc->inProtocol = (u_int)curChar << 8; + pc->inState = PDPROTOCOL2; + } + break; + case PDPROTOCOL2: /* Process protocol field 2. */ + pc->inProtocol |= curChar; + pc->inState = PDDATA; + break; + case PDDATA: /* Process data byte. */ + /* Make space to receive processed data. */ + if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) { + if(pc->inTail) { + pc->inTail->tot_len = pc->inTail->len; + if (pc->inTail != pc->inHead) { + pbuf_cat(pc->inHead, pc->inTail); + } + } + /* If we haven't started a packet, we need a packet header. */ + nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (nextNBuf == NULL) { + /* No free buffers. Drop the input packet and let the + * higher layers deal with it. Continue processing + * the received pbuf chain in case a new packet starts. */ + PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd)); +#if LINK_STATS + lwip_stats.link.memerr++; +#endif /* LINK_STATS */ + pppDrop(pc); + pc->inState = PDSTART; /* Wait for flag sequence. */ + break; + } + if (pc->inHead == NULL) { + struct pppInputHeader *pih = nextNBuf->payload; + + pih->unit = pd; + pih->proto = pc->inProtocol; + + nextNBuf->len += sizeof(*pih); + + pc->inHead = nextNBuf; + } + pc->inTail = nextNBuf; + } + /* Load character into buffer. */ + ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar; + break; + } + + /* update the frame check sequence number. */ + pc->inFCS = PPP_FCS(pc->inFCS, curChar); + } + } + avRandomize(); +} + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ppp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ppp.h new file mode 100644 index 0000000..0943248 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/ppp.h @@ -0,0 +1,446 @@ +/***************************************************************************** +* ppp.h - Network Point to Point Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ + +#ifndef PPP_H +#define PPP_H + +#include "lwip/opt.h" + +#if PPP_SUPPORT > 0 +#include "lwip/sio.h" +#include "lwip/api.h" +#include "lwip/sockets.h" +#include "lwip/stats.h" +#include "lwip/mem.h" +#include "lwip/tcpip.h" +#include "lwip/netif.h" + +/* + * pppd.h - PPP daemon global declarations. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ +/* + * ppp_defs.h - PPP definitions. + * + * Copyright (c) 1994 The Australian National University. + * All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, provided that the above copyright + * notice appears in all copies. This software is provided without any + * warranty, express or implied. The Australian National University + * makes no representations about the suitability of this software for + * any purpose. + * + * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY + * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES + * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, + * OR MODIFICATIONS. + */ + +#define TIMEOUT(f, a, t) sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a)) +#define UNTIMEOUT(f, a) sys_untimeout((f), (a)) + + +# ifndef __u_char_defined + +/* Type definitions for BSD code. */ +typedef unsigned long u_long; +typedef unsigned int u_int; +typedef unsigned short u_short; +typedef unsigned char u_char; + +#endif + +/* + * Constants and structures defined by the internet system, + * Per RFC 790, September 1981, and numerous additions. + */ + +/* + * The basic PPP frame. + */ +#define PPP_HDRLEN 4 /* octets for standard ppp header */ +#define PPP_FCSLEN 2 /* octets for FCS */ + + +/* + * Significant octet values. + */ +#define PPP_ALLSTATIONS 0xff /* All-Stations broadcast address */ +#define PPP_UI 0x03 /* Unnumbered Information */ +#define PPP_FLAG 0x7e /* Flag Sequence */ +#define PPP_ESCAPE 0x7d /* Asynchronous Control Escape */ +#define PPP_TRANS 0x20 /* Asynchronous transparency modifier */ + +/* + * Protocol field values. + */ +#define PPP_IP 0x21 /* Internet Protocol */ +#define PPP_AT 0x29 /* AppleTalk Protocol */ +#define PPP_VJC_COMP 0x2d /* VJ compressed TCP */ +#define PPP_VJC_UNCOMP 0x2f /* VJ uncompressed TCP */ +#define PPP_COMP 0xfd /* compressed packet */ +#define PPP_IPCP 0x8021 /* IP Control Protocol */ +#define PPP_ATCP 0x8029 /* AppleTalk Control Protocol */ +#define PPP_CCP 0x80fd /* Compression Control Protocol */ +#define PPP_LCP 0xc021 /* Link Control Protocol */ +#define PPP_PAP 0xc023 /* Password Authentication Protocol */ +#define PPP_LQR 0xc025 /* Link Quality Report protocol */ +#define PPP_CHAP 0xc223 /* Cryptographic Handshake Auth. Protocol */ +#define PPP_CBCP 0xc029 /* Callback Control Protocol */ + +/* + * Values for FCS calculations. + */ +#define PPP_INITFCS 0xffff /* Initial FCS value */ +#define PPP_GOODFCS 0xf0b8 /* Good final FCS value */ +#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff]) + +/* + * Extended asyncmap - allows any character to be escaped. + */ +typedef u_char ext_accm[32]; + +/* + * What to do with network protocol (NP) packets. + */ +enum NPmode { + NPMODE_PASS, /* pass the packet through */ + NPMODE_DROP, /* silently drop the packet */ + NPMODE_ERROR, /* return an error */ + NPMODE_QUEUE /* save it up for later. */ +}; + +/* + * Inline versions of get/put char/short/long. + * Pointer is advanced; we assume that both arguments + * are lvalues and will already be in registers. + * cp MUST be u_char *. + */ +#define GETCHAR(c, cp) { \ + (c) = *(cp)++; \ +} +#define PUTCHAR(c, cp) { \ + *(cp)++ = (u_char) (c); \ +} + + +#define GETSHORT(s, cp) { \ + (s) = *(cp); (cp)++; (s) << 8; \ + (s) |= *(cp); (cp)++; \ +} +#define PUTSHORT(s, cp) { \ + *(cp)++ = (u_char) ((s) >> 8); \ + *(cp)++ = (u_char) (s); \ +} + +#define GETLONG(l, cp) { \ + (l) = *(cp); (cp)++; (l) << 8; \ + (l) |= *(cp); (cp)++; (l) <<= 8; \ + (l) |= *(cp); (cp)++; (l) <<= 8; \ + (l) |= *(cp); (cp)++; \ +} +#define PUTLONG(l, cp) { \ + *(cp)++ = (u_char) ((l) >> 24); \ + *(cp)++ = (u_char) ((l) >> 16); \ + *(cp)++ = (u_char) ((l) >> 8); \ + *(cp)++ = (u_char) (l); \ +} + + +#define INCPTR(n, cp) ((cp) += (n)) +#define DECPTR(n, cp) ((cp) -= (n)) + +#define BCMP(s0, s1, l) memcmp((u_char *)(s0), (u_char *)(s1), (l)) +#define BCOPY(s, d, l) memcpy((d), (s), (l)) +#define BZERO(s, n) memset(s, 0, n) +#if PPP_DEBUG +#define PRINTMSG(m, l) { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); } +#else +#define PRINTMSG(m, l) +#endif + +/* + * MAKEHEADER - Add PPP Header fields to a packet. + */ +#define MAKEHEADER(p, t) { \ + PUTCHAR(PPP_ALLSTATIONS, p); \ + PUTCHAR(PPP_UI, p); \ + PUTSHORT(t, p); } + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ + +/* Error codes. */ +#define PPPERR_NONE 0 /* No error. */ +#define PPPERR_PARAM -1 /* Invalid parameter. */ +#define PPPERR_OPEN -2 /* Unable to open PPP session. */ +#define PPPERR_DEVICE -3 /* Invalid I/O device for PPP. */ +#define PPPERR_ALLOC -4 /* Unable to allocate resources. */ +#define PPPERR_USER -5 /* User interrupt. */ +#define PPPERR_CONNECT -6 /* Connection lost. */ +#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */ +#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */ + +/* + * PPP IOCTL commands. + */ +/* + * Get the up status - 0 for down, non-zero for up. The argument must + * point to an int. + */ +#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */ +#define PPPCTLS_ERRCODE 101 /* Set the error code */ +#define PPPCTLG_ERRCODE 102 /* Get the error code */ +#define PPPCTLG_FD 103 /* Get the fd associated with the ppp */ + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * The following struct gives the addresses of procedures to call + * for a particular protocol. + */ +struct protent { + u_short protocol; /* PPP protocol number */ + /* Initialization procedure */ + void (*init) (int unit); + /* Process a received packet */ + void (*input) (int unit, u_char *pkt, int len); + /* Process a received protocol-reject */ + void (*protrej) (int unit); + /* Lower layer has come up */ + void (*lowerup) (int unit); + /* Lower layer has gone down */ + void (*lowerdown) (int unit); + /* Open the protocol */ + void (*open) (int unit); + /* Close the protocol */ + void (*close) (int unit, char *reason); +#if 0 + /* Print a packet in readable form */ + int (*printpkt) (u_char *pkt, int len, + void (*printer) (void *, char *, ...), + void *arg); + /* Process a received data packet */ + void (*datainput) (int unit, u_char *pkt, int len); +#endif + int enabled_flag; /* 0 iff protocol is disabled */ + char *name; /* Text name of protocol */ +#if 0 + /* Check requested options, assign defaults */ + void (*check_options) (u_long); + /* Configure interface for demand-dial */ + int (*demand_conf) (int unit); + /* Say whether to bring up link for this pkt */ + int (*active_pkt) (u_char *pkt, int len); +#endif +}; + +/* + * The following structure records the time in seconds since + * the last NP packet was sent or received. + */ +struct ppp_idle { + u_short xmit_idle; /* seconds since last NP packet sent */ + u_short recv_idle; /* seconds since last NP packet received */ +}; + +struct ppp_settings { + + u_int disable_defaultip : 1; /* Don't use hostname for default IP addrs */ + u_int auth_required : 1; /* Peer is required to authenticate */ + u_int explicit_remote : 1; /* remote_name specified with remotename opt */ + u_int refuse_pap : 1; /* Don't wanna auth. ourselves with PAP */ + u_int refuse_chap : 1; /* Don't wanna auth. ourselves with CHAP */ + u_int usehostname : 1; /* Use hostname for our_name */ + u_int usepeerdns : 1; /* Ask peer for DNS adds */ + + u_short idle_time_limit; /* Shut down link if idle for this long */ + int maxconnect; /* Maximum connect time (seconds) */ + + char user[MAXNAMELEN + 1];/* Username for PAP */ + char passwd[MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */ + char our_name[MAXNAMELEN + 1]; /* Our name for authentication purposes */ + char remote_name[MAXNAMELEN + 1]; /* Peer's name for authentication */ +}; + +struct ppp_addrs { + struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2; +}; + +/***************************** +*** PUBLIC DATA STRUCTURES *** +*****************************/ +/* Buffers for outgoing packets. */ +extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; + +extern struct ppp_settings ppp_settings; + +extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */ + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +/* Initialize the PPP subsystem. */ +void pppInit(void); + +/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. + * RFC 1994 says: + * + * In practice, within or associated with each PPP server, there is a + * database which associates "user" names with authentication + * information ("secrets"). It is not anticipated that a particular + * named user would be authenticated by multiple methods. This would + * make the user vulnerable to attacks which negotiate the least secure + * method from among a set (such as PAP rather than CHAP). If the same + * secret was used, PAP would reveal the secret to be used later with + * CHAP. + * + * Instead, for each user name there should be an indication of exactly + * one method used to authenticate that user name. If a user needs to + * make use of different authentication methods under different + * circumstances, then distinct user names SHOULD be employed, each of + * which identifies exactly one authentication method. + * + */ +enum pppAuthType { + PPPAUTHTYPE_NONE, + PPPAUTHTYPE_ANY, + PPPAUTHTYPE_PAP, + PPPAUTHTYPE_CHAP +}; + +void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd); + +/* + * Open a new PPP connection using the given I/O device. + * This initializes the PPP control block but does not + * attempt to negotiate the LCP session. + * Return a new PPP connection descriptor on success or + * an error code (negative) on failure. + */ +int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx); + +/* + * Close a PPP connection and release the descriptor. + * Any outstanding packets in the queues are dropped. + * Return 0 on success, an error code on failure. + */ +int pppClose(int pd); + +/* + * Indicate to the PPP process that the line has disconnected. + */ +void pppSigHUP(int pd); + +/* + * Get and set parameters for the given connection. + * Return 0 on success, an error code on failure. + */ +int pppIOCtl(int pd, int cmd, void *arg); + +/* + * Return the Maximum Transmission Unit for the given PPP connection. + */ +u_int pppMTU(int pd); + +/* + * Write n characters to a ppp link. + * RETURN: >= 0 Number of characters written + * -1 Failed to write to device + */ +int pppWrite(int pd, const u_char *s, int n); + +void pppMainWakeup(int pd); + +/* Configure i/f transmit parameters */ +void ppp_send_config (int, int, u32_t, int, int); +/* Set extended transmit ACCM */ +void ppp_set_xaccm (int, ext_accm *); +/* Configure i/f receive parameters */ +void ppp_recv_config (int, int, u32_t, int, int); +/* Find out how long link has been idle */ +int get_idle_time (int, struct ppp_idle *); + +/* Configure VJ TCP header compression */ +int sifvjcomp (int, int, int, int); +/* Configure i/f down (for IP) */ +int sifup (int); +/* Set mode for handling packets for proto */ +int sifnpmode (int u, int proto, enum NPmode mode); +/* Configure i/f down (for IP) */ +int sifdown (int); +/* Configure IP addresses for i/f */ +int sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t); +/* Reset i/f IP addresses */ +int cifaddr (int, u32_t, u32_t); +/* Create default route through i/f */ +int sifdefaultroute (int, u32_t, u32_t); +/* Delete default route through i/f */ +int cifdefaultroute (int, u32_t, u32_t); + +/* Get appropriate netmask for address */ +u32_t GetMask (u32_t); + +#endif /* PPP_SUPPORT */ + +#endif /* PPP_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/pppdebug.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/pppdebug.h new file mode 100644 index 0000000..e4cf25a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/pppdebug.h @@ -0,0 +1,89 @@ +/***************************************************************************** +* pppdebug.h - System debugging utilities. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* portions Copyright (c) 2001 by Cognizant Pty Ltd. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY (please don't use tabs!) +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-07-29 Guy Lancaster , Global Election Systems Inc. +* Original. +* +***************************************************************************** +*/ +#ifndef PPPDEBUG_H +#define PPPDEBUG_H + +/************************ +*** PUBLIC DATA TYPES *** +************************/ +/* Trace levels. */ +typedef enum { + LOG_CRITICAL = 0, + LOG_ERR = 1, + LOG_NOTICE = 2, + LOG_WARNING = 3, + LOG_INFO = 5, + LOG_DETAIL = 6, + LOG_DEBUG = 7 +} LogCodes; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ +/* + * ppp_trace - a form of printf to send tracing information to stderr + */ +void ppp_trace(int level, const char *format,...); + +#if PPP_DEBUG > 0 + +#define AUTHDEBUG(a) ppp_trace a +#define IPCPDEBUG(a) ppp_trace a +#define UPAPDEBUG(a) ppp_trace a +#define LCPDEBUG(a) ppp_trace a +#define FSMDEBUG(a) ppp_trace a +#define CHAPDEBUG(a) ppp_trace a +#define PPPDEBUG(a) ppp_trace a + +#define TRACELCP 1 + +#else + +#define AUTHDEBUG(a) +#define IPCPDEBUG(a) +#define UPAPDEBUG(a) +#define LCPDEBUG(a) +#define FSMDEBUG(a) +#define CHAPDEBUG(a) + +#define PPPDEBUG(a) + +#define TRACELCP 0 + +#endif + +#endif /* PPPDEBUG_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/randm.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/randm.c new file mode 100644 index 0000000..d4431dd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/randm.c @@ -0,0 +1,242 @@ +/***************************************************************************** +* randm.c - Random number generator program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1998 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-06-03 Guy Lancaster , Global Election Systems Inc. +* Extracted from avos. +*****************************************************************************/ + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "md5.h" +#include "randm.h" + +#include "pppdebug.h" + + +#if MD5_SUPPORT>0 /* this module depends on MD5 */ +#define RANDPOOLSZ 16 /* Bytes stored in the pool of randomness. */ + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static char randPool[RANDPOOLSZ]; /* Pool of randomness. */ +static long randCount = 0; /* Pseudo-random incrementer */ + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * Initialize the random number generator. + * + * Since this is to be called on power up, we don't have much + * system randomess to work with. Here all we use is the + * real-time clock. We'll accumulate more randomness as soon + * as things start happening. + */ +void avRandomInit() +{ + avChurnRand(NULL, 0); +} + +/* + * Churn the randomness pool on a random event. Call this early and often + * on random and semi-random system events to build randomness in time for + * usage. For randomly timed events, pass a null pointer and a zero length + * and this will use the system timer and other sources to add randomness. + * If new random data is available, pass a pointer to that and it will be + * included. + * + * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 + */ +void avChurnRand(char *randData, u32_t randLen) +{ + MD5_CTX md5; + +/* ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */ + MD5Init(&md5); + MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); + if (randData) + MD5Update(&md5, (u_char *)randData, randLen); + else { + struct { + /* INCLUDE fields for any system sources of randomness */ + char foobar; + } sysData; + + /* Load sysData fields here. */ + ; + MD5Update(&md5, (u_char *)&sysData, sizeof(sysData)); + } + MD5Final((u_char *)randPool, &md5); +/* ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */ +} + +/* + * Use the random pool to generate random data. This degrades to pseudo + * random when used faster than randomness is supplied using churnRand(). + * Note: It's important that there be sufficient randomness in randPool + * before this is called for otherwise the range of the result may be + * narrow enough to make a search feasible. + * + * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 + * + * XXX Why does he not just call churnRand() for each block? Probably + * so that you don't ever publish the seed which could possibly help + * predict future values. + * XXX Why don't we preserve md5 between blocks and just update it with + * randCount each time? Probably there is a weakness but I wish that + * it was documented. + */ +void avGenRand(char *buf, u32_t bufLen) +{ + MD5_CTX md5; + u_char tmp[16]; + u32_t n; + + while (bufLen > 0) { + n = LWIP_MIN(bufLen, RANDPOOLSZ); + MD5Init(&md5); + MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); + MD5Update(&md5, (u_char *)&randCount, sizeof(randCount)); + MD5Final(tmp, &md5); + randCount++; + memcpy(buf, tmp, n); + buf += n; + bufLen -= n; + } +} + +/* + * Return a new random number. + */ +u32_t avRandom() +{ + u32_t newRand; + + avGenRand((char *)&newRand, sizeof(newRand)); + + return newRand; +} + +#else /* MD5_SUPPORT */ + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static int avRandomized = 0; /* Set when truely randomized. */ +static u32_t avRandomSeed = 0; /* Seed used for random number generation. */ + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * Initialize the random number generator. + * + * Here we attempt to compute a random number seed but even if + * it isn't random, we'll randomize it later. + * + * The current method uses the fields from the real time clock, + * the idle process counter, the millisecond counter, and the + * hardware timer tick counter. When this is invoked + * in startup(), then the idle counter and timer values may + * repeat after each boot and the real time clock may not be + * operational. Thus we call it again on the first random + * event. + */ +void avRandomInit() +{ +#if 0 + /* Get a pointer into the last 4 bytes of clockBuf. */ + u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]); + + /* + * Initialize our seed using the real-time clock, the idle + * counter, the millisecond timer, and the hardware timer + * tick counter. The real-time clock and the hardware + * tick counter are the best sources of randomness but + * since the tick counter is only 16 bit (and truncated + * at that), the idle counter and millisecond timer + * (which may be small values) are added to help + * randomize the lower 16 bits of the seed. + */ + readClk(); + avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr + + ppp_mtime() + ((u32_t)TM1 << 16) + TM1; +#else + avRandomSeed += sys_jiffies(); /* XXX */ +#endif + + /* Initialize the Borland random number generator. */ + srand((unsigned)avRandomSeed); +} + +/* + * Randomize our random seed value. Here we use the fact that + * this function is called at *truely random* times by the polling + * and network functions. Here we only get 16 bits of new random + * value but we use the previous value to randomize the other 16 + * bits. + */ +void avRandomize(void) +{ + static u32_t last_jiffies; + + if (!avRandomized) { + avRandomized = !0; + avRandomInit(); + /* The initialization function also updates the seed. */ + } else { +/* avRandomSeed += (avRandomSeed << 16) + TM1; */ + avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */ + } + last_jiffies = sys_jiffies(); +} + +/* + * Return a new random number. + * Here we use the Borland rand() function to supply a pseudo random + * number which we make truely random by combining it with our own + * seed which is randomized by truely random events. + * Thus the numbers will be truely random unless there have been no + * operator or network events in which case it will be pseudo random + * seeded by the real time clock. + */ +u32_t avRandom() +{ + return ((((u32_t)rand() << 16) + rand()) + avRandomSeed); +} + + + +#endif /* MD5_SUPPORT */ +#endif /* PPP_SUPPORT */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/randm.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/randm.h new file mode 100644 index 0000000..2563d89 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/randm.h @@ -0,0 +1,81 @@ +/***************************************************************************** +* randm.h - Random number generator header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-05-29 Guy Lancaster , Global Election Systems Inc. +* Extracted from avos. +*****************************************************************************/ + +#ifndef RANDM_H +#define RANDM_H + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ +/* + * Initialize the random number generator. + */ +void avRandomInit(void); + +/* + * Churn the randomness pool on a random event. Call this early and often + * on random and semi-random system events to build randomness in time for + * usage. For randomly timed events, pass a null pointer and a zero length + * and this will use the system timer and other sources to add randomness. + * If new random data is available, pass a pointer to that and it will be + * included. + */ +void avChurnRand(char *randData, u32_t randLen); + +/* + * Randomize our random seed value. To be called for truely random events + * such as user operations and network traffic. + */ +#if MD5_SUPPORT +#define avRandomize() avChurnRand(NULL, 0) +#else +void avRandomize(void); +#endif + +/* + * Use the random pool to generate random data. This degrades to pseudo + * random when used faster than randomness is supplied using churnRand(). + * Thus it's important to make sure that the results of this are not + * published directly because one could predict the next result to at + * least some degree. Also, it's important to get a good seed before + * the first use. + */ +void avGenRand(char *buf, u32_t bufLen); + +/* + * Return a new random number. + */ +u32_t avRandom(void); + + +#endif /* RANDM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/vj.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/vj.c new file mode 100644 index 0000000..2c11aff --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/vj.c @@ -0,0 +1,633 @@ +/* + * Routines to compress and uncompess tcp packets (for transmission + * over low speed serial lines. + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: + * - Initial distribution. + * + * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au, + * so that the entire packet being decompressed doesn't have + * to be in contiguous memory (just the compressed header). + * + * Modified March 1998 by Guy Lancaster, glanca@gesn.com, + * for a 16 bit processor. + */ + +#include + +#include "ppp.h" +#include "vj.h" +#include "pppdebug.h" + +#if VJ_SUPPORT > 0 + +#if LINK_STATS +#define INCR(counter) ++comp->stats.counter +#else +#define INCR(counter) +#endif + +#if defined(NO_CHAR_BITFIELDS) +#define getip_hl(base) ((base).ip_hl_v&0xf) +#define getth_off(base) (((base).th_x2_off&0xf0)>>4) +#else +#define getip_hl(base) ((base).ip_hl) +#define getth_off(base) ((base).th_off) +#endif + +void vj_compress_init(struct vjcompress *comp) +{ + register u_int i; + register struct cstate *tstate = comp->tstate; + +#if MAX_SLOTS == 0 + memset((char *)comp, 0, sizeof(*comp)); +#endif + comp->maxSlotIndex = MAX_SLOTS - 1; + comp->compressSlot = 0; /* Disable slot ID compression by default. */ + for (i = MAX_SLOTS - 1; i > 0; --i) { + tstate[i].cs_id = i; + tstate[i].cs_next = &tstate[i - 1]; + } + tstate[0].cs_next = &tstate[MAX_SLOTS - 1]; + tstate[0].cs_id = 0; + comp->last_cs = &tstate[0]; + comp->last_recv = 255; + comp->last_xmit = 255; + comp->flags = VJF_TOSS; +} + + +/* ENCODE encodes a number that is known to be non-zero. ENCODEZ + * checks for zero (since zero has to be encoded in the long, 3 byte + * form). + */ +#define ENCODE(n) { \ + if ((u_short)(n) >= 256) { \ + *cp++ = 0; \ + cp[1] = (n); \ + cp[0] = (n) >> 8; \ + cp += 2; \ + } else { \ + *cp++ = (n); \ + } \ +} +#define ENCODEZ(n) { \ + if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \ + *cp++ = 0; \ + cp[1] = (n); \ + cp[0] = (n) >> 8; \ + cp += 2; \ + } else { \ + *cp++ = (n); \ + } \ +} + +#define DECODEL(f) { \ + if (*cp == 0) {\ + u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \ + (f) = htonl(tmp); \ + cp += 3; \ + } else { \ + u32_t tmp = ntohl(f) + (u32_t)*cp++; \ + (f) = htonl(tmp); \ + } \ +} + +#define DECODES(f) { \ + if (*cp == 0) {\ + u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \ + (f) = htons(tmp); \ + cp += 3; \ + } else { \ + u_short tmp = ntohs(f) + (u_short)*cp++; \ + (f) = htons(tmp); \ + } \ +} + +#define DECODEU(f) { \ + if (*cp == 0) {\ + (f) = htons(((u_short)cp[1] << 8) | cp[2]); \ + cp += 3; \ + } else { \ + (f) = htons((u_short)*cp++); \ + } \ +} + +/* + * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a + * packet. This assumes that nb and comp are not null and that the first + * buffer of the chain contains a valid IP header. + * Return the VJ type code indicating whether or not the packet was + * compressed. + */ +u_int vj_compress_tcp( + struct vjcompress *comp, + struct pbuf *pb +) +{ + register struct ip *ip = (struct ip *)pb->payload; + register struct cstate *cs = comp->last_cs->cs_next; + register u_short hlen = getip_hl(*ip); + register struct tcphdr *oth; + register struct tcphdr *th; + register u_short deltaS, deltaA; + register u_long deltaL; + register u_int changes = 0; + u_char new_seq[16]; + register u_char *cp = new_seq; + + /* + * Check that the packet is IP proto TCP. + */ + if (ip->ip_p != IPPROTO_TCP) + return (TYPE_IP); + + /* + * Bail if this is an IP fragment or if the TCP packet isn't + * `compressible' (i.e., ACK isn't set or some other control bit is + * set). + */ + if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40) + return (TYPE_IP); + th = (struct tcphdr *)&((long *)ip)[hlen]; + if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) + return (TYPE_IP); + + /* + * Packet is compressible -- we're going to send either a + * COMPRESSED_TCP or UNCOMPRESSED_TCP packet. Either way we need + * to locate (or create) the connection state. Special case the + * most recently used connection since it's most likely to be used + * again & we don't have to do any reordering if it's used. + */ + INCR(vjs_packets); + if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr + || ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr + || *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) { + /* + * Wasn't the first -- search for it. + * + * States are kept in a circularly linked list with + * last_cs pointing to the end of the list. The + * list is kept in lru order by moving a state to the + * head of the list whenever it is referenced. Since + * the list is short and, empirically, the connection + * we want is almost always near the front, we locate + * states via linear search. If we don't find a state + * for the datagram, the oldest state is (re-)used. + */ + register struct cstate *lcs; + register struct cstate *lastcs = comp->last_cs; + + do { + lcs = cs; cs = cs->cs_next; + INCR(vjs_searches); + if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr + && ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr + && *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) + goto found; + } while (cs != lastcs); + + /* + * Didn't find it -- re-use oldest cstate. Send an + * uncompressed packet that tells the other side what + * connection number we're using for this conversation. + * Note that since the state list is circular, the oldest + * state points to the newest and we only need to set + * last_cs to update the lru linkage. + */ + INCR(vjs_misses); + comp->last_cs = lcs; + hlen += getth_off(*th); + hlen <<= 2; + /* Check that the IP/TCP headers are contained in the first buffer. */ + if (hlen > pb->len) + return (TYPE_IP); + goto uncompressed; + + found: + /* + * Found it -- move to the front on the connection list. + */ + if (cs == lastcs) + comp->last_cs = lcs; + else { + lcs->cs_next = cs->cs_next; + cs->cs_next = lastcs->cs_next; + lastcs->cs_next = cs; + } + } + + oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen]; + deltaS = hlen; + hlen += getth_off(*th); + hlen <<= 2; + /* Check that the IP/TCP headers are contained in the first buffer. */ + if (hlen > pb->len) { + PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", + hlen)); + return (TYPE_IP); + } + + /* + * Make sure that only what we expect to change changed. The first + * line of the `if' checks the IP protocol version, header length & + * type of service. The 2nd line checks the "Don't fragment" bit. + * The 3rd line checks the time-to-live and protocol (the protocol + * check is unnecessary but costless). The 4th line checks the TCP + * header length. The 5th line checks IP options, if any. The 6th + * line checks TCP options, if any. If any of these things are + * different between the previous & current datagram, we send the + * current datagram `uncompressed'. + */ + if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] + || ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] + || ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] + || getth_off(*th) != getth_off(*oth) + || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) + || (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2))) + goto uncompressed; + + /* + * Figure out which of the changing fields changed. The + * receiver expects changes in the order: urgent, window, + * ack, seq (the order minimizes the number of temporaries + * needed in this section of code). + */ + if (th->th_flags & TCP_URG) { + deltaS = ntohs(th->th_urp); + ENCODEZ(deltaS); + changes |= NEW_U; + } else if (th->th_urp != oth->th_urp) + /* argh! URG not set but urp changed -- a sensible + * implementation should never do this but RFC793 + * doesn't prohibit the change so we have to deal + * with it. */ + goto uncompressed; + + if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) { + ENCODE(deltaS); + changes |= NEW_W; + } + + if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) { + if (deltaL > 0xffff) + goto uncompressed; + deltaA = (u_short)deltaL; + ENCODE(deltaA); + changes |= NEW_A; + } + + if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) { + if (deltaL > 0xffff) + goto uncompressed; + deltaS = (u_short)deltaL; + ENCODE(deltaS); + changes |= NEW_S; + } + + switch(changes) { + + case 0: + /* + * Nothing changed. If this packet contains data and the + * last one didn't, this is probably a data packet following + * an ack (normal on an interactive connection) and we send + * it compressed. Otherwise it's probably a retransmit, + * retransmitted ack or window probe. Send it uncompressed + * in case the other side missed the compressed version. + */ + if (ip->ip_len != cs->cs_ip.ip_len && + ntohs(cs->cs_ip.ip_len) == hlen) + break; + + /* (fall through) */ + + case SPECIAL_I: + case SPECIAL_D: + /* + * actual changes match one of our special case encodings -- + * send packet uncompressed. + */ + goto uncompressed; + + case NEW_S|NEW_A: + if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) { + /* special case for echoed terminal traffic */ + changes = SPECIAL_I; + cp = new_seq; + } + break; + + case NEW_S: + if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) { + /* special case for data xfer */ + changes = SPECIAL_D; + cp = new_seq; + } + break; + } + + deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id)); + if (deltaS != 1) { + ENCODEZ(deltaS); + changes |= NEW_I; + } + if (th->th_flags & TCP_PSH) + changes |= TCP_PUSH_BIT; + /* + * Grab the cksum before we overwrite it below. Then update our + * state with this packet's header. + */ + deltaA = ntohs(th->th_sum); + BCOPY(ip, &cs->cs_ip, hlen); + + /* + * We want to use the original packet as our compressed packet. + * (cp - new_seq) is the number of bytes we need for compressed + * sequence numbers. In addition we need one byte for the change + * mask, one for the connection id and two for the tcp checksum. + * So, (cp - new_seq) + 4 bytes of header are needed. hlen is how + * many bytes of the original packet to toss so subtract the two to + * get the new packet size. + */ + deltaS = (u_short)(cp - new_seq); + if (!comp->compressSlot || comp->last_xmit != cs->cs_id) { + comp->last_xmit = cs->cs_id; + hlen -= deltaS + 4; + pbuf_header(pb, -hlen); + cp = (u_char *)pb->payload; + *cp++ = changes | NEW_C; + *cp++ = cs->cs_id; + } else { + hlen -= deltaS + 3; + pbuf_header(pb, -hlen); + cp = (u_char *)pb->payload; + *cp++ = changes; + } + *cp++ = deltaA >> 8; + *cp++ = deltaA; + BCOPY(new_seq, cp, deltaS); + INCR(vjs_compressed); + return (TYPE_COMPRESSED_TCP); + + /* + * Update connection state cs & send uncompressed packet (that is, + * a regular ip/tcp packet but with the 'conversation id' we hope + * to use on future compressed packets in the protocol field). + */ +uncompressed: + BCOPY(ip, &cs->cs_ip, hlen); + ip->ip_p = cs->cs_id; + comp->last_xmit = cs->cs_id; + return (TYPE_UNCOMPRESSED_TCP); +} + +/* + * Called when we may have missed a packet. + */ +void vj_uncompress_err(struct vjcompress *comp) +{ + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); +} + +/* + * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP. + * Return 0 on success, -1 on failure. + */ +int vj_uncompress_uncomp( + struct pbuf *nb, + struct vjcompress *comp +) +{ + register u_int hlen; + register struct cstate *cs; + register struct ip *ip; + + ip = (struct ip *)nb->payload; + hlen = getip_hl(*ip) << 2; + if (ip->ip_p >= MAX_SLOTS + || hlen + sizeof(struct tcphdr) > nb->len + || (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2) + > nb->len + || hlen > MAX_HDR) { + PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", + ip->ip_p, hlen, nb->len)); + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); + return -1; + } + cs = &comp->rstate[comp->last_recv = ip->ip_p]; + comp->flags &=~ VJF_TOSS; + ip->ip_p = IPPROTO_TCP; + BCOPY(ip, &cs->cs_ip, hlen); + cs->cs_hlen = hlen; + INCR(vjs_uncompressedin); + return 0; +} + +/* + * Uncompress a packet of type TYPE_COMPRESSED_TCP. + * The packet is composed of a buffer chain and the first buffer + * must contain an accurate chain length. + * The first buffer must include the entire compressed TCP/IP header. + * This procedure replaces the compressed header with the uncompressed + * header and returns the length of the VJ header. + */ +int vj_uncompress_tcp( + struct pbuf **nb, + struct vjcompress *comp +) +{ + u_char *cp; + struct tcphdr *th; + struct cstate *cs; + u_short *bp; + struct pbuf *n0 = *nb; + u32_t tmp; + u_int vjlen, hlen, changes; + + INCR(vjs_compressedin); + cp = (u_char *)n0->payload; + changes = *cp++; + if (changes & NEW_C) { + /* + * Make sure the state index is in range, then grab the state. + * If we have a good state index, clear the 'discard' flag. + */ + if (*cp >= MAX_SLOTS) { + PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp)); + goto bad; + } + + comp->flags &=~ VJF_TOSS; + comp->last_recv = *cp++; + } else { + /* + * this packet has an implicit state index. If we've + * had a line error since the last time we got an + * explicit state index, we have to toss the packet. + */ + if (comp->flags & VJF_TOSS) { + PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n")); + INCR(vjs_tossed); + return (-1); + } + } + cs = &comp->rstate[comp->last_recv]; + hlen = getip_hl(cs->cs_ip) << 2; + th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen]; + th->th_sum = htons((*cp << 8) | cp[1]); + cp += 2; + if (changes & TCP_PUSH_BIT) + th->th_flags |= TCP_PSH; + else + th->th_flags &=~ TCP_PSH; + + switch (changes & SPECIALS_MASK) { + case SPECIAL_I: + { + register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen; + /* some compilers can't nest inline assembler.. */ + tmp = ntohl(th->th_ack) + i; + th->th_ack = htonl(tmp); + tmp = ntohl(th->th_seq) + i; + th->th_seq = htonl(tmp); + } + break; + + case SPECIAL_D: + /* some compilers can't nest inline assembler.. */ + tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen; + th->th_seq = htonl(tmp); + break; + + default: + if (changes & NEW_U) { + th->th_flags |= TCP_URG; + DECODEU(th->th_urp); + } else + th->th_flags &=~ TCP_URG; + if (changes & NEW_W) + DECODES(th->th_win); + if (changes & NEW_A) + DECODEL(th->th_ack); + if (changes & NEW_S) + DECODEL(th->th_seq); + break; + } + if (changes & NEW_I) { + DECODES(cs->cs_ip.ip_id); + } else { + cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1; + cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id); + } + + /* + * At this point, cp points to the first byte of data in the + * packet. Fill in the IP total length and update the IP + * header checksum. + */ + vjlen = (u_short)(cp - (u_char*)n0->payload); + if (n0->len < vjlen) { + /* + * We must have dropped some characters (crc should detect + * this but the old slip framing won't) + */ + PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", + n0->len, vjlen)); + goto bad; + } + +#if BYTE_ORDER == LITTLE_ENDIAN + tmp = n0->tot_len - vjlen + cs->cs_hlen; + cs->cs_ip.ip_len = htons(tmp); +#else + cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen); +#endif + + /* recompute the ip header checksum */ + bp = (u_short *) &cs->cs_ip; + cs->cs_ip.ip_sum = 0; + for (tmp = 0; hlen > 0; hlen -= 2) + tmp += *bp++; + tmp = (tmp & 0xffff) + (tmp >> 16); + tmp = (tmp & 0xffff) + (tmp >> 16); + cs->cs_ip.ip_sum = (u_short)(~tmp); + + /* Remove the compressed header and prepend the uncompressed header. */ + pbuf_header(n0, -vjlen); + + if(MEM_ALIGN(n0->payload) != n0->payload) { + struct pbuf *np, *q; + u8_t *bufptr; + + np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL); + if(!np) { + PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n")); + *nb = NULL; + goto bad; + } + + pbuf_header(np, -cs->cs_hlen); + + bufptr = n0->payload; + for(q = np; q != NULL; q = q->next) { + memcpy(q->payload, bufptr, q->len); + bufptr += q->len; + } + + if(n0->next) { + pbuf_chain(np, n0->next); + pbuf_dechain(n0); + } + pbuf_free(n0); + n0 = np; + } + + if(pbuf_header(n0, cs->cs_hlen)) { + struct pbuf *np; + + LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE); + np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL); + if(!np) { + PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n")); + *nb = NULL; + goto bad; + } + pbuf_cat(np, n0); + n0 = np; + } + LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen); + memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen); + + *nb = n0; + + return vjlen; + +bad: + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); + return (-1); +} + +#endif + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/vj.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/vj.h new file mode 100644 index 0000000..9da2714 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/vj.h @@ -0,0 +1,155 @@ +/* + * Definitions for tcp compression routines. + * + * $Id: vj.h,v 1.4 2004/02/07 00:30:03 likewise Exp $ + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: + * - Initial distribution. + */ + +#ifndef VJ_H +#define VJ_H + +#include "vjbsdhdr.h" + +#define MAX_SLOTS 16 /* must be > 2 and < 256 */ +#define MAX_HDR 128 + +/* + * Compressed packet format: + * + * The first octet contains the packet type (top 3 bits), TCP + * 'push' bit, and flags that indicate which of the 4 TCP sequence + * numbers have changed (bottom 5 bits). The next octet is a + * conversation number that associates a saved IP/TCP header with + * the compressed packet. The next two octets are the TCP checksum + * from the original datagram. The next 0 to 15 octets are + * sequence number changes, one change per bit set in the header + * (there may be no changes and there are two special cases where + * the receiver implicitly knows what changed -- see below). + * + * There are 5 numbers which can change (they are always inserted + * in the following order): TCP urgent pointer, window, + * acknowlegement, sequence number and IP ID. (The urgent pointer + * is different from the others in that its value is sent, not the + * change in value.) Since typical use of SLIP links is biased + * toward small packets (see comments on MTU/MSS below), changes + * use a variable length coding with one octet for numbers in the + * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the + * range 256 - 65535 or 0. (If the change in sequence number or + * ack is more than 65535, an uncompressed packet is sent.) + */ + +/* + * Packet types (must not conflict with IP protocol version) + * + * The top nibble of the first octet is the packet type. There are + * three possible types: IP (not proto TCP or tcp with one of the + * control flags set); uncompressed TCP (a normal IP/TCP packet but + * with the 8-bit protocol field replaced by an 8-bit connection id -- + * this type of packet syncs the sender & receiver); and compressed + * TCP (described above). + * + * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and + * is logically part of the 4-bit "changes" field that follows. Top + * three bits are actual packet type. For backward compatibility + * and in the interest of conserving bits, numbers are chosen so the + * IP protocol version number (4) which normally appears in this nibble + * means "IP packet". + */ + +/* packet types */ +#define TYPE_IP 0x40 +#define TYPE_UNCOMPRESSED_TCP 0x70 +#define TYPE_COMPRESSED_TCP 0x80 +#define TYPE_ERROR 0x00 + +/* Bits in first octet of compressed packet */ +#define NEW_C 0x40 /* flag bits for what changed in a packet */ +#define NEW_I 0x20 +#define NEW_S 0x08 +#define NEW_A 0x04 +#define NEW_W 0x02 +#define NEW_U 0x01 + +/* reserved, special-case values of above */ +#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */ +#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */ +#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U) + +#define TCP_PUSH_BIT 0x10 + + +/* + * "state" data for each active tcp conversation on the wire. This is + * basically a copy of the entire IP/TCP header from the last packet + * we saw from the conversation together with a small identifier + * the transmit & receive ends of the line use to locate saved header. + */ +struct cstate { + struct cstate *cs_next; /* next most recently used state (xmit only) */ + u_short cs_hlen; /* size of hdr (receive only) */ + u_char cs_id; /* connection # associated with this state */ + u_char cs_filler; + union { + char csu_hdr[MAX_HDR]; + struct ip csu_ip; /* ip/tcp hdr from most recent packet */ + } vjcs_u; +}; +#define cs_ip vjcs_u.csu_ip +#define cs_hdr vjcs_u.csu_hdr + + +struct vjstat { + unsigned long vjs_packets; /* outbound packets */ + unsigned long vjs_compressed; /* outbound compressed packets */ + unsigned long vjs_searches; /* searches for connection state */ + unsigned long vjs_misses; /* times couldn't find conn. state */ + unsigned long vjs_uncompressedin; /* inbound uncompressed packets */ + unsigned long vjs_compressedin; /* inbound compressed packets */ + unsigned long vjs_errorin; /* inbound unknown type packets */ + unsigned long vjs_tossed; /* inbound packets tossed because of error */ +}; + +/* + * all the state data for one serial line (we need one of these per line). + */ +struct vjcompress { + struct cstate *last_cs; /* most recently used tstate */ + u_char last_recv; /* last rcvd conn. id */ + u_char last_xmit; /* last sent conn. id */ + u_short flags; + u_char maxSlotIndex; + u_char compressSlot; /* Flag indicating OK to compress slot ID. */ +#if LINK_STATS + struct vjstat stats; +#endif + struct cstate tstate[MAX_SLOTS]; /* xmit connection states */ + struct cstate rstate[MAX_SLOTS]; /* receive connection states */ +}; + +/* flag values */ +#define VJF_TOSS 1U /* tossing rcvd frames because of input err */ + +extern void vj_compress_init (struct vjcompress *comp); +extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb); +extern void vj_uncompress_err (struct vjcompress *comp); +extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp); +extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp); + +#endif /* VJ_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/vjbsdhdr.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/vjbsdhdr.h new file mode 100644 index 0000000..a7d180c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/ppp/vjbsdhdr.h @@ -0,0 +1,76 @@ +#ifndef VJBSDHDR_H +#define VJBSDHDR_H + +#include "lwip/tcp.h" + + +/* + * Structure of an internet header, naked of options. + * + * We declare ip_len and ip_off to be short, rather than u_short + * pragmatically since otherwise unsigned comparisons can result + * against negative integers quite easily, and fail in subtle ways. + */ +PACK_STRUCT_BEGIN +struct ip +{ +#if defined(NO_CHAR_BITFIELDS) + u_char ip_hl_v; /* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */ +#else +#if BYTE_ORDER == LITTLE_ENDIAN + unsigned ip_hl:4, /* header length */ + ip_v:4; /* version */ +#elif BYTE_ORDER == BIG_ENDIAN + unsigned ip_v:4, /* version */ + ip_hl:4; /* header length */ +#else + COMPLAIN - NO BYTE ORDER SELECTED! +#endif +#endif + u_char ip_tos; /* type of service */ + u_short ip_len; /* total length */ + u_short ip_id; /* identification */ + u_short ip_off; /* fragment offset field */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + u_char ip_ttl; /* time to live */ + u_char ip_p; /* protocol */ + u_short ip_sum; /* checksum */ + struct in_addr ip_src,ip_dst; /* source and dest address */ +}; +PACK_STRUCT_END + +typedef u32_t tcp_seq; + +/* + * TCP header. + * Per RFC 793, September, 1981. + */ +PACK_STRUCT_BEGIN +struct tcphdr +{ + u_short th_sport; /* source port */ + u_short th_dport; /* destination port */ + tcp_seq th_seq; /* sequence number */ + tcp_seq th_ack; /* acknowledgement number */ +#if defined(NO_CHAR_BITFIELDS) + u_char th_x2_off; +#else +#if BYTE_ORDER == LITTLE_ENDIAN + unsigned th_x2:4, /* (unused) */ + th_off:4; /* data offset */ +#endif +#if BYTE_ORDER == BIG_ENDIAN + unsigned th_off:4, /* data offset */ + th_x2:4; /* (unused) */ +#endif +#endif + u_char th_flags; + u_short th_win; /* window */ + u_short th_sum; /* checksum */ + u_short th_urp; /* urgent pointer */ +}; +PACK_STRUCT_END + +#endif /* VJBSDHDR_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/slipif.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/slipif.c new file mode 100644 index 0000000..ba8510b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwIP/netif/slipif.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is built upon the file: src/arch/rtxc/netif/sioslip.c + * + * Author: Magnus Ivarsson + */ + +/* + * This is an arch independent SLIP netif. The specific serial hooks must be + * provided by another file. They are sio_open, sio_recv and sio_send + */ + +#include "netif/slipif.h" +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "lwip/stats.h" +#include "lwip/sio.h" + +#define SLIP_END 0300 +#define SLIP_ESC 0333 +#define SLIP_ESC_END 0334 +#define SLIP_ESC_ESC 0335 + +#define MAX_SIZE 1500 + +/** + * Send a pbuf doing the necessary SLIP encapsulation + * + * Uses the serial layer's sio_send() + */ +err_t +slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr) +{ + struct pbuf *q; + u16_t i; + u8_t c; + + /* Send pbuf out on the serial I/O device. */ + sio_send(SLIP_END, netif->state); + + for (q = p; q != NULL; q = q->next) { + for (i = 0; i < q->len; i++) { + c = ((u8_t *)q->payload)[i]; + switch (c) { + case SLIP_END: + sio_send(SLIP_ESC, netif->state); + sio_send(SLIP_ESC_END, netif->state); + break; + case SLIP_ESC: + sio_send(SLIP_ESC, netif->state); + sio_send(SLIP_ESC_ESC, netif->state); + break; + default: + sio_send(c, netif->state); + break; + } + } + } + sio_send(SLIP_END, netif->state); + return 0; +} + +/** + * Handle the incoming SLIP stream character by character + * + * Poll the serial layer by calling sio_recv() + * + * @return The IP packet when SLIP_END is received + */ +static struct pbuf * +slipif_input(struct netif *netif) +{ + u8_t c; + struct pbuf *p, *q; + u16_t recved; + u16_t i; + + q = p = NULL; + recved = i = 0; + c = 0; + + while (1) { + c = sio_recv(netif->state); + switch (c) { + case SLIP_END: + if (recved > 0) { + /* Received whole packet. */ + pbuf_realloc(q, recved); + + LINK_STATS_INC(link.recv); + + LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n")); + return q; + } + break; + + case SLIP_ESC: + c = sio_recv(netif->state); + switch (c) { + case SLIP_ESC_END: + c = SLIP_END; + break; + case SLIP_ESC_ESC: + c = SLIP_ESC; + break; + } + /* FALLTHROUGH */ + + default: + if (p == NULL) { + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n")); + p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL); + + if (p == NULL) { + LINK_STATS_INC(link.drop); + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n")); + } + + if (q != NULL) { + pbuf_cat(q, p); + } else { + q = p; + } + } + if (p != NULL && recved < MAX_SIZE) { + ((u8_t *)p->payload)[i] = c; + recved++; + i++; + if (i >= p->len) { + i = 0; + if (p->next != NULL && p->next->len > 0) + p = p->next; + else + p = NULL; + } + } + break; + } + + } + return NULL; +} + +/** + * The SLIP input thread. + * + * Feed the IP layer with incoming packets + */ +static void +slipif_loop(void *nf) +{ + struct pbuf *p; + struct netif *netif = (struct netif *)nf; + + while (1) { + p = slipif_input(netif); + netif->input(p, netif); + } +} + +/** + * SLIP netif initialization + * + * Call the arch specific sio_open and remember + * the opened device in the state field of the netif. + */ +err_t +slipif_init(struct netif *netif) +{ + + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num)); + + netif->name[0] = 's'; + netif->name[1] = 'l'; + netif->output = slipif_output; + netif->mtu = 1500; + netif->flags = NETIF_FLAG_POINTTOPOINT; + + netif->state = sio_open(netif->num); + if (!netif->state) + return ERR_IF; + + sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO); + return ERR_OK; +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/CHANGELOG b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/CHANGELOG new file mode 100644 index 0000000..6e27a66 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/CHANGELOG @@ -0,0 +1,3050 @@ +HISTORY + +(CVS HEAD) + + * [Enter new changes just after this line - do not remove this line] + + ++ New features: + + + ++ Bugfixes: + + + + +(STABLE-1.4.0) + + ++ New features: + + 2011-03-27: Simon Goldschmidt + * tcp_impl.h, tcp_in.c, tcp_out.c: Removed 'dataptr' from 'struct tcp_seg' and + calculate it in tcp_zero_window_probe (the only place where it was used). + + 2010-11-21: Simon Goldschmidt + * dhcp.c/.h: Added a function to deallocate the struct dhcp from a netif + (fixes bug #31525). + + 2010-07-12: Simon Goldschmidt (patch by Stephane Lesage) + * ip.c, udp.c/.h, pbuf.h, sockets.c: task #10495: Added support for + IP_MULTICAST_LOOP at socket- and raw-API level. + + 2010-06-16: Simon Goldschmidt + * ip.c: Added an optional define (LWIP_IP_ACCEPT_UDP_PORT) that can allow + link-layer-addressed UDP traffic to be received while a netif is down (just + like DHCP during configuration) + + 2010-05-22: Simon Goldschmidt + * many many files: bug #27352: removed packing from ip_addr_t, the packed + version is now only used in protocol headers. Added global storage for + current src/dest IP address while in input functions. + + 2010-05-16: Simon Goldschmidt + * def.h: task #10391: Add preprocessor-macros for compile-time htonl + calculation (and use them throughout the stack where applicable) + + 2010-05-16: Simon Goldschmidt + * opt.h, memp_std.h, memp.c, ppp_oe.h/.c: PPPoE now uses its own MEMP pool + instead of the heap (moved struct pppoe_softc from ppp_oe.c to ppp_oe.h) + + 2010-05-16: Simon Goldschmidt + * opt.h, memp_std.h, dns.h/.c: DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses its own + MEMP pool instead of the heap + + 2010-05-13: Simon Goldschmidt + * tcp.c, udp.c: task #6995: Implement SO_REUSEADDR (correctly), added + new option SO_REUSE_RXTOALL to pass received UDP broadcast/multicast + packets to more than one pcb. + + 2010-05-02: Simon Goldschmidt + * netbuf.h/.c, sockets.c, api_msg.c: use checksum-on-copy for sending + UDP data for LWIP_NETIF_TX_SINGLE_PBUF==1 + + 2010-04-30: Simon Goldschmidt + * udp.h/.c, pbuf.h/.c: task #6849: added udp_send(_to/_if) functions that + take a precalculated checksum, added pbuf_fill_chksum() to copy data + into a pbuf and at the same time calculating the checksum for that data + + 2010-04-29: Simon Goldschmidt + * ip_addr.h, etharp.h/.c, autoip.c: Create overridable macros for copying + 2-byte-aligned IP addresses and MAC addresses + + 2010-04-28: Patch by Bill Auerbach + * ip.c: Inline generating IP checksum to save a function call + + 2010-04-14: Simon Goldschmidt + * tcpip.h/.c, timers.c: Added an overridable define to get informed when the + tcpip_thread processes messages or timeouts to implement a watchdog. + + 2010-03-28: Simon Goldschmidt + * ip_frag.c: create a new (contiguous) PBUF_RAM for every outgoing + fragment if LWIP_NETIF_TX_SINGLE_PBUF==1 + + 2010-03-27: Simon Goldschmidt + * etharp.c: Speedup TX by moving code from find_entry to etharp_output/ + etharp_query to prevent unnecessary function calls (inspired by + patch #7135). + + 2010-03-20: Simon Goldschmidt + * opt.h, tcpip.c/.h: Added an option to disable tcpip_(un)timeout code + since the linker cannot do this automatically to save space. + + 2010-03-20: Simon Goldschmidt + * opt.h, etharp.c/.h: Added support for static ARP table entries + + 2010-03-14: Simon Goldschmidt + * tcp_impl.h, tcp_out.c, inet_chksum.h/.c: task #6849: Calculate checksum + when creating TCP segments, not when (re-)transmitting them. + + 2010-03-07: Simon Goldschmidt + * sockets.c: bug #28775 (select/event_callback: only check select_cb_list + on change) plus use SYS_LIGHTWEIGHT_PROT to protect the select code. + This should speed up receiving data on sockets as the select code in + event_callback is only executed when select is waiting. + + 2010-03-06: Simon Goldschmidt + * tcp_out.c: task #7013 (Create option to have all packets delivered to + netif->output in one piece): Always copy to try to create single pbufs + in tcp_write. + + 2010-03-06: Simon Goldschmidt + * api.h, api_lib.c, sockets.c: task #10167 (sockets: speed up TCP recv + by not allocating a netbuf): added function netconn_recv_tcp_pbuf() + for tcp netconns to receive pbufs, not netbufs; use that function + for tcp sockets. + + 2010-03-05: Jakob Ole Stoklundsen / Simon Goldschmidt + * opt.h, tcp.h, tcp_impl.h, tcp.c, tcp_in.c, tcp_out.c: task #7040: + Work on tcp_enqueue: Don't waste memory when chaining segments, + added option TCP_OVERSIZE to prevent creating many small pbufs when + calling tcp_write with many small blocks of data. Instead, pbufs are + allocated larger than needed and the space is used for later calls to + tcp_write. + + 2010-02-21: Simon Goldschmidt + * stats.c/.h: Added const char* name to mem- and memp-stats for easier + debugging. + + 2010-02-21: Simon Goldschmidt + * tcp.h (and usages), added tcp_impl.h: Splitted API and internal + implementation of tcp to make API usage cleare to application programmers + + 2010-02-14: Simon Goldschmidt/Stephane Lesage + * ip_addr.h: Improved some defines working on ip addresses, added faster + macro to copy addresses that cannot be NULL + + 2010-02-13: Simon Goldschmidt + * api.h, api_lib.c, api_msg.c, sockets.c: task #7865 (implement non- + blocking send operation) + + 2010-02-12: Simon Goldschmidt + * sockets.c/.h: Added a minimal version of posix fctl() to have a + standardised way to set O_NONBLOCK for nonblocking sockets. + + 2010-02-12: Simon Goldschmidt + * dhcp.c/.h, autoip.c/.h: task #10139 (Prefer statically allocated + memory): added autoip_set_struct() and dhcp_set_struct() to let autoip + and dhcp work with user-allocated structs instead of callin mem_malloc + + 2010-02-12: Simon Goldschmidt/Jeff Barber + * tcp.c/h: patch #6865 (SO_REUSEADDR for TCP): if pcb.so_options has + SOF_REUSEADDR set, allow binding to endpoint in TIME_WAIT + + 2010-02-12: Simon Goldschmidt + * sys layer: task #10139 (Prefer statically allocated memory): converted + mbox and semaphore functions to take pointers to sys_mbox_t/sys_sem_t; + converted sys_mbox_new/sys_sem_new to take pointers and return err_t; + task #7212: Add Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX + to let sys.h use binary semaphores instead of mutexes - as before) + + 2010-02-09: Simon Goldschmidt (Simon Kallweit) + * timers.c/.h: Added function sys_restart_timeouts() from patch #7085 + (Restart system timeout handling) + + 2010-02-09: Simon Goldschmidt + * netif.c/.h, removed loopif.c/.h: task #10153 (Integrate loopif into + netif.c) - loopif does not have to be created by the port any more, + just define LWIP_HAVE_LOOPIF to 1. + + 2010-02-08: Simon Goldschmidt + * inet.h, ip_addr.c/.h: Added reentrant versions of inet_ntoa/ipaddr_ntoa + inet_ntoa_r/ipaddr_ntoa_r + + 2010-02-08: Simon Goldschmidt + * netif.h: Added netif_s/get_igmp_mac_filter() macros + + 2010-02-05: Simon Goldschmidt + * netif.h: Added function-like macros to get/set the hostname on a netif + + 2010-02-04: Simon Goldschmidt + * nearly every file: Replaced struct ip_addr by typedef ip_addr_t to + make changing the actual implementation behind the typedef easier. + + 2010-02-01: Simon Goldschmidt + * opt.h, memp_std.h, dns.h, netdb.c, memp.c: Let netdb use a memp pool + for allocating memory when getaddrinfo() is called. + + 2010-01-31: Simon Goldschmidt + * dhcp.h, dhcp.c: Reworked the code that parses DHCP options: parse + them once instead of parsing for every option. This also removes + the need for mem_malloc from dhcp_recv and makes it possible to + correctly retrieve the BOOTP file. + + 2010-01-30: simon Goldschmidt + * sockets.c: Use SYS_LIGHTWEIGHT_PROT instead of a semaphore to protect + the sockets array. + + 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) + * api.h, api_msg.c, sockets.c: Added except set support in select + (patch #6860) + + 2010-01-29: Simon Goldschmidt (patch by Laura Garrett) + * api.h, sockets.h, err.h, api_lib.c, api_msg.c, sockets.c, err.c: + Add non-blocking support for connect (partly from patch #6860), + plus many cleanups in socket & netconn API. + + 2010-01-27: Simon Goldschmidt + * opt.h, tcp.h, init.c, api_msg.c: Added TCP_SNDQUEUELOWAT corresponding + to TCP_SNDLOWAT and added tcp_sndqueuelen() - this fixes bug #28605 + + 2010-01-26: Simon Goldschmidt + * snmp: Use memp pools for snmp instead of the heap; added 4 new pools. + + 2010-01-14: Simon Goldschmidt + * ppp.c/.h: Fixed bug #27856: PPP: Set netif link- and status-callback + by adding ppp_set_netif_statuscallback()/ppp_set_netif_linkcallback() + + 2010-01-13: Simon Goldschmidt + * mem.c: The heap now may be moved to user-defined memory by defining + LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address + (patch #6966 and bug #26133) + + 2010-01-10: Simon Goldschmidt (Bill Auerbach) + * opt.h, memp.c: patch #6822 (Add option to place memory pools in + separate arrays) + + 2010-01-10: Simon Goldschmidt + * init.c, igmp.c: patch #6463 (IGMP - Adding Random Delay): added define + LWIP_RAND() for lwip-wide randomization (to be defined in cc.h) + + 2009-12-31: Simon Goldschmidt + * tcpip.c, init.c, memp.c, sys.c, memp_std.h, sys.h, tcpip.h + added timers.c/.h: Separated timer implementation from semaphore/mbox + implementation, moved timer implementation to timers.c/.h, timers are + now only called from tcpip_thread or by explicitly checking them. + (TASK#7235) + + 2009-12-27: Simon Goldschmidt + * opt.h, etharp.h/.c, init.c, tcpip.c: Added an additional option + LWIP_ETHERNET to support ethernet without ARP (necessary for pure PPPoE) + + + ++ Bugfixes: + + 2011-04-20: Simon Goldschmidt + * sys_arch.txt: sys_arch_timeouts() is not needed any more. + + 2011-04-13: Simon Goldschmidt + * tcp.c, udp.c: Fixed bug #33048 (Bad range for IP source port numbers) by + using ports in the IANA private/dynamic range (49152 through 65535). + + 2011-03-29: Simon Goldschmidt, patch by Emil Lhungdahl: + * etharp.h/.c: Fixed broken VLAN support. + + 2011-03-27: Simon Goldschmidt + * tcp.c: Fixed bug #32926 (TCP_RMV(&tcp_bound_pcbs) is called on unbound tcp + pcbs) by checking if the pcb was bound (local_port != 0). + + 2011-03-27: Simon Goldschmidt + * ppp.c: Fixed bug #32280 (ppp: a pbuf is freed twice) + + 2011-03-27: Simon Goldschmidt + * sockets.c: Fixed bug #32906: lwip_connect+lwip_send did not work for udp and + raw pcbs with LWIP_TCPIP_CORE_LOCKING==1. + + 2011-03-27: Simon Goldschmidt + * tcp_out.c: Fixed bug #32820 (Outgoing TCP connections created before route + is present never times out) by starting retransmission timer before checking + route. + + 2011-03-22: Simon Goldschmidt + * ppp.c: Fixed bug #32648 (PPP code crashes when terminating a link) by only + calling sio_read_abort() if the file descriptor is valid. + + 2011-03-14: Simon Goldschmidt + * err.h/.c, sockets.c, api_msg.c: fixed bug #31748 (Calling non-blocking connect + more than once can render a socket useless) since it mainly involves changing + "FATAL" classification of error codes: ERR_USE and ERR_ISCONN just aren't fatal. + + 2011-03-13: Simon Goldschmidt + * sockets.c: fixed bug #32769 (ESHUTDOWN is linux-specific) by fixing + err_to_errno_table (ERR_CLSD: ENOTCONN instead of ESHUTDOWN), ERR_ISCONN: + use EALRADY instead of -1 + + 2011-03-13: Simon Goldschmidt + * api_lib.c: netconn_accept: return ERR_ABRT instead of ERR_CLSD if the + connection has been aborted by err_tcp (since this is not a normal closing + procedure). + + 2011-03-13: Simon Goldschmidt + * tcp.c: tcp_bind: return ERR_VAL instead of ERR_ISCONN when trying to bind + with pcb->state != CLOSED + + 2011-02-17: Simon Goldschmidt + * rawapi.txt: Fixed bug #32561 tcp_poll argument definition out-of-order in + documentation + + 2011-02-17: Simon Goldschmidt + * many files: Added missing U/UL modifiers to fix 16-bit-arch portability. + + 2011-01-24: Simon Goldschmidt + * sockets.c: Fixed bug #31741: lwip_select seems to have threading problems + + 2010-12-02: Simon Goldschmidt + * err.h: Fixed ERR_IS_FATAL so that ERR_WOULDBLOCK is not fatal. + + 2010-11-23: Simon Goldschmidt + * api.h, api_lib.c, api_msg.c, sockets.c: netconn.recv_avail is only used for + LWIP_SO_RCVBUF and ioctl/FIONREAD. + + 2010-11-23: Simon Goldschmidt + * etharp.c: Fixed bug #31720: ARP-queueing: RFC 1122 recommends to queue at + least 1 packet -> ARP_QUEUEING==0 now queues the most recent packet. + + 2010-11-23: Simon Goldschmidt + * tcp_in.c: Fixed bug #30577: tcp_input: don't discard ACK-only packets after + refusing 'refused_data' again. + + 2010-11-22: Simon Goldschmidt + * sockets.c: Fixed bug #31590: getsockopt(... SO_ERROR ...) gives EINPROGRESS + after a successful nonblocking connection. + + 2010-11-22: Simon Goldschmidt + * etharp.c: Fixed bug #31722: IP packets sent with an AutoIP source addr + must be sent link-local + + 2010-11-22: Simon Goldschmidt + * timers.c: patch #7329: tcp_timer_needed prototype was ifdef'ed out for + LWIP_TIMERS==0 + + 2010-11-20: Simon Goldschmidt + * sockets.c: Fixed bug #31170: lwip_setsockopt() does not set socket number + + 2010-11-20: Simon Goldschmidt + * sockets.h: Fixed bug #31304: Changed SHUT_RD, SHUT_WR and SHUT_RDWR to + resemble other stacks. + + 2010-11-20: Simon Goldschmidt + * dns.c: Fixed bug #31535: TCP_SND_QUEUELEN must be at least 2 or else + no-copy TCP writes will never succeed. + + 2010-11-20: Simon Goldschmidt + * dns.c: Fixed bug #31701: Error return value from dns_gethostbyname() does + not match documentation: return ERR_ARG instead of ERR_VAL if not + initialized or wrong argument. + + 2010-10-20: Simon Goldschmidt + * sockets.h: Fixed bug #31385: sizeof(struct sockaddr) is 30 but should be 16 + + 2010-10-05: Simon Goldschmidt + * dhcp.c: Once again fixed #30038: DHCP/AutoIP cooperation failed when + replugging the network cable after an AutoIP address was assigned. + + 2010-08-10: Simon Goldschmidt + * tcp.c: Fixed bug #30728: tcp_new_port() did not check listen pcbs + + 2010-08-03: Simon Goldschmidt + * udp.c, raw.c: Don't chain empty pbufs when sending them (fixes bug #30625) + + 2010-08-01: Simon Goldschmidt (patch by Greg Renda) + * ppp.c: Applied patch #7264 (PPP protocols are rejected incorrectly on big + endian architectures) + + 2010-07-28: Simon Goldschmidt + * api_lib.c, api_msg.c, sockets.c, mib2.c: Fixed compilation with TCP or UDP + disabled. + + 2010-07-27: Simon Goldschmidt + * tcp.c: Fixed bug #30565 (tcp_connect() check bound list): that check did no + harm but never did anything + + 2010-07-21: Simon Goldschmidt + * ip.c: Fixed invalid fix for bug #30402 (CHECKSUM_GEN_IP_INLINE does not + add IP options) + + 2010-07-16: Kieran Mansley + * msg_in.c: Fixed SNMP ASN constant defines to not use ! operator + + 2010-07-10: Simon Goldschmidt + * ip.c: Fixed bug #30402: CHECKSUM_GEN_IP_INLINE does not add IP options + + 2010-06-30: Simon Goldschmidt + * api_msg.c: fixed bug #30300 (shutdown parameter was not initialized in + netconn_delete) + + 2010-06-28: Kieran Mansley + * timers.c remove unportable printing of C function pointers + + 2010-06-24: Simon Goldschmidt + * init.c, timers.c/.h, opt.h, memp_std.h: From patch #7221: added flag + NO_SYS_NO_TIMERS to drop timer support for NO_SYS==1 for easier upgrading + + 2010-06-24: Simon Goldschmidt + * api(_lib).c/.h, api_msg.c/.h, sockets.c/.h: Fixed bug #10088: Correctly + implemented shutdown at socket level. + + 2010-06-21: Simon Goldschmidt + * pbuf.c/.h, ip_frag.c/.h, opt.h, memp_std.h: Fixed bug #29361 (ip_frag has + problems with zero-copy DMA MACs) by adding custom pbufs and implementing + custom pbufs that reference other (original) pbufs. Additionally set + IP_FRAG_USES_STATIC_BUF=0 as default to be on the safe side. + + 2010-06-15: Simon Goldschmidt + * dhcp.c: Fixed bug #29970: DHCP endian issue parsing option responses + + 2010-06-14: Simon Goldschmidt + * autoip.c: Fixed bug #30039: AutoIP does not reuse previous addresses + + 2010-06-12: Simon Goldschmidt + * dhcp.c: Fixed bug #30038: dhcp_network_changed doesn't reset AUTOIP coop + state + + 2010-05-17: Simon Goldschmidt + * netdb.c: Correctly NULL-terminate h_addr_list + + 2010-05-16: Simon Goldschmidt + * def.h/.c: changed the semantics of LWIP_PREFIX_BYTEORDER_FUNCS to prevent + "symbol already defined" i.e. when linking to winsock + + 2010-05-05: Simon Goldschmidt + * def.h, timers.c: Fixed bug #29769 (sys_check_timeouts: sys_now() may + overflow) + + 2010-04-21: Simon Goldschmidt + * api_msg.c: Fixed bug #29617 (sometime cause stall on delete listening + connection) + + 2010-03-28: Luca Ceresoli + * ip_addr.c/.h: patch #7143: Add a few missing const qualifiers + + 2010-03-27: Luca Ceresoli + * mib2.c: patch #7130: remove meaningless const qualifiers + + 2010-03-26: Simon Goldschmidt + * tcp_out.c: Make LWIP_NETIF_TX_SINGLE_PBUF work for TCP, too + + 2010-03-26: Simon Goldschmidt + * various files: Fixed compiling with different options disabled (TCP/UDP), + triggered by bug #29345; don't allocate acceptmbox if LWIP_TCP is disabled + + 2010-03-25: Simon Goldschmidt + * sockets.c: Fixed bug #29332: lwip_select() processes readset incorrectly + + 2010-03-25: Simon Goldschmidt + * tcp_in.c, test_tcp_oos.c: Fixed bug #29080: Correctly handle remote side + overrunning our rcv_wnd in ooseq case. + + 2010-03-22: Simon Goldschmidt + * tcp.c: tcp_listen() did not copy the pcb's prio. + + 2010-03-19: Simon Goldschmidt + * snmp_msg.c: Fixed bug #29256: SNMP Trap address was not correctly set + + 2010-03-14: Simon Goldschmidt + * opt.h, etharp.h: Fixed bug #29148 (Incorrect PBUF_POOL_BUFSIZE for ports + where ETH_PAD_SIZE > 0) by moving definition of ETH_PAD_SIZE to opt.h + and basing PBUF_LINK_HLEN on it. + + 2010-03-08: Simon Goldschmidt + * netif.c, ipv4/ip.c: task #10241 (AutoIP: don't break existing connections + when assiging routable address): when checking incoming packets and + aborting existing connection on address change, filter out link-local + addresses. + + 2010-03-06: Simon Goldschmidt + * sockets.c: Fixed LWIP_NETIF_TX_SINGLE_PBUF for LWIP_TCPIP_CORE_LOCKING + + 2010-03-06: Simon Goldschmidt + * ipv4/ip.c: Don't try to forward link-local addresses + + 2010-03-06: Simon Goldschmidt + * etharp.c: Fixed bug #29087: etharp: don't send packets for LinkLocal- + addresses to gw + + 2010-03-05: Simon Goldschmidt + * dhcp.c: Fixed bug #29072: Correctly set ciaddr based on message-type + and state. + + 2010-03-05: Simon Goldschmidt + * api_msg.c: Correctly set TCP_WRITE_FLAG_MORE when netconn_write is split + into multiple calls to tcp_write. + + 2010-02-21: Simon Goldschmidt + * opt.h, mem.h, dns.c: task #10140: Remove DNS_USES_STATIC_BUF (keep + the implementation of DNS_USES_STATIC_BUF==1) + + 2010-02-20: Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Task #10088: Correctly implement + close() vs. shutdown(). Now the application does not get any more + recv callbacks after calling tcp_close(). Added tcp_shutdown(). + + 2010-02-19: Simon Goldschmidt + * mem.c/.h, pbuf.c: Renamed mem_realloc() to mem_trim() to prevent + confusion with realloc() + + 2010-02-15: Simon Goldschmidt/Stephane Lesage + * netif.c/.h: Link status does not depend on LWIP_NETIF_LINK_CALLBACK + (fixes bug #28899) + + 2010-02-14: Simon Goldschmidt + * netif.c: Fixed bug #28877 (Duplicate ARP gratuitous packet with + LWIP_NETIF_LINK_CALLBACK set on) by only sending if both link- and + admin-status of a netif are up + + 2010-02-14: Simon Goldschmidt + * opt.h: Disable ETHARP_TRUST_IP_MAC by default since it slows down packet + reception and is not really necessary + + 2010-02-14: Simon Goldschmidt + * etharp.c/.h: Fixed ARP input processing: only add a new entry if a + request was directed as us (RFC 826, Packet Reception), otherwise + only update existing entries; internalized some functions + + 2010-02-14: Simon Goldschmidt + * netif.h, etharp.c, tcpip.c: Fixed bug #28183 (ARP and TCP/IP cannot be + disabled on netif used for PPPoE) by adding a new netif flag + (NETIF_FLAG_ETHERNET) that tells the stack the device is an ethernet + device but prevents usage of ARP (so that ethernet_input can be used + for PPPoE). + + 2010-02-12: Simon Goldschmidt + * netif.c: netif_set_link_up/down: only do something if the link state + actually changes + + 2010-02-12: Simon Goldschmidt/Stephane Lesage + * api_msg.c: Fixed bug #28865 (Cannot close socket/netconn in non-blocking + connect) + + 2010-02-12: Simon Goldschmidt + * mem.h: Fixed bug #28866 (mem_realloc function defined in mem.h) + + 2010-02-09: Simon Goldschmidt + * api_lib.c, api_msg.c, sockets.c, api.h, api_msg.h: Fixed bug #22110 + (recv() makes receive window update for data that wasn't received by + application) + + 2010-02-09: Simon Goldschmidt/Stephane Lesage + * sockets.c: Fixed bug #28853 (lwip_recvfrom() returns 0 on receive time-out + or any netconn_recv() error) + + 2010-02-09: Simon Goldschmidt + * ppp.c: task #10154 (PPP: Update snmp in/out counters for tx/rx packets) + + 2010-02-09: Simon Goldschmidt + * netif.c: For loopback packets, adjust the stats- and snmp-counters + for the loopback netif. + + 2010-02-08: Simon Goldschmidt + * igmp.c/.h, ip.h: Moved most defines from igmp.h to igmp.c for clarity + since they are not used anywhere else. + + 2010-02-08: Simon Goldschmidt (Stphane Lesage) + * igmp.c, igmp.h, stats.c, stats.h: Improved IGMP stats + (patch from bug #28798) + + 2010-02-08: Simon Goldschmidt (Stphane Lesage) + * igmp.c: Fixed bug #28798 (Error in "Max Response Time" processing) and + another bug when LWIP_RAND() returns zero. + + 2010-02-04: Simon Goldschmidt + * nearly every file: Use macros defined in ip_addr.h (some of them new) + to work with IP addresses (preparation for bug #27352 - Change ip_addr + from struct to typedef (u32_t) - and better code). + + 2010-01-31: Simon Goldschmidt + * netif.c: Don't call the link-callback from netif_set_up/down() since + this invalidly retriggers DHCP. + + 2010-01-29: Simon Goldschmidt + * ip_addr.h, inet.h, def.h, inet.c, def.c, more: Cleanly separate the + portability file inet.h and its contents from the stack: moved htonX- + functions to def.h (and the new def.c - they are not ipv4 dependent), + let inet.h depend on ip_addr.h and not the other way round. + This fixes bug #28732. + + 2010-01-28: Kieran Mansley + * tcp.c: Ensure ssthresh >= 2*MSS + + 2010-01-27: Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c: Fixed bug #27871: Calling tcp_abort() in recv + callback can lead to accessing unallocated memory. As a consequence, + ERR_ABRT means the application has called tcp_abort()! + + 2010-01-25: Simon Goldschmidt + * snmp_structs.h, msg_in.c: Partly fixed bug #22070 (MIB_OBJECT_WRITE_ONLY + not implemented in SNMP): write-only or not-accessible are still + returned by getnext (though not by get) + + 2010-01-24: Simon Goldschmidt + * snmp: Renamed the private mib node from 'private' to 'mib_private' to + not use reserved C/C++ keywords + + 2010-01-23: Simon Goldschmidt + * sockets.c: Fixed bug #28716: select() returns 0 after waiting for less + than 1 ms + + 2010-01-21: Simon Goldschmidt + * tcp.c, api_msg.c: Fixed bug #28651 (tcp_connect: no callbacks called + if tcp_enqueue fails) both in raw- and netconn-API + + 2010-01-19: Simon Goldschmidt + * api_msg.c: Fixed bug #27316: netconn: Possible deadlock in err_tcp + + 2010-01-18: Iordan Neshev/Simon Goldschmidt + * src/netif/ppp: reorganised PPP sourcecode to 2.3.11 including some + bugfix backports from 2.4.x. + + 2010-01-18: Simon Goldschmidt + * mem.c: Fixed bug #28679: mem_realloc calculates mem_stats wrong + + 2010-01-17: Simon Goldschmidt + * api_lib.c, api_msg.c, (api_msg.h, api.h, sockets.c, tcpip.c): + task #10102: "netconn: clean up conn->err threading issues" by adding + error return value to struct api_msg_msg + + 2010-01-17: Simon Goldschmidt + * api.h, api_lib.c, sockets.c: Changed netconn_recv() and netconn_accept() + to return err_t (bugs #27709 and #28087) + + 2010-01-14: Simon Goldschmidt + * ...: Use typedef for function prototypes throughout the stack. + + 2010-01-13: Simon Goldschmidt + * api_msg.h/.c, api_lib.c: Fixed bug #26672 (close connection when receive + window = 0) by correctly draining recvmbox/acceptmbox + + 2010-01-11: Simon Goldschmidt + * pap.c: Fixed bug #13315 (PPP PAP authentication can result in + erroneous callbacks) by copying the code from recent pppd + + 2010-01-10: Simon Goldschmidt + * raw.c: Fixed bug #28506 (raw_bind should filter received packets) + + 2010-01-10: Simon Goldschmidt + * tcp.h/.c: bug #28127 (remove call to tcp_output() from tcp_ack(_now)()) + + 2010-01-08: Simon Goldschmidt + * sockets.c: Fixed bug #28519 (lwip_recvfrom bug with len > 65535) + + 2010-01-08: Simon Goldschmidt + * dns.c: Copy hostname for DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1 since string + passed to dns_local_addhost() might be volatile + + 2010-01-07: Simon Goldschmidt + * timers.c, tcp.h: Call tcp_timer_needed() with NO_SYS==1, too + + 2010-01-06: Simon Goldschmidt + * netdb.h: Fixed bug #28496: missing include guards in netdb.h + + 2009-12-31: Simon Goldschmidt + * many ppp files: Reorganised PPP source code from ucip structure to pppd + structure to easily compare our code against the pppd code (around v2.3.1) + + 2009-12-27: Simon Goldschmidt + * tcp_in.c: Another fix for bug #28241 (ooseq processing) and adapted + unit test + + +(STABLE-1.3.2) + + ++ New features: + + 2009-10-27 Simon Goldschmidt/Stephan Lesage + * netifapi.c/.h: Added netifapi_netif_set_addr() + + 2009-10-07 Simon Goldschmidt/Fabian Koch + * api_msg.c, netbuf.c/.h, opt.h: patch #6888: Patch for UDP Netbufs to + support dest-addr and dest-port (optional: LWIP_NETBUF_RECVINFO) + + 2009-08-26 Simon Goldschmidt/Simon Kallweit + * slipif.c/.h: bug #26397: SLIP polling support + + 2009-08-25 Simon Goldschmidt + * opt.h, etharp.h/.c: task #9033: Support IEEE 802.1q tagged frame (VLAN), + New configuration options ETHARP_SUPPORT_VLAN and ETHARP_VLAN_CHECK. + + 2009-08-25 Simon Goldschmidt + * ip_addr.h, netdb.c: patch #6900: added define ip_ntoa(struct ip_addr*) + + 2009-08-24 Jakob Stoklund Olesen + * autoip.c, dhcp.c, netif.c: patch #6725: Teach AutoIP and DHCP to respond + to netif_set_link_up(). + + 2009-08-23 Simon Goldschmidt + * tcp.h/.c: Added function tcp_debug_state_str() to convert a tcp state + to a human-readable string. + + ++ Bugfixes: + + 2009-12-24: Kieran Mansley + * tcp_in.c Apply patches from Oleg Tyshev to improve OOS processing + (BUG#28241) + + 2009-12-06: Simon Goldschmidt + * ppp.h/.c: Fixed bug #27079 (Yet another leak in PPP): outpacket_buf can + be statically allocated (like in ucip) + + 2009-12-04: Simon Goldschmidt (patch by Ioardan Neshev) + * pap.c: patch #6969: PPP: missing PAP authentication UNTIMEOUT + + 2009-12-03: Simon Goldschmidt + * tcp.h, tcp_in.c, tcp_out.c: Fixed bug #28106: dup ack for fast retransmit + could have non-zero length + + 2009-12-02: Simon Goldschmidt + * tcp_in.c: Fixed bug #27904: TCP sends too many ACKs: delay resetting + tcp_input_pcb until after calling the pcb's callbacks + + 2009-11-29: Simon Goldschmidt + * tcp_in.c: Fixed bug #28054: Two segments with FIN flag on the out-of- + sequence queue, also fixed PBUF_POOL leak in the out-of-sequence code + + 2009-11-29: Simon Goldschmidt + * pbuf.c: Fixed bug #28064: pbuf_alloc(PBUF_POOL) is not thread-safe by + queueing a call into tcpip_thread to free ooseq-bufs if the pool is empty + + 2009-11-26: Simon Goldschmidt + * tcp.h: Fixed bug #28098: Nagle can prevent fast retransmit from sending + segment + + 2009-11-26: Simon Goldschmidt + * tcp.h, sockets.c: Fixed bug #28099: API required to disable Nagle + algorithm at PCB level + + 2009-11-22: Simon Goldschmidt + * tcp_out.c: Fixed bug #27905: FIN isn't combined with data on unsent + + 2009-11-22: Simon Goldschmidt (suggested by Bill Auerbach) + * tcp.c: tcp_alloc: prevent increasing stats.err for MEMP_TCP_PCB when + reusing time-wait pcb + + 2009-11-20: Simon Goldschmidt (patch by Albert Bartel) + * sockets.c: Fixed bug #28062: Data received directly after accepting + does not wake up select + + 2009-11-11: Simon Goldschmidt + * netdb.h: Fixed bug #27994: incorrect define for freeaddrinfo(addrinfo) + + 2009-10-30: Simon Goldschmidt + * opt.h: Increased default value for TCP_MSS to 536, updated default + value for TCP_WND to 4*TCP_MSS to keep delayed ACK working. + + 2009-10-28: Kieran Mansley + * tcp_in.c, tcp_out.c, tcp.h: re-work the fast retransmission code + to follow algorithm from TCP/IP Illustrated + + 2009-10-27: Kieran Mansley + * tcp_in.c: fix BUG#27445: grow cwnd with every duplicate ACK + + 2009-10-25: Simon Goldschmidt + * tcp.h: bug-fix in the TCP_EVENT_RECV macro (has to call tcp_recved if + pcb->recv is NULL to keep rcv_wnd correct) + + 2009-10-25: Simon Goldschmidt + * tcp_in.c: Fixed bug #26251: RST process in TIME_WAIT TCP state + + 2009-10-23: Simon Goldschmidt (David Empson) + * tcp.c: Fixed bug #27783: Silly window avoidance for small window sizes + + 2009-10-21: Simon Goldschmidt + * tcp_in.c: Fixed bug #27215: TCP sent() callback gives leading and + trailing 1 byte len (SYN/FIN) + + 2009-10-21: Simon Goldschmidt + * tcp_out.c: Fixed bug #27315: zero window probe and FIN + + 2009-10-19: Simon Goldschmidt + * dhcp.c/.h: Minor code simplification (don't store received pbuf, change + conditional code to assert where applicable), check pbuf length before + testing for valid reply + + 2009-10-19: Simon Goldschmidt + * dhcp.c: Removed most calls to udp_connect since they aren't necessary + when using udp_sendto_if() - always stay connected to IP_ADDR_ANY. + + 2009-10-16: Simon Goldschmidt + * ip.c: Fixed bug #27390: Source IP check in ip_input() causes it to drop + valid DHCP packets -> allow 0.0.0.0 as source address when LWIP_DHCP is + enabled + + 2009-10-15: Simon Goldschmidt (Oleg Tyshev) + * tcp_in.c: Fixed bug #27329: dupacks by unidirectional data transmit + + 2009-10-15: Simon Goldschmidt + * api_lib.c: Fixed bug #27709: conn->err race condition on netconn_recv() + timeout + + 2009-10-15: Simon Goldschmidt + * autoip.c: Fixed bug #27704: autoip starts with wrong address + LWIP_AUTOIP_CREATE_SEED_ADDR() returned address in host byte order instead + of network byte order + + 2009-10-11 Simon Goldschmidt (Jrg Kesten) + * tcp_out.c: Fixed bug #27504: tcp_enqueue wrongly concatenates segments + which are not consecutive when retransmitting unacked segments + + 2009-10-09 Simon Goldschmidt + * opt.h: Fixed default values of some stats to only be enabled if used + Fixes bug #27338: sys_stats is defined when NO_SYS = 1 + + 2009-08-30 Simon Goldschmidt + * ip.c: Fixed bug bug #27345: "ip_frag() does not use the LWIP_NETIF_LOOPBACK + function" by checking for loopback before calling ip_frag + + 2009-08-25 Simon Goldschmidt + * dhcp.c: fixed invalid dependency to etharp_query if DHCP_DOES_ARP_CHECK==0 + + 2009-08-23 Simon Goldschmidt + * ppp.c: bug #27078: Possible memory leak in pppInit() + + 2009-08-23 Simon Goldschmidt + * netdb.c, dns.c: bug #26657: DNS, if host name is "localhost", result + is error. + + 2009-08-23 Simon Goldschmidt + * opt.h, init.c: bug #26649: TCP fails when TCP_MSS > TCP_SND_BUF + Fixed wrong parenthesis, added check in init.c + + 2009-08-23 Simon Goldschmidt + * ppp.c: bug #27266: wait-state debug message in pppMain occurs every ms + + 2009-08-23 Simon Goldschmidt + * many ppp files: bug #27267: Added include to string.h where needed + + 2009-08-23 Simon Goldschmidt + * tcp.h: patch #6843: tcp.h macro optimization patch (for little endian) + + +(STABLE-1.3.1) + + ++ New features: + + 2009-05-10 Simon Goldschmidt + * opt.h, sockets.c, pbuf.c, netbuf.h, pbuf.h: task #7013: Added option + LWIP_NETIF_TX_SINGLE_PBUF to try to create transmit packets from only + one pbuf to help MACs that don't support scatter-gather DMA. + + 2009-05-09 Simon Goldschmidt + * icmp.h, icmp.c: Shrinked ICMP code, added option to NOT check icoming + ECHO pbuf for size (just use it): LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN + + 2009-05-05 Simon Goldschmidt, Jakob Stoklund Olesen + * ip.h, ip.c: Added ip_current_netif() & ip_current_header() to receive + extended info about the currently received packet. + + 2009-04-27 Simon Goldschmidt + * sys.h: Made SYS_LIGHTWEIGHT_PROT and sys_now() work with NO_SYS=1 + + 2009-04-25 Simon Goldschmidt + * mem.c, opt.h: Added option MEM_USE_POOLS_TRY_BIGGER_POOL to try the next + bigger malloc pool if one is empty (only usable with MEM_USE_POOLS). + + 2009-04-21 Simon Goldschmidt + * dns.c, init.c, dns.h, opt.h: task #7507, patch #6786: DNS supports static + hosts table. New configuration options DNS_LOCAL_HOSTLIST and + DNS_LOCAL_HOSTLIST_IS_DYNAMIC. Also, DNS_LOOKUP_LOCAL_EXTERN() can be defined + as an external function for lookup. + + 2009-04-15 Simon Goldschmidt + * dhcp.c: patch #6763: Global DHCP XID can be redefined to something more unique + + 2009-03-31 Kieran Mansley + * tcp.c, tcp_out.c, tcp_in.c, sys.h, tcp.h, opts.h: add support for + TCP timestamp options, off by default. Rework tcp_enqueue() to + take option flags rather than specified option data + + 2009-02-18 Simon Goldschmidt + * cc.h: Added printf formatter for size_t: SZT_F + + 2009-02-16 Simon Goldschmidt (patch by Rishi Khan) + * icmp.c, opt.h: patch #6539: (configurable) response to broadcast- and multicast + pings + + 2009-02-12 Simon Goldschmidt + * init.h: Added LWIP_VERSION to get the current version of the stack + + 2009-02-11 Simon Goldschmidt (suggested by Gottfried Spitaler) + * opt.h, memp.h/.c: added MEMP_MEM_MALLOC to use mem_malloc/mem_free instead + of the pool allocator (can save code size with MEM_LIBC_MALLOC if libc-malloc + is otherwise used) + + 2009-01-28 Jonathan Larmour (suggested by Bill Bauerbach) + * ipv4/inet_chksum.c, ipv4/lwip/inet_chksum.h: inet_chksum_pseudo_partial() + is only used by UDPLITE at present, so conditionalise it. + + 2008-12-03 Simon Goldschmidt (base on patch from Luca Ceresoli) + * autoip.c: checked in (slightly modified) patch #6683: Customizable AUTOIP + "seed" address. This should reduce AUTOIP conflicts if + LWIP_AUTOIP_CREATE_SEED_ADDR is overridden. + + 2008-10-02 Jonathan Larmour and Rishi Khan + * sockets.c (lwip_accept): Return EWOULDBLOCK if would block on non-blocking + socket. + + 2008-06-30 Simon Goldschmidt + * mem.c, opt.h, stats.h: fixed bug #21433: Calling mem_free/pbuf_free from + interrupt context isn't safe: LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT allows + mem_free to run between mem_malloc iterations. Added illegal counter for + mem stats. + + 2008-06-27 Simon Goldschmidt + * stats.h/.c, some other files: patch #6483: stats module improvement: + Added defines to display each module's statistic individually, added stats + defines for MEM, MEMP and SYS modules, removed (unused) rexmit counter. + + 2008-06-17 Simon Goldschmidt + * err.h: patch #6459: Made err_t overridable to use a more efficient type + (define LWIP_ERR_T in cc.h) + + 2008-06-17 Simon Goldschmidt + * slipif.c: patch #6480: Added a configuration option for slipif for symmetry + to loopif + + 2008-06-17 Simon Goldschmidt (patch by Luca Ceresoli) + * netif.c, loopif.c, ip.c, netif.h, loopif.h, opt.h: Checked in slightly + modified version of patch # 6370: Moved loopif code to netif.c so that + loopback traffic is supported on all netifs (all local IPs). + Added option to limit loopback packets for each netifs. + + + ++ Bugfixes: + 2009-08-12 Kieran Mansley + * tcp_in.c, tcp.c: Fix bug #27209: handle trimming of segments when + out of window or out of order properly + + 2009-08-12 Kieran Mansley + * tcp_in.c: Fix bug #27199: use snd_wl2 instead of snd_wl1 + + 2009-07-28 Simon Goldschmidt + * mem.h: Fixed bug #27105: "realloc() cannot replace mem_realloc()"s + + 2009-07-27 Kieran Mansley + * api.h api_msg.h netdb.h sockets.h: add missing #include directives + + 2009-07-09 Kieran Mansley + * api_msg.c, sockets.c, api.h: BUG23240 use signed counters for + recv_avail and don't increment counters until message successfully + sent to mbox + + 2009-06-25 Kieran Mansley + * api_msg.c api.h: BUG26722: initialise netconn write variables + in netconn_alloc + + 2009-06-25 Kieran Mansley + * tcp.h: BUG26879: set ret value in TCP_EVENT macros when function is not set + + 2009-06-25 Kieran Mansley + * tcp.c, tcp_in.c, tcp_out.c, tcp.h: BUG26301 and BUG26267: correct + simultaneous close behaviour, and make snd_nxt have the same meaning + as in the RFCs. + + 2009-05-12 Simon Goldschmidt + * etharp.h, etharp.c, netif.c: fixed bug #26507: "Gratuitous ARP depends on + arp_table / uses etharp_query" by adding etharp_gratuitous() + + 2009-05-12 Simon Goldschmidt + * ip.h, ip.c, igmp.c: bug #26487: Added ip_output_if_opt that can add IP options + to the IP header (used by igmp_ip_output_if) + + 2009-05-06 Simon Goldschmidt + * inet_chksum.c: On little endian architectures, use LWIP_PLATFORM_HTONS (if + defined) for SWAP_BYTES_IN_WORD to speed up checksumming. + + 2009-05-05 Simon Goldschmidt + * sockets.c: bug #26405: Prematurely released semaphore causes lwip_select() + to crash + + 2009-05-04 Simon Goldschmidt + * init.c: snmp was not initialized in lwip_init() + + 2009-05-04 Frdric Bernon + * dhcp.c, netbios.c: Changes if IP_SOF_BROADCAST is enabled. + + 2009-05-03 Simon Goldschmidt + * tcp.h: bug #26349: Nagle algorithm doesn't send although segment is full + (and unsent->next == NULL) + + 2009-05-02 Simon Goldschmidt + * tcpip.h, tcpip.c: fixed tcpip_untimeout (does not need the time, broken after + 1.3.0 in CVS only) - fixes compilation of ppp_oe.c + + 2009-05-02 Simon Goldschmidt + * msg_in.c: fixed bug #25636: SNMPSET value is ignored for integer fields + + 2009-05-01 Simon Goldschmidt + * pap.c: bug #21680: PPP upap_rauthnak() drops legal NAK packets + + 2009-05-01 Simon Goldschmidt + * ppp.c: bug #24228: Memory corruption with PPP and DHCP + + 2009-04-29 Frdric Bernon + * raw.c, udp.c, init.c, opt.h, ip.h, sockets.h: bug #26309: Implement the + SO(F)_BROADCAST filter for all API layers. Avoid the unindented reception + of broadcast packets even when this option wasn't set. Port maintainers + which want to enable this filter have to set IP_SOF_BROADCAST=1 in opt.h. + If you want this option also filter broadcast on recv operations, you also + have to set IP_SOF_BROADCAST_RECV=1 in opt.h. + + 2009-04-28 Simon Goldschmidt, Jakob Stoklund Olesen + * dhcp.c: patch #6721, bugs #25575, #25576: Some small fixes to DHCP and + DHCP/AUTOIP cooperation + + 2009-04-25 Simon Goldschmidt, Oleg Tyshev + * tcp_out.c: bug #24212: Deadlocked tcp_retransmit due to exceeded pcb->cwnd + Fixed by sorting the unsent and unacked queues (segments are inserted at the + right place in tcp_output and tcp_rexmit). + + 2009-04-25 Simon Goldschmidt + * memp.c, mem.c, memp.h, mem_std.h: bug #26213 "Problem with memory allocation + when debugging": memp_sizes contained the wrong sizes (including sanity + regions); memp pools for MEM_USE_POOLS were too small + + 2009-04-24 Simon Goldschmidt, Frdric Bernon + * inet.c: patch #6765: Fix a small problem with the last changes (incorrect + behavior, with with ip address string not ended by a '\0', a space or a + end of line) + + 2009-04-19 Simon Goldschmidt + * rawapi.txt: Fixed bug #26069: Corrected documentation: if tcp_connect fails, + pcb->err is called, not pcb->connected (with an error code). + + 2009-04-19 Simon Goldschmidt + * tcp_out.c: Fixed bug #26236: "TCP options (timestamp) don't work with + no-copy-tcpwrite": deallocate option data, only concat segments with same flags + + 2009-04-19 Simon Goldschmidt + * tcp_out.c: Fixed bug #25094: "Zero-length pbuf" (options are now allocated + in the header pbuf, not the data pbuf) + + 2009-04-18 Simon Goldschmidt + * api_msg.c: fixed bug #25695: Segmentation fault in do_writemore() + + 2009-04-15 Simon Goldschmidt + * sockets.c: tried to fix bug #23559: lwip_recvfrom problem with tcp + + 2009-04-15 Simon Goldschmidt + * dhcp.c: task #9192: mem_free of dhcp->options_in and dhcp->msg_in + + 2009-04-15 Simon Goldschmidt + * ip.c, ip6.c, tcp_out.c, ip.h: patch #6808: Add a utility function + ip_hinted_output() (for smaller code mainly) + + 2009-04-15 Simon Goldschmidt + * inet.c: patch #6765: Supporting new line characters in inet_aton() + + 2009-04-15 Simon Goldschmidt + * dhcp.c: patch #6764: DHCP rebind and renew did not send hostnam option; + Converted constant OPTION_MAX_MSG_SIZE to netif->mtu, check if netif->mtu + is big enough in dhcp_start + + 2009-04-15 Simon Goldschmidt + * netbuf.c: bug #26027: netbuf_chain resulted in pbuf memory leak + + 2009-04-15 Simon Goldschmidt + * sockets.c, ppp.c: bug #25763: corrected 4 occurrences of SMEMCPY to MEMCPY + + 2009-04-15 Simon Goldschmidt + * sockets.c: bug #26121: set_errno can be overridden + + 2009-04-09 Kieran Mansley (patch from Luca Ceresoli ) + * init.c, opt.h: Patch#6774 TCP_QUEUE_OOSEQ breaks compilation when + LWIP_TCP==0 + + 2009-04-09 Kieran Mansley (patch from Roy Lee ) + * tcp.h: Patch#6802 Add do-while-clauses to those function like + macros in tcp.h + + 2009-03-31 Kieran Mansley + * tcp.c, tcp_in.c, tcp_out.c, tcp.h, opt.h: Rework the way window + updates are calculated and sent (BUG20515) + + * tcp_in.c: cope with SYN packets received during established states, + and retransmission of initial SYN. + + * tcp_out.c: set push bit correctly when tcp segments are merged + + 2009-03-27 Kieran Mansley + * tcp_out.c set window correctly on probes (correcting change made + yesterday) + + 2009-03-26 Kieran Mansley + * tcp.c, tcp_in.c, tcp.h: add tcp_abandon() to cope with dropping + connections where no reset required (bug #25622) + + * tcp_out.c: set TCP_ACK flag on keepalive and zero window probes + (bug #20779) + + 2009-02-18 Simon Goldschmidt (Jonathan Larmour and Bill Auerbach) + * ip_frag.c: patch #6528: the buffer used for IP_FRAG_USES_STATIC_BUF could be + too small depending on MEM_ALIGNMENT + + 2009-02-16 Simon Goldschmidt + * sockets.h/.c, api_*.h/.c: fixed arguments of socket functions to match the standard; + converted size argument of netconn_write to 'size_t' + + 2009-02-16 Simon Goldschmidt + * tcp.h, tcp.c: fixed bug #24440: TCP connection close problem on 64-bit host + by moving accept callback function pointer to TCP_PCB_COMMON + + 2009-02-12 Simon Goldschmidt + * dhcp.c: fixed bug #25345 (DHCPDECLINE is sent with "Maximum message size" + option) + + 2009-02-11 Simon Goldschmidt + * dhcp.c: fixed bug #24480 (releasing old udp_pdb and pbuf in dhcp_start) + + 2009-02-11 Simon Goldschmidt + * opt.h, api_msg.c: added configurable default valud for netconn->recv_bufsize: + RECV_BUFSIZE_DEFAULT (fixes bug #23726: pbuf pool exhaustion on slow recv()) + + 2009-02-10 Simon Goldschmidt + * tcp.c: fixed bug #25467: Listen backlog is not reset on timeout in SYN_RCVD: + Accepts_pending is decrease on a corresponding listen pcb when a connection + in state SYN_RCVD is close. + + 2009-01-28 Jonathan Larmour + * pbuf.c: reclaim pbufs from TCP out-of-sequence segments if we run + out of pool pbufs. + + 2008-12-19 Simon Goldschmidt + * many files: patch #6699: fixed some warnings on platform where sizeof(int) == 2 + + 2008-12-10 Tamas Somogyi, Frdric Bernon + * sockets.c: fixed bug #25051: lwip_recvfrom problem with udp: fromaddr and + port uses deleted netbuf. + + 2008-10-18 Simon Goldschmidt + * tcp_in.c: fixed bug ##24596: Vulnerability on faulty TCP options length + in tcp_parseopt + + 2008-10-15 Simon Goldschmidt + * ip_frag.c: fixed bug #24517: IP reassembly crashes on unaligned IP headers + by packing the struct ip_reass_helper. + + 2008-10-03 David Woodhouse, Jonathan Larmour + * etharp.c (etharp_arp_input): Fix type aliasing problem copying ip address. + + 2008-10-02 Jonathan Larmour + * dns.c: Hard-code structure sizes, to avoid issues on some compilers where + padding is included. + + 2008-09-30 Jonathan Larmour + * sockets.c (lwip_accept): check addr isn't NULL. If it's valid, do an + assertion check that addrlen isn't NULL. + + 2008-09-30 Jonathan Larmour + * tcp.c: Fix bug #24227, wrong error message in tcp_bind. + + 2008-08-26 Simon Goldschmidt + * inet.h, ip_addr.h: fixed bug #24132: Cross-dependency between ip_addr.h and + inet.h -> moved declaration of struct in_addr from ip_addr.h to inet.h + + 2008-08-14 Simon Goldschmidt + * api_msg.c: fixed bug #23847: do_close_internal references freed memory (when + tcp_close returns != ERR_OK) + + 2008-07-08 Frdric Bernon + * stats.h: Fix some build bugs introduced with patch #6483 (missing some parameters + in macros, mainly if MEM_STATS=0 and MEMP_STATS=0). + + 2008-06-24 Jonathan Larmour + * tcp_in.c: Fix for bug #23693 as suggested by Art R. Ensure cseg is unused + if tcp_seg_copy fails. + + 2008-06-17 Simon Goldschmidt + * inet_chksum.c: Checked in some ideas of patch #6460 (loop optimizations) + and created defines for swapping bytes and folding u32 to u16. + + 2008-05-30 Kieran Mansley + * tcp_in.c Remove redundant "if" statement, and use real rcv_wnd + rather than rcv_ann_wnd when deciding if packets are in-window. + Contributed by + + 2008-05-30 Kieran Mansley + * mem.h: Fix BUG#23254. Change macro definition of mem_* to allow + passing as function pointers when MEM_LIBC_MALLOC is defined. + + 2008-05-09 Jonathan Larmour + * err.h, err.c, sockets.c: Fix bug #23119: Reorder timeout error code to + stop it being treated as a fatal error. + + 2008-04-15 Simon Goldschmidt + * dhcp.c: fixed bug #22804: dhcp_stop doesn't clear NETIF_FLAG_DHCP + (flag now cleared) + + 2008-03-27 Simon Goldschmidt + * mem.c, tcpip.c, tcpip.h, opt.h: fixed bug #21433 (Calling mem_free/pbuf_free + from interrupt context isn't safe): set LWIP_USE_HEAP_FROM_INTERRUPT to 1 + in lwipopts.h or use pbuf_free_callback(p)/mem_free_callback(m) to free pbufs + or heap memory from interrupt context + + 2008-03-26 Simon Goldschmidt + * tcp_in.c, tcp.c: fixed bug #22249: division by zero could occur if a remote + host sent a zero mss as TCP option. + + +(STABLE-1.3.0) + + ++ New features: + + 2008-03-10 Jonathan Larmour + * inet_chksum.c: Allow choice of one of the sample algorithms to be + made from lwipopts.h. Fix comment on how to override LWIP_CHKSUM. + + 2008-01-22 Frdric Bernon + * tcp.c, tcp_in.c, tcp.h, opt.h: Rename LWIP_CALCULATE_EFF_SEND_MSS in + TCP_CALCULATE_EFF_SEND_MSS to have coherent TCP options names. + + 2008-01-14 Frdric Bernon + * rawapi.txt, api_msg.c, tcp.c, tcp_in.c, tcp.h: changes for task #7675 "Enable + to refuse data on a TCP_EVENT_RECV call". Important, behavior changes for the + tcp_recv callback (see rawapi.txt). + + 2008-01-14 Frdric Bernon, Marc Chaland + * ip.c: Integrate patch #6369" ip_input : checking before realloc". + + 2008-01-12 Frdric Bernon + * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field + netconn::sem per netconn::op_completed like suggested for the task #7490 + "Add return value to sys_mbox_post". + + 2008-01-12 Frdric Bernon + * api_msg.c, opt.h: replace DEFAULT_RECVMBOX_SIZE per DEFAULT_TCP_RECVMBOX_SIZE, + DEFAULT_UDP_RECVMBOX_SIZE and DEFAULT_RAW_RECVMBOX_SIZE (to optimize queues + sizes), like suggested for the task #7490 "Add return value to sys_mbox_post". + + 2008-01-10 Frdric Bernon + * tcpip.h, tcpip.c: add tcpip_callback_with_block function for the task #7490 + "Add return value to sys_mbox_post". tcpip_callback is always defined as + "blocking" ("block" parameter = 1). + + 2008-01-10 Frdric Bernon + * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field + netconn::mbox (sys_mbox_t) per netconn::sem (sys_sem_t) for the task #7490 + "Add return value to sys_mbox_post". + + 2008-01-05 Frdric Bernon + * sys_arch.txt, api.h, api_lib.c, api_msg.h, api_msg.c, tcpip.c, sys.h, opt.h: + Introduce changes for task #7490 "Add return value to sys_mbox_post" with some + modifications in the sys_mbox api: sys_mbox_new take a "size" parameters which + indicate the number of pointers query by the mailbox. There is three defines + in opt.h to indicate sizes for tcpip::mbox, netconn::recvmbox, and for the + netconn::acceptmbox. Port maintainers, you can decide to just add this new + parameter in your implementation, but to ignore it to keep the previous behavior. + The new sys_mbox_trypost function return a value to know if the mailbox is + full or if the message is posted. Take a look to sys_arch.txt for more details. + This new function is used in tcpip_input (so, can be called in an interrupt + context since the function is not blocking), and in recv_udp and recv_raw. + + 2008-01-04 Frdric Bernon, Simon Goldschmidt, Jonathan Larmour + * rawapi.txt, api.h, api_lib.c, api_msg.h, api_msg.c, sockets.c, tcp.h, tcp.c, + tcp_in.c, init.c, opt.h: rename backlog options with TCP_ prefix, limit the + "backlog" parameter in an u8_t, 0 is interpreted as "smallest queue", add + documentation in the rawapi.txt file. + + 2007-12-31 Kieran Mansley (based on patch from Per-Henrik Lundbolm) + * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Add TCP persist timer + + 2007-12-31 Frdric Bernon, Luca Ceresoli + * autoip.c, etharp.c: ip_addr.h: Integrate patch #6348: "Broadcast ARP packets + in autoip". The change in etharp_raw could be removed, since all calls to + etharp_raw use ethbroadcast for the "ethdst_addr" parameter. But it could be + wrong in the future. + + 2007-12-30 Frdric Bernon, Tom Evans + * ip.c: Fix bug #21846 "LwIP doesn't appear to perform any IP Source Address + Filtering" reported by Tom Evans. + + 2007-12-21 Frdric Bernon, Simon Goldschmidt, Jonathan Larmour + * tcp.h, opt.h, api.h, api_msg.h, tcp.c, tcp_in.c, api_lib.c, api_msg.c, + sockets.c, init.c: task #7252: Implement TCP listen backlog: Warning: raw API + applications have to call 'tcp_accepted(pcb)' in their accept callback to + keep accepting new connections. + + 2007-12-13 Frdric Bernon + * api_msg.c, err.h, err.c, sockets.c, dns.c, dns.h: replace "enum dns_result" + by err_t type. Add a new err_t code "ERR_INPROGRESS". + + 2007-12-12 Frdric Bernon + * dns.h, dns.c, opt.h: move DNS options to the "right" place. Most visibles + are the one which have ram usage. + + 2007-12-05 Frdric Bernon + * netdb.c: add a LWIP_DNS_API_HOSTENT_STORAGE option to decide to use a static + set of variables (=0) or a local one (=1). In this last case, your port should + provide a function "struct hostent* sys_thread_hostent( struct hostent* h)" + which have to do a copy of "h" and return a pointer ont the "per-thread" copy. + + 2007-12-03 Simon Goldschmidt + * ip.c: ip_input: check if a packet is for inp first before checking all other + netifs on netif_list (speeds up packet receiving in most cases) + + 2007-11-30 Simon Goldschmidt + * udp.c, raw.c: task #7497: Sort lists (pcb, netif, ...) for faster access + UDP: move a (connected) pcb selected for input to the front of the list of + pcbs so that it is found faster next time. Same for RAW pcbs that have eaten + a packet. + + 2007-11-28 Simon Goldschmidt + * etharp.c, stats.c, stats.h, opt.h: Introduced ETHARP_STATS + + 2007-11-25 Simon Goldschmidt + * dhcp.c: dhcp_unfold_reply() uses pbuf_copy_partial instead of its own copy + algorithm. + + 2007-11-24 Simon Goldschmidt + * netdb.h, netdb.c, sockets.h/.c: Moved lwip_gethostbyname from sockets.c + to the new file netdb.c; included lwip_getaddrinfo. + + 2007-11-21 Simon Goldschmidt + * tcp.h, opt.h, tcp.c, tcp_in.c: implemented calculating the effective send-mss + based on the MTU of the netif used to send. Enabled by default. Disable by + setting LWIP_CALCULATE_EFF_SEND_MSS to 0. This fixes bug #21492. + + 2007-11-19 Frdric Bernon + * api_msg.c, dns.h, dns.c: Implement DNS_DOES_NAME_CHECK option (check if name + received match the name query), implement DNS_USES_STATIC_BUF (the place where + copy dns payload to parse the response), return an error if there is no place + for a new query, and fix some minor problems. + + 2007-11-16 Simon Goldschmidt + * new files: ipv4/inet.c, ipv4/inet_chksum.c, ipv6/inet6.c + removed files: core/inet.c, core/inet6.c + Moved inet files into ipv4/ipv6 directory; splitted inet.c/inet.h into + inet and chksum part; changed includes in all lwIP files as appropriate + + 2007-11-16 Simon Goldschmidt + * api.h, api_msg.h, api_lib.c, api_msg.c, socket.h, socket.c: Added sequential + dns resolver function for netconn api (netconn_gethostbyname) and socket api + (gethostbyname/gethostbyname_r). + + 2007-11-15 Jim Pettinato, Frdric Bernon + * opt.h, init.c, tcpip.c, dhcp.c, dns.h, dns.c: add DNS client for simple name + requests with RAW api interface. Initialization is done in lwip_init() with + build time options. DNS timer is added in tcpip_thread context. DHCP can set + DNS server ip addresses when options are received. You need to set LWIP_DNS=1 + in your lwipopts.h file (LWIP_DNS=0 in opt.h). DNS_DEBUG can be set to get + some traces with LWIP_DEBUGF. Sanity check have been added. There is a "todo" + list with points to improve. + + 2007-11-06 Simon Goldschmidt + * opt.h, mib2.c: Patch #6215: added ifAdminStatus write support (if explicitly + enabled by defining SNMP_SAFE_REQUESTS to 0); added code to check link status + for ifOperStatus if LWIP_NETIF_LINK_CALLBACK is defined. + + 2007-11-06 Simon Goldschmidt + * api.h, api_msg.h and dependent files: Task #7410: Removed the need to include + core header files in api.h (ip/tcp/udp/raw.h) to hide the internal + implementation from netconn api applications. + + 2007-11-03 Frdric Bernon + * api.h, api_lib.c, api_msg.c, sockets.c, opt.h: add SO_RCVBUF option for UDP & + RAW netconn. You need to set LWIP_SO_RCVBUF=1 in your lwipopts.h (it's disabled + by default). Netconn API users can use the netconn_recv_bufsize macro to access + it. This is a first release which have to be improve for TCP. Note it used the + netconn::recv_avail which need to be more "thread-safe" (note there is already + the problem for FIONREAD with lwip_ioctl/ioctlsocket). + + 2007-11-01 Frdric Bernon, Marc Chaland + * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, tcp.h, tcp_out.c: + Integrate "patch #6250 : MSG_MORE flag for send". MSG_MORE is used at socket api + layer, NETCONN_MORE at netconn api layer, and TCP_WRITE_FLAG_MORE at raw api + layer. This option enable to delayed TCP PUSH flag on multiple "write" calls. + Note that previous "copy" parameter for "write" APIs is now called "apiflags". + + 2007-10-24 Frdric Bernon + * api.h, api_lib.c, api_msg.c: Add macro API_EVENT in the same spirit than + TCP_EVENT_xxx macros to get a code more readable. It could also help to remove + some code (like we have talk in "patch #5919 : Create compile switch to remove + select code"), but it could be done later. + + 2007-10-08 Simon Goldschmidt + * many files: Changed initialization: many init functions are not needed any + more since we now rely on the compiler initializing global and static + variables to zero! + + 2007-10-06 Simon Goldschmidt + * ip_frag.c, memp.c, mib2.c, ip_frag.h, memp_std.h, opt.h: Changed IP_REASSEMBLY + to enqueue the received pbufs so that multiple packets can be reassembled + simultaneously and no static reassembly buffer is needed. + + 2007-10-05 Simon Goldschmidt + * tcpip.c, etharp.h, etharp.c: moved ethernet_input from tcpip.c to etharp.c so + all netifs (or ports) can use it. + + 2007-10-05 Frdric Bernon + * netifapi.h, netifapi.c: add function netifapi_netif_set_default. Change the + common function to reduce a little bit the footprint (for all functions using + only the "netif" parameter). + + 2007-10-03 Frdric Bernon + * netifapi.h, netifapi.c: add functions netifapi_netif_set_up, netifapi_netif_set_down, + netifapi_autoip_start and netifapi_autoip_stop. Use a common function to reduce + a little bit the footprint (for all functions using only the "netif" parameter). + + 2007-09-15 Frdric Bernon + * udp.h, udp.c, sockets.c: Changes for "#20503 IGMP Improvement". Add IP_MULTICAST_IF + option in socket API, and a new field "multicast_ip" in "struct udp_pcb" (for + netconn and raw API users), only if LWIP_IGMP=1. Add getsockopt processing for + IP_MULTICAST_TTL and IP_MULTICAST_IF. + + 2007-09-10 Frdric Bernon + * snmp.h, mib2.c: enable to remove SNMP timer (which consumne several cycles + even when it's not necessary). snmp_agent.txt tell to call snmp_inc_sysuptime() + each 10ms (but, it's intrusive if you use sys_timeout feature). Now, you can + decide to call snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but + call to a lower frequency). Or, you can decide to not call snmp_inc_sysuptime() + or snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro. + This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside + snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only + when it's queried (any direct call to "sysuptime" is changed by a call to + snmp_get_sysuptime). + + 2007-09-09 Frdric Bernon, Bill Florac + * igmp.h, igmp.c, netif.h, netif.c, ip.c: To enable to have interfaces with IGMP, + and others without it, there is a new NETIF_FLAG_IGMP flag to set in netif->flags + if you want IGMP on an interface. igmp_stop() is now called inside netif_remove(). + igmp_report_groups() is now called inside netif_set_link_up() (need to have + LWIP_NETIF_LINK_CALLBACK=1) to resend reports once the link is up (avoid to wait + the next query message to receive the matching multicast streams). + + 2007-09-08 Frdric Bernon + * sockets.c, ip.h, api.h, tcp.h: declare a "struct ip_pcb" which only contains + IP_PCB. Add in the netconn's "pcb" union a "struct ip_pcb *ip;" (no size change). + Use this new field to access to common pcb fields (ttl, tos, so_options, etc...). + Enable to access to these fields with LWIP_TCP=0. + + 2007-09-05 Frdric Bernon + * udp.c, ipv4/icmp.c, ipv4/ip.c, ipv6/icmp.c, ipv6/ip6.c, ipv4/icmp.h, + ipv6/icmp.h, opt.h: Integrate "task #7272 : LWIP_ICMP option". The new option + LWIP_ICMP enable/disable ICMP module inside the IP stack (enable per default). + Be careful, disabling ICMP make your product non-compliant to RFC1122, but + help to reduce footprint, and to reduce "visibility" on the Internet. + + 2007-09-05 Frdric Bernon, Bill Florac + * opt.h, sys.h, tcpip.c, slipif.c, ppp.c, sys_arch.txt: Change parameters list + for sys_thread_new (see "task #7252 : Create sys_thread_new_ex()"). Two new + parameters have to be provided: a task name, and a task stack size. For this + one, since it's platform dependant, you could define the best one for you in + your lwipopts.h. For port maintainers, you can just add these new parameters + in your sys_arch.c file, and but it's not mandatory, use them in your OS + specific functions. + + 2007-09-05 Frdric Bernon + * inet.c, autoip.c, msg_in.c, msg_out.c, init.c: Move some build time checkings + inside init.c for task #7142 "Sanity check user-configurable values". + + 2007-09-04 Frdric Bernon, Bill Florac + * igmp.h, igmp.c, memp_std.h, memp.c, init.c, opt.h: Replace mem_malloc call by + memp_malloc, and use a new MEMP_NUM_IGMP_GROUP option (see opt.h to define the + value). It will avoid potential fragmentation problems, use a counter to know + how many times a group is used on an netif, and free it when all applications + leave it. MEMP_NUM_IGMP_GROUP got 8 as default value (and init.c got a sanity + check if LWIP_IGMP!=0). + + 2007-09-03 Frdric Bernon + * igmp.h, igmp.c, sockets.c, api_msg.c: Changes for "#20503 IGMP Improvement". + Initialize igmp_mac_filter to NULL in netif_add (this field should be set in + the netif's "init" function). Use the "imr_interface" field (for socket layer) + and/or the "interface" field (for netconn layer), for join/leave operations. + The igmp_join/leavegroup first parameter change from a netif to an ipaddr. + This field could be a netif's ipaddr, or "any" (same meaning than ip_addr_isany). + + 2007-08-30 Frdric Bernon + * Add netbuf.h, netbuf.c, Change api.h, api_lib.c: #7249 "Split netbuf functions + from api/api_lib". Now netbuf API is independant of netconn, and can be used + with other API (application based on raw API, or future "socket2" API). Ports + maintainers just have to add src/api/netbuf.c in their makefile/projects. + + 2007-08-30 Frdric Bernon, Jonathan Larmour + * init.c: Add first version of lwip_sanity_check for task #7142 "Sanity check + user-configurable values". + + 2007-08-29 Frdric Bernon + * igmp.h, igmp.c, tcpip.c, init.c, netif.c: change igmp_init and add igmp_start. + igmp_start is call inside netif_add. Now, igmp initialization is in the same + spirit than the others modules. Modify some IGMP debug traces. + + 2007-08-29 Frdric Bernon + * Add init.h, init.c, Change opt.h, tcpip.c: Task #7213 "Add a lwip_init function" + Add lwip_init function to regroup all modules initializations, and to provide + a place to add code for task #7142 "Sanity check user-configurable values". + Ports maintainers should remove direct initializations calls from their code, + and add init.c in their makefiles. Note that lwip_init() function is called + inside tcpip_init, but can also be used by raw api users since all calls are + disabled when matching options are disabled. Also note that their is new options + in opt.h, you should configure in your lwipopts.h (they are enabled per default). + + 2007-08-26 Marc Boucher + * api_msg.c: do_close_internal(): Reset the callbacks and arg (conn) to NULL + since they can under certain circumstances be called with an invalid conn + pointer after the connection has been closed (and conn has been freed). + + 2007-08-25 Frdric Bernon (Artem Migaev's Patch) + * netif.h, netif.c: Integrate "patch #6163 : Function to check if link layer is up". + Add a netif_is_link_up() function if LWIP_NETIF_LINK_CALLBACK option is set. + + 2007-08-22 Frdric Bernon + * netif.h, netif.c, opt.h: Rename LWIP_NETIF_CALLBACK in LWIP_NETIF_STATUS_CALLBACK + to be coherent with new LWIP_NETIF_LINK_CALLBACK option before next release. + + 2007-08-22 Frdric Bernon + * tcpip.h, tcpip.c, ethernetif.c, opt.h: remove options ETHARP_TCPIP_INPUT & + ETHARP_TCPIP_ETHINPUT, now, only "ethinput" code is supported, even if the + name is tcpip_input (we keep the name of 1.2.0 function). + + 2007-08-17 Jared Grubb + * memp_std.h, memp.h, memp.c, mem.c, stats.c: (Task #7136) Centralize mempool + settings into new memp_std.h and optional user file lwippools.h. This adds + more dynamic mempools, and allows the user to create an arbitrary number of + mempools for mem_malloc. + + 2007-08-16 Marc Boucher + * api_msg.c: Initialize newconn->state to NETCONN_NONE in accept_function; + otherwise it was left to NETCONN_CLOSE and sent_tcp() could prematurely + close the connection. + + 2007-08-16 Marc Boucher + * sockets.c: lwip_accept(): check netconn_peer() error return. + + 2007-08-16 Marc Boucher + * mem.c, mem.h: Added mem_calloc(). + + 2007-08-16 Marc Boucher + * tcpip.c, tcpip.h memp.c, memp.h: Added distinct memp (MEMP_TCPIP_MSG_INPKT) + for input packets to prevent floods from consuming all of MEMP_TCPIP_MSG + and starving other message types. + Renamed MEMP_TCPIP_MSG to MEMP_TCPIP_MSG_API + + 2007-08-16 Marc Boucher + * pbuf.c, pbuf.h, etharp.c, tcp_in.c, sockets.c: Split pbuf flags in pbuf + type and flgs (later renamed to flags). + Use enum pbuf_flag as pbuf_type. Renumber PBUF_FLAG_*. + Improved lwip_recvfrom(). TCP push now propagated. + + 2007-08-16 Marc Boucher + * ethernetif.c, contrib/ports/various: ethbroadcast now a shared global + provided by etharp. + + 2007-08-16 Marc Boucher + * ppp_oe.c ppp_oe.h, auth.c chap.c fsm.c lcp.c ppp.c ppp.h, + etharp.c ethernetif.c, etharp.h, opt.h tcpip.h, tcpip.c: + Added PPPoE support and various PPP improvements. + + 2007-07-25 Simon Goldschmidt + * api_lib.c, ip_frag.c, pbuf.c, api.h, pbuf.h: Introduced pbuf_copy_partial, + making netbuf_copy_partial use this function. + + 2007-07-25 Simon Goldschmidt + * tcp_in.c: Fix bug #20506: Slow start / initial congestion window starts with + 2 * mss (instead of 1 * mss previously) to comply with some newer RFCs and + other stacks. + + 2007-07-13 Jared Grubb (integrated by Frdric Bernon) + * opt.h, netif.h, netif.c, ethernetif.c: Add new configuration option to add + a link callback in the netif struct, and functions to handle it. Be carefull + for port maintainers to add the NETIF_FLAG_LINK_UP flag (like in ethernetif.c) + if you want to be sure to be compatible with future changes... + + 2007-06-30 Frdric Bernon + * sockets.h, sockets.c: Implement MSG_PEEK flag for recv/recvfrom functions. + + 2007-06-21 Simon Goldschmidt + * etharp.h, etharp.c: Combined etharp_request with etharp_raw for both + LWIP_AUTOIP =0 and =1 to remove redundant code. + + 2007-06-21 Simon Goldschmidt + * mem.c, memp.c, mem.h, memp.h, opt.h: task #6863: Introduced the option + MEM_USE_POOLS to use 4 pools with different sized elements instead of a + heap. This both prevents memory fragmentation and gives a higher speed + at the cost of more memory consumption. Turned off by default. + + 2007-06-21 Simon Goldschmidt + * api_lib.c, api_msg.c, api.h, api_msg.h: Converted the length argument of + netconn_write (and therefore also api_msg_msg.msg.w.len) from u16_t into + int to be able to send a bigger buffer than 64K with one time (mainly + used from lwip_send). + + 2007-06-21 Simon Goldschmidt + * tcp.h, api_msg.c: Moved the nagle algorithm from netconn_write/do_write + into a define (tcp_output_nagle) in tcp.h to provide it to raw api users, too. + + 2007-06-21 Simon Goldschmidt + * api.h, api_lib.c, api_msg.c: Fixed bug #20021: Moved sendbuf-processing in + netconn_write from api_lib.c to api_msg.c to also prevent multiple context- + changes on low memory or empty send-buffer. + + 2007-06-18 Simon Goldschmidt + * etharp.c, etharp.h: Changed etharp to use a defined hardware address length + of 6 to avoid loading netif->hwaddr_len every time (since this file is only + used for ethernet and struct eth_addr already had a defined length of 6). + + 2007-06-17 Simon Goldschmidt + * sockets.c, sockets.h: Implemented socket options SO_NO_CHECK for UDP sockets + to disable UDP checksum generation on transmit. + + 2007-06-13 Frdric Bernon, Simon Goldschmidt + * debug.h, api_msg.c: change LWIP_ERROR to use it to check errors like invalid + pointers or parameters, and let the possibility to redefined it in cc.h. Use + this macro to check "conn" parameter in api_msg.c functions. + + 2007-06-11 Simon Goldschmidt + * sockets.c, sockets.h: Added UDP lite support for sockets + + 2007-06-10 Simon Goldschmidt + * udp.h, opt.h, api_msg.c, ip.c, udp.c: Included switch LWIP_UDPLITE (enabled + by default) to switch off UDP-Lite support if not needed (reduces udp.c code + size) + + 2007-06-09 Dominik Spies (integrated by Frdric Bernon) + * autoip.h, autoip.c, dhcp.h, dhcp.c, netif.h, netif.c, etharp.h, etharp.c, opt.h: + AutoIP implementation available for IPv4, with new options LWIP_AUTOIP and + LWIP_DHCP_AUTOIP_COOP if you want to cooperate with DHCP. Some tips to adapt + (see TODO mark in the source code). + + 2007-06-09 Simon Goldschmidt + * etharp.h, etharp.c, ethernetif.c: Modified order of parameters for + etharp_output() to match netif->output so etharp_output() can be used + directly as netif->output to save one function call. + + 2007-06-08 Simon Goldschmidt + * netif.h, ethernetif.c, slipif.c, loopif.c: Added define + NETIF_INIT_SNMP(netif, type, speed) to initialize per-netif snmp variables, + added initialization of those to ethernetif, slipif and loopif. + + 2007-05-18 Simon Goldschmidt + * opt.h, ip_frag.c, ip_frag.h, ip.c: Added option IP_FRAG_USES_STATIC_BUF + (defaulting to off for now) that can be set to 0 to send fragmented + packets by passing PBUF_REFs down the stack. + + 2007-05-23 Frdric Bernon + * api_lib.c: Implement SO_RCVTIMEO for accept and recv on TCP + connections, such present in patch #5959. + + 2007-05-23 Frdric Bernon + * api.h, api_lib.c, api_msg.c, sockets.c: group the different NETCONN_UDPxxx + code in only one part... + + 2007-05-18 Simon Goldschmidt + * opt.h, memp.h, memp.c: Added option MEMP_OVERFLOW_CHECK to check for memp + elements to overflow. This is achieved by adding some bytes before and after + each pool element (increasing their size, of course), filling them with a + prominent value and checking them on freeing the element. + Set it to 2 to also check every element in every pool each time memp_malloc() + or memp_free() is called (slower but more helpful). + + 2007-05-10 Simon Goldschmidt + * opt.h, memp.h, memp.c, pbuf.c (see task #6831): use a new memp pool for + PBUF_POOL pbufs instead of the old pool implementation in pbuf.c to reduce + code size. + + 2007-05-11 Frdric Bernon + * sockets.c, api_lib.c, api_msg.h, api_msg.c, netifapi.h, netifapi.c, tcpip.c: + Include a function pointer instead of a table index in the message to reduce + footprint. Disable some part of lwip_send and lwip_sendto if some options are + not set (LWIP_TCP, LWIP_UDP, LWIP_RAW). + + 2007-05-10 Simon Goldschmidt + * *.h (except netif/ppp/*.h): Included patch #5448: include '#ifdef __cplusplus + \ extern "C" {' in all header files. Now you can write your application using + the lwIP stack in C++ and simply #include the core files. Note I have left + out the netif/ppp/*h header files for now, since I don't know which files are + included by applications and which are for internal use only. + + 2007-05-09 Simon Goldschmidt + * opt.h, *.c/*.h: Included patch #5920: Create define to override C-library + memcpy. 2 Defines are created: MEMCPY() for normal memcpy, SMEMCPY() for + situations where some compilers might inline the copy and save a function + call. Also replaced all calls to memcpy() with calls to (S)MEMCPY(). + + 2007-05-08 Simon Goldschmidt + * mem.h: If MEM_LIBC_MALLOC==1, allow the defines (e.g. mem_malloc() -> malloc()) + to be overriden in case the C-library malloc implementation is not protected + against concurrent access. + + 2007-05-04 Simon Goldschmidt (Atte Kojo) + * etharp.c: Introduced fast one-entry-cache to speed up ARP lookup when sending + multiple packets to the same host. + + 2007-05-04 Frdric Bernon, Jonathan Larmour + * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fix bug #19162 "lwip_sento: a possible + to corrupt remote addr/port connection state". Reduce problems "not enought memory" with + netbuf (if we receive lot of datagrams). Improve lwip_sendto (only one exchange between + sockets api and api_msg which run in tcpip_thread context). Add netconn_sento function. + Warning, if you directly access to "fromaddr" & "fromport" field from netbuf struct, + these fields are now renamed "addr" & "port". + + 2007-04-11 Jonathan Larmour + * sys.h, api_lib.c: Provide new sys_mbox_tryfetch function. Require ports to provide new + sys_arch_mbox_tryfetch function to get a message if one is there, otherwise return + with SYS_MBOX_EMPTY. sys_arch_mbox_tryfetch can be implemented as a function-like macro + by the port in sys_arch.h if desired. + + 2007-04-06 Frdric Bernon, Simon Goldschmidt + * opt.h, tcpip.h, tcpip.c, netifapi.h, netifapi.c: New configuration option LWIP_NETIF_API + allow to use thread-safe functions to add/remove netif in list, and to start/stop dhcp + clients, using new functions from netifapi.h. Disable as default (no port change to do). + + 2007-04-05 Frdric Bernon + * sockets.c: remplace ENOBUFS errors on alloc_socket by ENFILE to be more BSD compliant. + + 2007-04-04 Simon Goldschmidt + * arch.h, api_msg.c, dhcp.c, msg_in.c, sockets.c: Introduced #define LWIP_UNUSED_ARG(x) + use this for and architecture-independent form to tell the compiler you intentionally + are not using this variable. Can be overriden in cc.h. + + 2007-03-28 Frdric Bernon + * opt.h, netif.h, dhcp.h, dhcp.c: New configuration option LWIP_NETIF_HOSTNAME allow to + define a hostname in netif struct (this is just a pointer, so, you can use a hardcoded + string, point on one of your's ethernetif field, or alloc a string you will free yourself). + It will be used by DHCP to register a client hostname, but can also be use when you call + snmp_set_sysname. + + 2007-03-28 Frdric Bernon + * netif.h, netif.c: A new NETIF_FLAG_ETHARP flag is defined in netif.h, to allow to + initialize a network interface's flag with. It tell this interface is an ethernet + device, and we can use ARP with it to do a "gratuitous ARP" (RFC 3220 "IP Mobility + Support for IPv4" section 4.6) when interface is "up" with netif_set_up(). + + 2007-03-26 Frdric Bernon, Jonathan Larmour + * opt.h, tcpip.c: New configuration option LWIP_ARP allow to disable ARP init at build + time if you only use PPP or SLIP. The default is enable. Note we don't have to call + etharp_init in your port's initilization sequence if you use tcpip.c, because this call + is done in tcpip_init function. + + 2007-03-22 Frdric Bernon + * stats.h, stats.c, msg_in.c: Stats counters can be change to u32_t if necessary with the + new option LWIP_STATS_LARGE. If you need this option, define LWIP_STATS_LARGE to 1 in + your lwipopts.h. More, unused counters are not defined in the stats structs, and not + display by stats_display(). Note that some options (SYS_STATS and RAW_STATS) are defined + but never used. Fix msg_in.c with the correct #if test for a stat display. + + 2007-03-21 Kieran Mansley + * netif.c, netif.h: Apply patch#4197 with some changes (originator: rireland@hmgsl.com). + Provides callback on netif up/down state change. + + 2007-03-11 Frdric Bernon, Mace Gael, Steve Reynolds + * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, igmp.h, igmp.c, + ip.c, netif.h, tcpip.c, opt.h: + New configuration option LWIP_IGMP to enable IGMP processing. Based on only one + filter per all network interfaces. Declare a new function in netif to enable to + control the MAC filter (to reduce lwIP traffic processing). + + 2007-03-11 Frdric Bernon + * tcp.h, tcp.c, sockets.c, tcp_out.c, tcp_in.c, opt.h: Keepalive values can + be configured at run time with LWIP_TCP_KEEPALIVE, but don't change this + unless you know what you're doing (default are RFC1122 compliant). Note + that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set in seconds. + + 2007-03-08 Frdric Bernon + * tcp.h: Keepalive values can be configured at compile time, but don't change + this unless you know what you're doing (default are RFC1122 compliant). + + 2007-03-08 Frdric Bernon + * sockets.c, api.h, api_lib.c, tcpip.c, sys.h, sys.c, err.c, opt.h: + Implement LWIP_SO_RCVTIMEO configuration option to enable/disable SO_RCVTIMEO + on UDP sockets/netconn. + + 2007-03-08 Simon Goldschmidt + * snmp_msg.h, msg_in.c: SNMP UDP ports can be configured at compile time. + + 2007-03-06 Frdric Bernon + * api.h, api_lib.c, sockets.h, sockets.c, tcpip.c, sys.h, sys.c, err.h: + Implement SO_RCVTIMEO on UDP sockets/netconn. + + 2007-02-28 Kieran Mansley (based on patch from Simon Goldschmidt) + * api_lib.c, tcpip.c, memp.c, memp.h: make API msg structs allocated + on the stack and remove the API msg type from memp + + 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt) + * sockets.h, sockets.c: Move socket initialization to new + lwip_socket_init() function. + NOTE: this changes the API with ports. Ports will have to be + updated to call lwip_socket_init() now. + + 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt) + * api_lib.c: Use memcpy in netbuf_copy_partial. + + + ++ Bug fixes: + + 2008-03-17 Frdric Bernon, Ed Kerekes + * igmp.h, igmp.c: Fix bug #22613 "IGMP iphdr problem" (could have + some problems to fill the IP header on some targets, use now the + ip.h macros to do it). + + 2008-03-13 Frdric Bernon + * sockets.c: Fix bug #22435 "lwip_recvfrom with TCP break;". Using + (lwip_)recvfrom with valid "from" and "fromlen" parameters, on a + TCP connection caused a crash. Note that using (lwip_)recvfrom + like this is a bit slow and that using (lwip)getpeername is the + good lwip way to do it (so, using recv is faster on tcp sockets). + + 2008-03-12 Frdric Bernon, Jonathan Larmour + * api_msg.c, contrib/apps/ping.c: Fix bug #22530 "api_msg.c's + recv_raw() does not consume data", and the ping sample (with + LWIP_SOCKET=1, the code did the wrong supposition that lwip_recvfrom + returned the IP payload, without the IP header). + + 2008-03-04 Jonathan Larmour + * mem.c, stats.c, mem.h: apply patch #6414 to avoid compiler errors + and/or warnings on some systems where mem_size_t and size_t differ. + * pbuf.c, ppp.c: Fix warnings on some systems with mem_malloc. + + 2008-03-04 Kieran Mansley (contributions by others) + * Numerous small compiler error/warning fixes from contributions to + mailing list after 1.3.0 release candidate made. + + 2008-01-25 Cui hengbin (integrated by Frdric Bernon) + * dns.c: Fix bug #22108 "DNS problem" caused by unaligned structures. + + 2008-01-15 Kieran Mansley + * tcp_out.c: BUG20511. Modify persist timer to start when we are + prevented from sending by a small send window, not just a zero + send window. + + 2008-01-09 Jonathan Larmour + * opt.h, ip.c: Rename IP_OPTIONS define to IP_OPTIONS_ALLOWED to avoid + conflict with Linux system headers. + + 2008-01-06 Jonathan Larmour + * dhcp.c: fix bug #19927: "DHCP NACK problem" by clearing any existing set IP + address entirely on receiving a DHCPNAK, and restarting discovery. + + 2007-12-21 Simon Goldschmidt + * sys.h, api_lib.c, api_msg.c, sockets.c: fix bug #21698: "netconn->recv_avail + is not protected" by using new macros for interlocked access to modify/test + netconn->recv_avail. + + 2007-12-20 Kieran Mansley (based on patch from Oleg Tyshev) + * tcp_in.c: fix bug# 21535 (nrtx not reset correctly in SYN_SENT state) + + 2007-12-20 Kieran Mansley (based on patch from Per-Henrik Lundbolm) + * tcp.c, tcp_in.c, tcp_out.c, tcp.h: fix bug #20199 (better handling + of silly window avoidance and prevent lwIP from shrinking the window) + + 2007-12-04 Simon Goldschmidt + * tcp.c, tcp_in.c: fix bug #21699 (segment leak in ooseq processing when last + data packet was lost): add assert that all segment lists are empty in + tcp_pcb_remove before setting pcb to CLOSED state; don't directly set CLOSED + state from LAST_ACK in tcp_process + + 2007-12-02 Simon Goldschmidt + * sockets.h: fix bug #21654: exclude definition of struct timeval from #ifndef FD_SET + If including for system-struct timeval, LWIP_TIMEVAL_PRIVATE now + has to be set to 0 in lwipopts.h + + 2007-12-02 Simon Goldschmidt + * api_msg.c, api_lib.c: fix bug #21656 (recvmbox problem in netconn API): always + allocate a recvmbox in netconn_new_with_proto_and_callback. For a tcp-listen + netconn, this recvmbox is later freed and a new mbox is allocated for acceptmbox. + This is a fix for thread-safety and allocates all items needed for a netconn + when the netconn is created. + + 2007-11-30 Simon Goldschmidt + * udp.c: first attempt to fix bug #21655 (DHCP doesn't work reliably with multiple + netifs): if LWIP_DHCP is enabled, UDP packets to DHCP_CLIENT_PORT are passed + to netif->dhcp->pcb only (if that exists) and not to any other pcb for the same + port (only solution to let UDP pcbs 'bind' to a netif instead of an IP address) + + 2007-11-27 Simon Goldschmidt + * ip.c: fixed bug #21643 (udp_send/raw_send don't fail if netif is down) by + letting ip_route only use netifs that are up. + + 2007-11-27 Simon Goldschmidt + * err.h, api_lib.c, api_msg.c, sockets.c: Changed error handling: ERR_MEM, ERR_BUF + and ERR_RTE are seen as non-fatal, all other errors are fatal. netconns and + sockets block most operations once they have seen a fatal error. + + 2007-11-27 Simon Goldschmidt + * udp.h, udp.c, dhcp.c: Implemented new function udp_sendto_if which takes the + netif to send as an argument (to be able to send on netifs that are down). + + 2007-11-26 Simon Goldschmidt + * tcp_in.c: Fixed bug #21582: pcb->acked accounting can be wrong when ACKs + arrive out-of-order + + 2007-11-21 Simon Goldschmidt + * tcp.h, tcp_out.c, api_msg.c: Fixed bug #20287: tcp_output_nagle sends too early + Fixed the nagle algorithm; nagle now also works for all raw API applications + and has to be explicitly disabled with 'tcp_pcb->flags |= TF_NODELAY' + + 2007-11-12 Frdric Bernon + * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fixed bug #20900. Now, most + of the netconn_peer and netconn_addr processing is done inside tcpip_thread + context in do_getaddr. + + 2007-11-10 Simon Goldschmidt + * etharp.c: Fixed bug: assert fired when MEMP_ARP_QUEUE was empty (which can + happen any time). Now the packet simply isn't enqueued when out of memory. + + 2007-11-01 Simon Goldschmidt + * tcp.c, tcp_in.c: Fixed bug #21494: The send mss (pcb->mss) is set to 536 (or + TCP_MSS if that is smaller) as long as no MSS option is received from the + remote host. + + 2007-11-01 Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c: Fixed bug #21491: The MSS option sent (with SYN) + is now based on TCP_MSS instead of pcb->mss (on passive open now effectively + sending our configured TCP_MSS instead of the one received). + + 2007-11-01 Simon Goldschmidt + * tcp_in.c: Fixed bug #21181: On active open, the initial congestion window was + calculated based on the configured TCP_MSS, not on the MSS option received + with SYN+ACK. + + 2007-10-09 Simon Goldschmidt + * udp.c, inet.c, inet.h: Fixed UDPLite: send: Checksum was always generated too + short and also was generated wrong if checksum coverage != tot_len; + receive: checksum was calculated wrong if checksum coverage != tot_len + + 2007-10-08 Simon Goldschmidt + * mem.c: lfree was not updated in mem_realloc! + + 2007-10-07 Frdric Bernon + * sockets.c, api.h, api_lib.c: First step to fix "bug #20900 : Potential + crash error problem with netconn_peer & netconn_addr". VERY IMPORTANT: + this change cause an API breakage for netconn_addr, since a parameter + type change. Any compiler should cause an error without any changes in + yours netconn_peer calls (so, it can't be a "silent change"). It also + reduce a little bit the footprint for socket layer (lwip_getpeername & + lwip_getsockname use now a common lwip_getaddrname function since + netconn_peer & netconn_addr have the same parameters). + + 2007-09-20 Simon Goldschmidt + * tcp.c: Fixed bug #21080 (tcp_bind without check pcbs in TIME_WAIT state) + by checking tcp_tw_pcbs also + + 2007-09-19 Simon Goldschmidt + * icmp.c: Fixed bug #21107 (didn't reset IP TTL in ICMP echo replies) + + 2007-09-15 Mike Kleshov + * mem.c: Fixed bug #21077 (inaccuracy in calculation of lwip_stat.mem.used) + + 2007-09-06 Frdric Bernon + * several-files: replace some #include "arch/cc.h" by "lwip/arch.h", or simply remove + it as long as "lwip/opt.h" is included before (this one include "lwip/debug.h" which + already include "lwip/arch.h"). Like that, default defines are provided by "lwip/arch.h" + if they are not defined in cc.h, in the same spirit than "lwip/opt.h" for lwipopts.h. + + 2007-08-30 Frdric Bernon + * igmp.h, igmp.c: Some changes to remove some redundant code, add some traces, + and fix some coding style. + + 2007-08-28 Frdric Bernon + * tcpip.c: Fix TCPIP_MSG_INPKT processing: now, tcpip_input can be used for any + kind of packets. These packets are considered like Ethernet packets (payload + pointing to ethhdr) if the netif got the NETIF_FLAG_ETHARP flag. Else, packets + are considered like IP packets (payload pointing to iphdr). + + 2007-08-27 Frdric Bernon + * api.h, api_lib.c, api_msg.c: First fix for "bug #20900 : Potential crash error + problem with netconn_peer & netconn_addr". Introduce NETCONN_LISTEN netconn_state + and remove obsolete ones (NETCONN_RECV & NETCONN_ACCEPT). + + 2007-08-24 Kieran Mansley + * inet.c Modify (acc >> 16) test to ((acc >> 16) != 0) to help buggy + compiler (Paradigm C++) + + 2007-08-09 Frdric Bernon, Bill Florac + * stats.h, stats.c, igmp.h, igmp.c, opt.h: Fix for bug #20503 : IGMP Improvement. + Introduce IGMP_STATS to centralize statistics management. + + 2007-08-09 Frdric Bernon, Bill Florac + * udp.c: Fix for bug #20503 : IGMP Improvement. Enable to receive a multicast + packet on a udp pcb binded on an netif's IP address, and not on "any". + + 2007-08-09 Frdric Bernon, Bill Florac + * igmp.h, igmp.c, ip.c: Fix minor changes from bug #20503 : IGMP Improvement. + This is mainly on using lookup/lookfor, and some coding styles... + + 2007-07-26 Frdric Bernon (and "thedoctor") + * igmp.c: Fix bug #20595 to accept IGMPv3 "Query" messages. + + 2007-07-25 Simon Goldschmidt + * api_msg.c, tcp.c: Another fix for bug #20021: by not returning an error if + tcp_output fails in tcp_close, the code in do_close_internal gets simpler + (tcp_output is called again later from tcp timers). + + 2007-07-25 Simon Goldschmidt + * ip_frag.c: Fixed bug #20429: use the new pbuf_copy_partial instead of the old + copy_from_pbuf, which illegally modified the given pbuf. + + 2007-07-25 Simon Goldschmidt + * tcp_out.c: tcp_enqueue: pcb->snd_queuelen didn't work for chaine PBUF_RAMs: + changed snd_queuelen++ to snd_queuelen += pbuf_clen(p). + + 2007-07-24 Simon Goldschmidt + * api_msg.c, tcp.c: Fix bug #20480: Check the pcb passed to tcp_listen() for the + correct state (must be CLOSED). + + 2007-07-13 Thomas Taranowski (commited by Jared Grubb) + * memp.c: Fix bug #20478: memp_malloc returned NULL+MEMP_SIZE on failed + allocation. It now returns NULL. + + 2007-07-13 Frdric Bernon + * api_msg.c: Fix bug #20318: api_msg "recv" callbacks don't call pbuf_free in + all error cases. + + 2007-07-13 Frdric Bernon + * api_msg.c: Fix bug #20315: possible memory leak problem if tcp_listen failed, + because current code doesn't follow rawapi.txt documentation. + + 2007-07-13 Kieran Mansley + * src/core/tcp_in.c Apply patch#5741 from Oleg Tyshev to fix bug in + out of sequence processing of received packets + + 2007-07-03 Simon Goldschmidt + * nearly-all-files: Added assertions where PBUF_RAM pbufs are used and an + assumption is made that this pbuf is in one piece (i.e. not chained). These + assumptions clash with the possibility of converting to fully pool-based + pbuf implementations, where PBUF_RAM pbufs might be chained. + + 2007-07-03 Simon Goldschmidt + * api.h, api_lib.c, api_msg.c: Final fix for bug #20021 and some other problems + when closing tcp netconns: removed conn->sem, less context switches when + closing, both netconn_close and netconn_delete should safely close tcp + connections. + + 2007-07-02 Simon Goldschmidt + * ipv4/ip.h, ipv6/ip.h, opt.h, netif.h, etharp.h, ipv4/ip.c, netif.c, raw.c, + tcp_out.c, udp.c, etharp.c: Added option LWIP_NETIF_HWADDRHINT (default=off) + to cache ARP table indices with each pcb instead of single-entry cache for + the complete stack. + + 2007-07-02 Simon Goldschmidt + * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Added some ASSERTS and casts to prevent + warnings when assigning to smaller types. + + 2007-06-28 Simon Goldschmidt + * tcp_out.c: Added check to prevent tcp_pcb->snd_queuelen from overflowing. + + 2007-06-28 Simon Goldschmidt + * tcp.h: Fixed bug #20287: Fixed nagle algorithm (sending was done too early if + a segment contained chained pbufs) + + 2007-06-28 Frdric Bernon + * autoip.c: replace most of rand() calls by a macro LWIP_AUTOIP_RAND which compute + a "pseudo-random" value based on netif's MAC and some autoip fields. It's always + possible to define this macro in your own lwipopts.h to always use C library's + rand(). Note that autoip_create_rand_addr doesn't use this macro. + + 2007-06-28 Frdric Bernon + * netifapi.h, netifapi.c, tcpip.h, tcpip.c: Update code to handle the option + LWIP_TCPIP_CORE_LOCKING, and do some changes to be coherent with last modifications + in api_lib/api_msg (use pointers and not type with table, etc...) + + 2007-06-26 Simon Goldschmidt + * udp.h: Fixed bug #20259: struct udp_hdr was lacking the packin defines. + + 2007-06-25 Simon Goldschmidt + * udp.c: Fixed bug #20253: icmp_dest_unreach was called with a wrong p->payload + for udp packets with no matching pcb. + + 2007-06-25 Simon Goldschmidt + * udp.c: Fixed bug #20220: UDP PCB search in udp_input(): a non-local match + could get udp input packets if the remote side matched. + + 2007-06-13 Simon Goldschmidt + * netif.c: Fixed bug #20180 (TCP pcbs listening on IP_ADDR_ANY could get + changed in netif_set_ipaddr if previous netif->ip_addr.addr was 0. + + 2007-06-13 Simon Goldschmidt + * api_msg.c: pcb_new sets conn->err if protocol is not implemented + -> netconn_new_..() does not allocate a new connection for unsupported + protocols. + + 2007-06-13 Frdric Bernon, Simon Goldschmidt + * api_lib.c: change return expression in netconn_addr and netconn_peer, because + conn->err was reset to ERR_OK without any reasons (and error was lost)... + + 2007-06-13 Frdric Bernon, Matthias Weisser + * opt.h, mem.h, mem.c, memp.c, pbuf.c, ip_frag.c, vj.c: Fix bug #20162. Rename + MEM_ALIGN in LWIP_MEM_ALIGN and MEM_ALIGN_SIZE in LWIP_MEM_ALIGN_SIZE to avoid + some macro names collision with some OS macros. + + 2007-06-11 Simon Goldschmidt + * udp.c: UDP Lite: corrected the use of chksum_len (based on RFC3828: if it's 0, + create checksum over the complete packet. On RX, if it's < 8 (and not 0), + discard the packet. Also removed the duplicate 'udphdr->chksum = 0' for both + UDP & UDP Lite. + + 2007-06-11 Srinivas Gollakota & Oleg Tyshev + * tcp_out.c: Fix for bug #20075 : "A problem with keep-alive timer and TCP flags" + where TCP flags wasn't initialized in tcp_keepalive. + + 2007-06-03 Simon Goldschmidt + * udp.c: udp_input(): Input pbuf was not freed if pcb had no recv function + registered, p->payload was modified without modifying p->len if sending + icmp_dest_unreach() (had no negative effect but was definitively wrong). + + 2007-06-03 Simon Goldschmidt + * icmp.c: Corrected bug #19937: For responding to an icmp echo request, icmp + re-used the input pbuf even if that didn't have enough space to include the + link headers. Now the space is tested and a new pbuf is allocated for the + echo response packet if the echo request pbuf isn't big enough. + + 2007-06-01 Simon Goldschmidt + * sockets.c: Checked in patch #5914: Moved sockopt processing into tcpip_thread. + + 2007-05-23 Frdric Bernon + * api_lib.c, sockets.c: Fixed bug #5958 for netconn_listen (acceptmbox only + allocated by do_listen if success) and netconn_accept errors handling. In + most of api_lib functions, we replace some errors checkings like "if (conn==NULL)" + by ASSERT, except for netconn_delete. + + 2007-05-23 Frdric Bernon + * api_lib.c: Fixed bug #5957 "Safe-thread problem inside netconn_recv" to return + an error code if it's impossible to fetch a pbuf on a TCP connection (and not + directly close the recvmbox). + + 2007-05-22 Simon Goldschmidt + * tcp.c: Fixed bug #1895 (tcp_bind not correct) by introducing a list of + bound but unconnected (and non-listening) tcp_pcbs. + + 2007-05-22 Frdric Bernon + * sys.h, sys.c, api_lib.c, tcpip.c: remove sys_mbox_fetch_timeout() (was only + used for LWIP_SO_RCVTIMEO option) and use sys_arch_mbox_fetch() instead of + sys_mbox_fetch() in api files. Now, users SHOULD NOT use internal lwIP features + like "sys_timeout" in their application threads. + + 2007-05-22 Frdric Bernon + * api.h, api_lib.c, api_msg.h, api_msg.c: change the struct api_msg_msg to see + which parameters are used by which do_xxx function, and to avoid "misusing" + parameters (patch #5938). + + 2007-05-22 Simon Goldschmidt + * api_lib.c, api_msg.c, raw.c, api.h, api_msg.h, raw.h: Included patch #5938: + changed raw_pcb.protocol from u16_t to u8_t since for IPv4 and IPv6, proto + is only 8 bits wide. This affects the api, as there, the protocol was + u16_t, too. + + 2007-05-18 Simon Goldschmidt + * memp.c: addition to patch #5913: smaller pointer was returned but + memp_memory was the same size -> did not save memory. + + 2007-05-16 Simon Goldschmidt + * loopif.c, slipif.c: Fix bug #19729: free pbuf if netif->input() returns + != ERR_OK. + + 2007-05-16 Simon Goldschmidt + * api_msg.c, udp.c: If a udp_pcb has a local_ip set, check if it is the same + as the one of the netif used for sending to prevent sending from old + addresses after a netif address gets changed (partly fixes bug #3168). + + 2007-05-16 Frdric Bernon + * tcpip.c, igmp.h, igmp.c: Fixed bug "#19800 : IGMP: igmp_tick() will not work + with NO_SYS=1". Note that igmp_init is always in tcpip_thread (and not in + tcpip_init) because we have to be sure that network interfaces are already + added (mac filter is updated only in igmp_init for the moment). + + 2007-05-16 Simon Goldschmidt + * mem.c, memp.c: Removed semaphores from memp, changed sys_sem_wait calls + into sys_arch_sem_wait calls to prevent timers from running while waiting + for the heap. This fixes bug #19167. + + 2007-05-13 Simon Goldschmidt + * tcp.h, sockets.h, sockets.c: Fixed bug from patch #5865 by moving the defines + for socket options (lwip_set/-getsockopt) used with level IPPROTO_TCP from + tcp.h to sockets.h. + + 2007-05-07 Simon Goldschmidt + * mem.c: Another attempt to fix bug #17922. + + 2007-05-04 Simon Goldschmidt + * pbuf.c, pbuf.h, etharp.c: Further update to ARP queueing: Changed pbuf_copy() + implementation so that it can be reused (don't allocate the target + pbuf inside pbuf_copy()). + + 2007-05-04 Simon Goldschmidt + * memp.c: checked in patch #5913: in memp_malloc() we can return memp as mem + to save a little RAM (next pointer of memp is not used while not in pool). + + 2007-05-03 "maq" + * sockets.c: Fix ioctl FIONREAD when some data remains from last recv. + (patch #3574). + + 2007-04-23 Simon Goldschmidt + * loopif.c, loopif.h, opt.h, src/netif/FILES: fix bug #2595: "loopif results + in NULL reference for incoming TCP packets". Loopif has to be configured + (using LWIP_LOOPIF_MULTITHREADING) to directly call netif->input() + (multithreading environments, e.g. netif->input() = tcpip_input()) or + putting packets on a list that is fed to the stack by calling loopif_poll() + (single-thread / NO_SYS / polling environment where e.g. + netif->input() = ip_input). + + 2007-04-17 Jonathan Larmour + * pbuf.c: Use s32_t in pbuf_realloc(), as an s16_t can't reliably hold + the difference between two u16_t's. + * sockets.h: FD_SETSIZE needs to match number of sockets, which is + MEMP_NUM_NETCONN in sockets.c right now. + + 2007-04-12 Jonathan Larmour + * icmp.c: Reset IP header TTL in ICMP ECHO responses (bug #19580). + + 2007-04-12 Kieran Mansley + * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Modify way the retransmission + timer is reset to fix bug#19434, with help from Oleg Tyshev. + + 2007-04-11 Simon Goldschmidt + * etharp.c, pbuf.c, pbuf.h: 3rd fix for bug #11400 (arp-queuing): More pbufs than + previously thought need to be copied (everything but PBUF_ROM!). Cleaned up + pbuf.c: removed functions no needed any more (by etharp). + + 2007-04-11 Kieran Mansley + * inet.c, ip_addr.h, sockets.h, sys.h, tcp.h: Apply patch #5745: Fix + "Constant is long" warnings with 16bit compilers. Contributed by + avatar@mmlab.cse.yzu.edu.tw + + 2007-04-05 Frdric Bernon, Jonathan Larmour + * api_msg.c: Fix bug #16830: "err_tcp() posts to connection mailbox when no pend on + the mailbox is active". Now, the post is only done during a connect, and do_send, + do_write and do_join_leave_group don't do anything if a previous error was signaled. + + 2007-04-03 Frdric Bernon + * ip.c: Don't set the IP_DF ("Don't fragment") flag in the IP header in IP output + packets. See patch #5834. + + 2007-03-30 Frdric Bernon + * api_msg.c: add a "pcb_new" helper function to avoid redundant code, and to add + missing pcb allocations checking (in do_bind, and for each raw_new). Fix style. + + 2007-03-30 Frdric Bernon + * most of files: prefix all debug.h define with "LWIP_" to avoid any conflict with + others environment defines (these were too "generic"). + + 2007-03-28 Frdric Bernon + * api.h, api_lib.c, sockets.c: netbuf_ref doesn't check its internal pbuf_alloc call + result and can cause a crash. lwip_send now check netbuf_ref result. + + 2007-03-28 Simon Goldschmidt + * sockets.c Remove "#include " from sockets.c to avoid multiple + definition of macros (in errno.h and lwip/arch.h) if LWIP_PROVIDE_ERRNO is + defined. This is the way it should have been already (looking at + doc/sys_arch.txt) + + 2007-03-28 Kieran Mansley + * opt.h Change default PBUF_POOL_BUFSIZE (again) to accomodate default MSS + + IP and TCP headers *and* physical link headers + + 2007-03-26 Frdric Bernon (based on patch from Dmitry Potapov) + * api_lib.c: patch for netconn_write(), fixes a possible race condition which cause + to send some garbage. It is not a definitive solution, but the patch does solve + the problem for most cases. + + 2007-03-22 Frdric Bernon + * api_msg.h, api_msg.c: Remove obsolete API_MSG_ACCEPT and do_accept (never used). + + 2007-03-22 Frdric Bernon + * api_lib.c: somes resources couldn't be freed if there was errors during + netconn_new_with_proto_and_callback. + + 2007-03-22 Frdric Bernon + * ethernetif.c: update netif->input calls to check return value. In older ports, + it's a good idea to upgrade them, even if before, there could be another problem + (access to an uninitialized mailbox). + + 2007-03-21 Simon Goldschmidt + * sockets.c: fixed bug #5067 (essentialy a signed/unsigned warning fixed + by casting to unsigned). + + 2007-03-21 Frdric Bernon + * api_lib.c, api_msg.c, tcpip.c: integrate sys_mbox_fetch(conn->mbox, NULL) calls from + api_lib.c to tcpip.c's tcpip_apimsg(). Now, use a local variable and not a + dynamic one from memp to send tcpip_msg to tcpip_thread in a synchrone call. + Free tcpip_msg from tcpip_apimsg is not done in tcpip_thread. This give a + faster and more reliable communication between api_lib and tcpip. + + 2007-03-21 Frdric Bernon + * opt.h: Add LWIP_NETIF_CALLBACK (to avoid compiler warning) and set it to 0. + + 2007-03-21 Frdric Bernon + * api_msg.c, igmp.c, igmp.h: Fix C++ style comments + + 2007-03-21 Kieran Mansley + * opt.h Change default PBUF_POOL_BUFSIZE to accomodate default MSS + + IP and TCP headers + + 2007-03-21 Kieran Mansley + * Fix all uses of pbuf_header to check the return value. In some + cases just assert if it fails as I'm not sure how to fix them, but + this is no worse than before when they would carry on regardless + of the failure. + + 2007-03-21 Kieran Mansley + * sockets.c, igmp.c, igmp.h, memp.h: Fix C++ style comments and + comment out missing header include in icmp.c + + 2007-03-20 Frdric Bernon + * memp.h, stats.c: Fix stats_display function where memp_names table wasn't + synchronized with memp.h. + + 2007-03-20 Frdric Bernon + * tcpip.c: Initialize tcpip's mbox, and verify if initialized in tcpip_input, + tcpip_ethinput, tcpip_callback, tcpip_apimsg, to fix a init problem with + network interfaces. Also fix a compiler warning. + + 2007-03-20 Kieran Mansley + * udp.c: Only try and use pbuf_header() to make space for headers if + not a ROM or REF pbuf. + + 2007-03-19 Frdric Bernon + * api_msg.h, api_msg.c, tcpip.h, tcpip.c: Add return types to tcpip_apimsg() + and api_msg_post(). + + 2007-03-19 Frdric Bernon + * Remove unimplemented "memp_realloc" function from memp.h. + + 2007-03-11 Simon Goldschmidt + * pbuf.c: checked in patch #5796: pbuf_alloc: len field claculation caused + memory corruption. + + 2007-03-11 Simon Goldschmidt (based on patch from Dmitry Potapov) + * api_lib.c, sockets.c, api.h, api_msg.h, sockets.h: Fixed bug #19251 + (missing `const' qualifier in socket functions), to get more compatible to + standard POSIX sockets. + + 2007-03-11 Frdric Bernon (based on patch from Dmitry Potapov) + * sockets.c: Add asserts inside bind, connect and sendto to check input + parameters. Remove excessive set_errno() calls after get_socket(), because + errno is set inside of get_socket(). Move last sock_set_errno() inside + lwip_close. + + 2007-03-09 Simon Goldschmidt + * memp.c: Fixed bug #11400: New etharp queueing introduced bug: memp_memory + was allocated too small. + + 2007-03-06 Simon Goldschmidt + * tcpip.c: Initialize dhcp timers in tcpip_thread (if LWIP_DHCP) to protect + the stack from concurrent access. + + 2007-03-06 Frdric Bernon, Dmitry Potapov + * tcpip.c, ip_frag.c, ethernetif.c: Fix some build problems, and a redundancy + call to "lwip_stats.link.recv++;" in low_level_input() & ethernetif_input(). + + 2007-03-06 Simon Goldschmidt + * ip_frag.c, ip_frag.h: Reduce code size: don't include code in those files + if IP_FRAG == 0 and IP_REASSEMBLY == 0 + + 2007-03-06 Frdric Bernon, Simon Goldschmidt + * opt.h, ip_frag.h, tcpip.h, tcpip.c, ethernetif.c: add new configuration + option named ETHARP_TCPIP_ETHINPUT, which enable the new tcpip_ethinput. + Allow to do ARP processing for incoming packets inside tcpip_thread + (protecting ARP layer against concurrent access). You can also disable + old code using tcp_input with new define ETHARP_TCPIP_INPUT set to 0. + Older ports have to use tcpip_ethinput. + + 2007-03-06 Simon Goldschmidt (based on patch from Dmitry Potapov) + * err.h, err.c: fixed compiler warning "initialization dircards qualifiers + from pointer target type" + + 2007-03-05 Frdric Bernon + * opt.h, sockets.h: add new configuration options (LWIP_POSIX_SOCKETS_IO_NAMES, + ETHARP_TRUST_IP_MAC, review SO_REUSE) + + 2007-03-04 Frdric Bernon + * api_msg.c: Remove some compiler warnings : parameter "pcb" was never + referenced. + + 2007-03-04 Frdric Bernon + * api_lib.c: Fix "[patch #5764] api_lib.c cleanup: after patch #5687" (from + Dmitry Potapov). + The api_msg struct stay on the stack (not moved to netconn struct). + + 2007-03-04 Simon Goldschmidt (based on patch from Dmitry Potapov) + * pbuf.c: Fix BUG#19168 - pbuf_free can cause deadlock (if + SYS_LIGHTWEIGHT_PROT=1 & freeing PBUF_RAM when mem_sem is not available) + Also fixed cast warning in pbuf_alloc() + + 2007-03-04 Simon Goldschmidt + * etharp.c, etharp.h, memp.c, memp.h, opt.h: Fix BUG#11400 - don't corrupt + existing pbuf chain when enqueuing multiple pbufs to a pending ARP request + + 2007-03-03 Frdric Bernon + * udp.c: remove obsolete line "static struct udp_pcb *pcb_cache = NULL;" + It is static, and never used in udp.c except udp_init(). + + 2007-03-02 Simon Goldschmidt + * tcpip.c: Moved call to ip_init(), udp_init() and tcp_init() from + tcpip_thread() to tcpip_init(). This way, raw API connections can be + initialized before tcpip_thread is running (e.g. before OS is started) + + 2007-03-02 Frdric Bernon + * rawapi.txt: Fix documentation mismatch with etharp.h about etharp_tmr's call + interval. + + 2007-02-28 Kieran Mansley + * pbuf.c: Fix BUG#17645 - ensure pbuf payload pointer is not moved + outside the region of the pbuf by pbuf_header() + + 2007-02-28 Kieran Mansley + * sockets.c: Fix BUG#19161 - ensure milliseconds timeout is non-zero + when supplied timeout is also non-zero + +(STABLE-1.2.0) + + 2006-12-05 Leon Woestenberg + * CHANGELOG: Mention STABLE-1.2.0 release. + + ++ New features: + + 2006-12-01 Christiaan Simons + * mem.h, opt.h: Added MEM_LIBC_MALLOC option. + Note this is a workaround. Currently I have no other options left. + + 2006-10-26 Christiaan Simons (accepted patch by Jonathan Larmour) + * ipv4/ip_frag.c: rename MAX_MTU to IP_FRAG_MAX_MTU and move define + to include/lwip/opt.h. + * ipv4/lwip/ip_frag.h: Remove unused IP_REASS_INTERVAL. + Move IP_REASS_MAXAGE and IP_REASS_BUFSIZE to include/lwip/opt.h. + * opt.h: Add above new options. + + 2006-08-18 Christiaan Simons + * tcp_{in,out}.c: added SNMP counters. + * ipv4/ip.c: added SNMP counters. + * ipv4/ip_frag.c: added SNMP counters. + + 2006-08-08 Christiaan Simons + * etharp.{c,h}: added etharp_find_addr() to read + (stable) ethernet/IP address pair from ARP table + + 2006-07-14 Christiaan Simons + * mib_structs.c: added + * include/lwip/snmp_structs.h: added + * netif.{c,h}, netif/ethernetif.c: added SNMP statistics to netif struct + + 2006-07-06 Christiaan Simons + * snmp/asn1_{enc,dec}.c added + * snmp/mib2.c added + * snmp/msg_{in,out}.c added + * include/lwip/snmp_asn1.h added + * include/lwip/snmp_msg.h added + * doc/snmp_agent.txt added + + 2006-03-29 Christiaan Simons + * inet.c, inet.h: Added platform byteswap support. + Added LWIP_PLATFORM_BYTESWAP define (defaults to 0) and + optional LWIP_PLATFORM_HTONS(), LWIP_PLATFORM_HTONL() macros. + + ++ Bug fixes: + + 2006-11-30 Christiaan Simons + * dhcp.c: Fixed false triggers of request_timeout. + + 2006-11-28 Christiaan Simons + * netif.c: In netif_add() fixed missing clear of ip_addr, netmask, gw and flags. + + 2006-10-11 Christiaan Simons + * api_lib.c etharp.c, ip.c, memp.c, stats.c, sys.{c,h} tcp.h: + Partially accepted patch #5449 for ANSI C compatibility / build fixes. + * ipv4/lwip/ip.h ipv6/lwip/ip.h: Corrected UDP-Lite protocol + identifier from 170 to 136 (bug #17574). + + 2006-10-10 Christiaan Simons + * api_msg.c: Fixed Nagle algorithm as reported by Bob Grice. + + 2006-08-17 Christiaan Simons + * udp.c: Fixed bug #17200, added check for broadcast + destinations for PCBs bound to a unicast address. + + 2006-08-07 Christiaan Simons + * api_msg.c: Flushing TCP output in do_close() (bug #15926). + + 2006-06-27 Christiaan Simons + * api_msg.c: Applied patch for cold case (bug #11135). + In accept_function() ensure newconn->callback is always initialized. + + 2006-06-15 Christiaan Simons + * mem.h: added MEM_SIZE_F alias to fix an ancient cold case (bug #1748), + facilitate printing of mem_size_t and u16_t statistics. + + 2006-06-14 Christiaan Simons + * api_msg.c: Applied patch #5146 to handle allocation failures + in accept() by Kevin Lawson. + + 2006-05-26 Christiaan Simons + * api_lib.c: Removed conn->sem creation and destruction + from netconn_write() and added sys_sem_new to netconn_new_*. + +(STABLE-1_1_1) + + 2006-03-03 Christiaan Simons + * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap + access and added pbuf_alloc() return value checks. + + 2006-01-01 Leon Woestenberg + * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is + now handled by the checksum routine properly. + + 2006-02-27 Leon Woestenberg + * pbuf.c: Fix alignment; pbuf_init() would not work unless + pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.) + + 2005-12-20 Leon Woestenberg + * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch + submitted by Mitrani Hiroshi. + + 2005-12-15 Christiaan Simons + * inet.c: Disabled the added summing routine to preserve code space. + + 2005-12-14 Leon Woestenberg + * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson. + Added Curt McDowell's optimized checksumming routine for future + inclusion. Need to create test case for unaliged, aligned, odd, + even length combination of cases on various endianess machines. + + 2005-12-09 Christiaan Simons + * inet.c: Rewrote standard checksum routine in proper portable C. + + 2005-11-25 Christiaan Simons + * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only. + * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t, + u32_t, s32_t typedefs. This solves most debug word-length assumes. + + 2005-07-17 Leon Woestenberg + * inet.c: Fixed unaligned 16-bit access in the standard checksum + routine by Peter Jolasson. + * slipif.c: Fixed implementation assumption of single-pbuf datagrams. + + 2005-02-04 Leon Woestenberg + * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch. + * tcp_{out|in}.c: Applied patch fixing unaligned access. + + 2005-01-04 Leon Woestenberg + * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement. + + 2005-01-03 Leon Woestenberg + * udp.c: UDP pcb->recv() was called even when it was NULL. + +(STABLE-1_1_0) + + 2004-12-28 Leon Woestenberg + * etharp.*: Disabled multiple packets on the ARP queue. + This clashes with TCP queueing. + + 2004-11-28 Leon Woestenberg + * etharp.*: Fixed race condition from ARP request to ARP timeout. + Halved the ARP period, doubled the period counts. + ETHARP_MAX_PENDING now should be at least 2. This prevents + the counter from reaching 0 right away (which would allow + too little time for ARP responses to be received). + + 2004-11-25 Leon Woestenberg + * dhcp.c: Decline messages were not multicast but unicast. + * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD. + Do not try hard to insert arbitrary packet's source address, + etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. + etharp_query() now always DOES call ETHARP_TRY_HARD so that users + querying an address will see it appear in the cache (DHCP could + suffer from this when a server invalidly gave an in-use address.) + * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are + comparing network addresses (identifiers), not the network masks + themselves. + * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given + IP address actually belongs to the network of the given interface. + + 2004-11-24 Kieran Mansley + * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state. + +(STABLE-1_1_0-RC1) + + 2004-10-16 Kieran Mansley + * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately, + even if one is already pending, if the rcv_wnd is above a threshold + (currently TCP_WND/2). This avoids waiting for a timer to expire to send a + delayed ACK in order to open the window if the stack is only receiving data. + + 2004-09-12 Kieran Mansley + * tcp*.*: Retransmit time-out handling improvement by Sam Jansen. + + 2004-08-20 Tony Mountifield + * etharp.c: Make sure the first pbuf queued on an ARP entry + is properly ref counted. + + 2004-07-27 Tony Mountifield + * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler + warnings about comparison. + * pbuf.c: Stopped compiler complaining of empty if statement + when LWIP_DEBUGF() empty. Closed an unclosed comment. + * tcp.c: Stopped compiler complaining of empty if statement + when LWIP_DEBUGF() empty. + * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons(). + * inet.c: Added a couple of casts to quiet the compiler. + No need to test isascii(c) before isdigit(c) or isxdigit(c). + + 2004-07-22 Tony Mountifield + * inet.c: Made data types consistent in inet_ntoa(). + Added casts for return values of checksum routines, to pacify compiler. + * ip_frag.c, tcp_out.c, sockets.c, pbuf.c + Small corrections to some debugging statements, to pacify compiler. + + 2004-07-21 Tony Mountifield + * etharp.c: Removed spurious semicolon and added missing end-of-comment. + * ethernetif.c Updated low_level_output() to match prototype for + netif->linkoutput and changed low_level_input() similarly for consistency. + * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype + of raw_recv() in raw.h and so avoid compiler error. + * sockets.c: Added trivial (int) cast to keep compiler happier. + * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros. + +(STABLE-1_0_0) + + ++ Changes: + + 2004-07-05 Leon Woestenberg + * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure + your cc.h file defines this either 1 or 0. If non-defined, + defaults to 1. + * .c: Added and includes where used. + * etharp.c: Made some array indices unsigned. + + 2004-06-27 Leon Woestenberg + * netif.*: Added netif_set_up()/down(). + * dhcp.c: Changes to restart program flow. + + 2004-05-07 Leon Woestenberg + * etharp.c: In find_entry(), instead of a list traversal per candidate, do a + single-pass lookup for different candidates. Should exploit locality. + + 2004-04-29 Leon Woestenberg + * tcp*.c: Cleaned up source comment documentation for Doxygen processing. + * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC. + * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by + the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option. + + ++ Bug fixes: + + 2004-04-27 Leon Woestenberg + * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution + suggested by Timmy Brolin. Fix for 32-bit processors that cannot access + non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix + is to prefix the 14-bit Ethernet headers with two padding bytes. + + 2004-04-23 Leon Woestenberg + * ip_addr.c: Fix in the ip_addr_isbroadcast() check. + * etharp.c: Fixed the case where the packet that initiates the ARP request + is not queued, and gets lost. Fixed the case where the packets destination + address is already known; we now always queue the packet and perform an ARP + request. + +(STABLE-0_7_0) + + ++ Bug fixes: + + * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition. + * Fixed TCP bug in dequeueing of FIN from out of order segment queue. + * Fixed two possible NULL references in rare cases. + +(STABLE-0_6_6) + + ++ Bug fixes: + + * Fixed DHCP which did not include the IP address in DECLINE messages. + + ++ Changes: + + * etharp.c has been hauled over a bit. + +(STABLE-0_6_5) + + ++ Bug fixes: + + * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic. + * Packets sent from ARP queue had invalid source hardware address. + + ++ Changes: + + * Pass-by ARP requests do now update the cache. + + ++ New features: + + * No longer dependent on ctype.h. + * New socket options. + * Raw IP pcb support. + +(STABLE-0_6_4) + + ++ Bug fixes: + + * Some debug formatters and casts fixed. + * Numereous fixes in PPP. + + ++ Changes: + + * DEBUGF now is LWIP_DEBUGF + * pbuf_dechain() has been re-enabled. + * Mentioned the changed use of CVS branches in README. + +(STABLE-0_6_3) + + ++ Bug fixes: + + * Fixed pool pbuf memory leak in pbuf_alloc(). + Occured if not enough PBUF_POOL pbufs for a packet pbuf chain. + Reported by Savin Zlobec. + + * PBUF_POOL chains had their tot_len field not set for non-first + pbufs. Fixed in pbuf_alloc(). + + ++ New features: + + * Added PPP stack contributed by Marc Boucher + + ++ Changes: + + * Now drops short packets for ICMP/UDP/TCP protocols. More robust. + + * ARP queueuing now queues the latest packet instead of the first. + This is the RFC recommended behaviour, but can be overridden in + lwipopts.h. + +(0.6.2) + + ++ Bugfixes: + + * TCP has been fixed to deal with the new use of the pbuf->ref + counter. + + * DHCP dhcp_inform() crash bug fixed. + + ++ Changes: + + * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed + pbuf_refresh(). This has sped up pbuf pool operations considerably. + Implemented by David Haas. + +(0.6.1) + + ++ New features: + + * The packet buffer implementation has been enhanced to support + zero-copy and copy-on-demand for packet buffers which have their + payloads in application-managed memory. + Implemented by David Haas. + + Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy + if an outgoing packet can be directly sent on the link, or perform + a copy-on-demand when necessary. + + The application can safely assume the packet is sent, and the RAM + is available to the application directly after calling udp_send() + or similar function. + + ++ Bugfixes: + + * ARP_QUEUEING should now correctly work for all cases, including + PBUF_REF. + Implemented by Leon Woestenberg. + + ++ Changes: + + * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer + to a '0.0.0.0' IP address. + + * The packet buffer implementation is changed. The pbuf->ref counter + meaning has changed, and several pbuf functions have been + adapted accordingly. + + * netif drivers have to be changed to set the hardware address length field + that must be initialized correctly by the driver (hint: 6 for Ethernet MAC). + See the contrib/ports/c16x cs8900 driver as a driver example. + + * netif's have a dhcp field that must be initialized to NULL by the driver. + See the contrib/ports/c16x cs8900 driver as a driver example. + +(0.5.x) This file has been unmaintained up to 0.6.1. All changes are + logged in CVS but have not been explained here. + +(0.5.3) Changes since version 0.5.2 + + ++ Bugfixes: + + * memp_malloc(MEMP_API_MSG) could fail with multiple application + threads because it wasn't protected by semaphores. + + ++ Other changes: + + * struct ip_addr now packed. + + * The name of the time variable in arp.c has been changed to ctime + to avoid conflicts with the time() function. + +(0.5.2) Changes since version 0.5.1 + + ++ New features: + + * A new TCP function, tcp_tmr(), now handles both TCP timers. + + ++ Bugfixes: + + * A bug in tcp_parseopt() could cause the stack to hang because of a + malformed TCP option. + + * The address of new connections in the accept() function in the BSD + socket library was not handled correctly. + + * pbuf_dechain() did not update the ->tot_len field of the tail. + + * Aborted TCP connections were not handled correctly in all + situations. + + ++ Other changes: + + * All protocol header structs are now packed. + + * The ->len field in the tcp_seg structure now counts the actual + amount of data, and does not add one for SYN and FIN segments. + +(0.5.1) Changes since version 0.5.0 + + ++ New features: + + * Possible to run as a user process under Linux. + + * Preliminary support for cross platform packed structs. + + * ARP timer now implemented. + + ++ Bugfixes: + + * TCP output queue length was badly initialized when opening + connections. + + * TCP delayed ACKs were not sent correctly. + + * Explicit initialization of BSS segment variables. + + * read() in BSD socket library could drop data. + + * Problems with memory alignment. + + * Situations when all TCP buffers were used could lead to + starvation. + + * TCP MSS option wasn't parsed correctly. + + * Problems with UDP checksum calculation. + + * IP multicast address tests had endianess problems. + + * ARP requests had wrong destination hardware address. + + ++ Other changes: + + * struct eth_addr changed from u16_t[3] array to u8_t[6]. + + * A ->linkoutput() member was added to struct netif. + + * TCP and UDP ->dest_* struct members where changed to ->remote_*. + + * ntoh* macros are now null definitions for big endian CPUs. + +(0.5.0) Changes since version 0.4.2 + + ++ New features: + + * Redesigned operating system emulation layer to make porting easier. + + * Better control over TCP output buffers. + + * Documenation added. + + ++ Bugfixes: + + * Locking issues in buffer management. + + * Bugfixes in the sequential API. + + * IP forwarding could cause memory leakage. This has been fixed. + + ++ Other changes: + + * Directory structure somewhat changed; the core/ tree has been + collapsed. + +(0.4.2) Changes since version 0.4.1 + + ++ New features: + + * Experimental ARP implementation added. + + * Skeleton Ethernet driver added. + + * Experimental BSD socket API library added. + + ++ Bugfixes: + + * In very intense situations, memory leakage could occur. This has + been fixed. + + ++ Other changes: + + * Variables named "data" and "code" have been renamed in order to + avoid name conflicts in certain compilers. + + * Variable++ have in appliciable cases been translated to ++variable + since some compilers generate better code in the latter case. + +(0.4.1) Changes since version 0.4 + + ++ New features: + + * TCP: Connection attempts time out earlier than data + transmissions. Nagle algorithm implemented. Push flag set on the + last segment in a burst. + + * UDP: experimental support for UDP-Lite extensions. + + ++ Bugfixes: + + * TCP: out of order segments were in some cases handled incorrectly, + and this has now been fixed. Delayed acknowledgements was broken + in 0.4, has now been fixed. Binding to an address that is in use + now results in an error. Reset connections sometimes hung an + application; this has been fixed. + + * Checksum calculation sometimes failed for chained pbufs with odd + lengths. This has been fixed. + + * API: a lot of bug fixes in the API. The UDP API has been improved + and tested. Error reporting and handling has been + improved. Logical flaws and race conditions for incoming TCP + connections has been found and removed. + + * Memory manager: alignment issues. Reallocating memory sometimes + failed, this has been fixed. + + * Generic library: bcopy was flawed and has been fixed. + + ++ Other changes: + + * API: all datatypes has been changed from generic ones such as + ints, to specified ones such as u16_t. Functions that return + errors now have the correct type (err_t). + + * General: A lot of code cleaned up and debugging code removed. Many + portability issues have been fixed. + + * The license was changed; the advertising clause was removed. + + * C64 port added. + + * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri + Kosunen, Mikael Caleres, and Frits Wilmink for reporting and + fixing bugs! + +(0.4) Changes since version 0.3.1 + + * Memory management has been radically changed; instead of + allocating memory from a shared heap, memory for objects that are + rapidly allocated and deallocated is now kept in pools. Allocation + and deallocation from those memory pools is very fast. The shared + heap is still present but is used less frequently. + + * The memory, memory pool, and packet buffer subsystems now support + 4-, 2-, or 1-byte alignment. + + * "Out of memory" situations are handled in a more robust way. + + * Stack usage has been reduced. + + * Easier configuration of lwIP parameters such as memory usage, + TTLs, statistics gathering, etc. All configuration parameters are + now kept in a single header file "lwipopts.h". + + * The directory structure has been changed slightly so that all + architecture specific files are kept under the src/arch + hierarchy. + + * Error propagation has been improved, both in the protocol modules + and in the API. + + * The code for the RTXC architecture has been implemented, tested + and put to use. + + * Bugs have been found and corrected in the TCP, UDP, IP, API, and + the Internet checksum modules. + + * Bugs related to porting between a 32-bit and a 16-bit architecture + have been found and corrected. + + * The license has been changed slightly to conform more with the + original BSD license, including the advertisement clause. + +(0.3.1) Changes since version 0.3 + + * Fix of a fatal bug in the buffer management. Pbufs with allocated + RAM never returned the RAM when the pbuf was deallocated. + + * TCP congestion control, window updates and retransmissions did not + work correctly. This has now been fixed. + + * Bugfixes in the API. + +(0.3) Changes since version 0.2 + + * New and improved directory structure. All include files are now + kept in a dedicated include/ directory. + + * The API now has proper error handling. A new function, + netconn_err(), now returns an error code for the connection in + case of errors. + + * Improvements in the memory management subsystem. The system now + keeps a pointer to the lowest free memory block. A new function, + mem_malloc2() tries to allocate memory once, and if it fails tries + to free some memory and retry the allocation. + + * Much testing has been done with limited memory + configurations. lwIP now does a better job when overloaded. + + * Some bugfixes and improvements to the buffer (pbuf) subsystem. + + * Many bugfixes in the TCP code: + + - Fixed a bug in tcp_close(). + + - The TCP receive window was incorrectly closed when out of + sequence segments was received. This has been fixed. + + - Connections are now timed-out of the FIN-WAIT-2 state. + + - The initial congestion window could in some cases be too + large. This has been fixed. + + - The retransmission queue could in some cases be screwed up. This + has been fixed. + + - TCP RST flag now handled correctly. + + - Out of sequence data was in some cases never delivered to the + application. This has been fixed. + + - Retransmitted segments now contain the correct acknowledgment + number and advertised window. + + - TCP retransmission timeout backoffs are not correctly computed + (ala BSD). After a number of retransmissions, TCP now gives up + the connection. + + * TCP connections now are kept on three lists, one for active + connections, one for listening connections, and one for + connections that are in TIME-WAIT. This greatly speeds up the fast + timeout processing for sending delayed ACKs. + + * TCP now provides proper feedback to the application when a + connection has been successfully set up. + + * More comments have been added to the code. The code has also been + somewhat cleaned up. + +(0.2) Initial public release. diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/COPYING b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/COPYING new file mode 100644 index 0000000..e23898b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/COPYING @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/FILES b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/FILES new file mode 100644 index 0000000..6625319 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/FILES @@ -0,0 +1,4 @@ +src/ - The source code for the lwIP TCP/IP stack. +doc/ - The documentation for lwIP. + +See also the FILES file in each subdirectory. diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/README b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/README new file mode 100644 index 0000000..a62cc4f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/README @@ -0,0 +1,89 @@ +INTRODUCTION + +lwIP is a small independent implementation of the TCP/IP protocol +suite that has been developed by Adam Dunkels at the Computer and +Networks Architectures (CNA) lab at the Swedish Institute of Computer +Science (SICS). + +The focus of the lwIP TCP/IP implementation is to reduce the RAM usage +while still having a full scale TCP. This making lwIP suitable for use +in embedded systems with tens of kilobytes of free RAM and room for +around 40 kilobytes of code ROM. + +FEATURES + + * IP (Internet Protocol) including packet forwarding over multiple network + interfaces + * ICMP (Internet Control Message Protocol) for network maintenance and debugging + * IGMP (Internet Group Management Protocol) for multicast traffic management + * UDP (User Datagram Protocol) including experimental UDP-lite extensions + * TCP (Transmission Control Protocol) with congestion control, RTT estimation + and fast recovery/fast retransmit + * Specialized raw/native API for enhanced performance + * Optional Berkeley-like socket API + * DNS (Domain names resolver) + * SNMP (Simple Network Management Protocol) + * DHCP (Dynamic Host Configuration Protocol) + * AUTOIP (for IPv4, conform with RFC 3927) + * PPP (Point-to-Point Protocol) + * ARP (Address Resolution Protocol) for Ethernet + +LICENSE + +lwIP is freely available under a BSD license. + +DEVELOPMENT + +lwIP has grown into an excellent TCP/IP stack for embedded devices, +and developers using the stack often submit bug fixes, improvements, +and additions to the stack to further increase its usefulness. + +Development of lwIP is hosted on Savannah, a central point for +software development, maintenance and distribution. Everyone can +help improve lwIP by use of Savannah's interface, CVS and the +mailing list. A core team of developers will commit changes to the +CVS source tree. + +The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and +contributions (such as platform ports) are in the 'contrib' module. + +See doc/savannah.txt for details on CVS server access for users and +developers. + +Last night's CVS tar ball can be downloaded from: + http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING] + +The current CVS trees are web-browsable: + http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/ + http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/ + +Submit patches and bugs via the lwIP project page: + http://savannah.nongnu.org/projects/lwip/ + + +DOCUMENTATION + +The original out-dated homepage of lwIP and Adam Dunkels' papers on +lwIP are at the official lwIP home page: + http://www.sics.se/~adam/lwip/ + +Self documentation of the source code is regularly extracted from the +current CVS sources and is available from this web page: + http://www.nongnu.org/lwip/ + +There is now a constantly growin wiki about lwIP at + http://lwip.wikia.com/wiki/LwIP_Wiki + +Also, there are mailing lists you can subscribe at + http://savannah.nongnu.org/mail/?group=lwip +plus searchable archives: + http://lists.nongnu.org/archive/html/lwip-users/ + http://lists.nongnu.org/archive/html/lwip-devel/ + +Reading Adam's papers, the files in docs/, browsing the source code +documentation and browsing the mailing list archives is a good way to +become familiar with the design of lwIP. + +Adam Dunkels +Leon Woestenberg + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/UPGRADING b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/UPGRADING new file mode 100644 index 0000000..6501107 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/UPGRADING @@ -0,0 +1,144 @@ +This file lists major changes between release versions that require +ports or applications to be changed. Use it to update a port or an +application written for an older version of lwIP to correctly work +with newer versions. + + +(CVS HEAD) + + * [Enter new changes just after this line - do not remove this line] + + ++ Application changes: + + * Replaced struct ip_addr by typedef ip_addr_t (struct ip_addr is kept for + compatibility to old applications, but will be removed in the future). + + * Renamed mem_realloc() to mem_trim() to prevent confusion with realloc() + + +++ Raw API: + * Changed the semantics of tcp_close() (since it was rather a + shutdown before): Now the application does *NOT* get any calls to the recv + callback (aside from NULL/closed) after calling tcp_close() + + * When calling tcp_abort() from a raw API TCP callback function, + make sure you return ERR_ABRT to prevent accessing unallocated memory. + (ERR_ABRT now means the applicaiton has called tcp_abort!) + + +++ Netconn API: + * Changed netconn_receive() and netconn_accept() to return + err_t, not a pointer to new data/netconn. + + +++ Socket API: + * LWIP_SO_RCVTIMEO: when accept() or recv() time out, they + now set errno to EWOULDBLOCK/EAGAIN, not ETIMEDOUT. + + * Added a minimal version of posix fctl() to have a + standardised way to set O_NONBLOCK for nonblocking sockets. + + +++ all APIs: + * correctly implemented SO(F)_REUSEADDR + + ++ Port changes + + +++ new files: + + * Added 4 new files: def.c, timers.c, timers.h, tcp_impl.h: + + * Moved stack-internal parts of tcp.h to tcp_impl.h, tcp.h now only contains + the actual application programmer's API + + * Separated timer implementation from sys.h/.c, moved to timers.h/.c; + Added timer implementation for NO_SYS==1, set NO_SYS_NO_TIMERS==1 if you + still want to use your own timer implementation for NO_SYS==0 (as before). + + +++ sys layer: + + * Converted mbox- and semaphore-functions to take pointers to sys_mbox_t/ + sys_sem_t; + + * Converted sys_mbox_new/sys_sem_new to take pointers and return err_t; + + * Added Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX to let sys.h use + binary semaphores instead of mutexes - as before) + + +++ new options: + + * Don't waste memory when chaining segments, added option TCP_OVERSIZE to + prevent creating many small pbufs when calling tcp_write with many small + blocks of data. Instead, pbufs are allocated larger than needed and the + space is used for later calls to tcp_write. + + * Added LWIP_NETIF_TX_SINGLE_PBUF to always copy to try to create single pbufs + in tcp_write/udp_send. + + * Added an additional option LWIP_ETHERNET to support ethernet without ARP + (necessary for pure PPPoE) + + * Add MEMP_SEPARATE_POOLS to place memory pools in separate arrays. This may + be used to place these pools into user-defined memory by using external + declaration. + + * Added TCP_SNDQUEUELOWAT corresponding to TCP_SNDLOWAT + + +++ new pools: + + * Netdb uses a memp pool for allocating memory when getaddrinfo() is called, + so MEMP_NUM_NETDB has to be set accordingly. + + * DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses a memp pool instead of the heap, so + MEMP_NUM_LOCALHOSTLIST has to be set accordingly. + + * Snmp-agent uses a memp pools instead of the heap, so MEMP_NUM_SNMP_* have + to be set accordingly. + + * PPPoE uses a MEMP pool instead of the heap, so MEMP_NUM_PPPOE_INTERFACES + has to be set accordingly + + * Integrated loopif into netif.c - loopif does not have to be created by the + port any more, just define LWIP_HAVE_LOOPIF to 1. + + * Added define LWIP_RAND() for lwip-wide randomization (needs to be defined + in cc.h, e.g. used by igmp) + + * Added printf-formatter X8_F to printf u8_t as hex + + * The heap now may be moved to user-defined memory by defining + LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address + + * added autoip_set_struct() and dhcp_set_struct() to let autoip and dhcp work + with user-allocated structs instead of calling mem_malloc + + * Added const char* name to mem- and memp-stats for easier debugging. + + * Calculate the TCP/UDP checksum while copying to only fetch data once: + Define LWIP_CHKSUM_COPY to a memcpy-like function that returns the checksum + + * Added SO_REUSE_RXTOALL to pass received UDP broadcast/multicast packets to + more than one pcb. + + * Changed the semantics of ARP_QUEUEING==0: ARP_QUEUEING now cannot be turned + off any more, if this is set to 0, only one packet (the most recent one) is + queued (like demanded by RFC 1122). + + + ++ Major bugfixes/improvements + + * Implemented tcp_shutdown() to only shut down one end of a connection + * Implemented shutdown() at socket- and netconn-level + * Added errorset support to select() + improved select speed overhead + * Merged pppd to v2.3.11 (including some backported bugfixes from 2.4.x) + * Added timer implementation for NO_SYS==1 (may be disabled with NO_SYS_NO_TIMERS==1 + * Use macros defined in ip_addr.h to work with IP addresses + * Implemented many nonblocking socket/netconn functions + * Fixed ARP input processing: only add a new entry if a request was directed as us + * mem_realloc() to mem_trim() to prevent confusion with realloc() + * Some improvements for AutoIP (don't route/forward link-local addresses, don't break + existing connections when assigning a routable address) + * Correctly handle remote side overrunning our rcv_wnd in ooseq case + * Removed packing from ip_addr_t, the packed version is now only used in protocol headers + * Corrected PBUF_POOL_BUFSIZE for ports where ETH_PAD_SIZE > 0 + * Added support for static ARP table entries + +(STABLE-1.3.2) + + * initial version of this file diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/FILES b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/FILES new file mode 100644 index 0000000..05d356f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/FILES @@ -0,0 +1,6 @@ +savannah.txt - How to obtain the current development source code. +contrib.txt - How to contribute to lwIP as a developer. +rawapi.txt - The documentation for the core API of lwIP. + Also provides an overview about the other APIs and multithreading. +snmp_agent.txt - The documentation for the lwIP SNMP agent. +sys_arch.txt - The documentation for a system abstraction layer of lwIP. diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/contrib.txt b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/contrib.txt new file mode 100644 index 0000000..39596fc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/contrib.txt @@ -0,0 +1,63 @@ +1 Introduction + +This document describes some guidelines for people participating +in lwIP development. + +2 How to contribute to lwIP + +Here is a short list of suggestions to anybody working with lwIP and +trying to contribute bug reports, fixes, enhancements, platform ports etc. +First of all as you may already know lwIP is a volunteer project so feedback +to fixes or questions might often come late. Hopefully the bug and patch tracking +features of Savannah help us not lose users' input. + +2.1 Source code style: + +1. do not use tabs. +2. indentation is two spaces per level (i.e. per tab). +3. end debug messages with a trailing newline (\n). +4. one space between keyword and opening bracket. +5. no space between function and opening bracket. +6. one space and no newline before opening curly braces of a block. +7. closing curly brace on a single line. +8. spaces surrounding assignment and comparisons. +9. don't initialize static and/or global variables to zero, the compiler takes care of that. +10. use current source code style as further reference. + +2.2 Source code documentation style: + +1. JavaDoc compliant and Doxygen compatible. +2. Function documentation above functions in .c files, not .h files. + (This forces you to synchronize documentation and implementation.) +3. Use current documentation style as further reference. + +2.3 Bug reports and patches: + +1. Make sure you are reporting bugs or send patches against the latest + sources. (From the latest release and/or the current CVS sources.) +2. If you think you found a bug make sure it's not already filed in the + bugtracker at Savannah. +3. If you have a fix put the patch on Savannah. If it is a patch that affects + both core and arch specific stuff please separate them so that the core can + be applied separately while leaving the other patch 'open'. The prefered way + is to NOT touch archs you can't test and let maintainers take care of them. + This is a good way to see if they are used at all - the same goes for unix + netifs except tapif. +4. Do not file a bug and post a fix to it to the patch area. Either a bug report + or a patch will be enough. + If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area. +5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two) + can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded + as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead + for reporting a compiler warning fix. +6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other + trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you + change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than + if it's not to the point and long :) so the chances for it to be applied are greater. + +2.4 Platform porters: + +1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and + you think it could benefit others[1] you might want discuss this on the mailing list. You + can also ask for CVS access to submit and maintain your port in the contrib CVS module. + \ No newline at end of file diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/rawapi.txt b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/rawapi.txt new file mode 100644 index 0000000..bd452cf --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/rawapi.txt @@ -0,0 +1,505 @@ +Raw TCP/IP interface for lwIP + +Authors: Adam Dunkels, Leon Woestenberg, Christiaan Simons + +lwIP provides three Application Program's Interfaces (APIs) for programs +to use for communication with the TCP/IP code: +* low-level "core" / "callback" or "raw" API. +* higher-level "sequential" API. +* BSD-style socket API. + +The sequential API provides a way for ordinary, sequential, programs +to use the lwIP stack. It is quite similar to the BSD socket API. The +model of execution is based on the blocking open-read-write-close +paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP +code and the application program must reside in different execution +contexts (threads). + +The socket API is a compatibility API for existing applications, +currently it is built on top of the sequential API. It is meant to +provide all functions needed to run socket API applications running +on other platforms (e.g. unix / windows etc.). However, due to limitations +in the specification of this API, there might be incompatibilities +that require small modifications of existing programs. + +** Threading + +lwIP started targeting single-threaded environments. When adding multi- +threading support, instead of making the core thread-safe, another +approach was chosen: there is one main thread running the lwIP core +(also known as the "tcpip_thread"). The raw API may only be used from +this thread! Application threads using the sequential- or socket API +communicate with this main thread through message passing. + + As such, the list of functions that may be called from + other threads or an ISR is very limited! Only functions + from these API header files are thread-safe: + - api.h + - netbuf.h + - netdb.h + - netifapi.h + - sockets.h + - sys.h + + Additionaly, memory (de-)allocation functions may be + called from multiple threads (not ISR!) with NO_SYS=0 + since they are protected by SYS_LIGHTWEIGHT_PROT and/or + semaphores. + + Only since 1.3.0, if SYS_LIGHTWEIGHT_PROT is set to 1 + and LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT is set to 1, + pbuf_free() may also be called from another thread or + an ISR (since only then, mem_free - for PBUF_RAM - may + be called from an ISR: otherwise, the HEAP is only + protected by semaphores). + + +** The remainder of this document discusses the "raw" API. ** + +The raw TCP/IP interface allows the application program to integrate +better with the TCP/IP code. Program execution is event based by +having callback functions being called from within the TCP/IP +code. The TCP/IP code and the application program both run in the same +thread. The sequential API has a much higher overhead and is not very +well suited for small systems since it forces a multithreaded paradigm +on the application. + +The raw TCP/IP interface is not only faster in terms of code execution +time but is also less memory intensive. The drawback is that program +development is somewhat harder and application programs written for +the raw TCP/IP interface are more difficult to understand. Still, this +is the preferred way of writing applications that should be small in +code size and memory usage. + +Both APIs can be used simultaneously by different application +programs. In fact, the sequential API is implemented as an application +program using the raw TCP/IP interface. + +--- Callbacks + +Program execution is driven by callbacks. Each callback is an ordinary +C function that is called from within the TCP/IP code. Every callback +function is passed the current TCP or UDP connection state as an +argument. Also, in order to be able to keep program specific state, +the callback functions are called with a program specified argument +that is independent of the TCP/IP state. + +The function for setting the application connection state is: + +- void tcp_arg(struct tcp_pcb *pcb, void *arg) + + Specifies the program specific state that should be passed to all + other callback functions. The "pcb" argument is the current TCP + connection control block, and the "arg" argument is the argument + that will be passed to the callbacks. + + +--- TCP connection setup + +The functions used for setting up connections is similar to that of +the sequential API and of the BSD socket API. A new TCP connection +identifier (i.e., a protocol control block - PCB) is created with the +tcp_new() function. This PCB can then be either set to listen for new +incoming connections or be explicitly connected to another host. + +- struct tcp_pcb *tcp_new(void) + + Creates a new connection identifier (PCB). If memory is not + available for creating the new pcb, NULL is returned. + +- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port) + + Binds the pcb to a local IP address and port number. The IP address + can be specified as IP_ADDR_ANY in order to bind the connection to + all local IP addresses. + + If another connection is bound to the same port, the function will + return ERR_USE, otherwise ERR_OK is returned. + +- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb) + + Commands a pcb to start listening for incoming connections. When an + incoming connection is accepted, the function specified with the + tcp_accept() function will be called. The pcb will have to be bound + to a local port with the tcp_bind() function. + + The tcp_listen() function returns a new connection identifier, and + the one passed as an argument to the function will be + deallocated. The reason for this behavior is that less memory is + needed for a connection that is listening, so tcp_listen() will + reclaim the memory needed for the original connection and allocate a + new smaller memory block for the listening connection. + + tcp_listen() may return NULL if no memory was available for the + listening connection. If so, the memory associated with the pcb + passed as an argument to tcp_listen() will not be deallocated. + +- struct tcp_pcb *tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog) + + Same as tcp_listen, but limits the number of outstanding connections + in the listen queue to the value specified by the backlog argument. + To use it, your need to set TCP_LISTEN_BACKLOG=1 in your lwipopts.h. + +- void tcp_accepted(struct tcp_pcb *pcb) + + Inform lwIP that an incoming connection has been accepted. This would + usually be called from the accept callback. This allows lwIP to perform + housekeeping tasks, such as allowing further incoming connections to be + queued in the listen backlog. + +- void tcp_accept(struct tcp_pcb *pcb, + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, + err_t err)) + + Specified the callback function that should be called when a new + connection arrives on a listening connection. + +- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port, err_t (* connected)(void *arg, + struct tcp_pcb *tpcb, + err_t err)); + + Sets up the pcb to connect to the remote host and sends the + initial SYN segment which opens the connection. + + The tcp_connect() function returns immediately; it does not wait for + the connection to be properly setup. Instead, it will call the + function specified as the fourth argument (the "connected" argument) + when the connection is established. If the connection could not be + properly established, either because the other host refused the + connection or because the other host didn't answer, the "err" + callback function of this pcb (registered with tcp_err, see below) + will be called. + + The tcp_connect() function can return ERR_MEM if no memory is + available for enqueueing the SYN segment. If the SYN indeed was + enqueued successfully, the tcp_connect() function returns ERR_OK. + + +--- Sending TCP data + +TCP data is sent by enqueueing the data with a call to +tcp_write(). When the data is successfully transmitted to the remote +host, the application will be notified with a call to a specified +callback function. + +- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len, + u8_t copy) + + Enqueues the data pointed to by the argument dataptr. The length of + the data is passed as the len parameter. The copy argument is either + 0 or 1 and indicates whether the new memory should be allocated for + the data to be copied into. If the argument is 0, no new memory + should be allocated and the data should only be referenced by + pointer. + + The tcp_write() function will fail and return ERR_MEM if the length + of the data exceeds the current send buffer size or if the length of + the queue of outgoing segment is larger than the upper limit defined + in lwipopts.h. The number of bytes available in the output queue can + be retrieved with the tcp_sndbuf() function. + + The proper way to use this function is to call the function with at + most tcp_sndbuf() bytes of data. If the function returns ERR_MEM, + the application should wait until some of the currently enqueued + data has been successfully received by the other host and try again. + +- void tcp_sent(struct tcp_pcb *pcb, + err_t (* sent)(void *arg, struct tcp_pcb *tpcb, + u16_t len)) + + Specifies the callback function that should be called when data has + successfully been received (i.e., acknowledged) by the remote + host. The len argument passed to the callback function gives the + amount bytes that was acknowledged by the last acknowledgment. + + +--- Receiving TCP data + +TCP data reception is callback based - an application specified +callback function is called when new data arrives. When the +application has taken the data, it has to call the tcp_recved() +function to indicate that TCP can advertise increase the receive +window. + +- void tcp_recv(struct tcp_pcb *pcb, + err_t (* recv)(void *arg, struct tcp_pcb *tpcb, + struct pbuf *p, err_t err)) + + Sets the callback function that will be called when new data + arrives. The callback function will be passed a NULL pbuf to + indicate that the remote host has closed the connection. If + there are no errors and the callback function is to return + ERR_OK, then it must free the pbuf. Otherwise, it must not + free the pbuf so that lwIP core code can store it. + +- void tcp_recved(struct tcp_pcb *pcb, u16_t len) + + Must be called when the application has received the data. The len + argument indicates the length of the received data. + + +--- Application polling + +When a connection is idle (i.e., no data is either transmitted or +received), lwIP will repeatedly poll the application by calling a +specified callback function. This can be used either as a watchdog +timer for killing connections that have stayed idle for too long, or +as a method of waiting for memory to become available. For instance, +if a call to tcp_write() has failed because memory wasn't available, +the application may use the polling functionality to call tcp_write() +again when the connection has been idle for a while. + +- void tcp_poll(struct tcp_pcb *pcb, + err_t (* poll)(void *arg, struct tcp_pcb *tpcb), + u8_t interval) + + Specifies the polling interval and the callback function that should + be called to poll the application. The interval is specified in + number of TCP coarse grained timer shots, which typically occurs + twice a second. An interval of 10 means that the application would + be polled every 5 seconds. + + +--- Closing and aborting connections + +- err_t tcp_close(struct tcp_pcb *pcb) + + Closes the connection. The function may return ERR_MEM if no memory + was available for closing the connection. If so, the application + should wait and try again either by using the acknowledgment + callback or the polling functionality. If the close succeeds, the + function returns ERR_OK. + + The pcb is deallocated by the TCP code after a call to tcp_close(). + +- void tcp_abort(struct tcp_pcb *pcb) + + Aborts the connection by sending a RST (reset) segment to the remote + host. The pcb is deallocated. This function never fails. + + ATTENTION: When calling this from one of the TCP callbacks, make + sure you always return ERR_ABRT (and never return ERR_ABRT otherwise + or you will risk accessing deallocated memory or memory leaks! + + +If a connection is aborted because of an error, the application is +alerted of this event by the err callback. Errors that might abort a +connection are when there is a shortage of memory. The callback +function to be called is set using the tcp_err() function. + +- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg, + err_t err)) + + The error callback function does not get the pcb passed to it as a + parameter since the pcb may already have been deallocated. + + +--- Lower layer TCP interface + +TCP provides a simple interface to the lower layers of the +system. During system initialization, the function tcp_init() has +to be called before any other TCP function is called. When the system +is running, the two timer functions tcp_fasttmr() and tcp_slowtmr() +must be called with regular intervals. The tcp_fasttmr() should be +called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and +tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. + + +--- UDP interface + +The UDP interface is similar to that of TCP, but due to the lower +level of complexity of UDP, the interface is significantly simpler. + +- struct udp_pcb *udp_new(void) + + Creates a new UDP pcb which can be used for UDP communication. The + pcb is not active until it has either been bound to a local address + or connected to a remote address. + +- void udp_remove(struct udp_pcb *pcb) + + Removes and deallocates the pcb. + +- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port) + + Binds the pcb to a local address. The IP-address argument "ipaddr" + can be IP_ADDR_ANY to indicate that it should listen to any local IP + address. The function currently always return ERR_OK. + +- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port) + + Sets the remote end of the pcb. This function does not generate any + network traffic, but only set the remote address of the pcb. + +- err_t udp_disconnect(struct udp_pcb *pcb) + + Remove the remote end of the pcb. This function does not generate + any network traffic, but only removes the remote address of the pcb. + +- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p) + + Sends the pbuf p. The pbuf is not deallocated. + +- void udp_recv(struct udp_pcb *pcb, + void (* recv)(void *arg, struct udp_pcb *upcb, + struct pbuf *p, + struct ip_addr *addr, + u16_t port), + void *recv_arg) + + Specifies a callback function that should be called when a UDP + datagram is received. + + +--- System initalization + +A truly complete and generic sequence for initializing the lwip stack +cannot be given because it depends on the build configuration (lwipopts.h) +and additional initializations for your runtime environment (e.g. timers). + +We can give you some idea on how to proceed when using the raw API. +We assume a configuration using a single Ethernet netif and the +UDP and TCP transport layers, IPv4 and the DHCP client. + +Call these functions in the order of appearance: + +- stats_init() + + Clears the structure where runtime statistics are gathered. + +- sys_init() + + Not of much use since we set the NO_SYS 1 option in lwipopts.h, + to be called for easy configuration changes. + +- mem_init() + + Initializes the dynamic memory heap defined by MEM_SIZE. + +- memp_init() + + Initializes the memory pools defined by MEMP_NUM_x. + +- pbuf_init() + + Initializes the pbuf memory pool defined by PBUF_POOL_SIZE. + +- etharp_init() + + Initializes the ARP table and queue. + Note: you must call etharp_tmr at a ARP_TMR_INTERVAL (5 seconds) regular interval + after this initialization. + +- ip_init() + + Doesn't do much, it should be called to handle future changes. + +- udp_init() + + Clears the UDP PCB list. + +- tcp_init() + + Clears the TCP PCB list and clears some internal TCP timers. + Note: you must call tcp_fasttmr() and tcp_slowtmr() at the + predefined regular intervals after this initialization. + +- netif_add(struct netif *netif, struct ip_addr *ipaddr, + struct ip_addr *netmask, struct ip_addr *gw, + void *state, err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif)) + + Adds your network interface to the netif_list. Allocate a struct + netif and pass a pointer to this structure as the first argument. + Give pointers to cleared ip_addr structures when using DHCP, + or fill them with sane numbers otherwise. The state pointer may be NULL. + + The init function pointer must point to a initialization function for + your ethernet netif interface. The following code illustrates it's use. + + err_t netif_if_init(struct netif *netif) + { + u8_t i; + + for(i = 0; i < ETHARP_HWADDR_LEN; i++) netif->hwaddr[i] = some_eth_addr[i]; + init_my_eth_device(); + return ERR_OK; + } + + For ethernet drivers, the input function pointer must point to the lwip + function ethernet_input() declared in "netif/etharp.h". Other drivers + must use ip_input() declared in "lwip/ip.h". + +- netif_set_default(struct netif *netif) + + Registers the default network interface. + +- netif_set_up(struct netif *netif) + + When the netif is fully configured this function must be called. + +- dhcp_start(struct netif *netif) + + Creates a new DHCP client for this interface on the first call. + Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at + the predefined regular intervals after starting the client. + + You can peek in the netif->dhcp struct for the actual DHCP status. + + +--- Optimalization hints + +The first thing you want to optimize is the lwip_standard_checksum() +routine from src/core/inet.c. You can override this standard +function with the #define LWIP_CHKSUM . + +There are C examples given in inet.c or you might want to +craft an assembly function for this. RFC1071 is a good +introduction to this subject. + +Other significant improvements can be made by supplying +assembly or inline replacements for htons() and htonl() +if you're using a little-endian architecture. +#define LWIP_PLATFORM_BYTESWAP 1 +#define LWIP_PLATFORM_HTONS(x) +#define LWIP_PLATFORM_HTONL(x) + +Check your network interface driver if it reads at +a higher speed than the maximum wire-speed. If the +hardware isn't serviced frequently and fast enough +buffer overflows are likely to occur. + +E.g. when using the cs8900 driver, call cs8900if_service(ethif) +as frequently as possible. When using an RTOS let the cs8900 interrupt +wake a high priority task that services your driver using a binary +semaphore or event flag. Some drivers might allow additional tuning +to match your application and network. + +For a production release it is recommended to set LWIP_STATS to 0. +Note that speed performance isn't influenced much by simply setting +high values to the memory options. + +For more optimization hints take a look at the lwIP wiki. + +--- Zero-copy MACs + +To achieve zero-copy on transmit, the data passed to the raw API must +remain unchanged until sent. Because the send- (or write-)functions return +when the packets have been enqueued for sending, data must be kept stable +after that, too. + +This implies that PBUF_RAM/PBUF_POOL pbufs passed to raw-API send functions +must *not* be reused by the application unless their ref-count is 1. + +For no-copy pbufs (PBUF_ROM/PBUF_REF), data must be kept unchanged, too, +but the stack/driver will/must copy PBUF_REF'ed data when enqueueing, while +PBUF_ROM-pbufs are just enqueued (as ROM-data is expected to never change). + +Also, data passed to tcp_write without the copy-flag must not be changed! + +Therefore, be careful which type of PBUF you use and if you copy TCP data +or not! diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/savannah.txt b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/savannah.txt new file mode 100644 index 0000000..409905b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/savannah.txt @@ -0,0 +1,135 @@ +Daily Use Guide for using Savannah for lwIP + +Table of Contents: + +1 - Obtaining lwIP from the CVS repository +2 - Committers/developers CVS access using SSH (to be written) +3 - Merging from DEVEL branch to main trunk (stable branch) +4 - How to release lwIP + + + +1 Obtaining lwIP from the CVS repository +---------------------------------------- + +To perform an anonymous CVS checkout of the main trunk (this is where +bug fixes and incremental enhancements occur), do this: + +cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout lwip + +Or, obtain a stable branch (updated with bug fixes only) as follows: +cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ + -r STABLE-0_7 -d lwip-0.7 lwip + +Or, obtain a specific (fixed) release as follows: +cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ + -r STABLE-0_7_0 -d lwip-0.7.0 lwip + +3 Committers/developers CVS access using SSH +-------------------------------------------- + +The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption. +As such, CVS commits to the server occur through a SSH tunnel for project members. +To create a SSH2 key pair in UNIX-like environments, do this: + +ssh-keygen -t dsa + +Under Windows, a recommended SSH client is "PuTTY", freely available with good +documentation and a graphic user interface. Use its key generator. + +Now paste the id_dsa.pub contents into your Savannah account public key list. Wait +a while so that Savannah can update its configuration (This can take minutes). + +Try to login using SSH: + +ssh -v your_login@cvs.sv.gnu.org + +If it tells you: + +Authenticating with public key "your_key_name"... +Server refused to allocate pty + +then you could login; Savannah refuses to give you a shell - which is OK, as we +are allowed to use SSH for CVS only. Now, you should be able to do this: + +export CVS_RSH=ssh +cvs -z3 -d:ext:your_login@cvs.sv.gnu.org:/sources/lwip co lwip + +after which you can edit your local files with bug fixes or new features and +commit them. Make sure you know what you are doing when using CVS to make +changes on the repository. If in doubt, ask on the lwip-members mailing list. + +(If SSH asks about authenticity of the host, you can check the key + fingerprint against http://savannah.nongnu.org/cvs/?group=lwip) + + +3 Merging from DEVEL branch to main trunk (stable) +-------------------------------------------------- + +Merging is a delicate process in CVS and requires the +following disciplined steps in order to prevent conflicts +in the future. Conflicts can be hard to solve! + +Merging from branch A to branch B requires that the A branch +has a tag indicating the previous merger. This tag is called +'merged_from_A_to_B'. After merging, the tag is moved in the +A branch to remember this merger for future merge actions. + +IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE +REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE +MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME). + +Merge all changes in DEVEL since our last merge to main: + +In the working copy of the main trunk: +cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL + +(This will apply the changes between 'merged_from_DEVEL_to_main' +and 'DEVEL' to your work set of files) + +We can now commit the merge result. +cvs commit -R -m "Merged from DEVEL to main." + +If this worked out OK, we now move the tag in the DEVEL branch +to this merge point, so we can use this point for future merges: + +cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip + +4 How to release lwIP +--------------------- + +First, checkout a clean copy of the branch to be released. Tag this set with +tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example). + +Login CVS using pserver authentication, then export a clean copy of the +tagged tree. Export is similar to a checkout, except that the CVS metadata +is not created locally. + +export CVS_RSH=ssh +cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ + -r STABLE-0_6_3 -d lwip-0.6.3 lwip + +Archive this directory using tar, gzip'd, bzip2'd and zip'd. + +tar czvf lwip-0.6.3.tar.gz lwip-0.6.3 +tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3 +zip -r lwip-0.6.3.zip lwip-0.6.3 + +Now, sign the archives with a detached GPG binary signature as follows: + +gpg -b lwip-0.6.3.tar.gz +gpg -b lwip-0.6.3.tar.bz2 +gpg -b lwip-0.6.3.zip + +Upload these files using anonymous FTP: +ncftp ftp://savannah.gnu.org/incoming/savannah/lwip + +ncftp>mput *0.6.3.* + +Additionally, you may post a news item on Savannah, like this: + +A new 0.6.3 release is now available here: +http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3 + +You will have to submit this via the user News interface, then approve +this via the Administrator News interface. \ No newline at end of file diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/snmp_agent.txt b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/snmp_agent.txt new file mode 100644 index 0000000..2653230 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/snmp_agent.txt @@ -0,0 +1,181 @@ +SNMPv1 agent for lwIP + +Author: Christiaan Simons + +This is a brief introduction how to use and configure the SNMP agent. +Note the agent uses the raw-API UDP interface so you may also want to +read rawapi.txt to gain a better understanding of the SNMP message handling. + +0 Agent Capabilities +==================== + +SNMPv1 per RFC1157 + This is an old(er) standard but is still widely supported. + For SNMPv2c and v3 have a greater complexity and need many + more lines of code. IMHO this breaks the idea of "lightweight IP". + + Note the S in SNMP stands for "Simple". Note that "Simple" is + relative. SNMP is simple compared to the complex ISO network + management protocols CMIP (Common Management Information Protocol) + and CMOT (CMip Over Tcp). + +MIB II per RFC1213 + The standard lwIP stack management information base. + This is a required MIB, so this is always enabled. + When builing lwIP without TCP, the mib-2.tcp group is omitted. + The groups EGP, CMOT and transmission are disabled by default. + + Most mib-2 objects are not writable except: + sysName, sysLocation, sysContact, snmpEnableAuthenTraps. + Writing to or changing the ARP and IP address and route + tables is not possible. + + Note lwIP has a very limited notion of IP routing. It currently + doen't have a route table and doesn't have a notion of the U,G,H flags. + Instead lwIP uses the interface list with only one default interface + acting as a single gateway interface (G) for the default route. + + The agent returns a "virtual table" with the default route 0.0.0.0 + for the default interface and network routes (no H) for each + network interface in the netif_list. + All routes are considered to be up (U). + +Loading additional MIBs + MIBs can only be added in compile-time, not in run-time. + There is no MIB compiler thus additional MIBs must be hand coded. + +Large SNMP message support + The packet decoding and encoding routines are designed + to use pbuf-chains. Larger payloads than the minimum + SNMP requirement of 484 octets are supported if the + PBUF_POOL_SIZE and IP_REASS_BUFSIZE are set to match your + local requirement. + +1 Building the Agent +==================== + +First of all you'll need to add the following define +to your local lwipopts.h: + +#define LWIP_SNMP 1 + +and add the source files in lwip/src/core/snmp +and some snmp headers in lwip/src/include/lwip to your makefile. + +Note you'll might need to adapt you network driver to update +the mib2 variables for your interface. + +2 Running the Agent +=================== + +The following function calls must be made in your program to +actually get the SNMP agent running. + +Before starting the agent you should supply pointers +to non-volatile memory for sysContact, sysLocation, +and snmpEnableAuthenTraps. You can do this by calling + +snmp_set_syscontact() +snmp_set_syslocation() +snmp_set_snmpenableauthentraps() + +Additionally you may want to set + +snmp_set_sysdescr() +snmp_set_sysobjid() (if you have a private MIB) +snmp_set_sysname() + +Also before starting the agent you need to setup +one or more trap destinations using these calls: + +snmp_trap_dst_enable(); +snmp_trap_dst_ip_set(); + +In the lwIP initialisation sequence call snmp_init() just after +the call to udp_init(). + +Exactly every 10 msec the SNMP uptime timestamp must be updated with +snmp_inc_sysuptime(). You should call this from a timer interrupt +or a timer signal handler depending on your runtime environment. + +An alternative way to update the SNMP uptime timestamp is to do a call like +snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but call to +a lower frequency). Another one is to not call snmp_inc_sysuptime() or +snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro. +This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside +snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only +when it's queried (any function which need "sysuptime" have to call +snmp_get_sysuptime). + + +3 Private MIBs +============== + +If want to extend the agent with your own private MIB you'll need to +add the following define to your local lwipopts.h: + +#define SNMP_PRIVATE_MIB 1 + +You must provide the private_mib.h and associated files yourself. +Note we don't have a "MIB compiler" that generates C source from a MIB, +so you're required to do some serious coding if you enable this! + +Note the lwIP enterprise ID (26381) is assigned to the lwIP project, +ALL OBJECT IDENTIFIERS LIVING UNDER THIS ID ARE ASSIGNED BY THE lwIP +MAINTAINERS! + +If you need to create your own private MIB you'll need +to apply for your own enterprise ID with IANA: http://www.iana.org/numbers.html + +You can set it by passing a struct snmp_obj_id to the agent +using snmp_set_sysobjid(&my_object_id), just before snmp_init(). + +Note the object identifiers for thes MIB-2 and your private MIB +tree must be kept in sorted ascending (lexicographical) order. +This to ensure correct getnext operation. + +An example for a private MIB is part of the "minimal Unix" project: +contrib/ports/unix/proj/minimal/lwip_prvmib.c + +The next chapter gives a more detailed description of the +MIB-2 tree and the optional private MIB. + +4 The Gory Details +================== + +4.0 Object identifiers and the MIB tree. + +We have three distinct parts for all object identifiers: + +The prefix + .iso.org.dod.internet + +the middle part + .mgmt.mib-2.ip.ipNetToMediaTable.ipNetToMediaEntry.ipNetToMediaPhysAddress + +and the index part + .1.192.168.0.1 + +Objects located above the .internet hierarchy aren't supported. +Currently only the .mgmt sub-tree is available and +when the SNMP_PRIVATE_MIB is enabled the .private tree +becomes available too. + +Object identifiers from incoming requests are checked +for a matching prefix, middle part and index part +or are expanded(*) for GetNext requests with short +or inexisting names in the request. +(* we call this "expansion" but this also +resembles the "auto-completion" operation) + +The middle part is usually located in ROM (const) +to preserve precious RAM on small microcontrollers. +However RAM location is possible for a dynamically +changing private tree. + +The index part is handled by functions which in +turn use dynamically allocated index trees from RAM. +These trees are updated by e.g. the etharp code +when new entries are made or removed form the ARP cache. + +/** @todo more gory details */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/sys_arch.txt b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/sys_arch.txt new file mode 100644 index 0000000..38377b6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/doc/sys_arch.txt @@ -0,0 +1,216 @@ +sys_arch interface for lwIP 0.6++ + +Author: Adam Dunkels + +The operating system emulation layer provides a common interface +between the lwIP code and the underlying operating system kernel. The +general idea is that porting lwIP to new architectures requires only +small changes to a few header files and a new sys_arch +implementation. It is also possible to do a sys_arch implementation +that does not rely on any underlying operating system. + +The sys_arch provides semaphores and mailboxes to lwIP. For the full +lwIP functionality, multiple threads support can be implemented in the +sys_arch, but this is not required for the basic lwIP +functionality. Previous versions of lwIP required the sys_arch to +implement timer scheduling as well but as of lwIP 0.5 this is +implemented in a higher layer. + +In addition to the source file providing the functionality of sys_arch, +the OS emulation layer must provide several header files defining +macros used throughout lwip. The files required and the macros they +must define are listed below the sys_arch description. + +Semaphores can be either counting or binary - lwIP works with both +kinds. Mailboxes are used for message passing and can be implemented +either as a queue which allows multiple messages to be posted to a +mailbox, or as a rendez-vous point where only one message can be +posted at a time. lwIP works with both kinds, but the former type will +be more efficient. A message in a mailbox is just a pointer, nothing +more. + +Semaphores are represented by the type "sys_sem_t" which is typedef'd +in the sys_arch.h file. Mailboxes are equivalently represented by the +type "sys_mbox_t". lwIP does not place any restrictions on how +sys_sem_t or sys_mbox_t are represented internally. + +The following functions must be implemented by the sys_arch: + +- void sys_init(void) + + Is called to initialize the sys_arch layer. + +- sys_sem_t sys_sem_new(u8_t count) + + Creates and returns a new semaphore. The "count" argument specifies + the initial state of the semaphore. + +- void sys_sem_free(sys_sem_t sem) + + Deallocates a semaphore. + +- void sys_sem_signal(sys_sem_t sem) + + Signals a semaphore. + +- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) + + Blocks the thread while waiting for the semaphore to be + signaled. If the "timeout" argument is non-zero, the thread should + only be blocked for the specified time (measured in + milliseconds). If the "timeout" argument is zero, the thread should be + blocked until the semaphore is signalled. + + If the timeout argument is non-zero, the return value is the number of + milliseconds spent waiting for the semaphore to be signaled. If the + semaphore wasn't signaled within the specified time, the return value is + SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore + (i.e., it was already signaled), the function may return zero. + + Notice that lwIP implements a function with a similar name, + sys_sem_wait(), that uses the sys_arch_sem_wait() function. + +- sys_mbox_t sys_mbox_new(int size) + + Creates an empty mailbox for maximum "size" elements. Elements stored + in mailboxes are pointers. You have to define macros "_MBOX_SIZE" + in your lwipopts.h, or ignore this parameter in your implementation + and use a default size. + +- void sys_mbox_free(sys_mbox_t mbox) + + Deallocates a mailbox. If there are messages still present in the + mailbox when the mailbox is deallocated, it is an indication of a + programming error in lwIP and the developer should be notified. + +- void sys_mbox_post(sys_mbox_t mbox, void *msg) + + Posts the "msg" to the mailbox. This function have to block until + the "msg" is really posted. + +- err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg) + + Try to post the "msg" to the mailbox. Returns ERR_MEM if this one + is full, else, ERR_OK if the "msg" is posted. + +- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout) + + Blocks the thread until a message arrives in the mailbox, but does + not block the thread longer than "timeout" milliseconds (similar to + the sys_arch_sem_wait() function). If "timeout" is 0, the thread should + be blocked until a message arrives. The "msg" argument is a result + parameter that is set by the function (i.e., by doing "*msg = + ptr"). The "msg" parameter maybe NULL to indicate that the message + should be dropped. + + The return values are the same as for the sys_arch_sem_wait() function: + Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a + timeout. + + Note that a function with a similar name, sys_mbox_fetch(), is + implemented by lwIP. + +- u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg) + + This is similar to sys_arch_mbox_fetch, however if a message is not + present in the mailbox, it immediately returns with the code + SYS_MBOX_EMPTY. On success 0 is returned. + + To allow for efficient implementations, this can be defined as a + function-like macro in sys_arch.h instead of a normal function. For + example, a naive implementation could be: + #define sys_arch_mbox_tryfetch(mbox,msg) \ + sys_arch_mbox_fetch(mbox,msg,1) + although this would introduce unnecessary delays. + +If threads are supported by the underlying operating system and if +such functionality is needed in lwIP, the following function will have +to be implemented as well: + +- sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio) + + Starts a new thread named "name" with priority "prio" that will begin its + execution in the function "thread()". The "arg" argument will be passed as an + argument to the thread() function. The stack size to used for this thread is + the "stacksize" parameter. The id of the new thread is returned. Both the id + and the priority are system dependent. + +- sys_prot_t sys_arch_protect(void) + + This optional function does a "fast" critical region protection and returns + the previous protection level. This function is only called during very short + critical regions. An embedded system which supports ISR-based drivers might + want to implement this function by disabling interrupts. Task-based systems + might want to implement this by using a mutex or disabling tasking. This + function should support recursive calls from the same task or interrupt. In + other words, sys_arch_protect() could be called while already protected. In + that case the return value indicates that it is already protected. + + sys_arch_protect() is only required if your port is supporting an operating + system. + +- void sys_arch_unprotect(sys_prot_t pval) + + This optional function does a "fast" set of critical region protection to the + value specified by pval. See the documentation for sys_arch_protect() for + more information. This function is only required if your port is supporting + an operating system. + +Note: + +Be carefull with using mem_malloc() in sys_arch. When malloc() refers to +mem_malloc() you can run into a circular function call problem. In mem.c +mem_init() tries to allcate a semaphore using mem_malloc, which of course +can't be performed when sys_arch uses mem_malloc. + +------------------------------------------------------------------------------- +Additional files required for the "OS support" emulation layer: +------------------------------------------------------------------------------- + +cc.h - Architecture environment, some compiler specific, some + environment specific (probably should move env stuff + to sys_arch.h.) + + Typedefs for the types used by lwip - + u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t + + Compiler hints for packing lwip's structures - + PACK_STRUCT_FIELD(x) + PACK_STRUCT_STRUCT + PACK_STRUCT_BEGIN + PACK_STRUCT_END + + Platform specific diagnostic output - + LWIP_PLATFORM_DIAG(x) - non-fatal, print a message. + LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution. + Portability defines for printf formatters: + U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F + + "lightweight" synchronization mechanisms - + SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable. + SYS_ARCH_PROTECT(x) - enter protection mode. + SYS_ARCH_UNPROTECT(x) - leave protection mode. + + If the compiler does not provide memset() this file must include a + definition of it, or include a file which defines it. + + This file must either include a system-local which defines + the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO + to make lwip/arch.h define the codes which are used throughout. + + +perf.h - Architecture specific performance measurement. + Measurement calls made throughout lwip, these can be defined to nothing. + PERF_START - start measuring something. + PERF_STOP(x) - stop measuring something, and record the result. + +sys_arch.h - Tied to sys_arch.c + + Arch dependent types for the following objects: + sys_sem_t, sys_mbox_t, sys_thread_t, + And, optionally: + sys_prot_t + + Defines to set vars of sys_mbox_t and sys_sem_t to NULL. + SYS_MBOX_NULL NULL + SYS_SEM_NULL NULL diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/SP605_PHY.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/SP605_PHY.c new file mode 100644 index 0000000..003af44 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/SP605_PHY.c @@ -0,0 +1,163 @@ +/* + * Code provided by Xilinx. + */ + +/* BSP includes. */ +#include "xemaclite.h" + +/* lwIP includes. */ +#include "lwip/opt.h" + + +/* Advertisement control register. */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_100_AND_10 (ADVERTISE_10FULL | ADVERTISE_100FULL | ADVERTISE_10HALF | ADVERTISE_100HALF) + +/* PHY registers/offsets. */ +#define IEEE_CONTROL_REG_OFFSET 0 +#define IEEE_STATUS_REG_OFFSET 1 +#define IEEE_AUTONEGO_ADVERTISE_REG 4 +#define IEEE_PARTNER_ABILITIES_1_REG_OFFSET 5 +#define IEEE_PARTNER_ABILITIES_3_REG_OFFSET 10 +#define IEEE_1000_ADVERTISE_REG_OFFSET 9 +#define IEEE_CTRL_1GBPS_LINKSPEED_MASK 0x2040 +#define IEEE_CTRL_LINKSPEED_MASK 0x0040 +#define IEEE_CTRL_LINKSPEED_1000M 0x0040 +#define IEEE_CTRL_LINKSPEED_100M 0x2000 +#define IEEE_CTRL_LINKSPEED_10M 0x0000 +#define IEEE_CTRL_AUTONEGOTIATE_ENABLE 0x1000 +#define IEEE_STAT_AUTONEGOTIATE_CAPABLE 0x0008 +#define IEEE_STAT_AUTONEGOTIATE_COMPLETE 0x0020 +#define IEEE_STAT_AUTONEGOTIATE_RESTART 0x0200 +#define IEEE_STAT_1GBPS_EXTENSIONS 0x0100 +#define IEEE_AN3_ABILITY_MASK_1GBPS 0x0C00 +#define IEEE_AN1_ABILITY_MASK_100MBPS 0x0380 +#define IEEE_AN1_ABILITY_MASK_10MBPS 0x0060 + +#define PHY_DETECT_REG 1 +#define PHY_DETECT_MASK 0x1808 + +static int detect_phy_emaclite(XEmacLite *pxEMACLiteInstance); + +unsigned short vInitialisePHY( XEmacLite *pxEMACLiteInstance ) +{ +u16 control; +u16 status; +u16 partner_capabilities; +u16 partner_capabilities_1000; +u16 phylinkspeed; +u32 phy_addr = detect_phy_emaclite(pxEMACLiteInstance); + + /* Dont advertise PHY speed of 1000 Mbps */ + XEmacLite_PhyWrite(pxEMACLiteInstance, phy_addr, + IEEE_1000_ADVERTISE_REG_OFFSET, + 0); + /* Advertise PHY speed of 100 and 10 Mbps */ + XEmacLite_PhyWrite(pxEMACLiteInstance, phy_addr, + IEEE_AUTONEGO_ADVERTISE_REG, + ADVERTISE_100_AND_10); + + XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr, + IEEE_CONTROL_REG_OFFSET, + &control); + control |= (IEEE_CTRL_AUTONEGOTIATE_ENABLE | + IEEE_STAT_AUTONEGOTIATE_RESTART); + + XEmacLite_PhyWrite(pxEMACLiteInstance, phy_addr, + IEEE_CONTROL_REG_OFFSET, + control); + + /* Read PHY control and status registers is successful. */ + XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr, + IEEE_CONTROL_REG_OFFSET, + &control); + XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr, + IEEE_STATUS_REG_OFFSET, + &status); + + if ((control & IEEE_CTRL_AUTONEGOTIATE_ENABLE) && + (status & IEEE_STAT_AUTONEGOTIATE_CAPABLE)) { + + while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) { + XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr, + IEEE_STATUS_REG_OFFSET, + &status); + } + + XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr, + IEEE_PARTNER_ABILITIES_1_REG_OFFSET, + &partner_capabilities); + + if (status & IEEE_STAT_1GBPS_EXTENSIONS) { + XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr, + IEEE_PARTNER_ABILITIES_3_REG_OFFSET, + &partner_capabilities_1000); + if (partner_capabilities_1000 & IEEE_AN3_ABILITY_MASK_1GBPS) return 1000; + } + + if (partner_capabilities & IEEE_AN1_ABILITY_MASK_100MBPS) return 100; + if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS) return 10; + + xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\r\n", + __FUNCTION__); + return 10; + + + } else { + + /* Update TEMAC speed accordingly */ + if (status & IEEE_STAT_1GBPS_EXTENSIONS) { + + /* Get commanded link speed */ + phylinkspeed = control & IEEE_CTRL_1GBPS_LINKSPEED_MASK; + + switch (phylinkspeed) { + case (IEEE_CTRL_LINKSPEED_1000M): + return 1000; + case (IEEE_CTRL_LINKSPEED_100M): + return 100; + case (IEEE_CTRL_LINKSPEED_10M): + return 10; + default: + xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\r\n", + __FUNCTION__, phylinkspeed); + return 10; + } + + } else { + + return (control & IEEE_CTRL_LINKSPEED_MASK) ? 100 : 10; + + } + + } +} + + +static int detect_phy_emaclite(XEmacLite *pxEMACLiteInstance) +{ + u16 phy_reg; + u32 phy_addr; + + for (phy_addr = 31; phy_addr > 0; phy_addr--) { + XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr, PHY_DETECT_REG, &phy_reg); + + if ((phy_reg != 0xFFFF) && + ((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + LWIP_DEBUGF(NETIF_DEBUG, ("XEMacLite detect_phy: PHY detected at address %d.\r\n", phy_addr)); + LWIP_DEBUGF(NETIF_DEBUG, ("XEMacLite detect_phy: PHY detected.\r\n")); + return phy_addr; + } + } + + LWIP_DEBUGF(NETIF_DEBUG, ("XEMacLite detect_phy: No PHY detected. Assuming a PHY at address 0\r\n")); + + /* default to zero */ + return 0; +} + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c new file mode 100644 index 0000000..6215a2b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c @@ -0,0 +1,473 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* BSP includes. */ +#include "xemaclite.h" +#include "xintc_l.h" + +/* lwIP includes. */ +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include +#include +#include "netif/etharp.h" + +/* Define those to better describe your network interface. */ +#define IFNAME0 'e' +#define IFNAME1 'l' + +/* When a packet is ready to be sent, if it cannot be sent immediately then + * the task performing the transmit will block for netifTX_BUFFER_FREE_WAIT + * milliseconds. It will do this a maximum of netifMAX_TX_ATTEMPTS before + * giving up. + */ +#define netifTX_BUFFER_FREE_WAIT ( ( TickType_t ) 2UL / portTICK_PERIOD_MS ) +#define netifMAX_TX_ATTEMPTS ( 5 ) + +#define netifMAX_MTU 1500 + +struct xEthernetIf +{ + struct eth_addr *ethaddr; + /* Add whatever per-interface state that is needed here. */ +}; + +/* + * Copy the received data into a pbuf. + */ +static struct pbuf *prvLowLevelInput( const unsigned char * const pucInputData, unsigned short usDataLength ); + +/* + * Send data from a pbuf to the hardware. + */ +static err_t prvLowLevelOutput( struct netif *pxNetIf, struct pbuf *p ); + +/* + * Perform any hardware and/or driver initialisation necessary. + */ +static void prvLowLevelInit( struct netif *pxNetIf ); + +/* + * Functions that get registered as the Rx and Tx interrupt handers + * respectively. + */ +static void prvRxHandler( void *pvNetIf ); +static void prvTxHandler( void *pvUnused ); + + +/*-----------------------------------------------------------*/ + +/* The instance of the xEmacLite IP being used in this driver. */ +static XEmacLite xEMACInstance; + +/*-----------------------------------------------------------*/ + +/** + * In this function, the hardware should be initialized. + * Called from ethernetif_init(). + * + * @param pxNetIf the already initialized lwip network interface structure + * for this etherpxNetIf + */ +static void prvLowLevelInit( struct netif *pxNetIf ) +{ +portBASE_TYPE xStatus; +extern void vInitialisePHY( XEmacLite *xemaclitep ); +unsigned portBASE_TYPE uxOriginalPriority; + + /* Hardware initialisation can take some time, so temporarily lower the + task priority to ensure other functionality is not adversely effected. + The priority will get raised again before this function exits. */ + uxOriginalPriority = uxTaskPriorityGet( NULL ); + vTaskPrioritySet( NULL, tskIDLE_PRIORITY ); + + /* set MAC hardware address length */ + pxNetIf->hwaddr_len = ETHARP_HWADDR_LEN; + + /* set MAC hardware address */ + pxNetIf->hwaddr[ 0 ] = configMAC_ADDR0; + pxNetIf->hwaddr[ 1 ] = configMAC_ADDR1; + pxNetIf->hwaddr[ 2 ] = configMAC_ADDR2; + pxNetIf->hwaddr[ 3 ] = configMAC_ADDR3; + pxNetIf->hwaddr[ 4 ] = configMAC_ADDR4; + pxNetIf->hwaddr[ 5 ] = configMAC_ADDR5; + + /* device capabilities */ + pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + + /* maximum transfer unit */ + pxNetIf->mtu = netifMAX_MTU; + + /* Broadcast capability */ + pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + + /* Initialize the mac */ + xStatus = XEmacLite_Initialize( &xEMACInstance, XPAR_EMACLITE_0_DEVICE_ID ); + + if( xStatus == XST_SUCCESS ) + { + /* Set mac address */ + XEmacLite_SetMacAddress( &xEMACInstance, ( Xuint8* )( pxNetIf->hwaddr ) ); + + /* Flush any frames already received */ + XEmacLite_FlushReceive( &xEMACInstance ); + + /* Set Rx, Tx interrupt handlers */ + XEmacLite_SetRecvHandler( &xEMACInstance, ( void * ) pxNetIf, prvRxHandler ); + XEmacLite_SetSendHandler( &xEMACInstance, NULL, prvTxHandler ); + + /* Enable Rx, Tx interrupts */ + XEmacLite_EnableInterrupts( &xEMACInstance ); + + /* Install the standard Xilinx library interrupt handler itself. + *NOTE* The xPortInstallInterruptHandler() API function must be used + for this purpose. */ + xStatus = xPortInstallInterruptHandler( XPAR_INTC_0_EMACLITE_0_VEC_ID, ( XInterruptHandler ) XEmacLite_InterruptHandler, &xEMACInstance ); + + vInitialisePHY( &xEMACInstance ); + + /* Enable the interrupt in the interrupt controller. + *NOTE* The vPortEnableInterrupt() API function must be used for this + purpose. */ + vPortEnableInterrupt( XPAR_INTC_0_EMACLITE_0_VEC_ID ); + } + + /* Reset the task priority back to its original value. */ + vTaskPrioritySet( NULL, uxOriginalPriority ); + + configASSERT( xStatus == pdPASS ); +} + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + * @param pxNetIf the lwip network interface structure for this etherpxNetIf + * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) + * @return ERR_OK if the packet could be sent + * an err_t value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become available since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ + +static err_t prvLowLevelOutput( struct netif *pxNetIf, struct pbuf *p ) +{ + + /* This is taken from lwIP example code and therefore does not conform + to the FreeRTOS coding standard. */ + +struct pbuf *q; +static unsigned char ucBuffer[ 1520 ] __attribute__((aligned(32))); +unsigned char *pucBuffer = ucBuffer; +unsigned char *pucChar; +struct eth_hdr *pxHeader; +u16_t usTotalLength = p->tot_len - ETH_PAD_SIZE; +err_t xReturn = ERR_OK; +long x; + + ( void ) pxNetIf; + + #if defined(LWIP_DEBUG) && LWIP_NETIF_TX_SINGLE_PBUF + LWIP_ASSERT("p->next == NULL && p->len == p->tot_len", p->next == NULL && p->len == p->tot_len); + #endif + + /* Initiate transfer. */ + if( p->len == p->tot_len ) + { + /* No pbuf chain, don't have to copy -> faster. */ + pucBuffer = &( ( unsigned char * ) p->payload )[ ETH_PAD_SIZE ]; + } + else + { + /* pbuf chain, copy into contiguous ucBuffer. */ + if( p->tot_len >= sizeof( ucBuffer ) ) + { + LINK_STATS_INC( link.lenerr ); + LINK_STATS_INC( link.drop ); + snmp_inc_ifoutdiscards( pxNetIf ); + xReturn = ERR_BUF; + } + else + { + pucChar = ucBuffer; + + for( q = p; q != NULL; q = q->next ) + { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + /* send data from(q->payload, q->len); */ + LWIP_DEBUGF( NETIF_DEBUG, ( "NETIF: send pucChar %p q->payload %p q->len %i q->next %p\n", pucChar, q->payload, ( int ) q->len, ( void* ) q->next ) ); + if( q == p ) + { + memcpy( pucChar, &( ( char * ) q->payload )[ ETH_PAD_SIZE ], q->len - ETH_PAD_SIZE ); + pucChar += q->len - ETH_PAD_SIZE; + } + else + { + memcpy( pucChar, q->payload, q->len ); + pucChar += q->len; + } + } + } + } + + if( xReturn == ERR_OK ) + { + for( x = 0; x < netifMAX_TX_ATTEMPTS; x++ ) + { + xReturn = XEmacLite_Send( &xEMACInstance, pucBuffer, ( int ) usTotalLength ); + if( xReturn == XST_SUCCESS ) + { + break; + } + else + { + vTaskDelay( netifTX_BUFFER_FREE_WAIT ); + } + } + + if( xReturn != XST_SUCCESS ) + { + LINK_STATS_INC( link.memerr ); + LINK_STATS_INC( link.drop ); + snmp_inc_ifoutdiscards( pxNetIf ); + xReturn = ERR_BUF; + } + else + { + LINK_STATS_INC( link.xmit ); + snmp_add_ifoutoctets( pxNetIf, usTotalLength ); + pxHeader = ( struct eth_hdr * )p->payload; + + if( ( pxHeader->dest.addr[ 0 ] & 1 ) != 0 ) + { + /* broadcast or multicast packet*/ + snmp_inc_ifoutnucastpkts( pxNetIf ); + } + else + { + /* unicast packet */ + snmp_inc_ifoutucastpkts( pxNetIf ); + } + } + } + + return xReturn; +} + +/** + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + * @param pxNetIf the lwip network interface structure for this etherpxNetIf + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +static struct pbuf *prvLowLevelInput( const unsigned char * const pucInputData, unsigned short usDataLength ) +{ +struct pbuf *p = NULL, *q; + + if( usDataLength > 0U ) + { + #if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ + #endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc( PBUF_RAW, usDataLength, PBUF_POOL ); + + if( p != NULL ) + { + #if ETH_PAD_SIZE + pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */ + #endif + + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + usDataLength = 0U; + for( q = p; q != NULL; q = q->next ) + { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. + * This does not necessarily have to be a memcpy, you can also preallocate + * pbufs for a DMA-enabled MAC and after receiving truncate it to the + * actually received size. In this case, ensure the usTotalLength member of the + * pbuf is the sum of the chained pbuf len members. + */ + memcpy( q->payload, &( pucInputData[ usDataLength ] ), q->len ); + usDataLength += q->len; + } + + #if ETH_PAD_SIZE + pbuf_header( p, ETH_PAD_SIZE ); /* reclaim the padding word */ + #endif + + LINK_STATS_INC(link.recv); + } + } + + return p; +} + +/** + * Should be called at the beginning of the program to set up the + * network interface. It calls the function prvLowLevelInit() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to pxNetIf_add(). + * + * @param pxNetIf the lwip network interface structure for this etherpxNetIf + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t ethernetif_init( struct netif *pxNetIf ) +{ +err_t xReturn = ERR_OK; + + /* This is taken from lwIP example code and therefore does not conform + to the FreeRTOS coding standard. */ + +struct xEthernetIf *pxEthernetIf; + + LWIP_ASSERT( "pxNetIf != NULL", ( pxNetIf != NULL ) ); + + pxEthernetIf = mem_malloc( sizeof( struct xEthernetIf ) ); + if( pxEthernetIf == NULL ) + { + LWIP_DEBUGF(NETIF_DEBUG, ( "ethernetif_init: out of memory\n" ) ); + xReturn = ERR_MEM; + } + else + { + #if LWIP_NETIF_HOSTNAME + { + /* Initialize interface hostname */ + pxNetIf->hostname = "lwip"; + } + #endif /* LWIP_NETIF_HOSTNAME */ + + pxNetIf->state = pxEthernetIf; + pxNetIf->name[ 0 ] = IFNAME0; + pxNetIf->name[ 1 ] = IFNAME1; + + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ + pxNetIf->output = etharp_output; + pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_IGMP; + pxNetIf->hwaddr_len = ETHARP_HWADDR_LEN; + pxNetIf->mtu = netifMAX_MTU; + pxNetIf->linkoutput = prvLowLevelOutput; + + pxEthernetIf->ethaddr = ( struct eth_addr * ) &( pxNetIf->hwaddr[ 0 ] ); + + /* initialize the hardware */ + prvLowLevelInit( pxNetIf ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvRxHandler( void *pvNetIf ) +{ + /* This is taken from lwIP example code and therefore does not conform + to the FreeRTOS coding standard. */ + +struct eth_hdr *pxHeader; +struct pbuf *p; +unsigned short usInputLength; +static unsigned char ucBuffer[ 1520 ] __attribute__((aligned(32))); +extern portBASE_TYPE xInsideISR; +struct netif *pxNetIf = ( struct netif * ) pvNetIf; + + XIntc_AckIntr( XPAR_ETHERNET_LITE_BASEADDR, XPAR_ETHERNET_LITE_IP2INTC_IRPT_MASK ); + + /* Ensure the pbuf handling functions don't attempt to use critical + sections. */ + xInsideISR++; + + usInputLength = ( long ) XEmacLite_Recv( &xEMACInstance, ucBuffer ); + + /* move received packet into a new pbuf */ + p = prvLowLevelInput( ucBuffer, usInputLength ); + + /* no packet could be read, silently ignore this */ + if( p != NULL ) + { + /* points to packet payload, which starts with an Ethernet header */ + pxHeader = p->payload; + + switch( htons( pxHeader->type ) ) + { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: + /* full packet send to tcpip_thread to process */ + if( pxNetIf->input( p, pxNetIf ) != ERR_OK ) + { + LWIP_DEBUGF(NETIF_DEBUG, ( "ethernetif_input: IP input error\n" ) ); + pbuf_free(p); + p = NULL; + } + break; + + default: + pbuf_free( p ); + p = NULL; + break; + } + } + + xInsideISR--; +} +/*-----------------------------------------------------------*/ + +static void prvTxHandler( void *pvUnused ) +{ + ( void ) pvUnused; + XIntc_AckIntr( XPAR_ETHERNET_LITE_BASEADDR, XPAR_ETHERNET_LITE_IP2INTC_IRPT_MASK ); +} + + + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/bpstruct.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/bpstruct.h new file mode 100644 index 0000000..1d81e3f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/bpstruct.h @@ -0,0 +1 @@ +#pragma pack(push,1) diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/cc.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/cc.h new file mode 100644 index 0000000..4075cc2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/cc.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __ARCH_CC_H__ +#define __ARCH_CC_H__ + +/* Include some files for defining library routines */ +#include /* printf, fflush, FILE */ +#include /* abort */ + + + +/** @todo fix some warnings: don't use #pragma if compiling with cygwin gcc */ +#ifndef __GNUC__ + #include + #pragma warning (disable: 4244) /* disable conversion warning (implicit integer promotion!) */ + #pragma warning (disable: 4127) /* conditional expression is constant */ + #pragma warning (disable: 4996) /* 'strncpy' was declared deprecated */ + #pragma warning (disable: 4103) /* structure packing changed by including file */ +#endif + +#define LWIP_PROVIDE_ERRNO + +/* Define generic types used in lwIP */ +typedef unsigned char u8_t; +typedef signed char s8_t; +typedef unsigned short u16_t; +typedef signed short s16_t; +typedef unsigned long u32_t; +typedef signed long s32_t; + +typedef size_t mem_ptr_t; +typedef u32_t sys_prot_t; + +/* Define (sn)printf formatters for these lwIP types */ +#define X8_F "02x" +#define U16_F "hu" +#define S16_F "hd" +#define X16_F "hx" +#define U32_F "lu" +#define S32_F "ld" +#define X32_F "lx" +#define SZT_F U32_F + +/* Compiler hints for packing structures */ +#define PACK_STRUCT_STRUCT __attribute__( (packed) ) + +/* Plaform specific diagnostic output */ +#define LWIP_PLATFORM_DIAG(x) do { printf x; } while(0) + +#define LWIP_PLATFORM_ASSERT(x) do { printf("Assertion \"%s\" failed at line %d in %s\n", \ + x, __LINE__, __FILE__); fflush(NULL); abort(); } while(0) + +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + printf("Assertion \"%s\" failed at line %d in %s\n", message, __LINE__, __FILE__); \ + fflush(NULL);handler;} } while(0) + +/* C runtime functions redefined */ +#define snprintf _snprintf + +u32_t dns_lookup_external_hosts_file(const char *name); + +#define LWIP_RAND() ((u32_t)rand()) + +#endif /* __ARCH_CC_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/epstruct.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/epstruct.h new file mode 100644 index 0000000..65898b5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/epstruct.h @@ -0,0 +1 @@ +#pragma pack(pop) diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/perf.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/perf.h new file mode 100644 index 0000000..089faca --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/perf.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START /* null definition */ +#define PERF_STOP(x) /* null definition */ + +#endif /* __PERF_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/sys_arch.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/sys_arch.h new file mode 100644 index 0000000..3fc3739 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/sys_arch.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __ARCH_SYS_ARCH_H__ +#define __ARCH_SYS_ARCH_H__ + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +#define SYS_MBOX_NULL ( ( QueueHandle_t ) NULL ) +#define SYS_SEM_NULL ( ( SemaphoreHandle_t ) NULL ) +#define SYS_DEFAULT_THREAD_STACK_DEPTH configMINIMAL_STACK_SIZE + +typedef SemaphoreHandle_t sys_sem_t; +typedef SemaphoreHandle_t sys_mutex_t; +typedef QueueHandle_t sys_mbox_t; +typedef TaskHandle_t sys_thread_t; + +#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE ) +#define sys_mbox_set_invalid( x ) ( ( *x ) = NULL ) +#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE ) +#define sys_sem_set_invalid( x ) ( ( *x ) = NULL ) + + +#endif /* __ARCH_SYS_ARCH_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/sys_arch.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/sys_arch.c new file mode 100644 index 0000000..fa1c20e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/sys_arch.c @@ -0,0 +1,584 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +//***************************************************************************** +// +// Include OS functionality. +// +//***************************************************************************** + +/* ------------------------ System architecture includes ----------------------------- */ +#include "arch/sys_arch.h" + +/* ------------------------ lwIP includes --------------------------------- */ +#include "lwip/opt.h" + +#include "lwip/debug.h" +#include "lwip/def.h" +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/stats.h" + +/* Very crude mechanism used to determine if the critical section handling +functions are being called from an interrupt context or not. This relies on +the interrupt handler setting this variable manually. */ +portBASE_TYPE xInsideISR = pdFALSE; + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_new + *---------------------------------------------------------------------------* + * Description: + * Creates a new mailbox + * Inputs: + * int size -- Size of elements in the mailbox + * Outputs: + * sys_mbox_t -- Handle to new mailbox + *---------------------------------------------------------------------------*/ +err_t sys_mbox_new( sys_mbox_t *pxMailBox, int iSize ) +{ +err_t xReturn = ERR_MEM; + + *pxMailBox = xQueueCreate( iSize, sizeof( void * ) ); + + if( *pxMailBox != NULL ) + { + xReturn = ERR_OK; + SYS_STATS_INC_USED( mbox ); + } + + return xReturn; +} + + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_free + *---------------------------------------------------------------------------* + * Description: + * Deallocates a mailbox. If there are messages still present in the + * mailbox when the mailbox is deallocated, it is an indication of a + * programming error in lwIP and the developer should be notified. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * Outputs: + * sys_mbox_t -- Handle to new mailbox + *---------------------------------------------------------------------------*/ +void sys_mbox_free( sys_mbox_t *pxMailBox ) +{ +unsigned long ulMessagesWaiting; + + ulMessagesWaiting = uxQueueMessagesWaiting( *pxMailBox ); + configASSERT( ( ulMessagesWaiting == 0 ) ); + + #if SYS_STATS + { + if( ulMessagesWaiting != 0UL ) + { + SYS_STATS_INC( mbox.err ); + } + + SYS_STATS_DEC( mbox.used ); + } + #endif /* SYS_STATS */ + + vQueueDelete( *pxMailBox ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_post + *---------------------------------------------------------------------------* + * Description: + * Post the "msg" to the mailbox. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void *data -- Pointer to data to post + *---------------------------------------------------------------------------*/ +void sys_mbox_post( sys_mbox_t *pxMailBox, void *pxMessageToPost ) +{ + while( xQueueSendToBack( *pxMailBox, &pxMessageToPost, portMAX_DELAY ) != pdTRUE ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_trypost + *---------------------------------------------------------------------------* + * Description: + * Try to post the "msg" to the mailbox. Returns immediately with + * error if cannot. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void *msg -- Pointer to data to post + * Outputs: + * err_t -- ERR_OK if message posted, else ERR_MEM + * if not. + *---------------------------------------------------------------------------*/ +err_t sys_mbox_trypost( sys_mbox_t *pxMailBox, void *pxMessageToPost ) +{ +err_t xReturn; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + if( xInsideISR != pdFALSE ) + { + xReturn = xQueueSendFromISR( *pxMailBox, &pxMessageToPost, &xHigherPriorityTaskWoken ); + } + else + { + xReturn = xQueueSend( *pxMailBox, &pxMessageToPost, ( TickType_t ) 0 ); + } + + if( xReturn == pdPASS ) + { + xReturn = ERR_OK; + } + else + { + /* The queue was already full. */ + xReturn = ERR_MEM; + SYS_STATS_INC( mbox.err ); + } + + return xReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_mbox_fetch + *---------------------------------------------------------------------------* + * Description: + * Blocks the thread until a message arrives in the mailbox, but does + * not block the thread longer than "timeout" milliseconds (similar to + * the sys_arch_sem_wait() function). The "msg" argument is a result + * parameter that is set by the function (i.e., by doing "*msg = + * ptr"). The "msg" parameter maybe NULL to indicate that the message + * should be dropped. + * + * The return values are the same as for the sys_arch_sem_wait() function: + * Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a + * timeout. + * + * Note that a function with a similar name, sys_mbox_fetch(), is + * implemented by lwIP. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void **msg -- Pointer to pointer to msg received + * u32_t timeout -- Number of milliseconds until timeout + * Outputs: + * u32_t -- SYS_ARCH_TIMEOUT if timeout, else number + * of milliseconds until received. + *---------------------------------------------------------------------------*/ +u32_t sys_arch_mbox_fetch( sys_mbox_t *pxMailBox, void **ppvBuffer, u32_t ulTimeOut ) +{ +void *pvDummy; +TickType_t xStartTime, xEndTime, xElapsed; +unsigned long ulReturn; + + xStartTime = xTaskGetTickCount(); + + if( NULL == ppvBuffer ) + { + ppvBuffer = &pvDummy; + } + + if( ulTimeOut != 0UL ) + { + configASSERT( xInsideISR == ( portBASE_TYPE ) 0 ); + + if( pdTRUE == xQueueReceive( *pxMailBox, &( *ppvBuffer ), ulTimeOut/ portTICK_PERIOD_MS ) ) + { + xEndTime = xTaskGetTickCount(); + xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS; + + ulReturn = xElapsed; + } + else + { + /* Timed out. */ + *ppvBuffer = NULL; + ulReturn = SYS_ARCH_TIMEOUT; + } + } + else + { + while( pdTRUE != xQueueReceive( *pxMailBox, &( *ppvBuffer ), portMAX_DELAY ) ); + xEndTime = xTaskGetTickCount(); + xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS; + + if( xElapsed == 0UL ) + { + xElapsed = 1UL; + } + + ulReturn = xElapsed; + } + + return ulReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_mbox_tryfetch + *---------------------------------------------------------------------------* + * Description: + * Similar to sys_arch_mbox_fetch, but if message is not ready + * immediately, we'll return with SYS_MBOX_EMPTY. On success, 0 is + * returned. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void **msg -- Pointer to pointer to msg received + * Outputs: + * u32_t -- SYS_MBOX_EMPTY if no messages. Otherwise, + * return ERR_OK. + *---------------------------------------------------------------------------*/ +u32_t sys_arch_mbox_tryfetch( sys_mbox_t *pxMailBox, void **ppvBuffer ) +{ +void *pvDummy; +unsigned long ulReturn; +long lResult; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + if( ppvBuffer== NULL ) + { + ppvBuffer = &pvDummy; + } + + if( xInsideISR != pdFALSE ) + { + lResult = xQueueReceiveFromISR( *pxMailBox, &( *ppvBuffer ), &xHigherPriorityTaskWoken ); + } + else + { + lResult = xQueueReceive( *pxMailBox, &( *ppvBuffer ), 0UL ); + } + + if( lResult == pdPASS ) + { + ulReturn = ERR_OK; + } + else + { + ulReturn = SYS_MBOX_EMPTY; + } + + return ulReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_sem_new + *---------------------------------------------------------------------------* + * Description: + * Creates and returns a new semaphore. The "ucCount" argument specifies + * the initial state of the semaphore. + * NOTE: Currently this routine only creates counts of 1 or 0 + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * u8_t ucCount -- Initial ucCount of semaphore (1 or 0) + * Outputs: + * sys_sem_t -- Created semaphore or 0 if could not create. + *---------------------------------------------------------------------------*/ +err_t sys_sem_new( sys_sem_t *pxSemaphore, u8_t ucCount ) +{ +err_t xReturn = ERR_MEM; + + vSemaphoreCreateBinary( ( *pxSemaphore ) ); + + if( *pxSemaphore != NULL ) + { + if( ucCount == 0U ) + { + xSemaphoreTake( *pxSemaphore, 1UL ); + } + + xReturn = ERR_OK; + SYS_STATS_INC_USED( sem ); + } + else + { + SYS_STATS_INC( sem.err ); + } + + return xReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_sem_wait + *---------------------------------------------------------------------------* + * Description: + * Blocks the thread while waiting for the semaphore to be + * signaled. If the "timeout" argument is non-zero, the thread should + * only be blocked for the specified time (measured in + * milliseconds). + * + * If the timeout argument is non-zero, the return value is the number of + * milliseconds spent waiting for the semaphore to be signaled. If the + * semaphore wasn't signaled within the specified time, the return value is + * SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore + * (i.e., it was already signaled), the function may return zero. + * + * Notice that lwIP implements a function with a similar name, + * sys_sem_wait(), that uses the sys_arch_sem_wait() function. + * Inputs: + * sys_sem_t sem -- Semaphore to wait on + * u32_t timeout -- Number of milliseconds until timeout + * Outputs: + * u32_t -- Time elapsed or SYS_ARCH_TIMEOUT. + *---------------------------------------------------------------------------*/ +u32_t sys_arch_sem_wait( sys_sem_t *pxSemaphore, u32_t ulTimeout ) +{ +TickType_t xStartTime, xEndTime, xElapsed; +unsigned long ulReturn; + + xStartTime = xTaskGetTickCount(); + + if( ulTimeout != 0UL ) + { + if( xSemaphoreTake( *pxSemaphore, ulTimeout / portTICK_PERIOD_MS ) == pdTRUE ) + { + xEndTime = xTaskGetTickCount(); + xElapsed = (xEndTime - xStartTime) * portTICK_PERIOD_MS; + ulReturn = xElapsed; + } + else + { + ulReturn = SYS_ARCH_TIMEOUT; + } + } + else + { + while( xSemaphoreTake( *pxSemaphore, portMAX_DELAY ) != pdTRUE ); + xEndTime = xTaskGetTickCount(); + xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS; + + if( xElapsed == 0UL ) + { + xElapsed = 1UL; + } + + ulReturn = xElapsed; + } + + return ulReturn; +} + +/** Create a new mutex + * @param mutex pointer to the mutex to create + * @return a new mutex */ +err_t sys_mutex_new( sys_mutex_t *pxMutex ) +{ +err_t xReturn = ERR_MEM; + + *pxMutex = xSemaphoreCreateMutex(); + + if( *pxMutex != NULL ) + { + xReturn = ERR_OK; + SYS_STATS_INC_USED( mutex ); + } + else + { + SYS_STATS_INC( mutex.err ); + } + + return xReturn; +} + +/** Lock a mutex + * @param mutex the mutex to lock */ +void sys_mutex_lock( sys_mutex_t *pxMutex ) +{ + while( xSemaphoreTake( *pxMutex, portMAX_DELAY ) != pdPASS ); +} + +/** Unlock a mutex + * @param mutex the mutex to unlock */ +void sys_mutex_unlock(sys_mutex_t *pxMutex ) +{ + xSemaphoreGive( *pxMutex ); +} + + +/** Delete a semaphore + * @param mutex the mutex to delete */ +void sys_mutex_free( sys_mutex_t *pxMutex ) +{ + SYS_STATS_DEC( mutex.used ); + vQueueDelete( *pxMutex ); +} + + +/*---------------------------------------------------------------------------* + * Routine: sys_sem_signal + *---------------------------------------------------------------------------* + * Description: + * Signals (releases) a semaphore + * Inputs: + * sys_sem_t sem -- Semaphore to signal + *---------------------------------------------------------------------------*/ +void sys_sem_signal( sys_sem_t *pxSemaphore ) +{ +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + if( xInsideISR != pdFALSE ) + { + xSemaphoreGiveFromISR( *pxSemaphore, &xHigherPriorityTaskWoken ); + } + else + { + xSemaphoreGive( *pxSemaphore ); + } +} + +/*---------------------------------------------------------------------------* + * Routine: sys_sem_free + *---------------------------------------------------------------------------* + * Description: + * Deallocates a semaphore + * Inputs: + * sys_sem_t sem -- Semaphore to free + *---------------------------------------------------------------------------*/ +void sys_sem_free( sys_sem_t *pxSemaphore ) +{ + SYS_STATS_DEC(sem.used); + vQueueDelete( *pxSemaphore ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_init + *---------------------------------------------------------------------------* + * Description: + * Initialize sys arch + *---------------------------------------------------------------------------*/ +void sys_init(void) +{ +} + +u32_t sys_now(void) +{ + return xTaskGetTickCount(); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_thread_new + *---------------------------------------------------------------------------* + * Description: + * Starts a new thread with priority "prio" that will begin its + * execution in the function "thread()". The "arg" argument will be + * passed as an argument to the thread() function. The id of the new + * thread is returned. Both the id and the priority are system + * dependent. + * Inputs: + * char *name -- Name of thread + * void (* thread)(void *arg) -- Pointer to function to run. + * void *arg -- Argument passed into function + * int stacksize -- Required stack amount in bytes + * int prio -- Thread priority + * Outputs: + * sys_thread_t -- Pointer to per-thread timeouts. + *---------------------------------------------------------------------------*/ +sys_thread_t sys_thread_new( const char *pcName, void( *pxThread )( void *pvParameters ), void *pvArg, int iStackSize, int iPriority ) +{ +TaskHandle_t xCreatedTask; +portBASE_TYPE xResult; +sys_thread_t xReturn; + + xResult = xTaskCreate( pxThread, pcName, iStackSize, pvArg, iPriority, &xCreatedTask ); + + if( xResult == pdPASS ) + { + xReturn = xCreatedTask; + } + else + { + xReturn = NULL; + } + + return xReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_protect + *---------------------------------------------------------------------------* + * Description: + * This optional function does a "fast" critical region protection and + * returns the previous protection level. This function is only called + * during very short critical regions. An embedded system which supports + * ISR-based drivers might want to implement this function by disabling + * interrupts. Task-based systems might want to implement this by using + * a mutex or disabling tasking. This function should support recursive + * calls from the same task or interrupt. In other words, + * sys_arch_protect() could be called while already protected. In + * that case the return value indicates that it is already protected. + * + * sys_arch_protect() is only required if your port is supporting an + * operating system. + * Outputs: + * sys_prot_t -- Previous protection level (not used here) + *---------------------------------------------------------------------------*/ +sys_prot_t sys_arch_protect( void ) +{ + if( xInsideISR == pdFALSE ) + { + taskENTER_CRITICAL(); + } + return ( sys_prot_t ) 1; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_unprotect + *---------------------------------------------------------------------------* + * Description: + * This optional function does a "fast" set of critical region + * protection to the value specified by pval. See the documentation for + * sys_arch_protect() for more information. This function is only + * required if your port is supporting an operating system. + * Inputs: + * sys_prot_t -- Previous protection level (not used here) + *---------------------------------------------------------------------------*/ +void sys_arch_unprotect( sys_prot_t xValue ) +{ + (void) xValue; + if( xInsideISR == pdFALSE ) + { + taskEXIT_CRITICAL(); + } +} + +/* + * Prints an assertion messages and aborts execution. + */ +void sys_assert( const char *pcMessage ) +{ + (void) pcMessage; + + for (;;) + { + } +} +/*-------------------------------------------------------------------------* + * End of File: sys_arch.c + *-------------------------------------------------------------------------*/ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Packet32.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Packet32.h new file mode 100644 index 0000000..1e0eacd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Packet32.h @@ -0,0 +1,359 @@ +/* + * Copyright (c) 1999 - 2005 NetGroup, Politecnico di Torino (Italy) + * Copyright (c) 2005 - 2007 CACE Technologies, Davis (California) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Politecnico di Torino, CACE Technologies + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** @ingroup packetapi + * @{ + */ + +/** @defgroup packet32h Packet.dll definitions and data structures + * Packet32.h contains the data structures and the definitions used by packet.dll. + * The file is used both by the Win9x and the WinNTx versions of packet.dll, and can be included + * by the applications that use the functions of this library + * @{ + */ + +#ifndef __PACKET32 +#define __PACKET32 + +#include + +#ifdef HAVE_AIRPCAP_API +#include +#else +#if !defined(AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_) +#define AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ +typedef struct _AirpcapHandle *PAirpcapHandle; +#endif /* AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ */ +#endif /* HAVE_AIRPCAP_API */ + +#ifdef HAVE_DAG_API +#include +#endif /* HAVE_DAG_API */ + +// Working modes +#define PACKET_MODE_CAPT 0x0 ///< Capture mode +#define PACKET_MODE_STAT 0x1 ///< Statistical mode +#define PACKET_MODE_MON 0x2 ///< Monitoring mode +#define PACKET_MODE_DUMP 0x10 ///< Dump mode +#define PACKET_MODE_STAT_DUMP MODE_DUMP | MODE_STAT ///< Statistical dump Mode + + +/// Alignment macro. Defines the alignment size. +#define Packet_ALIGNMENT sizeof(int) +/// Alignment macro. Rounds up to the next even multiple of Packet_ALIGNMENT. +#define Packet_WORDALIGN(x) (((x)+(Packet_ALIGNMENT-1))&~(Packet_ALIGNMENT-1)) + +#define NdisMediumNull -1 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumCHDLC -2 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumPPPSerial -3 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumBare80211 -4 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumRadio80211 -5 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumPpi -6 ///< Custom linktype: NDIS doesn't provide an equivalent + +// Loopback behaviour definitions +#define NPF_DISABLE_LOOPBACK 1 ///< Drop the packets sent by the NPF driver +#define NPF_ENABLE_LOOPBACK 2 ///< Capture the packets sent by the NPF driver + +/*! + \brief Network type structure. + + This structure is used by the PacketGetNetType() function to return information on the current adapter's type and speed. +*/ +typedef struct NetType +{ + UINT LinkType; ///< The MAC of the current network adapter (see function PacketGetNetType() for more information) + ULONGLONG LinkSpeed; ///< The speed of the network in bits per second +}NetType; + + +//some definitions stolen from libpcap + +#ifndef BPF_MAJOR_VERSION + +/*! + \brief A BPF pseudo-assembly program. + + The program will be injected in the kernel by the PacketSetBPF() function and applied to every incoming packet. +*/ +struct bpf_program +{ + UINT bf_len; ///< Indicates the number of instructions of the program, i.e. the number of struct bpf_insn that will follow. + struct bpf_insn *bf_insns; ///< A pointer to the first instruction of the program. +}; + +/*! + \brief A single BPF pseudo-instruction. + + bpf_insn contains a single instruction for the BPF register-machine. It is used to send a filter program to the driver. +*/ +struct bpf_insn +{ + USHORT code; ///< Instruction type and addressing mode. + UCHAR jt; ///< Jump if true + UCHAR jf; ///< Jump if false + int k; ///< Generic field used for various purposes. +}; + +/*! + \brief Structure that contains a couple of statistics values on the current capture. + + It is used by packet.dll to return statistics about a capture session. +*/ +struct bpf_stat +{ + UINT bs_recv; ///< Number of packets that the driver received from the network adapter + ///< from the beginning of the current capture. This value includes the packets + ///< lost by the driver. + UINT bs_drop; ///< number of packets that the driver lost from the beginning of a capture. + ///< Basically, a packet is lost when the the buffer of the driver is full. + ///< In this situation the packet cannot be stored and the driver rejects it. + UINT ps_ifdrop; ///< drops by interface. XXX not yet supported + UINT bs_capt; ///< number of packets that pass the filter, find place in the kernel buffer and + ///< thus reach the application. +}; + +/*! + \brief Packet header. + + This structure defines the header associated with every packet delivered to the application. +*/ +struct bpf_hdr +{ + struct timeval bh_tstamp; ///< The timestamp associated with the captured packet. + ///< It is stored in a TimeVal structure. + UINT bh_caplen; ///< Length of captured portion. The captured portion can be different + ///< from the original packet, because it is possible (with a proper filter) + ///< to instruct the driver to capture only a portion of the packets. + UINT bh_datalen; ///< Original length of packet + USHORT bh_hdrlen; ///< Length of bpf header (this struct plus alignment padding). In some cases, + ///< a padding could be added between the end of this structure and the packet + ///< data for performance reasons. This filed can be used to retrieve the actual data + ///< of the packet. +}; + +/*! + \brief Dump packet header. + + This structure defines the header associated with the packets in a buffer to be used with PacketSendPackets(). + It is simpler than the bpf_hdr, because it corresponds to the header associated by WinPcap and libpcap to a + packet in a dump file. This makes straightforward sending WinPcap dump files to the network. +*/ +struct dump_bpf_hdr{ + struct timeval ts; ///< Time stamp of the packet + UINT caplen; ///< Length of captured portion. The captured portion can smaller than the + ///< the original packet, because it is possible (with a proper filter) to + ///< instruct the driver to capture only a portion of the packets. + UINT len; ///< Length of the original packet (off wire). +}; + + +#endif + +struct bpf_stat; + +#define DOSNAMEPREFIX TEXT("Packet_") ///< Prefix added to the adapters device names to create the WinPcap devices +#define MAX_LINK_NAME_LENGTH 64 //< Maximum length of the devices symbolic links +#define NMAX_PACKET 65535 + +/*! + \brief Addresses of a network adapter. + + This structure is used by the PacketGetNetInfoEx() function to return the IP addresses associated with + an adapter. +*/ +typedef struct npf_if_addr { + struct sockaddr_storage IPAddress; ///< IP address. + struct sockaddr_storage SubnetMask; ///< Netmask for that address. + struct sockaddr_storage Broadcast; ///< Broadcast address. +}npf_if_addr; + + +#define ADAPTER_NAME_LENGTH 256 + 12 ///< Maximum length for the name of an adapter. The value is the same used by the IP Helper API. +#define ADAPTER_DESC_LENGTH 128 ///< Maximum length for the description of an adapter. The value is the same used by the IP Helper API. +#define MAX_MAC_ADDR_LENGTH 8 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. +#define MAX_NETWORK_ADDRESSES 16 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. + + +typedef struct WAN_ADAPTER_INT WAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API +typedef WAN_ADAPTER *PWAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API + +#define INFO_FLAG_NDIS_ADAPTER 0 ///< Flag for ADAPTER_INFO: this is a traditional ndis adapter +#define INFO_FLAG_NDISWAN_ADAPTER 1 ///< Flag for ADAPTER_INFO: this is a NdisWan adapter, and it's managed by WANPACKET +#define INFO_FLAG_DAG_CARD 2 ///< Flag for ADAPTER_INFO: this is a DAG card +#define INFO_FLAG_DAG_FILE 6 ///< Flag for ADAPTER_INFO: this is a DAG file +#define INFO_FLAG_DONT_EXPORT 8 ///< Flag for ADAPTER_INFO: when this flag is set, the adapter will not be listed or openend by winpcap. This allows to prevent exporting broken network adapters, like for example FireWire ones. +#define INFO_FLAG_AIRPCAP_CARD 16 ///< Flag for ADAPTER_INFO: this is an airpcap card +#define INFO_FLAG_NPFIM_DEVICE 32 + +/*! + \brief Describes an opened network adapter. + + This structure is the most important for the functioning of packet.dll, but the great part of its fields + should be ignored by the user, since the library offers functions that avoid to cope with low-level parameters +*/ +typedef struct _ADAPTER { + HANDLE hFile; ///< \internal Handle to an open instance of the NPF driver. + CHAR SymbolicLink[MAX_LINK_NAME_LENGTH]; ///< \internal A string containing the name of the network adapter currently opened. + int NumWrites; ///< \internal Number of times a packets written on this adapter will be repeated + ///< on the wire. + HANDLE ReadEvent; ///< A notification event associated with the read calls on the adapter. + ///< It can be passed to standard Win32 functions (like WaitForSingleObject + ///< or WaitForMultipleObjects) to wait until the driver's buffer contains some + ///< data. It is particularly useful in GUI applications that need to wait + ///< concurrently on several events. In Windows NT/2000 the PacketSetMinToCopy() + ///< function can be used to define the minimum amount of data in the kernel buffer + ///< that will cause the event to be signalled. + + UINT ReadTimeOut; ///< \internal The amount of time after which a read on the driver will be released and + ///< ReadEvent will be signaled, also if no packets were captured + CHAR Name[ADAPTER_NAME_LENGTH]; + PWAN_ADAPTER pWanAdapter; + UINT Flags; ///< Adapter's flags. Tell if this adapter must be treated in a different way, using the Netmon API or the dagc API. + +#ifdef HAVE_AIRPCAP_API + PAirpcapHandle AirpcapAd; +#endif // HAVE_AIRPCAP_API + +#ifdef HAVE_NPFIM_API + void* NpfImHandle; +#endif // HAVE_NPFIM_API + +#ifdef HAVE_DAG_API + dagc_t *pDagCard; ///< Pointer to the dagc API adapter descriptor for this adapter + PCHAR DagBuffer; ///< Pointer to the buffer with the packets that is received from the DAG card + struct timeval DagReadTimeout; ///< Read timeout. The dagc API requires a timeval structure + unsigned DagFcsLen; ///< Length of the frame check sequence attached to any packet by the card. Obtained from the registry + DWORD DagFastProcess; ///< True if the user requests fast capture processing on this card. Higher level applications can use this value to provide a faster but possibly unprecise capture (for example, libpcap doesn't convert the timestamps). +#endif // HAVE_DAG_API +} ADAPTER, *LPADAPTER; + +/*! + \brief Structure that contains a group of packets coming from the driver. + + This structure defines the header associated with every packet delivered to the application. +*/ +typedef struct _PACKET { + HANDLE hEvent; ///< \deprecated Still present for compatibility with old applications. + OVERLAPPED OverLapped; ///< \deprecated Still present for compatibility with old applications. + PVOID Buffer; ///< Buffer with containing the packets. See the PacketReceivePacket() for + ///< details about the organization of the data in this buffer + UINT Length; ///< Length of the buffer + DWORD ulBytesReceived; ///< Number of valid bytes present in the buffer, i.e. amount of data + ///< received by the last call to PacketReceivePacket() + BOOLEAN bIoComplete; ///< \deprecated Still present for compatibility with old applications. +} PACKET, *LPPACKET; + +/*! + \brief Structure containing an OID request. + + It is used by the PacketRequest() function to send an OID to the interface card driver. + It can be used, for example, to retrieve the status of the error counters on the adapter, its MAC address, + the list of the multicast groups defined on it, and so on. +*/ +struct _PACKET_OID_DATA { + ULONG Oid; ///< OID code. See the Microsoft DDK documentation or the file ntddndis.h + ///< for a complete list of valid codes. + ULONG Length; ///< Length of the data field + UCHAR Data[1]; ///< variable-lenght field that contains the information passed to or received + ///< from the adapter. +}; +typedef struct _PACKET_OID_DATA PACKET_OID_DATA, *PPACKET_OID_DATA; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @} + */ + +/* +BOOLEAN QueryWinPcapRegistryStringA(CHAR *SubKeyName, + CHAR *Value, + UINT *pValueLen, + CHAR *DefaultVal); + +BOOLEAN QueryWinPcapRegistryStringW(WCHAR *SubKeyName, + WCHAR *Value, + UINT *pValueLen, + WCHAR *DefaultVal); +*/ + +//--------------------------------------------------------------------------- +// EXPORTED FUNCTIONS +//--------------------------------------------------------------------------- + +PCHAR PacketGetVersion(); +PCHAR PacketGetDriverVersion(); +BOOLEAN PacketSetMinToCopy(LPADAPTER AdapterObject,int nbytes); +BOOLEAN PacketSetNumWrites(LPADAPTER AdapterObject,int nwrites); +BOOLEAN PacketSetMode(LPADAPTER AdapterObject,int mode); +BOOLEAN PacketSetReadTimeout(LPADAPTER AdapterObject,int timeout); +BOOLEAN PacketSetBpf(LPADAPTER AdapterObject,struct bpf_program *fp); +BOOLEAN PacketSetLoopbackBehavior(LPADAPTER AdapterObject, UINT LoopbackBehavior); +INT PacketSetSnapLen(LPADAPTER AdapterObject,int snaplen); +BOOLEAN PacketGetStats(LPADAPTER AdapterObject,struct bpf_stat *s); +BOOLEAN PacketGetStatsEx(LPADAPTER AdapterObject,struct bpf_stat *s); +BOOLEAN PacketSetBuff(LPADAPTER AdapterObject,int dim); +BOOLEAN PacketGetNetType (LPADAPTER AdapterObject,NetType *type); +LPADAPTER PacketOpenAdapter(PCHAR AdapterName); +BOOLEAN PacketSendPacket(LPADAPTER AdapterObject,LPPACKET pPacket,BOOLEAN Sync); +INT PacketSendPackets(LPADAPTER AdapterObject,PVOID PacketBuff,ULONG Size, BOOLEAN Sync); +LPPACKET PacketAllocatePacket(void); +VOID PacketInitPacket(LPPACKET lpPacket,PVOID Buffer,UINT Length); +VOID PacketFreePacket(LPPACKET lpPacket); +BOOLEAN PacketReceivePacket(LPADAPTER AdapterObject,LPPACKET lpPacket,BOOLEAN Sync); +BOOLEAN PacketSetHwFilter(LPADAPTER AdapterObject,ULONG Filter); +BOOLEAN PacketGetAdapterNames(PTSTR pStr,PULONG BufferSize); +BOOLEAN PacketGetNetInfoEx(PCHAR AdapterName, npf_if_addr* buffer, PLONG NEntries); +BOOLEAN PacketRequest(LPADAPTER AdapterObject,BOOLEAN Set,PPACKET_OID_DATA OidData); +HANDLE PacketGetReadEvent(LPADAPTER AdapterObject); +BOOLEAN PacketSetDumpName(LPADAPTER AdapterObject, void *name, int len); +BOOLEAN PacketSetDumpLimits(LPADAPTER AdapterObject, UINT maxfilesize, UINT maxnpacks); +BOOLEAN PacketIsDumpEnded(LPADAPTER AdapterObject, BOOLEAN sync); +BOOL PacketStopDriver(); +VOID PacketCloseAdapter(LPADAPTER lpAdapter); +BOOLEAN PacketStartOem(PCHAR errorString, UINT errorStringLength); +BOOLEAN PacketStartOemEx(PCHAR errorString, UINT errorStringLength, ULONG flags); +PAirpcapHandle PacketGetAirPcapHandle(LPADAPTER AdapterObject); + +// +// Used by PacketStartOemEx +// +#define PACKET_START_OEM_NO_NETMON 0x00000001 + +#ifdef __cplusplus +} +#endif + +#endif //__PACKET32 diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/PacketData.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/PacketData.h new file mode 100644 index 0000000..8124db6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/PacketData.h @@ -0,0 +1,267 @@ +char pkt1[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x30, 0x09, 0x9c, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x07, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc7, 0x35, 0x00, 0x00, 0x00, 0x00, 0x70, 0x02, +0x40, 0x00, 0xdf, 0xab, 0x00, 0x00, 0x02, 0x04, +0x05, 0xb4, 0x01, 0x01, 0x04, 0x02 }; + +char pkt2[] = { +0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, +0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, +0x00, 0x2c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06, +0xf8, 0xa6, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, +0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, +0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, +0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, +0x05, 0x92 }; + +char pkt3[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0x9e, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x0d, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, +0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; + +char pkt4[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x02, 0x27, 0x09, 0x9f, 0x40, 0x00, 0x80, 0x06, +0x6d, 0x0d, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x18, +0x42, 0xd8, 0x84, 0x3e, 0x00, 0x00, 0x47, 0x45, +0x54, 0x20, 0x2f, 0x20, 0x48, 0x54, 0x54, 0x50, +0x2f, 0x31, 0x2e, 0x31, 0x0d, 0x0a, 0x41, 0x63, +0x63, 0x65, 0x70, 0x74, 0x3a, 0x20, 0x69, 0x6d, +0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0x2c, +0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x78, +0x2d, 0x78, 0x62, 0x69, 0x74, 0x6d, 0x61, 0x70, +0x2c, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, +0x6a, 0x70, 0x65, 0x67, 0x2c, 0x20, 0x69, 0x6d, +0x61, 0x67, 0x65, 0x2f, 0x70, 0x6a, 0x70, 0x65, +0x67, 0x2c, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, +0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, +0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, 0x65, 0x78, +0x63, 0x65, 0x6c, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x6d, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x2c, +0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, +0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, 0x6e, 0x64, +0x2e, 0x6d, 0x73, 0x2d, 0x70, 0x6f, 0x77, 0x65, +0x72, 0x70, 0x6f, 0x69, 0x6e, 0x74, 0x2c, 0x20, +0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, +0x69, 0x6f, 0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, +0x2d, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, +0x74, 0x69, 0x6f, 0x6e, 0x2c, 0x20, 0x61, 0x70, +0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, +0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, 0x2d, 0x78, +0x62, 0x61, 0x70, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x76, 0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, +0x78, 0x70, 0x73, 0x64, 0x6f, 0x63, 0x75, 0x6d, +0x65, 0x6e, 0x74, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x78, 0x61, 0x6d, 0x6c, 0x2b, 0x78, 0x6d, +0x6c, 0x2c, 0x20, 0x2a, 0x2f, 0x2a, 0x0d, 0x0a, +0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x4c, +0x61, 0x6e, 0x67, 0x75, 0x61, 0x67, 0x65, 0x3a, +0x20, 0x65, 0x6e, 0x2d, 0x67, 0x62, 0x0d, 0x0a, +0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x45, +0x6e, 0x63, 0x6f, 0x64, 0x69, 0x6e, 0x67, 0x3a, +0x20, 0x67, 0x7a, 0x69, 0x70, 0x2c, 0x20, 0x64, +0x65, 0x66, 0x6c, 0x61, 0x74, 0x65, 0x0d, 0x0a, +0x55, 0x73, 0x65, 0x72, 0x2d, 0x41, 0x67, 0x65, +0x6e, 0x74, 0x3a, 0x20, 0x4d, 0x6f, 0x7a, 0x69, +0x6c, 0x6c, 0x61, 0x2f, 0x34, 0x2e, 0x30, 0x20, +0x28, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, +0x62, 0x6c, 0x65, 0x3b, 0x20, 0x4d, 0x53, 0x49, +0x45, 0x20, 0x36, 0x2e, 0x30, 0x3b, 0x20, 0x57, +0x69, 0x6e, 0x64, 0x6f, 0x77, 0x73, 0x20, 0x4e, +0x54, 0x20, 0x35, 0x2e, 0x31, 0x3b, 0x20, 0x53, +0x56, 0x31, 0x3b, 0x20, 0x47, 0x6f, 0x6f, 0x67, +0x6c, 0x65, 0x54, 0x35, 0x3b, 0x20, 0x2e, 0x4e, +0x45, 0x54, 0x20, 0x43, 0x4c, 0x52, 0x20, 0x32, +0x2e, 0x30, 0x2e, 0x35, 0x30, 0x37, 0x32, 0x37, +0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, +0x4c, 0x52, 0x20, 0x33, 0x2e, 0x30, 0x2e, 0x30, +0x34, 0x35, 0x30, 0x36, 0x2e, 0x36, 0x34, 0x38, +0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, +0x4c, 0x52, 0x20, 0x33, 0x2e, 0x35, 0x2e, 0x32, +0x31, 0x30, 0x32, 0x32, 0x29, 0x0d, 0x0a, 0x48, +0x6f, 0x73, 0x74, 0x3a, 0x20, 0x31, 0x39, 0x32, +0x2e, 0x31, 0x36, 0x38, 0x2e, 0x30, 0x2e, 0x31, +0x32, 0x0d, 0x0a, 0x43, 0x6f, 0x6e, 0x6e, 0x65, +0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x4b, +0x65, 0x65, 0x70, 0x2d, 0x41, 0x6c, 0x69, 0x76, +0x65, 0x0d, 0x0a, 0x0d, 0x0a }; + +char pkt5[] = { +0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, +0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, +0x00, 0x2c, 0x00, 0x02, 0x00, 0x00, 0x40, 0x06, +0xf8, 0xa5, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, +0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, +0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, +0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, +0x05, 0x92 }; + +char pkt6[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0xa1, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x0a, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, +0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; + +char pkt7[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x02, 0x27, 0x09, 0xa2, 0x40, 0x00, 0x80, 0x06, +0x6d, 0x0a, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x18, +0x42, 0xd8, 0x84, 0x3e, 0x00, 0x00, 0x47, 0x45, +0x54, 0x20, 0x2f, 0x20, 0x48, 0x54, 0x54, 0x50, +0x2f, 0x31, 0x2e, 0x31, 0x0d, 0x0a, 0x41, 0x63, +0x63, 0x65, 0x70, 0x74, 0x3a, 0x20, 0x69, 0x6d, +0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0x2c, +0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x78, +0x2d, 0x78, 0x62, 0x69, 0x74, 0x6d, 0x61, 0x70, +0x2c, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, +0x6a, 0x70, 0x65, 0x67, 0x2c, 0x20, 0x69, 0x6d, +0x61, 0x67, 0x65, 0x2f, 0x70, 0x6a, 0x70, 0x65, +0x67, 0x2c, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, +0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, +0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, 0x65, 0x78, +0x63, 0x65, 0x6c, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x6d, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x2c, +0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, +0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, 0x6e, 0x64, +0x2e, 0x6d, 0x73, 0x2d, 0x70, 0x6f, 0x77, 0x65, +0x72, 0x70, 0x6f, 0x69, 0x6e, 0x74, 0x2c, 0x20, +0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, +0x69, 0x6f, 0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, +0x2d, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, +0x74, 0x69, 0x6f, 0x6e, 0x2c, 0x20, 0x61, 0x70, +0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, +0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, 0x2d, 0x78, +0x62, 0x61, 0x70, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x76, 0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, +0x78, 0x70, 0x73, 0x64, 0x6f, 0x63, 0x75, 0x6d, +0x65, 0x6e, 0x74, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x78, 0x61, 0x6d, 0x6c, 0x2b, 0x78, 0x6d, +0x6c, 0x2c, 0x20, 0x2a, 0x2f, 0x2a, 0x0d, 0x0a, +0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x4c, +0x61, 0x6e, 0x67, 0x75, 0x61, 0x67, 0x65, 0x3a, +0x20, 0x65, 0x6e, 0x2d, 0x67, 0x62, 0x0d, 0x0a, +0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x45, +0x6e, 0x63, 0x6f, 0x64, 0x69, 0x6e, 0x67, 0x3a, +0x20, 0x67, 0x7a, 0x69, 0x70, 0x2c, 0x20, 0x64, +0x65, 0x66, 0x6c, 0x61, 0x74, 0x65, 0x0d, 0x0a, +0x55, 0x73, 0x65, 0x72, 0x2d, 0x41, 0x67, 0x65, +0x6e, 0x74, 0x3a, 0x20, 0x4d, 0x6f, 0x7a, 0x69, +0x6c, 0x6c, 0x61, 0x2f, 0x34, 0x2e, 0x30, 0x20, +0x28, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, +0x62, 0x6c, 0x65, 0x3b, 0x20, 0x4d, 0x53, 0x49, +0x45, 0x20, 0x36, 0x2e, 0x30, 0x3b, 0x20, 0x57, +0x69, 0x6e, 0x64, 0x6f, 0x77, 0x73, 0x20, 0x4e, +0x54, 0x20, 0x35, 0x2e, 0x31, 0x3b, 0x20, 0x53, +0x56, 0x31, 0x3b, 0x20, 0x47, 0x6f, 0x6f, 0x67, +0x6c, 0x65, 0x54, 0x35, 0x3b, 0x20, 0x2e, 0x4e, +0x45, 0x54, 0x20, 0x43, 0x4c, 0x52, 0x20, 0x32, +0x2e, 0x30, 0x2e, 0x35, 0x30, 0x37, 0x32, 0x37, +0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, +0x4c, 0x52, 0x20, 0x33, 0x2e, 0x30, 0x2e, 0x30, +0x34, 0x35, 0x30, 0x36, 0x2e, 0x36, 0x34, 0x38, +0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, +0x4c, 0x52, 0x20, 0x33, 0x2e, 0x35, 0x2e, 0x32, +0x31, 0x30, 0x32, 0x32, 0x29, 0x0d, 0x0a, 0x48, +0x6f, 0x73, 0x74, 0x3a, 0x20, 0x31, 0x39, 0x32, +0x2e, 0x31, 0x36, 0x38, 0x2e, 0x30, 0x2e, 0x31, +0x32, 0x0d, 0x0a, 0x43, 0x6f, 0x6e, 0x6e, 0x65, +0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x4b, +0x65, 0x65, 0x70, 0x2d, 0x41, 0x6c, 0x69, 0x76, +0x65, 0x0d, 0x0a, 0x0d, 0x0a }; + +char pkt8[] = { +0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, +0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, +0x00, 0x2c, 0x00, 0x03, 0x00, 0x00, 0x40, 0x06, +0xf8, 0xa4, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, +0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, +0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, +0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, +0x05, 0x92 }; + +char pkt9[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0xa3, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x08, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, +0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; + +char pkt10[] = { +0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, +0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, +0x00, 0x2c, 0x00, 0x04, 0x00, 0x00, 0x40, 0x06, +0xf8, 0xa3, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, +0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, +0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, +0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, +0x05, 0x92 }; + +char pkt11[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0xa6, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x05, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, +0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; + +char pkt12[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0xa7, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x04, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x14, +0x00, 0x00, 0x43, 0xf4, 0x00, 0x00 }; + + +typedef struct +{ + char *pcData; + int iDataLen; +} xPacketData; + +xPacketData xAllPackets[] = +{ + { pkt1, sizeof( pkt1 ) }, +// { pkt2, sizeof( pkt2 ) }, + { pkt3, sizeof( pkt3 ) }, + { pkt4, sizeof( pkt4 ) }, +// { pkt5, sizeof( pkt5 ) }, + { pkt6, sizeof( pkt6 ) }, + { pkt7, sizeof( pkt7 ) }, + { pkt8, sizeof( pkt8 ) }, + { pkt9, sizeof( pkt9 ) }, + { pkt10, sizeof( pkt10 ) }, +// { pkt11, sizeof( pkt11 ) }, +// { pkt12, sizeof( pkt12 ) }, +// { pkt13, sizeof( pkt13 ) }, +// { pkt14, sizeof( pkt14 ) }, +// { pkt15, sizeof( pkt15 ) }, +// { pkt16, sizeof( pkt16 ) }, +}; diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Win32-Extensions.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Win32-Extensions.h new file mode 100644 index 0000000..d3b063b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Win32-Extensions.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 1999 - 2005 NetGroup, Politecnico di Torino (Italy) + * Copyright (c) 2005 - 2006 CACE Technologies, Davis (California) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Politecnico di Torino, CACE Technologies + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __WIN32_EXTENSIONS_H__ +#define __WIN32_EXTENSIONS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Definitions */ + +/*! + \brief A queue of raw packets that will be sent to the network with pcap_sendqueue_transmit(). +*/ +struct pcap_send_queue +{ + u_int maxlen; ///< Maximum size of the the queue, in bytes. This variable contains the size of the buffer field. + u_int len; ///< Current size of the queue, in bytes. + char *buffer; ///< Buffer containing the packets to be sent. +}; + +typedef struct pcap_send_queue pcap_send_queue; + +/*! + \brief This typedef is a support for the pcap_get_airpcap_handle() function +*/ +#if !defined(AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_) +#define AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ +typedef struct _AirpcapHandle *PAirpcapHandle; +#endif + +#define BPF_MEM_EX_IMM 0xc0 +#define BPF_MEM_EX_IND 0xe0 + +/*used for ST*/ +#define BPF_MEM_EX 0xc0 +#define BPF_TME 0x08 + +#define BPF_LOOKUP 0x90 +#define BPF_EXECUTE 0xa0 +#define BPF_INIT 0xb0 +#define BPF_VALIDATE 0xc0 +#define BPF_SET_ACTIVE 0xd0 +#define BPF_RESET 0xe0 +#define BPF_SET_MEMORY 0x80 +#define BPF_GET_REGISTER_VALUE 0x70 +#define BPF_SET_REGISTER_VALUE 0x60 +#define BPF_SET_WORKING 0x50 +#define BPF_SET_ACTIVE_READ 0x40 +#define BPF_SET_AUTODELETION 0x30 +#define BPF_SEPARATION 0xff + +/* Prototypes */ +pcap_send_queue* pcap_sendqueue_alloc(u_int memsize); + +void pcap_sendqueue_destroy(pcap_send_queue* queue); + +int pcap_sendqueue_queue(pcap_send_queue* queue, const struct pcap_pkthdr *pkt_header, const u_char *pkt_data); + +u_int pcap_sendqueue_transmit(pcap_t *p, pcap_send_queue* queue, int sync); + +HANDLE pcap_getevent(pcap_t *p); + +struct pcap_stat *pcap_stats_ex(pcap_t *p, int *pcap_stat_size); + +int pcap_setuserbuffer(pcap_t *p, int size); + +int pcap_live_dump(pcap_t *p, char *filename, int maxsize, int maxpacks); + +int pcap_live_dump_ended(pcap_t *p, int sync); + +int pcap_offline_filter(struct bpf_program *prog, const struct pcap_pkthdr *header, const u_char *pkt_data); + +int pcap_start_oem(char* err_str, int flags); + +PAirpcapHandle pcap_get_airpcap_handle(pcap_t *p); + +#ifdef __cplusplus +} +#endif + +#endif //__WIN32_EXTENSIONS_H__ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c new file mode 100644 index 0000000..a56116f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c @@ -0,0 +1,335 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* WinPCap includes. */ +#include "pcap.h" +#include "remote-ext.h" + +/* uIP includes. */ +#include "net/uip.h" +#include "net/uip_arp.h" +#include "net/clock-arch.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* + * Query the computer the simulation is being executed on to find the network + * interfaces it has installed. + */ +static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ); + +/* + * Open the network interface. The number of the interface to be opened is set + * by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. + */ +static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ); + +/* + * Configure the capture filter to allow blocking reads, and to filter out + * packets that are not of interest to this demo. + */ +static void prvConfigureCaptureBehaviour( void ); + +pcap_t *pxOpenedInterfaceHandle = NULL; +LARGE_INTEGER freq, sys_start_time; + +#define archNUM_BUFFERS 5 +#define archNUM_BUFFER_POINTERS ( archNUM_BUFFERS - 1 ) + +static void prvInterruptSimulator( void *pvParameters ); + +static unsigned char ucEthernetBuffer[ archNUM_BUFFERS ][ UIP_CONF_BUFFER_SIZE ]; +static unsigned char *pucEthernetBufferPointers[ archNUM_BUFFER_POINTERS ]; + +static long lLengthOfDataInBuffer[ archNUM_BUFFER_POINTERS ] = { 0 }; +static unsigned char ucNextBufferToFill = 0U, ucNextBufferToProcess = 0U; + +unsigned char *uip_buf = NULL; +char cErrorBuffer[PCAP_ERRBUF_SIZE]; + +void vNetifTx( void ) +{ + pcap_sendpacket( pxOpenedInterfaceHandle, uip_buf, uip_len ); + pcap_sendpacket( pxOpenedInterfaceHandle, uip_buf, uip_len ); +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxNetifRx( void ) +{ +unsigned portBASE_TYPE xDataLen; +unsigned char *pucTemp; + + /* Check there is really data available. */ + xDataLen = lLengthOfDataInBuffer[ ucNextBufferToProcess ]; + if( xDataLen != 0L ) + { + + /* The buffer pointed to by uip_buf is going to change. Remember which + buffer uip_buf is currently pointing to. */ + pucTemp = uip_buf; + + /* Point uip_buf at the next buffer that contains data. */ + uip_buf = pucEthernetBufferPointers[ ucNextBufferToProcess ]; + + /* The buffer pointed to by + pucEthernetBufferPointeres[ ucNextBufferToProcess ] is now in use by + uip_buf, but the buffer uip_buf was pointing to on entry to this + function is free. Set + pucEthernetBufferPointeres[ ucNextBufferToProcess ] to the free + buffer. */ + pucEthernetBufferPointers[ ucNextBufferToProcess ] = pucTemp; + lLengthOfDataInBuffer[ ucNextBufferToProcess ] = 0L; + + ucNextBufferToProcess++; + if( ucNextBufferToProcess >= archNUM_BUFFER_POINTERS ) + { + ucNextBufferToProcess = 0L; + } + } + + return xDataLen; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xNetifInit( void ) +{ +portBASE_TYPE x; +pcap_if_t *pxAllNetworkInterfaces; + + /* Allocate a free buffer to each buffer pointer. */ + for( x = 0; x < sizeof( pucEthernetBufferPointers ) / sizeof( unsigned char * ); x++ ) + { + pucEthernetBufferPointers[ x ] = &( ucEthernetBuffer[ x ][ 0 ] ); + } + + /* Start with uip_buf pointing to a buffer that is not referenced from the + pucEthernetBufferPointers[] array. */ + uip_buf = &( ucEthernetBuffer[ archNUM_BUFFERS - 1 ][ 0 ] ); + + /* Query the computer the simulation is being executed on to find the + network interfaces it has installed. */ + pxAllNetworkInterfaces = prvPrintAvailableNetworkInterfaces(); + + /* Open the network interface. The number of the interface to be opened is + set by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. + Calling this function will set the pxOpenedInterfaceHandle variable. If, + after calling this function, pxOpenedInterfaceHandle is equal to NULL, then + the interface could not be opened. */ + if( pxAllNetworkInterfaces != NULL ) + { + prvOpenSelectedNetworkInterface( pxAllNetworkInterfaces ); + } + + + return x; +} +/*-----------------------------------------------------------*/ + +static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ) +{ +pcap_if_t * pxAllNetworkInterfaces = NULL, *xInterface; +long lInterfaceNumber = 1; + + if( pcap_findalldevs_ex( PCAP_SRC_IF_STRING, NULL, &pxAllNetworkInterfaces, cErrorBuffer ) == -1 ) + { + printf( "\r\nCould not obtain a list of network interfaces\r\n%s\r\n", cErrorBuffer ); + pxAllNetworkInterfaces = NULL; + } + + if( pxAllNetworkInterfaces != NULL ) + { + /* Print out the list of network interfaces. The first in the list + is interface '1', not interface '0'. */ + for( xInterface = pxAllNetworkInterfaces; xInterface != NULL; xInterface = xInterface->next ) + { + printf( "%d. %s", lInterfaceNumber, xInterface->name ); + + if( xInterface->description != NULL ) + { + printf( " (%s)\r\n", xInterface->description ); + } + else + { + printf( " (No description available)\r\n") ; + } + + lInterfaceNumber++; + } + } + + if( lInterfaceNumber == 1 ) + { + /* The interface number was never incremented, so the above for() loop + did not execute meaning no interfaces were found. */ + printf( " \r\nNo network interfaces were found.\r\n" ); + pxAllNetworkInterfaces = NULL; + } + + printf( "\r\nThe interface that will be opened is set by configNETWORK_INTERFACE_TO_USE which should be defined in FreeRTOSConfig.h\r\n" ); + printf( "Attempting to open interface number %d.\r\n", configNETWORK_INTERFACE_TO_USE ); + + if( ( configNETWORK_INTERFACE_TO_USE < 1L ) || ( configNETWORK_INTERFACE_TO_USE > lInterfaceNumber ) ) + { + printf("\r\nconfigNETWORK_INTERFACE_TO_USE is not in the valid range.\r\n" ); + + if( pxAllNetworkInterfaces != NULL ) + { + /* Free the device list, as no devices are going to be opened. */ + pcap_freealldevs( pxAllNetworkInterfaces ); + pxAllNetworkInterfaces = NULL; + } + } + + return pxAllNetworkInterfaces; +} +/*-----------------------------------------------------------*/ + +static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ) +{ +pcap_if_t *xInterface; +long x; + + /* Walk the list of devices until the selected device is located. */ + xInterface = pxAllNetworkInterfaces; + for( x = 0L; x < ( configNETWORK_INTERFACE_TO_USE - 1L ); x++ ) + { + xInterface = xInterface->next; + } + + /* Open the selected interface. */ + pxOpenedInterfaceHandle = pcap_open( xInterface->name, /* The name of the selected interface. */ + UIP_CONF_BUFFER_SIZE, /* The size of the packet to capture. */ + PCAP_OPENFLAG_PROMISCUOUS, /* Open in promiscious mode as the MAC and + IP address is going to be "simulated", and + not be the real MAC and IP address. This allows + trafic to the simulated IP address to be routed + to uIP, and trafic to the real IP address to be + routed to the Windows TCP/IP stack. */ + 0xfffffffL, /* The read time out. This is going to block + until data is available. */ + NULL, /* No authentication is required as this is + not a remote capture session. */ + cErrorBuffer + ); + + if ( pxOpenedInterfaceHandle == NULL ) + { + printf( "\r\n%s is not supported by WinPcap and cannot be opened\r\n", xInterface->name ); + } + else + { + /* Configure the capture filter to allow blocking reads, and to filter + out packets that are not of interest to this demo. */ + prvConfigureCaptureBehaviour(); + } + + /* The device list is no longer required. */ + pcap_freealldevs( pxAllNetworkInterfaces ); +} +/*-----------------------------------------------------------*/ + +static void prvConfigureCaptureBehaviour( void ) +{ +struct bpf_program xFilterCode; +const long lMinBytesToCopy = 10L, lBlocking = 0L; +unsigned long ulNetMask; + + /* Unblock a read as soon as anything is received. */ + pcap_setmintocopy( pxOpenedInterfaceHandle, lMinBytesToCopy ); + + /* Allow blocking. */ + pcap_setnonblock( pxOpenedInterfaceHandle, lBlocking, cErrorBuffer ); + + /* Set up a filter so only the packets of interest are passed to the uIP + stack. cErrorBuffer is used for convenience to create the string. Don't + confuse this with an error message. */ + sprintf( cErrorBuffer, "broadcast or multicast or host %d.%d.%d.%d", configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 ); + + ulNetMask = ( configNET_MASK3 << 24UL ) | ( configNET_MASK2 << 16UL ) | ( configNET_MASK1 << 8L ) | configNET_MASK0; + + if( pcap_compile(pxOpenedInterfaceHandle, &xFilterCode, cErrorBuffer, 1, ulNetMask ) < 0 ) + { + printf("\r\nThe packet filter string is invalid\r\n" ); + } + else + { + if( pcap_setfilter( pxOpenedInterfaceHandle, &xFilterCode ) < 0 ) + { + printf( "\r\nAn error occurred setting the packet filter.\r\n" ); + } + } + + /* Create a task that simulates an interrupt in a real system. This will + block waiting for packets, then send a message to the uIP task when data + is available. */ + xTaskCreate( prvInterruptSimulator, "MAC_ISR", configMINIMAL_STACK_SIZE, NULL, ( configuIP_TASK_PRIORITY - 1 ), NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvInterruptSimulator( void *pvParameters ) +{ +static struct pcap_pkthdr *pxHeader; +const unsigned char *pucPacketData; +extern QueueHandle_t xEMACEventQueue; +const unsigned long ulRxEvent = uipETHERNET_RX_EVENT; +long lResult; + + /* Just to kill the compiler warning. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Get the next packet. */ + lResult = pcap_next_ex( pxOpenedInterfaceHandle, &pxHeader, &pucPacketData ); + if( lResult ) + { + /* Is the next buffer into which data should be placed free? */ + if( lLengthOfDataInBuffer[ ucNextBufferToFill ] == 0L ) + { + /* Copy the data from the captured packet into the buffer. */ + memcpy( pucEthernetBufferPointers[ ucNextBufferToFill ], pucPacketData, pxHeader->len ); + + /* Note the amount of data that was copied. */ + lLengthOfDataInBuffer[ ucNextBufferToFill ] = pxHeader->len; + + /* Move onto the next buffer, wrapping around if necessary. */ + ucNextBufferToFill++; + if( ucNextBufferToFill >= archNUM_BUFFER_POINTERS ) + { + ucNextBufferToFill = 0U; + } + + /* Data was received and stored. Send a message to the uIP task + to let it know. */ + xQueueSendToBack( xEMACEventQueue, &ulRxEvent, portMAX_DELAY ); + } + } + } +} + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/bittypes.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/bittypes.h new file mode 100644 index 0000000..f55fcec --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/bittypes.h @@ -0,0 +1,137 @@ +/* + * Copyright (C) 1999 WIDE Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _BITTYPES_H +#define _BITTYPES_H + +#ifndef HAVE_U_INT8_T + +#if SIZEOF_CHAR == 1 +typedef unsigned char u_int8_t; +typedef signed char _int8_t; +#elif SIZEOF_INT == 1 +typedef unsigned int u_int8_t; +typedef signed int int8_t; +#else /* XXX */ +#error "there's no appropriate type for u_int8_t" +#endif +#define HAVE_U_INT8_T 1 +#define HAVE_INT8_T 1 + +#endif /* HAVE_U_INT8_T */ + +#ifndef HAVE_U_INT16_T + +#if SIZEOF_SHORT == 2 +typedef unsigned short u_int16_t; +typedef signed short _int16_t; +#elif SIZEOF_INT == 2 +typedef unsigned int u_int16_t; +typedef signed int int16_t; +#elif SIZEOF_CHAR == 2 +typedef unsigned char u_int16_t; +typedef signed char int16_t; +#else /* XXX */ +#error "there's no appropriate type for u_int16_t" +#endif +#define HAVE_U_INT16_T 1 +#define HAVE_INT16_T 1 + +#endif /* HAVE_U_INT16_T */ + +#ifndef HAVE_U_INT32_T + +#if SIZEOF_INT == 4 +typedef unsigned int u_int32_t; +typedef signed int _int32_t; +#elif SIZEOF_LONG == 4 +typedef unsigned long u_int32_t; +typedef signed long int32_t; +#elif SIZEOF_SHORT == 4 +typedef unsigned short u_int32_t; +typedef signed short int32_t; +#else /* XXX */ +#error "there's no appropriate type for u_int32_t" +#endif +#define HAVE_U_INT32_T 1 +#define HAVE_INT32_T 1 + +#endif /* HAVE_U_INT32_T */ + +#ifndef HAVE_U_INT64_T +#if SIZEOF_LONG_LONG == 8 +typedef unsigned long long u_int64_t; +typedef long long int64_t; +#elif defined(_MSC_EXTENSIONS) +typedef unsigned _int64 u_int64_t; +typedef _int64 int64_t; +#elif SIZEOF_INT == 8 +typedef unsigned int u_int64_t; +#elif SIZEOF_LONG == 8 +typedef unsigned long u_int64_t; +#elif SIZEOF_SHORT == 8 +typedef unsigned short u_int64_t; +#else /* XXX */ +#error "there's no appropriate type for u_int64_t" +#endif + +#endif /* HAVE_U_INT64_T */ + +#ifndef PRId64 +#ifdef _MSC_EXTENSIONS +#define PRId64 "I64d" +#else /* _MSC_EXTENSIONS */ +#define PRId64 "lld" +#endif /* _MSC_EXTENSIONS */ +#endif /* PRId64 */ + +#ifndef PRIo64 +#ifdef _MSC_EXTENSIONS +#define PRIo64 "I64o" +#else /* _MSC_EXTENSIONS */ +#define PRIo64 "llo" +#endif /* _MSC_EXTENSIONS */ +#endif /* PRIo64 */ + +#ifndef PRIx64 +#ifdef _MSC_EXTENSIONS +#define PRIx64 "I64x" +#else /* _MSC_EXTENSIONS */ +#define PRIx64 "llx" +#endif /* _MSC_EXTENSIONS */ +#endif /* PRIx64 */ + +#ifndef PRIu64 +#ifdef _MSC_EXTENSIONS +#define PRIu64 "I64u" +#else /* _MSC_EXTENSIONS */ +#define PRIu64 "llu" +#endif /* _MSC_EXTENSIONS */ +#endif /* PRIu64 */ + +#endif /* _BITTYPES_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/ip6_misc.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/ip6_misc.h new file mode 100644 index 0000000..562fa61 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/ip6_misc.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 1993, 1994, 1997 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that: (1) source code distributions + * retain the above copyright notice and this paragraph in its entirety, (2) + * distributions including binary code include the above copyright notice and + * this paragraph in its entirety in the documentation or other materials + * provided with the distribution, and (3) all advertising materials mentioning + * features or use of this software display the following acknowledgement: + * ``This product includes software developed by the University of California, + * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of + * the University nor the names of its contributors may be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * @(#) $Header: /tcpdump/master/libpcap/Win32/Include/ip6_misc.h,v 1.5 2006-01-22 18:02:18 gianluca Exp $ (LBL) + */ + +/* + * This file contains a collage of declarations for IPv6 from FreeBSD not present in Windows + */ + +#include + +#include + +#ifndef __MINGW32__ +#define IN_MULTICAST(a) IN_CLASSD(a) +#endif + +#define IN_EXPERIMENTAL(a) ((((u_int32_t) (a)) & 0xf0000000) == 0xf0000000) + +#define IN_LOOPBACKNET 127 + +#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) +/* IPv6 address */ +struct in6_addr + { + union + { + u_int8_t u6_addr8[16]; + u_int16_t u6_addr16[8]; + u_int32_t u6_addr32[4]; + } in6_u; +#define s6_addr in6_u.u6_addr8 +#define s6_addr16 in6_u.u6_addr16 +#define s6_addr32 in6_u.u6_addr32 +#define s6_addr64 in6_u.u6_addr64 + }; + +#define IN6ADDR_ANY_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } +#define IN6ADDR_LOOPBACK_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1 } +#endif /* __MINGW32__ */ + + +#if (defined _MSC_VER) || (defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)) +typedef unsigned short sa_family_t; +#endif + + +#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) + +#define __SOCKADDR_COMMON(sa_prefix) \ + sa_family_t sa_prefix##family + +/* Ditto, for IPv6. */ +struct sockaddr_in6 + { + __SOCKADDR_COMMON (sin6_); + u_int16_t sin6_port; /* Transport layer port # */ + u_int32_t sin6_flowinfo; /* IPv6 flow information */ + struct in6_addr sin6_addr; /* IPv6 address */ + }; + +#define IN6_IS_ADDR_V4MAPPED(a) \ + ((((u_int32_t *) (a))[0] == 0) && (((u_int32_t *) (a))[1] == 0) && \ + (((u_int32_t *) (a))[2] == htonl (0xffff))) + +#define IN6_IS_ADDR_MULTICAST(a) (((u_int8_t *) (a))[0] == 0xff) + +#define IN6_IS_ADDR_LINKLOCAL(a) \ + ((((u_int32_t *) (a))[0] & htonl (0xffc00000)) == htonl (0xfe800000)) + +#define IN6_IS_ADDR_LOOPBACK(a) \ + (((u_int32_t *) (a))[0] == 0 && ((u_int32_t *) (a))[1] == 0 && \ + ((u_int32_t *) (a))[2] == 0 && ((u_int32_t *) (a))[3] == htonl (1)) +#endif /* __MINGW32__ */ + +#define ip6_vfc ip6_ctlun.ip6_un2_vfc +#define ip6_flow ip6_ctlun.ip6_un1.ip6_un1_flow +#define ip6_plen ip6_ctlun.ip6_un1.ip6_un1_plen +#define ip6_nxt ip6_ctlun.ip6_un1.ip6_un1_nxt +#define ip6_hlim ip6_ctlun.ip6_un1.ip6_un1_hlim +#define ip6_hops ip6_ctlun.ip6_un1.ip6_un1_hlim + +#define nd_rd_type nd_rd_hdr.icmp6_type +#define nd_rd_code nd_rd_hdr.icmp6_code +#define nd_rd_cksum nd_rd_hdr.icmp6_cksum +#define nd_rd_reserved nd_rd_hdr.icmp6_data32[0] + +/* + * IPV6 extension headers + */ +#define IPPROTO_HOPOPTS 0 /* IPv6 hop-by-hop options */ +#define IPPROTO_IPV6 41 /* IPv6 header. */ +#define IPPROTO_ROUTING 43 /* IPv6 routing header */ +#define IPPROTO_FRAGMENT 44 /* IPv6 fragmentation header */ +#define IPPROTO_ESP 50 /* encapsulating security payload */ +#define IPPROTO_AH 51 /* authentication header */ +#define IPPROTO_ICMPV6 58 /* ICMPv6 */ +#define IPPROTO_NONE 59 /* IPv6 no next header */ +#define IPPROTO_DSTOPTS 60 /* IPv6 destination options */ +#define IPPROTO_PIM 103 /* Protocol Independent Multicast. */ + +#define IPV6_RTHDR_TYPE_0 0 + +/* Option types and related macros */ +#define IP6OPT_PAD1 0x00 /* 00 0 00000 */ +#define IP6OPT_PADN 0x01 /* 00 0 00001 */ +#define IP6OPT_JUMBO 0xC2 /* 11 0 00010 = 194 */ +#define IP6OPT_JUMBO_LEN 6 +#define IP6OPT_ROUTER_ALERT 0x05 /* 00 0 00101 */ + +#define IP6OPT_RTALERT_LEN 4 +#define IP6OPT_RTALERT_MLD 0 /* Datagram contains an MLD message */ +#define IP6OPT_RTALERT_RSVP 1 /* Datagram contains an RSVP message */ +#define IP6OPT_RTALERT_ACTNET 2 /* contains an Active Networks msg */ +#define IP6OPT_MINLEN 2 + +#define IP6OPT_BINDING_UPDATE 0xc6 /* 11 0 00110 */ +#define IP6OPT_BINDING_ACK 0x07 /* 00 0 00111 */ +#define IP6OPT_BINDING_REQ 0x08 /* 00 0 01000 */ +#define IP6OPT_HOME_ADDRESS 0xc9 /* 11 0 01001 */ +#define IP6OPT_EID 0x8a /* 10 0 01010 */ + +#define IP6OPT_TYPE(o) ((o) & 0xC0) +#define IP6OPT_TYPE_SKIP 0x00 +#define IP6OPT_TYPE_DISCARD 0x40 +#define IP6OPT_TYPE_FORCEICMP 0x80 +#define IP6OPT_TYPE_ICMP 0xC0 + +#define IP6OPT_MUTABLE 0x20 + + +#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) +#ifndef EAI_ADDRFAMILY +struct addrinfo { + int ai_flags; /* AI_PASSIVE, AI_CANONNAME */ + int ai_family; /* PF_xxx */ + int ai_socktype; /* SOCK_xxx */ + int ai_protocol; /* 0 or IPPROTO_xxx for IPv4 and IPv6 */ + size_t ai_addrlen; /* length of ai_addr */ + char *ai_canonname; /* canonical name for hostname */ + struct sockaddr *ai_addr; /* binary address */ + struct addrinfo *ai_next; /* next structure in linked list */ +}; +#endif +#endif /* __MINGW32__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h new file mode 100644 index 0000000..cc4c1eb --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h @@ -0,0 +1,51 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef NET_IF_H +#define NET_IF_H + +/* + * Send uip_len bytes from uip_buf to the network interface selected by the + * configNETWORK_INTERFACE_TO_USE constant (defined in FreeRTOSConfig.h). + */ +void vNetifTx( void ); + +/* + * Receive bytes from the network interface selected by the + * configNETWORK_INTERFACE_TO_USE constant (defined in FreeRTOSConfig.h). The + * bytes are placed in uip_buf. The number of bytes copied into uip_buf is + * returned. + */ +unsigned portBASE_TYPE uxNetifRx( void ); + +/* + * Prepare a packet capture session. This will print out all the network + * interfaces available, and the one actually used is set by the + * configNETWORK_INTERFACE_TO_USE constant that is defined in + * FreeRTOSConfig.h. */ +portBASE_TYPE xNetifInit( void ); + +#endif /* NET_IF_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-bpf.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-bpf.h new file mode 100644 index 0000000..5fe129d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-bpf.h @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from the Stanford/CMU enet packet filter, + * (net/enet.c) distributed as part of 4.3BSD, and code contributed + * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence + * Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap-bpf.h,v 1.50 2007/04/01 21:43:55 guy Exp $ (LBL) + */ + +/* + * For backwards compatibility. + * + * Note to OS vendors: do NOT get rid of this file! Some applications + * might expect to be able to include . + */ +#include diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-namedb.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-namedb.h new file mode 100644 index 0000000..80a2f00 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-namedb.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 1994, 1996 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. + * 4. Neither the name of the University nor of the Laboratory may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap-namedb.h,v 1.13 2006/10/04 18:13:32 guy Exp $ (LBL) + */ + +/* + * For backwards compatibility. + * + * Note to OS vendors: do NOT get rid of this file! Some applications + * might expect to be able to include . + */ +#include diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-stdinc.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-stdinc.h new file mode 100644 index 0000000..f1ea03f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-stdinc.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2002 - 2005 NetGroup, Politecnico di Torino (Italy) + * Copyright (c) 2005 - 2009 CACE Technologies, Inc. Davis (California) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Politecnico di Torino nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap-stdinc.h,v 1.10.2.1 2008-10-06 15:38:39 gianluca Exp $ (LBL) + */ + +#define SIZEOF_CHAR 1 +#define SIZEOF_SHORT 2 +#define SIZEOF_INT 4 +#ifndef _MSC_EXTENSIONS +#define SIZEOF_LONG_LONG 8 +#endif + +/* + * Avoids a compiler warning in case this was already defined + * (someone defined _WINSOCKAPI_ when including 'windows.h', in order + * to prevent it from including 'winsock.h') + */ +#ifdef _WINSOCKAPI_ +#undef _WINSOCKAPI_ +#endif +//_RB_#include + +#include + +#include "bittypes.h" +#include +#include + +#ifndef __MINGW32__ +#include "IP6_misc.h" +#endif + +#define caddr_t char* + +#if _MSC_VER < 1500 +#define snprintf _snprintf +#define vsnprintf _vsnprintf +#define strdup _strdup +#endif + +#define inline __inline + +#ifdef __MINGW32__ +#include +#else /*__MINGW32__*/ +/* MSVC compiler */ +#ifndef _UINTPTR_T_DEFINED +#ifdef _WIN64 +typedef unsigned __int64 uintptr_t; +#else +typedef _W64 unsigned int uintptr_t; +#endif +#define _UINTPTR_T_DEFINED +#endif + +#ifndef _INTPTR_T_DEFINED +#ifdef _WIN64 +typedef __int64 intptr_t; +#else +typedef _W64 int intptr_t; +#endif +#define _INTPTR_T_DEFINED +#endif + +#endif /*__MINGW32__*/ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap.h new file mode 100644 index 0000000..ad8fc40 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap.h @@ -0,0 +1,407 @@ +/* -*- Mode: c; tab-width: 8; indent-tabs-mode: 1; c-basic-offset: 8; -*- */ +/* + * Copyright (c) 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. + * 4. Neither the name of the University nor of the Laboratory may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/pcap.h,v 1.4.2.11 2008-10-06 15:38:39 gianluca Exp $ (LBL) + */ + +#ifndef lib_pcap_pcap_h +#define lib_pcap_pcap_h + +#if defined(WIN32) + #include +#elif defined(MSDOS) + #include + #include /* u_int, u_char etc. */ +#else /* UN*X */ + #include + #include +#endif /* WIN32/MSDOS/UN*X */ + +#ifndef PCAP_DONT_INCLUDE_PCAP_BPF_H +#include +#endif + +#include + +#ifdef HAVE_REMOTE + // We have to define the SOCKET here, although it has been defined in sockutils.h + // This is to avoid the distribution of the 'sockutils.h' file around + // (for example in the WinPcap developer's pack) + #ifndef SOCKET + #ifdef WIN32 + #define SOCKET unsigned int + #else + #define SOCKET int + #endif + #endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define PCAP_VERSION_MAJOR 2 +#define PCAP_VERSION_MINOR 4 + +#define PCAP_ERRBUF_SIZE 256 + +/* + * Compatibility for systems that have a bpf.h that + * predates the bpf typedefs for 64-bit support. + */ +#if BPF_RELEASE - 0 < 199406 +typedef int bpf_int32; +typedef u_int bpf_u_int32; +#endif + +typedef struct pcap pcap_t; +typedef struct pcap_dumper pcap_dumper_t; +typedef struct pcap_if pcap_if_t; +typedef struct pcap_addr pcap_addr_t; + +/* + * The first record in the file contains saved values for some + * of the flags used in the printout phases of tcpdump. + * Many fields here are 32 bit ints so compilers won't insert unwanted + * padding; these files need to be interchangeable across architectures. + * + * Do not change the layout of this structure, in any way (this includes + * changes that only affect the length of fields in this structure). + * + * Also, do not change the interpretation of any of the members of this + * structure, in any way (this includes using values other than + * LINKTYPE_ values, as defined in "savefile.c", in the "linktype" + * field). + * + * Instead: + * + * introduce a new structure for the new format, if the layout + * of the structure changed; + * + * send mail to "tcpdump-workers@lists.tcpdump.org", requesting + * a new magic number for your new capture file format, and, when + * you get the new magic number, put it in "savefile.c"; + * + * use that magic number for save files with the changed file + * header; + * + * make the code in "savefile.c" capable of reading files with + * the old file header as well as files with the new file header + * (using the magic number to determine the header format). + * + * Then supply the changes as a patch at + * + * http://sourceforge.net/projects/libpcap/ + * + * so that future versions of libpcap and programs that use it (such as + * tcpdump) will be able to read your new capture file format. + */ +struct pcap_file_header { + bpf_u_int32 magic; + u_short version_major; + u_short version_minor; + bpf_int32 thiszone; /* gmt to local correction */ + bpf_u_int32 sigfigs; /* accuracy of timestamps */ + bpf_u_int32 snaplen; /* max length saved portion of each pkt */ + bpf_u_int32 linktype; /* data link type (LINKTYPE_*) */ +}; + +/* + * Macros for the value returned by pcap_datalink_ext(). + * + * If LT_FCS_LENGTH_PRESENT(x) is true, the LT_FCS_LENGTH(x) macro + * gives the FCS length of packets in the capture. + */ +#define LT_FCS_LENGTH_PRESENT(x) ((x) & 0x04000000) +#define LT_FCS_LENGTH(x) (((x) & 0xF0000000) >> 28) +#define LT_FCS_DATALINK_EXT(x) ((((x) & 0xF) << 28) | 0x04000000) + +typedef enum { + PCAP_D_INOUT = 0, + PCAP_D_IN, + PCAP_D_OUT +} pcap_direction_t; + +/* + * Generic per-packet information, as supplied by libpcap. + * + * The time stamp can and should be a "struct timeval", regardless of + * whether your system supports 32-bit tv_sec in "struct timeval", + * 64-bit tv_sec in "struct timeval", or both if it supports both 32-bit + * and 64-bit applications. The on-disk format of savefiles uses 32-bit + * tv_sec (and tv_usec); this structure is irrelevant to that. 32-bit + * and 64-bit versions of libpcap, even if they're on the same platform, + * should supply the appropriate version of "struct timeval", even if + * that's not what the underlying packet capture mechanism supplies. + */ +struct pcap_pkthdr { + struct timeval ts; /* time stamp */ + bpf_u_int32 caplen; /* length of portion present */ + bpf_u_int32 len; /* length this packet (off wire) */ +}; + +/* + * As returned by the pcap_stats() + */ +struct pcap_stat { + u_int ps_recv; /* number of packets received */ + u_int ps_drop; /* number of packets dropped */ + u_int ps_ifdrop; /* drops by interface XXX not yet supported */ +#ifdef HAVE_REMOTE + u_int ps_capt; /* number of packets that are received by the application; please get rid off the Win32 ifdef */ + u_int ps_sent; /* number of packets sent by the server on the network */ + u_int ps_netdrop; /* number of packets lost on the network */ +#endif /* HAVE_REMOTE */ +}; + +#ifdef MSDOS +/* + * As returned by the pcap_stats_ex() + */ +struct pcap_stat_ex { + u_long rx_packets; /* total packets received */ + u_long tx_packets; /* total packets transmitted */ + u_long rx_bytes; /* total bytes received */ + u_long tx_bytes; /* total bytes transmitted */ + u_long rx_errors; /* bad packets received */ + u_long tx_errors; /* packet transmit problems */ + u_long rx_dropped; /* no space in Rx buffers */ + u_long tx_dropped; /* no space available for Tx */ + u_long multicast; /* multicast packets received */ + u_long collisions; + + /* detailed rx_errors: */ + u_long rx_length_errors; + u_long rx_over_errors; /* receiver ring buff overflow */ + u_long rx_crc_errors; /* recv'd pkt with crc error */ + u_long rx_frame_errors; /* recv'd frame alignment error */ + u_long rx_fifo_errors; /* recv'r fifo overrun */ + u_long rx_missed_errors; /* recv'r missed packet */ + + /* detailed tx_errors */ + u_long tx_aborted_errors; + u_long tx_carrier_errors; + u_long tx_fifo_errors; + u_long tx_heartbeat_errors; + u_long tx_window_errors; + }; +#endif + +/* + * Item in a list of interfaces. + */ +struct pcap_if { + struct pcap_if *next; + char *name; /* name to hand to "pcap_open_live()" */ + char *description; /* textual description of interface, or NULL */ + struct pcap_addr *addresses; + bpf_u_int32 flags; /* PCAP_IF_ interface flags */ +}; + +#define PCAP_IF_LOOPBACK 0x00000001 /* interface is loopback */ + +/* + * Representation of an interface address. + */ +struct pcap_addr { + struct pcap_addr *next; + struct sockaddr *addr; /* address */ + struct sockaddr *netmask; /* netmask for that address */ + struct sockaddr *broadaddr; /* broadcast address for that address */ + struct sockaddr *dstaddr; /* P2P destination address for that address */ +}; + +typedef void (*pcap_handler)(u_char *, const struct pcap_pkthdr *, + const u_char *); + +/* + * Error codes for the pcap API. + * These will all be negative, so you can check for the success or + * failure of a call that returns these codes by checking for a + * negative value. + */ +#define PCAP_ERROR -1 /* generic error code */ +#define PCAP_ERROR_BREAK -2 /* loop terminated by pcap_breakloop */ +#define PCAP_ERROR_NOT_ACTIVATED -3 /* the capture needs to be activated */ +#define PCAP_ERROR_ACTIVATED -4 /* the operation can't be performed on already activated captures */ +#define PCAP_ERROR_NO_SUCH_DEVICE -5 /* no such device exists */ +#define PCAP_ERROR_RFMON_NOTSUP -6 /* this device doesn't support rfmon (monitor) mode */ +#define PCAP_ERROR_NOT_RFMON -7 /* operation supported only in monitor mode */ +#define PCAP_ERROR_PERM_DENIED -8 /* no permission to open the device */ +#define PCAP_ERROR_IFACE_NOT_UP -9 /* interface isn't up */ + +/* + * Warning codes for the pcap API. + * These will all be positive and non-zero, so they won't look like + * errors. + */ +#define PCAP_WARNING 1 /* generic warning code */ +#define PCAP_WARNING_PROMISC_NOTSUP 2 /* this device doesn't support promiscuous mode */ + +char *pcap_lookupdev(char *); +int pcap_lookupnet(const char *, bpf_u_int32 *, bpf_u_int32 *, char *); + +pcap_t *pcap_create(const char *, char *); +int pcap_set_snaplen(pcap_t *, int); +int pcap_set_promisc(pcap_t *, int); +int pcap_can_set_rfmon(pcap_t *); +int pcap_set_rfmon(pcap_t *, int); +int pcap_set_timeout(pcap_t *, int); +int pcap_set_buffer_size(pcap_t *, int); +int pcap_activate(pcap_t *); + +pcap_t *pcap_open_live(const char *, int, int, int, char *); +pcap_t *pcap_open_dead(int, int); +pcap_t *pcap_open_offline(const char *, char *); +#if defined(WIN32) +pcap_t *pcap_hopen_offline(intptr_t, char *); +#if !defined(LIBPCAP_EXPORTS) +#define pcap_fopen_offline(f,b) \ + pcap_hopen_offline(_get_osfhandle(_fileno(f)), b) +#else /*LIBPCAP_EXPORTS*/ +static pcap_t *pcap_fopen_offline(FILE *, char *); +#endif +#else /*WIN32*/ +pcap_t *pcap_fopen_offline(FILE *, char *); +#endif /*WIN32*/ + +void pcap_close(pcap_t *); +int pcap_loop(pcap_t *, int, pcap_handler, u_char *); +int pcap_dispatch(pcap_t *, int, pcap_handler, u_char *); +const u_char* + pcap_next(pcap_t *, struct pcap_pkthdr *); +int pcap_next_ex(pcap_t *, struct pcap_pkthdr **, const u_char **); +void pcap_breakloop(pcap_t *); +int pcap_stats(pcap_t *, struct pcap_stat *); +int pcap_setfilter(pcap_t *, struct bpf_program *); +int pcap_setdirection(pcap_t *, pcap_direction_t); +int pcap_getnonblock(pcap_t *, char *); +int pcap_setnonblock(pcap_t *, int, char *); +int pcap_inject(pcap_t *, const void *, size_t); +int pcap_sendpacket(pcap_t *, const u_char *, int); +const char *pcap_statustostr(int); +const char *pcap_strerror(int); +char *pcap_geterr(pcap_t *); +void pcap_perror(pcap_t *, char *); +int pcap_compile(pcap_t *, struct bpf_program *, const char *, int, + bpf_u_int32); +int pcap_compile_nopcap(int, int, struct bpf_program *, + const char *, int, bpf_u_int32); +void pcap_freecode(struct bpf_program *); +int pcap_offline_filter(struct bpf_program *, const struct pcap_pkthdr *, + const u_char *); +int pcap_datalink(pcap_t *); +int pcap_datalink_ext(pcap_t *); +int pcap_list_datalinks(pcap_t *, int **); +int pcap_set_datalink(pcap_t *, int); +void pcap_free_datalinks(int *); +int pcap_datalink_name_to_val(const char *); +const char *pcap_datalink_val_to_name(int); +const char *pcap_datalink_val_to_description(int); +int pcap_snapshot(pcap_t *); +int pcap_is_swapped(pcap_t *); +int pcap_major_version(pcap_t *); +int pcap_minor_version(pcap_t *); + +/* XXX */ +FILE *pcap_file(pcap_t *); +int pcap_fileno(pcap_t *); + +pcap_dumper_t *pcap_dump_open(pcap_t *, const char *); +pcap_dumper_t *pcap_dump_fopen(pcap_t *, FILE *fp); +FILE *pcap_dump_file(pcap_dumper_t *); +long pcap_dump_ftell(pcap_dumper_t *); +int pcap_dump_flush(pcap_dumper_t *); +void pcap_dump_close(pcap_dumper_t *); +void pcap_dump(u_char *, const struct pcap_pkthdr *, const u_char *); + +int pcap_findalldevs(pcap_if_t **, char *); +void pcap_freealldevs(pcap_if_t *); + +const char *pcap_lib_version(void); + +/* XXX this guy lives in the bpf tree */ +u_int bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int); +int bpf_validate(const struct bpf_insn *f, int len); +char *bpf_image(const struct bpf_insn *, int); +void bpf_dump(const struct bpf_program *, int); + +#if defined(WIN32) + +/* + * Win32 definitions + */ + +int pcap_setbuff(pcap_t *p, int dim); +int pcap_setmode(pcap_t *p, int mode); +int pcap_setmintocopy(pcap_t *p, int size); + +#ifdef WPCAP +/* Include file with the wpcap-specific extensions */ +#include +#endif /* WPCAP */ + +#define MODE_CAPT 0 +#define MODE_STAT 1 +#define MODE_MON 2 + +#elif defined(MSDOS) + +/* + * MS-DOS definitions + */ + +int pcap_stats_ex (pcap_t *, struct pcap_stat_ex *); +void pcap_set_wait (pcap_t *p, void (*yield)(void), int wait); +u_long pcap_mac_packets (void); + +#else /* UN*X */ + +/* + * UN*X definitions + */ + +int pcap_get_selectable_fd(pcap_t *); + +#endif /* WIN32/MSDOS/UN*X */ + +#ifdef HAVE_REMOTE +/* Includes most of the public stuff that is needed for the remote capture */ +#include +#endif /* HAVE_REMOTE */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bluetooth.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bluetooth.h new file mode 100644 index 0000000..7bf65df --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bluetooth.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006 Paolo Abeni (Italy) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * bluetooth data struct + * By Paolo Abeni + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/bluetooth.h,v 1.1 2007/09/22 02:10:17 guy Exp $ + */ + +#ifndef _PCAP_BLUETOOTH_STRUCTS_H__ +#define _PCAP_BLUETOOTH_STRUCTS_H__ + +/* + * Header prepended libpcap to each bluetooth h:4 frame. + * fields are in network byte order + */ +typedef struct _pcap_bluetooth_h4_header { + u_int32_t direction; /* if first bit is set direction is incoming */ +} pcap_bluetooth_h4_header; + + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bpf.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bpf.h new file mode 100644 index 0000000..9f4ca33 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bpf.h @@ -0,0 +1,934 @@ +/*- + * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from the Stanford/CMU enet packet filter, + * (net/enet.c) distributed as part of 4.3BSD, and code contributed + * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence + * Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)bpf.h 7.1 (Berkeley) 5/7/91 + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/bpf.h,v 1.19.2.8 2008-09-22 20:16:01 guy Exp $ (LBL) + */ + +/* + * This is libpcap's cut-down version of bpf.h; it includes only + * the stuff needed for the code generator and the userland BPF + * interpreter, and the libpcap APIs for setting filters, etc.. + * + * "pcap-bpf.c" will include the native OS version, as it deals with + * the OS's BPF implementation. + * + * XXX - should this all just be moved to "pcap.h"? + */ + +#ifndef BPF_MAJOR_VERSION + +#ifdef __cplusplus +extern "C" { +#endif + +/* BSD style release date */ +#define BPF_RELEASE 199606 + +#ifdef MSDOS /* must be 32-bit */ +typedef long bpf_int32; +typedef unsigned long bpf_u_int32; +#else +typedef int bpf_int32; +typedef u_int bpf_u_int32; +#endif + +/* + * Alignment macros. BPF_WORDALIGN rounds up to the next + * even multiple of BPF_ALIGNMENT. + */ +#ifndef __NetBSD__ +#define BPF_ALIGNMENT sizeof(bpf_int32) +#else +#define BPF_ALIGNMENT sizeof(long) +#endif +#define BPF_WORDALIGN(x) (((x)+(BPF_ALIGNMENT-1))&~(BPF_ALIGNMENT-1)) + +#define BPF_MAXBUFSIZE 0x8000 +#define BPF_MINBUFSIZE 32 + +/* + * Structure for "pcap_compile()", "pcap_setfilter()", etc.. + */ +struct bpf_program { + u_int bf_len; + struct bpf_insn *bf_insns; +}; + +/* + * Struct return by BIOCVERSION. This represents the version number of + * the filter language described by the instruction encodings below. + * bpf understands a program iff kernel_major == filter_major && + * kernel_minor >= filter_minor, that is, if the value returned by the + * running kernel has the same major number and a minor number equal + * equal to or less than the filter being downloaded. Otherwise, the + * results are undefined, meaning an error may be returned or packets + * may be accepted haphazardly. + * It has nothing to do with the source code version. + */ +struct bpf_version { + u_short bv_major; + u_short bv_minor; +}; +/* Current version number of filter architecture. */ +#define BPF_MAJOR_VERSION 1 +#define BPF_MINOR_VERSION 1 + +/* + * Data-link level type codes. + * + * Do *NOT* add new values to this list without asking + * "tcpdump-workers@lists.tcpdump.org" for a value. Otherwise, you run + * the risk of using a value that's already being used for some other + * purpose, and of having tools that read libpcap-format captures not + * being able to handle captures with your new DLT_ value, with no hope + * that they will ever be changed to do so (as that would destroy their + * ability to read captures using that value for that other purpose). + */ + +/* + * These are the types that are the same on all platforms, and that + * have been defined by for ages. + */ +#define DLT_NULL 0 /* BSD loopback encapsulation */ +#define DLT_EN10MB 1 /* Ethernet (10Mb) */ +#define DLT_EN3MB 2 /* Experimental Ethernet (3Mb) */ +#define DLT_AX25 3 /* Amateur Radio AX.25 */ +#define DLT_PRONET 4 /* Proteon ProNET Token Ring */ +#define DLT_CHAOS 5 /* Chaos */ +#define DLT_IEEE802 6 /* 802.5 Token Ring */ +#define DLT_ARCNET 7 /* ARCNET, with BSD-style header */ +#define DLT_SLIP 8 /* Serial Line IP */ +#define DLT_PPP 9 /* Point-to-point Protocol */ +#define DLT_FDDI 10 /* FDDI */ + +/* + * These are types that are different on some platforms, and that + * have been defined by for ages. We use #ifdefs to + * detect the BSDs that define them differently from the traditional + * libpcap + * + * XXX - DLT_ATM_RFC1483 is 13 in BSD/OS, and DLT_RAW is 14 in BSD/OS, + * but I don't know what the right #define is for BSD/OS. + */ +#define DLT_ATM_RFC1483 11 /* LLC-encapsulated ATM */ + +#ifdef __OpenBSD__ +#define DLT_RAW 14 /* raw IP */ +#else +#define DLT_RAW 12 /* raw IP */ +#endif + +/* + * Given that the only OS that currently generates BSD/OS SLIP or PPP + * is, well, BSD/OS, arguably everybody should have chosen its values + * for DLT_SLIP_BSDOS and DLT_PPP_BSDOS, which are 15 and 16, but they + * didn't. So it goes. + */ +#if defined(__NetBSD__) || defined(__FreeBSD__) +#ifndef DLT_SLIP_BSDOS +#define DLT_SLIP_BSDOS 13 /* BSD/OS Serial Line IP */ +#define DLT_PPP_BSDOS 14 /* BSD/OS Point-to-point Protocol */ +#endif +#else +#define DLT_SLIP_BSDOS 15 /* BSD/OS Serial Line IP */ +#define DLT_PPP_BSDOS 16 /* BSD/OS Point-to-point Protocol */ +#endif + +/* + * 17 is used for DLT_OLD_PFLOG in OpenBSD; + * OBSOLETE: DLT_PFLOG is 117 in OpenBSD now as well. See below. + * 18 is used for DLT_PFSYNC in OpenBSD; don't use it for anything else. + */ + +#define DLT_ATM_CLIP 19 /* Linux Classical-IP over ATM */ + +/* + * Apparently Redback uses this for its SmartEdge 400/800. I hope + * nobody else decided to use it, too. + */ +#define DLT_REDBACK_SMARTEDGE 32 + +/* + * These values are defined by NetBSD; other platforms should refrain from + * using them for other purposes, so that NetBSD savefiles with link + * types of 50 or 51 can be read as this type on all platforms. + */ +#define DLT_PPP_SERIAL 50 /* PPP over serial with HDLC encapsulation */ +#define DLT_PPP_ETHER 51 /* PPP over Ethernet */ + +/* + * The Axent Raptor firewall - now the Symantec Enterprise Firewall - uses + * a link-layer type of 99 for the tcpdump it supplies. The link-layer + * header has 6 bytes of unknown data, something that appears to be an + * Ethernet type, and 36 bytes that appear to be 0 in at least one capture + * I've seen. + */ +#define DLT_SYMANTEC_FIREWALL 99 + +/* + * Values between 100 and 103 are used in capture file headers as + * link-layer types corresponding to DLT_ types that differ + * between platforms; don't use those values for new DLT_ new types. + */ + +/* + * This value was defined by libpcap 0.5; platforms that have defined + * it with a different value should define it here with that value - + * a link type of 104 in a save file will be mapped to DLT_C_HDLC, + * whatever value that happens to be, so programs will correctly + * handle files with that link type regardless of the value of + * DLT_C_HDLC. + * + * The name DLT_C_HDLC was used by BSD/OS; we use that name for source + * compatibility with programs written for BSD/OS. + * + * libpcap 0.5 defined it as DLT_CHDLC; we define DLT_CHDLC as well, + * for source compatibility with programs written for libpcap 0.5. + */ +#define DLT_C_HDLC 104 /* Cisco HDLC */ +#define DLT_CHDLC DLT_C_HDLC + +#define DLT_IEEE802_11 105 /* IEEE 802.11 wireless */ + +/* + * 106 is reserved for Linux Classical IP over ATM; it's like DLT_RAW, + * except when it isn't. (I.e., sometimes it's just raw IP, and + * sometimes it isn't.) We currently handle it as DLT_LINUX_SLL, + * so that we don't have to worry about the link-layer header.) + */ + +/* + * Frame Relay; BSD/OS has a DLT_FR with a value of 11, but that collides + * with other values. + * DLT_FR and DLT_FRELAY packets start with the Q.922 Frame Relay header + * (DLCI, etc.). + */ +#define DLT_FRELAY 107 + +/* + * OpenBSD DLT_LOOP, for loopback devices; it's like DLT_NULL, except + * that the AF_ type in the link-layer header is in network byte order. + * + * DLT_LOOP is 12 in OpenBSD, but that's DLT_RAW in other OSes, so + * we don't use 12 for it in OSes other than OpenBSD. + */ +#ifdef __OpenBSD__ +#define DLT_LOOP 12 +#else +#define DLT_LOOP 108 +#endif + +/* + * Encapsulated packets for IPsec; DLT_ENC is 13 in OpenBSD, but that's + * DLT_SLIP_BSDOS in NetBSD, so we don't use 13 for it in OSes other + * than OpenBSD. + */ +#ifdef __OpenBSD__ +#define DLT_ENC 13 +#else +#define DLT_ENC 109 +#endif + +/* + * Values between 110 and 112 are reserved for use in capture file headers + * as link-layer types corresponding to DLT_ types that might differ + * between platforms; don't use those values for new DLT_ types + * other than the corresponding DLT_ types. + */ + +/* + * This is for Linux cooked sockets. + */ +#define DLT_LINUX_SLL 113 + +/* + * Apple LocalTalk hardware. + */ +#define DLT_LTALK 114 + +/* + * Acorn Econet. + */ +#define DLT_ECONET 115 + +/* + * Reserved for use with OpenBSD ipfilter. + */ +#define DLT_IPFILTER 116 + +/* + * OpenBSD DLT_PFLOG; DLT_PFLOG is 17 in OpenBSD, but that's DLT_LANE8023 + * in SuSE 6.3, so we can't use 17 for it in capture-file headers. + * + * XXX: is there a conflict with DLT_PFSYNC 18 as well? + */ +#ifdef __OpenBSD__ +#define DLT_OLD_PFLOG 17 +#define DLT_PFSYNC 18 +#endif +#define DLT_PFLOG 117 + +/* + * Registered for Cisco-internal use. + */ +#define DLT_CISCO_IOS 118 + +/* + * For 802.11 cards using the Prism II chips, with a link-layer + * header including Prism monitor mode information plus an 802.11 + * header. + */ +#define DLT_PRISM_HEADER 119 + +/* + * Reserved for Aironet 802.11 cards, with an Aironet link-layer header + * (see Doug Ambrisko's FreeBSD patches). + */ +#define DLT_AIRONET_HEADER 120 + +/* + * Reserved for Siemens HiPath HDLC. + */ +#define DLT_HHDLC 121 + +/* + * This is for RFC 2625 IP-over-Fibre Channel. + * + * This is not for use with raw Fibre Channel, where the link-layer + * header starts with a Fibre Channel frame header; it's for IP-over-FC, + * where the link-layer header starts with an RFC 2625 Network_Header + * field. + */ +#define DLT_IP_OVER_FC 122 + +/* + * This is for Full Frontal ATM on Solaris with SunATM, with a + * pseudo-header followed by an AALn PDU. + * + * There may be other forms of Full Frontal ATM on other OSes, + * with different pseudo-headers. + * + * If ATM software returns a pseudo-header with VPI/VCI information + * (and, ideally, packet type information, e.g. signalling, ILMI, + * LANE, LLC-multiplexed traffic, etc.), it should not use + * DLT_ATM_RFC1483, but should get a new DLT_ value, so tcpdump + * and the like don't have to infer the presence or absence of a + * pseudo-header and the form of the pseudo-header. + */ +#define DLT_SUNATM 123 /* Solaris+SunATM */ + +/* + * Reserved as per request from Kent Dahlgren + * for private use. + */ +#define DLT_RIO 124 /* RapidIO */ +#define DLT_PCI_EXP 125 /* PCI Express */ +#define DLT_AURORA 126 /* Xilinx Aurora link layer */ + +/* + * Header for 802.11 plus a number of bits of link-layer information + * including radio information, used by some recent BSD drivers as + * well as the madwifi Atheros driver for Linux. + */ +#define DLT_IEEE802_11_RADIO 127 /* 802.11 plus radiotap radio header */ + +/* + * Reserved for the TZSP encapsulation, as per request from + * Chris Waters + * TZSP is a generic encapsulation for any other link type, + * which includes a means to include meta-information + * with the packet, e.g. signal strength and channel + * for 802.11 packets. + */ +#define DLT_TZSP 128 /* Tazmen Sniffer Protocol */ + +/* + * BSD's ARCNET headers have the source host, destination host, + * and type at the beginning of the packet; that's what's handed + * up to userland via BPF. + * + * Linux's ARCNET headers, however, have a 2-byte offset field + * between the host IDs and the type; that's what's handed up + * to userland via PF_PACKET sockets. + * + * We therefore have to have separate DLT_ values for them. + */ +#define DLT_ARCNET_LINUX 129 /* ARCNET */ + +/* + * Juniper-private data link types, as per request from + * Hannes Gredler . The DLT_s are used + * for passing on chassis-internal metainformation such as + * QOS profiles, etc.. + */ +#define DLT_JUNIPER_MLPPP 130 +#define DLT_JUNIPER_MLFR 131 +#define DLT_JUNIPER_ES 132 +#define DLT_JUNIPER_GGSN 133 +#define DLT_JUNIPER_MFR 134 +#define DLT_JUNIPER_ATM2 135 +#define DLT_JUNIPER_SERVICES 136 +#define DLT_JUNIPER_ATM1 137 + +/* + * Apple IP-over-IEEE 1394, as per a request from Dieter Siegmund + * . The header that's presented is an Ethernet-like + * header: + * + * #define FIREWIRE_EUI64_LEN 8 + * struct firewire_header { + * u_char firewire_dhost[FIREWIRE_EUI64_LEN]; + * u_char firewire_shost[FIREWIRE_EUI64_LEN]; + * u_short firewire_type; + * }; + * + * with "firewire_type" being an Ethernet type value, rather than, + * for example, raw GASP frames being handed up. + */ +#define DLT_APPLE_IP_OVER_IEEE1394 138 + +/* + * Various SS7 encapsulations, as per a request from Jeff Morriss + * and subsequent discussions. + */ +#define DLT_MTP2_WITH_PHDR 139 /* pseudo-header with various info, followed by MTP2 */ +#define DLT_MTP2 140 /* MTP2, without pseudo-header */ +#define DLT_MTP3 141 /* MTP3, without pseudo-header or MTP2 */ +#define DLT_SCCP 142 /* SCCP, without pseudo-header or MTP2 or MTP3 */ + +/* + * DOCSIS MAC frames. + */ +#define DLT_DOCSIS 143 + +/* + * Linux-IrDA packets. Protocol defined at http://www.irda.org. + * Those packets include IrLAP headers and above (IrLMP...), but + * don't include Phy framing (SOF/EOF/CRC & byte stuffing), because Phy + * framing can be handled by the hardware and depend on the bitrate. + * This is exactly the format you would get capturing on a Linux-IrDA + * interface (irdaX), but not on a raw serial port. + * Note the capture is done in "Linux-cooked" mode, so each packet include + * a fake packet header (struct sll_header). This is because IrDA packet + * decoding is dependant on the direction of the packet (incomming or + * outgoing). + * When/if other platform implement IrDA capture, we may revisit the + * issue and define a real DLT_IRDA... + * Jean II + */ +#define DLT_LINUX_IRDA 144 + +/* + * Reserved for IBM SP switch and IBM Next Federation switch. + */ +#define DLT_IBM_SP 145 +#define DLT_IBM_SN 146 + +/* + * Reserved for private use. If you have some link-layer header type + * that you want to use within your organization, with the capture files + * using that link-layer header type not ever be sent outside your + * organization, you can use these values. + * + * No libpcap release will use these for any purpose, nor will any + * tcpdump release use them, either. + * + * Do *NOT* use these in capture files that you expect anybody not using + * your private versions of capture-file-reading tools to read; in + * particular, do *NOT* use them in products, otherwise you may find that + * people won't be able to use tcpdump, or snort, or Ethereal, or... to + * read capture files from your firewall/intrusion detection/traffic + * monitoring/etc. appliance, or whatever product uses that DLT_ value, + * and you may also find that the developers of those applications will + * not accept patches to let them read those files. + * + * Also, do not use them if somebody might send you a capture using them + * for *their* private type and tools using them for *your* private type + * would have to read them. + * + * Instead, ask "tcpdump-workers@lists.tcpdump.org" for a new DLT_ value, + * as per the comment above, and use the type you're given. + */ +#define DLT_USER0 147 +#define DLT_USER1 148 +#define DLT_USER2 149 +#define DLT_USER3 150 +#define DLT_USER4 151 +#define DLT_USER5 152 +#define DLT_USER6 153 +#define DLT_USER7 154 +#define DLT_USER8 155 +#define DLT_USER9 156 +#define DLT_USER10 157 +#define DLT_USER11 158 +#define DLT_USER12 159 +#define DLT_USER13 160 +#define DLT_USER14 161 +#define DLT_USER15 162 + +/* + * For future use with 802.11 captures - defined by AbsoluteValue + * Systems to store a number of bits of link-layer information + * including radio information: + * + * http://www.shaftnet.org/~pizza/software/capturefrm.txt + * + * but it might be used by some non-AVS drivers now or in the + * future. + */ +#define DLT_IEEE802_11_RADIO_AVS 163 /* 802.11 plus AVS radio header */ + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . The DLT_s are used + * for passing on chassis-internal metainformation such as + * QOS profiles, etc.. + */ +#define DLT_JUNIPER_MONITOR 164 + +/* + * Reserved for BACnet MS/TP. + */ +#define DLT_BACNET_MS_TP 165 + +/* + * Another PPP variant as per request from Karsten Keil . + * + * This is used in some OSes to allow a kernel socket filter to distinguish + * between incoming and outgoing packets, on a socket intended to + * supply pppd with outgoing packets so it can do dial-on-demand and + * hangup-on-lack-of-demand; incoming packets are filtered out so they + * don't cause pppd to hold the connection up (you don't want random + * input packets such as port scans, packets from old lost connections, + * etc. to force the connection to stay up). + * + * The first byte of the PPP header (0xff03) is modified to accomodate + * the direction - 0x00 = IN, 0x01 = OUT. + */ +#define DLT_PPP_PPPD 166 + +/* + * Names for backwards compatibility with older versions of some PPP + * software; new software should use DLT_PPP_PPPD. + */ +#define DLT_PPP_WITH_DIRECTION DLT_PPP_PPPD +#define DLT_LINUX_PPP_WITHDIRECTION DLT_PPP_PPPD + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . The DLT_s are used + * for passing on chassis-internal metainformation such as + * QOS profiles, cookies, etc.. + */ +#define DLT_JUNIPER_PPPOE 167 +#define DLT_JUNIPER_PPPOE_ATM 168 + +#define DLT_GPRS_LLC 169 /* GPRS LLC */ +#define DLT_GPF_T 170 /* GPF-T (ITU-T G.7041/Y.1303) */ +#define DLT_GPF_F 171 /* GPF-F (ITU-T G.7041/Y.1303) */ + +/* + * Requested by Oolan Zimmer for use in Gcom's T1/E1 line + * monitoring equipment. + */ +#define DLT_GCOM_T1E1 172 +#define DLT_GCOM_SERIAL 173 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . The DLT_ is used + * for internal communication to Physical Interface Cards (PIC) + */ +#define DLT_JUNIPER_PIC_PEER 174 + +/* + * Link types requested by Gregor Maier of Endace + * Measurement Systems. They add an ERF header (see + * http://www.endace.com/support/EndaceRecordFormat.pdf) in front of + * the link-layer header. + */ +#define DLT_ERF_ETH 175 /* Ethernet */ +#define DLT_ERF_POS 176 /* Packet-over-SONET */ + +/* + * Requested by Daniele Orlandi for raw LAPD + * for vISDN (http://www.orlandi.com/visdn/). Its link-layer header + * includes additional information before the LAPD header, so it's + * not necessarily a generic LAPD header. + */ +#define DLT_LINUX_LAPD 177 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . + * The DLT_ are used for prepending meta-information + * like interface index, interface name + * before standard Ethernet, PPP, Frelay & C-HDLC Frames + */ +#define DLT_JUNIPER_ETHER 178 +#define DLT_JUNIPER_PPP 179 +#define DLT_JUNIPER_FRELAY 180 +#define DLT_JUNIPER_CHDLC 181 + +/* + * Multi Link Frame Relay (FRF.16) + */ +#define DLT_MFR 182 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . + * The DLT_ is used for internal communication with a + * voice Adapter Card (PIC) + */ +#define DLT_JUNIPER_VP 183 + +/* + * Arinc 429 frames. + * DLT_ requested by Gianluca Varenni . + * Every frame contains a 32bit A429 label. + * More documentation on Arinc 429 can be found at + * http://www.condoreng.com/support/downloads/tutorials/ARINCTutorial.pdf + */ +#define DLT_A429 184 + +/* + * Arinc 653 Interpartition Communication messages. + * DLT_ requested by Gianluca Varenni . + * Please refer to the A653-1 standard for more information. + */ +#define DLT_A653_ICM 185 + +/* + * USB packets, beginning with a USB setup header; requested by + * Paolo Abeni . + */ +#define DLT_USB 186 + +/* + * Bluetooth HCI UART transport layer (part H:4); requested by + * Paolo Abeni. + */ +#define DLT_BLUETOOTH_HCI_H4 187 + +/* + * IEEE 802.16 MAC Common Part Sublayer; requested by Maria Cruz + * . + */ +#define DLT_IEEE802_16_MAC_CPS 188 + +/* + * USB packets, beginning with a Linux USB header; requested by + * Paolo Abeni . + */ +#define DLT_USB_LINUX 189 + +/* + * Controller Area Network (CAN) v. 2.0B packets. + * DLT_ requested by Gianluca Varenni . + * Used to dump CAN packets coming from a CAN Vector board. + * More documentation on the CAN v2.0B frames can be found at + * http://www.can-cia.org/downloads/?269 + */ +#define DLT_CAN20B 190 + +/* + * IEEE 802.15.4, with address fields padded, as is done by Linux + * drivers; requested by Juergen Schimmer. + */ +#define DLT_IEEE802_15_4_LINUX 191 + +/* + * Per Packet Information encapsulated packets. + * DLT_ requested by Gianluca Varenni . + */ +#define DLT_PPI 192 + +/* + * Header for 802.16 MAC Common Part Sublayer plus a radiotap radio header; + * requested by Charles Clancy. + */ +#define DLT_IEEE802_16_MAC_CPS_RADIO 193 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . + * The DLT_ is used for internal communication with a + * integrated service module (ISM). + */ +#define DLT_JUNIPER_ISM 194 + +/* + * IEEE 802.15.4, exactly as it appears in the spec (no padding, no + * nothing); requested by Mikko Saarnivala . + */ +#define DLT_IEEE802_15_4 195 + +/* + * Various link-layer types, with a pseudo-header, for SITA + * (http://www.sita.aero/); requested by Fulko Hew (fulko.hew@gmail.com). + */ +#define DLT_SITA 196 + +/* + * Various link-layer types, with a pseudo-header, for Endace DAG cards; + * encapsulates Endace ERF records. Requested by Stephen Donnelly + * . + */ +#define DLT_ERF 197 + +/* + * Special header prepended to Ethernet packets when capturing from a + * u10 Networks board. Requested by Phil Mulholland + * . + */ +#define DLT_RAIF1 198 + +/* + * IPMB packet for IPMI, beginning with the I2C slave address, followed + * by the netFn and LUN, etc.. Requested by Chanthy Toeung + * . + */ +#define DLT_IPMB 199 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . + * The DLT_ is used for capturing data on a secure tunnel interface. + */ +#define DLT_JUNIPER_ST 200 + +/* + * Bluetooth HCI UART transport layer (part H:4), with pseudo-header + * that includes direction information; requested by Paolo Abeni. + */ +#define DLT_BLUETOOTH_HCI_H4_WITH_PHDR 201 + +/* + * AX.25 packet with a 1-byte KISS header; see + * + * http://www.ax25.net/kiss.htm + * + * as per Richard Stearn . + */ +#define DLT_AX25_KISS 202 + +/* + * LAPD packets from an ISDN channel, starting with the address field, + * with no pseudo-header. + * Requested by Varuna De Silva . + */ +#define DLT_LAPD 203 + +/* + * Variants of various link-layer headers, with a one-byte direction + * pseudo-header prepended - zero means "received by this host", + * non-zero (any non-zero value) means "sent by this host" - as per + * Will Barker . + */ +#define DLT_PPP_WITH_DIR 204 /* PPP - don't confuse with DLT_PPP_WITH_DIRECTION */ +#define DLT_C_HDLC_WITH_DIR 205 /* Cisco HDLC */ +#define DLT_FRELAY_WITH_DIR 206 /* Frame Relay */ +#define DLT_LAPB_WITH_DIR 207 /* LAPB */ + +/* + * 208 is reserved for an as-yet-unspecified proprietary link-layer + * type, as requested by Will Barker. + */ + +/* + * IPMB with a Linux-specific pseudo-header; as requested by Alexey Neyman + * . + */ +#define DLT_IPMB_LINUX 209 + +/* + * FlexRay automotive bus - http://www.flexray.com/ - as requested + * by Hannes Kaelber . + */ +#define DLT_FLEXRAY 210 + +/* + * Media Oriented Systems Transport (MOST) bus for multimedia + * transport - http://www.mostcooperation.com/ - as requested + * by Hannes Kaelber . + */ +#define DLT_MOST 211 + +/* + * Local Interconnect Network (LIN) bus for vehicle networks - + * http://www.lin-subbus.org/ - as requested by Hannes Kaelber + * . + */ +#define DLT_LIN 212 + +/* + * X2E-private data link type used for serial line capture, + * as requested by Hannes Kaelber . + */ +#define DLT_X2E_SERIAL 213 + +/* + * X2E-private data link type used for the Xoraya data logger + * family, as requested by Hannes Kaelber . + */ +#define DLT_X2E_XORAYA 214 + +/* + * IEEE 802.15.4, exactly as it appears in the spec (no padding, no + * nothing), but with the PHY-level data for non-ASK PHYs (4 octets + * of 0 as preamble, one octet of SFD, one octet of frame length+ + * reserved bit, and then the MAC-layer data, starting with the + * frame control field). + * + * Requested by Max Filippov . + */ +#define DLT_IEEE802_15_4_NONASK_PHY 215 + + +/* + * DLT and savefile link type values are split into a class and + * a member of that class. A class value of 0 indicates a regular + * DLT_/LINKTYPE_ value. + */ +#define DLT_CLASS(x) ((x) & 0x03ff0000) + +/* + * NetBSD-specific generic "raw" link type. The class value indicates + * that this is the generic raw type, and the lower 16 bits are the + * address family we're dealing with. Those values are NetBSD-specific; + * do not assume that they correspond to AF_ values for your operating + * system. + */ +#define DLT_CLASS_NETBSD_RAWAF 0x02240000 +#define DLT_NETBSD_RAWAF(af) (DLT_CLASS_NETBSD_RAWAF | (af)) +#define DLT_NETBSD_RAWAF_AF(x) ((x) & 0x0000ffff) +#define DLT_IS_NETBSD_RAWAF(x) (DLT_CLASS(x) == DLT_CLASS_NETBSD_RAWAF) + + +/* + * The instruction encodings. + */ +/* instruction classes */ +#define BPF_CLASS(code) ((code) & 0x07) +#define BPF_LD 0x00 +#define BPF_LDX 0x01 +#define BPF_ST 0x02 +#define BPF_STX 0x03 +#define BPF_ALU 0x04 +#define BPF_JMP 0x05 +#define BPF_RET 0x06 +#define BPF_MISC 0x07 + +/* ld/ldx fields */ +#define BPF_SIZE(code) ((code) & 0x18) +#define BPF_W 0x00 +#define BPF_H 0x08 +#define BPF_B 0x10 +#define BPF_MODE(code) ((code) & 0xe0) +#define BPF_IMM 0x00 +#define BPF_ABS 0x20 +#define BPF_IND 0x40 +#define BPF_MEM 0x60 +#define BPF_LEN 0x80 +#define BPF_MSH 0xa0 + +/* alu/jmp fields */ +#define BPF_OP(code) ((code) & 0xf0) +#define BPF_ADD 0x00 +#define BPF_SUB 0x10 +#define BPF_MUL 0x20 +#define BPF_DIV 0x30 +#define BPF_OR 0x40 +#define BPF_AND 0x50 +#define BPF_LSH 0x60 +#define BPF_RSH 0x70 +#define BPF_NEG 0x80 +#define BPF_JA 0x00 +#define BPF_JEQ 0x10 +#define BPF_JGT 0x20 +#define BPF_JGE 0x30 +#define BPF_JSET 0x40 +#define BPF_SRC(code) ((code) & 0x08) +#define BPF_K 0x00 +#define BPF_X 0x08 + +/* ret - BPF_K and BPF_X also apply */ +#define BPF_RVAL(code) ((code) & 0x18) +#define BPF_A 0x10 + +/* misc */ +#define BPF_MISCOP(code) ((code) & 0xf8) +#define BPF_TAX 0x00 +#define BPF_TXA 0x80 + +/* + * The instruction data structure. + */ +struct bpf_insn { + u_short code; + u_char jt; + u_char jf; + bpf_u_int32 k; +}; + +/* + * Macros for insn array initializers. + */ +#define BPF_STMT(code, k) { (u_short)(code), 0, 0, k } +#define BPF_JUMP(code, k, jt, jf) { (u_short)(code), jt, jf, k } + +#if __STDC__ || defined(__cplusplus) +extern int bpf_validate(const struct bpf_insn *, int); +extern u_int bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int); +#else +extern int bpf_validate(); +extern u_int bpf_filter(); +#endif + +/* + * Number of scratch memory words (for BPF_LD|BPF_MEM and BPF_ST). + */ +#define BPF_MEMWORDS 16 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/namedb.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/namedb.h new file mode 100644 index 0000000..9002c75 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/namedb.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 1994, 1996 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. + * 4. Neither the name of the University nor of the Laboratory may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/namedb.h,v 1.1 2006/10/04 18:09:22 guy Exp $ (LBL) + */ + +#ifndef lib_pcap_namedb_h +#define lib_pcap_namedb_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * As returned by the pcap_next_etherent() + * XXX this stuff doesn't belong in this interface, but this + * library already must do name to address translation, so + * on systems that don't have support for /etc/ethers, we + * export these hooks since they'll + */ +struct pcap_etherent { + u_char addr[6]; + char name[122]; +}; +#ifndef PCAP_ETHERS_FILE +#define PCAP_ETHERS_FILE "/etc/ethers" +#endif +struct pcap_etherent *pcap_next_etherent(FILE *); +u_char *pcap_ether_hostton(const char*); +u_char *pcap_ether_aton(const char *); + +bpf_u_int32 **pcap_nametoaddr(const char *); +#ifdef INET6 +struct addrinfo *pcap_nametoaddrinfo(const char *); +#endif +bpf_u_int32 pcap_nametonetaddr(const char *); + +int pcap_nametoport(const char *, int *, int *); +int pcap_nametoportrange(const char *, int *, int *, int *); +int pcap_nametoproto(const char *); +int pcap_nametoeproto(const char *); +int pcap_nametollc(const char *); +/* + * If a protocol is unknown, PROTO_UNDEF is returned. + * Also, pcap_nametoport() returns the protocol along with the port number. + * If there are ambiguous entried in /etc/services (i.e. domain + * can be either tcp or udp) PROTO_UNDEF is returned. + */ +#define PROTO_UNDEF -1 + +/* XXX move these to pcap-int.h? */ +int __pcap_atodn(const char *, bpf_u_int32 *); +int __pcap_atoin(const char *, bpf_u_int32 *); +u_short __pcap_nametodnaddr(const char *); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/sll.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/sll.h new file mode 100644 index 0000000..e9d5452 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/sll.h @@ -0,0 +1,129 @@ +/*- + * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from the Stanford/CMU enet packet filter, + * (net/enet.c) distributed as part of 4.3BSD, and code contributed + * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence + * Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/sll.h,v 1.2.2.1 2008-05-30 01:36:06 guy Exp $ (LBL) + */ + +/* + * For captures on Linux cooked sockets, we construct a fake header + * that includes: + * + * a 2-byte "packet type" which is one of: + * + * LINUX_SLL_HOST packet was sent to us + * LINUX_SLL_BROADCAST packet was broadcast + * LINUX_SLL_MULTICAST packet was multicast + * LINUX_SLL_OTHERHOST packet was sent to somebody else + * LINUX_SLL_OUTGOING packet was sent *by* us; + * + * a 2-byte Ethernet protocol field; + * + * a 2-byte link-layer type; + * + * a 2-byte link-layer address length; + * + * an 8-byte source link-layer address, whose actual length is + * specified by the previous value. + * + * All fields except for the link-layer address are in network byte order. + * + * DO NOT change the layout of this structure, or change any of the + * LINUX_SLL_ values below. If you must change the link-layer header + * for a "cooked" Linux capture, introduce a new DLT_ type (ask + * "tcpdump-workers@lists.tcpdump.org" for one, so that you don't give it + * a value that collides with a value already being used), and use the + * new header in captures of that type, so that programs that can + * handle DLT_LINUX_SLL captures will continue to handle them correctly + * without any change, and so that capture files with different headers + * can be told apart and programs that read them can dissect the + * packets in them. + */ + +#ifndef lib_pcap_sll_h +#define lib_pcap_sll_h + +/* + * A DLT_LINUX_SLL fake link-layer header. + */ +#define SLL_HDR_LEN 16 /* total header length */ +#define SLL_ADDRLEN 8 /* length of address field */ + +struct sll_header { + u_int16_t sll_pkttype; /* packet type */ + u_int16_t sll_hatype; /* link-layer address type */ + u_int16_t sll_halen; /* link-layer address length */ + u_int8_t sll_addr[SLL_ADDRLEN]; /* link-layer address */ + u_int16_t sll_protocol; /* protocol */ +}; + +/* + * The LINUX_SLL_ values for "sll_pkttype"; these correspond to the + * PACKET_ values on Linux, but are defined here so that they're + * available even on systems other than Linux, and so that they + * don't change even if the PACKET_ values change. + */ +#define LINUX_SLL_HOST 0 +#define LINUX_SLL_BROADCAST 1 +#define LINUX_SLL_MULTICAST 2 +#define LINUX_SLL_OTHERHOST 3 +#define LINUX_SLL_OUTGOING 4 + +/* + * The LINUX_SLL_ values for "sll_protocol"; these correspond to the + * ETH_P_ values on Linux, but are defined here so that they're + * available even on systems other than Linux. We assume, for now, + * that the ETH_P_ values won't change in Linux; if they do, then: + * + * if we don't translate them in "pcap-linux.c", capture files + * won't necessarily be readable if captured on a system that + * defines ETH_P_ values that don't match these values; + * + * if we do translate them in "pcap-linux.c", that makes life + * unpleasant for the BPF code generator, as the values you test + * for in the kernel aren't the values that you test for when + * reading a capture file, so the fixup code run on BPF programs + * handed to the kernel ends up having to do more work. + * + * Add other values here as necessary, for handling packet types that + * might show up on non-Ethernet, non-802.x networks. (Not all the ones + * in the Linux "if_ether.h" will, I suspect, actually show up in + * captures.) + */ +#define LINUX_SLL_P_802_3 0x0001 /* Novell 802.3 frames without 802.2 LLC header */ +#define LINUX_SLL_P_802_2 0x0004 /* 802.2 frames (not D/I/X Ethernet) */ + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/usb.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/usb.h new file mode 100644 index 0000000..adcd19c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/usb.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006 Paolo Abeni (Italy) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Basic USB data struct + * By Paolo Abeni + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/usb.h,v 1.6 2007/09/22 02:06:08 guy Exp $ + */ + +#ifndef _PCAP_USB_STRUCTS_H__ +#define _PCAP_USB_STRUCTS_H__ + +/* + * possible transfer mode + */ +#define URB_TRANSFER_IN 0x80 +#define URB_ISOCHRONOUS 0x0 +#define URB_INTERRUPT 0x1 +#define URB_CONTROL 0x2 +#define URB_BULK 0x3 + +/* + * possible event type + */ +#define URB_SUBMIT 'S' +#define URB_COMPLETE 'C' +#define URB_ERROR 'E' + +/* + * USB setup header as defined in USB specification. + * Appears at the front of each packet in DLT_USB captures. + */ +typedef struct _usb_setup { + u_int8_t bmRequestType; + u_int8_t bRequest; + u_int16_t wValue; + u_int16_t wIndex; + u_int16_t wLength; +} pcap_usb_setup; + + +/* + * Header prepended by linux kernel to each event. + * Appears at the front of each packet in DLT_USB_LINUX captures. + */ +typedef struct _usb_header { + u_int64_t id; + u_int8_t event_type; + u_int8_t transfer_type; + u_int8_t endpoint_number; + u_int8_t device_address; + u_int16_t bus_id; + char setup_flag;/*if !=0 the urb setup header is not present*/ + char data_flag; /*if !=0 no urb data is present*/ + int64_t ts_sec; + int32_t ts_usec; + int32_t status; + u_int32_t urb_len; + u_int32_t data_len; /* amount of urb data really present in this event*/ + pcap_usb_setup setup; +} pcap_usb_header; + + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/vlan.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/vlan.h new file mode 100644 index 0000000..b0cb794 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/vlan.h @@ -0,0 +1,46 @@ +/*- + * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/vlan.h,v 1.1.2.2 2008-08-06 07:45:59 guy Exp $ + */ + +#ifndef lib_pcap_vlan_h +#define lib_pcap_vlan_h + +struct vlan_tag { + u_int16_t vlan_tpid; /* ETH_P_8021Q */ + u_int16_t vlan_tci; /* VLAN TCI */ +}; + +#define VLAN_TAG_LEN 4 + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/remote-ext.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/remote-ext.h new file mode 100644 index 0000000..9f54d69 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/remote-ext.h @@ -0,0 +1,444 @@ +/* + * Copyright (c) 2002 - 2003 + * NetGroup, Politecnico di Torino (Italy) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Politecnico di Torino nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __REMOTE_EXT_H__ +#define __REMOTE_EXT_H__ + + +#ifndef HAVE_REMOTE +#error Please do not include this file directly. Just define HAVE_REMOTE and then include pcap.h +#endif + +// Definition for Microsoft Visual Studio +#if _MSC_VER > 1000 +#pragma once +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \file remote-ext.h + + The goal of this file it to include most of the new definitions that should be + placed into the pcap.h file. + + It includes all new definitions (structures and functions like pcap_open(). + Some of the functions are not really a remote feature, but, right now, + they are placed here. +*/ + + + +// All this stuff is public +/*! \addtogroup remote_struct + \{ +*/ + + + + +/*! + \brief Defines the maximum buffer size in which address, port, interface names are kept. + + In case the adapter name or such is larger than this value, it is truncated. + This is not used by the user; however it must be aware that an hostname / interface + name longer than this value will be truncated. +*/ +#define PCAP_BUF_SIZE 1024 + + +/*! \addtogroup remote_source_ID + \{ +*/ + + +/*! + \brief Internal representation of the type of source in use (file, + remote/local interface). + + This indicates a file, i.e. the user want to open a capture from a local file. +*/ +#define PCAP_SRC_FILE 2 +/*! + \brief Internal representation of the type of source in use (file, + remote/local interface). + + This indicates a local interface, i.e. the user want to open a capture from + a local interface. This does not involve the RPCAP protocol. +*/ +#define PCAP_SRC_IFLOCAL 3 +/*! + \brief Internal representation of the type of source in use (file, + remote/local interface). + + This indicates a remote interface, i.e. the user want to open a capture from + an interface on a remote host. This does involve the RPCAP protocol. +*/ +#define PCAP_SRC_IFREMOTE 4 + +/*! + \} +*/ + + + +/*! \addtogroup remote_source_string + + The formats allowed by the pcap_open() are the following: + - file://path_and_filename [opens a local file] + - rpcap://devicename [opens the selected device devices available on the local host, without using the RPCAP protocol] + - rpcap://host/devicename [opens the selected device available on a remote host] + - rpcap://host:port/devicename [opens the selected device available on a remote host, using a non-standard port for RPCAP] + - adaptername [to open a local adapter; kept for compability, but it is strongly discouraged] + - (NULL) [to open the first local adapter; kept for compability, but it is strongly discouraged] + + The formats allowed by the pcap_findalldevs_ex() are the following: + - file://folder/ [lists all the files in the given folder] + - rpcap:// [lists all local adapters] + - rpcap://host:port/ [lists the devices available on a remote host] + + Referring to the 'host' and 'port' paramters, they can be either numeric or literal. Since + IPv6 is fully supported, these are the allowed formats: + + - host (literal): e.g. host.foo.bar + - host (numeric IPv4): e.g. 10.11.12.13 + - host (numeric IPv4, IPv6 style): e.g. [10.11.12.13] + - host (numeric IPv6): e.g. [1:2:3::4] + - port: can be either numeric (e.g. '80') or literal (e.g. 'http') + + Here you find some allowed examples: + - rpcap://host.foo.bar/devicename [everything literal, no port number] + - rpcap://host.foo.bar:1234/devicename [everything literal, with port number] + - rpcap://10.11.12.13/devicename [IPv4 numeric, no port number] + - rpcap://10.11.12.13:1234/devicename [IPv4 numeric, with port number] + - rpcap://[10.11.12.13]:1234/devicename [IPv4 numeric with IPv6 format, with port number] + - rpcap://[1:2:3::4]/devicename [IPv6 numeric, no port number] + - rpcap://[1:2:3::4]:1234/devicename [IPv6 numeric, with port number] + - rpcap://[1:2:3::4]:http/devicename [IPv6 numeric, with literal port number] + + \{ +*/ + + +/*! + \brief String that will be used to determine the type of source in use (file, + remote/local interface). + + This string will be prepended to the interface name in order to create a string + that contains all the information required to open the source. + + This string indicates that the user wants to open a capture from a local file. +*/ +#define PCAP_SRC_FILE_STRING "file://" +/*! + \brief String that will be used to determine the type of source in use (file, + remote/local interface). + + This string will be prepended to the interface name in order to create a string + that contains all the information required to open the source. + + This string indicates that the user wants to open a capture from a network interface. + This string does not necessarily involve the use of the RPCAP protocol. If the + interface required resides on the local host, the RPCAP protocol is not involved + and the local functions are used. +*/ +#define PCAP_SRC_IF_STRING "rpcap://" + +/*! + \} +*/ + + + + + +/*! + \addtogroup remote_open_flags + \{ +*/ + +/*! + \brief Defines if the adapter has to go in promiscuous mode. + + It is '1' if you have to open the adapter in promiscuous mode, '0' otherwise. + Note that even if this parameter is false, the interface could well be in promiscuous + mode for some other reason (for example because another capture process with + promiscuous mode enabled is currently using that interface). + On on Linux systems with 2.2 or later kernels (that have the "any" device), this + flag does not work on the "any" device; if an argument of "any" is supplied, + the 'promisc' flag is ignored. +*/ +#define PCAP_OPENFLAG_PROMISCUOUS 1 + +/*! + \brief Defines if the data trasfer (in case of a remote + capture) has to be done with UDP protocol. + + If it is '1' if you want a UDP data connection, '0' if you want + a TCP data connection; control connection is always TCP-based. + A UDP connection is much lighter, but it does not guarantee that all + the captured packets arrive to the client workstation. Moreover, + it could be harmful in case of network congestion. + This flag is meaningless if the source is not a remote interface. + In that case, it is simply ignored. +*/ +#define PCAP_OPENFLAG_DATATX_UDP 2 + + +/*! + \brief Defines if the remote probe will capture its own generated traffic. + + In case the remote probe uses the same interface to capture traffic and to send + data back to the caller, the captured traffic includes the RPCAP traffic as well. + If this flag is turned on, the RPCAP traffic is excluded from the capture, so that + the trace returned back to the collector is does not include this traffic. +*/ +#define PCAP_OPENFLAG_NOCAPTURE_RPCAP 4 + +/*! + \brief Defines if the local adapter will capture its own generated traffic. + + This flag tells the underlying capture driver to drop the packets that were sent by itself. + This is usefult when building applications like bridges, that should ignore the traffic + they just sent. +*/ +#define PCAP_OPENFLAG_NOCAPTURE_LOCAL 8 + +/*! + \brief This flag configures the adapter for maximum responsiveness. + + In presence of a large value for nbytes, WinPcap waits for the arrival of several packets before + copying the data to the user. This guarantees a low number of system calls, i.e. lower processor usage, + i.e. better performance, which is good for applications like sniffers. If the user sets the + PCAP_OPENFLAG_MAX_RESPONSIVENESS flag, the capture driver will copy the packets as soon as the application + is ready to receive them. This is suggested for real time applications (like, for example, a bridge) + that need the best responsiveness.*/ +#define PCAP_OPENFLAG_MAX_RESPONSIVENESS 16 + +/*! + \} +*/ + + +/*! + \addtogroup remote_samp_methods + \{ +*/ + +/*! + \brief No sampling has to be done on the current capture. + + In this case, no sampling algorithms are applied to the current capture. +*/ +#define PCAP_SAMP_NOSAMP 0 + +/*! + \brief It defines that only 1 out of N packets must be returned to the user. + + In this case, the 'value' field of the 'pcap_samp' structure indicates the + number of packets (minus 1) that must be discarded before one packet got accepted. + In other words, if 'value = 10', the first packet is returned to the caller, while + the following 9 are discarded. +*/ +#define PCAP_SAMP_1_EVERY_N 1 + +/*! + \brief It defines that we have to return 1 packet every N milliseconds. + + In this case, the 'value' field of the 'pcap_samp' structure indicates the 'waiting + time' in milliseconds before one packet got accepted. + In other words, if 'value = 10', the first packet is returned to the caller; the next + returned one will be the first packet that arrives when 10ms have elapsed. +*/ +#define PCAP_SAMP_FIRST_AFTER_N_MS 2 + +/*! + \} +*/ + + +/*! + \addtogroup remote_auth_methods + \{ +*/ + +/*! + \brief It defines the NULL authentication. + + This value has to be used within the 'type' member of the pcap_rmtauth structure. + The 'NULL' authentication has to be equal to 'zero', so that old applications + can just put every field of struct pcap_rmtauth to zero, and it does work. +*/ +#define RPCAP_RMTAUTH_NULL 0 +/*! + \brief It defines the username/password authentication. + + With this type of authentication, the RPCAP protocol will use the username/ + password provided to authenticate the user on the remote machine. If the + authentication is successful (and the user has the right to open network devices) + the RPCAP connection will continue; otherwise it will be dropped. + + This value has to be used within the 'type' member of the pcap_rmtauth structure. +*/ +#define RPCAP_RMTAUTH_PWD 1 + +/*! + \} +*/ + + + + +/*! + + \brief This structure keeps the information needed to autheticate + the user on a remote machine. + + The remote machine can either grant or refuse the access according + to the information provided. + In case the NULL authentication is required, both 'username' and + 'password' can be NULL pointers. + + This structure is meaningless if the source is not a remote interface; + in that case, the functions which requires such a structure can accept + a NULL pointer as well. +*/ +struct pcap_rmtauth +{ + /*! + \brief Type of the authentication required. + + In order to provide maximum flexibility, we can support different types + of authentication based on the value of this 'type' variable. The currently + supported authentication methods are defined into the + \link remote_auth_methods Remote Authentication Methods Section\endlink. + + */ + int type; + /*! + \brief Zero-terminated string containing the username that has to be + used on the remote machine for authentication. + + This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication + and it can be NULL. + */ + char *username; + /*! + \brief Zero-terminated string containing the password that has to be + used on the remote machine for authentication. + + This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication + and it can be NULL. + */ + char *password; +}; + + +/*! + \brief This structure defines the information related to sampling. + + In case the sampling is requested, the capturing device should read + only a subset of the packets coming from the source. The returned packets depend + on the sampling parameters. + + \warning The sampling process is applied after the filtering process. + In other words, packets are filtered first, then the sampling process selects a + subset of the 'filtered' packets and it returns them to the caller. +*/ +struct pcap_samp +{ + /*! + Method used for sampling. Currently, the supported methods are listed in the + \link remote_samp_methods Sampling Methods Section\endlink. + */ + int method; + + /*! + This value depends on the sampling method defined. For its meaning, please check + at the \link remote_samp_methods Sampling Methods Section\endlink. + */ + int value; +}; + + + + +//! Maximum lenght of an host name (needed for the RPCAP active mode) +#define RPCAP_HOSTLIST_SIZE 1024 + + +/*! + \} +*/ // end of public documentation + + +// Exported functions + + + +/** \name New WinPcap functions + + This section lists the new functions that are able to help considerably in writing + WinPcap programs because of their easiness of use. + */ +//\{ +pcap_t *pcap_open(const char *source, int snaplen, int flags, int read_timeout, struct pcap_rmtauth *auth, char *errbuf); +int pcap_createsrcstr(char *source, int type, const char *host, const char *port, const char *name, char *errbuf); +int pcap_parsesrcstr(const char *source, int *type, char *host, char *port, char *name, char *errbuf); +int pcap_findalldevs_ex(char *source, struct pcap_rmtauth *auth, pcap_if_t **alldevs, char *errbuf); +struct pcap_samp *pcap_setsampling(pcap_t *p); + +//\} +// End of new winpcap functions + + + +/** \name Remote Capture functions + */ +//\{ +SOCKET pcap_remoteact_accept(const char *address, const char *port, const char *hostlist, char *connectinghost, struct pcap_rmtauth *auth, char *errbuf); +int pcap_remoteact_list(char *hostlist, char sep, int size, char *errbuf); +int pcap_remoteact_close(const char *host, char *errbuf); +void pcap_remoteact_cleanup(); +//\} +// End of remote capture functions + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/wpcap.lib b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/wpcap.lib new file mode 100644 index 0000000..f832e04 Binary files /dev/null and b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/wpcap.lib differ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c new file mode 100644 index 0000000..f2d05e1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c @@ -0,0 +1,614 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* WinPCap includes. */ +#define HAVE_REMOTE +#include "pcap.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* lwIP includes. */ +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include +#include +#include "netif/etharp.h" + +/* Define those to better describe your network interface. */ +#define IFNAME0 'w' +#define IFNAME1 'p' + +#define netifMAX_MTU 1500 + +struct xEthernetIf +{ + struct eth_addr *ethaddr; + /* Add whatever per-interface state that is needed here. */ +}; + +/* + * Place received packet in a pbuf and send a message to the tcpip task to let + * it know new data has arrived. + */ +static void prvEthernetInput( const unsigned char * const pucInputData, long lInputLength ); + +/* + * Copy the received data into a pbuf. + */ +static struct pbuf *prvLowLevelInput( const unsigned char * const pucInputData, long lDataLength ); + +/* + * Send data from a pbuf to the hardware. + */ +static err_t prvLowLevelOutput( struct netif *pxNetIf, struct pbuf *p ); + +/* + * Perform any hardware and/or driver initialisation necessary. + */ +static void prvLowLevelInit( struct netif *pxNetIf ); + +/* + * Query the computer the simulation is being executed on to find the network + * interfaces it has installed. + */ +static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ); + +/* + * Open the network interface. The number of the interface to be opened is set + * by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. + */ +static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ); + +/* + * Interrupts cannot truely be simulated using WinPCap. In reality this task + * just polls the interface. + */ +static void prvInterruptSimulator( void *pvParameters ); + +/* + * Configure the capture filter to allow blocking reads, and to filter out + * packets that are not of interest to this demo. + */ +static void prvConfigureCaptureBehaviour( void ); + +/*-----------------------------------------------------------*/ + +/* The WinPCap interface being used. */ +static pcap_t *pxOpenedInterfaceHandle = NULL; + +/* Parameter required for WinPCap API functions. */ +static char cErrorBuffer[ PCAP_ERRBUF_SIZE ]; + +/* The network interface that was opened. */ +static struct netif *pxlwIPNetIf = NULL; + +/*-----------------------------------------------------------*/ + +/** + * In this function, the hardware should be initialized. + * Called from ethernetif_init(). + * + * @param pxNetIf the already initialized lwip network interface structure + * for this ethernetif. + */ +static void prvLowLevelInit( struct netif *pxNetIf ) +{ +pcap_if_t *pxAllNetworkInterfaces; + + /* set MAC hardware address length */ + pxNetIf->hwaddr_len = ETHARP_HWADDR_LEN; + + /* set MAC hardware address */ + pxNetIf->hwaddr[ 0 ] = configMAC_ADDR0; + pxNetIf->hwaddr[ 1 ] = configMAC_ADDR1; + pxNetIf->hwaddr[ 2 ] = configMAC_ADDR2; + pxNetIf->hwaddr[ 3 ] = configMAC_ADDR3; + pxNetIf->hwaddr[ 4 ] = configMAC_ADDR4; + pxNetIf->hwaddr[ 5 ] = configMAC_ADDR5; + + /* device capabilities */ + /* don't set pxNetIf_FLAG_ETHARP if this device is not an ethernet one */ + pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + + /* Query the computer the simulation is being executed on to find the + network interfaces it has installed. */ + pxAllNetworkInterfaces = prvPrintAvailableNetworkInterfaces(); + + /* Open the network interface. The number of the interface to be opened is + set by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. + Calling this function will set the pxOpenedInterfaceHandle variable. If, + after calling this function, pxOpenedInterfaceHandle is equal to NULL, then + the interface could not be opened. */ + if( pxAllNetworkInterfaces != NULL ) + { + prvOpenSelectedNetworkInterface( pxAllNetworkInterfaces ); + } + + /* Remember which interface was opened as it is used in the interrupt + simulator task. */ + pxlwIPNetIf = pxNetIf; +} + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + * @param pxNetIf the lwip network interface structure for this ethernetif + * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) + * @return ERR_OK if the packet could be sent + * an err_t value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become available since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ + +static err_t prvLowLevelOutput( struct netif *pxNetIf, struct pbuf *p ) +{ + + /* This is taken from lwIP example code and therefore does not conform + to the FreeRTOS coding standard. */ + +struct pbuf *q; +static unsigned char ucBuffer[ 1520 ]; +unsigned char *pucBuffer = ucBuffer; +unsigned char *pucChar; +struct eth_hdr *pxHeader; +u16_t usTotalLength = p->tot_len - ETH_PAD_SIZE; +err_t xReturn = ERR_OK; + + ( void ) pxNetIf; + + #if defined(LWIP_DEBUG) && LWIP_NETIF_TX_SINGLE_PBUF + LWIP_ASSERT("p->next == NULL && p->len == p->tot_len", p->next == NULL && p->len == p->tot_len); + #endif + + /* Initiate transfer. */ + if( p->len == p->tot_len ) + { + /* No pbuf chain, don't have to copy -> faster. */ + pucBuffer = &( ( unsigned char * ) p->payload )[ ETH_PAD_SIZE ]; + } + else + { + /* pbuf chain, copy into contiguous ucBuffer. */ + if( p->tot_len >= sizeof( ucBuffer ) ) + { + LINK_STATS_INC( link.lenerr ); + LINK_STATS_INC( link.drop ); + snmp_inc_ifoutdiscards( pxNetIf ); + xReturn = ERR_BUF; + } + else + { + pucChar = ucBuffer; + + for( q = p; q != NULL; q = q->next ) + { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + /* send data from(q->payload, q->len); */ + LWIP_DEBUGF( NETIF_DEBUG, ("NETIF: send pucChar %p q->payload %p q->len %i q->next %p\n", pucChar, q->payload, ( int ) q->len, ( void* ) q->next ) ); + if( q == p ) + { + memcpy( pucChar, &( ( char * ) q->payload )[ ETH_PAD_SIZE ], q->len - ETH_PAD_SIZE ); + pucChar += q->len - ETH_PAD_SIZE; + } + else + { + memcpy( pucChar, q->payload, q->len ); + pucChar += q->len; + } + } + } + } + + if( xReturn == ERR_OK ) + { + /* signal that packet should be sent */ + if( pcap_sendpacket( pxOpenedInterfaceHandle, pucBuffer, usTotalLength ) < 0 ) + { + LINK_STATS_INC( link.memerr ); + LINK_STATS_INC( link.drop ); + snmp_inc_ifoutdiscards( pxNetIf ); + xReturn = ERR_BUF; + } + else + { + LINK_STATS_INC( link.xmit ); + snmp_add_ifoutoctets( pxNetIf, usTotalLength ); + pxHeader = ( struct eth_hdr * )p->payload; + + if( ( pxHeader->dest.addr[ 0 ] & 1 ) != 0 ) + { + /* broadcast or multicast packet*/ + snmp_inc_ifoutnucastpkts( pxNetIf ); + } + else + { + /* unicast packet */ + snmp_inc_ifoutucastpkts( pxNetIf ); + } + } + } + + return xReturn; +} + +/** + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + * @param pxNetIf the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +static struct pbuf *prvLowLevelInput( const unsigned char * const pucInputData, long lDataLength ) +{ +struct pbuf *p = NULL, *q; + + if( lDataLength > 0 ) + { + #if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ + #endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc( PBUF_RAW, lDataLength, PBUF_POOL ); + + if( p != NULL ) + { + #if ETH_PAD_SIZE + pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */ + #endif + + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + lDataLength = 0; + for( q = p; q != NULL; q = q->next ) + { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. + * This does not necessarily have to be a memcpy, you can also preallocate + * pbufs for a DMA-enabled MAC and after receiving truncate it to the + * actually received size. In this case, ensure the usTotalLength member of the + * pbuf is the sum of the chained pbuf len members. + */ + memcpy( q->payload, &( pucInputData[ lDataLength ] ), q->len ); + lDataLength += q->len; + } + + #if ETH_PAD_SIZE + pbuf_header( p, ETH_PAD_SIZE ); /* reclaim the padding word */ + #endif + + LINK_STATS_INC( link.recv ); + } + } + + return p; +} + +/** + * This function should be called when a packet is ready to be read + * from the interface. It uses the function prvLowLevelInput() that + * should handle the actual reception of bytes from the network + * interface. Then the type of the received packet is determined and + * the appropriate input function is called. + * + * @param pxNetIf the lwip network interface structure for this ethernetif + */ +static void prvEthernetInput( const unsigned char * const pucInputData, long lInputLength ) +{ + /* This is taken from lwIP example code and therefore does not conform + to the FreeRTOS coding standard. */ + +struct eth_hdr *pxHeader; +struct pbuf *p; + + /* move received packet into a new pbuf */ + p = prvLowLevelInput( pucInputData, lInputLength ); + + /* no packet could be read, silently ignore this */ + if( p != NULL ) + { + /* points to packet payload, which starts with an Ethernet header */ + pxHeader = p->payload; + + switch( htons( pxHeader->type ) ) + { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: + /* full packet send to tcpip_thread to process */ + if( pxlwIPNetIf->input( p, pxlwIPNetIf ) != ERR_OK ) + { + LWIP_DEBUGF(NETIF_DEBUG, ( "ethernetif_input: IP input error\n" ) ); + pbuf_free(p); + p = NULL; + } + break; + + default: + pbuf_free( p ); + p = NULL; + break; + } + } +} + +/** + * Should be called at the beginning of the program to set up the + * network interface. It calls the function prvLowLevelInit() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netif_add(). + * + * @param pxNetIf the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t ethernetif_init( struct netif *pxNetIf ) +{ +err_t xReturn = ERR_OK; + + /* This is taken from lwIP example code and therefore does not conform + to the FreeRTOS coding standard. */ + +struct xEthernetIf *pxEthernetIf; + + LWIP_ASSERT( "pxNetIf != NULL", ( pxNetIf != NULL ) ); + + pxEthernetIf = mem_malloc( sizeof( struct xEthernetIf ) ); + if( pxEthernetIf == NULL ) + { + LWIP_DEBUGF(NETIF_DEBUG, ( "ethernetif_init: out of memory\n" ) ); + xReturn = ERR_MEM; + } + else + { + #if LWIP_NETIF_HOSTNAME + { + /* Initialize interface hostname */ + pxNetIf->hostname = "lwip"; + } + #endif /* LWIP_NETIF_HOSTNAME */ + + pxNetIf->state = pxEthernetIf; + pxNetIf->name[ 0 ] = IFNAME0; + pxNetIf->name[ 1 ] = IFNAME1; + + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ + pxNetIf->output = etharp_output; + pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_IGMP; + pxNetIf->hwaddr_len = ETHARP_HWADDR_LEN; + pxNetIf->mtu = netifMAX_MTU; + pxNetIf->linkoutput = prvLowLevelOutput; + + pxEthernetIf->ethaddr = ( struct eth_addr * ) &( pxNetIf->hwaddr[ 0 ] ); + + /* initialize the hardware */ + prvLowLevelInit( pxNetIf ); + + /* Was an interface opened? */ + if( pxOpenedInterfaceHandle == NULL ) + { + /* Probably an invalid adapter number was defined in + FreeRTOSConfig.h. */ + xReturn = ERR_VAL; + configASSERT( pxOpenedInterfaceHandle ); + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ) +{ +pcap_if_t * pxAllNetworkInterfaces = NULL, *xInterface; +long lInterfaceNumber = 1; + + if( pcap_findalldevs_ex( PCAP_SRC_IF_STRING, NULL, &pxAllNetworkInterfaces, cErrorBuffer ) == -1 ) + { + printf( "\r\nCould not obtain a list of network interfaces\r\n%s\r\n", cErrorBuffer ); + pxAllNetworkInterfaces = NULL; + } + + if( pxAllNetworkInterfaces != NULL ) + { + /* Print out the list of network interfaces. The first in the list + is interface '1', not interface '0'. */ + for( xInterface = pxAllNetworkInterfaces; xInterface != NULL; xInterface = xInterface->next ) + { + printf( "%d. %s", lInterfaceNumber, xInterface->name ); + + if( xInterface->description != NULL ) + { + printf( " (%s)\r\n", xInterface->description ); + } + else + { + printf( " (No description available)\r\n") ; + } + + lInterfaceNumber++; + } + } + + if( lInterfaceNumber == 1 ) + { + /* The interface number was never incremented, so the above for() loop + did not execute meaning no interfaces were found. */ + printf( " \r\nNo network interfaces were found.\r\n" ); + pxAllNetworkInterfaces = NULL; + } + + printf( "\r\nThe interface that will be opened is set by configNETWORK_INTERFACE_TO_USE which should be defined in FreeRTOSConfig.h\r\n" ); + printf( "Attempting to open interface number %d.\r\n", configNETWORK_INTERFACE_TO_USE ); + + if( ( configNETWORK_INTERFACE_TO_USE < 1L ) || ( configNETWORK_INTERFACE_TO_USE > lInterfaceNumber ) ) + { + printf("\r\nconfigNETWORK_INTERFACE_TO_USE is not in the valid range.\r\n" ); + + if( pxAllNetworkInterfaces != NULL ) + { + /* Free the device list, as no devices are going to be opened. */ + pcap_freealldevs( pxAllNetworkInterfaces ); + pxAllNetworkInterfaces = NULL; + } + } + + return pxAllNetworkInterfaces; +} +/*-----------------------------------------------------------*/ + +static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ) +{ +pcap_if_t *xInterface; +long x; + + /* Walk the list of devices until the selected device is located. */ + xInterface = pxAllNetworkInterfaces; + for( x = 0L; x < ( configNETWORK_INTERFACE_TO_USE - 1L ); x++ ) + { + xInterface = xInterface->next; + } + + /* Open the selected interface. */ + pxOpenedInterfaceHandle = pcap_open( xInterface->name, /* The name of the selected interface. */ + netifMAX_MTU, /* The size of the packet to capture. */ + PCAP_OPENFLAG_PROMISCUOUS, /* Open in promiscious mode as the MAC and + IP address is going to be "simulated", and + not be the real MAC and IP address. This allows + trafic to the simulated IP address to be routed + to uIP, and trafic to the real IP address to be + routed to the Windows TCP/IP stack. */ + 0L, /* The read time out. This is going to block + until data is available. */ + NULL, /* No authentication is required as this is + not a remote capture session. */ + cErrorBuffer + ); + + if ( pxOpenedInterfaceHandle == NULL ) + { + printf( "\r\n%s is not supported by WinPcap and cannot be opened\r\n", xInterface->name ); + } + else + { + /* Configure the capture filter to allow blocking reads, and to filter + out packets that are not of interest to this demo. */ + prvConfigureCaptureBehaviour(); + } + + /* The device list is no longer required. */ + pcap_freealldevs( pxAllNetworkInterfaces ); +} +/*-----------------------------------------------------------*/ + +static void prvInterruptSimulator( void *pvParameters ) +{ +static struct pcap_pkthdr *pxHeader; +const unsigned char *pucPacketData; +extern QueueHandle_t xEMACEventQueue; +long lResult; + + /* Just to kill the compiler warning. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Get the next packet. */ + lResult = pcap_next_ex( pxOpenedInterfaceHandle, &pxHeader, &pucPacketData ); + if( lResult == 1 ) + { + if( pxlwIPNetIf != NULL ) + { + prvEthernetInput( pucPacketData, pxHeader->len ); + } + } + else + { + /* There is no real way of simulating an interrupt. + Make sure other tasks can run. */ + vTaskDelay( 5 ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvConfigureCaptureBehaviour( void ) +{ +struct bpf_program xFilterCode; +const long lMinBytesToCopy = 10L, lBlocking = 1L; +unsigned long ulNetMask; + + /* Unblock a read as soon as anything is received. */ + pcap_setmintocopy( pxOpenedInterfaceHandle, lMinBytesToCopy ); + + /* Allow blocking. */ + pcap_setnonblock( pxOpenedInterfaceHandle, lBlocking, cErrorBuffer ); + + /* Set up a filter so only the packets of interest are passed to the lwIP + stack. cErrorBuffer is used for convenience to create the string. Don't + confuse this with an error message. */ + sprintf( cErrorBuffer, "broadcast or multicast or host %d.%d.%d.%d", configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 ); + + ulNetMask = ( configNET_MASK3 << 24UL ) | ( configNET_MASK2 << 16UL ) | ( configNET_MASK1 << 8L ) | configNET_MASK0; + + if( pcap_compile(pxOpenedInterfaceHandle, &xFilterCode, cErrorBuffer, 1, ulNetMask ) < 0 ) + { + printf( "\r\nThe packet filter string is invalid\r\n" ); + } + else + { + if( pcap_setfilter( pxOpenedInterfaceHandle, &xFilterCode ) < 0 ) + { + printf( "\r\nAn error occurred setting the packet filter.\r\n" ); + } + } + + /* Create a task that simulates an interrupt in a real system. This will + block waiting for packets, then send a message to the uIP task when data + is available. */ + xTaskCreate( prvInterruptSimulator, "MAC_ISR", configMINIMAL_STACK_SIZE, NULL, configMAC_ISR_SIMULATOR_PRIORITY, NULL ); +} + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/bpstruct.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/bpstruct.h new file mode 100644 index 0000000..1d81e3f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/bpstruct.h @@ -0,0 +1 @@ +#pragma pack(push,1) diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/cc.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/cc.h new file mode 100644 index 0000000..8c64b5d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/cc.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __ARCH_CC_H__ +#define __ARCH_CC_H__ + +#if 1 +/* Include some files for defining library routines */ +#include /* printf, fflush, FILE */ +#include /* abort */ +#else +/* Declare fuction prototypes for assert/diag/error - leads to some warnings, + * but good to test if no includes are missing. */ +int printf(const char *format, ...); +void abort(void); +struct _iobuf; +typedef struct _iobuf FILE; +int fflush(FILE *stream); +#endif + + + +/** @todo fix some warnings: don't use #pragma if compiling with cygwin gcc */ +#ifndef __GNUC__ +#include +#pragma warning (disable: 4244) /* disable conversion warning (implicit integer promotion!) */ +#pragma warning (disable: 4127) /* conditional expression is constant */ +#pragma warning (disable: 4996) /* 'strncpy' was declared deprecated */ +#pragma warning (disable: 4103) /* structure packing changed by including file */ +#endif + +#define LWIP_PROVIDE_ERRNO + +/* Define platform endianness (might already be defined) */ +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif /* BYTE_ORDER */ + +/* Define generic types used in lwIP */ +typedef unsigned char u8_t; +typedef signed char s8_t; +typedef unsigned short u16_t; +typedef signed short s16_t; +typedef unsigned long u32_t; +typedef signed long s32_t; + +typedef size_t mem_ptr_t; +typedef u32_t sys_prot_t; + +/* Define (sn)printf formatters for these lwIP types */ +#define X8_F "02x" +#define U16_F "hu" +#define S16_F "hd" +#define X16_F "hx" +#define U32_F "lu" +#define S32_F "ld" +#define X32_F "lx" +#define SZT_F U32_F + +/* Compiler hints for packing structures */ +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_USE_INCLUDES + +/* Plaform specific diagnostic output */ +#define LWIP_PLATFORM_DIAG(x) do { printf x; } while(0) + +#define LWIP_PLATFORM_ASSERT(x) do { printf("Assertion \"%s\" failed at line %d in %s\n", \ + x, __LINE__, __FILE__); fflush(NULL); abort(); } while(0) + +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + printf("Assertion \"%s\" failed at line %d in %s\n", message, __LINE__, __FILE__); \ + fflush(NULL);handler;} } while(0) + +/* C runtime functions redefined */ +#define snprintf _snprintf + +u32_t dns_lookup_external_hosts_file(const char *name); + +#define LWIP_RAND() ((u32_t)rand()) + +#endif /* __ARCH_CC_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/epstruct.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/epstruct.h new file mode 100644 index 0000000..65898b5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/epstruct.h @@ -0,0 +1 @@ +#pragma pack(pop) diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/perf.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/perf.h new file mode 100644 index 0000000..089faca --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/perf.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START /* null definition */ +#define PERF_STOP(x) /* null definition */ + +#endif /* __PERF_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/sys_arch.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/sys_arch.h new file mode 100644 index 0000000..f9eae84 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/sys_arch.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __ARCH_SYS_ARCH_H__ +#define __ARCH_SYS_ARCH_H__ + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +#define SYS_MBOX_NULL ( ( QueueHandle_t ) NULL ) +#define SYS_SEM_NULL ( ( SemaphoreHandle_t ) NULL ) +#define SYS_DEFAULT_THREAD_STACK_DEPTH configMINIMAL_STACK_SIZE + +typedef SemaphoreHandle_t sys_sem_t; +typedef SemaphoreHandle_t sys_mutex_t; +typedef QueueHandle_t sys_mbox_t; +typedef TaskHandle_t sys_thread_t; + +typedef unsigned long sys_prot_t; + +#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE ) +#define sys_mbox_set_invalid( x ) ( ( *x ) = NULL ) +#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE ) +#define sys_sem_set_invalid( x ) ( ( *x ) = NULL ) + + +#endif /* __ARCH_SYS_ARCH_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/lwipcfg_msvc.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/lwipcfg_msvc.h new file mode 100644 index 0000000..a6b5208 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/lwipcfg_msvc.h @@ -0,0 +1,45 @@ +/** + * Additional settings for the win32 port. + * Copy this to lwipcfg_msvc.h and make the config changes you need. + */ + +/* configuration for this port */ +#define PPP_USERNAME "Admin" +#define PPP_PASSWORD "pass" + +/** Define this to the index of the windows network adapter to use */ +#define PACKET_LIB_ADAPTER_NR 2 +/** Define this to the GUID of the windows network adapter to use + * or NOT define this if you want PACKET_LIB_ADAPTER_NR to be used */ +/*#define PACKET_LIB_ADAPTER_GUID "00000000-0000-0000-0000-000000000000"*/ +/*#define PACKET_LIB_GET_ADAPTER_NETADDRESS(addr) IP4_ADDR((addr), 192,168,1,0)*/ +/*#define PACKET_LIB_QUIET*/ + +#define LWIP_PORT_INIT_IPADDR(addr) IP4_ADDR((addr), 192,168,0,200) +#define LWIP_PORT_INIT_GW(addr) IP4_ADDR((addr), 192,168,0,3) +#define LWIP_PORT_INIT_NETMASK(addr) IP4_ADDR((addr), 255,255,255,0) + +/* remember to change this MAC address to suit your needs! + the last octet will be increased by netif->num for each netif */ +#define LWIP_MAC_ADDR_BASE {0x00,0x01,0x02,0x03,0x04,0x05} + +/* configuration for applications */ + +#define LWIP_CHARGEN_APP 0 +#define LWIP_DNS_APP 0 +#define LWIP_HTTPD_APP 1 +/* Set this to 1 to use the netconn http server, + * otherwise the raw api server will be used. */ +/*#define LWIP_HTTPD_APP_NETCONN */ +#define LWIP_NETBIOS_APP 0 +#define LWIP_NETIO_APP 0 +#define LWIP_PING_APP 0 +#define LWIP_RTP_APP 0 +#define LWIP_SHELL_APP 0 +#define LWIP_SNTP_APP 0 +#define LWIP_SOCKET_EXAMPLES_APP 0 +#define LWIP_TCPECHO_APP 0 +/* Set this to 1 to use the netconn tcpecho server, + * otherwise the raw api server will be used. */ +/*#define LWIP_TCPECHO_APP_NETCONN */ +#define LWIP_UDPECHO_APP 0 diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/sys_arch.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/sys_arch.c new file mode 100644 index 0000000..78b1298 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/ports/win32/sys_arch.c @@ -0,0 +1,541 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +//***************************************************************************** +// +// Include OS functionality. +// +//***************************************************************************** + +/* ------------------------ System architecture includes ----------------------------- */ +#include "arch/sys_arch.h" + +/* ------------------------ lwIP includes --------------------------------- */ +#include "lwip/opt.h" + +#include "lwip/debug.h" +#include "lwip/def.h" +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/stats.h" + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_new + *---------------------------------------------------------------------------* + * Description: + * Creates a new mailbox + * Inputs: + * int size -- Size of elements in the mailbox + * Outputs: + * sys_mbox_t -- Handle to new mailbox + *---------------------------------------------------------------------------*/ +err_t sys_mbox_new( sys_mbox_t *pxMailBox, int iSize ) +{ +err_t xReturn = ERR_MEM; + + *pxMailBox = xQueueCreate( iSize, sizeof( void * ) ); + + if( *pxMailBox != NULL ) + { + xReturn = ERR_OK; + SYS_STATS_INC_USED( mbox ); + } + + return xReturn; +} + + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_free + *---------------------------------------------------------------------------* + * Description: + * Deallocates a mailbox. If there are messages still present in the + * mailbox when the mailbox is deallocated, it is an indication of a + * programming error in lwIP and the developer should be notified. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * Outputs: + * sys_mbox_t -- Handle to new mailbox + *---------------------------------------------------------------------------*/ +void sys_mbox_free( sys_mbox_t *pxMailBox ) +{ +unsigned long ulMessagesWaiting; + + ulMessagesWaiting = uxQueueMessagesWaiting( *pxMailBox ); + configASSERT( ( ulMessagesWaiting == 0 ) ); + + #if SYS_STATS + { + if( ulMessagesWaiting != 0UL ) + { + SYS_STATS_INC( mbox.err ); + } + + SYS_STATS_DEC( mbox.used ); + } + #endif /* SYS_STATS */ + + vQueueDelete( *pxMailBox ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_post + *---------------------------------------------------------------------------* + * Description: + * Post the "msg" to the mailbox. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void *data -- Pointer to data to post + *---------------------------------------------------------------------------*/ +void sys_mbox_post( sys_mbox_t *pxMailBox, void *pxMessageToPost ) +{ + while( xQueueSendToBack( *pxMailBox, &pxMessageToPost, portMAX_DELAY ) != pdTRUE ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_trypost + *---------------------------------------------------------------------------* + * Description: + * Try to post the "msg" to the mailbox. Returns immediately with + * error if cannot. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void *msg -- Pointer to data to post + * Outputs: + * err_t -- ERR_OK if message posted, else ERR_MEM + * if not. + *---------------------------------------------------------------------------*/ +err_t sys_mbox_trypost( sys_mbox_t *pxMailBox, void *pxMessageToPost ) +{ +err_t xReturn; + + if( xQueueSend( *pxMailBox, &pxMessageToPost, 0UL ) == pdPASS ) + { + xReturn = ERR_OK; + } + else + { + /* The queue was already full. */ + xReturn = ERR_MEM; + SYS_STATS_INC( mbox.err ); + } + + return xReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_mbox_fetch + *---------------------------------------------------------------------------* + * Description: + * Blocks the thread until a message arrives in the mailbox, but does + * not block the thread longer than "timeout" milliseconds (similar to + * the sys_arch_sem_wait() function). The "msg" argument is a result + * parameter that is set by the function (i.e., by doing "*msg = + * ptr"). The "msg" parameter maybe NULL to indicate that the message + * should be dropped. + * + * The return values are the same as for the sys_arch_sem_wait() function: + * Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a + * timeout. + * + * Note that a function with a similar name, sys_mbox_fetch(), is + * implemented by lwIP. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void **msg -- Pointer to pointer to msg received + * u32_t timeout -- Number of milliseconds until timeout + * Outputs: + * u32_t -- SYS_ARCH_TIMEOUT if timeout, else number + * of milliseconds until received. + *---------------------------------------------------------------------------*/ +u32_t sys_arch_mbox_fetch( sys_mbox_t *pxMailBox, void **ppvBuffer, u32_t ulTimeOut ) +{ +void *pvDummy; +TickType_t xStartTime, xEndTime, xElapsed; +unsigned long ulReturn; + + xStartTime = xTaskGetTickCount(); + + if( NULL == ppvBuffer ) + { + ppvBuffer = &pvDummy; + } + + if( ulTimeOut != 0UL ) + { + if( pdTRUE == xQueueReceive( *pxMailBox, &( *ppvBuffer ), ulTimeOut/ portTICK_PERIOD_MS ) ) + { + xEndTime = xTaskGetTickCount(); + xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS; + + ulReturn = xElapsed; + } + else + { + /* Timed out. */ + *ppvBuffer = NULL; + ulReturn = SYS_ARCH_TIMEOUT; + } + } + else + { + while( pdTRUE != xQueueReceive( *pxMailBox, &( *ppvBuffer ), portMAX_DELAY ) ); + xEndTime = xTaskGetTickCount(); + xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS; + + if( xElapsed == 0UL ) + { + xElapsed = 1UL; + } + + ulReturn = xElapsed; + } + + return ulReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_mbox_tryfetch + *---------------------------------------------------------------------------* + * Description: + * Similar to sys_arch_mbox_fetch, but if message is not ready + * immediately, we'll return with SYS_MBOX_EMPTY. On success, 0 is + * returned. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void **msg -- Pointer to pointer to msg received + * Outputs: + * u32_t -- SYS_MBOX_EMPTY if no messages. Otherwise, + * return ERR_OK. + *---------------------------------------------------------------------------*/ +u32_t sys_arch_mbox_tryfetch( sys_mbox_t *pxMailBox, void **ppvBuffer ) +{ +void *pvDummy; +unsigned long ulReturn; + + if( ppvBuffer== NULL ) + { + ppvBuffer = &pvDummy; + } + + if( pdTRUE == xQueueReceive( *pxMailBox, &( *ppvBuffer ), 0UL ) ) + { + ulReturn = ERR_OK; + } + else + { + ulReturn = SYS_MBOX_EMPTY; + } + + return ulReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_sem_new + *---------------------------------------------------------------------------* + * Description: + * Creates and returns a new semaphore. The "ucCount" argument specifies + * the initial state of the semaphore. + * NOTE: Currently this routine only creates counts of 1 or 0 + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * u8_t ucCount -- Initial ucCount of semaphore (1 or 0) + * Outputs: + * sys_sem_t -- Created semaphore or 0 if could not create. + *---------------------------------------------------------------------------*/ +err_t sys_sem_new( sys_sem_t *pxSemaphore, u8_t ucCount ) +{ +err_t xReturn = ERR_MEM; + + vSemaphoreCreateBinary( ( *pxSemaphore ) ); + + if( *pxSemaphore != NULL ) + { + if( ucCount == 0U ) + { + xSemaphoreTake( *pxSemaphore, 1UL ); + } + + xReturn = ERR_OK; + SYS_STATS_INC_USED( sem ); + } + else + { + SYS_STATS_INC( sem.err ); + } + + return xReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_sem_wait + *---------------------------------------------------------------------------* + * Description: + * Blocks the thread while waiting for the semaphore to be + * signaled. If the "timeout" argument is non-zero, the thread should + * only be blocked for the specified time (measured in + * milliseconds). + * + * If the timeout argument is non-zero, the return value is the number of + * milliseconds spent waiting for the semaphore to be signaled. If the + * semaphore wasn't signaled within the specified time, the return value is + * SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore + * (i.e., it was already signaled), the function may return zero. + * + * Notice that lwIP implements a function with a similar name, + * sys_sem_wait(), that uses the sys_arch_sem_wait() function. + * Inputs: + * sys_sem_t sem -- Semaphore to wait on + * u32_t timeout -- Number of milliseconds until timeout + * Outputs: + * u32_t -- Time elapsed or SYS_ARCH_TIMEOUT. + *---------------------------------------------------------------------------*/ +u32_t sys_arch_sem_wait( sys_sem_t *pxSemaphore, u32_t ulTimeout ) +{ +TickType_t xStartTime, xEndTime, xElapsed; +unsigned long ulReturn; + + xStartTime = xTaskGetTickCount(); + + if( ulTimeout != 0UL ) + { + if( xSemaphoreTake( *pxSemaphore, ulTimeout / portTICK_PERIOD_MS ) == pdTRUE ) + { + xEndTime = xTaskGetTickCount(); + xElapsed = (xEndTime - xStartTime) * portTICK_PERIOD_MS; + ulReturn = xElapsed; + } + else + { + ulReturn = SYS_ARCH_TIMEOUT; + } + } + else + { + while( xSemaphoreTake( *pxSemaphore, portMAX_DELAY ) != pdTRUE ); + xEndTime = xTaskGetTickCount(); + xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS; + + if( xElapsed == 0UL ) + { + xElapsed = 1UL; + } + + ulReturn = xElapsed; + } + + return ulReturn; +} + +/** Create a new mutex + * @param mutex pointer to the mutex to create + * @return a new mutex */ +err_t sys_mutex_new( sys_mutex_t *pxMutex ) +{ +err_t xReturn = ERR_MEM; + + *pxMutex = xSemaphoreCreateMutex(); + + if( *pxMutex != NULL ) + { + xReturn = ERR_OK; + SYS_STATS_INC_USED( mutex ); + } + else + { + SYS_STATS_INC( mutex.err ); + } + + return xReturn; +} + +/** Lock a mutex + * @param mutex the mutex to lock */ +void sys_mutex_lock( sys_mutex_t *pxMutex ) +{ + while( xSemaphoreTake( *pxMutex, portMAX_DELAY ) != pdPASS ); +} + +/** Unlock a mutex + * @param mutex the mutex to unlock */ +void sys_mutex_unlock(sys_mutex_t *pxMutex ) +{ + xSemaphoreGive( *pxMutex ); +} + + +/** Delete a semaphore + * @param mutex the mutex to delete */ +void sys_mutex_free( sys_mutex_t *pxMutex ) +{ + SYS_STATS_DEC( mutex.used ); + vQueueDelete( *pxMutex ); +} + + +/*---------------------------------------------------------------------------* + * Routine: sys_sem_signal + *---------------------------------------------------------------------------* + * Description: + * Signals (releases) a semaphore + * Inputs: + * sys_sem_t sem -- Semaphore to signal + *---------------------------------------------------------------------------*/ +void sys_sem_signal( sys_sem_t *pxSemaphore ) +{ + xSemaphoreGive( *pxSemaphore ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_sem_free + *---------------------------------------------------------------------------* + * Description: + * Deallocates a semaphore + * Inputs: + * sys_sem_t sem -- Semaphore to free + *---------------------------------------------------------------------------*/ +void sys_sem_free( sys_sem_t *pxSemaphore ) +{ + SYS_STATS_DEC(sem.used); + vQueueDelete( *pxSemaphore ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_init + *---------------------------------------------------------------------------* + * Description: + * Initialize sys arch + *---------------------------------------------------------------------------*/ +void sys_init(void) +{ +} + +u32_t sys_now(void) +{ + return xTaskGetTickCount(); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_thread_new + *---------------------------------------------------------------------------* + * Description: + * Starts a new thread with priority "prio" that will begin its + * execution in the function "thread()". The "arg" argument will be + * passed as an argument to the thread() function. The id of the new + * thread is returned. Both the id and the priority are system + * dependent. + * Inputs: + * char *name -- Name of thread + * void (* thread)(void *arg) -- Pointer to function to run. + * void *arg -- Argument passed into function + * int stacksize -- Required stack amount in bytes + * int prio -- Thread priority + * Outputs: + * sys_thread_t -- Pointer to per-thread timeouts. + *---------------------------------------------------------------------------*/ +sys_thread_t sys_thread_new( const char *pcName, void( *pxThread )( void *pvParameters ), void *pvArg, int iStackSize, int iPriority ) +{ +TaskHandle_t xCreatedTask; +portBASE_TYPE xResult; +sys_thread_t xReturn; + + xResult = xTaskCreate( pxThread, pcName, iStackSize, pvArg, iPriority, &xCreatedTask ); + + if( xResult == pdPASS ) + { + xReturn = xCreatedTask; + } + else + { + xReturn = NULL; + } + + return xReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_protect + *---------------------------------------------------------------------------* + * Description: + * This optional function does a "fast" critical region protection and + * returns the previous protection level. This function is only called + * during very short critical regions. An embedded system which supports + * ISR-based drivers might want to implement this function by disabling + * interrupts. Task-based systems might want to implement this by using + * a mutex or disabling tasking. This function should support recursive + * calls from the same task or interrupt. In other words, + * sys_arch_protect() could be called while already protected. In + * that case the return value indicates that it is already protected. + * + * sys_arch_protect() is only required if your port is supporting an + * operating system. + * Outputs: + * sys_prot_t -- Previous protection level (not used here) + *---------------------------------------------------------------------------*/ +sys_prot_t sys_arch_protect( void ) +{ + vPortEnterCritical(); + return ( sys_prot_t ) 1; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_unprotect + *---------------------------------------------------------------------------* + * Description: + * This optional function does a "fast" set of critical region + * protection to the value specified by pval. See the documentation for + * sys_arch_protect() for more information. This function is only + * required if your port is supporting an operating system. + * Inputs: + * sys_prot_t -- Previous protection level (not used here) + *---------------------------------------------------------------------------*/ +void sys_arch_unprotect( sys_prot_t xValue ) +{ + (void) xValue; + taskEXIT_CRITICAL(); +} + +/* + * Prints an assertion messages and aborts execution. + */ +void sys_assert( const char *pcMessage ) +{ + (void) pcMessage; + + for (;;) + { + } +} +/*-------------------------------------------------------------------------* + * End of File: sys_arch.c + *-------------------------------------------------------------------------*/ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/.hgignore b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/.hgignore new file mode 100644 index 0000000..f88587d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/.hgignore @@ -0,0 +1,26 @@ +syntax: glob + +*.pyc +*.orig +*.rej +*~ +TAGS +Module.symvers +*.ncb +*.suo +*.bak +*.orig +*.rej + +syntax: regexp +\.\#.+ +[\\/]CVS$ +^CVS$ +^build$ +^install$ +^logs.build_tree$ +[\\/]bin$ +^bin$ +[\\/]obj$ +^obj$ +\.cvsignore diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/FILES b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/FILES new file mode 100644 index 0000000..952aeab --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/FILES @@ -0,0 +1,13 @@ +api/ - The code for the high-level wrapper API. Not needed if + you use the lowel-level call-back/raw API. + +core/ - The core of the TPC/IP stack; protocol implementations, + memory and buffer management, and the low-level raw API. + +include/ - lwIP include files. + +netif/ - Generic network interface device drivers are kept here, + as well as the ARP module. + +For more information on the various subdirectories, check the FILES +file in each directory. diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/api_lib.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/api_lib.c new file mode 100644 index 0000000..b1a9e52 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/api_lib.c @@ -0,0 +1,740 @@ +/** + * @file + * Sequential API External module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* This is the part of the API that is linked with + the application */ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/api.h" +#include "lwip/tcpip.h" +#include "lwip/memp.h" + +#include "lwip/ip.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" + +#include + +/** + * Create a new netconn (of a specific type) that has a callback function. + * The corresponding pcb is also created. + * + * @param t the type of 'connection' to create (@see enum netconn_type) + * @param proto the IP protocol for RAW IP pcbs + * @param callback a function to call on status changes (RX available, TX'ed) + * @return a newly allocated struct netconn or + * NULL on memory error + */ +struct netconn* +netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback) +{ + struct netconn *conn; + struct api_msg msg; + + conn = netconn_alloc(t, callback); + if (conn != NULL) { + msg.function = do_newconn; + msg.msg.msg.n.proto = proto; + msg.msg.conn = conn; + if (TCPIP_APIMSG(&msg) != ERR_OK) { + LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL); + LWIP_ASSERT("conn has no op_completed", sys_sem_valid(&conn->op_completed)); + LWIP_ASSERT("conn has no recvmbox", sys_mbox_valid(&conn->recvmbox)); +#if LWIP_TCP + LWIP_ASSERT("conn->acceptmbox shouldn't exist", !sys_mbox_valid(&conn->acceptmbox)); +#endif /* LWIP_TCP */ + sys_sem_free(&conn->op_completed); + sys_mbox_free(&conn->recvmbox); + memp_free(MEMP_NETCONN, conn); + return NULL; + } + } + return conn; +} + +/** + * Close a netconn 'connection' and free its resources. + * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate + * after this returns. + * + * @param conn the netconn to delete + * @return ERR_OK if the connection was deleted + */ +err_t +netconn_delete(struct netconn *conn) +{ + struct api_msg msg; + + /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */ + if (conn == NULL) { + return ERR_OK; + } + + msg.function = do_delconn; + msg.msg.conn = conn; + tcpip_apimsg(&msg); + + netconn_free(conn); + + /* don't care for return value of do_delconn since it only calls void functions */ + + return ERR_OK; +} + +/** + * Get the local or remote IP address and port of a netconn. + * For RAW netconns, this returns the protocol instead of a port! + * + * @param conn the netconn to query + * @param addr a pointer to which to save the IP address + * @param port a pointer to which to save the port (or protocol for RAW) + * @param local 1 to get the local IP address, 0 to get the remote one + * @return ERR_CONN for invalid connections + * ERR_OK if the information was retrieved + */ +err_t +netconn_getaddr(struct netconn *conn, ip_addr_t *addr, u16_t *port, u8_t local) +{ + struct api_msg msg; + err_t err; + + LWIP_ERROR("netconn_getaddr: invalid conn", (conn != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_getaddr: invalid addr", (addr != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_getaddr: invalid port", (port != NULL), return ERR_ARG;); + + msg.function = do_getaddr; + msg.msg.conn = conn; + msg.msg.msg.ad.ipaddr = addr; + msg.msg.msg.ad.port = port; + msg.msg.msg.ad.local = local; + err = TCPIP_APIMSG(&msg); + + NETCONN_SET_SAFE_ERR(conn, err); + return err; +} + +/** + * Bind a netconn to a specific local IP address and port. + * Binding one netconn twice might not always be checked correctly! + * + * @param conn the netconn to bind + * @param addr the local IP address to bind the netconn to (use IP_ADDR_ANY + * to bind to all addresses) + * @param port the local port to bind the netconn to (not used for RAW) + * @return ERR_OK if bound, any other err_t on failure + */ +err_t +netconn_bind(struct netconn *conn, ip_addr_t *addr, u16_t port) +{ + struct api_msg msg; + err_t err; + + LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;); + + msg.function = do_bind; + msg.msg.conn = conn; + msg.msg.msg.bc.ipaddr = addr; + msg.msg.msg.bc.port = port; + err = TCPIP_APIMSG(&msg); + + NETCONN_SET_SAFE_ERR(conn, err); + return err; +} + +/** + * Connect a netconn to a specific remote IP address and port. + * + * @param conn the netconn to connect + * @param addr the remote IP address to connect to + * @param port the remote port to connect to (no used for RAW) + * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise + */ +err_t +netconn_connect(struct netconn *conn, ip_addr_t *addr, u16_t port) +{ + struct api_msg msg; + err_t err; + + LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;); + + msg.function = do_connect; + msg.msg.conn = conn; + msg.msg.msg.bc.ipaddr = addr; + msg.msg.msg.bc.port = port; + /* This is the only function which need to not block tcpip_thread */ + err = tcpip_apimsg(&msg); + + NETCONN_SET_SAFE_ERR(conn, err); + return err; +} + +/** + * Disconnect a netconn from its current peer (only valid for UDP netconns). + * + * @param conn the netconn to disconnect + * @return TODO: return value is not set here... + */ +err_t +netconn_disconnect(struct netconn *conn) +{ + struct api_msg msg; + err_t err; + + LWIP_ERROR("netconn_disconnect: invalid conn", (conn != NULL), return ERR_ARG;); + + msg.function = do_disconnect; + msg.msg.conn = conn; + err = TCPIP_APIMSG(&msg); + + NETCONN_SET_SAFE_ERR(conn, err); + return err; +} + +/** + * Set a TCP netconn into listen mode + * + * @param conn the tcp netconn to set to listen mode + * @param backlog the listen backlog, only used if TCP_LISTEN_BACKLOG==1 + * @return ERR_OK if the netconn was set to listen (UDP and RAW netconns + * don't return any error (yet?)) + */ +err_t +netconn_listen_with_backlog(struct netconn *conn, u8_t backlog) +{ +#if LWIP_TCP + struct api_msg msg; + err_t err; + + /* This does no harm. If TCP_LISTEN_BACKLOG is off, backlog is unused. */ + LWIP_UNUSED_ARG(backlog); + + LWIP_ERROR("netconn_listen: invalid conn", (conn != NULL), return ERR_ARG;); + + msg.function = do_listen; + msg.msg.conn = conn; +#if TCP_LISTEN_BACKLOG + msg.msg.msg.lb.backlog = backlog; +#endif /* TCP_LISTEN_BACKLOG */ + err = TCPIP_APIMSG(&msg); + + NETCONN_SET_SAFE_ERR(conn, err); + return err; +#else /* LWIP_TCP */ + LWIP_UNUSED_ARG(conn); + LWIP_UNUSED_ARG(backlog); + return ERR_ARG; +#endif /* LWIP_TCP */ +} + +/** + * Accept a new connection on a TCP listening netconn. + * + * @param conn the TCP listen netconn + * @param new_conn pointer where the new connection is stored + * @return ERR_OK if a new connection has been received or an error + * code otherwise + */ +err_t +netconn_accept(struct netconn *conn, struct netconn **new_conn) +{ +#if LWIP_TCP + struct netconn *newconn; + err_t err; +#if TCP_LISTEN_BACKLOG + struct api_msg msg; +#endif /* TCP_LISTEN_BACKLOG */ + + LWIP_ERROR("netconn_accept: invalid pointer", (new_conn != NULL), return ERR_ARG;); + *new_conn = NULL; + LWIP_ERROR("netconn_accept: invalid conn", (conn != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_accept: invalid acceptmbox", sys_mbox_valid(&conn->acceptmbox), return ERR_ARG;); + + err = conn->last_err; + if (ERR_IS_FATAL(err)) { + /* don't recv on fatal errors: this might block the application task + waiting on acceptmbox forever! */ + return err; + } + +#if LWIP_SO_RCVTIMEO + if (sys_arch_mbox_fetch(&conn->acceptmbox, (void **)&newconn, conn->recv_timeout) == SYS_ARCH_TIMEOUT) { + NETCONN_SET_SAFE_ERR(conn, ERR_TIMEOUT); + return ERR_TIMEOUT; + } +#else + sys_arch_mbox_fetch(&conn->acceptmbox, (void **)&newconn, 0); +#endif /* LWIP_SO_RCVTIMEO*/ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0); + + if (newconn == NULL) { + /* connection has been aborted */ + NETCONN_SET_SAFE_ERR(conn, ERR_ABRT); + return ERR_ABRT; + } +#if TCP_LISTEN_BACKLOG + /* Let the stack know that we have accepted the connection. */ + msg.function = do_recv; + msg.msg.conn = conn; + /* don't care for the return value of do_recv */ + TCPIP_APIMSG(&msg); +#endif /* TCP_LISTEN_BACKLOG */ + + *new_conn = newconn; + /* don't set conn->last_err: it's only ERR_OK, anyway */ + return ERR_OK; +#else /* LWIP_TCP */ + LWIP_UNUSED_ARG(conn); + LWIP_UNUSED_ARG(new_conn); + return ERR_ARG; +#endif /* LWIP_TCP */ +} + +/** + * Receive data: actual implementation that doesn't care whether pbuf or netbuf + * is received + * + * @param conn the netconn from which to receive data + * @param new_buf pointer where a new pbuf/netbuf is stored when received data + * @return ERR_OK if data has been received, an error code otherwise (timeout, + * memory error or another error) + */ +static err_t +netconn_recv_data(struct netconn *conn, void **new_buf) +{ + void *buf = NULL; + u16_t len; + err_t err; +#if LWIP_TCP + struct api_msg msg; +#endif /* LWIP_TCP */ + + LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;); + *new_buf = NULL; + LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_accept: invalid recvmbox", sys_mbox_valid(&conn->recvmbox), return ERR_CONN;); + + err = conn->last_err; + if (ERR_IS_FATAL(err)) { + /* don't recv on fatal errors: this might block the application task + waiting on recvmbox forever! */ + /* @todo: this does not allow us to fetch data that has been put into recvmbox + before the fatal error occurred - is that a problem? */ + return err; + } + +#if LWIP_SO_RCVTIMEO + if (sys_arch_mbox_fetch(&conn->recvmbox, &buf, conn->recv_timeout) == SYS_ARCH_TIMEOUT) { + NETCONN_SET_SAFE_ERR(conn, ERR_TIMEOUT); + return ERR_TIMEOUT; + } +#else + sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0); +#endif /* LWIP_SO_RCVTIMEO*/ + +#if LWIP_TCP + if (conn->type == NETCONN_TCP) { + if (!netconn_get_noautorecved(conn) || (buf == NULL)) { + /* Let the stack know that we have taken the data. */ + /* TODO: Speedup: Don't block and wait for the answer here + (to prevent multiple thread-switches). */ + msg.function = do_recv; + msg.msg.conn = conn; + if (buf != NULL) { + msg.msg.msg.r.len = ((struct pbuf *)buf)->tot_len; + } else { + msg.msg.msg.r.len = 1; + } + /* don't care for the return value of do_recv */ + TCPIP_APIMSG(&msg); + } + + /* If we are closed, we indicate that we no longer wish to use the socket */ + if (buf == NULL) { + API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0); + /* Avoid to lose any previous error code */ + NETCONN_SET_SAFE_ERR(conn, ERR_CLSD); + return ERR_CLSD; + } + len = ((struct pbuf *)buf)->tot_len; + } +#endif /* LWIP_TCP */ +#if LWIP_TCP && (LWIP_UDP || LWIP_RAW) + else +#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */ +#if (LWIP_UDP || LWIP_RAW) + { + LWIP_ASSERT("buf != NULL", buf != NULL); + len = netbuf_len((struct netbuf *)buf); + } +#endif /* (LWIP_UDP || LWIP_RAW) */ + +#if LWIP_SO_RCVBUF + SYS_ARCH_DEC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVMINUS, len); + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv_data: received %p, len=%"U16_F"\n", buf, len)); + + *new_buf = buf; + /* don't set conn->last_err: it's only ERR_OK, anyway */ + return ERR_OK; +} + +/** + * Receive data (in form of a pbuf) from a TCP netconn + * + * @param conn the netconn from which to receive data + * @param new_buf pointer where a new pbuf is stored when received data + * @return ERR_OK if data has been received, an error code otherwise (timeout, + * memory error or another error) + * ERR_ARG if conn is not a TCP netconn + */ +err_t +netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf) +{ + LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL) && + netconn_type(conn) == NETCONN_TCP, return ERR_ARG;); + + return netconn_recv_data(conn, (void **)new_buf); +} + +/** + * Receive data (in form of a netbuf containing a packet buffer) from a netconn + * + * @param conn the netconn from which to receive data + * @param new_buf pointer where a new netbuf is stored when received data + * @return ERR_OK if data has been received, an error code otherwise (timeout, + * memory error or another error) + */ +err_t +netconn_recv(struct netconn *conn, struct netbuf **new_buf) +{ +#if LWIP_TCP + struct netbuf *buf = NULL; + err_t err; +#endif /* LWIP_TCP */ + + LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;); + *new_buf = NULL; + LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_accept: invalid recvmbox", sys_mbox_valid(&conn->recvmbox), return ERR_CONN;); + +#if LWIP_TCP + if (conn->type == NETCONN_TCP) { + struct pbuf *p = NULL; + /* This is not a listening netconn, since recvmbox is set */ + + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + NETCONN_SET_SAFE_ERR(conn, ERR_MEM); + return ERR_MEM; + } + + err = netconn_recv_data(conn, (void **)&p); + if (err != ERR_OK) { + memp_free(MEMP_NETBUF, buf); + return err; + } + LWIP_ASSERT("p != NULL", p != NULL); + + buf->p = p; + buf->ptr = p; + buf->port = 0; + ip_addr_set_any(&buf->addr); + *new_buf = buf; + /* don't set conn->last_err: it's only ERR_OK, anyway */ + return ERR_OK; + } else +#endif /* LWIP_TCP */ + { +#if (LWIP_UDP || LWIP_RAW) + return netconn_recv_data(conn, (void **)new_buf); +#endif /* (LWIP_UDP || LWIP_RAW) */ + } +} + +/** + * TCP: update the receive window: by calling this, the application + * tells the stack that it has processed data and is able to accept + * new data. + * ATTENTION: use with care, this is mainly used for sockets! + * Can only be used when calling netconn_set_noautorecved(conn, 1) before. + * + * @param conn the netconn for which to update the receive window + * @param length amount of data processed (ATTENTION: this must be accurate!) + */ +void +netconn_recved(struct netconn *conn, u32_t length) +{ +#if LWIP_TCP + if ((conn != NULL) && (conn->type == NETCONN_TCP) && + (netconn_get_noautorecved(conn))) { + struct api_msg msg; + /* Let the stack know that we have taken the data. */ + /* TODO: Speedup: Don't block and wait for the answer here + (to prevent multiple thread-switches). */ + msg.function = do_recv; + msg.msg.conn = conn; + msg.msg.msg.r.len = length; + /* don't care for the return value of do_recv */ + TCPIP_APIMSG(&msg); + } +#else /* LWIP_TCP */ + LWIP_UNUSED_ARG(conn); + LWIP_UNUSED_ARG(length); +#endif /* LWIP_TCP */ +} + +/** + * Send data (in form of a netbuf) to a specific remote IP address and port. + * Only to be used for UDP and RAW netconns (not TCP). + * + * @param conn the netconn over which to send data + * @param buf a netbuf containing the data to send + * @param addr the remote IP address to which to send the data + * @param port the remote port to which to send the data + * @return ERR_OK if data was sent, any other err_t on error + */ +err_t +netconn_sendto(struct netconn *conn, struct netbuf *buf, ip_addr_t *addr, u16_t port) +{ + if (buf != NULL) { + ip_addr_set(&buf->addr, addr); + buf->port = port; + return netconn_send(conn, buf); + } + return ERR_VAL; +} + +/** + * Send data over a UDP or RAW netconn (that is already connected). + * + * @param conn the UDP or RAW netconn over which to send data + * @param buf a netbuf containing the data to send + * @return ERR_OK if data was sent, any other err_t on error + */ +err_t +netconn_send(struct netconn *conn, struct netbuf *buf) +{ + struct api_msg msg; + err_t err; + + LWIP_ERROR("netconn_send: invalid conn", (conn != NULL), return ERR_ARG;); + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %"U16_F" bytes\n", buf->p->tot_len)); + msg.function = do_send; + msg.msg.conn = conn; + msg.msg.msg.b = buf; + err = TCPIP_APIMSG(&msg); + + NETCONN_SET_SAFE_ERR(conn, err); + return err; +} + +/** + * Send data over a TCP netconn. + * + * @param conn the TCP netconn over which to send data + * @param dataptr pointer to the application buffer that contains the data to send + * @param size size of the application data to send + * @param apiflags combination of following flags : + * - NETCONN_COPY: data will be copied into memory belonging to the stack + * - NETCONN_MORE: for TCP connection, PSH flag will be set on last segment sent + * - NETCONN_DONTBLOCK: only write the data if all dat can be written at once + * @return ERR_OK if data was sent, any other err_t on error + */ +err_t +netconn_write(struct netconn *conn, const void *dataptr, size_t size, u8_t apiflags) +{ + struct api_msg msg; + err_t err; + + LWIP_ERROR("netconn_write: invalid conn", (conn != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_write: invalid conn->type", (conn->type == NETCONN_TCP), return ERR_VAL;); + if (size == 0) { + return ERR_OK; + } + + /* @todo: for non-blocking write, check if 'size' would ever fit into + snd_queue or snd_buf */ + msg.function = do_write; + msg.msg.conn = conn; + msg.msg.msg.w.dataptr = dataptr; + msg.msg.msg.w.apiflags = apiflags; + msg.msg.msg.w.len = size; + /* For locking the core: this _can_ be delayed on low memory/low send buffer, + but if it is, this is done inside api_msg.c:do_write(), so we can use the + non-blocking version here. */ + err = TCPIP_APIMSG(&msg); + + NETCONN_SET_SAFE_ERR(conn, err); + return err; +} + +/** + * Close ot shutdown a TCP netconn (doesn't delete it). + * + * @param conn the TCP netconn to close or shutdown + * @param how fully close or only shutdown one side? + * @return ERR_OK if the netconn was closed, any other err_t on error + */ +static err_t +netconn_close_shutdown(struct netconn *conn, u8_t how) +{ + struct api_msg msg; + err_t err; + + LWIP_ERROR("netconn_close: invalid conn", (conn != NULL), return ERR_ARG;); + + msg.function = do_close; + msg.msg.conn = conn; + /* shutting down both ends is the same as closing */ + msg.msg.msg.sd.shut = how; + /* because of the LWIP_TCPIP_CORE_LOCKING implementation of do_close, + don't use TCPIP_APIMSG here */ + err = tcpip_apimsg(&msg); + + NETCONN_SET_SAFE_ERR(conn, err); + return err; +} + +/** + * Close a TCP netconn (doesn't delete it). + * + * @param conn the TCP netconn to close + * @return ERR_OK if the netconn was closed, any other err_t on error + */ +err_t +netconn_close(struct netconn *conn) +{ + /* shutting down both ends is the same as closing */ + return netconn_close_shutdown(conn, NETCONN_SHUT_RDWR); +} + +/** + * Shut down one or both sides of a TCP netconn (doesn't delete it). + * + * @param conn the TCP netconn to shut down + * @return ERR_OK if the netconn was closed, any other err_t on error + */ +err_t +netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx) +{ + return netconn_close_shutdown(conn, (shut_rx ? NETCONN_SHUT_RD : 0) | (shut_tx ? NETCONN_SHUT_WR : 0)); +} + +#if LWIP_IGMP +/** + * Join multicast groups for UDP netconns. + * + * @param conn the UDP netconn for which to change multicast addresses + * @param multiaddr IP address of the multicast group to join or leave + * @param netif_addr the IP address of the network interface on which to send + * the igmp message + * @param join_or_leave flag whether to send a join- or leave-message + * @return ERR_OK if the action was taken, any err_t on error + */ +err_t +netconn_join_leave_group(struct netconn *conn, + ip_addr_t *multiaddr, + ip_addr_t *netif_addr, + enum netconn_igmp join_or_leave) +{ + struct api_msg msg; + err_t err; + + LWIP_ERROR("netconn_join_leave_group: invalid conn", (conn != NULL), return ERR_ARG;); + + msg.function = do_join_leave_group; + msg.msg.conn = conn; + msg.msg.msg.jl.multiaddr = multiaddr; + msg.msg.msg.jl.netif_addr = netif_addr; + msg.msg.msg.jl.join_or_leave = join_or_leave; + err = TCPIP_APIMSG(&msg); + + NETCONN_SET_SAFE_ERR(conn, err); + return err; +} +#endif /* LWIP_IGMP */ + +#if LWIP_DNS +/** + * Execute a DNS query, only one IP address is returned + * + * @param name a string representation of the DNS host name to query + * @param addr a preallocated ip_addr_t where to store the resolved IP address + * @return ERR_OK: resolving succeeded + * ERR_MEM: memory error, try again later + * ERR_ARG: dns client not initialized or invalid hostname + * ERR_VAL: dns server response was invalid + */ +err_t +netconn_gethostbyname(const char *name, ip_addr_t *addr) +{ + struct dns_api_msg msg; + err_t err; + sys_sem_t sem; + + LWIP_ERROR("netconn_gethostbyname: invalid name", (name != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_gethostbyname: invalid addr", (addr != NULL), return ERR_ARG;); + + err = sys_sem_new(&sem, 0); + if (err != ERR_OK) { + return err; + } + + msg.name = name; + msg.addr = addr; + msg.err = &err; + msg.sem = &sem; + + tcpip_callback(do_gethostbyname, &msg); + sys_sem_wait(&sem); + sys_sem_free(&sem); + + return err; +} +#endif /* LWIP_DNS*/ + +#endif /* LWIP_NETCONN */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/api_msg.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/api_msg.c new file mode 100644 index 0000000..448f96d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/api_msg.c @@ -0,0 +1,1535 @@ +/** + * @file + * Sequential API Internal module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/api_msg.h" + +#include "lwip/ip.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" +#include "lwip/raw.h" + +#include "lwip/memp.h" +#include "lwip/tcpip.h" +#include "lwip/igmp.h" +#include "lwip/dns.h" + +#include + +#define SET_NONBLOCKING_CONNECT(conn, val) do { if(val) { \ + (conn)->flags |= NETCONN_FLAG_IN_NONBLOCKING_CONNECT; \ +} else { \ + (conn)->flags &= ~ NETCONN_FLAG_IN_NONBLOCKING_CONNECT; }} while(0) +#define IN_NONBLOCKING_CONNECT(conn) (((conn)->flags & NETCONN_FLAG_IN_NONBLOCKING_CONNECT) != 0) + +/* forward declarations */ +#if LWIP_TCP +static err_t do_writemore(struct netconn *conn); +static void do_close_internal(struct netconn *conn); +#endif + +#if LWIP_RAW +/** + * Receive callback function for RAW netconns. + * Doesn't 'eat' the packet, only references it and sends it to + * conn->recvmbox + * + * @see raw.h (struct raw_pcb.recv) for parameters and return value + */ +static u8_t +recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, + ip_addr_t *addr) +{ + struct pbuf *q; + struct netbuf *buf; + struct netconn *conn; + + LWIP_UNUSED_ARG(addr); + conn = (struct netconn *)arg; + + if ((conn != NULL) && sys_mbox_valid(&conn->recvmbox)) { +#if LWIP_SO_RCVBUF + int recv_avail; + SYS_ARCH_GET(conn->recv_avail, recv_avail); + if ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize) { + return 0; + } +#endif /* LWIP_SO_RCVBUF */ + /* copy the whole packet into new pbufs */ + q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if(q != NULL) { + if (pbuf_copy(q, p) != ERR_OK) { + pbuf_free(q); + q = NULL; + } + } + + if (q != NULL) { + u16_t len; + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(q); + return 0; + } + + buf->p = q; + buf->ptr = q; + ip_addr_copy(buf->addr, *ip_current_src_addr()); + buf->port = pcb->protocol; + + len = q->tot_len; + if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { + netbuf_delete(buf); + return 0; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } + } + } + + return 0; /* do not eat the packet */ +} +#endif /* LWIP_RAW*/ + +#if LWIP_UDP +/** + * Receive callback function for UDP netconns. + * Posts the packet to conn->recvmbox or deletes it on memory error. + * + * @see udp.h (struct udp_pcb.recv) for parameters + */ +static void +recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *addr, u16_t port) +{ + struct netbuf *buf; + struct netconn *conn; + u16_t len; +#if LWIP_SO_RCVBUF + int recv_avail; +#endif /* LWIP_SO_RCVBUF */ + + LWIP_UNUSED_ARG(pcb); /* only used for asserts... */ + LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL); + LWIP_ASSERT("recv_udp must have an argument", arg != NULL); + conn = (struct netconn *)arg; + LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb); + +#if LWIP_SO_RCVBUF + SYS_ARCH_GET(conn->recv_avail, recv_avail); + if ((conn == NULL) || !sys_mbox_valid(&conn->recvmbox) || + ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) { +#else /* LWIP_SO_RCVBUF */ + if ((conn == NULL) || !sys_mbox_valid(&conn->recvmbox)) { +#endif /* LWIP_SO_RCVBUF */ + pbuf_free(p); + return; + } + + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(p); + return; + } else { + buf->p = p; + buf->ptr = p; + ip_addr_set(&buf->addr, addr); + buf->port = port; +#if LWIP_NETBUF_RECVINFO + { + const struct ip_hdr* iphdr = ip_current_header(); + /* get the UDP header - always in the first pbuf, ensured by udp_input */ + const struct udp_hdr* udphdr = (void*)(((char*)iphdr) + IPH_LEN(iphdr)); +#if LWIP_CHECKSUM_ON_COPY + buf->flags = NETBUF_FLAG_DESTADDR; +#endif /* LWIP_CHECKSUM_ON_COPY */ + ip_addr_set(&buf->toaddr, ip_current_dest_addr()); + buf->toport_chksum = udphdr->dest; + } +#endif /* LWIP_NETBUF_RECVINFO */ + } + + len = p->tot_len; + if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { + netbuf_delete(buf); + return; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } +} +#endif /* LWIP_UDP */ + +#if LWIP_TCP +/** + * Receive callback function for TCP netconns. + * Posts the packet to conn->recvmbox, but doesn't delete it on errors. + * + * @see tcp.h (struct tcp_pcb.recv) for parameters and return value + */ +static err_t +recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + struct netconn *conn; + u16_t len; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL); + LWIP_ASSERT("recv_tcp must have an argument", arg != NULL); + conn = (struct netconn *)arg; + LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb); + + if (conn == NULL) { + return ERR_VAL; + } + if (!sys_mbox_valid(&conn->recvmbox)) { + /* recvmbox already deleted */ + if (p != NULL) { + tcp_recved(pcb, p->tot_len); + pbuf_free(p); + } + return ERR_OK; + } + /* Unlike for UDP or RAW pcbs, don't check for available space + using recv_avail since that could break the connection + (data is already ACKed) */ + + /* don't overwrite fatal errors! */ + NETCONN_SET_SAFE_ERR(conn, err); + + if (p != NULL) { + len = p->tot_len; + } else { + len = 0; + } + + if (sys_mbox_trypost(&conn->recvmbox, p) != ERR_OK) { + /* don't deallocate p: it is presented to us later again from tcp_fasttmr! */ + return ERR_MEM; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } + + return ERR_OK; +} + +/** + * Poll callback function for TCP netconns. + * Wakes up an application thread that waits for a connection to close + * or data to be sent. The application thread then takes the + * appropriate action to go on. + * + * Signals the conn->sem. + * netconn_close waits for conn->sem if closing failed. + * + * @see tcp.h (struct tcp_pcb.poll) for parameters and return value + */ +static err_t +poll_tcp(void *arg, struct tcp_pcb *pcb) +{ + struct netconn *conn = (struct netconn *)arg; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + if (conn->state == NETCONN_WRITE) { + do_writemore(conn); + } else if (conn->state == NETCONN_CLOSE) { + do_close_internal(conn); + } + /* @todo: implement connect timeout here? */ + + /* Did a nonblocking write fail before? Then check available write-space. */ + if (conn->flags & NETCONN_FLAG_CHECK_WRITESPACE) { + /* If the queued byte- or pbuf-count drops below the configured low-water limit, + let select mark this pcb as writable again. */ + if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && + (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { + conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE; + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + } + } + + return ERR_OK; +} + +/** + * Sent callback function for TCP netconns. + * Signals the conn->sem and calls API_EVENT. + * netconn_write waits for conn->sem if send buffer is low. + * + * @see tcp.h (struct tcp_pcb.sent) for parameters and return value + */ +static err_t +sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) +{ + struct netconn *conn = (struct netconn *)arg; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + if (conn->state == NETCONN_WRITE) { + do_writemore(conn); + } else if (conn->state == NETCONN_CLOSE) { + do_close_internal(conn); + } + + if (conn) { + /* If the queued byte- or pbuf-count drops below the configured low-water limit, + let select mark this pcb as writable again. */ + if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && + (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { + conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE; + API_EVENT(conn, NETCONN_EVT_SENDPLUS, len); + } + } + + return ERR_OK; +} + +/** + * Error callback function for TCP netconns. + * Signals conn->sem, posts to all conn mboxes and calls API_EVENT. + * The application thread has then to decide what to do. + * + * @see tcp.h (struct tcp_pcb.err) for parameters + */ +static void +err_tcp(void *arg, err_t err) +{ + struct netconn *conn; + enum netconn_state old_state; + SYS_ARCH_DECL_PROTECT(lev); + + conn = (struct netconn *)arg; + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + conn->pcb.tcp = NULL; + + /* no check since this is always fatal! */ + SYS_ARCH_PROTECT(lev); + conn->last_err = err; + SYS_ARCH_UNPROTECT(lev); + + /* reset conn->state now before waking up other threads */ + old_state = conn->state; + conn->state = NETCONN_NONE; + + /* Notify the user layer about a connection error. Used to signal + select. */ + API_EVENT(conn, NETCONN_EVT_ERROR, 0); + /* Try to release selects pending on 'read' or 'write', too. + They will get an error if they actually try to read or write. */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + + /* pass NULL-message to recvmbox to wake up pending recv */ + if (sys_mbox_valid(&conn->recvmbox)) { + /* use trypost to prevent deadlock */ + sys_mbox_trypost(&conn->recvmbox, NULL); + } + /* pass NULL-message to acceptmbox to wake up pending accept */ + if (sys_mbox_valid(&conn->acceptmbox)) { + /* use trypost to preven deadlock */ + sys_mbox_trypost(&conn->acceptmbox, NULL); + } + + if ((old_state == NETCONN_WRITE) || (old_state == NETCONN_CLOSE) || + (old_state == NETCONN_CONNECT)) { + /* calling do_writemore/do_close_internal is not necessary + since the pcb has already been deleted! */ + int was_nonblocking_connect = IN_NONBLOCKING_CONNECT(conn); + SET_NONBLOCKING_CONNECT(conn, 0); + + if (!was_nonblocking_connect) { + /* set error return code */ + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + conn->current_msg->err = err; + conn->current_msg = NULL; + /* wake up the waiting task */ + sys_sem_signal(&conn->op_completed); + } + } else { + LWIP_ASSERT("conn->current_msg == NULL", conn->current_msg == NULL); + } +} + +/** + * Setup a tcp_pcb with the correct callback function pointers + * and their arguments. + * + * @param conn the TCP netconn to setup + */ +static void +setup_tcp(struct netconn *conn) +{ + struct tcp_pcb *pcb; + + pcb = conn->pcb.tcp; + tcp_arg(pcb, conn); + tcp_recv(pcb, recv_tcp); + tcp_sent(pcb, sent_tcp); + tcp_poll(pcb, poll_tcp, 4); + tcp_err(pcb, err_tcp); +} + +/** + * Accept callback function for TCP netconns. + * Allocates a new netconn and posts that to conn->acceptmbox. + * + * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value + */ +static err_t +accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) +{ + struct netconn *newconn; + struct netconn *conn = (struct netconn *)arg; + + LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: newpcb->tate: %s\n", tcp_debug_state_str(newpcb->state))); + + if (!sys_mbox_valid(&conn->acceptmbox)) { + LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: acceptmbox already deleted\n")); + return ERR_VAL; + } + + /* We have to set the callback here even though + * the new socket is unknown. conn->socket is marked as -1. */ + newconn = netconn_alloc(conn->type, conn->callback); + if (newconn == NULL) { + return ERR_MEM; + } + newconn->pcb.tcp = newpcb; + setup_tcp(newconn); + /* no protection: when creating the pcb, the netconn is not yet known + to the application thread */ + newconn->last_err = err; + + if (sys_mbox_trypost(&conn->acceptmbox, newconn) != ERR_OK) { + /* When returning != ERR_OK, the pcb is aborted in tcp_process(), + so do nothing here! */ + newconn->pcb.tcp = NULL; + /* no need to drain since we know the recvmbox is empty. */ + sys_mbox_free(&newconn->recvmbox); + sys_mbox_set_invalid(&newconn->recvmbox); + netconn_free(newconn); + return ERR_MEM; + } else { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Create a new pcb of a specific type. + * Called from do_newconn(). + * + * @param msg the api_msg_msg describing the connection type + * @return msg->conn->err, but the return value is currently ignored + */ +static void +pcb_new(struct api_msg_msg *msg) +{ + LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL); + + /* Allocate a PCB for this connection */ + switch(NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new(msg->msg.n.proto); + if(msg->conn->pcb.raw == NULL) { + msg->err = ERR_MEM; + break; + } + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new(); + if(msg->conn->pcb.udp == NULL) { + msg->err = ERR_MEM; + break; + } +#if LWIP_UDPLITE + if (msg->conn->type==NETCONN_UDPLITE) { + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + } +#endif /* LWIP_UDPLITE */ + if (msg->conn->type==NETCONN_UDPNOCHKSUM) { + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + } + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new(); + if(msg->conn->pcb.tcp == NULL) { + msg->err = ERR_MEM; + break; + } + setup_tcp(msg->conn); + break; +#endif /* LWIP_TCP */ + default: + /* Unsupported netconn type, e.g. protocol disabled */ + msg->err = ERR_VAL; + break; + } +} + +/** + * Create a new pcb of a specific type inside a netconn. + * Called from netconn_new_with_proto_and_callback. + * + * @param msg the api_msg_msg describing the connection type + */ +void +do_newconn(struct api_msg_msg *msg) +{ + msg->err = ERR_OK; + if(msg->conn->pcb.tcp == NULL) { + pcb_new(msg); + } + /* Else? This "new" connection already has a PCB allocated. */ + /* Is this an error condition? Should it be deleted? */ + /* We currently just are happy and return. */ + + TCPIP_APIMSG_ACK(msg); +} + +/** + * Create a new netconn (of a specific type) that has a callback function. + * The corresponding pcb is NOT created! + * + * @param t the type of 'connection' to create (@see enum netconn_type) + * @param proto the IP protocol for RAW IP pcbs + * @param callback a function to call on status changes (RX available, TX'ed) + * @return a newly allocated struct netconn or + * NULL on memory error + */ +struct netconn* +netconn_alloc(enum netconn_type t, netconn_callback callback) +{ + struct netconn *conn; + int size; + + conn = (struct netconn *)memp_malloc(MEMP_NETCONN); + if (conn == NULL) { + return NULL; + } + + conn->last_err = ERR_OK; + conn->type = t; + conn->pcb.tcp = NULL; + +#if (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_UDP_RECVMBOX_SIZE) && \ + (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_TCP_RECVMBOX_SIZE) + size = DEFAULT_RAW_RECVMBOX_SIZE; +#else + switch(NETCONNTYPE_GROUP(t)) { +#if LWIP_RAW + case NETCONN_RAW: + size = DEFAULT_RAW_RECVMBOX_SIZE; + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + size = DEFAULT_UDP_RECVMBOX_SIZE; + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + size = DEFAULT_TCP_RECVMBOX_SIZE; + break; +#endif /* LWIP_TCP */ + default: + LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0); + break; + } +#endif + + if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) { + memp_free(MEMP_NETCONN, conn); + return NULL; + } + if (sys_mbox_new(&conn->recvmbox, size) != ERR_OK) { + sys_sem_free(&conn->op_completed); + memp_free(MEMP_NETCONN, conn); + return NULL; + } + +#if LWIP_TCP + sys_mbox_set_invalid(&conn->acceptmbox); +#endif + conn->state = NETCONN_NONE; +#if LWIP_SOCKET + /* initialize socket to -1 since 0 is a valid socket */ + conn->socket = -1; +#endif /* LWIP_SOCKET */ + conn->callback = callback; +#if LWIP_TCP + conn->current_msg = NULL; + conn->write_offset = 0; +#endif /* LWIP_TCP */ +#if LWIP_SO_RCVTIMEO + conn->recv_timeout = 0; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + conn->recv_bufsize = RECV_BUFSIZE_DEFAULT; + conn->recv_avail = 0; +#endif /* LWIP_SO_RCVBUF */ + conn->flags = 0; + return conn; +} + +/** + * Delete a netconn and all its resources. + * The pcb is NOT freed (since we might not be in the right thread context do this). + * + * @param conn the netconn to free + */ +void +netconn_free(struct netconn *conn) +{ + LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL); + LWIP_ASSERT("recvmbox must be deallocated before calling this function", + !sys_mbox_valid(&conn->recvmbox)); +#if LWIP_TCP + LWIP_ASSERT("acceptmbox must be deallocated before calling this function", + !sys_mbox_valid(&conn->acceptmbox)); +#endif /* LWIP_TCP */ + + sys_sem_free(&conn->op_completed); + sys_sem_set_invalid(&conn->op_completed); + + memp_free(MEMP_NETCONN, conn); +} + +/** + * Delete rcvmbox and acceptmbox of a netconn and free the left-over data in + * these mboxes + * + * @param conn the netconn to free + * @bytes_drained bytes drained from recvmbox + * @accepts_drained pending connections drained from acceptmbox + */ +static void +netconn_drain(struct netconn *conn) +{ + void *mem; +#if LWIP_TCP + struct pbuf *p; +#endif /* LWIP_TCP */ + + /* This runs in tcpip_thread, so we don't need to lock against rx packets */ + + /* Delete and drain the recvmbox. */ + if (sys_mbox_valid(&conn->recvmbox)) { + while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) { +#if LWIP_TCP + if (conn->type == NETCONN_TCP) { + if(mem != NULL) { + p = (struct pbuf*)mem; + /* pcb might be set to NULL already by err_tcp() */ + if (conn->pcb.tcp != NULL) { + tcp_recved(conn->pcb.tcp, p->tot_len); + } + pbuf_free(p); + } + } else +#endif /* LWIP_TCP */ + { + netbuf_delete((struct netbuf *)mem); + } + } + sys_mbox_free(&conn->recvmbox); + sys_mbox_set_invalid(&conn->recvmbox); + } + + /* Delete and drain the acceptmbox. */ +#if LWIP_TCP + if (sys_mbox_valid(&conn->acceptmbox)) { + while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) { + struct netconn *newconn = (struct netconn *)mem; + /* Only tcp pcbs have an acceptmbox, so no need to check conn->type */ + /* pcb might be set to NULL already by err_tcp() */ + if (conn->pcb.tcp != NULL) { + tcp_accepted(conn->pcb.tcp); + } + /* drain recvmbox */ + netconn_drain(newconn); + if (newconn->pcb.tcp != NULL) { + tcp_abort(newconn->pcb.tcp); + newconn->pcb.tcp = NULL; + } + netconn_free(newconn); + } + sys_mbox_free(&conn->acceptmbox); + sys_mbox_set_invalid(&conn->acceptmbox); + } +#endif /* LWIP_TCP */ +} + +#if LWIP_TCP +/** + * Internal helper function to close a TCP netconn: since this sometimes + * doesn't work at the first attempt, this function is called from multiple + * places. + * + * @param conn the TCP netconn to close + */ +static void +do_close_internal(struct netconn *conn) +{ + err_t err; + u8_t shut, shut_rx, shut_tx, close; + + LWIP_ASSERT("invalid conn", (conn != NULL)); + LWIP_ASSERT("this is for tcp netconns only", (conn->type == NETCONN_TCP)); + LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE)); + LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL)); + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + + shut = conn->current_msg->msg.sd.shut; + shut_rx = shut & NETCONN_SHUT_RD; + shut_tx = shut & NETCONN_SHUT_WR; + /* shutting down both ends is the same as closing */ + close = shut == NETCONN_SHUT_RDWR; + + /* Set back some callback pointers */ + if (close) { + tcp_arg(conn->pcb.tcp, NULL); + } + if (conn->pcb.tcp->state == LISTEN) { + tcp_accept(conn->pcb.tcp, NULL); + } else { + /* some callbacks have to be reset if tcp_close is not successful */ + if (shut_rx) { + tcp_recv(conn->pcb.tcp, NULL); + tcp_accept(conn->pcb.tcp, NULL); + } + if (shut_tx) { + tcp_sent(conn->pcb.tcp, NULL); + } + if (close) { + tcp_poll(conn->pcb.tcp, NULL, 4); + tcp_err(conn->pcb.tcp, NULL); + } + } + /* Try to close the connection */ + if (shut == NETCONN_SHUT_RDWR) { + err = tcp_close(conn->pcb.tcp); + } else { + err = tcp_shutdown(conn->pcb.tcp, shut & NETCONN_SHUT_RD, shut & NETCONN_SHUT_WR); + } + if (err == ERR_OK) { + /* Closing succeeded */ + conn->current_msg->err = ERR_OK; + conn->current_msg = NULL; + conn->state = NETCONN_NONE; + /* Set back some callback pointers as conn is going away */ + conn->pcb.tcp = NULL; + /* Trigger select() in socket layer. Make sure everybody notices activity + on the connection, error first! */ + if (close) { + API_EVENT(conn, NETCONN_EVT_ERROR, 0); + } + if (shut_rx) { + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + if (shut_tx) { + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + } + /* wake up the application task */ + sys_sem_signal(&conn->op_completed); + } else { + /* Closing failed, restore some of the callbacks */ + /* Closing of listen pcb will never fail! */ + LWIP_ASSERT("Closing a listen pcb may not fail!", (conn->pcb.tcp->state != LISTEN)); + tcp_sent(conn->pcb.tcp, sent_tcp); + tcp_poll(conn->pcb.tcp, poll_tcp, 4); + tcp_err(conn->pcb.tcp, err_tcp); + tcp_arg(conn->pcb.tcp, conn); + /* don't restore recv callback: we don't want to receive any more data */ + } + /* If closing didn't succeed, we get called again either + from poll_tcp or from sent_tcp */ +} +#endif /* LWIP_TCP */ + +/** + * Delete the pcb inside a netconn. + * Called from netconn_delete. + * + * @param msg the api_msg_msg pointing to the connection + */ +void +do_delconn(struct api_msg_msg *msg) +{ + /* @todo TCP: abort running write/connect? */ + if ((msg->conn->state != NETCONN_NONE) && + (msg->conn->state != NETCONN_LISTEN) && + (msg->conn->state != NETCONN_CONNECT)) { + /* this only happens for TCP netconns */ + LWIP_ASSERT("msg->conn->type == NETCONN_TCP", msg->conn->type == NETCONN_TCP); + msg->err = ERR_INPROGRESS; + } else { + LWIP_ASSERT("blocking connect in progress", + (msg->conn->state != NETCONN_CONNECT) || IN_NONBLOCKING_CONNECT(msg->conn)); + /* Drain and delete mboxes */ + netconn_drain(msg->conn); + + if (msg->conn->pcb.tcp != NULL) { + + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + raw_remove(msg->conn->pcb.raw); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->conn->pcb.udp->recv_arg = NULL; + udp_remove(msg->conn->pcb.udp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && + msg->conn->write_offset == 0); + msg->conn->state = NETCONN_CLOSE; + msg->msg.sd.shut = NETCONN_SHUT_RDWR; + msg->conn->current_msg = msg; + do_close_internal(msg->conn); + /* API_EVENT is called inside do_close_internal, before releasing + the application thread, so we can return at this point! */ + return; +#endif /* LWIP_TCP */ + default: + break; + } + msg->conn->pcb.tcp = NULL; + } + /* tcp netconns don't come here! */ + + /* @todo: this lets select make the socket readable and writable, + which is wrong! errfd instead? */ + API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0); + API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0); + } + if (sys_sem_valid(&msg->conn->op_completed)) { + sys_sem_signal(&msg->conn->op_completed); + } +} + +/** + * Bind a pcb contained in a netconn + * Called from netconn_bind. + * + * @param msg the api_msg_msg pointing to the connection and containing + * the IP address and port to bind to + */ +void +do_bind(struct api_msg_msg *msg) +{ + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + msg->err = ERR_VAL; + if (msg->conn->pcb.tcp != NULL) { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->err = raw_bind(msg->conn->pcb.raw, msg->msg.bc.ipaddr); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->err = tcp_bind(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port); + break; +#endif /* LWIP_TCP */ + default: + break; + } + } + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * TCP callback function if a connection (opened by tcp_connect/do_connect) has + * been established (or reset by the remote host). + * + * @see tcp.h (struct tcp_pcb.connected) for parameters and return values + */ +static err_t +do_connected(void *arg, struct tcp_pcb *pcb, err_t err) +{ + struct netconn *conn; + int was_blocking; + + LWIP_UNUSED_ARG(pcb); + + conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + + LWIP_ASSERT("conn->state == NETCONN_CONNECT", conn->state == NETCONN_CONNECT); + LWIP_ASSERT("(conn->current_msg != NULL) || conn->in_non_blocking_connect", + (conn->current_msg != NULL) || IN_NONBLOCKING_CONNECT(conn)); + + if (conn->current_msg != NULL) { + conn->current_msg->err = err; + } + if ((conn->type == NETCONN_TCP) && (err == ERR_OK)) { + setup_tcp(conn); + } + was_blocking = !IN_NONBLOCKING_CONNECT(conn); + SET_NONBLOCKING_CONNECT(conn, 0); + conn->current_msg = NULL; + conn->state = NETCONN_NONE; + if (!was_blocking) { + NETCONN_SET_SAFE_ERR(conn, ERR_OK); + } + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + + if (was_blocking) { + sys_sem_signal(&conn->op_completed); + } + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Connect a pcb contained inside a netconn + * Called from netconn_connect. + * + * @param msg the api_msg_msg pointing to the connection and containing + * the IP address and port to connect to + */ +void +do_connect(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp == NULL) { + /* This may happen when calling netconn_connect() a second time */ + msg->err = ERR_CLSD; + } else { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->err = raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->err = udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + /* Prevent connect while doing any other action. */ + if (msg->conn->state != NETCONN_NONE) { + msg->err = ERR_ISCONN; + } else { + setup_tcp(msg->conn); + msg->err = tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, + msg->msg.bc.port, do_connected); + if (msg->err == ERR_OK) { + u8_t non_blocking = netconn_is_nonblocking(msg->conn); + msg->conn->state = NETCONN_CONNECT; + SET_NONBLOCKING_CONNECT(msg->conn, non_blocking); + if (non_blocking) { + msg->err = ERR_INPROGRESS; + } else { + msg->conn->current_msg = msg; + /* sys_sem_signal() is called from do_connected (or err_tcp()), + * when the connection is established! */ + return; + } + } + } + break; +#endif /* LWIP_TCP */ + default: + LWIP_ERROR("Invalid netconn type", 0, do{ msg->err = ERR_VAL; }while(0)); + break; + } + } + sys_sem_signal(&msg->conn->op_completed); +} + +/** + * Connect a pcb contained inside a netconn + * Only used for UDP netconns. + * Called from netconn_disconnect. + * + * @param msg the api_msg_msg pointing to the connection to disconnect + */ +void +do_disconnect(struct api_msg_msg *msg) +{ +#if LWIP_UDP + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { + udp_disconnect(msg->conn->pcb.udp); + msg->err = ERR_OK; + } else +#endif /* LWIP_UDP */ + { + msg->err = ERR_VAL; + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * Set a TCP pcb contained in a netconn into listen mode + * Called from netconn_listen. + * + * @param msg the api_msg_msg pointing to the connection + */ +void +do_listen(struct api_msg_msg *msg) +{ + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + msg->err = ERR_CONN; + if (msg->conn->pcb.tcp != NULL) { + if (msg->conn->type == NETCONN_TCP) { + if (msg->conn->state == NETCONN_NONE) { +#if TCP_LISTEN_BACKLOG + struct tcp_pcb* lpcb = tcp_listen_with_backlog(msg->conn->pcb.tcp, msg->msg.lb.backlog); +#else /* TCP_LISTEN_BACKLOG */ + struct tcp_pcb* lpcb = tcp_listen(msg->conn->pcb.tcp); +#endif /* TCP_LISTEN_BACKLOG */ + if (lpcb == NULL) { + /* in this case, the old pcb is still allocated */ + msg->err = ERR_MEM; + } else { + /* delete the recvmbox and allocate the acceptmbox */ + if (sys_mbox_valid(&msg->conn->recvmbox)) { + /** @todo: should we drain the recvmbox here? */ + sys_mbox_free(&msg->conn->recvmbox); + sys_mbox_set_invalid(&msg->conn->recvmbox); + } + msg->err = ERR_OK; + if (!sys_mbox_valid(&msg->conn->acceptmbox)) { + msg->err = sys_mbox_new(&msg->conn->acceptmbox, DEFAULT_ACCEPTMBOX_SIZE); + } + if (msg->err == ERR_OK) { + msg->conn->state = NETCONN_LISTEN; + msg->conn->pcb.tcp = lpcb; + tcp_arg(msg->conn->pcb.tcp, msg->conn); + tcp_accept(msg->conn->pcb.tcp, accept_function); + } else { + /* since the old pcb is already deallocated, free lpcb now */ + tcp_close(lpcb); + msg->conn->pcb.tcp = NULL; + } + } + } + } + } + } + TCPIP_APIMSG_ACK(msg); +} +#endif /* LWIP_TCP */ + +/** + * Send some data on a RAW or UDP pcb contained in a netconn + * Called from netconn_send + * + * @param msg the api_msg_msg pointing to the connection + */ +void +do_send(struct api_msg_msg *msg) +{ + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + msg->err = ERR_CONN; + if (msg->conn->pcb.tcp != NULL) { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + if (ip_addr_isany(&msg->msg.b->addr)) { + msg->err = raw_send(msg->conn->pcb.raw, msg->msg.b->p); + } else { + msg->err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, &msg->msg.b->addr); + } + break; +#endif +#if LWIP_UDP + case NETCONN_UDP: +#if LWIP_CHECKSUM_ON_COPY + if (ip_addr_isany(&msg->msg.b->addr)) { + msg->err = udp_send_chksum(msg->conn->pcb.udp, msg->msg.b->p, + msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); + } else { + msg->err = udp_sendto_chksum(msg->conn->pcb.udp, msg->msg.b->p, + &msg->msg.b->addr, msg->msg.b->port, + msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); + } +#else /* LWIP_CHECKSUM_ON_COPY */ + if (ip_addr_isany(&msg->msg.b->addr)) { + msg->err = udp_send(msg->conn->pcb.udp, msg->msg.b->p); + } else { + msg->err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, &msg->msg.b->addr, msg->msg.b->port); + } +#endif /* LWIP_CHECKSUM_ON_COPY */ + break; +#endif /* LWIP_UDP */ + default: + break; + } + } + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * Indicate data has been received from a TCP pcb contained in a netconn + * Called from netconn_recv + * + * @param msg the api_msg_msg pointing to the connection + */ +void +do_recv(struct api_msg_msg *msg) +{ + msg->err = ERR_OK; + if (msg->conn->pcb.tcp != NULL) { + if (msg->conn->type == NETCONN_TCP) { +#if TCP_LISTEN_BACKLOG + if (msg->conn->pcb.tcp->state == LISTEN) { + tcp_accepted(msg->conn->pcb.tcp); + } else +#endif /* TCP_LISTEN_BACKLOG */ + { + u32_t remaining = msg->msg.r.len; + do { + u16_t recved = (remaining > 0xffff) ? 0xffff : (u16_t)remaining; + tcp_recved(msg->conn->pcb.tcp, recved); + remaining -= recved; + }while(remaining != 0); + } + } + } + TCPIP_APIMSG_ACK(msg); +} + +/** + * See if more data needs to be written from a previous call to netconn_write. + * Called initially from do_write. If the first call can't send all data + * (because of low memory or empty send-buffer), this function is called again + * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the + * blocking application thread (waiting in netconn_write) is released. + * + * @param conn netconn (that is currently in state NETCONN_WRITE) to process + * @return ERR_OK + * ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished + */ +static err_t +do_writemore(struct netconn *conn) +{ + err_t err = ERR_OK; + void *dataptr; + u16_t len, available; + u8_t write_finished = 0; + size_t diff; + u8_t dontblock = netconn_is_nonblocking(conn) || + (conn->current_msg->msg.w.apiflags & NETCONN_DONTBLOCK); + u8_t apiflags = conn->current_msg->msg.w.apiflags; + + LWIP_ASSERT("conn != NULL", conn != NULL); + LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE)); + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL); + LWIP_ASSERT("conn->write_offset < conn->current_msg->msg.w.len", + conn->write_offset < conn->current_msg->msg.w.len); + + dataptr = (u8_t*)conn->current_msg->msg.w.dataptr + conn->write_offset; + diff = conn->current_msg->msg.w.len - conn->write_offset; + if (diff > 0xffffUL) { /* max_u16_t */ + len = 0xffff; +#if LWIP_TCPIP_CORE_LOCKING + conn->flags |= NETCONN_FLAG_WRITE_DELAYED; +#endif + apiflags |= TCP_WRITE_FLAG_MORE; + } else { + len = (u16_t)diff; + } + available = tcp_sndbuf(conn->pcb.tcp); + if (available < len) { + /* don't try to write more than sendbuf */ + len = available; +#if LWIP_TCPIP_CORE_LOCKING + conn->flags |= NETCONN_FLAG_WRITE_DELAYED; +#endif + apiflags |= TCP_WRITE_FLAG_MORE; + } + if (dontblock && (len < conn->current_msg->msg.w.len)) { + /* failed to send all data at once -> nonblocking write not possible */ + err = ERR_MEM; + } + if (err == ERR_OK) { + LWIP_ASSERT("do_writemore: invalid length!", ((conn->write_offset + len) <= conn->current_msg->msg.w.len)); + err = tcp_write(conn->pcb.tcp, dataptr, len, apiflags); + } + if (dontblock && (err == ERR_MEM)) { + /* nonblocking write failed */ + write_finished = 1; + err = ERR_WOULDBLOCK; + /* let poll_tcp check writable space to mark the pcb + writable again */ + conn->flags |= NETCONN_FLAG_CHECK_WRITESPACE; + /* let select mark this pcb as non-writable. */ + API_EVENT(conn, NETCONN_EVT_SENDMINUS, len); + } else { + /* if OK or memory error, check available space */ + if (((err == ERR_OK) || (err == ERR_MEM)) && + ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) || + (tcp_sndqueuelen(conn->pcb.tcp) >= TCP_SNDQUEUELOWAT))) { + /* The queued byte- or pbuf-count exceeds the configured low-water limit, + let select mark this pcb as non-writable. */ + API_EVENT(conn, NETCONN_EVT_SENDMINUS, len); + } + + if (err == ERR_OK) { + conn->write_offset += len; + if (conn->write_offset == conn->current_msg->msg.w.len) { + /* everything was written */ + write_finished = 1; + conn->write_offset = 0; + } + tcp_output(conn->pcb.tcp); + } else if (err == ERR_MEM) { + /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called + we do NOT return to the application thread, since ERR_MEM is + only a temporary error! */ + + /* tcp_write returned ERR_MEM, try tcp_output anyway */ + tcp_output(conn->pcb.tcp); + + #if LWIP_TCPIP_CORE_LOCKING + conn->flags |= NETCONN_FLAG_WRITE_DELAYED; + #endif + } else { + /* On errors != ERR_MEM, we don't try writing any more but return + the error to the application thread. */ + write_finished = 1; + } + } + + if (write_finished) { + /* everything was written: set back connection state + and back to application task */ + conn->current_msg->err = err; + conn->current_msg = NULL; + conn->state = NETCONN_NONE; +#if LWIP_TCPIP_CORE_LOCKING + if ((conn->flags & NETCONN_FLAG_WRITE_DELAYED) != 0) +#endif + { + sys_sem_signal(&conn->op_completed); + } + } +#if LWIP_TCPIP_CORE_LOCKING + else + return ERR_MEM; +#endif + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Send some data on a TCP pcb contained in a netconn + * Called from netconn_write + * + * @param msg the api_msg_msg pointing to the connection + */ +void +do_write(struct api_msg_msg *msg) +{ + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + if (msg->conn->type == NETCONN_TCP) { +#if LWIP_TCP + if (msg->conn->state != NETCONN_NONE) { + /* netconn is connecting, closing or in blocking write */ + msg->err = ERR_INPROGRESS; + } else if (msg->conn->pcb.tcp != NULL) { + msg->conn->state = NETCONN_WRITE; + /* set all the variables used by do_writemore */ + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && + msg->conn->write_offset == 0); + LWIP_ASSERT("msg->msg.w.len != 0", msg->msg.w.len != 0); + msg->conn->current_msg = msg; + msg->conn->write_offset = 0; +#if LWIP_TCPIP_CORE_LOCKING + msg->conn->flags &= ~NETCONN_FLAG_WRITE_DELAYED; + if (do_writemore(msg->conn) != ERR_OK) { + LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(&msg->conn->op_completed, 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + do_writemore(msg->conn); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* for both cases: if do_writemore was called, don't ACK the APIMSG + since do_writemore ACKs it! */ + return; + } else { + msg->err = ERR_CONN; + } +#else /* LWIP_TCP */ + msg->err = ERR_VAL; +#endif /* LWIP_TCP */ +#if (LWIP_UDP || LWIP_RAW) + } else { + msg->err = ERR_VAL; +#endif /* (LWIP_UDP || LWIP_RAW) */ + } + } + TCPIP_APIMSG_ACK(msg); +} + +/** + * Return a connection's local or remote address + * Called from netconn_getaddr + * + * @param msg the api_msg_msg pointing to the connection + */ +void +do_getaddr(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.ip != NULL) { + *(msg->msg.ad.ipaddr) = (msg->msg.ad.local ? msg->conn->pcb.ip->local_ip : + msg->conn->pcb.ip->remote_ip); + + msg->err = ERR_OK; + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + if (msg->msg.ad.local) { + *(msg->msg.ad.port) = msg->conn->pcb.raw->protocol; + } else { + /* return an error as connecting is only a helper for upper layers */ + msg->err = ERR_CONN; + } + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + if (msg->msg.ad.local) { + *(msg->msg.ad.port) = msg->conn->pcb.udp->local_port; + } else { + if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) { + msg->err = ERR_CONN; + } else { + *(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port; + } + } + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + *(msg->msg.ad.port) = (msg->msg.ad.local?msg->conn->pcb.tcp->local_port:msg->conn->pcb.tcp->remote_port); + break; +#endif /* LWIP_TCP */ + default: + LWIP_ASSERT("invalid netconn_type", 0); + break; + } + } else { + msg->err = ERR_CONN; + } + TCPIP_APIMSG_ACK(msg); +} + +/** + * Close a TCP pcb contained in a netconn + * Called from netconn_close + * + * @param msg the api_msg_msg pointing to the connection + */ +void +do_close(struct api_msg_msg *msg) +{ +#if LWIP_TCP + /* @todo: abort running write/connect? */ + if ((msg->conn->state != NETCONN_NONE) && (msg->conn->state != NETCONN_LISTEN)) { + /* this only happens for TCP netconns */ + LWIP_ASSERT("msg->conn->type == NETCONN_TCP", msg->conn->type == NETCONN_TCP); + msg->err = ERR_INPROGRESS; + } else if ((msg->conn->pcb.tcp != NULL) && (msg->conn->type == NETCONN_TCP)) { + if ((msg->msg.sd.shut != NETCONN_SHUT_RDWR) && (msg->conn->state == NETCONN_LISTEN)) { + /* LISTEN doesn't support half shutdown */ + msg->err = ERR_CONN; + } else { + if (msg->msg.sd.shut & NETCONN_SHUT_RD) { + /* Drain and delete mboxes */ + netconn_drain(msg->conn); + } + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && + msg->conn->write_offset == 0); + msg->conn->state = NETCONN_CLOSE; + msg->conn->current_msg = msg; + do_close_internal(msg->conn); + /* for tcp netconns, do_close_internal ACKs the message */ + return; + } + } else +#endif /* LWIP_TCP */ + { + msg->err = ERR_VAL; + } + sys_sem_signal(&msg->conn->op_completed); +} + +#if LWIP_IGMP +/** + * Join multicast groups for UDP netconns. + * Called from netconn_join_leave_group + * + * @param msg the api_msg_msg pointing to the connection + */ +void +do_join_leave_group(struct api_msg_msg *msg) +{ + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { +#if LWIP_UDP + if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { + msg->err = igmp_joingroup(msg->msg.jl.netif_addr, msg->msg.jl.multiaddr); + } else { + msg->err = igmp_leavegroup(msg->msg.jl.netif_addr, msg->msg.jl.multiaddr); + } +#endif /* LWIP_UDP */ +#if (LWIP_TCP || LWIP_RAW) + } else { + msg->err = ERR_VAL; +#endif /* (LWIP_TCP || LWIP_RAW) */ + } + } else { + msg->err = ERR_CONN; + } + } + TCPIP_APIMSG_ACK(msg); +} +#endif /* LWIP_IGMP */ + +#if LWIP_DNS +/** + * Callback function that is called when DNS name is resolved + * (or on timeout). A waiting application thread is waked up by + * signaling the semaphore. + */ +static void +do_dns_found(const char *name, ip_addr_t *ipaddr, void *arg) +{ + struct dns_api_msg *msg = (struct dns_api_msg*)arg; + + LWIP_ASSERT("DNS response for wrong host name", strcmp(msg->name, name) == 0); + LWIP_UNUSED_ARG(name); + + if (ipaddr == NULL) { + /* timeout or memory error */ + *msg->err = ERR_VAL; + } else { + /* address was resolved */ + *msg->err = ERR_OK; + *msg->addr = *ipaddr; + } + /* wake up the application task waiting in netconn_gethostbyname */ + sys_sem_signal(msg->sem); +} + +/** + * Execute a DNS query + * Called from netconn_gethostbyname + * + * @param arg the dns_api_msg pointing to the query + */ +void +do_gethostbyname(void *arg) +{ + struct dns_api_msg *msg = (struct dns_api_msg*)arg; + + *msg->err = dns_gethostbyname(msg->name, msg->addr, do_dns_found, msg); + if (*msg->err != ERR_INPROGRESS) { + /* on error or immediate success, wake up the application + * task waiting in netconn_gethostbyname */ + sys_sem_signal(msg->sem); + } +} +#endif /* LWIP_DNS */ + +#endif /* LWIP_NETCONN */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/err.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/err.c new file mode 100644 index 0000000..92fa8b7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/err.c @@ -0,0 +1,75 @@ +/** + * @file + * Error Management module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/err.h" + +#ifdef LWIP_DEBUG + +static const char *err_strerr[] = { + "Ok.", /* ERR_OK 0 */ + "Out of memory error.", /* ERR_MEM -1 */ + "Buffer error.", /* ERR_BUF -2 */ + "Timeout.", /* ERR_TIMEOUT -3 */ + "Routing problem.", /* ERR_RTE -4 */ + "Operation in progress.", /* ERR_INPROGRESS -5 */ + "Illegal value.", /* ERR_VAL -6 */ + "Operation would block.", /* ERR_WOULDBLOCK -7 */ + "Address in use.", /* ERR_USE -8 */ + "Already connected.", /* ERR_ISCONN -9 */ + "Connection aborted.", /* ERR_ABRT -10 */ + "Connection reset.", /* ERR_RST -11 */ + "Connection closed.", /* ERR_CLSD -12 */ + "Not connected.", /* ERR_CONN -13 */ + "Illegal argument.", /* ERR_ARG -14 */ + "Low-level netif error.", /* ERR_IF -15 */ +}; + +/** + * Convert an lwip internal error to a string representation. + * + * @param err an lwip internal err_t + * @return a string representation for err + */ +const char * +lwip_strerr(err_t err) +{ + return err_strerr[-err]; + +} + +#endif /* LWIP_DEBUG */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/netbuf.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/netbuf.c new file mode 100644 index 0000000..9390c9e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/netbuf.c @@ -0,0 +1,245 @@ +/** + * @file + * Network buffer management + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netbuf.h" +#include "lwip/memp.h" + +#include + +/** + * Create (allocate) and initialize a new netbuf. + * The netbuf doesn't yet contain a packet buffer! + * + * @return a pointer to a new netbuf + * NULL on lack of memory + */ +struct +netbuf *netbuf_new(void) +{ + struct netbuf *buf; + + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf != NULL) { + buf->p = NULL; + buf->ptr = NULL; + ip_addr_set_any(&buf->addr); + buf->port = 0; +#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY +#if LWIP_CHECKSUM_ON_COPY + buf->flags = 0; +#endif /* LWIP_CHECKSUM_ON_COPY */ + buf->toport_chksum = 0; +#if LWIP_NETBUF_RECVINFO + ip_addr_set_any(&buf->toaddr); +#endif /* LWIP_NETBUF_RECVINFO */ +#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */ + return buf; + } else { + return NULL; + } +} + +/** + * Deallocate a netbuf allocated by netbuf_new(). + * + * @param buf pointer to a netbuf allocated by netbuf_new() + */ +void +netbuf_delete(struct netbuf *buf) +{ + if (buf != NULL) { + if (buf->p != NULL) { + pbuf_free(buf->p); + buf->p = buf->ptr = NULL; + } + memp_free(MEMP_NETBUF, buf); + } +} + +/** + * Allocate memory for a packet buffer for a given netbuf. + * + * @param buf the netbuf for which to allocate a packet buffer + * @param size the size of the packet buffer to allocate + * @return pointer to the allocated memory + * NULL if no memory could be allocated + */ +void * +netbuf_alloc(struct netbuf *buf, u16_t size) +{ + LWIP_ERROR("netbuf_alloc: invalid buf", (buf != NULL), return NULL;); + + /* Deallocate any previously allocated memory. */ + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM); + if (buf->p == NULL) { + return NULL; + } + LWIP_ASSERT("check that first pbuf can hold size", + (buf->p->len >= size)); + buf->ptr = buf->p; + return buf->p->payload; +} + +/** + * Free the packet buffer included in a netbuf + * + * @param buf pointer to the netbuf which contains the packet buffer to free + */ +void +netbuf_free(struct netbuf *buf) +{ + LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;); + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = buf->ptr = NULL; +} + +/** + * Let a netbuf reference existing (non-volatile) data. + * + * @param buf netbuf which should reference the data + * @param dataptr pointer to the data to reference + * @param size size of the data + * @return ERR_OK if data is referenced + * ERR_MEM if data couldn't be referenced due to lack of memory + */ +err_t +netbuf_ref(struct netbuf *buf, const void *dataptr, u16_t size) +{ + LWIP_ERROR("netbuf_ref: invalid buf", (buf != NULL), return ERR_ARG;); + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); + if (buf->p == NULL) { + buf->ptr = NULL; + return ERR_MEM; + } + buf->p->payload = (void*)dataptr; + buf->p->len = buf->p->tot_len = size; + buf->ptr = buf->p; + return ERR_OK; +} + +/** + * Chain one netbuf to another (@see pbuf_chain) + * + * @param head the first netbuf + * @param tail netbuf to chain after head, freed by this function, may not be reference after returning + */ +void +netbuf_chain(struct netbuf *head, struct netbuf *tail) +{ + LWIP_ERROR("netbuf_ref: invalid head", (head != NULL), return;); + LWIP_ERROR("netbuf_chain: invalid tail", (tail != NULL), return;); + pbuf_cat(head->p, tail->p); + head->ptr = head->p; + memp_free(MEMP_NETBUF, tail); +} + +/** + * Get the data pointer and length of the data inside a netbuf. + * + * @param buf netbuf to get the data from + * @param dataptr pointer to a void pointer where to store the data pointer + * @param len pointer to an u16_t where the length of the data is stored + * @return ERR_OK if the information was retreived, + * ERR_BUF on error. + */ +err_t +netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len) +{ + LWIP_ERROR("netbuf_data: invalid buf", (buf != NULL), return ERR_ARG;); + LWIP_ERROR("netbuf_data: invalid dataptr", (dataptr != NULL), return ERR_ARG;); + LWIP_ERROR("netbuf_data: invalid len", (len != NULL), return ERR_ARG;); + + if (buf->ptr == NULL) { + return ERR_BUF; + } + *dataptr = buf->ptr->payload; + *len = buf->ptr->len; + return ERR_OK; +} + +/** + * Move the current data pointer of a packet buffer contained in a netbuf + * to the next part. + * The packet buffer itself is not modified. + * + * @param buf the netbuf to modify + * @return -1 if there is no next part + * 1 if moved to the next part but now there is no next part + * 0 if moved to the next part and there are still more parts + */ +s8_t +netbuf_next(struct netbuf *buf) +{ + LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return -1;); + if (buf->ptr->next == NULL) { + return -1; + } + buf->ptr = buf->ptr->next; + if (buf->ptr->next == NULL) { + return 1; + } + return 0; +} + +/** + * Move the current data pointer of a packet buffer contained in a netbuf + * to the beginning of the packet. + * The packet buffer itself is not modified. + * + * @param buf the netbuf to modify + */ +void +netbuf_first(struct netbuf *buf) +{ + LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;); + buf->ptr = buf->p; +} + +#endif /* LWIP_NETCONN */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/netdb.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/netdb.c new file mode 100644 index 0000000..a7e4e06 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/netdb.c @@ -0,0 +1,352 @@ +/** + * @file + * API functions for name resolving + * + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "lwip/netdb.h" + +#if LWIP_DNS && LWIP_SOCKET + +#include "lwip/err.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/ip_addr.h" +#include "lwip/api.h" +#include "lwip/dns.h" + +#include +#include + +/** helper struct for gethostbyname_r to access the char* buffer */ +struct gethostbyname_r_helper { + ip_addr_t *addrs; + ip_addr_t addr; + char *aliases; +}; + +/** h_errno is exported in netdb.h for access by applications. */ +#if LWIP_DNS_API_DECLARE_H_ERRNO +int h_errno; +#endif /* LWIP_DNS_API_DECLARE_H_ERRNO */ + +/** define "hostent" variables storage: 0 if we use a static (but unprotected) + * set of variables for lwip_gethostbyname, 1 if we use a local storage */ +#ifndef LWIP_DNS_API_HOSTENT_STORAGE +#define LWIP_DNS_API_HOSTENT_STORAGE 0 +#endif + +/** define "hostent" variables storage */ +#if LWIP_DNS_API_HOSTENT_STORAGE +#define HOSTENT_STORAGE +#else +#define HOSTENT_STORAGE static +#endif /* LWIP_DNS_API_STATIC_HOSTENT */ + +/** + * Returns an entry containing addresses of address family AF_INET + * for the host with name name. + * Due to dns_gethostbyname limitations, only one address is returned. + * + * @param name the hostname to resolve + * @return an entry containing addresses of address family AF_INET + * for the host with name name + */ +struct hostent* +lwip_gethostbyname(const char *name) +{ + err_t err; + ip_addr_t addr; + + /* buffer variables for lwip_gethostbyname() */ + HOSTENT_STORAGE struct hostent s_hostent; + HOSTENT_STORAGE char *s_aliases; + HOSTENT_STORAGE ip_addr_t s_hostent_addr; + HOSTENT_STORAGE ip_addr_t *s_phostent_addr[2]; + + /* query host IP address */ + err = netconn_gethostbyname(name, &addr); + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err)); + h_errno = HOST_NOT_FOUND; + return NULL; + } + + /* fill hostent */ + s_hostent_addr = addr; + s_phostent_addr[0] = &s_hostent_addr; + s_phostent_addr[1] = NULL; + s_hostent.h_name = (char*)name; + s_hostent.h_aliases = &s_aliases; + s_hostent.h_addrtype = AF_INET; + s_hostent.h_length = sizeof(ip_addr_t); + s_hostent.h_addr_list = (char**)&s_phostent_addr; + +#if DNS_DEBUG + /* dump hostent */ + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_name == %s\n", s_hostent.h_name)); + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases == %p\n", s_hostent.h_aliases)); + if (s_hostent.h_aliases != NULL) { + u8_t idx; + for ( idx=0; s_hostent.h_aliases[idx]; idx++) { + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases[%i]-> == %p\n", idx, s_hostent.h_aliases[idx])); + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases[%i]-> == %s\n", idx, s_hostent.h_aliases[idx])); + } + } + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addrtype == %d\n", s_hostent.h_addrtype)); + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_length == %d\n", s_hostent.h_length)); + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list == %p\n", s_hostent.h_addr_list)); + if (s_hostent.h_addr_list != NULL) { + u8_t idx; + for ( idx=0; s_hostent.h_addr_list[idx]; idx++) { + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i] == %p\n", idx, s_hostent.h_addr_list[idx])); + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]-> == %s\n", idx, ip_ntoa((ip_addr_t*)s_hostent.h_addr_list[idx]))); + } + } +#endif /* DNS_DEBUG */ + +#if LWIP_DNS_API_HOSTENT_STORAGE + /* this function should return the "per-thread" hostent after copy from s_hostent */ + return sys_thread_hostent(&s_hostent); +#else + return &s_hostent; +#endif /* LWIP_DNS_API_HOSTENT_STORAGE */ +} + +/** + * Thread-safe variant of lwip_gethostbyname: instead of using a static + * buffer, this function takes buffer and errno pointers as arguments + * and uses these for the result. + * + * @param name the hostname to resolve + * @param ret pre-allocated struct where to store the result + * @param buf pre-allocated buffer where to store additional data + * @param buflen the size of buf + * @param result pointer to a hostent pointer that is set to ret on success + * and set to zero on error + * @param h_errnop pointer to an int where to store errors (instead of modifying + * the global h_errno) + * @return 0 on success, non-zero on error, additional error information + * is stored in *h_errnop instead of h_errno to be thread-safe + */ +int +lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf, + size_t buflen, struct hostent **result, int *h_errnop) +{ + err_t err; + struct gethostbyname_r_helper *h; + char *hostname; + size_t namelen; + int lh_errno; + + if (h_errnop == NULL) { + /* ensure h_errnop is never NULL */ + h_errnop = &lh_errno; + } + + if (result == NULL) { + /* not all arguments given */ + *h_errnop = EINVAL; + return -1; + } + /* first thing to do: set *result to nothing */ + *result = NULL; + if ((name == NULL) || (ret == NULL) || (buf == 0)) { + /* not all arguments given */ + *h_errnop = EINVAL; + return -1; + } + + namelen = strlen(name); + if (buflen < (sizeof(struct gethostbyname_r_helper) + namelen + 1 + (MEM_ALIGNMENT - 1))) { + /* buf can't hold the data needed + a copy of name */ + *h_errnop = ERANGE; + return -1; + } + + h = (struct gethostbyname_r_helper*)LWIP_MEM_ALIGN(buf); + hostname = ((char*)h) + sizeof(struct gethostbyname_r_helper); + + /* query host IP address */ + err = netconn_gethostbyname(name, &(h->addr)); + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err)); + *h_errnop = ENSRNOTFOUND; + return -1; + } + + /* copy the hostname into buf */ + MEMCPY(hostname, name, namelen); + hostname[namelen] = 0; + + /* fill hostent */ + h->addrs = &(h->addr); + h->aliases = NULL; + ret->h_name = (char*)hostname; + ret->h_aliases = &(h->aliases); + ret->h_addrtype = AF_INET; + ret->h_length = sizeof(ip_addr_t); + ret->h_addr_list = (char**)&(h->addrs); + + /* set result != NULL */ + *result = ret; + + /* return success */ + return 0; +} + +/** + * Frees one or more addrinfo structures returned by getaddrinfo(), along with + * any additional storage associated with those structures. If the ai_next field + * of the structure is not null, the entire list of structures is freed. + * + * @param ai struct addrinfo to free + */ +void +lwip_freeaddrinfo(struct addrinfo *ai) +{ + struct addrinfo *next; + + while (ai != NULL) { + next = ai->ai_next; + memp_free(MEMP_NETDB, ai); + ai = next; + } +} + +/** + * Translates the name of a service location (for example, a host name) and/or + * a service name and returns a set of socket addresses and associated + * information to be used in creating a socket with which to address the + * specified service. + * Memory for the result is allocated internally and must be freed by calling + * lwip_freeaddrinfo()! + * + * Due to a limitation in dns_gethostbyname, only the first address of a + * host is returned. + * Also, service names are not supported (only port numbers)! + * + * @param nodename descriptive name or address string of the host + * (may be NULL -> local address) + * @param servname port number as string of NULL + * @param hints structure containing input values that set socktype and protocol + * @param res pointer to a pointer where to store the result (set to NULL on failure) + * @return 0 on success, non-zero on failure + */ +int +lwip_getaddrinfo(const char *nodename, const char *servname, + const struct addrinfo *hints, struct addrinfo **res) +{ + err_t err; + ip_addr_t addr; + struct addrinfo *ai; + struct sockaddr_in *sa = NULL; + int port_nr = 0; + size_t total_size; + size_t namelen = 0; + + if (res == NULL) { + return EAI_FAIL; + } + *res = NULL; + if ((nodename == NULL) && (servname == NULL)) { + return EAI_NONAME; + } + + if (servname != NULL) { + /* service name specified: convert to port number + * @todo?: currently, only ASCII integers (port numbers) are supported! */ + port_nr = atoi(servname); + if ((port_nr <= 0) || (port_nr > 0xffff)) { + return EAI_SERVICE; + } + } + + if (nodename != NULL) { + /* service location specified, try to resolve */ + err = netconn_gethostbyname(nodename, &addr); + if (err != ERR_OK) { + return EAI_FAIL; + } + } else { + /* service location specified, use loopback address */ + ip_addr_set_loopback(&addr); + } + + total_size = sizeof(struct addrinfo) + sizeof(struct sockaddr_in); + if (nodename != NULL) { + namelen = strlen(nodename); + LWIP_ASSERT("namelen is too long", (namelen + 1) <= (mem_size_t)-1); + total_size += namelen + 1; + } + /* If this fails, please report to lwip-devel! :-) */ + LWIP_ASSERT("total_size <= NETDB_ELEM_SIZE: please report this!", + total_size <= NETDB_ELEM_SIZE); + ai = (struct addrinfo *)memp_malloc(MEMP_NETDB); + if (ai == NULL) { + goto memerr; + } + memset(ai, 0, total_size); + sa = (struct sockaddr_in*)((u8_t*)ai + sizeof(struct addrinfo)); + /* set up sockaddr */ + inet_addr_from_ipaddr(&sa->sin_addr, &addr); + sa->sin_family = AF_INET; + sa->sin_len = sizeof(struct sockaddr_in); + sa->sin_port = htons((u16_t)port_nr); + + /* set up addrinfo */ + ai->ai_family = AF_INET; + if (hints != NULL) { + /* copy socktype & protocol from hints if specified */ + ai->ai_socktype = hints->ai_socktype; + ai->ai_protocol = hints->ai_protocol; + } + if (nodename != NULL) { + /* copy nodename to canonname if specified */ + ai->ai_canonname = ((char*)ai + sizeof(struct addrinfo) + sizeof(struct sockaddr_in)); + MEMCPY(ai->ai_canonname, nodename, namelen); + ai->ai_canonname[namelen] = 0; + } + ai->ai_addrlen = sizeof(struct sockaddr_in); + ai->ai_addr = (struct sockaddr*)sa; + + *res = ai; + + return 0; +memerr: + if (ai != NULL) { + memp_free(MEMP_NETDB, ai); + } + return EAI_MEMORY; +} + +#endif /* LWIP_DNS && LWIP_SOCKET */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/netifapi.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/netifapi.c new file mode 100644 index 0000000..43e4720 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/netifapi.c @@ -0,0 +1,160 @@ +/** + * @file + * Network Interface Sequential API module + * + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/opt.h" + +#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netifapi.h" +#include "lwip/tcpip.h" + +/** + * Call netif_add() inside the tcpip_thread context. + */ +void +do_netifapi_netif_add(struct netifapi_msg_msg *msg) +{ + if (!netif_add( msg->netif, + msg->msg.add.ipaddr, + msg->msg.add.netmask, + msg->msg.add.gw, + msg->msg.add.state, + msg->msg.add.init, + msg->msg.add.input)) { + msg->err = ERR_IF; + } else { + msg->err = ERR_OK; + } + TCPIP_NETIFAPI_ACK(msg); +} + +/** + * Call netif_set_addr() inside the tcpip_thread context. + */ +void +do_netifapi_netif_set_addr(struct netifapi_msg_msg *msg) +{ + netif_set_addr( msg->netif, + msg->msg.add.ipaddr, + msg->msg.add.netmask, + msg->msg.add.gw); + msg->err = ERR_OK; + TCPIP_NETIFAPI_ACK(msg); +} + +/** + * Call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) inside the + * tcpip_thread context. + */ +void +do_netifapi_netif_common(struct netifapi_msg_msg *msg) +{ + if (msg->msg.common.errtfunc != NULL) { + msg->err = msg->msg.common.errtfunc(msg->netif); + } else { + msg->err = ERR_OK; + msg->msg.common.voidfunc(msg->netif); + } + TCPIP_NETIFAPI_ACK(msg); +} + +/** + * Call netif_add() in a thread-safe way by running that function inside the + * tcpip_thread context. + * + * @note for params @see netif_add() + */ +err_t +netifapi_netif_add(struct netif *netif, + ip_addr_t *ipaddr, + ip_addr_t *netmask, + ip_addr_t *gw, + void *state, + netif_init_fn init, + netif_input_fn input) +{ + struct netifapi_msg msg; + msg.function = do_netifapi_netif_add; + msg.msg.netif = netif; + msg.msg.msg.add.ipaddr = ipaddr; + msg.msg.msg.add.netmask = netmask; + msg.msg.msg.add.gw = gw; + msg.msg.msg.add.state = state; + msg.msg.msg.add.init = init; + msg.msg.msg.add.input = input; + TCPIP_NETIFAPI(&msg); + return msg.msg.err; +} + +/** + * Call netif_set_addr() in a thread-safe way by running that function inside the + * tcpip_thread context. + * + * @note for params @see netif_set_addr() + */ +err_t +netifapi_netif_set_addr(struct netif *netif, + ip_addr_t *ipaddr, + ip_addr_t *netmask, + ip_addr_t *gw) +{ + struct netifapi_msg msg; + msg.function = do_netifapi_netif_set_addr; + msg.msg.netif = netif; + msg.msg.msg.add.ipaddr = ipaddr; + msg.msg.msg.add.netmask = netmask; + msg.msg.msg.add.gw = gw; + TCPIP_NETIFAPI(&msg); + return msg.msg.err; +} + +/** + * call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) in a thread-safe + * way by running that function inside the tcpip_thread context. + * + * @note use only for functions where there is only "netif" parameter. + */ +err_t +netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc, + netifapi_errt_fn errtfunc) +{ + struct netifapi_msg msg; + msg.function = do_netifapi_netif_common; + msg.msg.netif = netif; + msg.msg.msg.common.voidfunc = voidfunc; + msg.msg.msg.common.errtfunc = errtfunc; + TCPIP_NETIFAPI(&msg); + return msg.msg.err; +} + +#endif /* LWIP_NETIF_API */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/sockets.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/sockets.c new file mode 100644 index 0000000..0f39bd2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/sockets.c @@ -0,0 +1,2347 @@ +/** + * @file + * Sockets BSD-Like API module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * Improved by Marc Boucher and David Haas + * + */ + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sockets.h" +#include "lwip/api.h" +#include "lwip/sys.h" +#include "lwip/igmp.h" +#include "lwip/inet.h" +#include "lwip/tcp.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/tcpip.h" +#include "lwip/pbuf.h" +#if LWIP_CHECKSUM_ON_COPY +#include "lwip/inet_chksum.h" +#endif + +#include + +#define NUM_SOCKETS MEMP_NUM_NETCONN + +/** Contains all internal pointers and states used for a socket */ +struct lwip_sock { + /** sockets currently are built on netconns, each socket has one netconn */ + struct netconn *conn; + /** data that was left from the previous read */ + void *lastdata; + /** offset in the data that was left from the previous read */ + u16_t lastoffset; + /** number of times data was received, set by event_callback(), + tested by the receive and select functions */ + s16_t rcvevent; + /** number of times data was ACKed (free send buffer), set by event_callback(), + tested by select */ + u16_t sendevent; + /** error happened for this socket, set by event_callback(), tested by select */ + u16_t errevent; + /** last error that occurred on this socket */ + int err; + /** counter of how many threads are waiting for this socket using select */ + int select_waiting; +}; + +/** Description for a task waiting in select */ +struct lwip_select_cb { + /** Pointer to the next waiting task */ + struct lwip_select_cb *next; + /** Pointer to the previous waiting task */ + struct lwip_select_cb *prev; + /** readset passed to select */ + fd_set *readset; + /** writeset passed to select */ + fd_set *writeset; + /** unimplemented: exceptset passed to select */ + fd_set *exceptset; + /** don't signal the same semaphore twice: set to 1 when signalled */ + int sem_signalled; + /** semaphore to wake up a task waiting for select */ + sys_sem_t sem; +}; + +/** This struct is used to pass data to the set/getsockopt_internal + * functions running in tcpip_thread context (only a void* is allowed) */ +struct lwip_setgetsockopt_data { + /** socket struct for which to change options */ + struct lwip_sock *sock; +#ifdef LWIP_DEBUG + /** socket index for which to change options */ + int s; +#endif /* LWIP_DEBUG */ + /** level of the option to process */ + int level; + /** name of the option to process */ + int optname; + /** set: value to set the option to + * get: value of the option is stored here */ + void *optval; + /** size of *optval */ + socklen_t *optlen; + /** if an error occures, it is temporarily stored here */ + err_t err; +}; + +/** The global array of available sockets */ +static struct lwip_sock sockets[NUM_SOCKETS]; +/** The global list of tasks waiting for select */ +static struct lwip_select_cb *select_cb_list; +/** This counter is increased from lwip_select when the list is chagned + and checked in event_callback to see if it has changed. */ +static volatile int select_cb_ctr; + +/** Table to quickly map an lwIP error (err_t) to a socket error + * by using -err as an index */ +static const int err_to_errno_table[] = { + 0, /* ERR_OK 0 No error, everything OK. */ + ENOMEM, /* ERR_MEM -1 Out of memory error. */ + ENOBUFS, /* ERR_BUF -2 Buffer error. */ + EWOULDBLOCK, /* ERR_TIMEOUT -3 Timeout */ + EHOSTUNREACH, /* ERR_RTE -4 Routing problem. */ + EINPROGRESS, /* ERR_INPROGRESS -5 Operation in progress */ + EINVAL, /* ERR_VAL -6 Illegal value. */ + EWOULDBLOCK, /* ERR_WOULDBLOCK -7 Operation would block. */ + EADDRINUSE, /* ERR_USE -8 Address in use. */ + EALREADY, /* ERR_ISCONN -9 Already connected. */ + ECONNABORTED, /* ERR_ABRT -10 Connection aborted. */ + ECONNRESET, /* ERR_RST -11 Connection reset. */ + ENOTCONN, /* ERR_CLSD -12 Connection closed. */ + ENOTCONN, /* ERR_CONN -13 Not connected. */ + EIO, /* ERR_ARG -14 Illegal argument. */ + -1, /* ERR_IF -15 Low-level netif error */ +}; + +#define ERR_TO_ERRNO_TABLE_SIZE \ + (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0])) + +#define err_to_errno(err) \ + ((unsigned)(-(err)) < ERR_TO_ERRNO_TABLE_SIZE ? \ + err_to_errno_table[-(err)] : EIO) + +#ifdef ERRNO +#ifndef set_errno +#define set_errno(err) errno = (err) +#endif +#else /* ERRNO */ +#define set_errno(err) +#endif /* ERRNO */ + +#define sock_set_errno(sk, e) do { \ + sk->err = (e); \ + set_errno(sk->err); \ +} while (0) + +/* Forward delcaration of some functions */ +static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); +static void lwip_getsockopt_internal(void *arg); +static void lwip_setsockopt_internal(void *arg); + +/** + * Initialize this module. This function has to be called before any other + * functions in this module! + */ +void +lwip_socket_init(void) +{ +} + +/** + * Map a externally used socket index to the internal socket representation. + * + * @param s externally used socket index + * @return struct lwip_sock for the socket or NULL if not found + */ +static struct lwip_sock * +get_socket(int s) +{ + struct lwip_sock *sock; + + if ((s < 0) || (s >= NUM_SOCKETS)) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s)); + set_errno(EBADF); + return NULL; + } + + sock = &sockets[s]; + + if (!sock->conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s)); + set_errno(EBADF); + return NULL; + } + + return sock; +} + +/** + * Same as get_socket but doesn't set errno + * + * @param s externally used socket index + * @return struct lwip_sock for the socket or NULL if not found + */ +static struct lwip_sock * +tryget_socket(int s) +{ + if ((s < 0) || (s >= NUM_SOCKETS)) { + return NULL; + } + if (!sockets[s].conn) { + return NULL; + } + return &sockets[s]; +} + +/** + * Allocate a new socket for a given netconn. + * + * @param newconn the netconn for which to allocate a socket + * @param accepted 1 if socket has been created by accept(), + * 0 if socket has been created by socket() + * @return the index of the new socket; -1 on error + */ +static int +alloc_socket(struct netconn *newconn, int accepted) +{ + int i; + SYS_ARCH_DECL_PROTECT(lev); + + /* allocate a new socket identifier */ + for (i = 0; i < NUM_SOCKETS; ++i) { + /* Protect socket array */ + SYS_ARCH_PROTECT(lev); + if (!sockets[i].conn) { + sockets[i].conn = newconn; + /* The socket is not yet known to anyone, so no need to protect + after having marked it as used. */ + SYS_ARCH_UNPROTECT(lev); + sockets[i].lastdata = NULL; + sockets[i].lastoffset = 0; + sockets[i].rcvevent = 0; + /* TCP sendbuf is empty, but the socket is not yet writable until connected + * (unless it has been created by accept()). */ + sockets[i].sendevent = (newconn->type == NETCONN_TCP ? (accepted != 0) : 1); + sockets[i].errevent = 0; + sockets[i].err = 0; + sockets[i].select_waiting = 0; + return i; + } + SYS_ARCH_UNPROTECT(lev); + } + return -1; +} + +/** Free a socket. The socket's netconn must have been + * delete before! + * + * @param sock the socket to free + * @param is_tcp != 0 for TCP sockets, used to free lastdata + */ +static void +free_socket(struct lwip_sock *sock, int is_tcp) +{ + void *lastdata; + SYS_ARCH_DECL_PROTECT(lev); + + lastdata = sock->lastdata; + sock->lastdata = NULL; + sock->lastoffset = 0; + sock->err = 0; + + /* Protect socket array */ + SYS_ARCH_PROTECT(lev); + sock->conn = NULL; + SYS_ARCH_UNPROTECT(lev); + /* don't use 'sock' after this line, as another task might have allocated it */ + + if (lastdata != NULL) { + if (is_tcp) { + pbuf_free((struct pbuf *)lastdata); + } else { + netbuf_delete((struct netbuf *)lastdata); + } + } +} + +/* Below this, the well-known socket functions are implemented. + * Use google.com or opengroup.org to get a good description :-) + * + * Exceptions are documented! + */ + +int +lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) +{ + struct lwip_sock *sock, *nsock; + struct netconn *newconn; + ip_addr_t naddr; + u16_t port; + int newsock; + struct sockaddr_in sin; + err_t err; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (netconn_is_nonblocking(sock->conn) && (sock->rcvevent <= 0)) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): returning EWOULDBLOCK\n", s)); + sock_set_errno(sock, EWOULDBLOCK); + return -1; + } + + /* wait for a new connection */ + err = netconn_accept(sock->conn, &newconn); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_acept failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + LWIP_ASSERT("newconn != NULL", newconn != NULL); + /* Prevent automatic window updates, we do this on our own! */ + netconn_set_noautorecved(newconn, 1); + + /* get the IP address and port of the remote host */ + err = netconn_peer(newconn, &naddr, &port); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_peer failed, err=%d\n", s, err)); + netconn_delete(newconn); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + /* Note that POSIX only requires us to check addr is non-NULL. addrlen must + * not be NULL if addr is valid. + */ + if (NULL != addr) { + LWIP_ASSERT("addr valid but addrlen NULL", addrlen != NULL); + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + sin.sin_port = htons(port); + inet_addr_from_ipaddr(&sin.sin_addr, &naddr); + + if (*addrlen > sizeof(sin)) + *addrlen = sizeof(sin); + + MEMCPY(addr, &sin, *addrlen); + } + + newsock = alloc_socket(newconn, 1); + if (newsock == -1) { + netconn_delete(newconn); + sock_set_errno(sock, ENFILE); + return -1; + } + LWIP_ASSERT("invalid socket index", (newsock >= 0) && (newsock < NUM_SOCKETS)); + LWIP_ASSERT("newconn->callback == event_callback", newconn->callback == event_callback); + nsock = &sockets[newsock]; + + /* See event_callback: If data comes in right away after an accept, even + * though the server task might not have created a new socket yet. + * In that case, newconn->socket is counted down (newconn->socket--), + * so nsock->rcvevent is >= 1 here! + */ + SYS_ARCH_PROTECT(lev); + nsock->rcvevent += (s16_t)(-1 - newconn->socket); + newconn->socket = newsock; + SYS_ARCH_UNPROTECT(lev); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); + ip_addr_debug_print(SOCKETS_DEBUG, &naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", port)); + + sock_set_errno(sock, 0); + return newsock; +} + +int +lwip_bind(int s, const struct sockaddr *name, socklen_t namelen) +{ + struct lwip_sock *sock; + ip_addr_t local_addr; + u16_t local_port; + err_t err; + const struct sockaddr_in *name_in; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* check size, familiy and alignment of 'name' */ + LWIP_ERROR("lwip_bind: invalid address", ((namelen == sizeof(struct sockaddr_in)) && + ((name->sa_family) == AF_INET) && ((((mem_ptr_t)name) % 4) == 0)), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + name_in = (const struct sockaddr_in *)(void*)name; + + inet_addr_to_ipaddr(&local_addr, &name_in->sin_addr); + local_port = name_in->sin_port; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, &local_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", ntohs(local_port))); + + err = netconn_bind(sock->conn, &local_addr, ntohs(local_port)); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_close(int s) +{ + struct lwip_sock *sock; + int is_tcp = 0; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if(sock->conn != NULL) { + is_tcp = netconn_type(sock->conn) == NETCONN_TCP; + } else { + LWIP_ASSERT("sock->lastdata == NULL", sock->lastdata == NULL); + } + + netconn_delete(sock->conn); + + free_socket(sock, is_tcp); + set_errno(0); + return 0; +} + +int +lwip_connect(int s, const struct sockaddr *name, socklen_t namelen) +{ + struct lwip_sock *sock; + err_t err; + const struct sockaddr_in *name_in; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* check size, familiy and alignment of 'name' */ + LWIP_ERROR("lwip_connect: invalid address", ((namelen == sizeof(struct sockaddr_in)) && + ((name->sa_family) == AF_INET) && ((((mem_ptr_t)name) % 4) == 0)), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + name_in = (const struct sockaddr_in *)(void*)name; + + if (name_in->sin_family == AF_UNSPEC) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); + err = netconn_disconnect(sock->conn); + } else { + ip_addr_t remote_addr; + u16_t remote_port; + + inet_addr_to_ipaddr(&remote_addr, &name_in->sin_addr); + remote_port = name_in->sin_port; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", ntohs(remote_port))); + + err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); + } + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +/** + * Set a socket into listen mode. + * The socket may not have been used for another connection previously. + * + * @param s the socket to set to listening mode + * @param backlog (ATTENTION: needs TCP_LISTEN_BACKLOG=1) + * @return 0 on success, non-zero on failure + */ +int +lwip_listen(int s, int backlog) +{ + struct lwip_sock *sock; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* limit the "backlog" parameter to fit in an u8_t */ + backlog = LWIP_MIN(LWIP_MAX(backlog, 0), 0xff); + + err = netconn_listen_with_backlog(sock->conn, (u8_t)backlog); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_recvfrom(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen) +{ + struct lwip_sock *sock; + void *buf = NULL; + struct pbuf *p; + u16_t buflen, copylen; + int off = 0; + ip_addr_t *addr; + u16_t port; + u8_t done = 0; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %"SZT_F", 0x%x, ..)\n", s, mem, len, flags)); + sock = get_socket(s); + if (!sock) { + return -1; + } + + do { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: top while sock->lastdata=%p\n", sock->lastdata)); + /* Check if there is data left from the last recv operation. */ + if (sock->lastdata) { + buf = sock->lastdata; + } else { + /* If this is non-blocking call, then check first */ + if (((flags & MSG_DONTWAIT) || netconn_is_nonblocking(sock->conn)) && + (sock->rcvevent <= 0)) { + if (off > 0) { + /* update receive window */ + netconn_recved(sock->conn, (u32_t)off); + /* already received data, return that */ + sock_set_errno(sock, 0); + return off; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s)); + sock_set_errno(sock, EWOULDBLOCK); + return -1; + } + + /* No data was left from the previous operation, so we try to get + some from the network. */ + if (netconn_type(sock->conn) == NETCONN_TCP) { + err = netconn_recv_tcp_pbuf(sock->conn, (struct pbuf **)&buf); + } else { + err = netconn_recv(sock->conn, (struct netbuf **)&buf); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: netconn_recv err=%d, netbuf=%p\n", + err, buf)); + + if (err != ERR_OK) { + if (off > 0) { + /* update receive window */ + netconn_recved(sock->conn, (u32_t)off); + /* already received data, return that */ + sock_set_errno(sock, 0); + return off; + } + /* We should really do some error checking here. */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL, error is \"%s\"!\n", + s, lwip_strerr(err))); + sock_set_errno(sock, err_to_errno(err)); + if (err == ERR_CLSD) { + return 0; + } else { + return -1; + } + } + LWIP_ASSERT("buf != NULL", buf != NULL); + sock->lastdata = buf; + } + + if (netconn_type(sock->conn) == NETCONN_TCP) { + p = (struct pbuf *)buf; + } else { + p = ((struct netbuf *)buf)->p; + } + buflen = p->tot_len; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: buflen=%"U16_F" len=%"SZT_F" off=%d sock->lastoffset=%"U16_F"\n", + buflen, len, off, sock->lastoffset)); + + buflen -= sock->lastoffset; + + if (len > buflen) { + copylen = buflen; + } else { + copylen = (u16_t)len; + } + + /* copy the contents of the received buffer into + the supplied memory pointer mem */ + pbuf_copy_partial(p, (u8_t*)mem + off, copylen, sock->lastoffset); + + off += copylen; + + if (netconn_type(sock->conn) == NETCONN_TCP) { + LWIP_ASSERT("invalid copylen, len would underflow", len >= copylen); + len -= copylen; + if ( (len <= 0) || + (p->flags & PBUF_FLAG_PUSH) || + (sock->rcvevent <= 0) || + ((flags & MSG_PEEK)!=0)) { + done = 1; + } + } else { + done = 1; + } + + /* Check to see from where the data was.*/ + if (done) { + ip_addr_t fromaddr; + if (from && fromlen) { + struct sockaddr_in sin; + + if (netconn_type(sock->conn) == NETCONN_TCP) { + addr = &fromaddr; + netconn_getaddr(sock->conn, addr, &port, 0); + } else { + addr = netbuf_fromaddr((struct netbuf *)buf); + port = netbuf_fromport((struct netbuf *)buf); + } + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + sin.sin_port = htons(port); + inet_addr_from_ipaddr(&sin.sin_addr, addr); + + if (*fromlen > sizeof(sin)) { + *fromlen = sizeof(sin); + } + + MEMCPY(from, &sin, *fromlen); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", port, off)); + } else { +#if SOCKETS_DEBUG + if (netconn_type(sock->conn) == NETCONN_TCP) { + addr = &fromaddr; + netconn_getaddr(sock->conn, addr, &port, 0); + } else { + addr = netbuf_fromaddr((struct netbuf *)buf); + port = netbuf_fromport((struct netbuf *)buf); + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", port, off)); +#endif /* SOCKETS_DEBUG */ + } + } + + /* If we don't peek the incoming message... */ + if ((flags & MSG_PEEK) == 0) { + /* If this is a TCP socket, check if there is data left in the + buffer. If so, it should be saved in the sock structure for next + time around. */ + if ((netconn_type(sock->conn) == NETCONN_TCP) && (buflen - copylen > 0)) { + sock->lastdata = buf; + sock->lastoffset += copylen; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: lastdata now netbuf=%p\n", buf)); + } else { + sock->lastdata = NULL; + sock->lastoffset = 0; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: deleting netbuf=%p\n", buf)); + if (netconn_type(sock->conn) == NETCONN_TCP) { + pbuf_free((struct pbuf *)buf); + } else { + netbuf_delete((struct netbuf *)buf); + } + } + } + } while (!done); + + if (off > 0) { + /* update receive window */ + netconn_recved(sock->conn, (u32_t)off); + } + sock_set_errno(sock, 0); + return off; +} + +int +lwip_read(int s, void *mem, size_t len) +{ + return lwip_recvfrom(s, mem, len, 0, NULL, NULL); +} + +int +lwip_recv(int s, void *mem, size_t len, int flags) +{ + return lwip_recvfrom(s, mem, len, flags, NULL, NULL); +} + +int +lwip_send(int s, const void *data, size_t size, int flags) +{ + struct lwip_sock *sock; + err_t err; + u8_t write_flags; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%"SZT_F", flags=0x%x)\n", + s, data, size, flags)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (sock->conn->type != NETCONN_TCP) { +#if (LWIP_UDP || LWIP_RAW) + return lwip_sendto(s, data, size, flags, NULL, 0); +#else /* (LWIP_UDP || LWIP_RAW) */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* (LWIP_UDP || LWIP_RAW) */ + } + + if ((flags & MSG_DONTWAIT) || netconn_is_nonblocking(sock->conn)) { + if ((size > TCP_SND_BUF) || ((size / TCP_MSS) > TCP_SND_QUEUELEN)) { + /* too much data to ever send nonblocking! */ + sock_set_errno(sock, EMSGSIZE); + return -1; + } + } + + write_flags = NETCONN_COPY | + ((flags & MSG_MORE) ? NETCONN_MORE : 0) | + ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0); + err = netconn_write(sock->conn, data, size, write_flags); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d size=%"SZT_F"\n", s, err, size)); + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? (int)size : -1); +} + +int +lwip_sendto(int s, const void *data, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen) +{ + struct lwip_sock *sock; + err_t err; + u16_t short_size; + const struct sockaddr_in *to_in; + u16_t remote_port; +#if !LWIP_TCPIP_CORE_LOCKING + struct netbuf buf; +#endif + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (sock->conn->type == NETCONN_TCP) { +#if LWIP_TCP + return lwip_send(s, data, size, flags); +#else /* LWIP_TCP */ + LWIP_UNUSED_ARG(flags); + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* LWIP_TCP */ + } + + /* @todo: split into multiple sendto's? */ + LWIP_ASSERT("lwip_sendto: size must fit in u16_t", size <= 0xffff); + short_size = (u16_t)size; + LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) || + ((tolen == sizeof(struct sockaddr_in)) && + ((to->sa_family) == AF_INET) && ((((mem_ptr_t)to) % 4) == 0))), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + to_in = (const struct sockaddr_in *)(void*)to; + +#if LWIP_TCPIP_CORE_LOCKING + /* Should only be consider like a sample or a simple way to experiment this option (no check of "to" field...) */ + { + struct pbuf* p; + ip_addr_t *remote_addr; + +#if LWIP_NETIF_TX_SINGLE_PBUF + p = pbuf_alloc(PBUF_TRANSPORT, short_size, PBUF_RAM); + if (p != NULL) { +#if LWIP_CHECKSUM_ON_COPY + u16_t chksum = 0; + if (sock->conn->type != NETCONN_RAW) { + chksum = LWIP_CHKSUM_COPY(p->payload, data, short_size); + } else +#endif /* LWIP_CHECKSUM_ON_COPY */ + MEMCPY(p->payload, data, size); +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + p = pbuf_alloc(PBUF_TRANSPORT, short_size, PBUF_REF); + if (p != NULL) { + p->payload = (void*)data; +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + if (to_in != NULL) { + inet_addr_to_ipaddr_p(remote_addr, &to_in->sin_addr); + remote_port = ntohs(to_in->sin_port); + } else { + remote_addr = &sock->conn->pcb.raw->remote_ip; + if (sock->conn->type == NETCONN_RAW) { + remote_port = 0; + } else { + remote_port = sock->conn->pcb.udp->remote_port; + } + } + + LOCK_TCPIP_CORE(); + if (sock->conn->type == NETCONN_RAW) { + err = sock->conn->last_err = raw_sendto(sock->conn->pcb.raw, p, remote_addr); + } else { +#if LWIP_UDP +#if LWIP_CHECKSUM_ON_COPY && LWIP_NETIF_TX_SINGLE_PBUF + err = sock->conn->last_err = udp_sendto_chksum(sock->conn->pcb.udp, p, + remote_addr, remote_port, 1, chksum); +#else /* LWIP_CHECKSUM_ON_COPY && LWIP_NETIF_TX_SINGLE_PBUF */ + err = sock->conn->last_err = udp_sendto(sock->conn->pcb.udp, p, + remote_addr, remote_port); +#endif /* LWIP_CHECKSUM_ON_COPY && LWIP_NETIF_TX_SINGLE_PBUF */ +#else /* LWIP_UDP */ + err = ERR_ARG; +#endif /* LWIP_UDP */ + } + UNLOCK_TCPIP_CORE(); + + pbuf_free(p); + } else { + err = ERR_MEM; + } + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + /* initialize a buffer */ + buf.p = buf.ptr = NULL; +#if LWIP_CHECKSUM_ON_COPY + buf.flags = 0; +#endif /* LWIP_CHECKSUM_ON_COPY */ + if (to) { + inet_addr_to_ipaddr(&buf.addr, &to_in->sin_addr); + remote_port = ntohs(to_in->sin_port); + netbuf_fromport(&buf) = remote_port; + } else { + remote_port = 0; + ip_addr_set_any(&buf.addr); + netbuf_fromport(&buf) = 0; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, short_size=%"U16_F", flags=0x%x to=", + s, data, short_size, flags)); + ip_addr_debug_print(SOCKETS_DEBUG, &buf.addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", remote_port)); + + /* make the buffer point to the data that should be sent */ +#if LWIP_NETIF_TX_SINGLE_PBUF + /* Allocate a new netbuf and copy the data into it. */ + if (netbuf_alloc(&buf, short_size) == NULL) { + err = ERR_MEM; + } else { +#if LWIP_CHECKSUM_ON_COPY + if (sock->conn->type != NETCONN_RAW) { + u16_t chksum = LWIP_CHKSUM_COPY(buf.p->payload, data, short_size); + netbuf_set_chksum(&buf, chksum); + err = ERR_OK; + } else +#endif /* LWIP_CHECKSUM_ON_COPY */ + { + err = netbuf_take(&buf, data, short_size); + } + } +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + err = netbuf_ref(&buf, data, short_size); +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + if (err == ERR_OK) { + /* send the data */ + err = netconn_send(sock->conn, &buf); + } + + /* deallocated the buffer */ + netbuf_free(&buf); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? short_size : -1); +} + +int +lwip_socket(int domain, int type, int protocol) +{ + struct netconn *conn; + int i; + + LWIP_UNUSED_ARG(domain); + + /* create a netconn */ + switch (type) { + case SOCK_RAW: + conn = netconn_new_with_proto_and_callback(NETCONN_RAW, (u8_t)protocol, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_DGRAM: + conn = netconn_new_with_callback( (protocol == IPPROTO_UDPLITE) ? + NETCONN_UDPLITE : NETCONN_UDP, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_STREAM: + conn = netconn_new_with_callback(NETCONN_TCP, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + if (conn != NULL) { + /* Prevent automatic window updates, we do this on our own! */ + netconn_set_noautorecved(conn, 1); + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", + domain, type, protocol)); + set_errno(EINVAL); + return -1; + } + + if (!conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); + set_errno(ENOBUFS); + return -1; + } + + i = alloc_socket(conn, 0); + + if (i == -1) { + netconn_delete(conn); + set_errno(ENFILE); + return -1; + } + conn->socket = i; + LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); + set_errno(0); + return i; +} + +int +lwip_write(int s, const void *data, size_t size) +{ + return lwip_send(s, data, size, 0); +} + +/** + * Go through the readset and writeset lists and see which socket of the sockets + * set in the sets has events. On return, readset, writeset and exceptset have + * the sockets enabled that had events. + * + * exceptset is not used for now!!! + * + * @param maxfdp1 the highest socket index in the sets + * @param readset_in: set of sockets to check for read events + * @param writeset_in: set of sockets to check for write events + * @param exceptset_in: set of sockets to check for error events + * @param readset_out: set of sockets that had read events + * @param writeset_out: set of sockets that had write events + * @param exceptset_out: set os sockets that had error events + * @return number of sockets that had events (read/write/exception) (>= 0) + */ +static int +lwip_selscan(int maxfdp1, fd_set *readset_in, fd_set *writeset_in, fd_set *exceptset_in, + fd_set *readset_out, fd_set *writeset_out, fd_set *exceptset_out) +{ + int i, nready = 0; + fd_set lreadset, lwriteset, lexceptset; + struct lwip_sock *sock; + SYS_ARCH_DECL_PROTECT(lev); + + FD_ZERO(&lreadset); + FD_ZERO(&lwriteset); + FD_ZERO(&lexceptset); + + /* Go through each socket in each list to count number of sockets which + currently match */ + for(i = 0; i < maxfdp1; i++) { + void* lastdata = NULL; + s16_t rcvevent = 0; + u16_t sendevent = 0; + u16_t errevent = 0; + /* First get the socket's status (protected)... */ + SYS_ARCH_PROTECT(lev); + sock = tryget_socket(i); + if (sock != NULL) { + lastdata = sock->lastdata; + rcvevent = sock->rcvevent; + sendevent = sock->sendevent; + errevent = sock->errevent; + } + SYS_ARCH_UNPROTECT(lev); + /* ... then examine it: */ + /* See if netconn of this socket is ready for read */ + if (readset_in && FD_ISSET(i, readset_in) && ((lastdata != NULL) || (rcvevent > 0))) { + FD_SET(i, &lreadset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); + nready++; + } + /* See if netconn of this socket is ready for write */ + if (writeset_in && FD_ISSET(i, writeset_in) && (sendevent != 0)) { + FD_SET(i, &lwriteset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); + nready++; + } + /* See if netconn of this socket had an error */ + if (exceptset_in && FD_ISSET(i, exceptset_in) && (errevent != 0)) { + FD_SET(i, &lexceptset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for exception\n", i)); + nready++; + } + } + /* copy local sets to the ones provided as arguments */ + *readset_out = lreadset; + *writeset_out = lwriteset; + *exceptset_out = lexceptset; + + LWIP_ASSERT("nready >= 0", nready >= 0); + return nready; +} + +/** + * Processing exceptset is not yet implemented. + */ +int +lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout) +{ + u32_t waitres = 0; + int nready; + fd_set lreadset, lwriteset, lexceptset; + u32_t msectimeout; + struct lwip_select_cb select_cb; + err_t err; + int i; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%"S32_F" tvusec=%"S32_F")\n", + maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, + timeout ? (s32_t)timeout->tv_sec : (s32_t)-1, + timeout ? (s32_t)timeout->tv_usec : (s32_t)-1)); + + /* Go through each socket in each list to count number of sockets which + currently match */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + + /* If we don't have any current events, then suspend if we are supposed to */ + if (!nready) { + if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); + /* This is OK as the local fdsets are empty and nready is zero, + or we would have returned earlier. */ + goto return_copy_fdsets; + } + + /* None ready: add our semaphore to list: + We don't actually need any dynamic memory. Our entry on the + list is only valid while we are in this function, so it's ok + to use local variables. */ + + select_cb.next = NULL; + select_cb.prev = NULL; + select_cb.readset = readset; + select_cb.writeset = writeset; + select_cb.exceptset = exceptset; + select_cb.sem_signalled = 0; + err = sys_sem_new(&select_cb.sem, 0); + if (err != ERR_OK) { + /* failed to create semaphore */ + set_errno(ENOMEM); + return -1; + } + + /* Protect the select_cb_list */ + SYS_ARCH_PROTECT(lev); + + /* Put this select_cb on top of list */ + select_cb.next = select_cb_list; + if (select_cb_list != NULL) { + select_cb_list->prev = &select_cb; + } + select_cb_list = &select_cb; + /* Increasing this counter tells even_callback that the list has changed. */ + select_cb_ctr++; + + /* Now we can safely unprotect */ + SYS_ARCH_UNPROTECT(lev); + + /* Increase select_waiting for each socket we are interested in */ + for(i = 0; i < maxfdp1; i++) { + if ((readset && FD_ISSET(i, readset)) || + (writeset && FD_ISSET(i, writeset)) || + (exceptset && FD_ISSET(i, exceptset))) { + struct lwip_sock *sock = tryget_socket(i); + LWIP_ASSERT("sock != NULL", sock != NULL); + SYS_ARCH_PROTECT(lev); + sock->select_waiting++; + LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0); + SYS_ARCH_UNPROTECT(lev); + } + } + + /* Call lwip_selscan again: there could have been events between + the last scan (whithout us on the list) and putting us on the list! */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + if (!nready) { + /* Still none ready, just wait to be woken */ + if (timeout == 0) { + /* Wait forever */ + msectimeout = 0; + } else { + msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000)); + if (msectimeout == 0) { + /* Wait 1ms at least (0 means wait forever) */ + msectimeout = 1; + } + } + + waitres = sys_arch_sem_wait(&select_cb.sem, msectimeout); + } + /* Increase select_waiting for each socket we are interested in */ + for(i = 0; i < maxfdp1; i++) { + if ((readset && FD_ISSET(i, readset)) || + (writeset && FD_ISSET(i, writeset)) || + (exceptset && FD_ISSET(i, exceptset))) { + struct lwip_sock *sock = tryget_socket(i); + LWIP_ASSERT("sock != NULL", sock != NULL); + SYS_ARCH_PROTECT(lev); + sock->select_waiting--; + LWIP_ASSERT("sock->select_waiting >= 0", sock->select_waiting >= 0); + SYS_ARCH_UNPROTECT(lev); + } + } + /* Take us off the list */ + SYS_ARCH_PROTECT(lev); + if (select_cb.next != NULL) { + select_cb.next->prev = select_cb.prev; + } + if (select_cb_list == &select_cb) { + LWIP_ASSERT("select_cb.prev == NULL", select_cb.prev == NULL); + select_cb_list = select_cb.next; + } else { + LWIP_ASSERT("select_cb.prev != NULL", select_cb.prev != NULL); + select_cb.prev->next = select_cb.next; + } + /* Increasing this counter tells even_callback that the list has changed. */ + select_cb_ctr++; + SYS_ARCH_UNPROTECT(lev); + + sys_sem_free(&select_cb.sem); + if (waitres == SYS_ARCH_TIMEOUT) { + /* Timeout */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); + /* This is OK as the local fdsets are empty and nready is zero, + or we would have returned earlier. */ + goto return_copy_fdsets; + } + + /* See what's set */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); +return_copy_fdsets: + set_errno(0); + if (readset) { + *readset = lreadset; + } + if (writeset) { + *writeset = lwriteset; + } + if (exceptset) { + *exceptset = lexceptset; + } + + + return nready; +} + +/** + * Callback registered in the netconn layer for each socket-netconn. + * Processes recvevent (data available) and wakes up tasks waiting for select. + */ +static void +event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) +{ + int s; + struct lwip_sock *sock; + struct lwip_select_cb *scb; + int last_select_cb_ctr; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_UNUSED_ARG(len); + + /* Get socket */ + if (conn) { + s = conn->socket; + if (s < 0) { + /* Data comes in right away after an accept, even though + * the server task might not have created a new socket yet. + * Just count down (or up) if that's the case and we + * will use the data later. Note that only receive events + * can happen before the new socket is set up. */ + SYS_ARCH_PROTECT(lev); + if (conn->socket < 0) { + if (evt == NETCONN_EVT_RCVPLUS) { + conn->socket--; + } + SYS_ARCH_UNPROTECT(lev); + return; + } + s = conn->socket; + SYS_ARCH_UNPROTECT(lev); + } + + sock = get_socket(s); + if (!sock) { + return; + } + } else { + return; + } + + SYS_ARCH_PROTECT(lev); + /* Set event as required */ + switch (evt) { + case NETCONN_EVT_RCVPLUS: + sock->rcvevent++; + break; + case NETCONN_EVT_RCVMINUS: + sock->rcvevent--; + break; + case NETCONN_EVT_SENDPLUS: + sock->sendevent = 1; + break; + case NETCONN_EVT_SENDMINUS: + sock->sendevent = 0; + break; + case NETCONN_EVT_ERROR: + sock->errevent = 1; + break; + default: + LWIP_ASSERT("unknown event", 0); + break; + } + + if (sock->select_waiting == 0) { + /* noone is waiting for this socket, no need to check select_cb_list */ + SYS_ARCH_UNPROTECT(lev); + return; + } + + /* Now decide if anyone is waiting for this socket */ + /* NOTE: This code goes through the select_cb_list list multiple times + ONLY IF a select was actually waiting. We go through the list the number + of waiting select calls + 1. This list is expected to be small. */ + + /* At this point, SYS_ARCH is still protected! */ +again: + for (scb = select_cb_list; scb != NULL; scb = scb->next) { + if (scb->sem_signalled == 0) { + /* semaphore not signalled yet */ + int do_signal = 0; + /* Test this select call for our socket */ + if (sock->rcvevent > 0) { + if (scb->readset && FD_ISSET(s, scb->readset)) { + do_signal = 1; + } + } + if (sock->sendevent != 0) { + if (!do_signal && scb->writeset && FD_ISSET(s, scb->writeset)) { + do_signal = 1; + } + } + if (sock->errevent != 0) { + if (!do_signal && scb->exceptset && FD_ISSET(s, scb->exceptset)) { + do_signal = 1; + } + } + if (do_signal) { + scb->sem_signalled = 1; + /* Don't call SYS_ARCH_UNPROTECT() before signaling the semaphore, as this might + lead to the select thread taking itself off the list, invalidagin the semaphore. */ + sys_sem_signal(&scb->sem); + } + } + /* unlock interrupts with each step */ + last_select_cb_ctr = select_cb_ctr; + SYS_ARCH_UNPROTECT(lev); + /* this makes sure interrupt protection time is short */ + SYS_ARCH_PROTECT(lev); + if (last_select_cb_ctr != select_cb_ctr) { + /* someone has changed select_cb_list, restart at the beginning */ + goto again; + } + } + SYS_ARCH_UNPROTECT(lev); +} + +/** + * Unimplemented: Close one end of a full-duplex connection. + * Currently, the full connection is closed. + */ +int +lwip_shutdown(int s, int how) +{ + struct lwip_sock *sock; + err_t err; + u8_t shut_rx = 0, shut_tx = 0; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (sock->conn != NULL) { + if (netconn_type(sock->conn) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + return EOPNOTSUPP; + } + } else { + sock_set_errno(sock, ENOTCONN); + return ENOTCONN; + } + + if (how == SHUT_RD) { + shut_rx = 1; + } else if (how == SHUT_WR) { + shut_tx = 1; + } else if(how == SHUT_RDWR) { + shut_rx = 1; + shut_tx = 1; + } else { + sock_set_errno(sock, EINVAL); + return EINVAL; + } + err = netconn_shutdown(sock->conn, shut_rx, shut_tx); + + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? 0 : -1); +} + +static int +lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local) +{ + struct lwip_sock *sock; + struct sockaddr_in sin; + ip_addr_t naddr; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + + /* get the IP address and port */ + netconn_getaddr(sock->conn, &naddr, &sin.sin_port, local); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, &naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", sin.sin_port)); + + sin.sin_port = htons(sin.sin_port); + inet_addr_from_ipaddr(&sin.sin_addr, &naddr); + + if (*namelen > sizeof(sin)) { + *namelen = sizeof(sin); + } + + MEMCPY(name, &sin, *namelen); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen) +{ + return lwip_getaddrname(s, name, namelen, 0); +} + +int +lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen) +{ + return lwip_getaddrname(s, name, namelen, 1); +} + +int +lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen) +{ + err_t err = ERR_OK; + struct lwip_sock *sock = get_socket(s); + struct lwip_setgetsockopt_data data; + + if (!sock) { + return -1; + } + + if ((NULL == optval) || (NULL == optlen)) { + sock_set_errno(sock, EFAULT); + return -1; + } + + /* Do length and type checks for the various options first, to keep it readable. */ + switch (level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + + case SO_ACCEPTCONN: + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_ERROR: + case SO_KEEPALIVE: + /* UNIMPL case SO_CONTIMEO: */ + /* UNIMPL case SO_SNDTIMEO: */ +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: +#endif /* LWIP_SO_RCVBUF */ + /* UNIMPL case SO_OOBINLINE: */ + /* UNIMPL case SO_SNDBUF: */ + /* UNIMPL case SO_RCVLOWAT: */ + /* UNIMPL case SO_SNDLOWAT: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + case SO_TYPE: + /* UNIMPL case SO_USELOOPBACK: */ + if (*optlen < sizeof(int)) { + err = EINVAL; + } + break; + + case SO_NO_CHECK: + if (*optlen < sizeof(int)) { + err = EINVAL; + } +#if LWIP_UDP + if ((sock->conn->type != NETCONN_UDP) || + ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) { + /* this flag is only available for UDP, not for UDP lite */ + err = EAFNOSUPPORT; + } +#endif /* LWIP_UDP */ + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + } /* switch (optname) */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + /* UNIMPL case IP_HDRINCL: */ + /* UNIMPL case IP_RCVDSTADDR: */ + /* UNIMPL case IP_RCVIF: */ + case IP_TTL: + case IP_TOS: + if (*optlen < sizeof(int)) { + err = EINVAL; + } + break; +#if LWIP_IGMP + case IP_MULTICAST_TTL: + if (*optlen < sizeof(u8_t)) { + err = EINVAL; + } + break; + case IP_MULTICAST_IF: + if (*optlen < sizeof(struct in_addr)) { + err = EINVAL; + } + break; + case IP_MULTICAST_LOOP: + if (*optlen < sizeof(u8_t)) { + err = EINVAL; + } + if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) { + err = EAFNOSUPPORT; + } + break; +#endif /* LWIP_IGMP */ + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + } /* switch (optname) */ + break; + +#if LWIP_TCP +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + if (*optlen < sizeof(int)) { + err = EINVAL; + break; + } + + /* If this is no TCP socket, ignore any options. */ + if (sock->conn->type != NETCONN_TCP) + return 0; + + switch (optname) { + case TCP_NODELAY: + case TCP_KEEPALIVE: +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + case TCP_KEEPINTVL: + case TCP_KEEPCNT: +#endif /* LWIP_TCP_KEEPALIVE */ + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP */ +#if LWIP_UDP && LWIP_UDPLITE +/* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + if (*optlen < sizeof(int)) { + err = EINVAL; + break; + } + + /* If this is no UDP lite socket, ignore any options. */ + if (sock->conn->type != NETCONN_UDPLITE) { + return 0; + } + + switch (optname) { + case UDPLITE_SEND_CSCOV: + case UDPLITE_RECV_CSCOV: + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP && LWIP_UDPLITE*/ +/* UNDEFINED LEVEL */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", + s, level, optname)); + err = ENOPROTOOPT; + } /* switch */ + + + if (err != ERR_OK) { + sock_set_errno(sock, err); + return -1; + } + + /* Now do the actual option processing */ + data.sock = sock; +#ifdef LWIP_DEBUG + data.s = s; +#endif /* LWIP_DEBUG */ + data.level = level; + data.optname = optname; + data.optval = optval; + data.optlen = optlen; + data.err = err; + tcpip_callback(lwip_getsockopt_internal, &data); + sys_arch_sem_wait(&sock->conn->op_completed, 0); + /* maybe lwip_getsockopt_internal has changed err */ + err = data.err; + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +static void +lwip_getsockopt_internal(void *arg) +{ + struct lwip_sock *sock; +#ifdef LWIP_DEBUG + int s; +#endif /* LWIP_DEBUG */ + int level, optname; + void *optval; + struct lwip_setgetsockopt_data *data; + + LWIP_ASSERT("arg != NULL", arg != NULL); + + data = (struct lwip_setgetsockopt_data*)arg; + sock = data->sock; +#ifdef LWIP_DEBUG + s = data->s; +#endif /* LWIP_DEBUG */ + level = data->level; + optname = data->optname; + optval = data->optval; + + switch (level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + + /* The option flags */ + case SO_ACCEPTCONN: + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINCLUDE: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + /*case SO_USELOOPBACK: UNIMPL */ + *(int*)optval = sock->conn->pcb.ip->so_options & optname; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", + s, optname, (*(int*)optval?"on":"off"))); + break; + + case SO_TYPE: + switch (NETCONNTYPE_GROUP(sock->conn->type)) { + case NETCONN_RAW: + *(int*)optval = SOCK_RAW; + break; + case NETCONN_TCP: + *(int*)optval = SOCK_STREAM; + break; + case NETCONN_UDP: + *(int*)optval = SOCK_DGRAM; + break; + default: /* unrecognized socket type */ + *(int*)optval = sock->conn->type; + LWIP_DEBUGF(SOCKETS_DEBUG, + ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", + s, *(int *)optval)); + } /* switch (sock->conn->type) */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", + s, *(int *)optval)); + break; + + case SO_ERROR: + /* only overwrite ERR_OK or tempoary errors */ + if ((sock->err == 0) || (sock->err == EINPROGRESS)) { + sock_set_errno(sock, err_to_errno(sock->conn->last_err)); + } + *(int *)optval = sock->err; + sock->err = 0; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", + s, *(int *)optval)); + break; + +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: + *(int *)optval = netconn_get_recvtimeout(sock->conn); + break; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: + *(int *)optval = netconn_get_recvbufsize(sock->conn); + break; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_UDP + case SO_NO_CHECK: + *(int*)optval = (udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_NOCHKSUM) ? 1 : 0; + break; +#endif /* LWIP_UDP*/ + default: + LWIP_ASSERT("unhandled optname", 0); + break; + } /* switch (optname) */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + case IP_TTL: + *(int*)optval = sock->conn->pcb.ip->ttl; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", + s, *(int *)optval)); + break; + case IP_TOS: + *(int*)optval = sock->conn->pcb.ip->tos; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", + s, *(int *)optval)); + break; +#if LWIP_IGMP + case IP_MULTICAST_TTL: + *(u8_t*)optval = sock->conn->pcb.ip->ttl; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n", + s, *(int *)optval)); + break; + case IP_MULTICAST_IF: + inet_addr_from_ipaddr((struct in_addr*)optval, &sock->conn->pcb.udp->multicast_ip); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%"X32_F"\n", + s, *(u32_t *)optval)); + break; + case IP_MULTICAST_LOOP: + if ((sock->conn->pcb.udp->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) { + *(u8_t*)optval = 1; + } else { + *(u8_t*)optval = 0; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_LOOP) = %d\n", + s, *(int *)optval)); + break; +#endif /* LWIP_IGMP */ + default: + LWIP_ASSERT("unhandled optname", 0); + break; + } /* switch (optname) */ + break; + +#if LWIP_TCP +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + switch (optname) { + case TCP_NODELAY: + *(int*)optval = tcp_nagle_disabled(sock->conn->pcb.tcp); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", + s, (*(int*)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + *(int*)optval = (int)sock->conn->pcb.tcp->keep_idle; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", + s, *(int *)optval)); + break; + +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + *(int*)optval = (int)(sock->conn->pcb.tcp->keep_idle/1000); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPIDLE) = %d\n", + s, *(int *)optval)); + break; + case TCP_KEEPINTVL: + *(int*)optval = (int)(sock->conn->pcb.tcp->keep_intvl/1000); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPINTVL) = %d\n", + s, *(int *)optval)); + break; + case TCP_KEEPCNT: + *(int*)optval = (int)sock->conn->pcb.tcp->keep_cnt; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPCNT) = %d\n", + s, *(int *)optval)); + break; +#endif /* LWIP_TCP_KEEPALIVE */ + default: + LWIP_ASSERT("unhandled optname", 0); + break; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP */ +#if LWIP_UDP && LWIP_UDPLITE + /* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + switch (optname) { + case UDPLITE_SEND_CSCOV: + *(int*)optval = sock->conn->pcb.udp->chksum_len_tx; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n", + s, (*(int*)optval)) ); + break; + case UDPLITE_RECV_CSCOV: + *(int*)optval = sock->conn->pcb.udp->chksum_len_rx; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n", + s, (*(int*)optval)) ); + break; + default: + LWIP_ASSERT("unhandled optname", 0); + break; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP */ + default: + LWIP_ASSERT("unhandled level", 0); + break; + } /* switch (level) */ + sys_sem_signal(&sock->conn->op_completed); +} + +int +lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen) +{ + struct lwip_sock *sock = get_socket(s); + err_t err = ERR_OK; + struct lwip_setgetsockopt_data data; + + if (!sock) { + return -1; + } + + if (NULL == optval) { + sock_set_errno(sock, EFAULT); + return -1; + } + + /* Do length and type checks for the various options first, to keep it readable. */ + switch (level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_KEEPALIVE: + /* UNIMPL case case SO_CONTIMEO: */ + /* UNIMPL case case SO_SNDTIMEO: */ +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: +#endif /* LWIP_SO_RCVBUF */ + /* UNIMPL case SO_OOBINLINE: */ + /* UNIMPL case SO_SNDBUF: */ + /* UNIMPL case SO_RCVLOWAT: */ + /* UNIMPL case SO_SNDLOWAT: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + /* UNIMPL case SO_USELOOPBACK: */ + if (optlen < sizeof(int)) { + err = EINVAL; + } + break; + case SO_NO_CHECK: + if (optlen < sizeof(int)) { + err = EINVAL; + } +#if LWIP_UDP + if ((sock->conn->type != NETCONN_UDP) || + ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) { + /* this flag is only available for UDP, not for UDP lite */ + err = EAFNOSUPPORT; + } +#endif /* LWIP_UDP */ + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + } /* switch (optname) */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + /* UNIMPL case IP_HDRINCL: */ + /* UNIMPL case IP_RCVDSTADDR: */ + /* UNIMPL case IP_RCVIF: */ + case IP_TTL: + case IP_TOS: + if (optlen < sizeof(int)) { + err = EINVAL; + } + break; +#if LWIP_IGMP + case IP_MULTICAST_TTL: + if (optlen < sizeof(u8_t)) { + err = EINVAL; + } + if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) { + err = EAFNOSUPPORT; + } + break; + case IP_MULTICAST_IF: + if (optlen < sizeof(struct in_addr)) { + err = EINVAL; + } + if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) { + err = EAFNOSUPPORT; + } + break; + case IP_MULTICAST_LOOP: + if (optlen < sizeof(u8_t)) { + err = EINVAL; + } + if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) { + err = EAFNOSUPPORT; + } + break; + case IP_ADD_MEMBERSHIP: + case IP_DROP_MEMBERSHIP: + if (optlen < sizeof(struct ip_mreq)) { + err = EINVAL; + } + if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) { + err = EAFNOSUPPORT; + } + break; +#endif /* LWIP_IGMP */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + } /* switch (optname) */ + break; + +#if LWIP_TCP +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + if (optlen < sizeof(int)) { + err = EINVAL; + break; + } + + /* If this is no TCP socket, ignore any options. */ + if (sock->conn->type != NETCONN_TCP) + return 0; + + switch (optname) { + case TCP_NODELAY: + case TCP_KEEPALIVE: +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + case TCP_KEEPINTVL: + case TCP_KEEPCNT: +#endif /* LWIP_TCP_KEEPALIVE */ + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP */ +#if LWIP_UDP && LWIP_UDPLITE +/* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + if (optlen < sizeof(int)) { + err = EINVAL; + break; + } + + /* If this is no UDP lite socket, ignore any options. */ + if (sock->conn->type != NETCONN_UDPLITE) + return 0; + + switch (optname) { + case UDPLITE_SEND_CSCOV: + case UDPLITE_RECV_CSCOV: + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP && LWIP_UDPLITE */ +/* UNDEFINED LEVEL */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", + s, level, optname)); + err = ENOPROTOOPT; + } /* switch (level) */ + + + if (err != ERR_OK) { + sock_set_errno(sock, err); + return -1; + } + + + /* Now do the actual option processing */ + data.sock = sock; +#ifdef LWIP_DEBUG + data.s = s; +#endif /* LWIP_DEBUG */ + data.level = level; + data.optname = optname; + data.optval = (void*)optval; + data.optlen = &optlen; + data.err = err; + tcpip_callback(lwip_setsockopt_internal, &data); + sys_arch_sem_wait(&sock->conn->op_completed, 0); + /* maybe lwip_setsockopt_internal has changed err */ + err = data.err; + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +static void +lwip_setsockopt_internal(void *arg) +{ + struct lwip_sock *sock; +#ifdef LWIP_DEBUG + int s; +#endif /* LWIP_DEBUG */ + int level, optname; + const void *optval; + struct lwip_setgetsockopt_data *data; + + LWIP_ASSERT("arg != NULL", arg != NULL); + + data = (struct lwip_setgetsockopt_data*)arg; + sock = data->sock; +#ifdef LWIP_DEBUG + s = data->s; +#endif /* LWIP_DEBUG */ + level = data->level; + optname = data->optname; + optval = data->optval; + + switch (level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + + /* The option flags */ + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINCLUDE: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + /* UNIMPL case SO_USELOOPBACK: */ + if (*(int*)optval) { + sock->conn->pcb.ip->so_options |= optname; + } else { + sock->conn->pcb.ip->so_options &= ~optname; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", + s, optname, (*(int*)optval?"on":"off"))); + break; +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: + netconn_set_recvtimeout(sock->conn, *(int*)optval); + break; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: + netconn_set_recvbufsize(sock->conn, *(int*)optval); + break; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_UDP + case SO_NO_CHECK: + if (*(int*)optval) { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_NOCHKSUM); + } else { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_NOCHKSUM); + } + break; +#endif /* LWIP_UDP */ + default: + LWIP_ASSERT("unhandled optname", 0); + break; + } /* switch (optname) */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + case IP_TTL: + sock->conn->pcb.ip->ttl = (u8_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %d\n", + s, sock->conn->pcb.ip->ttl)); + break; + case IP_TOS: + sock->conn->pcb.ip->tos = (u8_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %d\n", + s, sock->conn->pcb.ip->tos)); + break; +#if LWIP_IGMP + case IP_MULTICAST_TTL: + sock->conn->pcb.udp->ttl = (u8_t)(*(u8_t*)optval); + break; + case IP_MULTICAST_IF: + inet_addr_to_ipaddr(&sock->conn->pcb.udp->multicast_ip, (struct in_addr*)optval); + break; + case IP_MULTICAST_LOOP: + if (*(u8_t*)optval) { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_MULTICAST_LOOP); + } else { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_MULTICAST_LOOP); + } + break; + case IP_ADD_MEMBERSHIP: + case IP_DROP_MEMBERSHIP: + { + /* If this is a TCP or a RAW socket, ignore these options. */ + struct ip_mreq *imr = (struct ip_mreq *)optval; + ip_addr_t if_addr; + ip_addr_t multi_addr; + inet_addr_to_ipaddr(&if_addr, &imr->imr_interface); + inet_addr_to_ipaddr(&multi_addr, &imr->imr_multiaddr); + if(optname == IP_ADD_MEMBERSHIP){ + data->err = igmp_joingroup(&if_addr, &multi_addr); + } else { + data->err = igmp_leavegroup(&if_addr, &multi_addr); + } + if(data->err != ERR_OK) { + data->err = EADDRNOTAVAIL; + } + } + break; +#endif /* LWIP_IGMP */ + default: + LWIP_ASSERT("unhandled optname", 0); + break; + } /* switch (optname) */ + break; + +#if LWIP_TCP +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + switch (optname) { + case TCP_NODELAY: + if (*(int*)optval) { + tcp_nagle_disable(sock->conn->pcb.tcp); + } else { + tcp_nagle_enable(sock->conn->pcb.tcp); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", + s, (*(int *)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + sock->conn->pcb.tcp->keep_idle = (u32_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_idle)); + break; + +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + sock->conn->pcb.tcp->keep_idle = 1000*(u32_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_idle)); + break; + case TCP_KEEPINTVL: + sock->conn->pcb.tcp->keep_intvl = 1000*(u32_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_intvl)); + break; + case TCP_KEEPCNT: + sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_cnt)); + break; +#endif /* LWIP_TCP_KEEPALIVE */ + default: + LWIP_ASSERT("unhandled optname", 0); + break; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP*/ +#if LWIP_UDP && LWIP_UDPLITE + /* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + switch (optname) { + case UDPLITE_SEND_CSCOV: + if (((*(int*)optval != 0) && ((*(int*)optval < 8)) ) || (*(int*)optval > 0xffff)) { + /* don't allow illegal values! */ + sock->conn->pcb.udp->chksum_len_tx = 8; + } else { + sock->conn->pcb.udp->chksum_len_tx = (u16_t)*(int*)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n", + s, (*(int*)optval)) ); + break; + case UDPLITE_RECV_CSCOV: + if (((*(int*)optval != 0) && ((*(int*)optval < 8))) || (*(int*)optval > 0xffff)) { + /* don't allow illegal values! */ + sock->conn->pcb.udp->chksum_len_rx = 8; + } else { + sock->conn->pcb.udp->chksum_len_rx = (u16_t)*(int*)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n", + s, (*(int*)optval)) ); + break; + default: + LWIP_ASSERT("unhandled optname", 0); + break; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP */ + default: + LWIP_ASSERT("unhandled level", 0); + break; + } /* switch (level) */ + sys_sem_signal(&sock->conn->op_completed); +} + +int +lwip_ioctl(int s, long cmd, void *argp) +{ + struct lwip_sock *sock = get_socket(s); + u8_t val; +#if LWIP_SO_RCVBUF + u16_t buflen = 0; + s16_t recv_avail; +#endif /* LWIP_SO_RCVBUF */ + + if (!sock) { + return -1; + } + + switch (cmd) { +#if LWIP_SO_RCVBUF + case FIONREAD: + if (!argp) { + sock_set_errno(sock, EINVAL); + return -1; + } + + SYS_ARCH_GET(sock->conn->recv_avail, recv_avail); + if (recv_avail < 0) { + recv_avail = 0; + } + *((u16_t*)argp) = (u16_t)recv_avail; + + /* Check if there is data left from the last recv operation. /maq 041215 */ + if (sock->lastdata) { + struct pbuf *p = (struct pbuf *)sock->lastdata; + if (netconn_type(sock->conn) != NETCONN_TCP) { + p = ((struct netbuf *)p)->p; + } + buflen = p->tot_len; + buflen -= sock->lastoffset; + + *((u16_t*)argp) += buflen; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %"U16_F"\n", s, argp, *((u16_t*)argp))); + sock_set_errno(sock, 0); + return 0; +#endif /* LWIP_SO_RCVBUF */ + + case FIONBIO: + val = 0; + if (argp && *(u32_t*)argp) { + val = 1; + } + netconn_set_nonblocking(sock->conn, val); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, val)); + sock_set_errno(sock, 0); + return 0; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + return -1; + } /* switch (cmd) */ +} + +/** A minimal implementation of fcntl. + * Currently only the commands F_GETFL and F_SETFL are implemented. + * Only the flag O_NONBLOCK is implemented. + */ +int +lwip_fcntl(int s, int cmd, int val) +{ + struct lwip_sock *sock = get_socket(s); + int ret = -1; + + if (!sock || !sock->conn) { + return -1; + } + + switch (cmd) { + case F_GETFL: + ret = netconn_is_nonblocking(sock->conn) ? O_NONBLOCK : 0; + break; + case F_SETFL: + if ((val & ~O_NONBLOCK) == 0) { + /* only O_NONBLOCK, all other bits are zero */ + netconn_set_nonblocking(sock->conn, val & O_NONBLOCK); + ret = 0; + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_fcntl(%d, UNIMPL: %d, %d)\n", s, cmd, val)); + break; + } + return ret; +} + +#endif /* LWIP_SOCKET */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/tcpip.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/tcpip.c new file mode 100644 index 0000000..857e7d9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/api/tcpip.c @@ -0,0 +1,460 @@ +/** + * @file + * Sequential API Main thread module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/memp.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/tcpip.h" +#include "lwip/init.h" +#include "netif/etharp.h" +#include "netif/ppp_oe.h" + +/* global variables */ +static tcpip_init_done_fn tcpip_init_done; +static void *tcpip_init_done_arg; +static sys_mbox_t mbox; + +#if LWIP_TCPIP_CORE_LOCKING +/** The global semaphore to lock the stack. */ +sys_mutex_t lock_tcpip_core; +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + +/** + * The main lwIP thread. This thread has exclusive access to lwIP core functions + * (unless access to them is not locked). Other threads communicate with this + * thread using message boxes. + * + * It also starts all the timers to make sure they are running in the right + * thread context. + * + * @param arg unused argument + */ +static void +tcpip_thread(void *arg) +{ + struct tcpip_msg *msg; + LWIP_UNUSED_ARG(arg); + + if (tcpip_init_done != NULL) { + tcpip_init_done(tcpip_init_done_arg); + } + + LOCK_TCPIP_CORE(); + while (1) { /* MAIN Loop */ + UNLOCK_TCPIP_CORE(); + LWIP_TCPIP_THREAD_ALIVE(); + /* wait for a message, timeouts are processed while waiting */ + sys_timeouts_mbox_fetch(&mbox, (void **)&msg); + LOCK_TCPIP_CORE(); + switch (msg->type) { +#if LWIP_NETCONN + case TCPIP_MSG_API: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg)); + msg->msg.apimsg->function(&(msg->msg.apimsg->msg)); + break; +#endif /* LWIP_NETCONN */ + +#if !LWIP_TCPIP_CORE_LOCKING_INPUT + case TCPIP_MSG_INPKT: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg)); +#if LWIP_ETHERNET + if (msg->msg.inp.netif->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) { + ethernet_input(msg->msg.inp.p, msg->msg.inp.netif); + } else +#endif /* LWIP_ETHERNET */ + { + ip_input(msg->msg.inp.p, msg->msg.inp.netif); + } + memp_free(MEMP_TCPIP_MSG_INPKT, msg); + break; +#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */ + +#if LWIP_NETIF_API + case TCPIP_MSG_NETIFAPI: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: Netif API message %p\n", (void *)msg)); + msg->msg.netifapimsg->function(&(msg->msg.netifapimsg->msg)); + break; +#endif /* LWIP_NETIF_API */ + + case TCPIP_MSG_CALLBACK: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); + msg->msg.cb.function(msg->msg.cb.ctx); + memp_free(MEMP_TCPIP_MSG_API, msg); + break; + +#if LWIP_TCPIP_TIMEOUT + case TCPIP_MSG_TIMEOUT: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: TIMEOUT %p\n", (void *)msg)); + sys_timeout(msg->msg.tmo.msecs, msg->msg.tmo.h, msg->msg.tmo.arg); + memp_free(MEMP_TCPIP_MSG_API, msg); + break; + case TCPIP_MSG_UNTIMEOUT: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: UNTIMEOUT %p\n", (void *)msg)); + sys_untimeout(msg->msg.tmo.h, msg->msg.tmo.arg); + memp_free(MEMP_TCPIP_MSG_API, msg); + break; +#endif /* LWIP_TCPIP_TIMEOUT */ + + default: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type)); + LWIP_ASSERT("tcpip_thread: invalid message", 0); + break; + } + } +} + +/** + * Pass a received packet to tcpip_thread for input processing + * + * @param p the received packet, p->payload pointing to the Ethernet header or + * to an IP header (if inp doesn't have NETIF_FLAG_ETHARP or + * NETIF_FLAG_ETHERNET flags) + * @param inp the network interface on which the packet was received + */ +err_t +tcpip_input(struct pbuf *p, struct netif *inp) +{ +#if LWIP_TCPIP_CORE_LOCKING_INPUT + err_t ret; + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_input: PACKET %p/%p\n", (void *)p, (void *)inp)); + LOCK_TCPIP_CORE(); +#if LWIP_ETHERNET + if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) { + ret = ethernet_input(p, inp); + } else +#endif /* LWIP_ETHERNET */ + { + ret = ip_input(p, inp); + } + UNLOCK_TCPIP_CORE(); + return ret; +#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */ + struct tcpip_msg *msg; + + if (sys_mbox_valid(&mbox)) { + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_INPKT; + msg->msg.inp.p = p; + msg->msg.inp.netif = inp; + if (sys_mbox_trypost(&mbox, msg) != ERR_OK) { + memp_free(MEMP_TCPIP_MSG_INPKT, msg); + return ERR_MEM; + } + return ERR_OK; + } + return ERR_VAL; +#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */ +} + +/** + * Call a specific function in the thread context of + * tcpip_thread for easy access synchronization. + * A function called in that way may access lwIP core code + * without fearing concurrent access. + * + * @param f the function to call + * @param ctx parameter passed to f + * @param block 1 to block until the request is posted, 0 to non-blocking mode + * @return ERR_OK if the function was called, another err_t if not + */ +err_t +tcpip_callback_with_block(tcpip_callback_fn function, void *ctx, u8_t block) +{ + struct tcpip_msg *msg; + + if (sys_mbox_valid(&mbox)) { + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_CALLBACK; + msg->msg.cb.function = function; + msg->msg.cb.ctx = ctx; + if (block) { + sys_mbox_post(&mbox, msg); + } else { + if (sys_mbox_trypost(&mbox, msg) != ERR_OK) { + memp_free(MEMP_TCPIP_MSG_API, msg); + return ERR_MEM; + } + } + return ERR_OK; + } + return ERR_VAL; +} + +#if LWIP_TCPIP_TIMEOUT +/** + * call sys_timeout in tcpip_thread + * + * @param msec time in milliseconds for timeout + * @param h function to be called on timeout + * @param arg argument to pass to timeout function h + * @return ERR_MEM on memory error, ERR_OK otherwise + */ +err_t +tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg) +{ + struct tcpip_msg *msg; + + if (sys_mbox_valid(&mbox)) { + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_TIMEOUT; + msg->msg.tmo.msecs = msecs; + msg->msg.tmo.h = h; + msg->msg.tmo.arg = arg; + sys_mbox_post(&mbox, msg); + return ERR_OK; + } + return ERR_VAL; +} + +/** + * call sys_untimeout in tcpip_thread + * + * @param msec time in milliseconds for timeout + * @param h function to be called on timeout + * @param arg argument to pass to timeout function h + * @return ERR_MEM on memory error, ERR_OK otherwise + */ +err_t +tcpip_untimeout(sys_timeout_handler h, void *arg) +{ + struct tcpip_msg *msg; + + if (sys_mbox_valid(&mbox)) { + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_UNTIMEOUT; + msg->msg.tmo.h = h; + msg->msg.tmo.arg = arg; + sys_mbox_post(&mbox, msg); + return ERR_OK; + } + return ERR_VAL; +} +#endif /* LWIP_TCPIP_TIMEOUT */ + +#if LWIP_NETCONN +/** + * Call the lower part of a netconn_* function + * This function is then running in the thread context + * of tcpip_thread and has exclusive access to lwIP core code. + * + * @param apimsg a struct containing the function to call and its parameters + * @return ERR_OK if the function was called, another err_t if not + */ +err_t +tcpip_apimsg(struct api_msg *apimsg) +{ + struct tcpip_msg msg; +#ifdef LWIP_DEBUG + /* catch functions that don't set err */ + apimsg->msg.err = ERR_VAL; +#endif + + if (sys_mbox_valid(&mbox)) { + msg.type = TCPIP_MSG_API; + msg.msg.apimsg = apimsg; + sys_mbox_post(&mbox, &msg); + sys_arch_sem_wait(&apimsg->msg.conn->op_completed, 0); + return apimsg->msg.err; + } + return ERR_VAL; +} + +#if LWIP_TCPIP_CORE_LOCKING +/** + * Call the lower part of a netconn_* function + * This function has exclusive access to lwIP core code by locking it + * before the function is called. + * + * @param apimsg a struct containing the function to call and its parameters + * @return ERR_OK (only for compatibility fo tcpip_apimsg()) + */ +err_t +tcpip_apimsg_lock(struct api_msg *apimsg) +{ +#ifdef LWIP_DEBUG + /* catch functions that don't set err */ + apimsg->msg.err = ERR_VAL; +#endif + + LOCK_TCPIP_CORE(); + apimsg->function(&(apimsg->msg)); + UNLOCK_TCPIP_CORE(); + return apimsg->msg.err; + +} +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETCONN */ + +#if LWIP_NETIF_API +#if !LWIP_TCPIP_CORE_LOCKING +/** + * Much like tcpip_apimsg, but calls the lower part of a netifapi_* + * function. + * + * @param netifapimsg a struct containing the function to call and its parameters + * @return error code given back by the function that was called + */ +err_t +tcpip_netifapi(struct netifapi_msg* netifapimsg) +{ + struct tcpip_msg msg; + + if (sys_mbox_valid(&mbox)) { + err_t err = sys_sem_new(&netifapimsg->msg.sem, 0); + if (err != ERR_OK) { + netifapimsg->msg.err = err; + return err; + } + + msg.type = TCPIP_MSG_NETIFAPI; + msg.msg.netifapimsg = netifapimsg; + sys_mbox_post(&mbox, &msg); + sys_sem_wait(&netifapimsg->msg.sem); + sys_sem_free(&netifapimsg->msg.sem); + return netifapimsg->msg.err; + } + return ERR_VAL; +} +#else /* !LWIP_TCPIP_CORE_LOCKING */ +/** + * Call the lower part of a netifapi_* function + * This function has exclusive access to lwIP core code by locking it + * before the function is called. + * + * @param netifapimsg a struct containing the function to call and its parameters + * @return ERR_OK (only for compatibility fo tcpip_netifapi()) + */ +err_t +tcpip_netifapi_lock(struct netifapi_msg* netifapimsg) +{ + LOCK_TCPIP_CORE(); + netifapimsg->function(&(netifapimsg->msg)); + UNLOCK_TCPIP_CORE(); + return netifapimsg->msg.err; +} +#endif /* !LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETIF_API */ + +/** + * Initialize this module: + * - initialize all sub modules + * - start the tcpip_thread + * + * @param initfunc a function to call when tcpip_thread is running and finished initializing + * @param arg argument to pass to initfunc + */ +void +tcpip_init(tcpip_init_done_fn initfunc, void *arg) +{ + lwip_init(); + + tcpip_init_done = initfunc; + tcpip_init_done_arg = arg; + if(sys_mbox_new(&mbox, TCPIP_MBOX_SIZE) != ERR_OK) { + LWIP_ASSERT("failed to create tcpip_thread mbox", 0); + } +#if LWIP_TCPIP_CORE_LOCKING + if(sys_mutex_new(&lock_tcpip_core) != ERR_OK) { + LWIP_ASSERT("failed to create lock_tcpip_core", 0); + } +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO); +} + +/** + * Simple callback function used with tcpip_callback to free a pbuf + * (pbuf_free has a wrong signature for tcpip_callback) + * + * @param p The pbuf (chain) to be dereferenced. + */ +static void +pbuf_free_int(void *p) +{ + struct pbuf *q = (struct pbuf *)p; + pbuf_free(q); +} + +/** + * A simple wrapper function that allows you to free a pbuf from interrupt context. + * + * @param p The pbuf (chain) to be dereferenced. + * @return ERR_OK if callback could be enqueued, an err_t if not + */ +err_t +pbuf_free_callback(struct pbuf *p) +{ + return tcpip_callback_with_block(pbuf_free_int, p, 0); +} + +/** + * A simple wrapper function that allows you to free heap memory from + * interrupt context. + * + * @param m the heap memory to free + * @return ERR_OK if callback could be enqueued, an err_t if not + */ +err_t +mem_free_callback(void *m) +{ + return tcpip_callback_with_block(mem_free, m, 0); +} + +#endif /* !NO_SYS */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/def.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/def.c new file mode 100644 index 0000000..352b552 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/def.c @@ -0,0 +1,108 @@ +/** + * @file + * Common functions used throughout the stack. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "lwip/opt.h" +#include "lwip/def.h" + +/** + * These are reference implementations of the byte swapping functions. + * Again with the aim of being simple, correct and fully portable. + * Byte swapping is the second thing you would want to optimize. You will + * need to port it to your architecture and in your cc.h: + * + * #define LWIP_PLATFORM_BYTESWAP 1 + * #define LWIP_PLATFORM_HTONS(x) + * #define LWIP_PLATFORM_HTONL(x) + * + * Note ntohs() and ntohl() are merely references to the htonx counterparts. + */ + +#if (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) + +/** + * Convert an u16_t from host- to network byte order. + * + * @param n u16_t in host byte order + * @return n in network byte order + */ +u16_t +lwip_htons(u16_t n) +{ + return ((n & 0xff) << 8) | ((n & 0xff00) >> 8); +} + +/** + * Convert an u16_t from network- to host byte order. + * + * @param n u16_t in network byte order + * @return n in host byte order + */ +u16_t +lwip_ntohs(u16_t n) +{ + return lwip_htons(n); +} + +/** + * Convert an u32_t from host- to network byte order. + * + * @param n u32_t in host byte order + * @return n in network byte order + */ +u32_t +lwip_htonl(u32_t n) +{ + return ((n & 0xff) << 24) | + ((n & 0xff00) << 8) | + ((n & 0xff0000UL) >> 8) | + ((n & 0xff000000UL) >> 24); +} + +/** + * Convert an u32_t from network- to host byte order. + * + * @param n u32_t in network byte order + * @return n in host byte order + */ +u32_t +lwip_ntohl(u32_t n) +{ + return lwip_htonl(n); +} + +#endif /* (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/dhcp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/dhcp.c new file mode 100644 index 0000000..81b4be2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/dhcp.c @@ -0,0 +1,1745 @@ +/** + * @file + * Dynamic Host Configuration Protocol client + * + */ + +/* + * + * Copyright (c) 2001-2004 Leon Woestenberg + * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. + * + * Author: Leon Woestenberg + * + * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform + * with RFC 2131 and RFC 2132. + * + * TODO: + * - Support for interfaces other than Ethernet (SLIP, PPP, ...) + * + * Please coordinate changes and requests with Leon Woestenberg + * + * + * Integration with your code: + * + * In lwip/dhcp.h + * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute) + * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer) + * + * Then have your application call dhcp_coarse_tmr() and + * dhcp_fine_tmr() on the defined intervals. + * + * dhcp_start(struct netif *netif); + * starts a DHCP client instance which configures the interface by + * obtaining an IP address lease and maintaining it. + * + * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif) + * to remove the DHCP client. + * + */ + +#include "lwip/opt.h" + +#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/stats.h" +#include "lwip/mem.h" +#include "lwip/udp.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/def.h" +#include "lwip/sys.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" +#include "lwip/dns.h" +#include "netif/etharp.h" + +#include + +/** Default for DHCP_GLOBAL_XID is 0xABCD0000 + * This can be changed by defining DHCP_GLOBAL_XID and DHCP_GLOBAL_XID_HEADER, e.g. + * #define DHCP_GLOBAL_XID_HEADER "stdlib.h" + * #define DHCP_GLOBAL_XID rand() + */ +#ifdef DHCP_GLOBAL_XID_HEADER +#include DHCP_GLOBAL_XID_HEADER /* include optional starting XID generation prototypes */ +#endif + +/** DHCP_OPTION_MAX_MSG_SIZE is set to the MTU + * MTU is checked to be big enough in dhcp_start */ +#define DHCP_MAX_MSG_LEN(netif) (netif->mtu) +#define DHCP_MAX_MSG_LEN_MIN_REQUIRED 576 +/** Minimum length for reply before packet is parsed */ +#define DHCP_MIN_REPLY_LEN 44 + +#define REBOOT_TRIES 2 + +/** Option handling: options are parsed in dhcp_parse_reply + * and saved in an array where other functions can load them from. + * This might be moved into the struct dhcp (not necessarily since + * lwIP is single-threaded and the array is only used while in recv + * callback). */ +#define DHCP_OPTION_IDX_OVERLOAD 0 +#define DHCP_OPTION_IDX_MSG_TYPE 1 +#define DHCP_OPTION_IDX_SERVER_ID 2 +#define DHCP_OPTION_IDX_LEASE_TIME 3 +#define DHCP_OPTION_IDX_T1 4 +#define DHCP_OPTION_IDX_T2 5 +#define DHCP_OPTION_IDX_SUBNET_MASK 6 +#define DHCP_OPTION_IDX_ROUTER 7 +#define DHCP_OPTION_IDX_DNS_SERVER 8 +#define DHCP_OPTION_IDX_MAX (DHCP_OPTION_IDX_DNS_SERVER + DNS_MAX_SERVERS) + +/** Holds the decoded option values, only valid while in dhcp_recv. + @todo: move this into struct dhcp? */ +u32_t dhcp_rx_options_val[DHCP_OPTION_IDX_MAX]; +/** Holds a flag which option was received and is contained in dhcp_rx_options_val, + only valid while in dhcp_recv. + @todo: move this into struct dhcp? */ +u8_t dhcp_rx_options_given[DHCP_OPTION_IDX_MAX]; + +#define dhcp_option_given(dhcp, idx) (dhcp_rx_options_given[idx] != 0) +#define dhcp_got_option(dhcp, idx) (dhcp_rx_options_given[idx] = 1) +#define dhcp_clear_option(dhcp, idx) (dhcp_rx_options_given[idx] = 0) +#define dhcp_clear_all_options(dhcp) (memset(dhcp_rx_options_given, 0, sizeof(dhcp_rx_options_given))) +#define dhcp_get_option_value(dhcp, idx) (dhcp_rx_options_val[idx]) +#define dhcp_set_option_value(dhcp, idx, val) (dhcp_rx_options_val[idx] = (val)) + + +/* DHCP client state machine functions */ +static err_t dhcp_discover(struct netif *netif); +static err_t dhcp_select(struct netif *netif); +static void dhcp_bind(struct netif *netif); +#if DHCP_DOES_ARP_CHECK +static err_t dhcp_decline(struct netif *netif); +#endif /* DHCP_DOES_ARP_CHECK */ +static err_t dhcp_rebind(struct netif *netif); +static err_t dhcp_reboot(struct netif *netif); +static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state); + +/* receive, unfold, parse and free incoming messages */ +static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port); + +/* set the DHCP timers */ +static void dhcp_timeout(struct netif *netif); +static void dhcp_t1_timeout(struct netif *netif); +static void dhcp_t2_timeout(struct netif *netif); + +/* build outgoing messages */ +/* create a DHCP message, fill in common headers */ +static err_t dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type); +/* free a DHCP request */ +static void dhcp_delete_msg(struct dhcp *dhcp); +/* add a DHCP option (type, then length in bytes) */ +static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len); +/* add option values */ +static void dhcp_option_byte(struct dhcp *dhcp, u8_t value); +static void dhcp_option_short(struct dhcp *dhcp, u16_t value); +static void dhcp_option_long(struct dhcp *dhcp, u32_t value); +/* always add the DHCP options trailer to end and pad */ +static void dhcp_option_trailer(struct dhcp *dhcp); + +/** + * Back-off the DHCP client (because of a received NAK response). + * + * Back-off the DHCP client because of a received NAK. Receiving a + * NAK means the client asked for something non-sensible, for + * example when it tries to renew a lease obtained on another network. + * + * We clear any existing set IP address and restart DHCP negotiation + * afresh (as per RFC2131 3.2.3). + * + * @param netif the netif under DHCP control + */ +static void +dhcp_handle_nak(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", + (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + /* Set the interface down since the address must no longer be used, as per RFC2131 */ + netif_set_down(netif); + /* remove IP address from interface */ + netif_set_ipaddr(netif, IP_ADDR_ANY); + netif_set_gw(netif, IP_ADDR_ANY); + netif_set_netmask(netif, IP_ADDR_ANY); + /* Change to a defined state */ + dhcp_set_state(dhcp, DHCP_BACKING_OFF); + /* We can immediately restart discovery */ + dhcp_discover(netif); +} + +#if DHCP_DOES_ARP_CHECK +/** + * Checks if the offered IP address is already in use. + * + * It does so by sending an ARP request for the offered address and + * entering CHECKING state. If no ARP reply is received within a small + * interval, the address is assumed to be free for use by us. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_check(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], + (s16_t)netif->name[1])); + dhcp_set_state(dhcp, DHCP_CHECKING); + /* create an ARP query for the offered IP address, expecting that no host + responds, as the IP address should not be in use. */ + result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); + if (result != ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n")); + } + dhcp->tries++; + msecs = 500; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); +} +#endif /* DHCP_DOES_ARP_CHECK */ + +/** + * Remember the configuration offered by a DHCP server. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_handle_offer(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", + (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + /* obtain the server address */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) { + ip4_addr_set_u32(&dhcp->server_ip_addr, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID))); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", + ip4_addr_get_u32(&dhcp->server_ip_addr))); + /* remember offered address */ + ip_addr_copy(dhcp->offered_ip_addr, dhcp->msg_in->yiaddr); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", + ip4_addr_get_u32(&dhcp->offered_ip_addr))); + + dhcp_select(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void*)netif)); + } +} + +/** + * Select a DHCP server offer out of all offers. + * + * Simply select the first offer received. + * + * @param netif the netif under DHCP control + * @return lwIP specific error (see error.h) + */ +static err_t +dhcp_select(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + dhcp_set_state(dhcp, DHCP_REQUESTING); + + /* create and initialize the DHCP message header */ + result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST); + if (result == ERR_OK) { + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); + + /* MUST request the offered IP address */ + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); + + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->server_ip_addr))); + + dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); + dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); + dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); + dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); + dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); + +#if LWIP_NETIF_HOSTNAME + if (netif->hostname != NULL) { + const char *p = (const char*)netif->hostname; + u8_t namelen = (u8_t)strlen(p); + if (namelen > 0) { + LWIP_ASSERT("DHCP: hostname is too long!", namelen < 255); + dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, namelen); + while (*p) { + dhcp_option_byte(dhcp, *p++); + } + } + } +#endif /* LWIP_NETIF_HOSTNAME */ + + dhcp_option_trailer(dhcp); + /* shrink the pbuf to the actual content length */ + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* send broadcast to any DHCP server */ + udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); + dhcp_delete_msg(dhcp); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * The DHCP timer that checks for lease renewal/rebind timeouts. + */ +void +dhcp_coarse_tmr() +{ + struct netif *netif = netif_list; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n")); + /* iterate through all network interfaces */ + while (netif != NULL) { + /* only act on DHCP configured interfaces */ + if (netif->dhcp != NULL) { + /* timer is active (non zero), and triggers (zeroes) now? */ + if (netif->dhcp->t2_timeout-- == 1) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n")); + /* this clients' rebind timeout triggered */ + dhcp_t2_timeout(netif); + /* timer is active (non zero), and triggers (zeroes) now */ + } else if (netif->dhcp->t1_timeout-- == 1) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n")); + /* this clients' renewal timeout triggered */ + dhcp_t1_timeout(netif); + } + } + /* proceed to next netif */ + netif = netif->next; + } +} + +/** + * DHCP transaction timeout handling + * + * A DHCP server is expected to respond within a short period of time. + * This timer checks whether an outstanding DHCP request is timed out. + */ +void +dhcp_fine_tmr() +{ + struct netif *netif = netif_list; + /* loop through netif's */ + while (netif != NULL) { + /* only act on DHCP configured interfaces */ + if (netif->dhcp != NULL) { + /* timer is active (non zero), and is about to trigger now */ + if (netif->dhcp->request_timeout > 1) { + netif->dhcp->request_timeout--; + } + else if (netif->dhcp->request_timeout == 1) { + netif->dhcp->request_timeout--; + /* { netif->dhcp->request_timeout == 0 } */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); + /* this client's request timeout triggered */ + dhcp_timeout(netif); + } + } + /* proceed to next network interface */ + netif = netif->next; + } +} + +/** + * A DHCP negotiation transaction, or ARP request, has timed out. + * + * The timer that was started with the DHCP or ARP request has + * timed out, indicating no response was received in time. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n")); + /* back-off period has passed, or server selection timed out */ + if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n")); + dhcp_discover(netif); + /* receiving the requested lease timed out */ + } else if (dhcp->state == DHCP_REQUESTING) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n")); + if (dhcp->tries <= 5) { + dhcp_select(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n")); + dhcp_release(netif); + dhcp_discover(netif); + } +#if DHCP_DOES_ARP_CHECK + /* received no ARP reply for the offered address (which is good) */ + } else if (dhcp->state == DHCP_CHECKING) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n")); + if (dhcp->tries <= 1) { + dhcp_check(netif); + /* no ARP replies on the offered address, + looks like the IP address is indeed free */ + } else { + /* bind the interface to the offered address */ + dhcp_bind(netif); + } +#endif /* DHCP_DOES_ARP_CHECK */ + } + /* did not get response to renew request? */ + else if (dhcp->state == DHCP_RENEWING) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n")); + /* just retry renewal */ + /* note that the rebind timer will eventually time-out if renew does not work */ + dhcp_renew(netif); + /* did not get response to rebind request? */ + } else if (dhcp->state == DHCP_REBINDING) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n")); + if (dhcp->tries <= 8) { + dhcp_rebind(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n")); + dhcp_release(netif); + dhcp_discover(netif); + } + } else if (dhcp->state == DHCP_REBOOTING) { + if (dhcp->tries < REBOOT_TRIES) { + dhcp_reboot(netif); + } else { + dhcp_discover(netif); + } + } +} + +/** + * The renewal period has timed out. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_t1_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n")); + if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || + (dhcp->state == DHCP_RENEWING)) { + /* just retry to renew - note that the rebind timer (t2) will + * eventually time-out if renew tries fail. */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("dhcp_t1_timeout(): must renew\n")); + /* This slightly different to RFC2131: DHCPREQUEST will be sent from state + DHCP_RENEWING, not DHCP_BOUND */ + dhcp_renew(netif); + } +} + +/** + * The rebind period has timed out. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_t2_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n")); + if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || + (dhcp->state == DHCP_RENEWING)) { + /* just retry to rebind */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("dhcp_t2_timeout(): must rebind\n")); + /* This slightly different to RFC2131: DHCPREQUEST will be sent from state + DHCP_REBINDING, not DHCP_BOUND */ + dhcp_rebind(netif); + } +} + +/** + * Handle a DHCP ACK packet + * + * @param netif the netif under DHCP control + */ +static void +dhcp_handle_ack(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; +#if LWIP_DNS + u8_t n; +#endif /* LWIP_DNS */ + + /* clear options we might not get from the ACK */ + ip_addr_set_zero(&dhcp->offered_sn_mask); + ip_addr_set_zero(&dhcp->offered_gw_addr); +#if LWIP_DHCP_BOOTP_FILE + ip_addr_set_zero(&dhcp->offered_si_addr); +#endif /* LWIP_DHCP_BOOTP_FILE */ + + /* lease time given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) { + /* remember offered lease time */ + dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME); + } + /* renewal period given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) { + /* remember given renewal period */ + dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1); + } else { + /* calculate safe periods for renewal */ + dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2; + } + + /* renewal period given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) { + /* remember given rebind period */ + dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2); + } else { + /* calculate safe periods for rebinding */ + dhcp->offered_t2_rebind = dhcp->offered_t0_lease; + } + + /* (y)our internet address */ + ip_addr_copy(dhcp->offered_ip_addr, dhcp->msg_in->yiaddr); + +#if LWIP_DHCP_BOOTP_FILE + /* copy boot server address, + boot file name copied in dhcp_parse_reply if not overloaded */ + ip_addr_copy(dhcp->offered_si_addr, dhcp->msg_in->siaddr); +#endif /* LWIP_DHCP_BOOTP_FILE */ + + /* subnet mask given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) { + /* remember given subnet mask */ + ip4_addr_set_u32(&dhcp->offered_sn_mask, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK))); + dhcp->subnet_mask_given = 1; + } else { + dhcp->subnet_mask_given = 0; + } + + /* gateway router */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) { + ip4_addr_set_u32(&dhcp->offered_gw_addr, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER))); + } + +#if LWIP_DNS + /* DNS servers */ + n = 0; + while(dhcp_option_given(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n) && (n < DNS_MAX_SERVERS)) { + ip_addr_t dns_addr; + ip4_addr_set_u32(&dns_addr, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n))); + dns_setserver(n, &dns_addr); + n++; + } +#endif /* LWIP_DNS */ +} + +/** Set a statically allocated struct dhcp to work with. + * Using this prevents dhcp_start to allocate it using mem_malloc. + * + * @param netif the netif for which to set the struct dhcp + * @param dhcp (uninitialised) dhcp struct allocated by the application + */ +void +dhcp_set_struct(struct netif *netif, struct dhcp *dhcp) +{ + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("dhcp != NULL", dhcp != NULL); + LWIP_ASSERT("netif already has a struct dhcp set", netif->dhcp == NULL); + + /* clear data structure */ + memset(dhcp, 0, sizeof(struct dhcp)); + /* dhcp_set_state(&dhcp, DHCP_OFF); */ + netif->dhcp = dhcp; +} + +/** Removes a struct dhcp from a netif. + * + * ATTENTION: Only use this when not using dhcp_set_struct() to allocate the + * struct dhcp since the memory is passed back to the heap. + * + * @param netif the netif from which to remove the struct dhcp + */ +void dhcp_cleanup(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", netif != NULL); + + if (netif->dhcp != NULL) { + mem_free(netif->dhcp); + netif->dhcp = NULL; + } +} + +/** + * Start DHCP negotiation for a network interface. + * + * If no DHCP client instance was attached to this interface, + * a new client is created first. If a DHCP client instance + * was already present, it restarts negotiation. + * + * @param netif The lwIP network interface + * @return lwIP error code + * - ERR_OK - No error + * - ERR_MEM - Out of memory + */ +err_t +dhcp_start(struct netif *netif) +{ + struct dhcp *dhcp; + err_t result = ERR_OK; + + LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;); + dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + /* Remove the flag that says this netif is handled by DHCP, + it is set when we succeeded starting. */ + netif->flags &= ~NETIF_FLAG_DHCP; + + /* check hwtype of the netif */ + if ((netif->flags & NETIF_FLAG_ETHARP) == 0) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): No ETHARP netif\n")); + return ERR_ARG; + } + + /* check MTU of the netif */ + if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n")); + return ERR_MEM; + } + + /* no DHCP client attached yet? */ + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting new DHCP client\n")); + dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp)); + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); + return ERR_MEM; + } + /* store this dhcp client in the netif */ + netif->dhcp = dhcp; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp")); + /* already has DHCP client attached */ + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n")); + if (dhcp->pcb != NULL) { + udp_remove(dhcp->pcb); + } + LWIP_ASSERT("pbuf p_out wasn't freed", dhcp->p_out == NULL); + LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL ); + } + + /* clear data structure */ + memset(dhcp, 0, sizeof(struct dhcp)); + /* dhcp_set_state(&dhcp, DHCP_OFF); */ + /* allocate UDP PCB */ + dhcp->pcb = udp_new(); + if (dhcp->pcb == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not obtain pcb\n")); + return ERR_MEM; + } + dhcp->pcb->so_options |= SOF_BROADCAST; + /* set up local and remote port for the pcb */ + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + /* set up the recv callback and argument */ + udp_recv(dhcp->pcb, dhcp_recv, netif); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); + /* (re)start the DHCP negotiation */ + result = dhcp_discover(netif); + if (result != ERR_OK) { + /* free resources allocated above */ + dhcp_stop(netif); + return ERR_MEM; + } + /* Set the flag that says this netif is handled by DHCP. */ + netif->flags |= NETIF_FLAG_DHCP; + return result; +} + +/** + * Inform a DHCP server of our manual configuration. + * + * This informs DHCP servers of our fixed IP address configuration + * by sending an INFORM message. It does not involve DHCP address + * configuration, it is just here to be nice to the network. + * + * @param netif The lwIP network interface + */ +void +dhcp_inform(struct netif *netif) +{ + struct dhcp dhcp; + err_t result = ERR_OK; + struct udp_pcb *pcb; + + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + + memset(&dhcp, 0, sizeof(struct dhcp)); + dhcp_set_state(&dhcp, DHCP_INFORM); + + if ((netif->dhcp != NULL) && (netif->dhcp->pcb != NULL)) { + /* re-use existing pcb */ + pcb = netif->dhcp->pcb; + } else { + pcb = udp_new(); + if (pcb == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform(): could not obtain pcb")); + return; + } + dhcp.pcb = pcb; + dhcp.pcb->so_options |= SOF_BROADCAST; + udp_bind(dhcp.pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_inform(): created new udp pcb\n")); + } + /* create and initialize the DHCP message header */ + result = dhcp_create_msg(netif, &dhcp, DHCP_INFORM); + if (result == ERR_OK) { + dhcp_option(&dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(&dhcp, DHCP_MAX_MSG_LEN(netif)); + + dhcp_option_trailer(&dhcp); + + pbuf_realloc(dhcp.p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp.options_out_len); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_inform: INFORMING\n")); + udp_sendto_if(pcb, dhcp.p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); + dhcp_delete_msg(&dhcp); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform: could not allocate DHCP request\n")); + } + + if (dhcp.pcb != NULL) { + /* otherwise, the existing pcb was used */ + udp_remove(dhcp.pcb); + } +} + +/** Handle a possible change in the network configuration. + * + * This enters the REBOOTING state to verify that the currently bound + * address is still valid. + */ +void +dhcp_network_changed(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + if (!dhcp) + return; + switch (dhcp->state) { + case DHCP_REBINDING: + case DHCP_RENEWING: + case DHCP_BOUND: + case DHCP_REBOOTING: + netif_set_down(netif); + dhcp->tries = 0; + dhcp_reboot(netif); + break; + case DHCP_OFF: + /* stay off */ + break; + default: + dhcp->tries = 0; +#if LWIP_DHCP_AUTOIP_COOP + if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { + autoip_stop(netif); + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + dhcp_discover(netif); + break; + } +} + +#if DHCP_DOES_ARP_CHECK +/** + * Match an ARP reply with the offered IP address. + * + * @param netif the network interface on which the reply was received + * @param addr The IP address we received a reply from + */ +void dhcp_arp_reply(struct netif *netif, ip_addr_t *addr) +{ + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n")); + /* is a DHCP client doing an ARP check? */ + if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", + ip4_addr_get_u32(addr))); + /* did a host respond with the address we + were offered by the DHCP server? */ + if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) { + /* we will not accept the offered address */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, + ("dhcp_arp_reply(): arp reply matched with offered address, declining\n")); + dhcp_decline(netif); + } + } +} + +/** + * Decline an offered lease. + * + * Tell the DHCP server we do not accept the offered address. + * One reason to decline the lease is when we find out the address + * is already in use by another host (through ARP). + * + * @param netif the netif under DHCP control + */ +static err_t +dhcp_decline(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result = ERR_OK; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n")); + dhcp_set_state(dhcp, DHCP_BACKING_OFF); + /* create and initialize the DHCP message header */ + result = dhcp_create_msg(netif, dhcp, DHCP_DECLINE); + if (result == ERR_OK) { + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); + + dhcp_option_trailer(dhcp); + /* resize pbuf to reflect true size of options */ + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* per section 4.4.4, broadcast DECLINE messages */ + udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); + dhcp_delete_msg(dhcp); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp_decline: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = 10*1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} +#endif /* DHCP_DOES_ARP_CHECK */ + + +/** + * Start the DHCP process, discover a DHCP server. + * + * @param netif the netif under DHCP control + */ +static err_t +dhcp_discover(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result = ERR_OK; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n")); + ip_addr_set_any(&dhcp->offered_ip_addr); + dhcp_set_state(dhcp, DHCP_SELECTING); + /* create and initialize the DHCP message header */ + result = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER); + if (result == ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n")); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); + + dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); + dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); + dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); + dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); + dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); + + dhcp_option_trailer(dhcp); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: realloc()ing\n")); + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n")); + udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n")); + dhcp_delete_msg(dhcp); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n")); + } + dhcp->tries++; +#if LWIP_DHCP_AUTOIP_COOP + if(dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) { + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON; + autoip_start(netif); + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + + +/** + * Bind the interface to the offered IP address. + * + * @param netif network interface to bind to the offered address + */ +static void +dhcp_bind(struct netif *netif) +{ + u32_t timeout; + struct dhcp *dhcp; + ip_addr_t sn_mask, gw_addr; + LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;); + dhcp = netif->dhcp; + LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + /* temporary DHCP lease? */ + if (dhcp->offered_t1_renew != 0xffffffffUL) { + /* set renewal period timer */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); + timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if(timeout > 0xffff) { + timeout = 0xffff; + } + dhcp->t1_timeout = (u16_t)timeout; + if (dhcp->t1_timeout == 0) { + dhcp->t1_timeout = 1; + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000)); + } + /* set renewal period timer */ + if (dhcp->offered_t2_rebind != 0xffffffffUL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); + timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if(timeout > 0xffff) { + timeout = 0xffff; + } + dhcp->t2_timeout = (u16_t)timeout; + if (dhcp->t2_timeout == 0) { + dhcp->t2_timeout = 1; + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000)); + } + + if (dhcp->subnet_mask_given) { + /* copy offered network mask */ + ip_addr_copy(sn_mask, dhcp->offered_sn_mask); + } else { + /* subnet mask not given, choose a safe subnet mask given the network class */ + u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr); + if (first_octet <= 127) { + ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL)); + } else if (first_octet >= 192) { + ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL)); + } else { + ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL)); + } + } + + ip_addr_copy(gw_addr, dhcp->offered_gw_addr); + /* gateway address not given? */ + if (ip_addr_isany(&gw_addr)) { + /* copy network address */ + ip_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask); + /* use first host address on network as gateway */ + ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL)); + } + +#if LWIP_DHCP_AUTOIP_COOP + if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { + autoip_stop(netif); + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", + ip4_addr_get_u32(&dhcp->offered_ip_addr))); + netif_set_ipaddr(netif, &dhcp->offered_ip_addr); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", + ip4_addr_get_u32(&sn_mask))); + netif_set_netmask(netif, &sn_mask); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", + ip4_addr_get_u32(&gw_addr))); + netif_set_gw(netif, &gw_addr); + /* bring the interface up */ + netif_set_up(netif); + /* netif is now bound to DHCP leased address */ + dhcp_set_state(dhcp, DHCP_BOUND); +} + +/** + * Renew an existing DHCP lease at the involved DHCP server. + * + * @param netif network interface which must renew its lease + */ +err_t +dhcp_renew(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n")); + dhcp_set_state(dhcp, DHCP_RENEWING); + + /* create and initialize the DHCP message header */ + result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST); + if (result == ERR_OK) { + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); + +#if LWIP_NETIF_HOSTNAME + if (netif->hostname != NULL) { + const char *p = (const char*)netif->hostname; + u8_t namelen = (u8_t)strlen(p); + if (namelen > 0) { + LWIP_ASSERT("DHCP: hostname is too long!", namelen < 255); + dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, namelen); + while (*p) { + dhcp_option_byte(dhcp, *p++); + } + } + } +#endif /* LWIP_NETIF_HOSTNAME */ + +#if 0 + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); +#endif + +#if 0 + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); +#endif + /* append DHCP message trailer */ + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif); + dhcp_delete_msg(dhcp); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n")); + } + dhcp->tries++; + /* back-off on retries, but to a maximum of 20 seconds */ + msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * Rebind with a DHCP server for an existing DHCP lease. + * + * @param netif network interface which must rebind with a DHCP server + */ +static err_t +dhcp_rebind(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n")); + dhcp_set_state(dhcp, DHCP_REBINDING); + + /* create and initialize the DHCP message header */ + result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST); + if (result == ERR_OK) { + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif)); + +#if LWIP_NETIF_HOSTNAME + if (netif->hostname != NULL) { + const char *p = (const char*)netif->hostname; + u8_t namelen = (u8_t)strlen(p); + if (namelen > 0) { + LWIP_ASSERT("DHCP: hostname is too long!", namelen < 255); + dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, namelen); + while (*p) { + dhcp_option_byte(dhcp, *p++); + } + } + } +#endif /* LWIP_NETIF_HOSTNAME */ + +#if 0 + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); + + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); +#endif + + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* broadcast to server */ + udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); + dhcp_delete_msg(dhcp); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * Enter REBOOTING state to verify an existing lease + * + * @param netif network interface which must reboot + */ +static err_t +dhcp_reboot(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n")); + dhcp_set_state(dhcp, DHCP_REBOOTING); + + /* create and initialize the DHCP message header */ + result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST); + if (result == ERR_OK) { + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); + + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* broadcast to server */ + udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif); + dhcp_delete_msg(dhcp); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + + +/** + * Release a DHCP lease. + * + * @param netif network interface which must release its lease + */ +err_t +dhcp_release(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release()\n")); + + /* idle DHCP client */ + dhcp_set_state(dhcp, DHCP_OFF); + /* clean old DHCP offer */ + ip_addr_set_zero(&dhcp->server_ip_addr); + ip_addr_set_zero(&dhcp->offered_ip_addr); + ip_addr_set_zero(&dhcp->offered_sn_mask); + ip_addr_set_zero(&dhcp->offered_gw_addr); +#if LWIP_DHCP_BOOTP_FILE + ip_addr_set_zero(&dhcp->offered_si_addr); +#endif /* LWIP_DHCP_BOOTP_FILE */ + dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; + + /* create and initialize the DHCP message header */ + result = dhcp_create_msg(netif, dhcp, DHCP_RELEASE); + if (result == ERR_OK) { + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif); + dhcp_delete_msg(dhcp); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs)); + /* bring the interface down */ + netif_set_down(netif); + /* remove IP address from interface */ + netif_set_ipaddr(netif, IP_ADDR_ANY); + netif_set_gw(netif, IP_ADDR_ANY); + netif_set_netmask(netif, IP_ADDR_ANY); + + return result; +} + +/** + * Remove the DHCP client from the interface. + * + * @param netif The network interface to stop DHCP on + */ +void +dhcp_stop(struct netif *netif) +{ + struct dhcp *dhcp; + LWIP_ERROR("dhcp_stop: netif != NULL", (netif != NULL), return;); + dhcp = netif->dhcp; + /* Remove the flag that says this netif is handled by DHCP. */ + netif->flags &= ~NETIF_FLAG_DHCP; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_stop()\n")); + /* netif is DHCP configured? */ + if (dhcp != NULL) { +#if LWIP_DHCP_AUTOIP_COOP + if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { + autoip_stop(netif); + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + + if (dhcp->pcb != NULL) { + udp_remove(dhcp->pcb); + dhcp->pcb = NULL; + } + LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL); + dhcp_set_state(dhcp, DHCP_OFF); + } +} + +/* + * Set the DHCP state of a DHCP client. + * + * If the state changed, reset the number of tries. + */ +static void +dhcp_set_state(struct dhcp *dhcp, u8_t new_state) +{ + if (new_state != dhcp->state) { + dhcp->state = new_state; + dhcp->tries = 0; + dhcp->request_timeout = 0; + } +} + +/* + * Concatenate an option type and length field to the outgoing + * DHCP message. + * + */ +static void +dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len) +{ + LWIP_ASSERT("dhcp_option: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = option_type; + dhcp->msg_out->options[dhcp->options_out_len++] = option_len; +} +/* + * Concatenate a single byte to the outgoing DHCP message. + * + */ +static void +dhcp_option_byte(struct dhcp *dhcp, u8_t value) +{ + LWIP_ASSERT("dhcp_option_byte: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = value; +} + +static void +dhcp_option_short(struct dhcp *dhcp, u16_t value) +{ + LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U <= DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff00U) >> 8); + dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t) (value & 0x00ffU); +} + +static void +dhcp_option_long(struct dhcp *dhcp, u32_t value) +{ + LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4U <= DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24); + dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16); + dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8); + dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x000000ffUL)); +} + +/** + * Extract the DHCP message and the DHCP options. + * + * Extract the DHCP message and the DHCP options, each into a contiguous + * piece of memory. As a DHCP message is variable sized by its options, + * and also allows overriding some fields for options, the easy approach + * is to first unfold the options into a conitguous piece of memory, and + * use that further on. + * + */ +static err_t +dhcp_parse_reply(struct dhcp *dhcp, struct pbuf *p) +{ + u8_t *options; + u16_t offset; + u16_t offset_max; + u16_t options_idx; + u16_t options_idx_max; + struct pbuf *q; + int parse_file_as_options = 0; + int parse_sname_as_options = 0; + + /* clear received options */ + dhcp_clear_all_options(dhcp); + /* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */ + if (p->len < DHCP_SNAME_OFS) { + return ERR_BUF; + } + dhcp->msg_in = (struct dhcp_msg *)p->payload; +#if LWIP_DHCP_BOOTP_FILE + /* clear boot file name */ + dhcp->boot_file_name[0] = 0; +#endif /* LWIP_DHCP_BOOTP_FILE */ + + /* parse options */ + + /* start with options field */ + options_idx = DHCP_OPTIONS_OFS; + /* parse options to the end of the received packet */ + options_idx_max = p->tot_len; +again: + q = p; + while((q != NULL) && (options_idx >= q->len)) { + options_idx -= q->len; + options_idx_max -= q->len; + q = q->next; + } + if (q == NULL) { + return ERR_BUF; + } + offset = options_idx; + offset_max = options_idx_max; + options = (u8_t*)q->payload; + /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ + while((q != NULL) && (options[offset] != DHCP_OPTION_END) && (offset < offset_max)) { + u8_t op = options[offset]; + u8_t len; + u8_t decode_len = 0; + int decode_idx = -1; + u16_t val_offset = offset + 2; + /* len byte might be in the next pbuf */ + if (offset + 1 < q->len) { + len = options[offset + 1]; + } else { + len = (q->next != NULL ? ((u8_t*)q->next->payload)[0] : 0); + } + /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ + decode_len = len; + switch(op) { + /* case(DHCP_OPTION_END): handled above */ + case(DHCP_OPTION_PAD): + /* special option: no len encoded */ + decode_len = len = 0; + /* will be increased below */ + offset--; + break; + case(DHCP_OPTION_SUBNET_MASK): + LWIP_ASSERT("len == 4", len == 4); + decode_idx = DHCP_OPTION_IDX_SUBNET_MASK; + break; + case(DHCP_OPTION_ROUTER): + decode_len = 4; /* only copy the first given router */ + LWIP_ASSERT("len >= decode_len", len >= decode_len); + decode_idx = DHCP_OPTION_IDX_ROUTER; + break; + case(DHCP_OPTION_DNS_SERVER): + /* special case: there might be more than one server */ + LWIP_ASSERT("len % 4 == 0", len % 4 == 0); + /* limit number of DNS servers */ + decode_len = LWIP_MIN(len, 4 * DNS_MAX_SERVERS); + LWIP_ASSERT("len >= decode_len", len >= decode_len); + decode_idx = DHCP_OPTION_IDX_DNS_SERVER; + break; + case(DHCP_OPTION_LEASE_TIME): + LWIP_ASSERT("len == 4", len == 4); + decode_idx = DHCP_OPTION_IDX_LEASE_TIME; + break; + case(DHCP_OPTION_OVERLOAD): + LWIP_ASSERT("len == 1", len == 1); + decode_idx = DHCP_OPTION_IDX_OVERLOAD; + break; + case(DHCP_OPTION_MESSAGE_TYPE): + LWIP_ASSERT("len == 1", len == 1); + decode_idx = DHCP_OPTION_IDX_MSG_TYPE; + break; + case(DHCP_OPTION_SERVER_ID): + LWIP_ASSERT("len == 4", len == 4); + decode_idx = DHCP_OPTION_IDX_SERVER_ID; + break; + case(DHCP_OPTION_T1): + LWIP_ASSERT("len == 4", len == 4); + decode_idx = DHCP_OPTION_IDX_T1; + break; + case(DHCP_OPTION_T2): + LWIP_ASSERT("len == 4", len == 4); + decode_idx = DHCP_OPTION_IDX_T2; + break; + default: + decode_len = 0; + LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", op)); + break; + } + offset += len + 2; + if (decode_len > 0) { + u32_t value = 0; + u16_t copy_len; +decode_next: + LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX); + LWIP_ASSERT("option already decoded", !dhcp_option_given(dhcp, decode_idx)); + copy_len = LWIP_MIN(decode_len, 4); + pbuf_copy_partial(q, &value, copy_len, val_offset); + if (decode_len > 4) { + /* decode more than one u32_t */ + LWIP_ASSERT("decode_len % 4 == 0", decode_len % 4 == 0); + dhcp_got_option(dhcp, decode_idx); + dhcp_set_option_value(dhcp, decode_idx, htonl(value)); + decode_len -= 4; + val_offset += 4; + decode_idx++; + goto decode_next; + } else if (decode_len == 4) { + value = ntohl(value); + } else { + LWIP_ASSERT("invalid decode_len", decode_len == 1); + value = ((u8_t*)&value)[0]; + } + dhcp_got_option(dhcp, decode_idx); + dhcp_set_option_value(dhcp, decode_idx, value); + } + if (offset >= q->len) { + offset -= q->len; + offset_max -= q->len; + q = q->next; + options = (u8_t*)q->payload; + } + } + /* is this an overloaded message? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) { + u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD); + dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD); + if (overload == DHCP_OVERLOAD_FILE) { + parse_file_as_options = 1; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n")); + } else if (overload == DHCP_OVERLOAD_SNAME) { + parse_sname_as_options = 1; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n")); + } else if (overload == DHCP_OVERLOAD_SNAME_FILE) { + parse_sname_as_options = 1; + parse_file_as_options = 1; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload)); + } +#if LWIP_DHCP_BOOTP_FILE + if (!parse_file_as_options) { + /* only do this for ACK messages */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) && + (dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) == DHCP_ACK)) + /* copy bootp file name, don't care for sname (server hostname) */ + pbuf_copy_partial(p, dhcp->boot_file_name, DHCP_FILE_LEN-1, DHCP_FILE_OFS); + /* make sure the string is really NULL-terminated */ + dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0; + } +#endif /* LWIP_DHCP_BOOTP_FILE */ + } + if (parse_file_as_options) { + /* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */ + parse_file_as_options = 0; + options_idx = DHCP_FILE_OFS; + options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN; + goto again; + } else if (parse_sname_as_options) { + parse_sname_as_options = 0; + options_idx = DHCP_SNAME_OFS; + options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN; + goto again; + } + return ERR_OK; +} + +/** + * If an incoming DHCP message is in response to us, then trigger the state machine + */ +static void +dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port) +{ + struct netif *netif = (struct netif *)arg; + struct dhcp *dhcp = netif->dhcp; + struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload; + u8_t msg_type; + u8_t i; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p, + ip4_addr1_16(addr), ip4_addr2_16(addr), ip4_addr3_16(addr), ip4_addr4_16(addr), port)); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); + /* prevent warnings about unused arguments */ + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(addr); + LWIP_UNUSED_ARG(port); + + LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL); + + if (p->len < DHCP_MIN_REPLY_LEN) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n")); + goto free_pbuf_and_return; + } + + if (reply_msg->op != DHCP_BOOTREPLY) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); + goto free_pbuf_and_return; + } + /* iterate through hardware address and match against DHCP message */ + for (i = 0; i < netif->hwaddr_len; i++) { + if (netif->hwaddr[i] != reply_msg->chaddr[i]) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n", + (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); + goto free_pbuf_and_return; + } + } + /* match transaction ID against what we expected */ + if (ntohl(reply_msg->xid) != dhcp->xid) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",ntohl(reply_msg->xid),dhcp->xid)); + goto free_pbuf_and_return; + } + /* option fields could be unfold? */ + if (dhcp_parse_reply(dhcp, p) != ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("problem unfolding DHCP message - too short on memory?\n")); + goto free_pbuf_and_return; + } + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n")); + /* obtain pointer to DHCP message type */ + if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n")); + goto free_pbuf_and_return; + } + + /* read DHCP message type */ + msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE); + /* message type is DHCP ACK? */ + if (msg_type == DHCP_ACK) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n")); + /* in requesting state? */ + if (dhcp->state == DHCP_REQUESTING) { + dhcp_handle_ack(netif); +#if DHCP_DOES_ARP_CHECK + /* check if the acknowledged lease address is already in use */ + dhcp_check(netif); +#else + /* bind interface to the acknowledged lease address */ + dhcp_bind(netif); +#endif + } + /* already bound to the given lease address? */ + else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) { + dhcp_bind(netif); + } + } + /* received a DHCP_NAK in appropriate state? */ + else if ((msg_type == DHCP_NAK) && + ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) || + (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING ))) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n")); + dhcp_handle_nak(netif); + } + /* received a DHCP_OFFER in DHCP_SELECTING state? */ + else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_SELECTING state\n")); + dhcp->request_timeout = 0; + /* remember offered lease */ + dhcp_handle_offer(netif); + } +free_pbuf_and_return: + dhcp->msg_in = NULL; + pbuf_free(p); +} + +/** + * Create a DHCP request, fill in common headers + * + * @param netif the netif under DHCP control + * @param dhcp dhcp control struct + * @param message_type message type of the request + */ +static err_t +dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type) +{ + u16_t i; +#ifndef DHCP_GLOBAL_XID + /** default global transaction identifier starting value (easy to match + * with a packet analyser). We simply increment for each new request. + * Predefine DHCP_GLOBAL_XID to a better value or a function call to generate one + * at runtime, any supporting function prototypes can be defined in DHCP_GLOBAL_XID_HEADER */ + static u32_t xid = 0xABCD0000; +#else + static u32_t xid; + static u8_t xid_initialised = 0; + if (!xid_initialised) { + xid = DHCP_GLOBAL_XID; + xid_initialised = !xid_initialised; + } +#endif + LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return ERR_ARG;); + LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return ERR_VAL;); + LWIP_ASSERT("dhcp_create_msg: dhcp->p_out == NULL", dhcp->p_out == NULL); + LWIP_ASSERT("dhcp_create_msg: dhcp->msg_out == NULL", dhcp->msg_out == NULL); + dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM); + if (dhcp->p_out == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp_create_msg(): could not allocate pbuf\n")); + return ERR_MEM; + } + LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg", + (dhcp->p_out->len >= sizeof(struct dhcp_msg))); + + /* reuse transaction identifier in retransmissions */ + if (dhcp->tries == 0) { + xid++; + } + dhcp->xid = xid; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, + ("transaction id xid(%"X32_F")\n", xid)); + + dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload; + + dhcp->msg_out->op = DHCP_BOOTREQUEST; + /* TODO: make link layer independent */ + dhcp->msg_out->htype = DHCP_HTYPE_ETH; + dhcp->msg_out->hlen = netif->hwaddr_len; + dhcp->msg_out->hops = 0; + dhcp->msg_out->xid = htonl(dhcp->xid); + dhcp->msg_out->secs = 0; + /* we don't need the broadcast flag since we can receive unicast traffic + before being fully configured! */ + dhcp->msg_out->flags = 0; + ip_addr_set_zero(&dhcp->msg_out->ciaddr); + /* set ciaddr to netif->ip_addr based on message_type and state */ + if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || + ((message_type == DHCP_REQUEST) && /* DHCP_BOUND not used for sending! */ + ((dhcp->state==DHCP_RENEWING) || dhcp->state==DHCP_REBINDING))) { + ip_addr_copy(dhcp->msg_out->ciaddr, netif->ip_addr); + } + ip_addr_set_zero(&dhcp->msg_out->yiaddr); + ip_addr_set_zero(&dhcp->msg_out->siaddr); + ip_addr_set_zero(&dhcp->msg_out->giaddr); + for (i = 0; i < DHCP_CHADDR_LEN; i++) { + /* copy netif hardware address, pad with zeroes */ + dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/; + } + for (i = 0; i < DHCP_SNAME_LEN; i++) { + dhcp->msg_out->sname[i] = 0; + } + for (i = 0; i < DHCP_FILE_LEN; i++) { + dhcp->msg_out->file[i] = 0; + } + dhcp->msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE); + dhcp->options_out_len = 0; + /* fill options field with an incrementing array (for debugging purposes) */ + for (i = 0; i < DHCP_OPTIONS_LEN; i++) { + dhcp->msg_out->options[i] = (u8_t)i; /* for debugging only, no matter if truncated */ + } + /* Add option MESSAGE_TYPE */ + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, message_type); + return ERR_OK; +} + +/** + * Free previously allocated memory used to send a DHCP request. + * + * @param dhcp the dhcp struct to free the request from + */ +static void +dhcp_delete_msg(struct dhcp *dhcp) +{ + LWIP_ERROR("dhcp_delete_msg: dhcp != NULL", (dhcp != NULL), return;); + LWIP_ASSERT("dhcp_delete_msg: dhcp->p_out != NULL", dhcp->p_out != NULL); + LWIP_ASSERT("dhcp_delete_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL); + if (dhcp->p_out != NULL) { + pbuf_free(dhcp->p_out); + } + dhcp->p_out = NULL; + dhcp->msg_out = NULL; +} + +/** + * Add a DHCP message trailer + * + * Adds the END option to the DHCP message, and if + * necessary, up to three padding bytes. + * + * @param dhcp DHCP state structure + */ +static void +dhcp_option_trailer(struct dhcp *dhcp) +{ + LWIP_ERROR("dhcp_option_trailer: dhcp != NULL", (dhcp != NULL), return;); + LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL); + LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END; + /* packet is too small, or not 4 byte aligned? */ + while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) { + /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */ + LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); + /* add a fill/padding byte */ + dhcp->msg_out->options[dhcp->options_out_len++] = 0; + } +} + +#endif /* LWIP_DHCP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/dns.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/dns.c new file mode 100644 index 0000000..d633612 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/dns.c @@ -0,0 +1,970 @@ +/** + * @file + * DNS - host name to IP address resolver. + * + */ + +/** + + * This file implements a DNS host name to IP address resolver. + + * Port to lwIP from uIP + * by Jim Pettinato April 2007 + + * uIP version Copyright (c) 2002-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * DNS.C + * + * The lwIP DNS resolver functions are used to lookup a host name and + * map it to a numerical IP address. It maintains a list of resolved + * hostnames that can be queried with the dns_lookup() function. + * New hostnames can be resolved using the dns_query() function. + * + * The lwIP version of the resolver also adds a non-blocking version of + * gethostbyname() that will work with a raw API application. This function + * checks for an IP address string first and converts it if it is valid. + * gethostbyname() then does a dns_lookup() to see if the name is + * already in the table. If so, the IP is returned. If not, a query is + * issued and the function returns with a ERR_INPROGRESS status. The app + * using the dns client must then go into a waiting state. + * + * Once a hostname has been resolved (or found to be non-existent), + * the resolver code calls a specified callback function (which + * must be implemented by the module that uses the resolver). + */ + +/*----------------------------------------------------------------------------- + * RFC 1035 - Domain names - implementation and specification + * RFC 2181 - Clarifications to the DNS Specification + *----------------------------------------------------------------------------*/ + +/** @todo: define good default values (rfc compliance) */ +/** @todo: improve answer parsing, more checkings... */ +/** @todo: check RFC1035 - 7.3. Processing responses */ + +/*----------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "lwip/opt.h" + +#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/udp.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/dns.h" + +#include + +/** DNS server IP address */ +#ifndef DNS_SERVER_ADDRESS +#define DNS_SERVER_ADDRESS(ipaddr) (ip4_addr_set_u32(ipaddr, ipaddr_addr("208.67.222.222"))) /* resolver1.opendns.com */ +#endif + +/** DNS server port address */ +#ifndef DNS_SERVER_PORT +#define DNS_SERVER_PORT 53 +#endif + +/** DNS maximum number of retries when asking for a name, before "timeout". */ +#ifndef DNS_MAX_RETRIES +#define DNS_MAX_RETRIES 4 +#endif + +/** DNS resource record max. TTL (one week as default) */ +#ifndef DNS_MAX_TTL +#define DNS_MAX_TTL 604800 +#endif + +/* DNS protocol flags */ +#define DNS_FLAG1_RESPONSE 0x80 +#define DNS_FLAG1_OPCODE_STATUS 0x10 +#define DNS_FLAG1_OPCODE_INVERSE 0x08 +#define DNS_FLAG1_OPCODE_STANDARD 0x00 +#define DNS_FLAG1_AUTHORATIVE 0x04 +#define DNS_FLAG1_TRUNC 0x02 +#define DNS_FLAG1_RD 0x01 +#define DNS_FLAG2_RA 0x80 +#define DNS_FLAG2_ERR_MASK 0x0f +#define DNS_FLAG2_ERR_NONE 0x00 +#define DNS_FLAG2_ERR_NAME 0x03 + +/* DNS protocol states */ +#define DNS_STATE_UNUSED 0 +#define DNS_STATE_NEW 1 +#define DNS_STATE_ASKING 2 +#define DNS_STATE_DONE 3 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** DNS message header */ +struct dns_hdr { + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FIELD(u8_t flags1); + PACK_STRUCT_FIELD(u8_t flags2); + PACK_STRUCT_FIELD(u16_t numquestions); + PACK_STRUCT_FIELD(u16_t numanswers); + PACK_STRUCT_FIELD(u16_t numauthrr); + PACK_STRUCT_FIELD(u16_t numextrarr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define SIZEOF_DNS_HDR 12 + +/** DNS query message structure. + No packing needed: only used locally on the stack. */ +struct dns_query { + /* DNS query record starts with either a domain name or a pointer + to a name already present somewhere in the packet. */ + u16_t type; + u16_t cls; +}; +#define SIZEOF_DNS_QUERY 4 + +/** DNS answer message structure. + No packing needed: only used locally on the stack. */ +struct dns_answer { + /* DNS answer record starts with either a domain name or a pointer + to a name already present somewhere in the packet. */ + u16_t type; + u16_t cls; + u32_t ttl; + u16_t len; +}; +#define SIZEOF_DNS_ANSWER 10 + +/** DNS table entry */ +struct dns_table_entry { + u8_t state; + u8_t numdns; + u8_t tmr; + u8_t retries; + u8_t seqno; + u8_t err; + u32_t ttl; + char name[DNS_MAX_NAME_LENGTH]; + ip_addr_t ipaddr; + /* pointer to callback on DNS query done */ + dns_found_callback found; + void *arg; +}; + +#if DNS_LOCAL_HOSTLIST + +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC +/** Local host-list. For hostnames in this list, no + * external name resolution is performed */ +static struct local_hostlist_entry *local_hostlist_dynamic; +#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/** Defining this allows the local_hostlist_static to be placed in a different + * linker section (e.g. FLASH) */ +#ifndef DNS_LOCAL_HOSTLIST_STORAGE_PRE +#define DNS_LOCAL_HOSTLIST_STORAGE_PRE static +#endif /* DNS_LOCAL_HOSTLIST_STORAGE_PRE */ +/** Defining this allows the local_hostlist_static to be placed in a different + * linker section (e.g. FLASH) */ +#ifndef DNS_LOCAL_HOSTLIST_STORAGE_POST +#define DNS_LOCAL_HOSTLIST_STORAGE_POST +#endif /* DNS_LOCAL_HOSTLIST_STORAGE_POST */ +DNS_LOCAL_HOSTLIST_STORAGE_PRE struct local_hostlist_entry local_hostlist_static[] + DNS_LOCAL_HOSTLIST_STORAGE_POST = DNS_LOCAL_HOSTLIST_INIT; + +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +static void dns_init_local(); +#endif /* DNS_LOCAL_HOSTLIST */ + + +/* forward declarations */ +static void dns_recv(void *s, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port); +static void dns_check_entries(void); + +/*----------------------------------------------------------------------------- + * Globales + *----------------------------------------------------------------------------*/ + +/* DNS variables */ +static struct udp_pcb *dns_pcb; +static u8_t dns_seqno; +static struct dns_table_entry dns_table[DNS_TABLE_SIZE]; +static ip_addr_t dns_servers[DNS_MAX_SERVERS]; +/** Contiguous buffer for processing responses */ +static u8_t dns_payload_buffer[LWIP_MEM_ALIGN_BUFFER(DNS_MSG_SIZE)]; +static u8_t* dns_payload; + +/** + * Initialize the resolver: set up the UDP pcb and configure the default server + * (DNS_SERVER_ADDRESS). + */ +void +dns_init() +{ + ip_addr_t dnsserver; + + dns_payload = (u8_t *)LWIP_MEM_ALIGN(dns_payload_buffer); + + /* initialize default DNS server address */ + DNS_SERVER_ADDRESS(&dnsserver); + + LWIP_DEBUGF(DNS_DEBUG, ("dns_init: initializing\n")); + + /* if dns client not yet initialized... */ + if (dns_pcb == NULL) { + dns_pcb = udp_new(); + + if (dns_pcb != NULL) { + /* initialize DNS table not needed (initialized to zero since it is a + * global variable) */ + LWIP_ASSERT("For implicit initialization to work, DNS_STATE_UNUSED needs to be 0", + DNS_STATE_UNUSED == 0); + + /* initialize DNS client */ + udp_bind(dns_pcb, IP_ADDR_ANY, 0); + udp_recv(dns_pcb, dns_recv, NULL); + + /* initialize default DNS primary server */ + dns_setserver(0, &dnsserver); + } + } +#if DNS_LOCAL_HOSTLIST + dns_init_local(); +#endif +} + +/** + * Initialize one of the DNS servers. + * + * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS + * @param dnsserver IP address of the DNS server to set + */ +void +dns_setserver(u8_t numdns, ip_addr_t *dnsserver) +{ + if ((numdns < DNS_MAX_SERVERS) && (dns_pcb != NULL) && + (dnsserver != NULL) && !ip_addr_isany(dnsserver)) { + dns_servers[numdns] = (*dnsserver); + } +} + +/** + * Obtain one of the currently configured DNS server. + * + * @param numdns the index of the DNS server + * @return IP address of the indexed DNS server or "ip_addr_any" if the DNS + * server has not been configured. + */ +ip_addr_t +dns_getserver(u8_t numdns) +{ + if (numdns < DNS_MAX_SERVERS) { + return dns_servers[numdns]; + } else { + return *IP_ADDR_ANY; + } +} + +/** + * The DNS resolver client timer - handle retries and timeouts and should + * be called every DNS_TMR_INTERVAL milliseconds (every second by default). + */ +void +dns_tmr(void) +{ + if (dns_pcb != NULL) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_tmr: dns_check_entries\n")); + dns_check_entries(); + } +} + +#if DNS_LOCAL_HOSTLIST +static void +dns_init_local() +{ +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) + int i; + struct local_hostlist_entry *entry; + /* Dynamic: copy entries from DNS_LOCAL_HOSTLIST_INIT to list */ + struct local_hostlist_entry local_hostlist_init[] = DNS_LOCAL_HOSTLIST_INIT; + size_t namelen; + for (i = 0; i < sizeof(local_hostlist_init) / sizeof(struct local_hostlist_entry); i++) { + struct local_hostlist_entry *init_entry = &local_hostlist_init[i]; + LWIP_ASSERT("invalid host name (NULL)", init_entry->name != NULL); + namelen = strlen(init_entry->name); + LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN); + entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST); + LWIP_ASSERT("mem-error in dns_init_local", entry != NULL); + if (entry != NULL) { + entry->name = (char*)entry + sizeof(struct local_hostlist_entry); + MEMCPY((char*)entry->name, init_entry->name, namelen); + ((char*)entry->name)[namelen] = 0; + entry->addr = init_entry->addr; + entry->next = local_hostlist_dynamic; + local_hostlist_dynamic = entry; + } + } +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) */ +} + +/** + * Scans the local host-list for a hostname. + * + * @param hostname Hostname to look for in the local host-list + * @return The first IP address for the hostname in the local host-list or + * IPADDR_NONE if not found. + */ +static u32_t +dns_lookup_local(const char *hostname) +{ +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC + struct local_hostlist_entry *entry = local_hostlist_dynamic; + while(entry != NULL) { + if(strcmp(entry->name, hostname) == 0) { + return ip4_addr_get_u32(&entry->addr); + } + entry = entry->next; + } +#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + int i; + for (i = 0; i < sizeof(local_hostlist_static) / sizeof(struct local_hostlist_entry); i++) { + if(strcmp(local_hostlist_static[i].name, hostname) == 0) { + return ip4_addr_get_u32(&local_hostlist_static[i].addr); + } + } +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + return IPADDR_NONE; +} + +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC +/** Remove all entries from the local host-list for a specific hostname + * and/or IP addess + * + * @param hostname hostname for which entries shall be removed from the local + * host-list + * @param addr address for which entries shall be removed from the local host-list + * @return the number of removed entries + */ +int +dns_local_removehost(const char *hostname, const ip_addr_t *addr) +{ + int removed = 0; + struct local_hostlist_entry *entry = local_hostlist_dynamic; + struct local_hostlist_entry *last_entry = NULL; + while (entry != NULL) { + if (((hostname == NULL) || !strcmp(entry->name, hostname)) && + ((addr == NULL) || ip_addr_cmp(&entry->addr, addr))) { + struct local_hostlist_entry *free_entry; + if (last_entry != NULL) { + last_entry->next = entry->next; + } else { + local_hostlist_dynamic = entry->next; + } + free_entry = entry; + entry = entry->next; + memp_free(MEMP_LOCALHOSTLIST, free_entry); + removed++; + } else { + last_entry = entry; + entry = entry->next; + } + } + return removed; +} + +/** + * Add a hostname/IP address pair to the local host-list. + * Duplicates are not checked. + * + * @param hostname hostname of the new entry + * @param addr IP address of the new entry + * @return ERR_OK if succeeded or ERR_MEM on memory error + */ +err_t +dns_local_addhost(const char *hostname, const ip_addr_t *addr) +{ + struct local_hostlist_entry *entry; + size_t namelen; + LWIP_ASSERT("invalid host name (NULL)", hostname != NULL); + namelen = strlen(hostname); + LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN); + entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST); + if (entry == NULL) { + return ERR_MEM; + } + entry->name = (char*)entry + sizeof(struct local_hostlist_entry); + MEMCPY((char*)entry->name, hostname, namelen); + ((char*)entry->name)[namelen] = 0; + ip_addr_copy(entry->addr, *addr); + entry->next = local_hostlist_dynamic; + local_hostlist_dynamic = entry; + return ERR_OK; +} +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC*/ +#endif /* DNS_LOCAL_HOSTLIST */ + +/** + * Look up a hostname in the array of known hostnames. + * + * @note This function only looks in the internal array of known + * hostnames, it does not send out a query for the hostname if none + * was found. The function dns_enqueue() can be used to send a query + * for a hostname. + * + * @param name the hostname to look up + * @return the hostname's IP address, as u32_t (instead of ip_addr_t to + * better check for failure: != IPADDR_NONE) or IPADDR_NONE if the hostname + * was not found in the cached dns_table. + */ +static u32_t +dns_lookup(const char *name) +{ + u8_t i; +#if DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN) + u32_t addr; +#endif /* DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN) */ +#if DNS_LOCAL_HOSTLIST + if ((addr = dns_lookup_local(name)) != IPADDR_NONE) { + return addr; + } +#endif /* DNS_LOCAL_HOSTLIST */ +#ifdef DNS_LOOKUP_LOCAL_EXTERN + if((addr = DNS_LOOKUP_LOCAL_EXTERN(name)) != IPADDR_NONE) { + return addr; + } +#endif /* DNS_LOOKUP_LOCAL_EXTERN */ + + /* Walk through name list, return entry if found. If not, return NULL. */ + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + if ((dns_table[i].state == DNS_STATE_DONE) && + (strcmp(name, dns_table[i].name) == 0)) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_lookup: \"%s\": found = ", name)); + ip_addr_debug_print(DNS_DEBUG, &(dns_table[i].ipaddr)); + LWIP_DEBUGF(DNS_DEBUG, ("\n")); + return ip4_addr_get_u32(&dns_table[i].ipaddr); + } + } + + return IPADDR_NONE; +} + +#if DNS_DOES_NAME_CHECK +/** + * Compare the "dotted" name "query" with the encoded name "response" + * to make sure an answer from the DNS server matches the current dns_table + * entry (otherwise, answers might arrive late for hostname not on the list + * any more). + * + * @param query hostname (not encoded) from the dns_table + * @param response encoded hostname in the DNS response + * @return 0: names equal; 1: names differ + */ +static u8_t +dns_compare_name(unsigned char *query, unsigned char *response) +{ + unsigned char n; + + do { + n = *response++; + /** @see RFC 1035 - 4.1.4. Message compression */ + if ((n & 0xc0) == 0xc0) { + /* Compressed name */ + break; + } else { + /* Not compressed name */ + while (n > 0) { + if ((*query) != (*response)) { + return 1; + } + ++response; + ++query; + --n; + }; + ++query; + } + } while (*response != 0); + + return 0; +} +#endif /* DNS_DOES_NAME_CHECK */ + +/** + * Walk through a compact encoded DNS name and return the end of the name. + * + * @param query encoded DNS name in the DNS server response + * @return end of the name + */ +static unsigned char * +dns_parse_name(unsigned char *query) +{ + unsigned char n; + + do { + n = *query++; + /** @see RFC 1035 - 4.1.4. Message compression */ + if ((n & 0xc0) == 0xc0) { + /* Compressed name */ + break; + } else { + /* Not compressed name */ + while (n > 0) { + ++query; + --n; + }; + } + } while (*query != 0); + + return query + 1; +} + +/** + * Send a DNS query packet. + * + * @param numdns index of the DNS server in the dns_servers table + * @param name hostname to query + * @param id index of the hostname in dns_table, used as transaction ID in the + * DNS query packet + * @return ERR_OK if packet is sent; an err_t indicating the problem otherwise + */ +static err_t +dns_send(u8_t numdns, const char* name, u8_t id) +{ + err_t err; + struct dns_hdr *hdr; + struct dns_query qry; + struct pbuf *p; + char *query, *nptr; + const char *pHostname; + u8_t n; + + LWIP_DEBUGF(DNS_DEBUG, ("dns_send: dns_servers[%"U16_F"] \"%s\": request\n", + (u16_t)(numdns), name)); + LWIP_ASSERT("dns server out of array", numdns < DNS_MAX_SERVERS); + LWIP_ASSERT("dns server has no IP address set", !ip_addr_isany(&dns_servers[numdns])); + + /* if here, we have either a new query or a retry on a previous query to process */ + p = pbuf_alloc(PBUF_TRANSPORT, SIZEOF_DNS_HDR + DNS_MAX_NAME_LENGTH + + SIZEOF_DNS_QUERY, PBUF_RAM); + if (p != NULL) { + LWIP_ASSERT("pbuf must be in one piece", p->next == NULL); + /* fill dns header */ + hdr = (struct dns_hdr*)p->payload; + memset(hdr, 0, SIZEOF_DNS_HDR); + hdr->id = htons(id); + hdr->flags1 = DNS_FLAG1_RD; + hdr->numquestions = PP_HTONS(1); + query = (char*)hdr + SIZEOF_DNS_HDR; + pHostname = name; + --pHostname; + + /* convert hostname into suitable query format. */ + do { + ++pHostname; + nptr = query; + ++query; + for(n = 0; *pHostname != '.' && *pHostname != 0; ++pHostname) { + *query = *pHostname; + ++query; + ++n; + } + *nptr = n; + } while(*pHostname != 0); + *query++='\0'; + + /* fill dns query */ + qry.type = PP_HTONS(DNS_RRTYPE_A); + qry.cls = PP_HTONS(DNS_RRCLASS_IN); + SMEMCPY(query, &qry, SIZEOF_DNS_QUERY); + + /* resize pbuf to the exact dns query */ + pbuf_realloc(p, (u16_t)((query + SIZEOF_DNS_QUERY) - ((char*)(p->payload)))); + + /* connect to the server for faster receiving */ + udp_connect(dns_pcb, &dns_servers[numdns], DNS_SERVER_PORT); + /* send dns packet */ + err = udp_sendto(dns_pcb, p, &dns_servers[numdns], DNS_SERVER_PORT); + + /* free pbuf */ + pbuf_free(p); + } else { + err = ERR_MEM; + } + + return err; +} + +/** + * dns_check_entry() - see if pEntry has not yet been queried and, if so, sends out a query. + * Check an entry in the dns_table: + * - send out query for new entries + * - retry old pending entries on timeout (also with different servers) + * - remove completed entries from the table if their TTL has expired + * + * @param i index of the dns_table entry to check + */ +static void +dns_check_entry(u8_t i) +{ + err_t err; + struct dns_table_entry *pEntry = &dns_table[i]; + + LWIP_ASSERT("array index out of bounds", i < DNS_TABLE_SIZE); + + switch(pEntry->state) { + + case DNS_STATE_NEW: { + /* initialize new entry */ + pEntry->state = DNS_STATE_ASKING; + pEntry->numdns = 0; + pEntry->tmr = 1; + pEntry->retries = 0; + + /* send DNS packet for this entry */ + err = dns_send(pEntry->numdns, pEntry->name, i); + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING, + ("dns_send returned error: %s\n", lwip_strerr(err))); + } + break; + } + + case DNS_STATE_ASKING: { + if (--pEntry->tmr == 0) { + if (++pEntry->retries == DNS_MAX_RETRIES) { + if ((pEntry->numdns+1numdns+1])) { + /* change of server */ + pEntry->numdns++; + pEntry->tmr = 1; + pEntry->retries = 0; + break; + } else { + LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": timeout\n", pEntry->name)); + /* call specified callback function if provided */ + if (pEntry->found) + (*pEntry->found)(pEntry->name, NULL, pEntry->arg); + /* flush this entry */ + pEntry->state = DNS_STATE_UNUSED; + pEntry->found = NULL; + break; + } + } + + /* wait longer for the next retry */ + pEntry->tmr = pEntry->retries; + + /* send DNS packet for this entry */ + err = dns_send(pEntry->numdns, pEntry->name, i); + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING, + ("dns_send returned error: %s\n", lwip_strerr(err))); + } + } + break; + } + + case DNS_STATE_DONE: { + /* if the time to live is nul */ + if (--pEntry->ttl == 0) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": flush\n", pEntry->name)); + /* flush this entry */ + pEntry->state = DNS_STATE_UNUSED; + pEntry->found = NULL; + } + break; + } + case DNS_STATE_UNUSED: + /* nothing to do */ + break; + default: + LWIP_ASSERT("unknown dns_table entry state:", 0); + break; + } +} + +/** + * Call dns_check_entry for each entry in dns_table - check all entries. + */ +static void +dns_check_entries(void) +{ + u8_t i; + + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + dns_check_entry(i); + } +} + +/** + * Receive input function for DNS response packets arriving for the dns UDP pcb. + * + * @params see udp.h + */ +static void +dns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port) +{ + u16_t i; + char *pHostname; + struct dns_hdr *hdr; + struct dns_answer ans; + struct dns_table_entry *pEntry; + u16_t nquestions, nanswers; + + LWIP_UNUSED_ARG(arg); + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(addr); + LWIP_UNUSED_ARG(port); + + /* is the dns message too big ? */ + if (p->tot_len > DNS_MSG_SIZE) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too big\n")); + /* free pbuf and return */ + goto memerr; + } + + /* is the dns message big enough ? */ + if (p->tot_len < (SIZEOF_DNS_HDR + SIZEOF_DNS_QUERY + SIZEOF_DNS_ANSWER)) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too small\n")); + /* free pbuf and return */ + goto memerr; + } + + /* copy dns payload inside static buffer for processing */ + if (pbuf_copy_partial(p, dns_payload, p->tot_len, 0) == p->tot_len) { + /* The ID in the DNS header should be our entry into the name table. */ + hdr = (struct dns_hdr*)dns_payload; + i = htons(hdr->id); + if (i < DNS_TABLE_SIZE) { + pEntry = &dns_table[i]; + if(pEntry->state == DNS_STATE_ASKING) { + /* This entry is now completed. */ + pEntry->state = DNS_STATE_DONE; + pEntry->err = hdr->flags2 & DNS_FLAG2_ERR_MASK; + + /* We only care about the question(s) and the answers. The authrr + and the extrarr are simply discarded. */ + nquestions = htons(hdr->numquestions); + nanswers = htons(hdr->numanswers); + + /* Check for error. If so, call callback to inform. */ + if (((hdr->flags1 & DNS_FLAG1_RESPONSE) == 0) || (pEntry->err != 0) || (nquestions != 1)) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in flags\n", pEntry->name)); + /* call callback to indicate error, clean up memory and return */ + goto responseerr; + } + +#if DNS_DOES_NAME_CHECK + /* Check if the name in the "question" part match with the name in the entry. */ + if (dns_compare_name((unsigned char *)(pEntry->name), (unsigned char *)dns_payload + SIZEOF_DNS_HDR) != 0) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", pEntry->name)); + /* call callback to indicate error, clean up memory and return */ + goto responseerr; + } +#endif /* DNS_DOES_NAME_CHECK */ + + /* Skip the name in the "question" part */ + pHostname = (char *) dns_parse_name((unsigned char *)dns_payload + SIZEOF_DNS_HDR) + SIZEOF_DNS_QUERY; + + while (nanswers > 0) { + /* skip answer resource record's host name */ + pHostname = (char *) dns_parse_name((unsigned char *)pHostname); + + /* Check for IP address type and Internet class. Others are discarded. */ + SMEMCPY(&ans, pHostname, SIZEOF_DNS_ANSWER); + if((ans.type == PP_HTONS(DNS_RRTYPE_A)) && (ans.cls == PP_HTONS(DNS_RRCLASS_IN)) && + (ans.len == PP_HTONS(sizeof(ip_addr_t))) ) { + /* read the answer resource record's TTL, and maximize it if needed */ + pEntry->ttl = ntohl(ans.ttl); + if (pEntry->ttl > DNS_MAX_TTL) { + pEntry->ttl = DNS_MAX_TTL; + } + /* read the IP address after answer resource record's header */ + SMEMCPY(&(pEntry->ipaddr), (pHostname+SIZEOF_DNS_ANSWER), sizeof(ip_addr_t)); + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response = ", pEntry->name)); + ip_addr_debug_print(DNS_DEBUG, (&(pEntry->ipaddr))); + LWIP_DEBUGF(DNS_DEBUG, ("\n")); + /* call specified callback function if provided */ + if (pEntry->found) { + (*pEntry->found)(pEntry->name, &pEntry->ipaddr, pEntry->arg); + } + /* deallocate memory and return */ + goto memerr; + } else { + pHostname = pHostname + SIZEOF_DNS_ANSWER + htons(ans.len); + } + --nanswers; + } + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in response\n", pEntry->name)); + /* call callback to indicate error, clean up memory and return */ + goto responseerr; + } + } + } + + /* deallocate memory and return */ + goto memerr; + +responseerr: + /* ERROR: call specified callback function with NULL as name to indicate an error */ + if (pEntry->found) { + (*pEntry->found)(pEntry->name, NULL, pEntry->arg); + } + /* flush this entry */ + pEntry->state = DNS_STATE_UNUSED; + pEntry->found = NULL; + +memerr: + /* free pbuf */ + pbuf_free(p); + return; +} + +/** + * Queues a new hostname to resolve and sends out a DNS query for that hostname + * + * @param name the hostname that is to be queried + * @param found a callback founction to be called on success, failure or timeout + * @param callback_arg argument to pass to the callback function + * @return @return a err_t return code. + */ +static err_t +dns_enqueue(const char *name, dns_found_callback found, void *callback_arg) +{ + u8_t i; + u8_t lseq, lseqi; + struct dns_table_entry *pEntry = NULL; + size_t namelen; + + /* search an unused entry, or the oldest one */ + lseq = lseqi = 0; + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + pEntry = &dns_table[i]; + /* is it an unused entry ? */ + if (pEntry->state == DNS_STATE_UNUSED) + break; + + /* check if this is the oldest completed entry */ + if (pEntry->state == DNS_STATE_DONE) { + if ((dns_seqno - pEntry->seqno) > lseq) { + lseq = dns_seqno - pEntry->seqno; + lseqi = i; + } + } + } + + /* if we don't have found an unused entry, use the oldest completed one */ + if (i == DNS_TABLE_SIZE) { + if ((lseqi >= DNS_TABLE_SIZE) || (dns_table[lseqi].state != DNS_STATE_DONE)) { + /* no entry can't be used now, table is full */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS entries table is full\n", name)); + return ERR_MEM; + } else { + /* use the oldest completed one */ + i = lseqi; + pEntry = &dns_table[i]; + } + } + + /* use this entry */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS entry %"U16_F"\n", name, (u16_t)(i))); + + /* fill the entry */ + pEntry->state = DNS_STATE_NEW; + pEntry->seqno = dns_seqno++; + pEntry->found = found; + pEntry->arg = callback_arg; + namelen = LWIP_MIN(strlen(name), DNS_MAX_NAME_LENGTH-1); + MEMCPY(pEntry->name, name, namelen); + pEntry->name[namelen] = 0; + + /* force to send query without waiting timer */ + dns_check_entry(i); + + /* dns query is enqueued */ + return ERR_INPROGRESS; +} + +/** + * Resolve a hostname (string) into an IP address. + * NON-BLOCKING callback version for use with raw API!!! + * + * Returns immediately with one of err_t return codes: + * - ERR_OK if hostname is a valid IP address string or the host + * name is already in the local names table. + * - ERR_INPROGRESS enqueue a request to be sent to the DNS server + * for resolution if no errors are present. + * - ERR_ARG: dns client not initialized or invalid hostname + * + * @param hostname the hostname that is to be queried + * @param addr pointer to a ip_addr_t where to store the address if it is already + * cached in the dns_table (only valid if ERR_OK is returned!) + * @param found a callback function to be called on success, failure or timeout (only if + * ERR_INPROGRESS is returned!) + * @param callback_arg argument to pass to the callback function + * @return a err_t return code. + */ +err_t +dns_gethostbyname(const char *hostname, ip_addr_t *addr, dns_found_callback found, + void *callback_arg) +{ + u32_t ipaddr; + /* not initialized or no valid server yet, or invalid addr pointer + * or invalid hostname or invalid hostname length */ + if ((dns_pcb == NULL) || (addr == NULL) || + (!hostname) || (!hostname[0]) || + (strlen(hostname) >= DNS_MAX_NAME_LENGTH)) { + return ERR_ARG; + } + +#if LWIP_HAVE_LOOPIF + if (strcmp(hostname, "localhost")==0) { + ip_addr_set_loopback(addr); + return ERR_OK; + } +#endif /* LWIP_HAVE_LOOPIF */ + + /* host name already in octet notation? set ip addr and return ERR_OK */ + ipaddr = ipaddr_addr(hostname); + if (ipaddr == IPADDR_NONE) { + /* already have this address cached? */ + ipaddr = dns_lookup(hostname); + } + if (ipaddr != IPADDR_NONE) { + ip4_addr_set_u32(addr, ipaddr); + return ERR_OK; + } + + /* queue query with specified callback */ + return dns_enqueue(hostname, found, callback_arg); +} + +#endif /* LWIP_DNS */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/init.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/init.c new file mode 100644 index 0000000..bf5c79d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/init.c @@ -0,0 +1,306 @@ +/** + * @file + * Modules initialization + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/init.h" +#include "lwip/stats.h" +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/sockets.h" +#include "lwip/ip.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/tcp_impl.h" +#include "lwip/snmp_msg.h" +#include "lwip/autoip.h" +#include "lwip/igmp.h" +#include "lwip/dns.h" +#include "lwip/timers.h" +#include "netif/etharp.h" + +/* Compile-time sanity checks for configuration errors. + * These can be done independently of LWIP_DEBUG, without penalty. + */ +#ifndef BYTE_ORDER + #error "BYTE_ORDER is not defined, you have to define it in your cc.h" +#endif +#if (!IP_SOF_BROADCAST && IP_SOF_BROADCAST_RECV) + #error "If you want to use broadcast filter per pcb on recv operations, you have to define IP_SOF_BROADCAST=1 in your lwipopts.h" +#endif +#if (!LWIP_ARP && ARP_QUEUEING) + #error "If you want to use ARP Queueing, you have to define LWIP_ARP=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && LWIP_UDPLITE) + #error "If you want to use UDP Lite, you have to define LWIP_UDP=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && LWIP_SNMP) + #error "If you want to use SNMP, you have to define LWIP_UDP=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && LWIP_DHCP) + #error "If you want to use DHCP, you have to define LWIP_UDP=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && LWIP_IGMP) + #error "If you want to use IGMP, you have to define LWIP_UDP=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && LWIP_SNMP) + #error "If you want to use SNMP, you have to define LWIP_UDP=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && LWIP_DNS) + #error "If you want to use DNS, you have to define LWIP_UDP=1 in your lwipopts.h" +#endif +#if (LWIP_ARP && ARP_QUEUEING && (MEMP_NUM_ARP_QUEUE<=0)) + #error "If you want to use ARP Queueing, you have to define MEMP_NUM_ARP_QUEUE>=1 in your lwipopts.h" +#endif +#if (LWIP_RAW && (MEMP_NUM_RAW_PCB<=0)) + #error "If you want to use RAW, you have to define MEMP_NUM_RAW_PCB>=1 in your lwipopts.h" +#endif +#if (LWIP_UDP && (MEMP_NUM_UDP_PCB<=0)) + #error "If you want to use UDP, you have to define MEMP_NUM_UDP_PCB>=1 in your lwipopts.h" +#endif +#if (LWIP_TCP && (MEMP_NUM_TCP_PCB<=0)) + #error "If you want to use TCP, you have to define MEMP_NUM_TCP_PCB>=1 in your lwipopts.h" +#endif +#if (LWIP_TCP && (TCP_WND > 0xffff)) + #error "If you want to use TCP, TCP_WND must fit in an u16_t, so, you have to reduce it in your lwipopts.h" +#endif +#if (LWIP_TCP && (TCP_SND_QUEUELEN > 0xffff)) + #error "If you want to use TCP, TCP_SND_QUEUELEN must fit in an u16_t, so, you have to reduce it in your lwipopts.h" +#endif +#if (LWIP_TCP && (TCP_SND_QUEUELEN < 2)) + #error "TCP_SND_QUEUELEN must be at least 2 for no-copy TCP writes to work" +#endif +#if (LWIP_TCP && ((TCP_MAXRTX > 12) || (TCP_SYNMAXRTX > 12))) + #error "If you want to use TCP, TCP_MAXRTX and TCP_SYNMAXRTX must less or equal to 12 (due to tcp_backoff table), so, you have to reduce them in your lwipopts.h" +#endif +#if (LWIP_TCP && TCP_LISTEN_BACKLOG && (TCP_DEFAULT_LISTEN_BACKLOG < 0) || (TCP_DEFAULT_LISTEN_BACKLOG > 0xff)) + #error "If you want to use TCP backlog, TCP_DEFAULT_LISTEN_BACKLOG must fit into an u8_t" +#endif +#if (LWIP_IGMP && (MEMP_NUM_IGMP_GROUP<=1)) + #error "If you want to use IGMP, you have to define MEMP_NUM_IGMP_GROUP>1 in your lwipopts.h" +#endif +#if (LWIP_NETIF_API && (NO_SYS==1)) + #error "If you want to use NETIF API, you have to define NO_SYS=0 in your lwipopts.h" +#endif +#if ((LWIP_SOCKET || LWIP_NETCONN) && (NO_SYS==1)) + #error "If you want to use Sequential API, you have to define NO_SYS=0 in your lwipopts.h" +#endif +#if ((LWIP_NETCONN || LWIP_SOCKET) && (MEMP_NUM_TCPIP_MSG_API<=0)) + #error "If you want to use Sequential API, you have to define MEMP_NUM_TCPIP_MSG_API>=1 in your lwipopts.h" +#endif +#if (!LWIP_NETCONN && LWIP_SOCKET) + #error "If you want to use Socket API, you have to define LWIP_NETCONN=1 in your lwipopts.h" +#endif +#if (((!LWIP_DHCP) || (!LWIP_AUTOIP)) && LWIP_DHCP_AUTOIP_COOP) + #error "If you want to use DHCP/AUTOIP cooperation mode, you have to define LWIP_DHCP=1 and LWIP_AUTOIP=1 in your lwipopts.h" +#endif +#if (((!LWIP_DHCP) || (!LWIP_ARP)) && DHCP_DOES_ARP_CHECK) + #error "If you want to use DHCP ARP checking, you have to define LWIP_DHCP=1 and LWIP_ARP=1 in your lwipopts.h" +#endif +#if (!LWIP_ARP && LWIP_AUTOIP) + #error "If you want to use AUTOIP, you have to define LWIP_ARP=1 in your lwipopts.h" +#endif +#if (LWIP_SNMP && (SNMP_CONCURRENT_REQUESTS<=0)) + #error "If you want to use SNMP, you have to define SNMP_CONCURRENT_REQUESTS>=1 in your lwipopts.h" +#endif +#if (LWIP_SNMP && (SNMP_TRAP_DESTINATIONS<=0)) + #error "If you want to use SNMP, you have to define SNMP_TRAP_DESTINATIONS>=1 in your lwipopts.h" +#endif +#if (LWIP_TCP && ((LWIP_EVENT_API && LWIP_CALLBACK_API) || (!LWIP_EVENT_API && !LWIP_CALLBACK_API))) + #error "One and exactly one of LWIP_EVENT_API and LWIP_CALLBACK_API has to be enabled in your lwipopts.h" +#endif +/* There must be sufficient timeouts, taking into account requirements of the subsystems. */ +#if LWIP_TIMERS && (MEMP_NUM_SYS_TIMEOUT < (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT)) + #error "MEMP_NUM_SYS_TIMEOUT is too low to accomodate all required timeouts" +#endif +#if (IP_REASSEMBLY && (MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS)) + #error "MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS doesn't make sense since each struct ip_reassdata must hold 2 pbufs at least!" +#endif +#if (MEM_LIBC_MALLOC && MEM_USE_POOLS) + #error "MEM_LIBC_MALLOC and MEM_USE_POOLS may not both be simultaneously enabled in your lwipopts.h" +#endif +#if (MEM_USE_POOLS && !MEMP_USE_CUSTOM_POOLS) + #error "MEM_USE_POOLS requires custom pools (MEMP_USE_CUSTOM_POOLS) to be enabled in your lwipopts.h" +#endif +#if (PBUF_POOL_BUFSIZE <= MEM_ALIGNMENT) + #error "PBUF_POOL_BUFSIZE must be greater than MEM_ALIGNMENT or the offset may take the full first pbuf" +#endif +#if (TCP_QUEUE_OOSEQ && !LWIP_TCP) + #error "TCP_QUEUE_OOSEQ requires LWIP_TCP" +#endif +#if (DNS_LOCAL_HOSTLIST && !DNS_LOCAL_HOSTLIST_IS_DYNAMIC && !(defined(DNS_LOCAL_HOSTLIST_INIT))) + #error "you have to define define DNS_LOCAL_HOSTLIST_INIT {{'host1', 0x123}, {'host2', 0x234}} to initialize DNS_LOCAL_HOSTLIST" +#endif +#if PPP_SUPPORT && !PPPOS_SUPPORT & !PPPOE_SUPPORT + #error "PPP_SUPPORT needs either PPPOS_SUPPORT or PPPOE_SUPPORT turned on" +#endif +#if !LWIP_ETHERNET && (LWIP_ARP || PPPOE_SUPPORT) + #error "LWIP_ETHERNET needs to be turned on for LWIP_ARP or PPPOE_SUPPORT" +#endif +#if LWIP_IGMP && !defined(LWIP_RAND) + #error "When using IGMP, LWIP_RAND() needs to be defined to a random-function returning an u32_t random value" +#endif +#if LWIP_TCPIP_CORE_LOCKING_INPUT && !LWIP_TCPIP_CORE_LOCKING + #error "When using LWIP_TCPIP_CORE_LOCKING_INPUT, LWIP_TCPIP_CORE_LOCKING must be enabled, too" +#endif +#if LWIP_TCP && LWIP_NETIF_TX_SINGLE_PBUF && !TCP_OVERSIZE + #error "LWIP_NETIF_TX_SINGLE_PBUF needs TCP_OVERSIZE enabled to create single-pbuf TCP packets" +#endif +#if IP_FRAG && IP_FRAG_USES_STATIC_BUF && LWIP_NETIF_TX_SINGLE_PBUF + #error "LWIP_NETIF_TX_SINGLE_PBUF does not work with IP_FRAG_USES_STATIC_BUF==1 as that creates pbuf queues" +#endif + + +/* Compile-time checks for deprecated options. + */ +#ifdef MEMP_NUM_TCPIP_MSG + #error "MEMP_NUM_TCPIP_MSG option is deprecated. Remove it from your lwipopts.h." +#endif +#ifdef MEMP_NUM_API_MSG + #error "MEMP_NUM_API_MSG option is deprecated. Remove it from your lwipopts.h." +#endif +#ifdef TCP_REXMIT_DEBUG + #error "TCP_REXMIT_DEBUG option is deprecated. Remove it from your lwipopts.h." +#endif +#ifdef RAW_STATS + #error "RAW_STATS option is deprecated. Remove it from your lwipopts.h." +#endif +#ifdef ETHARP_QUEUE_FIRST + #error "ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h." +#endif +#ifdef ETHARP_ALWAYS_INSERT + #error "ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h." +#endif + +#ifdef LWIP_DEBUG +static void +lwip_sanity_check(void) +{ + /* Warnings */ +#if LWIP_NETCONN + if (MEMP_NUM_NETCONN > (MEMP_NUM_TCP_PCB+MEMP_NUM_TCP_PCB_LISTEN+MEMP_NUM_UDP_PCB+MEMP_NUM_RAW_PCB)) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_NETCONN should be less than the sum of MEMP_NUM_{TCP,RAW,UDP}_PCB+MEMP_NUM_TCP_PCB_LISTEN\n")); +#endif /* LWIP_NETCONN */ +#if LWIP_TCP + if (MEMP_NUM_TCP_SEG < TCP_SND_QUEUELEN) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_TCP_SEG should be at least as big as TCP_SND_QUEUELEN\n")); + if (TCP_SND_BUF < 2 * TCP_MSS) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SND_BUF must be at least as much as (2 * TCP_MSS) for things to work smoothly\n")); + if (TCP_SND_QUEUELEN < (2 * (TCP_SND_BUF/TCP_MSS))) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SND_QUEUELEN must be at least as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work\n")); + if (TCP_SNDLOWAT >= TCP_SND_BUF) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SNDLOWAT must be less than TCP_SND_BUF.\n")); + if (TCP_SNDQUEUELOWAT >= TCP_SND_QUEUELEN) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SNDQUEUELOWAT must be less than TCP_SND_QUEUELEN.\n")); + if (TCP_WND > (PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE)) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is larger than space provided by PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE\n")); + if (TCP_WND < TCP_MSS) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is smaller than MSS\n")); +#endif /* LWIP_TCP */ +#if LWIP_SOCKET + /* Check that the SO_* socket options and SOF_* lwIP-internal flags match */ + if (SO_ACCEPTCONN != SOF_ACCEPTCONN) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_ACCEPTCONN != SOF_ACCEPTCONN\n")); + if (SO_REUSEADDR != SOF_REUSEADDR) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_REUSEADDR != SOF_REUSEADDR\n")); + if (SO_KEEPALIVE != SOF_KEEPALIVE) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_KEEPALIVE != SOF_KEEPALIVE\n")); + if (SO_BROADCAST != SOF_BROADCAST) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_BROADCAST != SOF_BROADCAST\n")); + if (SO_LINGER != SOF_LINGER) + LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_LINGER != SOF_LINGER\n")); +#endif /* LWIP_SOCKET */ +} +#else /* LWIP_DEBUG */ +#define lwip_sanity_check() +#endif /* LWIP_DEBUG */ + +/** + * Perform Sanity check of user-configurable values, and initialize all modules. + */ +void +lwip_init(void) +{ + /* Sanity check user-configurable values */ + lwip_sanity_check(); + + /* Modules initialization */ + stats_init(); +#if !NO_SYS + sys_init(); +#endif /* !NO_SYS */ + mem_init(); + memp_init(); + pbuf_init(); + netif_init(); +#if LWIP_SOCKET + lwip_socket_init(); +#endif /* LWIP_SOCKET */ + ip_init(); +#if LWIP_ARP + etharp_init(); +#endif /* LWIP_ARP */ +#if LWIP_RAW + raw_init(); +#endif /* LWIP_RAW */ +#if LWIP_UDP + udp_init(); +#endif /* LWIP_UDP */ +#if LWIP_TCP + tcp_init(); +#endif /* LWIP_TCP */ +#if LWIP_SNMP + snmp_init(); +#endif /* LWIP_SNMP */ +#if LWIP_AUTOIP + autoip_init(); +#endif /* LWIP_AUTOIP */ +#if LWIP_IGMP + igmp_init(); +#endif /* LWIP_IGMP */ +#if LWIP_DNS + dns_init(); +#endif /* LWIP_DNS */ + +#if LWIP_TIMERS + sys_timeouts_init(); +#endif /* LWIP_TIMERS */ +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/autoip.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/autoip.c new file mode 100644 index 0000000..92bb459 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/autoip.c @@ -0,0 +1,536 @@ +/** + * @file + * AutoIP Automatic LinkLocal IP Configuration + * + */ + +/* + * + * Copyright (c) 2007 Dominik Spies + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Dominik Spies + * + * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform + * with RFC 3927. + * + * + * Please coordinate changes and requests with Dominik Spies + * + */ + +/******************************************************************************* + * USAGE: + * + * define LWIP_AUTOIP 1 in your lwipopts.h + * + * If you don't use tcpip.c (so, don't call, you don't call tcpip_init): + * - First, call autoip_init(). + * - call autoip_tmr() all AUTOIP_TMR_INTERVAL msces, + * that should be defined in autoip.h. + * I recommend a value of 100. The value must divide 1000 with a remainder almost 0. + * Possible values are 1000, 500, 333, 250, 200, 166, 142, 125, 111, 100 .... + * + * Without DHCP: + * - Call autoip_start() after netif_add(). + * + * With DHCP: + * - define LWIP_DHCP_AUTOIP_COOP 1 in your lwipopts.h. + * - Configure your DHCP Client. + * + */ + +#include "lwip/opt.h" + +#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/mem.h" +#include "lwip/udp.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/autoip.h" +#include "netif/etharp.h" + +#include +#include + +/* 169.254.0.0 */ +#define AUTOIP_NET 0xA9FE0000 +/* 169.254.1.0 */ +#define AUTOIP_RANGE_START (AUTOIP_NET | 0x0100) +/* 169.254.254.255 */ +#define AUTOIP_RANGE_END (AUTOIP_NET | 0xFEFF) + + +/** Pseudo random macro based on netif informations. + * You could use "rand()" from the C Library if you define LWIP_AUTOIP_RAND in lwipopts.h */ +#ifndef LWIP_AUTOIP_RAND +#define LWIP_AUTOIP_RAND(netif) ( (((u32_t)((netif->hwaddr[5]) & 0xff) << 24) | \ + ((u32_t)((netif->hwaddr[3]) & 0xff) << 16) | \ + ((u32_t)((netif->hwaddr[2]) & 0xff) << 8) | \ + ((u32_t)((netif->hwaddr[4]) & 0xff))) + \ + (netif->autoip?netif->autoip->tried_llipaddr:0)) +#endif /* LWIP_AUTOIP_RAND */ + +/** + * Macro that generates the initial IP address to be tried by AUTOIP. + * If you want to override this, define it to something else in lwipopts.h. + */ +#ifndef LWIP_AUTOIP_CREATE_SEED_ADDR +#define LWIP_AUTOIP_CREATE_SEED_ADDR(netif) \ + htonl(AUTOIP_RANGE_START + ((u32_t)(((u8_t)(netif->hwaddr[4])) | \ + ((u32_t)((u8_t)(netif->hwaddr[5]))) << 8))) +#endif /* LWIP_AUTOIP_CREATE_SEED_ADDR */ + +/* static functions */ +static void autoip_handle_arp_conflict(struct netif *netif); + +/* creates a pseudo random LL IP-Address for a network interface */ +static void autoip_create_addr(struct netif *netif, ip_addr_t *ipaddr); + +/* sends an ARP probe */ +static err_t autoip_arp_probe(struct netif *netif); + +/* sends an ARP announce */ +static err_t autoip_arp_announce(struct netif *netif); + +/* configure interface for use with current LL IP-Address */ +static err_t autoip_bind(struct netif *netif); + +/* start sending probes for llipaddr */ +static void autoip_start_probing(struct netif *netif); + +/** + * Initialize this module + */ +void +autoip_init(void) +{ + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_init()\n")); +} + +/** Set a statically allocated struct autoip to work with. + * Using this prevents autoip_start to allocate it using mem_malloc. + * + * @param netif the netif for which to set the struct autoip + * @param dhcp (uninitialised) dhcp struct allocated by the application + */ +void +autoip_set_struct(struct netif *netif, struct autoip *autoip) +{ + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("autoip != NULL", autoip != NULL); + LWIP_ASSERT("netif already has a struct autoip set", netif->autoip == NULL); + + /* clear data structure */ + memset(autoip, 0, sizeof(struct autoip)); + /* autoip->state = AUTOIP_STATE_OFF; */ + netif->autoip = autoip; +} + +/** Restart AutoIP client and check the next address (conflict detected) + * + * @param netif The netif under AutoIP control + */ +static void +autoip_restart(struct netif *netif) +{ + netif->autoip->tried_llipaddr++; + autoip_start(netif); +} + +/** + * Handle a IP address conflict after an ARP conflict detection + */ +static void +autoip_handle_arp_conflict(struct netif *netif) +{ + /* Somehow detect if we are defending or retreating */ + unsigned char defend = 1; /* tbd */ + + if(defend) { + if(netif->autoip->lastconflict > 0) { + /* retreat, there was a conflicting ARP in the last + * DEFEND_INTERVAL seconds + */ + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_handle_arp_conflict(): we are defending, but in DEFEND_INTERVAL, retreating\n")); + + /* TODO: close all TCP sessions */ + autoip_restart(netif); + } else { + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_handle_arp_conflict(): we are defend, send ARP Announce\n")); + autoip_arp_announce(netif); + netif->autoip->lastconflict = DEFEND_INTERVAL * AUTOIP_TICKS_PER_SECOND; + } + } else { + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_handle_arp_conflict(): we do not defend, retreating\n")); + /* TODO: close all TCP sessions */ + autoip_restart(netif); + } +} + +/** + * Create an IP-Address out of range 169.254.1.0 to 169.254.254.255 + * + * @param netif network interface on which create the IP-Address + * @param ipaddr ip address to initialize + */ +static void +autoip_create_addr(struct netif *netif, ip_addr_t *ipaddr) +{ + /* Here we create an IP-Address out of range 169.254.1.0 to 169.254.254.255 + * compliant to RFC 3927 Section 2.1 + * We have 254 * 256 possibilities */ + + u32_t addr = ntohl(LWIP_AUTOIP_CREATE_SEED_ADDR(netif)); + addr += netif->autoip->tried_llipaddr; + addr = AUTOIP_NET | (addr & 0xffff); + /* Now, 169.254.0.0 <= addr <= 169.254.255.255 */ + + if (addr < AUTOIP_RANGE_START) { + addr += AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1; + } + if (addr > AUTOIP_RANGE_END) { + addr -= AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1; + } + LWIP_ASSERT("AUTOIP address not in range", (addr >= AUTOIP_RANGE_START) && + (addr <= AUTOIP_RANGE_END)); + ip4_addr_set_u32(ipaddr, htonl(addr)); + + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_create_addr(): tried_llipaddr=%"U16_F", %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + (u16_t)(netif->autoip->tried_llipaddr), ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), + ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr))); +} + +/** + * Sends an ARP probe from a network interface + * + * @param netif network interface used to send the probe + */ +static err_t +autoip_arp_probe(struct netif *netif) +{ + return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast, + (struct eth_addr *)netif->hwaddr, IP_ADDR_ANY, ðzero, + &netif->autoip->llipaddr, ARP_REQUEST); +} + +/** + * Sends an ARP announce from a network interface + * + * @param netif network interface used to send the announce + */ +static err_t +autoip_arp_announce(struct netif *netif) +{ + return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast, + (struct eth_addr *)netif->hwaddr, &netif->autoip->llipaddr, ðzero, + &netif->autoip->llipaddr, ARP_REQUEST); +} + +/** + * Configure interface for use with current LL IP-Address + * + * @param netif network interface to configure with current LL IP-Address + */ +static err_t +autoip_bind(struct netif *netif) +{ + struct autoip *autoip = netif->autoip; + ip_addr_t sn_mask, gw_addr; + + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_bind(netif=%p) %c%c%"U16_F" %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num, + ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr), + ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr))); + + IP4_ADDR(&sn_mask, 255, 255, 0, 0); + IP4_ADDR(&gw_addr, 0, 0, 0, 0); + + netif_set_ipaddr(netif, &autoip->llipaddr); + netif_set_netmask(netif, &sn_mask); + netif_set_gw(netif, &gw_addr); + + /* bring the interface up */ + netif_set_up(netif); + + return ERR_OK; +} + +/** + * Start AutoIP client + * + * @param netif network interface on which start the AutoIP client + */ +err_t +autoip_start(struct netif *netif) +{ + struct autoip *autoip = netif->autoip; + err_t result = ERR_OK; + + if(netif_is_up(netif)) { + netif_set_down(netif); + } + + /* Set IP-Address, Netmask and Gateway to 0 to make sure that + * ARP Packets are formed correctly + */ + ip_addr_set_zero(&netif->ip_addr); + ip_addr_set_zero(&netif->netmask); + ip_addr_set_zero(&netif->gw); + + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], + netif->name[1], (u16_t)netif->num)); + if(autoip == NULL) { + /* no AutoIP client attached yet? */ + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_start(): starting new AUTOIP client\n")); + autoip = (struct autoip *)mem_malloc(sizeof(struct autoip)); + if(autoip == NULL) { + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_start(): could not allocate autoip\n")); + return ERR_MEM; + } + memset(autoip, 0, sizeof(struct autoip)); + /* store this AutoIP client in the netif */ + netif->autoip = autoip; + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_start(): allocated autoip")); + } else { + autoip->state = AUTOIP_STATE_OFF; + autoip->ttw = 0; + autoip->sent_num = 0; + ip_addr_set_zero(&autoip->llipaddr); + autoip->lastconflict = 0; + } + + autoip_create_addr(netif, &(autoip->llipaddr)); + autoip_start_probing(netif); + + return result; +} + +static void +autoip_start_probing(struct netif *netif) +{ + struct autoip *autoip = netif->autoip; + + autoip->state = AUTOIP_STATE_PROBING; + autoip->sent_num = 0; + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_start_probing(): changing state to PROBING: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(&netif->autoip->llipaddr), ip4_addr2_16(&netif->autoip->llipaddr), + ip4_addr3_16(&netif->autoip->llipaddr), ip4_addr4_16(&netif->autoip->llipaddr))); + + /* time to wait to first probe, this is randomly + * choosen out of 0 to PROBE_WAIT seconds. + * compliant to RFC 3927 Section 2.2.1 + */ + autoip->ttw = (u16_t)(LWIP_AUTOIP_RAND(netif) % (PROBE_WAIT * AUTOIP_TICKS_PER_SECOND)); + + /* + * if we tried more then MAX_CONFLICTS we must limit our rate for + * accquiring and probing address + * compliant to RFC 3927 Section 2.2.1 + */ + if(autoip->tried_llipaddr > MAX_CONFLICTS) { + autoip->ttw = RATE_LIMIT_INTERVAL * AUTOIP_TICKS_PER_SECOND; + } +} + +/** + * Handle a possible change in the network configuration. + * + * If there is an AutoIP address configured, take the interface down + * and begin probing with the same address. + */ +void +autoip_network_changed(struct netif *netif) +{ + if (netif->autoip && netif->autoip->state != AUTOIP_STATE_OFF) { + netif_set_down(netif); + autoip_start_probing(netif); + } +} + +/** + * Stop AutoIP client + * + * @param netif network interface on which stop the AutoIP client + */ +err_t +autoip_stop(struct netif *netif) +{ + netif->autoip->state = AUTOIP_STATE_OFF; + netif_set_down(netif); + return ERR_OK; +} + +/** + * Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds + */ +void +autoip_tmr() +{ + struct netif *netif = netif_list; + /* loop through netif's */ + while (netif != NULL) { + /* only act on AutoIP configured interfaces */ + if (netif->autoip != NULL) { + if(netif->autoip->lastconflict > 0) { + netif->autoip->lastconflict--; + } + + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_tmr() AutoIP-State: %"U16_F", ttw=%"U16_F"\n", + (u16_t)(netif->autoip->state), netif->autoip->ttw)); + + switch(netif->autoip->state) { + case AUTOIP_STATE_PROBING: + if(netif->autoip->ttw > 0) { + netif->autoip->ttw--; + } else { + if(netif->autoip->sent_num >= PROBE_NUM) { + netif->autoip->state = AUTOIP_STATE_ANNOUNCING; + netif->autoip->sent_num = 0; + netif->autoip->ttw = ANNOUNCE_WAIT * AUTOIP_TICKS_PER_SECOND; + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_tmr(): changing state to ANNOUNCING: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(&netif->autoip->llipaddr), ip4_addr2_16(&netif->autoip->llipaddr), + ip4_addr3_16(&netif->autoip->llipaddr), ip4_addr4_16(&netif->autoip->llipaddr))); + } else { + autoip_arp_probe(netif); + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_tmr() PROBING Sent Probe\n")); + netif->autoip->sent_num++; + /* calculate time to wait to next probe */ + netif->autoip->ttw = (u16_t)((LWIP_AUTOIP_RAND(netif) % + ((PROBE_MAX - PROBE_MIN) * AUTOIP_TICKS_PER_SECOND) ) + + PROBE_MIN * AUTOIP_TICKS_PER_SECOND); + } + } + break; + + case AUTOIP_STATE_ANNOUNCING: + if(netif->autoip->ttw > 0) { + netif->autoip->ttw--; + } else { + if(netif->autoip->sent_num == 0) { + /* We are here the first time, so we waited ANNOUNCE_WAIT seconds + * Now we can bind to an IP address and use it. + * + * autoip_bind calls netif_set_up. This triggers a gratuitous ARP + * which counts as an announcement. + */ + autoip_bind(netif); + } else { + autoip_arp_announce(netif); + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_tmr() ANNOUNCING Sent Announce\n")); + } + netif->autoip->ttw = ANNOUNCE_INTERVAL * AUTOIP_TICKS_PER_SECOND; + netif->autoip->sent_num++; + + if(netif->autoip->sent_num >= ANNOUNCE_NUM) { + netif->autoip->state = AUTOIP_STATE_BOUND; + netif->autoip->sent_num = 0; + netif->autoip->ttw = 0; + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_tmr(): changing state to BOUND: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(&netif->autoip->llipaddr), ip4_addr2_16(&netif->autoip->llipaddr), + ip4_addr3_16(&netif->autoip->llipaddr), ip4_addr4_16(&netif->autoip->llipaddr))); + } + } + break; + } + } + /* proceed to next network interface */ + netif = netif->next; + } +} + +/** + * Handles every incoming ARP Packet, called by etharp_arp_input. + * + * @param netif network interface to use for autoip processing + * @param hdr Incoming ARP packet + */ +void +autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr) +{ + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_arp_reply()\n")); + if ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) { + /* when ip.src == llipaddr && hw.src != netif->hwaddr + * + * when probing ip.dst == llipaddr && hw.src != netif->hwaddr + * we have a conflict and must solve it + */ + ip_addr_t sipaddr, dipaddr; + struct eth_addr netifaddr; + ETHADDR16_COPY(netifaddr.addr, netif->hwaddr); + + /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without + * structure packing (not using structure copy which breaks strict-aliasing rules). + */ + IPADDR2_COPY(&sipaddr, &hdr->sipaddr); + IPADDR2_COPY(&dipaddr, &hdr->dipaddr); + + if ((netif->autoip->state == AUTOIP_STATE_PROBING) || + ((netif->autoip->state == AUTOIP_STATE_ANNOUNCING) && + (netif->autoip->sent_num == 0))) { + /* RFC 3927 Section 2.2.1: + * from beginning to after ANNOUNCE_WAIT + * seconds we have a conflict if + * ip.src == llipaddr OR + * ip.dst == llipaddr && hw.src != own hwaddr + */ + if ((ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr)) || + (ip_addr_cmp(&dipaddr, &netif->autoip->llipaddr) && + !eth_addr_cmp(&netifaddr, &hdr->shwaddr))) { + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, + ("autoip_arp_reply(): Probe Conflict detected\n")); + autoip_restart(netif); + } + } else { + /* RFC 3927 Section 2.5: + * in any state we have a conflict if + * ip.src == llipaddr && hw.src != own hwaddr + */ + if (ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr) && + !eth_addr_cmp(&netifaddr, &hdr->shwaddr)) { + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, + ("autoip_arp_reply(): Conflicting ARP-Packet detected\n")); + autoip_handle_arp_conflict(netif); + } + } + } +} + +#endif /* LWIP_AUTOIP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/icmp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/icmp.c new file mode 100644 index 0000000..32902a5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/icmp.c @@ -0,0 +1,335 @@ +/** + * @file + * ICMP - Internet Control Message Protocol + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* Some ICMP messages should be passed to the transport protocols. This + is not implemented. */ + +#include "lwip/opt.h" + +#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/icmp.h" +#include "lwip/inet_chksum.h" +#include "lwip/ip.h" +#include "lwip/def.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +#include + +/** Small optimization: set to 0 if incoming PBUF_POOL pbuf always can be + * used to modify and send a response packet (and to 1 if this is not the case, + * e.g. when link header is stripped of when receiving) */ +#ifndef LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN +#define LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN 1 +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ + +/* The amount of data from the original packet to return in a dest-unreachable */ +#define ICMP_DEST_UNREACH_DATASIZE 8 + +static void icmp_send_response(struct pbuf *p, u8_t type, u8_t code); + +/** + * Processes ICMP input packets, called from ip_input(). + * + * Currently only processes icmp echo requests and sends + * out the echo response. + * + * @param p the icmp echo request packet, p->payload pointing to the ip header + * @param inp the netif on which this packet was received + */ +void +icmp_input(struct pbuf *p, struct netif *inp) +{ + u8_t type; +#ifdef LWIP_DEBUG + u8_t code; +#endif /* LWIP_DEBUG */ + struct icmp_echo_hdr *iecho; + struct ip_hdr *iphdr; + s16_t hlen; + + ICMP_STATS_INC(icmp.recv); + snmp_inc_icmpinmsgs(); + + + iphdr = (struct ip_hdr *)p->payload; + hlen = IPH_HL(iphdr) * 4; + if (pbuf_header(p, -hlen) || (p->tot_len < sizeof(u16_t)*2)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); + goto lenerr; + } + + type = *((u8_t *)p->payload); +#ifdef LWIP_DEBUG + code = *(((u8_t *)p->payload)+1); +#endif /* LWIP_DEBUG */ + switch (type) { + case ICMP_ER: + /* This is OK, echo reply might have been parsed by a raw PCB + (as obviously, an echo request has been sent, too). */ + break; + case ICMP_ECHO: +#if !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING + { + int accepted = 1; +#if !LWIP_MULTICAST_PING + /* multicast destination address? */ + if (ip_addr_ismulticast(¤t_iphdr_dest)) { + accepted = 0; + } +#endif /* LWIP_MULTICAST_PING */ +#if !LWIP_BROADCAST_PING + /* broadcast destination address? */ + if (ip_addr_isbroadcast(¤t_iphdr_dest, inp)) { + accepted = 0; + } +#endif /* LWIP_BROADCAST_PING */ + /* broadcast or multicast destination address not acceptd? */ + if (!accepted) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n")); + ICMP_STATS_INC(icmp.err); + pbuf_free(p); + return; + } + } +#endif /* !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */ + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); + if (p->tot_len < sizeof(struct icmp_echo_hdr)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); + goto lenerr; + } + if (inet_chksum_pbuf(p) != 0) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); + pbuf_free(p); + ICMP_STATS_INC(icmp.chkerr); + snmp_inc_icmpinerrors(); + return; + } +#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN + if (pbuf_header(p, (PBUF_IP_HLEN + PBUF_LINK_HLEN))) { + /* p is not big enough to contain link headers + * allocate a new one and copy p into it + */ + struct pbuf *r; + /* switch p->payload to ip header */ + if (pbuf_header(p, hlen)) { + LWIP_ASSERT("icmp_input: moving p->payload to ip header failed\n", 0); + goto memerr; + } + /* allocate new packet buffer with space for link headers */ + r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM); + if (r == NULL) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n")); + goto memerr; + } + LWIP_ASSERT("check that first pbuf can hold struct the ICMP header", + (r->len >= hlen + sizeof(struct icmp_echo_hdr))); + /* copy the whole packet including ip header */ + if (pbuf_copy(r, p) != ERR_OK) { + LWIP_ASSERT("icmp_input: copying to new pbuf failed\n", 0); + goto memerr; + } + iphdr = (struct ip_hdr *)r->payload; + /* switch r->payload back to icmp header */ + if (pbuf_header(r, -hlen)) { + LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0); + goto memerr; + } + /* free the original p */ + pbuf_free(p); + /* we now have an identical copy of p that has room for link headers */ + p = r; + } else { + /* restore p->payload to point to icmp header */ + if (pbuf_header(p, -(s16_t)(PBUF_IP_HLEN + PBUF_LINK_HLEN))) { + LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0); + goto memerr; + } + } +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ + /* At this point, all checks are OK. */ + /* We generate an answer by switching the dest and src ip addresses, + * setting the icmp type to ECHO_RESPONSE and updating the checksum. */ + iecho = (struct icmp_echo_hdr *)p->payload; + ip_addr_copy(iphdr->src, *ip_current_dest_addr()); + ip_addr_copy(iphdr->dest, *ip_current_src_addr()); + ICMPH_TYPE_SET(iecho, ICMP_ER); + /* adjust the checksum */ + if (iecho->chksum >= PP_HTONS(0xffffU - (ICMP_ECHO << 8))) { + iecho->chksum += PP_HTONS(ICMP_ECHO << 8) + 1; + } else { + iecho->chksum += PP_HTONS(ICMP_ECHO << 8); + } + + /* Set the correct TTL and recalculate the header checksum. */ + IPH_TTL_SET(iphdr, ICMP_TTL); + IPH_CHKSUM_SET(iphdr, 0); +#if CHECKSUM_GEN_IP + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); +#endif /* CHECKSUM_GEN_IP */ + + ICMP_STATS_INC(icmp.xmit); + /* increase number of messages attempted to send */ + snmp_inc_icmpoutmsgs(); + /* increase number of echo replies attempted to send */ + snmp_inc_icmpoutechoreps(); + + if(pbuf_header(p, hlen)) { + LWIP_ASSERT("Can't move over header in packet", 0); + } else { + err_t ret; + /* send an ICMP packet, src addr is the dest addr of the curren packet */ + ret = ip_output_if(p, ip_current_dest_addr(), IP_HDRINCL, + ICMP_TTL, 0, IP_PROTO_ICMP, inp); + if (ret != ERR_OK) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %c.\n", ret)); + } + } + break; + default: + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", + (s16_t)type, (s16_t)code)); + ICMP_STATS_INC(icmp.proterr); + ICMP_STATS_INC(icmp.drop); + } + pbuf_free(p); + return; +lenerr: + pbuf_free(p); + ICMP_STATS_INC(icmp.lenerr); + snmp_inc_icmpinerrors(); + return; +#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN +memerr: + pbuf_free(p); + ICMP_STATS_INC(icmp.err); + snmp_inc_icmpinerrors(); + return; +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ +} + +/** + * Send an icmp 'destination unreachable' packet, called from ip_input() if + * the transport layer protocol is unknown and from udp_input() if the local + * port is not bound. + * + * @param p the input packet for which the 'unreachable' should be sent, + * p->payload pointing to the IP header + * @param t type of the 'unreachable' packet + */ +void +icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) +{ + icmp_send_response(p, ICMP_DUR, t); +} + +#if IP_FORWARD || IP_REASSEMBLY +/** + * Send a 'time exceeded' packet, called from ip_forward() if TTL is 0. + * + * @param p the input packet for which the 'time exceeded' should be sent, + * p->payload pointing to the IP header + * @param t type of the 'time exceeded' packet + */ +void +icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) +{ + icmp_send_response(p, ICMP_TE, t); +} + +#endif /* IP_FORWARD || IP_REASSEMBLY */ + +/** + * Send an icmp packet in response to an incoming packet. + * + * @param p the input packet for which the 'unreachable' should be sent, + * p->payload pointing to the IP header + * @param type Type of the ICMP header + * @param code Code of the ICMP header + */ +static void +icmp_send_response(struct pbuf *p, u8_t type, u8_t code) +{ + struct pbuf *q; + struct ip_hdr *iphdr; + /* we can use the echo header here */ + struct icmp_echo_hdr *icmphdr; + ip_addr_t iphdr_src; + + /* ICMP header + IP header + 8 bytes of data */ + q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE, + PBUF_RAM); + if (q == NULL) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n")); + return; + } + LWIP_ASSERT("check that first pbuf can hold icmp message", + (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE))); + + iphdr = (struct ip_hdr *)p->payload; + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from ")); + ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src)); + LWIP_DEBUGF(ICMP_DEBUG, (" to ")); + ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest)); + LWIP_DEBUGF(ICMP_DEBUG, ("\n")); + + icmphdr = (struct icmp_echo_hdr *)q->payload; + icmphdr->type = type; + icmphdr->code = code; + icmphdr->id = 0; + icmphdr->seqno = 0; + + /* copy fields from original packet */ + SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload, + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE); + + /* calculate checksum */ + icmphdr->chksum = 0; + icmphdr->chksum = inet_chksum(icmphdr, q->len); + ICMP_STATS_INC(icmp.xmit); + /* increase number of messages attempted to send */ + snmp_inc_icmpoutmsgs(); + /* increase number of destination unreachable messages attempted to send */ + snmp_inc_icmpouttimeexcds(); + ip_addr_copy(iphdr_src, iphdr->src); + ip_output(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP); + pbuf_free(q); +} + +#endif /* LWIP_ICMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/igmp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/igmp.c new file mode 100644 index 0000000..4e4405e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/igmp.c @@ -0,0 +1,817 @@ +/** + * @file + * IGMP - Internet Group Management Protocol + * + */ + +/* + * Copyright (c) 2002 CITEL Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. +*/ + +/*------------------------------------------------------------- +Note 1) +Although the rfc requires V1 AND V2 capability +we will only support v2 since now V1 is very old (August 1989) +V1 can be added if required + +a debug print and statistic have been implemented to +show this up. +------------------------------------------------------------- +------------------------------------------------------------- +Note 2) +A query for a specific group address (as opposed to ALLHOSTS) +has now been implemented as I am unsure if it is required + +a debug print and statistic have been implemented to +show this up. +------------------------------------------------------------- +------------------------------------------------------------- +Note 3) +The router alert rfc 2113 is implemented in outgoing packets +but not checked rigorously incoming +------------------------------------------------------------- +Steve Reynolds +------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- + * RFC 988 - Host extensions for IP multicasting - V0 + * RFC 1054 - Host extensions for IP multicasting - + * RFC 1112 - Host extensions for IP multicasting - V1 + * RFC 2236 - Internet Group Management Protocol, Version 2 - V2 <- this code is based on this RFC (it's the "de facto" standard) + * RFC 3376 - Internet Group Management Protocol, Version 3 - V3 + * RFC 4604 - Using Internet Group Management Protocol Version 3... - V3+ + * RFC 2113 - IP Router Alert Option - + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "lwip/opt.h" + +#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/igmp.h" +#include "lwip/debug.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/ip.h" +#include "lwip/inet_chksum.h" +#include "lwip/netif.h" +#include "lwip/icmp.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" +#include "lwip/stats.h" + +#include "string.h" + +/* + * IGMP constants + */ +#define IGMP_TTL 1 +#define IGMP_MINLEN 8 +#define ROUTER_ALERT 0x9404U +#define ROUTER_ALERTLEN 4 + +/* + * IGMP message types, including version number. + */ +#define IGMP_MEMB_QUERY 0x11 /* Membership query */ +#define IGMP_V1_MEMB_REPORT 0x12 /* Ver. 1 membership report */ +#define IGMP_V2_MEMB_REPORT 0x16 /* Ver. 2 membership report */ +#define IGMP_LEAVE_GROUP 0x17 /* Leave-group message */ + +/* Group membership states */ +#define IGMP_GROUP_NON_MEMBER 0 +#define IGMP_GROUP_DELAYING_MEMBER 1 +#define IGMP_GROUP_IDLE_MEMBER 2 + +/** + * IGMP packet format. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct igmp_msg { + PACK_STRUCT_FIELD(u8_t igmp_msgtype); + PACK_STRUCT_FIELD(u8_t igmp_maxresp); + PACK_STRUCT_FIELD(u16_t igmp_checksum); + PACK_STRUCT_FIELD(ip_addr_p_t igmp_group_address); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + + +static struct igmp_group *igmp_lookup_group(struct netif *ifp, ip_addr_t *addr); +static err_t igmp_remove_group(struct igmp_group *group); +static void igmp_timeout( struct igmp_group *group); +static void igmp_start_timer(struct igmp_group *group, u8_t max_time); +static void igmp_stop_timer(struct igmp_group *group); +static void igmp_delaying_member(struct igmp_group *group, u8_t maxresp); +static err_t igmp_ip_output_if(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, struct netif *netif); +static void igmp_send(struct igmp_group *group, u8_t type); + + +static struct igmp_group* igmp_group_list; +static ip_addr_t allsystems; +static ip_addr_t allrouters; + + +/** + * Initialize the IGMP module + */ +void +igmp_init(void) +{ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_init: initializing\n")); + + IP4_ADDR(&allsystems, 224, 0, 0, 1); + IP4_ADDR(&allrouters, 224, 0, 0, 2); +} + +#ifdef LWIP_DEBUG +/** + * Dump global IGMP groups list + */ +void +igmp_dump_group_list() +{ + struct igmp_group *group = igmp_group_list; + + while (group != NULL) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_dump_group_list: [%"U32_F"] ", (u32_t)(group->group_state))); + ip_addr_debug_print(IGMP_DEBUG, &group->group_address); + LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", group->netif)); + group = group->next; + } + LWIP_DEBUGF(IGMP_DEBUG, ("\n")); +} +#else +#define igmp_dump_group_list() +#endif /* LWIP_DEBUG */ + +/** + * Start IGMP processing on interface + * + * @param netif network interface on which start IGMP processing + */ +err_t +igmp_start(struct netif *netif) +{ + struct igmp_group* group; + + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: starting IGMP processing on if %p\n", netif)); + + group = igmp_lookup_group(netif, &allsystems); + + if (group != NULL) { + group->group_state = IGMP_GROUP_IDLE_MEMBER; + group->use++; + + /* Allow the igmp messages at the MAC level */ + if (netif->igmp_mac_filter != NULL) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: igmp_mac_filter(ADD ")); + ip_addr_debug_print(IGMP_DEBUG, &allsystems); + LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif)); + netif->igmp_mac_filter(netif, &allsystems, IGMP_ADD_MAC_FILTER); + } + + return ERR_OK; + } + + return ERR_MEM; +} + +/** + * Stop IGMP processing on interface + * + * @param netif network interface on which stop IGMP processing + */ +err_t +igmp_stop(struct netif *netif) +{ + struct igmp_group *group = igmp_group_list; + struct igmp_group *prev = NULL; + struct igmp_group *next; + + /* look for groups joined on this interface further down the list */ + while (group != NULL) { + next = group->next; + /* is it a group joined on this interface? */ + if (group->netif == netif) { + /* is it the first group of the list? */ + if (group == igmp_group_list) { + igmp_group_list = next; + } + /* is there a "previous" group defined? */ + if (prev != NULL) { + prev->next = next; + } + /* disable the group at the MAC level */ + if (netif->igmp_mac_filter != NULL) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_stop: igmp_mac_filter(DEL ")); + ip_addr_debug_print(IGMP_DEBUG, &group->group_address); + LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif)); + netif->igmp_mac_filter(netif, &(group->group_address), IGMP_DEL_MAC_FILTER); + } + /* free group */ + memp_free(MEMP_IGMP_GROUP, group); + } else { + /* change the "previous" */ + prev = group; + } + /* move to "next" */ + group = next; + } + return ERR_OK; +} + +/** + * Report IGMP memberships for this interface + * + * @param netif network interface on which report IGMP memberships + */ +void +igmp_report_groups(struct netif *netif) +{ + struct igmp_group *group = igmp_group_list; + + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_report_groups: sending IGMP reports on if %p\n", netif)); + + while (group != NULL) { + if (group->netif == netif) { + igmp_delaying_member(group, IGMP_JOIN_DELAYING_MEMBER_TMR); + } + group = group->next; + } +} + +/** + * Search for a group in the global igmp_group_list + * + * @param ifp the network interface for which to look + * @param addr the group ip address to search for + * @return a struct igmp_group* if the group has been found, + * NULL if the group wasn't found. + */ +struct igmp_group * +igmp_lookfor_group(struct netif *ifp, ip_addr_t *addr) +{ + struct igmp_group *group = igmp_group_list; + + while (group != NULL) { + if ((group->netif == ifp) && (ip_addr_cmp(&(group->group_address), addr))) { + return group; + } + group = group->next; + } + + /* to be clearer, we return NULL here instead of + * 'group' (which is also NULL at this point). + */ + return NULL; +} + +/** + * Search for a specific igmp group and create a new one if not found- + * + * @param ifp the network interface for which to look + * @param addr the group ip address to search + * @return a struct igmp_group*, + * NULL on memory error. + */ +struct igmp_group * +igmp_lookup_group(struct netif *ifp, ip_addr_t *addr) +{ + struct igmp_group *group = igmp_group_list; + + /* Search if the group already exists */ + group = igmp_lookfor_group(ifp, addr); + if (group != NULL) { + /* Group already exists. */ + return group; + } + + /* Group doesn't exist yet, create a new one */ + group = (struct igmp_group *)memp_malloc(MEMP_IGMP_GROUP); + if (group != NULL) { + group->netif = ifp; + ip_addr_set(&(group->group_address), addr); + group->timer = 0; /* Not running */ + group->group_state = IGMP_GROUP_NON_MEMBER; + group->last_reporter_flag = 0; + group->use = 0; + group->next = igmp_group_list; + + igmp_group_list = group; + } + + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_lookup_group: %sallocated a new group with address ", (group?"":"impossible to "))); + ip_addr_debug_print(IGMP_DEBUG, addr); + LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", ifp)); + + return group; +} + +/** + * Remove a group in the global igmp_group_list + * + * @param group the group to remove from the global igmp_group_list + * @return ERR_OK if group was removed from the list, an err_t otherwise + */ +static err_t +igmp_remove_group(struct igmp_group *group) +{ + err_t err = ERR_OK; + + /* Is it the first group? */ + if (igmp_group_list == group) { + igmp_group_list = group->next; + } else { + /* look for group further down the list */ + struct igmp_group *tmpGroup; + for (tmpGroup = igmp_group_list; tmpGroup != NULL; tmpGroup = tmpGroup->next) { + if (tmpGroup->next == group) { + tmpGroup->next = group->next; + break; + } + } + /* Group not found in the global igmp_group_list */ + if (tmpGroup == NULL) + err = ERR_ARG; + } + /* free group */ + memp_free(MEMP_IGMP_GROUP, group); + + return err; +} + +/** + * Called from ip_input() if a new IGMP packet is received. + * + * @param p received igmp packet, p->payload pointing to the ip header + * @param inp network interface on which the packet was received + * @param dest destination ip address of the igmp packet + */ +void +igmp_input(struct pbuf *p, struct netif *inp, ip_addr_t *dest) +{ + struct ip_hdr * iphdr; + struct igmp_msg* igmp; + struct igmp_group* group; + struct igmp_group* groupref; + + IGMP_STATS_INC(igmp.recv); + + /* Note that the length CAN be greater than 8 but only 8 are used - All are included in the checksum */ + iphdr = (struct ip_hdr *)p->payload; + if (pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4)) || (p->len < IGMP_MINLEN)) { + pbuf_free(p); + IGMP_STATS_INC(igmp.lenerr); + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: length error\n")); + return; + } + + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: message from ")); + ip_addr_debug_print(IGMP_DEBUG, &(iphdr->src)); + LWIP_DEBUGF(IGMP_DEBUG, (" to address ")); + ip_addr_debug_print(IGMP_DEBUG, &(iphdr->dest)); + LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", inp)); + + /* Now calculate and check the checksum */ + igmp = (struct igmp_msg *)p->payload; + if (inet_chksum(igmp, p->len)) { + pbuf_free(p); + IGMP_STATS_INC(igmp.chkerr); + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: checksum error\n")); + return; + } + + /* Packet is ok so find an existing group */ + group = igmp_lookfor_group(inp, dest); /* use the destination IP address of incoming packet */ + + /* If group can be found or create... */ + if (!group) { + pbuf_free(p); + IGMP_STATS_INC(igmp.drop); + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP frame not for us\n")); + return; + } + + /* NOW ACT ON THE INCOMING MESSAGE TYPE... */ + switch (igmp->igmp_msgtype) { + case IGMP_MEMB_QUERY: { + /* IGMP_MEMB_QUERY to the "all systems" address ? */ + if ((ip_addr_cmp(dest, &allsystems)) && ip_addr_isany(&igmp->igmp_group_address)) { + /* THIS IS THE GENERAL QUERY */ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: General IGMP_MEMB_QUERY on \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); + + if (igmp->igmp_maxresp == 0) { + IGMP_STATS_INC(igmp.rx_v1); + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: got an all hosts query with time== 0 - this is V1 and not implemented - treat as v2\n")); + igmp->igmp_maxresp = IGMP_V1_DELAYING_MEMBER_TMR; + } else { + IGMP_STATS_INC(igmp.rx_general); + } + + groupref = igmp_group_list; + while (groupref) { + /* Do not send messages on the all systems group address! */ + if ((groupref->netif == inp) && (!(ip_addr_cmp(&(groupref->group_address), &allsystems)))) { + igmp_delaying_member(groupref, igmp->igmp_maxresp); + } + groupref = groupref->next; + } + } else { + /* IGMP_MEMB_QUERY to a specific group ? */ + if (!ip_addr_isany(&igmp->igmp_group_address)) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_MEMB_QUERY to a specific group ")); + ip_addr_debug_print(IGMP_DEBUG, &igmp->igmp_group_address); + if (ip_addr_cmp(dest, &allsystems)) { + ip_addr_t groupaddr; + LWIP_DEBUGF(IGMP_DEBUG, (" using \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); + /* we first need to re-look for the group since we used dest last time */ + ip_addr_copy(groupaddr, igmp->igmp_group_address); + group = igmp_lookfor_group(inp, &groupaddr); + } else { + LWIP_DEBUGF(IGMP_DEBUG, (" with the group address as destination [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); + } + + if (group != NULL) { + IGMP_STATS_INC(igmp.rx_group); + igmp_delaying_member(group, igmp->igmp_maxresp); + } else { + IGMP_STATS_INC(igmp.drop); + } + } else { + IGMP_STATS_INC(igmp.proterr); + } + } + break; + } + case IGMP_V2_MEMB_REPORT: { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_V2_MEMB_REPORT\n")); + IGMP_STATS_INC(igmp.rx_report); + if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) { + /* This is on a specific group we have already looked up */ + group->timer = 0; /* stopped */ + group->group_state = IGMP_GROUP_IDLE_MEMBER; + group->last_reporter_flag = 0; + } + break; + } + default: { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: unexpected msg %d in state %d on group %p on if %p\n", + igmp->igmp_msgtype, group->group_state, &group, group->netif)); + IGMP_STATS_INC(igmp.proterr); + break; + } + } + + pbuf_free(p); + return; +} + +/** + * Join a group on one network interface. + * + * @param ifaddr ip address of the network interface which should join a new group + * @param groupaddr the ip address of the group which to join + * @return ERR_OK if group was joined on the netif(s), an err_t otherwise + */ +err_t +igmp_joingroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr) +{ + err_t err = ERR_VAL; /* no matching interface */ + struct igmp_group *group; + struct netif *netif; + + /* make sure it is multicast address */ + LWIP_ERROR("igmp_joingroup: attempt to join non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;); + LWIP_ERROR("igmp_joingroup: attempt to join allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); + + /* loop through netif's */ + netif = netif_list; + while (netif != NULL) { + /* Should we join this interface ? */ + if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) { + /* find group or create a new one if not found */ + group = igmp_lookup_group(netif, groupaddr); + + if (group != NULL) { + /* This should create a new group, check the state to make sure */ + if (group->group_state != IGMP_GROUP_NON_MEMBER) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to group not in state IGMP_GROUP_NON_MEMBER\n")); + } else { + /* OK - it was new group */ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to new group: ")); + ip_addr_debug_print(IGMP_DEBUG, groupaddr); + LWIP_DEBUGF(IGMP_DEBUG, ("\n")); + + /* If first use of the group, allow the group at the MAC level */ + if ((group->use==0) && (netif->igmp_mac_filter != NULL)) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: igmp_mac_filter(ADD ")); + ip_addr_debug_print(IGMP_DEBUG, groupaddr); + LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif)); + netif->igmp_mac_filter(netif, groupaddr, IGMP_ADD_MAC_FILTER); + } + + IGMP_STATS_INC(igmp.tx_join); + igmp_send(group, IGMP_V2_MEMB_REPORT); + + igmp_start_timer(group, IGMP_JOIN_DELAYING_MEMBER_TMR); + + /* Need to work out where this timer comes from */ + group->group_state = IGMP_GROUP_DELAYING_MEMBER; + } + /* Increment group use */ + group->use++; + /* Join on this interface */ + err = ERR_OK; + } else { + /* Return an error even if some network interfaces are joined */ + /** @todo undo any other netif already joined */ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: Not enought memory to join to group\n")); + return ERR_MEM; + } + } + /* proceed to next network interface */ + netif = netif->next; + } + + return err; +} + +/** + * Leave a group on one network interface. + * + * @param ifaddr ip address of the network interface which should leave a group + * @param groupaddr the ip address of the group which to leave + * @return ERR_OK if group was left on the netif(s), an err_t otherwise + */ +err_t +igmp_leavegroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr) +{ + err_t err = ERR_VAL; /* no matching interface */ + struct igmp_group *group; + struct netif *netif; + + /* make sure it is multicast address */ + LWIP_ERROR("igmp_leavegroup: attempt to leave non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;); + LWIP_ERROR("igmp_leavegroup: attempt to leave allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); + + /* loop through netif's */ + netif = netif_list; + while (netif != NULL) { + /* Should we leave this interface ? */ + if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) { + /* find group */ + group = igmp_lookfor_group(netif, groupaddr); + + if (group != NULL) { + /* Only send a leave if the flag is set according to the state diagram */ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: Leaving group: ")); + ip_addr_debug_print(IGMP_DEBUG, groupaddr); + LWIP_DEBUGF(IGMP_DEBUG, ("\n")); + + /* If there is no other use of the group */ + if (group->use <= 1) { + /* If we are the last reporter for this group */ + if (group->last_reporter_flag) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: sending leaving group\n")); + IGMP_STATS_INC(igmp.tx_leave); + igmp_send(group, IGMP_LEAVE_GROUP); + } + + /* Disable the group at the MAC level */ + if (netif->igmp_mac_filter != NULL) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: igmp_mac_filter(DEL ")); + ip_addr_debug_print(IGMP_DEBUG, groupaddr); + LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif)); + netif->igmp_mac_filter(netif, groupaddr, IGMP_DEL_MAC_FILTER); + } + + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: remove group: ")); + ip_addr_debug_print(IGMP_DEBUG, groupaddr); + LWIP_DEBUGF(IGMP_DEBUG, ("\n")); + + /* Free the group */ + igmp_remove_group(group); + } else { + /* Decrement group use */ + group->use--; + } + /* Leave on this interface */ + err = ERR_OK; + } else { + /* It's not a fatal error on "leavegroup" */ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: not member of group\n")); + } + } + /* proceed to next network interface */ + netif = netif->next; + } + + return err; +} + +/** + * The igmp timer function (both for NO_SYS=1 and =0) + * Should be called every IGMP_TMR_INTERVAL milliseconds (100 ms is default). + */ +void +igmp_tmr(void) +{ + struct igmp_group *group = igmp_group_list; + + while (group != NULL) { + if (group->timer > 0) { + group->timer--; + if (group->timer == 0) { + igmp_timeout(group); + } + } + group = group->next; + } +} + +/** + * Called if a timeout for one group is reached. + * Sends a report for this group. + * + * @param group an igmp_group for which a timeout is reached + */ +static void +igmp_timeout(struct igmp_group *group) +{ + /* If the state is IGMP_GROUP_DELAYING_MEMBER then we send a report for this group */ + if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_timeout: report membership for group with address ")); + ip_addr_debug_print(IGMP_DEBUG, &(group->group_address)); + LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", group->netif)); + + IGMP_STATS_INC(igmp.tx_report); + igmp_send(group, IGMP_V2_MEMB_REPORT); + } +} + +/** + * Start a timer for an igmp group + * + * @param group the igmp_group for which to start a timer + * @param max_time the time in multiples of IGMP_TMR_INTERVAL (decrease with + * every call to igmp_tmr()) + */ +static void +igmp_start_timer(struct igmp_group *group, u8_t max_time) +{ + /* ensure the input value is > 0 */ + if (max_time == 0) { + max_time = 1; + } + /* ensure the random value is > 0 */ + group->timer = (LWIP_RAND() % (max_time - 1)) + 1; +} + +/** + * Stop a timer for an igmp_group + * + * @param group the igmp_group for which to stop the timer + */ +static void +igmp_stop_timer(struct igmp_group *group) +{ + group->timer = 0; +} + +/** + * Delaying membership report for a group if necessary + * + * @param group the igmp_group for which "delaying" membership report + * @param maxresp query delay + */ +static void +igmp_delaying_member(struct igmp_group *group, u8_t maxresp) +{ + if ((group->group_state == IGMP_GROUP_IDLE_MEMBER) || + ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) && + ((group->timer == 0) || (maxresp < group->timer)))) { + igmp_start_timer(group, maxresp); + group->group_state = IGMP_GROUP_DELAYING_MEMBER; + } +} + + +/** + * Sends an IP packet on a network interface. This function constructs the IP header + * and calculates the IP header checksum. If the source IP address is NULL, + * the IP address of the outgoing network interface is filled in as source address. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == IP_HDRINCL, p already includes an IP + header and p->payload points to that IP header) + * @param src the source IP address to send from (if src == IP_ADDR_ANY, the + * IP address of the netif used to send is used as source address) + * @param dest the destination IP address to send the packet to + * @param ttl the TTL value to be set in the IP header + * @param proto the PROTOCOL to be set in the IP header + * @param netif the netif on which to send this packet + * @return ERR_OK if the packet was sent OK + * ERR_BUF if p doesn't have enough space for IP/LINK headers + * returns errors returned by netif->output + */ +static err_t +igmp_ip_output_if(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, struct netif *netif) +{ + /* This is the "router alert" option */ + u16_t ra[2]; + ra[0] = PP_HTONS(ROUTER_ALERT); + ra[1] = 0x0000; /* Router shall examine packet */ + IGMP_STATS_INC(igmp.xmit); + return ip_output_if_opt(p, src, dest, IGMP_TTL, 0, IP_PROTO_IGMP, netif, ra, ROUTER_ALERTLEN); +} + +/** + * Send an igmp packet to a specific group. + * + * @param group the group to which to send the packet + * @param type the type of igmp packet to send + */ +static void +igmp_send(struct igmp_group *group, u8_t type) +{ + struct pbuf* p = NULL; + struct igmp_msg* igmp = NULL; + ip_addr_t src = *IP_ADDR_ANY; + ip_addr_t* dest = NULL; + + /* IP header + "router alert" option + IGMP header */ + p = pbuf_alloc(PBUF_TRANSPORT, IGMP_MINLEN, PBUF_RAM); + + if (p) { + igmp = (struct igmp_msg *)p->payload; + LWIP_ASSERT("igmp_send: check that first pbuf can hold struct igmp_msg", + (p->len >= sizeof(struct igmp_msg))); + ip_addr_copy(src, group->netif->ip_addr); + + if (type == IGMP_V2_MEMB_REPORT) { + dest = &(group->group_address); + ip_addr_copy(igmp->igmp_group_address, group->group_address); + group->last_reporter_flag = 1; /* Remember we were the last to report */ + } else { + if (type == IGMP_LEAVE_GROUP) { + dest = &allrouters; + ip_addr_copy(igmp->igmp_group_address, group->group_address); + } + } + + if ((type == IGMP_V2_MEMB_REPORT) || (type == IGMP_LEAVE_GROUP)) { + igmp->igmp_msgtype = type; + igmp->igmp_maxresp = 0; + igmp->igmp_checksum = 0; + igmp->igmp_checksum = inet_chksum(igmp, IGMP_MINLEN); + + igmp_ip_output_if(p, &src, dest, group->netif); + } + + pbuf_free(p); + } else { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_send: not enough memory for igmp_send\n")); + IGMP_STATS_INC(igmp.memerr); + } +} + +#endif /* LWIP_IGMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet.c new file mode 100644 index 0000000..e283a57 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet.c @@ -0,0 +1,42 @@ +/** + * @file + * Functions common to all TCP/IPv4 modules, such as the byte order functions. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/inet.h" + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet_chksum.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet_chksum.c new file mode 100644 index 0000000..960252f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet_chksum.c @@ -0,0 +1,450 @@ +/** + * @file + * Incluse internet checksum functions. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/inet_chksum.h" +#include "lwip/def.h" + +#include +#include + +/* These are some reference implementations of the checksum algorithm, with the + * aim of being simple, correct and fully portable. Checksumming is the + * first thing you would want to optimize for your platform. If you create + * your own version, link it in and in your cc.h put: + * + * #define LWIP_CHKSUM + * + * Or you can select from the implementations below by defining + * LWIP_CHKSUM_ALGORITHM to 1, 2 or 3. + */ + +#ifndef LWIP_CHKSUM +# define LWIP_CHKSUM lwip_standard_chksum +# ifndef LWIP_CHKSUM_ALGORITHM +# define LWIP_CHKSUM_ALGORITHM 2 +# endif +#endif +/* If none set: */ +#ifndef LWIP_CHKSUM_ALGORITHM +# define LWIP_CHKSUM_ALGORITHM 0 +#endif + +#if (LWIP_CHKSUM_ALGORITHM == 1) /* Version #1 */ +/** + * lwip checksum + * + * @param dataptr points to start of data to be summed at any boundary + * @param len length of data to be summed + * @return host order (!) lwip checksum (non-inverted Internet sum) + * + * @note accumulator size limits summable length to 64k + * @note host endianess is irrelevant (p3 RFC1071) + */ +static u16_t +lwip_standard_chksum(void *dataptr, u16_t len) +{ + u32_t acc; + u16_t src; + u8_t *octetptr; + + acc = 0; + /* dataptr may be at odd or even addresses */ + octetptr = (u8_t*)dataptr; + while (len > 1) { + /* declare first octet as most significant + thus assume network order, ignoring host order */ + src = (*octetptr) << 8; + octetptr++; + /* declare second octet as least significant */ + src |= (*octetptr); + octetptr++; + acc += src; + len -= 2; + } + if (len > 0) { + /* accumulate remaining octet */ + src = (*octetptr) << 8; + acc += src; + } + /* add deferred carry bits */ + acc = (acc >> 16) + (acc & 0x0000ffffUL); + if ((acc & 0xffff0000UL) != 0) { + acc = (acc >> 16) + (acc & 0x0000ffffUL); + } + /* This maybe a little confusing: reorder sum using htons() + instead of ntohs() since it has a little less call overhead. + The caller must invert bits for Internet sum ! */ + return htons((u16_t)acc); +} +#endif + +#if (LWIP_CHKSUM_ALGORITHM == 2) /* Alternative version #2 */ +/* + * Curt McDowell + * Broadcom Corp. + * csm@broadcom.com + * + * IP checksum two bytes at a time with support for + * unaligned buffer. + * Works for len up to and including 0x20000. + * by Curt McDowell, Broadcom Corp. 12/08/2005 + * + * @param dataptr points to start of data to be summed at any boundary + * @param len length of data to be summed + * @return host order (!) lwip checksum (non-inverted Internet sum) + */ + +static u16_t +lwip_standard_chksum(void *dataptr, int len) +{ + u8_t *pb = (u8_t *)dataptr; + u16_t *ps, t = 0; + u32_t sum = 0; + int odd = ((mem_ptr_t)pb & 1); + + /* Get aligned to u16_t */ + if (odd && len > 0) { + ((u8_t *)&t)[1] = *pb++; + len--; + } + + /* Add the bulk of the data */ + ps = (u16_t *)(void *)pb; + while (len > 1) { + sum += *ps++; + len -= 2; + } + + /* Consume left-over byte, if any */ + if (len > 0) { + ((u8_t *)&t)[0] = *(u8_t *)ps; + } + + /* Add end bytes */ + sum += t; + + /* Fold 32-bit sum to 16 bits + calling this twice is propably faster than if statements... */ + sum = FOLD_U32T(sum); + sum = FOLD_U32T(sum); + + /* Swap if alignment was odd */ + if (odd) { + sum = SWAP_BYTES_IN_WORD(sum); + } + + return (u16_t)sum; +} +#endif + +#if (LWIP_CHKSUM_ALGORITHM == 3) /* Alternative version #3 */ +/** + * An optimized checksum routine. Basically, it uses loop-unrolling on + * the checksum loop, treating the head and tail bytes specially, whereas + * the inner loop acts on 8 bytes at a time. + * + * @arg start of buffer to be checksummed. May be an odd byte address. + * @len number of bytes in the buffer to be checksummed. + * @return host order (!) lwip checksum (non-inverted Internet sum) + * + * by Curt McDowell, Broadcom Corp. December 8th, 2005 + */ + +static u16_t +lwip_standard_chksum(void *dataptr, int len) +{ + u8_t *pb = (u8_t *)dataptr; + u16_t *ps, t = 0; + u32_t *pl; + u32_t sum = 0, tmp; + /* starts at odd byte address? */ + int odd = ((mem_ptr_t)pb & 1); + + if (odd && len > 0) { + ((u8_t *)&t)[1] = *pb++; + len--; + } + + ps = (u16_t *)pb; + + if (((mem_ptr_t)ps & 3) && len > 1) { + sum += *ps++; + len -= 2; + } + + pl = (u32_t *)ps; + + while (len > 7) { + tmp = sum + *pl++; /* ping */ + if (tmp < sum) { + tmp++; /* add back carry */ + } + + sum = tmp + *pl++; /* pong */ + if (sum < tmp) { + sum++; /* add back carry */ + } + + len -= 8; + } + + /* make room in upper bits */ + sum = FOLD_U32T(sum); + + ps = (u16_t *)pl; + + /* 16-bit aligned word remaining? */ + while (len > 1) { + sum += *ps++; + len -= 2; + } + + /* dangling tail byte remaining? */ + if (len > 0) { /* include odd byte */ + ((u8_t *)&t)[0] = *(u8_t *)ps; + } + + sum += t; /* add end bytes */ + + /* Fold 32-bit sum to 16 bits + calling this twice is propably faster than if statements... */ + sum = FOLD_U32T(sum); + sum = FOLD_U32T(sum); + + if (odd) { + sum = SWAP_BYTES_IN_WORD(sum); + } + + return (u16_t)sum; +} +#endif + +/* inet_chksum_pseudo: + * + * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. + * IP addresses are expected to be in network byte order. + * + * @param p chain of pbufs over that a checksum should be calculated (ip data part) + * @param src source ip address (used for checksum of pseudo header) + * @param dst destination ip address (used for checksum of pseudo header) + * @param proto ip protocol (used for checksum of pseudo header) + * @param proto_len length of the ip data part (used for checksum of pseudo header) + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +inet_chksum_pseudo(struct pbuf *p, + ip_addr_t *src, ip_addr_t *dest, + u8_t proto, u16_t proto_len) +{ + u32_t acc; + u32_t addr; + struct pbuf *q; + u8_t swapped; + + acc = 0; + swapped = 0; + /* iterate through all pbuf in chain */ + for(q = p; q != NULL; q = q->next) { + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", + (void *)q, (void *)q->next)); + acc += LWIP_CHKSUM(q->payload, q->len); + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ + /* just executing this next line is probably faster that the if statement needed + to check whether we really need to execute it, and does no harm */ + acc = FOLD_U32T(acc); + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = SWAP_BYTES_IN_WORD(acc); + } + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ + } + + if (swapped) { + acc = SWAP_BYTES_IN_WORD(acc); + } + addr = ip4_addr_get_u32(src); + acc += (addr & 0xffffUL); + acc += ((addr >> 16) & 0xffffUL); + addr = ip4_addr_get_u32(dest); + acc += (addr & 0xffffUL); + acc += ((addr >> 16) & 0xffffUL); + acc += (u32_t)htons((u16_t)proto); + acc += (u32_t)htons(proto_len); + + /* Fold 32-bit sum to 16 bits + calling this twice is propably faster than if statements... */ + acc = FOLD_U32T(acc); + acc = FOLD_U32T(acc); + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); + return (u16_t)~(acc & 0xffffUL); +} + +/* inet_chksum_pseudo: + * + * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. + * IP addresses are expected to be in network byte order. + * + * @param p chain of pbufs over that a checksum should be calculated (ip data part) + * @param src source ip address (used for checksum of pseudo header) + * @param dst destination ip address (used for checksum of pseudo header) + * @param proto ip protocol (used for checksum of pseudo header) + * @param proto_len length of the ip data part (used for checksum of pseudo header) + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +inet_chksum_pseudo_partial(struct pbuf *p, + ip_addr_t *src, ip_addr_t *dest, + u8_t proto, u16_t proto_len, u16_t chksum_len) +{ + u32_t acc; + u32_t addr; + struct pbuf *q; + u8_t swapped; + u16_t chklen; + + acc = 0; + swapped = 0; + /* iterate through all pbuf in chain */ + for(q = p; (q != NULL) && (chksum_len > 0); q = q->next) { + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", + (void *)q, (void *)q->next)); + chklen = q->len; + if (chklen > chksum_len) { + chklen = chksum_len; + } + acc += LWIP_CHKSUM(q->payload, chklen); + chksum_len -= chklen; + LWIP_ASSERT("delete me", chksum_len < 0x7fff); + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ + /* fold the upper bit down */ + acc = FOLD_U32T(acc); + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = SWAP_BYTES_IN_WORD(acc); + } + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ + } + + if (swapped) { + acc = SWAP_BYTES_IN_WORD(acc); + } + addr = ip4_addr_get_u32(src); + acc += (addr & 0xffffUL); + acc += ((addr >> 16) & 0xffffUL); + addr = ip4_addr_get_u32(dest); + acc += (addr & 0xffffUL); + acc += ((addr >> 16) & 0xffffUL); + acc += (u32_t)htons((u16_t)proto); + acc += (u32_t)htons(proto_len); + + /* Fold 32-bit sum to 16 bits + calling this twice is propably faster than if statements... */ + acc = FOLD_U32T(acc); + acc = FOLD_U32T(acc); + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); + return (u16_t)~(acc & 0xffffUL); +} + +/* inet_chksum: + * + * Calculates the Internet checksum over a portion of memory. Used primarily for IP + * and ICMP. + * + * @param dataptr start of the buffer to calculate the checksum (no alignment needed) + * @param len length of the buffer to calculate the checksum + * @return checksum (as u16_t) to be saved directly in the protocol header + */ + +u16_t +inet_chksum(void *dataptr, u16_t len) +{ + return ~LWIP_CHKSUM(dataptr, len); +} + +/** + * Calculate a checksum over a chain of pbufs (without pseudo-header, much like + * inet_chksum only pbufs are used). + * + * @param p pbuf chain over that the checksum should be calculated + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +inet_chksum_pbuf(struct pbuf *p) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped; + + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { + acc += LWIP_CHKSUM(q->payload, q->len); + acc = FOLD_U32T(acc); + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = SWAP_BYTES_IN_WORD(acc); + } + } + + if (swapped) { + acc = SWAP_BYTES_IN_WORD(acc); + } + return (u16_t)~(acc & 0xffffUL); +} + +/* These are some implementations for LWIP_CHKSUM_COPY, which copies data + * like MEMCPY but generates a checksum at the same time. Since this is a + * performance-sensitive function, you might want to create your own version + * in assembly targeted at your hardware by defining it in lwipopts.h: + * #define LWIP_CHKSUM_COPY(dst, src, len) your_chksum_copy(dst, src, len) + */ + +#if (LWIP_CHKSUM_COPY_ALGORITHM == 1) /* Version #1 */ +/** Safe but slow: first call MEMCPY, then call LWIP_CHKSUM. + * For architectures with big caches, data might still be in cache when + * generating the checksum after copying. + */ +u16_t +lwip_chksum_copy(void *dst, const void *src, u16_t len) +{ + MEMCPY(dst, src, len); + return LWIP_CHKSUM(dst, len); +} +#endif /* (LWIP_CHKSUM_COPY_ALGORITHM == 1) */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip.c new file mode 100644 index 0000000..6f24871 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip.c @@ -0,0 +1,857 @@ +/** + * @file + * This is the IPv4 layer implementation for incoming and outgoing IP traffic. + * + * @see ip_frag.c + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" +#include "lwip/ip.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/ip_frag.h" +#include "lwip/inet_chksum.h" +#include "lwip/netif.h" +#include "lwip/icmp.h" +#include "lwip/igmp.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/tcp_impl.h" +#include "lwip/snmp.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" +#include "lwip/stats.h" +#include "arch/perf.h" + +#include + +/** Set this to 0 in the rare case of wanting to call an extra function to + * generate the IP checksum (in contrast to calculating it on-the-fly). */ +#ifndef LWIP_INLINE_IP_CHKSUM +#define LWIP_INLINE_IP_CHKSUM 1 +#endif +#if LWIP_INLINE_IP_CHKSUM && CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP_INLINE 1 +#else +#define CHECKSUM_GEN_IP_INLINE 0 +#endif + +#if LWIP_DHCP || defined(LWIP_IP_ACCEPT_UDP_PORT) +#define IP_ACCEPT_LINK_LAYER_ADDRESSING 1 + +/** Some defines for DHCP to let link-layer-addressed packets through while the + * netif is down. + * To use this in your own application/protocol, define LWIP_IP_ACCEPT_UDP_PORT + * to return 1 if the port is accepted and 0 if the port is not accepted. + */ +#if LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) +/* accept DHCP client port and custom port */ +#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (((port) == PP_NTOHS(DHCP_CLIENT_PORT)) \ + || (LWIP_IP_ACCEPT_UDP_PORT(port))) +#elif defined(LWIP_IP_ACCEPT_UDP_PORT) /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */ +/* accept custom port only */ +#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (LWIP_IP_ACCEPT_UDP_PORT(dst_port)) +#else /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */ +/* accept DHCP client port only */ +#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) ((port) == PP_NTOHS(DHCP_CLIENT_PORT)) +#endif /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */ + +#else /* LWIP_DHCP */ +#define IP_ACCEPT_LINK_LAYER_ADDRESSING 0 +#endif /* LWIP_DHCP */ + +/** + * The interface that provided the packet for the current callback + * invocation. + */ +struct netif *current_netif; + +/** + * Header of the input packet currently being processed. + */ +const struct ip_hdr *current_header; +/** Source IP address of current_header */ +ip_addr_t current_iphdr_src; +/** Destination IP address of current_header */ +ip_addr_t current_iphdr_dest; + +/** The IP header ID of the next outgoing IP packet */ +static u16_t ip_id; + +/** + * Finds the appropriate network interface for a given IP address. It + * searches the list of network interfaces linearly. A match is found + * if the masked IP address of the network interface equals the masked + * IP address given to the function. + * + * @param dest the destination IP address for which to find the route + * @return the netif on which to send to reach dest + */ +struct netif * +ip_route(ip_addr_t *dest) +{ + struct netif *netif; + + /* iterate through netifs */ + for(netif = netif_list; netif != NULL; netif = netif->next) { + /* network mask matches? */ + if (netif_is_up(netif)) { + if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { + /* return netif on which to forward IP packet */ + return netif; + } + } + } + if ((netif_default == NULL) || (!netif_is_up(netif_default))) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); + IP_STATS_INC(ip.rterr); + snmp_inc_ipoutnoroutes(); + return NULL; + } + /* no matching netif found, use default netif */ + return netif_default; +} + +#if IP_FORWARD +/** + * Forwards an IP packet. It finds an appropriate route for the + * packet, decrements the TTL value of the packet, adjusts the + * checksum and outputs the packet on the appropriate interface. + * + * @param p the packet to forward (p->payload points to IP header) + * @param iphdr the IP header of the input packet + * @param inp the netif on which this packet was received + */ +static void +ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp) +{ + struct netif *netif; + + PERF_START; + + /* RFC3927 2.7: do not forward link-local addresses */ + if (ip_addr_islinklocal(¤t_iphdr_dest)) { + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not forwarding LLA %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(¤t_iphdr_dest), ip4_addr2_16(¤t_iphdr_dest), + ip4_addr3_16(¤t_iphdr_dest), ip4_addr4_16(¤t_iphdr_dest))); + goto return_noroute; + } + + /* Find network interface where to forward this IP packet to. */ + netif = ip_route(¤t_iphdr_dest); + if (netif == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for %"U16_F".%"U16_F".%"U16_F".%"U16_F" found\n", + ip4_addr1_16(¤t_iphdr_dest), ip4_addr2_16(¤t_iphdr_dest), + ip4_addr3_16(¤t_iphdr_dest), ip4_addr4_16(¤t_iphdr_dest))); + goto return_noroute; + } + /* Do not forward packets onto the same network interface on which + * they arrived. */ + if (netif == inp) { + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n")); + goto return_noroute; + } + + /* decrement TTL */ + IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1); + /* send ICMP if TTL == 0 */ + if (IPH_TTL(iphdr) == 0) { + snmp_inc_ipinhdrerrors(); +#if LWIP_ICMP + /* Don't send ICMP messages in response to ICMP messages */ + if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) { + icmp_time_exceeded(p, ICMP_TE_TTL); + } +#endif /* LWIP_ICMP */ + return; + } + + /* Incrementally update the IP checksum. */ + if (IPH_CHKSUM(iphdr) >= PP_HTONS(0xffffU - 0x100)) { + IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + PP_HTONS(0x100) + 1); + } else { + IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + PP_HTONS(0x100)); + } + + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(¤t_iphdr_dest), ip4_addr2_16(¤t_iphdr_dest), + ip4_addr3_16(¤t_iphdr_dest), ip4_addr4_16(¤t_iphdr_dest))); + + IP_STATS_INC(ip.fw); + IP_STATS_INC(ip.xmit); + snmp_inc_ipforwdatagrams(); + + PERF_STOP("ip_forward"); + /* transmit pbuf on chosen interface */ + netif->output(netif, p, ¤t_iphdr_dest); + return; +return_noroute: + snmp_inc_ipoutnoroutes(); +} +#endif /* IP_FORWARD */ + +/** + * This function is called by the network interface device driver when + * an IP packet is received. The function does the basic checks of the + * IP header such as packet size being at least larger than the header + * size etc. If the packet was not destined for us, the packet is + * forwarded (using ip_forward). The IP checksum is always checked. + * + * Finally, the packet is sent to the upper layer protocol input function. + * + * @param p the received IP packet (p->payload points to IP header) + * @param inp the netif on which this packet was received + * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't + * processed, but currently always returns ERR_OK) + */ +err_t +ip_input(struct pbuf *p, struct netif *inp) +{ + struct ip_hdr *iphdr; + struct netif *netif; + u16_t iphdr_hlen; + u16_t iphdr_len; +#if IP_ACCEPT_LINK_LAYER_ADDRESSING + int check_ip_src=1; +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ + + IP_STATS_INC(ip.recv); + snmp_inc_ipinreceives(); + + /* identify the IP header */ + iphdr = (struct ip_hdr *)p->payload; + if (IPH_V(iphdr) != 4) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr))); + ip_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.err); + IP_STATS_INC(ip.drop); + snmp_inc_ipinhdrerrors(); + return ERR_OK; + } + + /* obtain IP header length in number of 32-bit words */ + iphdr_hlen = IPH_HL(iphdr); + /* calculate IP header length in bytes */ + iphdr_hlen *= 4; + /* obtain ip length in bytes */ + iphdr_len = ntohs(IPH_LEN(iphdr)); + + /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */ + if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len)) { + if (iphdr_hlen > p->len) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n", + iphdr_hlen, p->len)); + } + if (iphdr_len > p->tot_len) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n", + iphdr_len, p->tot_len)); + } + /* free (drop) packet pbufs */ + pbuf_free(p); + IP_STATS_INC(ip.lenerr); + IP_STATS_INC(ip.drop); + snmp_inc_ipindiscards(); + return ERR_OK; + } + + /* verify checksum */ +#if CHECKSUM_CHECK_IP + if (inet_chksum(iphdr, iphdr_hlen) != 0) { + + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdr_hlen))); + ip_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.chkerr); + IP_STATS_INC(ip.drop); + snmp_inc_ipinhdrerrors(); + return ERR_OK; + } +#endif + + /* Trim pbuf. This should have been done at the netif layer, + * but we'll do it anyway just to be sure that its done. */ + pbuf_realloc(p, iphdr_len); + + /* copy IP addresses to aligned ip_addr_t */ + ip_addr_copy(current_iphdr_dest, iphdr->dest); + ip_addr_copy(current_iphdr_src, iphdr->src); + + /* match packet against an interface, i.e. is this packet for us? */ +#if LWIP_IGMP + if (ip_addr_ismulticast(¤t_iphdr_dest)) { + if ((inp->flags & NETIF_FLAG_IGMP) && (igmp_lookfor_group(inp, ¤t_iphdr_dest))) { + netif = inp; + } else { + netif = NULL; + } + } else +#endif /* LWIP_IGMP */ + { + /* start trying with inp. if that's not acceptable, start walking the + list of configured netifs. + 'first' is used as a boolean to mark whether we started walking the list */ + int first = 1; + netif = inp; + do { + LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n", + ip4_addr_get_u32(&iphdr->dest), ip4_addr_get_u32(&netif->ip_addr), + ip4_addr_get_u32(&iphdr->dest) & ip4_addr_get_u32(&netif->netmask), + ip4_addr_get_u32(&netif->ip_addr) & ip4_addr_get_u32(&netif->netmask), + ip4_addr_get_u32(&iphdr->dest) & ~ip4_addr_get_u32(&netif->netmask))); + + /* interface is up and configured? */ + if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) { + /* unicast to this interface address? */ + if (ip_addr_cmp(¤t_iphdr_dest, &(netif->ip_addr)) || + /* or broadcast on this interface network address? */ + ip_addr_isbroadcast(¤t_iphdr_dest, netif)) { + LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n", + netif->name[0], netif->name[1])); + /* break out of for loop */ + break; + } +#if LWIP_AUTOIP + /* connections to link-local addresses must persist after changing + the netif's address (RFC3927 ch. 1.9) */ + if ((netif->autoip != NULL) && + ip_addr_cmp(¤t_iphdr_dest, &(netif->autoip->llipaddr))) { + LWIP_DEBUGF(IP_DEBUG, ("ip_input: LLA packet accepted on interface %c%c\n", + netif->name[0], netif->name[1])); + /* break out of for loop */ + break; + } +#endif /* LWIP_AUTOIP */ + } + if (first) { + first = 0; + netif = netif_list; + } else { + netif = netif->next; + } + if (netif == inp) { + netif = netif->next; + } + } while(netif != NULL); + } + +#if IP_ACCEPT_LINK_LAYER_ADDRESSING + /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed + * using link layer addressing (such as Ethernet MAC) so we must not filter on IP. + * According to RFC 1542 section 3.1.1, referred by RFC 2131). + * + * If you want to accept private broadcast communication while a netif is down, + * define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.: + * + * #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345)) + */ + if (netif == NULL) { + /* remote port is DHCP server? */ + if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { + struct udp_hdr *udphdr = (struct udp_hdr *)((u8_t *)iphdr + iphdr_hlen); + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: UDP packet to DHCP client port %"U16_F"\n", + ntohs(udphdr->dest))); + if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: DHCP packet accepted.\n")); + netif = inp; + check_ip_src = 0; + } + } + } +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ + + /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */ +#if IP_ACCEPT_LINK_LAYER_ADDRESSING + /* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */ + if (check_ip_src && !ip_addr_isany(¤t_iphdr_src)) +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ + { if ((ip_addr_isbroadcast(¤t_iphdr_src, inp)) || + (ip_addr_ismulticast(¤t_iphdr_src))) { + /* packet source is not valid */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip_input: packet source is not valid.\n")); + /* free (drop) packet pbufs */ + pbuf_free(p); + IP_STATS_INC(ip.drop); + snmp_inc_ipinaddrerrors(); + snmp_inc_ipindiscards(); + return ERR_OK; + } + } + + /* packet not for us? */ + if (netif == NULL) { + /* packet not for us, route or discard */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: packet not for us.\n")); +#if IP_FORWARD + /* non-broadcast packet? */ + if (!ip_addr_isbroadcast(¤t_iphdr_dest, inp)) { + /* try to forward IP packet on (other) interfaces */ + ip_forward(p, iphdr, inp); + } else +#endif /* IP_FORWARD */ + { + snmp_inc_ipinaddrerrors(); + snmp_inc_ipindiscards(); + } + pbuf_free(p); + return ERR_OK; + } + /* packet consists of multiple fragments? */ + if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) { +#if IP_REASSEMBLY /* packet fragment reassembly code present? */ + LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n", + ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8)); + /* reassemble the packet*/ + p = ip_reass(p); + /* packet not fully reassembled yet? */ + if (p == NULL) { + return ERR_OK; + } + iphdr = (struct ip_hdr *)p->payload; +#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */ + pbuf_free(p); + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n", + ntohs(IPH_OFFSET(iphdr)))); + IP_STATS_INC(ip.opterr); + IP_STATS_INC(ip.drop); + /* unsupported protocol feature */ + snmp_inc_ipinunknownprotos(); + return ERR_OK; +#endif /* IP_REASSEMBLY */ + } + +#if IP_OPTIONS_ALLOWED == 0 /* no support for IP options in the IP header? */ + +#if LWIP_IGMP + /* there is an extra "router alert" option in IGMP messages which we allow for but do not police */ + if((iphdr_hlen > IP_HLEN) && (IPH_PROTO(iphdr) != IP_PROTO_IGMP)) { +#else + if (iphdr_hlen > IP_HLEN) { +#endif /* LWIP_IGMP */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since there were IP options (while IP_OPTIONS_ALLOWED == 0).\n")); + pbuf_free(p); + IP_STATS_INC(ip.opterr); + IP_STATS_INC(ip.drop); + /* unsupported protocol feature */ + snmp_inc_ipinunknownprotos(); + return ERR_OK; + } +#endif /* IP_OPTIONS_ALLOWED == 0 */ + + /* send to upper layers */ + LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n")); + ip_debug_print(p); + LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); + + current_netif = inp; + current_header = iphdr; + +#if LWIP_RAW + /* raw input did not eat the packet? */ + if (raw_input(p, inp) == 0) +#endif /* LWIP_RAW */ + { + + switch (IPH_PROTO(iphdr)) { +#if LWIP_UDP + case IP_PROTO_UDP: +#if LWIP_UDPLITE + case IP_PROTO_UDPLITE: +#endif /* LWIP_UDPLITE */ + snmp_inc_ipindelivers(); + udp_input(p, inp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case IP_PROTO_TCP: + snmp_inc_ipindelivers(); + tcp_input(p, inp); + break; +#endif /* LWIP_TCP */ +#if LWIP_ICMP + case IP_PROTO_ICMP: + snmp_inc_ipindelivers(); + icmp_input(p, inp); + break; +#endif /* LWIP_ICMP */ +#if LWIP_IGMP + case IP_PROTO_IGMP: + igmp_input(p, inp, ¤t_iphdr_dest); + break; +#endif /* LWIP_IGMP */ + default: +#if LWIP_ICMP + /* send ICMP destination protocol unreachable unless is was a broadcast */ + if (!ip_addr_isbroadcast(¤t_iphdr_dest, inp) && + !ip_addr_ismulticast(¤t_iphdr_dest)) { + p->payload = iphdr; + icmp_dest_unreach(p, ICMP_DUR_PROTO); + } +#endif /* LWIP_ICMP */ + pbuf_free(p); + + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr))); + + IP_STATS_INC(ip.proterr); + IP_STATS_INC(ip.drop); + snmp_inc_ipinunknownprotos(); + } + } + + current_netif = NULL; + current_header = NULL; + ip_addr_set_any(¤t_iphdr_src); + ip_addr_set_any(¤t_iphdr_dest); + + return ERR_OK; +} + +/** + * Sends an IP packet on a network interface. This function constructs + * the IP header and calculates the IP header checksum. If the source + * IP address is NULL, the IP address of the outgoing network + * interface is filled in as source address. + * If the destination IP address is IP_HDRINCL, p is assumed to already + * include an IP header and p->payload points to it instead of the data. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == IP_HDRINCL, p already includes an IP + header and p->payload points to that IP header) + * @param src the source IP address to send from (if src == IP_ADDR_ANY, the + * IP address of the netif used to send is used as source address) + * @param dest the destination IP address to send the packet to + * @param ttl the TTL value to be set in the IP header + * @param tos the TOS value to be set in the IP header + * @param proto the PROTOCOL to be set in the IP header + * @param netif the netif on which to send this packet + * @return ERR_OK if the packet was sent OK + * ERR_BUF if p doesn't have enough space for IP/LINK headers + * returns errors returned by netif->output + * + * @note ip_id: RFC791 "some host may be able to simply use + * unique identifiers independent of destination" + */ +err_t +ip_output_if(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) +{ +#if IP_OPTIONS_SEND + return ip_output_if_opt(p, src, dest, ttl, tos, proto, netif, NULL, 0); +} + +/** + * Same as ip_output_if() but with the possibility to include IP options: + * + * @ param ip_options pointer to the IP options, copied into the IP header + * @ param optlen length of ip_options + */ +err_t ip_output_if_opt(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen) +{ +#endif /* IP_OPTIONS_SEND */ + struct ip_hdr *iphdr; + ip_addr_t dest_addr; +#if CHECKSUM_GEN_IP_INLINE + u32_t chk_sum = 0; +#endif /* CHECKSUM_GEN_IP_INLINE */ + + /* pbufs passed to IP must have a ref-count of 1 as their payload pointer + gets altered as the packet is passed down the stack */ + LWIP_ASSERT("p->ref == 1", p->ref == 1); + + snmp_inc_ipoutrequests(); + + /* Should the IP header be generated or is it already included in p? */ + if (dest != IP_HDRINCL) { + u16_t ip_hlen = IP_HLEN; +#if IP_OPTIONS_SEND + u16_t optlen_aligned = 0; + if (optlen != 0) { +#if CHECKSUM_GEN_IP_INLINE + int i; +#endif /* CHECKSUM_GEN_IP_INLINE */ + /* round up to a multiple of 4 */ + optlen_aligned = ((optlen + 3) & ~3); + ip_hlen += optlen_aligned; + /* First write in the IP options */ + if (pbuf_header(p, optlen_aligned)) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_output_if_opt: not enough room for IP options in pbuf\n")); + IP_STATS_INC(ip.err); + snmp_inc_ipoutdiscards(); + return ERR_BUF; + } + MEMCPY(p->payload, ip_options, optlen); + if (optlen < optlen_aligned) { + /* zero the remaining bytes */ + memset(((char*)p->payload) + optlen, 0, optlen_aligned - optlen); + } +#if CHECKSUM_GEN_IP_INLINE + for (i = 0; i < optlen_aligned/2; i++) { + chk_sum += ((u16_t*)p->payload)[i]; + } +#endif /* CHECKSUM_GEN_IP_INLINE */ + } +#endif /* IP_OPTIONS_SEND */ + /* generate IP header */ + if (pbuf_header(p, IP_HLEN)) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_output: not enough room for IP header in pbuf\n")); + + IP_STATS_INC(ip.err); + snmp_inc_ipoutdiscards(); + return ERR_BUF; + } + + iphdr = (struct ip_hdr *)p->payload; + LWIP_ASSERT("check that first pbuf can hold struct ip_hdr", + (p->len >= sizeof(struct ip_hdr))); + + IPH_TTL_SET(iphdr, ttl); + IPH_PROTO_SET(iphdr, proto); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += LWIP_MAKE_U16(proto, ttl); +#endif /* CHECKSUM_GEN_IP_INLINE */ + + /* dest cannot be NULL here */ + ip_addr_copy(iphdr->dest, *dest); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF; + chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16; +#endif /* CHECKSUM_GEN_IP_INLINE */ + + IPH_VHLTOS_SET(iphdr, 4, ip_hlen / 4, tos); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += iphdr->_v_hl_tos; +#endif /* CHECKSUM_GEN_IP_INLINE */ + IPH_LEN_SET(iphdr, htons(p->tot_len)); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += iphdr->_len; +#endif /* CHECKSUM_GEN_IP_INLINE */ + IPH_OFFSET_SET(iphdr, 0); + IPH_ID_SET(iphdr, htons(ip_id)); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += iphdr->_id; +#endif /* CHECKSUM_GEN_IP_INLINE */ + ++ip_id; + + if (ip_addr_isany(src)) { + ip_addr_copy(iphdr->src, netif->ip_addr); + } else { + /* src cannot be NULL here */ + ip_addr_copy(iphdr->src, *src); + } + +#if CHECKSUM_GEN_IP_INLINE + chk_sum += ip4_addr_get_u32(&iphdr->src) & 0xFFFF; + chk_sum += ip4_addr_get_u32(&iphdr->src) >> 16; + chk_sum = (chk_sum >> 16) + (chk_sum & 0xFFFF); + chk_sum = (chk_sum >> 16) + chk_sum; + chk_sum = ~chk_sum; + iphdr->_chksum = chk_sum; /* network order */ +#else /* CHECKSUM_GEN_IP_INLINE */ + IPH_CHKSUM_SET(iphdr, 0); +#if CHECKSUM_GEN_IP + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, ip_hlen)); +#endif +#endif /* CHECKSUM_GEN_IP_INLINE */ + } else { + /* IP header already included in p */ + iphdr = (struct ip_hdr *)p->payload; + ip_addr_copy(dest_addr, iphdr->dest); + dest = &dest_addr; + } + + IP_STATS_INC(ip.xmit); + + LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num)); + ip_debug_print(p); + +#if ENABLE_LOOPBACK + if (ip_addr_cmp(dest, &netif->ip_addr)) { + /* Packet to self, enqueue it for loopback */ + LWIP_DEBUGF(IP_DEBUG, ("netif_loop_output()")); + return netif_loop_output(netif, p, dest); + } +#if LWIP_IGMP + if ((p->flags & PBUF_FLAG_MCASTLOOP) != 0) { + netif_loop_output(netif, p, dest); + } +#endif /* LWIP_IGMP */ +#endif /* ENABLE_LOOPBACK */ +#if IP_FRAG + /* don't fragment if interface has mtu set to 0 [loopif] */ + if (netif->mtu && (p->tot_len > netif->mtu)) { + return ip_frag(p, netif, dest); + } +#endif /* IP_FRAG */ + + LWIP_DEBUGF(IP_DEBUG, ("netif->output()")); + return netif->output(netif, p, dest); +} + +/** + * Simple interface to ip_output_if. It finds the outgoing network + * interface and calls upon ip_output_if to do the actual work. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == IP_HDRINCL, p already includes an IP + header and p->payload points to that IP header) + * @param src the source IP address to send from (if src == IP_ADDR_ANY, the + * IP address of the netif used to send is used as source address) + * @param dest the destination IP address to send the packet to + * @param ttl the TTL value to be set in the IP header + * @param tos the TOS value to be set in the IP header + * @param proto the PROTOCOL to be set in the IP header + * + * @return ERR_RTE if no route is found + * see ip_output_if() for more return values + */ +err_t +ip_output(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto) +{ + struct netif *netif; + + /* pbufs passed to IP must have a ref-count of 1 as their payload pointer + gets altered as the packet is passed down the stack */ + LWIP_ASSERT("p->ref == 1", p->ref == 1); + + if ((netif = ip_route(dest)) == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); + IP_STATS_INC(ip.rterr); + return ERR_RTE; + } + + return ip_output_if(p, src, dest, ttl, tos, proto, netif); +} + +#if LWIP_NETIF_HWADDRHINT +/** Like ip_output, but takes and addr_hint pointer that is passed on to netif->addr_hint + * before calling ip_output_if. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == IP_HDRINCL, p already includes an IP + header and p->payload points to that IP header) + * @param src the source IP address to send from (if src == IP_ADDR_ANY, the + * IP address of the netif used to send is used as source address) + * @param dest the destination IP address to send the packet to + * @param ttl the TTL value to be set in the IP header + * @param tos the TOS value to be set in the IP header + * @param proto the PROTOCOL to be set in the IP header + * @param addr_hint address hint pointer set to netif->addr_hint before + * calling ip_output_if() + * + * @return ERR_RTE if no route is found + * see ip_output_if() for more return values + */ +err_t +ip_output_hinted(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint) +{ + struct netif *netif; + err_t err; + + /* pbufs passed to IP must have a ref-count of 1 as their payload pointer + gets altered as the packet is passed down the stack */ + LWIP_ASSERT("p->ref == 1", p->ref == 1); + + if ((netif = ip_route(dest)) == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); + IP_STATS_INC(ip.rterr); + return ERR_RTE; + } + + netif->addr_hint = addr_hint; + err = ip_output_if(p, src, dest, ttl, tos, proto, netif); + netif->addr_hint = NULL; + + return err; +} +#endif /* LWIP_NETIF_HWADDRHINT*/ + +#if IP_DEBUG +/* Print an IP header by using LWIP_DEBUGF + * @param p an IP packet, p->payload pointing to the IP header + */ +void +ip_debug_print(struct pbuf *p) +{ + struct ip_hdr *iphdr = (struct ip_hdr *)p->payload; + u8_t *payload; + + payload = (u8_t *)iphdr + IP_HLEN; + + LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n", + IPH_V(iphdr), + IPH_HL(iphdr), + IPH_TOS(iphdr), + ntohs(IPH_LEN(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n", + ntohs(IPH_ID(iphdr)), + ntohs(IPH_OFFSET(iphdr)) >> 15 & 1, + ntohs(IPH_OFFSET(iphdr)) >> 14 & 1, + ntohs(IPH_OFFSET(iphdr)) >> 13 & 1, + ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n", + IPH_TTL(iphdr), + IPH_PROTO(iphdr), + ntohs(IPH_CHKSUM(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n", + ip4_addr1_16(&iphdr->src), + ip4_addr2_16(&iphdr->src), + ip4_addr3_16(&iphdr->src), + ip4_addr4_16(&iphdr->src))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n", + ip4_addr1_16(&iphdr->dest), + ip4_addr2_16(&iphdr->dest), + ip4_addr3_16(&iphdr->dest), + ip4_addr4_16(&iphdr->dest))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* IP_DEBUG */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_addr.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_addr.c new file mode 100644 index 0000000..8f633ff --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_addr.c @@ -0,0 +1,312 @@ +/** + * @file + * This is the IPv4 address tools implementation. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */ +const ip_addr_t ip_addr_any = { IPADDR_ANY }; +const ip_addr_t ip_addr_broadcast = { IPADDR_BROADCAST }; + +/** + * Determine if an address is a broadcast address on a network interface + * + * @param addr address to be checked + * @param netif the network interface against which the address is checked + * @return returns non-zero if the address is a broadcast address + */ +u8_t +ip4_addr_isbroadcast(u32_t addr, const struct netif *netif) +{ + ip_addr_t ipaddr; + ip4_addr_set_u32(&ipaddr, addr); + + /* all ones (broadcast) or all zeroes (old skool broadcast) */ + if ((~addr == IPADDR_ANY) || + (addr == IPADDR_ANY)) { + return 1; + /* no broadcast support on this network interface? */ + } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) { + /* the given address cannot be a broadcast address + * nor can we check against any broadcast addresses */ + return 0; + /* address matches network interface address exactly? => no broadcast */ + } else if (addr == ip4_addr_get_u32(&netif->ip_addr)) { + return 0; + /* on the same (sub) network... */ + } else if (ip_addr_netcmp(&ipaddr, &(netif->ip_addr), &(netif->netmask)) + /* ...and host identifier bits are all ones? =>... */ + && ((addr & ~ip4_addr_get_u32(&netif->netmask)) == + (IPADDR_BROADCAST & ~ip4_addr_get_u32(&netif->netmask)))) { + /* => network broadcast address */ + return 1; + } else { + return 0; + } +} + +/** Checks if a netmask is valid (starting with ones, then only zeros) + * + * @param netmask the IPv4 netmask to check (in network byte order!) + * @return 1 if the netmask is valid, 0 if it is not + */ +u8_t +ip4_addr_netmask_valid(u32_t netmask) +{ + u32_t mask; + u32_t nm_hostorder = lwip_htonl(netmask); + + /* first, check for the first zero */ + for (mask = 1UL << 31 ; mask != 0; mask >>= 1) { + if ((nm_hostorder & mask) == 0) { + break; + } + } + /* then check that there is no one */ + for (; mask != 0; mask >>= 1) { + if ((nm_hostorder & mask) != 0) { + /* there is a one after the first zero -> invalid */ + return 0; + } + } + /* no one after the first zero -> valid */ + return 1; +} + +/* Here for now until needed in other places in lwIP */ +#ifndef isprint +#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up) +#define isprint(c) in_range(c, 0x20, 0x7f) +#define isdigit(c) in_range(c, '0', '9') +#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) +#define islower(c) in_range(c, 'a', 'z') +#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v') +#endif + +/** + * Ascii internet address interpretation routine. + * The value returned is in network order. + * + * @param cp IP address in ascii represenation (e.g. "127.0.0.1") + * @return ip address in network order + */ +u32_t +ipaddr_addr(const char *cp) +{ + ip_addr_t val; + + if (ipaddr_aton(cp, &val)) { + return ip4_addr_get_u32(&val); + } + return (IPADDR_NONE); +} + +/** + * Check whether "cp" is a valid ascii representation + * of an Internet address and convert to a binary address. + * Returns 1 if the address is valid, 0 if not. + * This replaces inet_addr, the return value from which + * cannot distinguish between failure and a local broadcast address. + * + * @param cp IP address in ascii represenation (e.g. "127.0.0.1") + * @param addr pointer to which to save the ip address in network order + * @return 1 if cp could be converted to addr, 0 on failure + */ +int +ipaddr_aton(const char *cp, ip_addr_t *addr) +{ + u32_t val; + u8_t base; + char c; + u32_t parts[4]; + u32_t *pp = parts; + + c = *cp; + for (;;) { + /* + * Collect number up to ``.''. + * Values are specified as for C: + * 0x=hex, 0=octal, 1-9=decimal. + */ + if (!isdigit(c)) + return (0); + val = 0; + base = 10; + if (c == '0') { + c = *++cp; + if (c == 'x' || c == 'X') { + base = 16; + c = *++cp; + } else + base = 8; + } + for (;;) { + if (isdigit(c)) { + val = (val * base) + (int)(c - '0'); + c = *++cp; + } else if (base == 16 && isxdigit(c)) { + val = (val << 4) | (int)(c + 10 - (islower(c) ? 'a' : 'A')); + c = *++cp; + } else + break; + } + if (c == '.') { + /* + * Internet format: + * a.b.c.d + * a.b.c (with c treated as 16 bits) + * a.b (with b treated as 24 bits) + */ + if (pp >= parts + 3) { + return (0); + } + *pp++ = val; + c = *++cp; + } else + break; + } + /* + * Check for trailing characters. + */ + if (c != '\0' && !isspace(c)) { + return (0); + } + /* + * Concoct the address according to + * the number of parts specified. + */ + switch (pp - parts + 1) { + + case 0: + return (0); /* initial nondigit */ + + case 1: /* a -- 32 bits */ + break; + + case 2: /* a.b -- 8.24 bits */ + if (val > 0xffffffUL) { + return (0); + } + val |= parts[0] << 24; + break; + + case 3: /* a.b.c -- 8.8.16 bits */ + if (val > 0xffff) { + return (0); + } + val |= (parts[0] << 24) | (parts[1] << 16); + break; + + case 4: /* a.b.c.d -- 8.8.8.8 bits */ + if (val > 0xff) { + return (0); + } + val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); + break; + default: + LWIP_ASSERT("unhandled", 0); + break; + } + if (addr) { + ip4_addr_set_u32(addr, htonl(val)); + } + return (1); +} + +/** + * Convert numeric IP address into decimal dotted ASCII representation. + * returns ptr to static buffer; not reentrant! + * + * @param addr ip address in network order to convert + * @return pointer to a global static (!) buffer that holds the ASCII + * represenation of addr + */ +char * +ipaddr_ntoa(const ip_addr_t *addr) +{ + static char str[16]; + return ipaddr_ntoa_r(addr, str, 16); +} + +/** + * Same as ipaddr_ntoa, but reentrant since a user-supplied buffer is used. + * + * @param addr ip address in network order to convert + * @param buf target buffer where the string is stored + * @param buflen length of buf + * @return either pointer to buf which now holds the ASCII + * representation of addr or NULL if buf was too small + */ +char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen) +{ + u32_t s_addr; + char inv[3]; + char *rp; + u8_t *ap; + u8_t rem; + u8_t n; + u8_t i; + int len = 0; + + s_addr = ip4_addr_get_u32(addr); + + rp = buf; + ap = (u8_t *)&s_addr; + for(n = 0; n < 4; n++) { + i = 0; + do { + rem = *ap % (u8_t)10; + *ap /= (u8_t)10; + inv[i++] = '0' + rem; + } while(*ap); + while(i--) { + if (len++ >= buflen) { + return NULL; + } + *rp++ = inv[i]; + } + if (len++ >= buflen) { + return NULL; + } + *rp++ = '.'; + ap++; + } + *--rp = 0; + return buf; +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_frag.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_frag.c new file mode 100644 index 0000000..8d18434 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_frag.c @@ -0,0 +1,863 @@ +/** + * @file + * This is the IPv4 packet segmentation and reassembly implementation. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * Simon Goldschmidt + * original reassembly code by Adam Dunkels + * + */ + +#include "lwip/opt.h" +#include "lwip/ip_frag.h" +#include "lwip/def.h" +#include "lwip/inet_chksum.h" +#include "lwip/netif.h" +#include "lwip/snmp.h" +#include "lwip/stats.h" +#include "lwip/icmp.h" + +#include + +#if IP_REASSEMBLY +/** + * The IP reassembly code currently has the following limitations: + * - IP header options are not supported + * - fragments must not overlap (e.g. due to different routes), + * currently, overlapping or duplicate fragments are thrown away + * if IP_REASS_CHECK_OVERLAP=1 (the default)! + * + * @todo: work with IP header options + */ + +/** Setting this to 0, you can turn off checking the fragments for overlapping + * regions. The code gets a little smaller. Only use this if you know that + * overlapping won't occur on your network! */ +#ifndef IP_REASS_CHECK_OVERLAP +#define IP_REASS_CHECK_OVERLAP 1 +#endif /* IP_REASS_CHECK_OVERLAP */ + +/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is + * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller. + * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA + * is set to 1, so one datagram can be reassembled at a time, only. */ +#ifndef IP_REASS_FREE_OLDEST +#define IP_REASS_FREE_OLDEST 1 +#endif /* IP_REASS_FREE_OLDEST */ + +#define IP_REASS_FLAG_LASTFRAG 0x01 + +/** This is a helper struct which holds the starting + * offset and the ending offset of this fragment to + * easily chain the fragments. + * It has the same packing requirements as the IP header, since it replaces + * the IP header in memory in incoming fragments (after copying it) to keep + * track of the various fragments. (-> If the IP header doesn't need packing, + * this struct doesn't need packing, too.) + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_reass_helper { + PACK_STRUCT_FIELD(struct pbuf *next_pbuf); + PACK_STRUCT_FIELD(u16_t start); + PACK_STRUCT_FIELD(u16_t end); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IP_ADDRESSES_AND_ID_MATCH(iphdrA, iphdrB) \ + (ip_addr_cmp(&(iphdrA)->src, &(iphdrB)->src) && \ + ip_addr_cmp(&(iphdrA)->dest, &(iphdrB)->dest) && \ + IPH_ID(iphdrA) == IPH_ID(iphdrB)) ? 1 : 0 + +/* global variables */ +static struct ip_reassdata *reassdatagrams; +static u16_t ip_reass_pbufcount; + +/* function prototypes */ +static void ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev); +static int ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev); + +/** + * Reassembly timer base function + * for both NO_SYS == 0 and 1 (!). + * + * Should be called every 1000 msec (defined by IP_TMR_INTERVAL). + */ +void +ip_reass_tmr(void) +{ + struct ip_reassdata *r, *prev = NULL; + + r = reassdatagrams; + while (r != NULL) { + /* Decrement the timer. Once it reaches 0, + * clean up the incomplete fragment assembly */ + if (r->timer > 0) { + r->timer--; + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n",(u16_t)r->timer)); + prev = r; + r = r->next; + } else { + /* reassembly timed out */ + struct ip_reassdata *tmp; + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n")); + tmp = r; + /* get the next pointer before freeing */ + r = r->next; + /* free the helper struct and all enqueued pbufs */ + ip_reass_free_complete_datagram(tmp, prev); + } + } +} + +/** + * Free a datagram (struct ip_reassdata) and all its pbufs. + * Updates the total count of enqueued pbufs (ip_reass_pbufcount), + * SNMP counters and sends an ICMP time exceeded packet. + * + * @param ipr datagram to free + * @param prev the previous datagram in the linked list + * @return the number of pbufs freed + */ +static int +ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) +{ + u16_t pbufs_freed = 0; + u8_t clen; + struct pbuf *p; + struct ip_reass_helper *iprh; + + LWIP_ASSERT("prev != ipr", prev != ipr); + if (prev != NULL) { + LWIP_ASSERT("prev->next == ipr", prev->next == ipr); + } + + snmp_inc_ipreasmfails(); +#if LWIP_ICMP + iprh = (struct ip_reass_helper *)ipr->p->payload; + if (iprh->start == 0) { + /* The first fragment was received, send ICMP time exceeded. */ + /* First, de-queue the first pbuf from r->p. */ + p = ipr->p; + ipr->p = iprh->next_pbuf; + /* Then, copy the original header into it. */ + SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN); + icmp_time_exceeded(p, ICMP_TE_FRAG); + clen = pbuf_clen(p); + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + pbufs_freed += clen; + pbuf_free(p); + } +#endif /* LWIP_ICMP */ + + /* First, free all received pbufs. The individual pbufs need to be released + separately as they have not yet been chained */ + p = ipr->p; + while (p != NULL) { + struct pbuf *pcur; + iprh = (struct ip_reass_helper *)p->payload; + pcur = p; + /* get the next pointer before freeing */ + p = iprh->next_pbuf; + clen = pbuf_clen(pcur); + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + pbufs_freed += clen; + pbuf_free(pcur); + } + /* Then, unchain the struct ip_reassdata from the list and free it. */ + ip_reass_dequeue_datagram(ipr, prev); + LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= pbufs_freed); + ip_reass_pbufcount -= pbufs_freed; + + return pbufs_freed; +} + +#if IP_REASS_FREE_OLDEST +/** + * Free the oldest datagram to make room for enqueueing new fragments. + * The datagram 'fraghdr' belongs to is not freed! + * + * @param fraghdr IP header of the current fragment + * @param pbufs_needed number of pbufs needed to enqueue + * (used for freeing other datagrams if not enough space) + * @return the number of pbufs freed + */ +static int +ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed) +{ + /* @todo Can't we simply remove the last datagram in the + * linked list behind reassdatagrams? + */ + struct ip_reassdata *r, *oldest, *prev; + int pbufs_freed = 0, pbufs_freed_current; + int other_datagrams; + + /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs, + * but don't free the datagram that 'fraghdr' belongs to! */ + do { + oldest = NULL; + prev = NULL; + other_datagrams = 0; + r = reassdatagrams; + while (r != NULL) { + if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) { + /* Not the same datagram as fraghdr */ + other_datagrams++; + if (oldest == NULL) { + oldest = r; + } else if (r->timer <= oldest->timer) { + /* older than the previous oldest */ + oldest = r; + } + } + if (r->next != NULL) { + prev = r; + } + r = r->next; + } + if (oldest != NULL) { + pbufs_freed_current = ip_reass_free_complete_datagram(oldest, prev); + pbufs_freed += pbufs_freed_current; + } + } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1)); + return pbufs_freed; +} +#endif /* IP_REASS_FREE_OLDEST */ + +/** + * Enqueues a new fragment into the fragment queue + * @param fraghdr points to the new fragments IP hdr + * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space) + * @return A pointer to the queue location into which the fragment was enqueued + */ +static struct ip_reassdata* +ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen) +{ + struct ip_reassdata* ipr; + /* No matching previous fragment found, allocate a new reassdata struct */ + ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); + if (ipr == NULL) { +#if IP_REASS_FREE_OLDEST + if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) { + ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); + } + if (ipr == NULL) +#endif /* IP_REASS_FREE_OLDEST */ + { + IPFRAG_STATS_INC(ip_frag.memerr); + LWIP_DEBUGF(IP_REASS_DEBUG,("Failed to alloc reassdata struct\n")); + return NULL; + } + } + memset(ipr, 0, sizeof(struct ip_reassdata)); + ipr->timer = IP_REASS_MAXAGE; + + /* enqueue the new structure to the front of the list */ + ipr->next = reassdatagrams; + reassdatagrams = ipr; + /* copy the ip header for later tests and input */ + /* @todo: no ip options supported? */ + SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN); + return ipr; +} + +/** + * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs. + * @param ipr points to the queue entry to dequeue + */ +static void +ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) +{ + + /* dequeue the reass struct */ + if (reassdatagrams == ipr) { + /* it was the first in the list */ + reassdatagrams = ipr->next; + } else { + /* it wasn't the first, so it must have a valid 'prev' */ + LWIP_ASSERT("sanity check linked list", prev != NULL); + prev->next = ipr->next; + } + + /* now we can free the ip_reass struct */ + memp_free(MEMP_REASSDATA, ipr); +} + +/** + * Chain a new pbuf into the pbuf list that composes the datagram. The pbuf list + * will grow over time as new pbufs are rx. + * Also checks that the datagram passes basic continuity checks (if the last + * fragment was received at least once). + * @param root_p points to the 'root' pbuf for the current datagram being assembled. + * @param new_p points to the pbuf for the current fragment + * @return 0 if invalid, >0 otherwise + */ +static int +ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p) +{ + struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev=NULL; + struct pbuf *q; + u16_t offset,len; + struct ip_hdr *fraghdr; + int valid = 1; + + /* Extract length and fragment offset from current fragment */ + fraghdr = (struct ip_hdr*)new_p->payload; + len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4; + offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8; + + /* overwrite the fragment's ip header from the pbuf with our helper struct, + * and setup the embedded helper structure. */ + /* make sure the struct ip_reass_helper fits into the IP header */ + LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN", + sizeof(struct ip_reass_helper) <= IP_HLEN); + iprh = (struct ip_reass_helper*)new_p->payload; + iprh->next_pbuf = NULL; + iprh->start = offset; + iprh->end = offset + len; + + /* Iterate through until we either get to the end of the list (append), + * or we find on with a larger offset (insert). */ + for (q = ipr->p; q != NULL;) { + iprh_tmp = (struct ip_reass_helper*)q->payload; + if (iprh->start < iprh_tmp->start) { + /* the new pbuf should be inserted before this */ + iprh->next_pbuf = q; + if (iprh_prev != NULL) { + /* not the fragment with the lowest offset */ +#if IP_REASS_CHECK_OVERLAP + if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) { + /* fragment overlaps with previous or following, throw away */ + goto freepbuf; + } +#endif /* IP_REASS_CHECK_OVERLAP */ + iprh_prev->next_pbuf = new_p; + } else { + /* fragment with the lowest offset */ + ipr->p = new_p; + } + break; + } else if(iprh->start == iprh_tmp->start) { + /* received the same datagram twice: no need to keep the datagram */ + goto freepbuf; +#if IP_REASS_CHECK_OVERLAP + } else if(iprh->start < iprh_tmp->end) { + /* overlap: no need to keep the new datagram */ + goto freepbuf; +#endif /* IP_REASS_CHECK_OVERLAP */ + } else { + /* Check if the fragments received so far have no wholes. */ + if (iprh_prev != NULL) { + if (iprh_prev->end != iprh_tmp->start) { + /* There is a fragment missing between the current + * and the previous fragment */ + valid = 0; + } + } + } + q = iprh_tmp->next_pbuf; + iprh_prev = iprh_tmp; + } + + /* If q is NULL, then we made it to the end of the list. Determine what to do now */ + if (q == NULL) { + if (iprh_prev != NULL) { + /* this is (for now), the fragment with the highest offset: + * chain it to the last fragment */ +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start); +#endif /* IP_REASS_CHECK_OVERLAP */ + iprh_prev->next_pbuf = new_p; + if (iprh_prev->end != iprh->start) { + valid = 0; + } + } else { +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("no previous fragment, this must be the first fragment!", + ipr->p == NULL); +#endif /* IP_REASS_CHECK_OVERLAP */ + /* this is the first fragment we ever received for this ip datagram */ + ipr->p = new_p; + } + } + + /* At this point, the validation part begins: */ + /* If we already received the last fragment */ + if ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0) { + /* and had no wholes so far */ + if (valid) { + /* then check if the rest of the fragments is here */ + /* Check if the queue starts with the first datagram */ + if (((struct ip_reass_helper*)ipr->p->payload)->start != 0) { + valid = 0; + } else { + /* and check that there are no wholes after this datagram */ + iprh_prev = iprh; + q = iprh->next_pbuf; + while (q != NULL) { + iprh = (struct ip_reass_helper*)q->payload; + if (iprh_prev->end != iprh->start) { + valid = 0; + break; + } + iprh_prev = iprh; + q = iprh->next_pbuf; + } + /* if still valid, all fragments are received + * (because to the MF==0 already arrived */ + if (valid) { + LWIP_ASSERT("sanity check", ipr->p != NULL); + LWIP_ASSERT("sanity check", + ((struct ip_reass_helper*)ipr->p->payload) != iprh); + LWIP_ASSERT("validate_datagram:next_pbuf!=NULL", + iprh->next_pbuf == NULL); + LWIP_ASSERT("validate_datagram:datagram end!=datagram len", + iprh->end == ipr->datagram_len); + } + } + } + /* If valid is 0 here, there are some fragments missing in the middle + * (since MF == 0 has already arrived). Such datagrams simply time out if + * no more fragments are received... */ + return valid; + } + /* If we come here, not all fragments were received, yet! */ + return 0; /* not yet valid! */ +#if IP_REASS_CHECK_OVERLAP +freepbuf: + ip_reass_pbufcount -= pbuf_clen(new_p); + pbuf_free(new_p); + return 0; +#endif /* IP_REASS_CHECK_OVERLAP */ +} + +/** + * Reassembles incoming IP fragments into an IP datagram. + * + * @param p points to a pbuf chain of the fragment + * @return NULL if reassembly is incomplete, ? otherwise + */ +struct pbuf * +ip_reass(struct pbuf *p) +{ + struct pbuf *r; + struct ip_hdr *fraghdr; + struct ip_reassdata *ipr; + struct ip_reass_helper *iprh; + u16_t offset, len; + u8_t clen; + struct ip_reassdata *ipr_prev = NULL; + + IPFRAG_STATS_INC(ip_frag.recv); + snmp_inc_ipreasmreqds(); + + fraghdr = (struct ip_hdr*)p->payload; + + if ((IPH_HL(fraghdr) * 4) != IP_HLEN) { + LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: IP options currently not supported!\n")); + IPFRAG_STATS_INC(ip_frag.err); + goto nullreturn; + } + + offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8; + len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4; + + /* Check if we are allowed to enqueue more datagrams. */ + clen = pbuf_clen(p); + if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) { +#if IP_REASS_FREE_OLDEST + if (!ip_reass_remove_oldest_datagram(fraghdr, clen) || + ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS)) +#endif /* IP_REASS_FREE_OLDEST */ + { + /* No datagram could be freed and still too many pbufs enqueued */ + LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: Overflow condition: pbufct=%d, clen=%d, MAX=%d\n", + ip_reass_pbufcount, clen, IP_REASS_MAX_PBUFS)); + IPFRAG_STATS_INC(ip_frag.memerr); + /* @todo: send ICMP time exceeded here? */ + /* drop this pbuf */ + goto nullreturn; + } + } + + /* Look for the datagram the fragment belongs to in the current datagram queue, + * remembering the previous in the queue for later dequeueing. */ + for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) { + /* Check if the incoming fragment matches the one currently present + in the reassembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n", + ntohs(IPH_ID(fraghdr)))); + IPFRAG_STATS_INC(ip_frag.cachehit); + break; + } + ipr_prev = ipr; + } + + if (ipr == NULL) { + /* Enqueue a new datagram into the datagram queue */ + ipr = ip_reass_enqueue_new_datagram(fraghdr, clen); + /* Bail if unable to enqueue */ + if(ipr == NULL) { + goto nullreturn; + } + } else { + if (((ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && + ((ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) { + /* ipr->iphdr is not the header from the first fragment, but fraghdr is + * -> copy fraghdr into ipr->iphdr since we want to have the header + * of the first fragment (for ICMP time exceeded and later, for copying + * all options, if supported)*/ + SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN); + } + } + /* Track the current number of pbufs current 'in-flight', in order to limit + the number of fragments that may be enqueued at any one time */ + ip_reass_pbufcount += clen; + + /* At this point, we have either created a new entry or pointing + * to an existing one */ + + /* check for 'no more fragments', and update queue entry*/ + if ((IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0) { + ipr->flags |= IP_REASS_FLAG_LASTFRAG; + ipr->datagram_len = offset + len; + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: last fragment seen, total len %"S16_F"\n", + ipr->datagram_len)); + } + /* find the right place to insert this pbuf */ + /* @todo: trim pbufs if fragments are overlapping */ + if (ip_reass_chain_frag_into_datagram_and_validate(ipr, p)) { + /* the totally last fragment (flag more fragments = 0) was received at least + * once AND all fragments are received */ + ipr->datagram_len += IP_HLEN; + + /* save the second pbuf before copying the header over the pointer */ + r = ((struct ip_reass_helper*)ipr->p->payload)->next_pbuf; + + /* copy the original ip header back to the first pbuf */ + fraghdr = (struct ip_hdr*)(ipr->p->payload); + SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN); + IPH_LEN_SET(fraghdr, htons(ipr->datagram_len)); + IPH_OFFSET_SET(fraghdr, 0); + IPH_CHKSUM_SET(fraghdr, 0); + /* @todo: do we need to set calculate the correct checksum? */ + IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN)); + + p = ipr->p; + + /* chain together the pbufs contained within the reass_data list. */ + while(r != NULL) { + iprh = (struct ip_reass_helper*)r->payload; + + /* hide the ip header for every succeding fragment */ + pbuf_header(r, -IP_HLEN); + pbuf_cat(p, r); + r = iprh->next_pbuf; + } + /* release the sources allocate for the fragment queue entry */ + ip_reass_dequeue_datagram(ipr, ipr_prev); + + /* and adjust the number of pbufs currently queued for reassembly. */ + ip_reass_pbufcount -= pbuf_clen(p); + + /* Return the pbuf chain */ + return p; + } + /* the datagram is not (yet?) reassembled completely */ + LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount)); + return NULL; + +nullreturn: + LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: nullreturn\n")); + IPFRAG_STATS_INC(ip_frag.drop); + pbuf_free(p); + return NULL; +} +#endif /* IP_REASSEMBLY */ + +#if IP_FRAG +#if IP_FRAG_USES_STATIC_BUF +static u8_t buf[LWIP_MEM_ALIGN_SIZE(IP_FRAG_MAX_MTU + MEM_ALIGNMENT - 1)]; +#else /* IP_FRAG_USES_STATIC_BUF */ + +#if !LWIP_NETIF_TX_SINGLE_PBUF +/** Allocate a new struct pbuf_custom_ref */ +static struct pbuf_custom_ref* +ip_frag_alloc_pbuf_custom_ref(void) +{ + return (struct pbuf_custom_ref*)memp_malloc(MEMP_FRAG_PBUF); +} + +/** Free a struct pbuf_custom_ref */ +static void +ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref* p) +{ + LWIP_ASSERT("p != NULL", p != NULL); + memp_free(MEMP_FRAG_PBUF, p); +} + +/** Free-callback function to free a 'struct pbuf_custom_ref', called by + * pbuf_free. */ +static void +ipfrag_free_pbuf_custom(struct pbuf *p) +{ + struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref*)p; + LWIP_ASSERT("pcr != NULL", pcr != NULL); + LWIP_ASSERT("pcr == p", (void*)pcr == (void*)p); + if (pcr->original != NULL) { + pbuf_free(pcr->original); + } + ip_frag_free_pbuf_custom_ref(pcr); +} +#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ +#endif /* IP_FRAG_USES_STATIC_BUF */ + +/** + * Fragment an IP datagram if too large for the netif. + * + * Chop the datagram in MTU sized chunks and send them in order + * by using a fixed size static memory buffer (PBUF_REF) or + * point PBUF_REFs into p (depending on IP_FRAG_USES_STATIC_BUF). + * + * @param p ip packet to send + * @param netif the netif on which to send + * @param dest destination ip address to which to send + * + * @return ERR_OK if sent successfully, err_t otherwise + */ +err_t +ip_frag(struct pbuf *p, struct netif *netif, ip_addr_t *dest) +{ + struct pbuf *rambuf; +#if IP_FRAG_USES_STATIC_BUF + struct pbuf *header; +#else +#if !LWIP_NETIF_TX_SINGLE_PBUF + struct pbuf *newpbuf; +#endif + struct ip_hdr *original_iphdr; +#endif + struct ip_hdr *iphdr; + u16_t nfb; + u16_t left, cop; + u16_t mtu = netif->mtu; + u16_t ofo, omf; + u16_t last; + u16_t poff = IP_HLEN; + u16_t tmp; +#if !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF + u16_t newpbuflen = 0; + u16_t left_to_copy; +#endif + + /* Get a RAM based MTU sized pbuf */ +#if IP_FRAG_USES_STATIC_BUF + /* When using a static buffer, we use a PBUF_REF, which we will + * use to reference the packet (without link header). + * Layer and length is irrelevant. + */ + rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF); + if (rambuf == NULL) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc(PBUF_LINK, 0, PBUF_REF) failed\n")); + return ERR_MEM; + } + rambuf->tot_len = rambuf->len = mtu; + rambuf->payload = LWIP_MEM_ALIGN((void *)buf); + + /* Copy the IP header in it */ + iphdr = (struct ip_hdr *)rambuf->payload; + SMEMCPY(iphdr, p->payload, IP_HLEN); +#else /* IP_FRAG_USES_STATIC_BUF */ + original_iphdr = (struct ip_hdr *)p->payload; + iphdr = original_iphdr; +#endif /* IP_FRAG_USES_STATIC_BUF */ + + /* Save original offset */ + tmp = ntohs(IPH_OFFSET(iphdr)); + ofo = tmp & IP_OFFMASK; + omf = tmp & IP_MF; + + left = p->tot_len - IP_HLEN; + + nfb = (mtu - IP_HLEN) / 8; + + while (left) { + last = (left <= mtu - IP_HLEN); + + /* Set new offset and MF flag */ + tmp = omf | (IP_OFFMASK & (ofo)); + if (!last) { + tmp = tmp | IP_MF; + } + + /* Fill this fragment */ + cop = last ? left : nfb * 8; + +#if IP_FRAG_USES_STATIC_BUF + poff += pbuf_copy_partial(p, (u8_t*)iphdr + IP_HLEN, cop, poff); +#else /* IP_FRAG_USES_STATIC_BUF */ +#if LWIP_NETIF_TX_SINGLE_PBUF + rambuf = pbuf_alloc(PBUF_IP, cop, PBUF_RAM); + if (rambuf == NULL) { + return ERR_MEM; + } + LWIP_ASSERT("this needs a pbuf in one piece!", + (rambuf->len == rambuf->tot_len) && (rambuf->next == NULL)); + poff += pbuf_copy_partial(p, rambuf->payload, cop, poff); + /* make room for the IP header */ + if(pbuf_header(rambuf, IP_HLEN)) { + pbuf_free(rambuf); + return ERR_MEM; + } + /* fill in the IP header */ + SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN); + iphdr = rambuf->payload; +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + /* When not using a static buffer, create a chain of pbufs. + * The first will be a PBUF_RAM holding the link and IP header. + * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged, + * but limited to the size of an mtu. + */ + rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM); + if (rambuf == NULL) { + return ERR_MEM; + } + LWIP_ASSERT("this needs a pbuf in one piece!", + (p->len >= (IP_HLEN))); + SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN); + iphdr = (struct ip_hdr *)rambuf->payload; + + /* Can just adjust p directly for needed offset. */ + p->payload = (u8_t *)p->payload + poff; + p->len -= poff; + + left_to_copy = cop; + while (left_to_copy) { + struct pbuf_custom_ref *pcr; + newpbuflen = (left_to_copy < p->len) ? left_to_copy : p->len; + /* Is this pbuf already empty? */ + if (!newpbuflen) { + p = p->next; + continue; + } + pcr = ip_frag_alloc_pbuf_custom_ref(); + if (pcr == NULL) { + pbuf_free(rambuf); + return ERR_MEM; + } + /* Mirror this pbuf, although we might not need all of it. */ + newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, p->payload, newpbuflen); + if (newpbuf == NULL) { + ip_frag_free_pbuf_custom_ref(pcr); + pbuf_free(rambuf); + return ERR_MEM; + } + pbuf_ref(p); + pcr->original = p; + pcr->pc.custom_free_function = ipfrag_free_pbuf_custom; + + /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain + * so that it is removed when pbuf_dechain is later called on rambuf. + */ + pbuf_cat(rambuf, newpbuf); + left_to_copy -= newpbuflen; + if (left_to_copy) { + p = p->next; + } + } + poff = newpbuflen; +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ +#endif /* IP_FRAG_USES_STATIC_BUF */ + + /* Correct header */ + IPH_OFFSET_SET(iphdr, htons(tmp)); + IPH_LEN_SET(iphdr, htons(cop + IP_HLEN)); + IPH_CHKSUM_SET(iphdr, 0); + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); + +#if IP_FRAG_USES_STATIC_BUF + if (last) { + pbuf_realloc(rambuf, left + IP_HLEN); + } + + /* This part is ugly: we alloc a RAM based pbuf for + * the link level header for each chunk and then + * free it.A PBUF_ROM style pbuf for which pbuf_header + * worked would make things simpler. + */ + header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM); + if (header != NULL) { + pbuf_chain(header, rambuf); + netif->output(netif, header, dest); + IPFRAG_STATS_INC(ip_frag.xmit); + snmp_inc_ipfragcreates(); + pbuf_free(header); + } else { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc() for header failed\n")); + pbuf_free(rambuf); + return ERR_MEM; + } +#else /* IP_FRAG_USES_STATIC_BUF */ + /* No need for separate header pbuf - we allowed room for it in rambuf + * when allocated. + */ + netif->output(netif, rambuf, dest); + IPFRAG_STATS_INC(ip_frag.xmit); + + /* Unfortunately we can't reuse rambuf - the hardware may still be + * using the buffer. Instead we free it (and the ensuing chain) and + * recreate it next time round the loop. If we're lucky the hardware + * will have already sent the packet, the free will really free, and + * there will be zero memory penalty. + */ + + pbuf_free(rambuf); +#endif /* IP_FRAG_USES_STATIC_BUF */ + left -= cop; + ofo += nfb; + } +#if IP_FRAG_USES_STATIC_BUF + pbuf_free(rambuf); +#endif /* IP_FRAG_USES_STATIC_BUF */ + snmp_inc_ipfragoks(); + return ERR_OK; +} +#endif /* IP_FRAG */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/README b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/README new file mode 100644 index 0000000..3620004 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/README @@ -0,0 +1 @@ +IPv6 support in lwIP is very experimental. diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/icmp6.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/icmp6.c new file mode 100644 index 0000000..4fcc895 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/icmp6.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* Some ICMP messages should be passed to the transport protocols. This + is not implemented. */ + +#include "lwip/opt.h" + +#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/icmp.h" +#include "lwip/inet.h" +#include "lwip/ip.h" +#include "lwip/def.h" +#include "lwip/stats.h" + +void +icmp_input(struct pbuf *p, struct netif *inp) +{ + u8_t type; + struct icmp_echo_hdr *iecho; + struct ip_hdr *iphdr; + struct ip_addr tmpaddr; + + ICMP_STATS_INC(icmp.recv); + + /* TODO: check length before accessing payload! */ + + type = ((u8_t *)p->payload)[0]; + + switch (type) { + case ICMP6_ECHO: + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); + + if (p->tot_len < sizeof(struct icmp_echo_hdr)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); + + pbuf_free(p); + ICMP_STATS_INC(icmp.lenerr); + return; + } + iecho = p->payload; + iphdr = (struct ip_hdr *)((u8_t *)p->payload - IP_HLEN); + if (inet_chksum_pbuf(p) != 0) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len))); + ICMP_STATS_INC(icmp.chkerr); + /* return;*/ + } + LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %"S16_F" p->tot_len %"S16_F"\n", p->len, p->tot_len)); + ip_addr_set(&tmpaddr, &(iphdr->src)); + ip_addr_set(&(iphdr->src), &(iphdr->dest)); + ip_addr_set(&(iphdr->dest), &tmpaddr); + iecho->type = ICMP6_ER; + /* adjust the checksum */ + if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) { + iecho->chksum += htons(ICMP6_ECHO << 8) + 1; + } else { + iecho->chksum += htons(ICMP6_ECHO << 8); + } + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len))); + ICMP_STATS_INC(icmp.xmit); + + /* LWIP_DEBUGF("icmp: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/ + ip_output_if (p, &(iphdr->src), IP_HDRINCL, + iphdr->hoplim, IP_PROTO_ICMP, inp); + break; + default: + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" not supported.\n", (s16_t)type)); + ICMP_STATS_INC(icmp.proterr); + ICMP_STATS_INC(icmp.drop); + } + + pbuf_free(p); +} + +void +icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) +{ + struct pbuf *q; + struct ip_hdr *iphdr; + struct icmp_dur_hdr *idur; + + /* @todo: can this be PBUF_LINK instead of PBUF_IP? */ + q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); + /* ICMP header + IP header + 8 bytes of data */ + if (q == NULL) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n")); + pbuf_free(p); + return; + } + LWIP_ASSERT("check that first pbuf can hold icmp message", + (q->len >= (8 + IP_HLEN + 8))); + + iphdr = p->payload; + + idur = q->payload; + idur->type = (u8_t)ICMP6_DUR; + idur->icode = (u8_t)t; + + SMEMCPY((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8); + + /* calculate checksum */ + idur->chksum = 0; + idur->chksum = inet_chksum(idur, q->len); + ICMP_STATS_INC(icmp.xmit); + + ip_output(q, NULL, + (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP); + pbuf_free(q); +} + +void +icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) +{ + struct pbuf *q; + struct ip_hdr *iphdr; + struct icmp_te_hdr *tehdr; + + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n")); + + /* @todo: can this be PBUF_LINK instead of PBUF_IP? */ + q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); + /* ICMP header + IP header + 8 bytes of data */ + if (q == NULL) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n")); + pbuf_free(p); + return; + } + LWIP_ASSERT("check that first pbuf can hold icmp message", + (q->len >= (8 + IP_HLEN + 8))); + + iphdr = p->payload; + + tehdr = q->payload; + tehdr->type = (u8_t)ICMP6_TE; + tehdr->icode = (u8_t)t; + + /* copy fields from original packet */ + SMEMCPY((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8); + + /* calculate checksum */ + tehdr->chksum = 0; + tehdr->chksum = inet_chksum(tehdr, q->len); + ICMP_STATS_INC(icmp.xmit); + ip_output(q, NULL, + (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP); + pbuf_free(q); +} + +#endif /* LWIP_ICMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/inet6.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/inet6.c new file mode 100644 index 0000000..c3de85c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/inet6.c @@ -0,0 +1,163 @@ +/** + * @file + * Functions common to all TCP/IPv6 modules, such as the Internet checksum and the + * byte order functions. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/inet.h" + +/* chksum: + * + * Sums up all 16 bit words in a memory portion. Also includes any odd byte. + * This function is used by the other checksum functions. + * + * For now, this is not optimized. Must be optimized for the particular processor + * arcitecture on which it is to run. Preferebly coded in assembler. + */ + +static u32_t +chksum(void *dataptr, u16_t len) +{ + u16_t *sdataptr = dataptr; + u32_t acc; + + + for(acc = 0; len > 1; len -= 2) { + acc += *sdataptr++; + } + + /* add up any odd byte */ + if (len == 1) { + acc += htons((u16_t)(*(u8_t *)dataptr) << 8); + } + + return acc; + +} + +/* inet_chksum_pseudo: + * + * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. + */ + +u16_t +inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u32_t proto_len) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped, i; + + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { + acc += chksum(q->payload, q->len); + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); + } + } + + if (swapped) { + acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); + } + + for(i = 0; i < 8; i++) { + acc += ((u16_t *)src->addr)[i] & 0xffff; + acc += ((u16_t *)dest->addr)[i] & 0xffff; + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + } + acc += (u16_t)htons((u16_t)proto); + acc += ((u16_t *)&proto_len)[0] & 0xffff; + acc += ((u16_t *)&proto_len)[1] & 0xffff; + + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + return ~(acc & 0xffff); +} + +/* inet_chksum: + * + * Calculates the Internet checksum over a portion of memory. Used primarely for IP + * and ICMP. + */ + +u16_t +inet_chksum(void *dataptr, u16_t len) +{ + u32_t acc, sum; + + acc = chksum(dataptr, len); + sum = (acc & 0xffff) + (acc >> 16); + sum += (sum >> 16); + return ~(sum & 0xffff); +} + +u16_t +inet_chksum_pbuf(struct pbuf *p) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped; + + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { + acc += chksum(q->payload, q->len); + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8); + } + } + + if (swapped) { + acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); + } + return ~(acc & 0xffff); +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6.c new file mode 100644 index 0000000..b945fc5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6.c @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + + +/* ip.c + * + * This is the code for the IP layer for IPv6. + * + */ + + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/ip.h" +#include "lwip/inet.h" +#include "lwip/netif.h" +#include "lwip/icmp.h" +#include "lwip/udp.h" +#include "lwip/tcp_impl.h" + +#include "lwip/stats.h" + +#include "arch/perf.h" + +/* ip_init: + * + * Initializes the IP layer. + */ + +void +ip_init(void) +{ +} + +/* ip_route: + * + * Finds the appropriate network interface for a given IP address. It searches the + * list of network interfaces linearly. A match is found if the masked IP address of + * the network interface equals the masked IP address given to the function. + */ + +struct netif * +ip_route(struct ip_addr *dest) +{ + struct netif *netif; + + for(netif = netif_list; netif != NULL; netif = netif->next) { + if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { + return netif; + } + } + + return netif_default; +} + +/* ip_forward: + * + * Forwards an IP packet. It finds an appropriate route for the packet, decrements + * the TTL value of the packet, adjusts the checksum and outputs the packet on the + * appropriate interface. + */ + +static void +ip_forward(struct pbuf *p, struct ip_hdr *iphdr) +{ + struct netif *netif; + + PERF_START; + + if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) { + + LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for ")); +#if IP_DEBUG + ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest))); +#endif /* IP_DEBUG */ + LWIP_DEBUGF(IP_DEBUG, ("\n")); + pbuf_free(p); + return; + } + /* Decrement TTL and send ICMP if ttl == 0. */ + if (--iphdr->hoplim == 0) { +#if LWIP_ICMP + /* Don't send ICMP messages in response to ICMP messages */ + if (iphdr->nexthdr != IP_PROTO_ICMP) { + icmp_time_exceeded(p, ICMP_TE_TTL); + } +#endif /* LWIP_ICMP */ + pbuf_free(p); + return; + } + + /* Incremental update of the IP checksum. */ + /* if (iphdr->chksum >= htons(0xffff - 0x100)) { + iphdr->chksum += htons(0x100) + 1; + } else { + iphdr->chksum += htons(0x100); + }*/ + + + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to ")); +#if IP_DEBUG + ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest))); +#endif /* IP_DEBUG */ + LWIP_DEBUGF(IP_DEBUG, ("\n")); + + IP_STATS_INC(ip.fw); + IP_STATS_INC(ip.xmit); + + PERF_STOP("ip_forward"); + + netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); +} + +/* ip_input: + * + * This function is called by the network interface device driver when an IP packet is + * received. The function does the basic checks of the IP header such as packet size + * being at least larger than the header size etc. If the packet was not destined for + * us, the packet is forwarded (using ip_forward). The IP checksum is always checked. + * + * Finally, the packet is sent to the upper layer protocol input function. + */ + +void +ip_input(struct pbuf *p, struct netif *inp) { + struct ip_hdr *iphdr; + struct netif *netif; + + + PERF_START; + +#if IP_DEBUG + ip_debug_print(p); +#endif /* IP_DEBUG */ + + + IP_STATS_INC(ip.recv); + + /* identify the IP header */ + iphdr = p->payload; + + + if (iphdr->v != 6) { + LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n")); +#if IP_DEBUG + ip_debug_print(p); +#endif /* IP_DEBUG */ + pbuf_free(p); + IP_STATS_INC(ip.err); + IP_STATS_INC(ip.drop); + return; + } + + /* is this packet for us? */ + for(netif = netif_list; netif != NULL; netif = netif->next) { +#if IP_DEBUG + LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest ")); + ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest))); + LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr ")); + ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest))); + LWIP_DEBUGF(IP_DEBUG, ("\n")); +#endif /* IP_DEBUG */ + if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) { + break; + } + } + + + if (netif == NULL) { + /* packet not for us, route or discard */ +#if IP_FORWARD + ip_forward(p, iphdr); +#endif + pbuf_free(p); + return; + } + + pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len)); + + /* send to upper layers */ +#if IP_DEBUG + /* LWIP_DEBUGF("ip_input: \n"); + ip_debug_print(p); + LWIP_DEBUGF("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/ +#endif /* IP_DEBUG */ + + if(pbuf_header(p, -IP_HLEN)) { + LWIP_ASSERT("Can't move over header in packet", 0); + return; + } + + switch (iphdr->nexthdr) { + case IP_PROTO_UDP: + udp_input(p, inp); + break; + case IP_PROTO_TCP: + tcp_input(p, inp); + break; +#if LWIP_ICMP + case IP_PROTO_ICMP: + icmp_input(p, inp); + break; +#endif /* LWIP_ICMP */ + default: +#if LWIP_ICMP + /* send ICMP destination protocol unreachable */ + icmp_dest_unreach(p, ICMP_DUR_PROTO); +#endif /* LWIP_ICMP */ + pbuf_free(p); + LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %"U16_F"\n", + iphdr->nexthdr)); + + IP_STATS_INC(ip.proterr); + IP_STATS_INC(ip.drop); + } + PERF_STOP("ip_input"); +} + + +/* ip_output_if: + * + * Sends an IP packet on a network interface. This function constructs the IP header + * and calculates the IP header checksum. If the source IP address is NULL, + * the IP address of the outgoing network interface is filled in as source address. + */ + +err_t +ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, + u8_t proto, struct netif *netif) +{ + struct ip_hdr *iphdr; + + PERF_START; + + LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len)); + if (pbuf_header(p, IP_HLEN)) { + LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n")); + IP_STATS_INC(ip.err); + + return ERR_BUF; + } + LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len)); + + iphdr = p->payload; + + + if (dest != IP_HDRINCL) { + LWIP_DEBUGF(IP_DEBUG, ("!IP_HDRLINCL\n")); + iphdr->hoplim = ttl; + iphdr->nexthdr = proto; + iphdr->len = htons(p->tot_len - IP_HLEN); + ip_addr_set(&(iphdr->dest), dest); + + iphdr->v = 6; + + if (ip_addr_isany(src)) { + ip_addr_set(&(iphdr->src), &(netif->ip_addr)); + } else { + ip_addr_set(&(iphdr->src), src); + } + + } else { + dest = &(iphdr->dest); + } + + IP_STATS_INC(ip.xmit); + + LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %"U16_F")\n", netif->name[0], netif->name[1], p->tot_len)); +#if IP_DEBUG + ip_debug_print(p); +#endif /* IP_DEBUG */ + + PERF_STOP("ip_output_if"); + return netif->output(netif, p, dest); +} + +/* ip_output: + * + * Simple interface to ip_output_if. It finds the outgoing network interface and + * calls upon ip_output_if to do the actual work. + */ + +err_t +ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t proto) +{ + struct netif *netif; + if ((netif = ip_route(dest)) == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); + IP_STATS_INC(ip.rterr); + return ERR_RTE; + } + + return ip_output_if (p, src, dest, ttl, proto, netif); +} + +#if LWIP_NETIF_HWADDRHINT +err_t +ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint) +{ + struct netif *netif; + err_t err; + + if ((netif = ip_route(dest)) == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); + IP_STATS_INC(ip.rterr); + return ERR_RTE; + } + + netif->addr_hint = addr_hint; + err = ip_output_if(p, src, dest, ttl, tos, proto, netif); + netif->addr_hint = NULL; + + return err; +} +#endif /* LWIP_NETIF_HWADDRHINT*/ + +#if IP_DEBUG +void +ip_debug_print(struct pbuf *p) +{ + struct ip_hdr *iphdr = p->payload; + + LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" | %"X16_F"%"X16_F" | %"X16_F"%"X16_F" | (v, traffic class, flow label)\n", + iphdr->v, + iphdr->tclass1, iphdr->tclass2, + iphdr->flow1, iphdr->flow2)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" | %2"U16_F" | %2"U16_F" | (len, nexthdr, hoplim)\n", + ntohs(iphdr->len), + iphdr->nexthdr, + iphdr->hoplim)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", + (ntohl(iphdr->src.addr[0]) >> 16) & 0xffff, + ntohl(iphdr->src.addr[0]) & 0xffff)); + LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", + (ntohl(iphdr->src.addr[1]) >> 16) & 0xffff, + ntohl(iphdr->src.addr[1]) & 0xffff)); + LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", + (ntohl(iphdr->src.addr[2]) >> 16) & 0xffff, + ntohl(iphdr->src.addr[2]) & 0xffff)); + LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", + (ntohl(iphdr->src.addr[3]) >> 16) & 0xffff, + ntohl(iphdr->src.addr[3]) & 0xffff)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", + (ntohl(iphdr->dest.addr[0]) >> 16) & 0xffff, + ntohl(iphdr->dest.addr[0]) & 0xffff)); + LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", + (ntohl(iphdr->dest.addr[1]) >> 16) & 0xffff, + ntohl(iphdr->dest.addr[1]) & 0xffff)); + LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", + (ntohl(iphdr->dest.addr[2]) >> 16) & 0xffff, + ntohl(iphdr->dest.addr[2]) & 0xffff)); + LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", + (ntohl(iphdr->dest.addr[3]) >> 16) & 0xffff, + ntohl(iphdr->dest.addr[3]) & 0xffff)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* IP_DEBUG */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6_addr.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6_addr.c new file mode 100644 index 0000000..2da6cea --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6_addr.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" +#include "lwip/inet.h" + +u8_t +ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2, + struct ip_addr *mask) +{ + return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) && + (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) && + (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) && + (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3])); + +} + +u8_t +ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2) +{ + return(addr1->addr[0] == addr2->addr[0] && + addr1->addr[1] == addr2->addr[1] && + addr1->addr[2] == addr2->addr[2] && + addr1->addr[3] == addr2->addr[3]); +} + +void +ip_addr_set(struct ip_addr *dest, struct ip_addr *src) +{ + SMEMCPY(dest, src, sizeof(struct ip_addr)); + /* dest->addr[0] = src->addr[0]; + dest->addr[1] = src->addr[1]; + dest->addr[2] = src->addr[2]; + dest->addr[3] = src->addr[3];*/ +} + +u8_t +ip_addr_isany(struct ip_addr *addr) +{ + if (addr == NULL) return 1; + return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0); +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/lwip_timers.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/lwip_timers.c new file mode 100644 index 0000000..dfed0bc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/lwip_timers.c @@ -0,0 +1,482 @@ +/** + * @file + * Stack-internal timers implementation. + * This file includes timer callbacks for stack-internal timers as well as + * functions to set up or stop timers and check for expired timers. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * Simon Goldschmidt + * + */ + +#include "lwip/opt.h" + +#include "lwip/timers.h" +#include "lwip/tcp_impl.h" + +#if LWIP_TIMERS + +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/tcpip.h" + +#include "lwip/ip_frag.h" +#include "netif/etharp.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" +#include "lwip/igmp.h" +#include "lwip/dns.h" + + +/** The one and only timeout list */ +static struct sys_timeo *next_timeout; +#if NO_SYS +static u32_t timeouts_last_time; +#endif /* NO_SYS */ + +#if LWIP_TCP +/** global variable that shows if the tcp timer is currently scheduled or not */ +static int tcpip_tcp_timer_active; + +/** + * Timer callback function that calls tcp_tmr() and reschedules itself. + * + * @param arg unused argument + */ +static void +tcpip_tcp_timer(void *arg) +{ + LWIP_UNUSED_ARG(arg); + + /* call TCP timer handler */ + tcp_tmr(); + /* timer still needed? */ + if (tcp_active_pcbs || tcp_tw_pcbs) { + /* restart timer */ + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + } else { + /* disable timer */ + tcpip_tcp_timer_active = 0; + } +} + +/** + * Called from TCP_REG when registering a new PCB: + * the reason is to have the TCP timer only running when + * there are active (or time-wait) PCBs. + */ +void +tcp_timer_needed(void) +{ + /* timer is off but needed again? */ + if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { + /* enable and start timer */ + tcpip_tcp_timer_active = 1; + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + } +} +#endif /* LWIP_TCP */ + +#if IP_REASSEMBLY +/** + * Timer callback function that calls ip_reass_tmr() and reschedules itself. + * + * @param arg unused argument + */ +static void +ip_reass_timer(void *arg) +{ + LWIP_UNUSED_ARG(arg); + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: ip_reass_tmr()\n")); + ip_reass_tmr(); + sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL); +} +#endif /* IP_REASSEMBLY */ + +#if LWIP_ARP +/** + * Timer callback function that calls etharp_tmr() and reschedules itself. + * + * @param arg unused argument + */ +static void +arp_timer(void *arg) +{ + LWIP_UNUSED_ARG(arg); + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: etharp_tmr()\n")); + etharp_tmr(); + sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); +} +#endif /* LWIP_ARP */ + +#if LWIP_DHCP +/** + * Timer callback function that calls dhcp_coarse_tmr() and reschedules itself. + * + * @param arg unused argument + */ +static void +dhcp_timer_coarse(void *arg) +{ + LWIP_UNUSED_ARG(arg); + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: dhcp_coarse_tmr()\n")); + dhcp_coarse_tmr(); + sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL); +} + +/** + * Timer callback function that calls dhcp_fine_tmr() and reschedules itself. + * + * @param arg unused argument + */ +static void +dhcp_timer_fine(void *arg) +{ + LWIP_UNUSED_ARG(arg); + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: dhcp_fine_tmr()\n")); + dhcp_fine_tmr(); + sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL); +} +#endif /* LWIP_DHCP */ + +#if LWIP_AUTOIP +/** + * Timer callback function that calls autoip_tmr() and reschedules itself. + * + * @param arg unused argument + */ +static void +autoip_timer(void *arg) +{ + LWIP_UNUSED_ARG(arg); + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: autoip_tmr()\n")); + autoip_tmr(); + sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL); +} +#endif /* LWIP_AUTOIP */ + +#if LWIP_IGMP +/** + * Timer callback function that calls igmp_tmr() and reschedules itself. + * + * @param arg unused argument + */ +static void +igmp_timer(void *arg) +{ + LWIP_UNUSED_ARG(arg); + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: igmp_tmr()\n")); + igmp_tmr(); + sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL); +} +#endif /* LWIP_IGMP */ + +#if LWIP_DNS +/** + * Timer callback function that calls dns_tmr() and reschedules itself. + * + * @param arg unused argument + */ +static void +dns_timer(void *arg) +{ + LWIP_UNUSED_ARG(arg); + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: dns_tmr()\n")); + dns_tmr(); + sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL); +} +#endif /* LWIP_DNS */ + +/** Initialize this module */ +void sys_timeouts_init(void) +{ +#if IP_REASSEMBLY + sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL); +#endif /* IP_REASSEMBLY */ +#if LWIP_ARP + sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); +#endif /* LWIP_ARP */ +#if LWIP_DHCP + sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL); + sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL); +#endif /* LWIP_DHCP */ +#if LWIP_AUTOIP + sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL); +#endif /* LWIP_AUTOIP */ +#if LWIP_IGMP + sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL); +#endif /* LWIP_IGMP */ +#if LWIP_DNS + sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL); +#endif /* LWIP_DNS */ + +#if NO_SYS + /* Initialise timestamp for sys_check_timeouts */ + timeouts_last_time = sys_now(); +#endif +} + +/** + * Create a one-shot timer (aka timeout). Timeouts are processed in the + * following cases: + * - while waiting for a message using sys_timeouts_mbox_fetch() + * - by calling sys_check_timeouts() (NO_SYS==1 only) + * + * @param msecs time in milliseconds after that the timer should expire + * @param handler callback function to call when msecs have elapsed + * @param arg argument to pass to the callback function + */ +#if LWIP_DEBUG_TIMERNAMES +void +sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name) +#else /* LWIP_DEBUG_TIMERNAMES */ +void +sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg) +#endif /* LWIP_DEBUG_TIMERNAMES */ +{ + struct sys_timeo *timeout, *t; + + timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT); + if (timeout == NULL) { + LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL); + return; + } + timeout->next = NULL; + timeout->h = handler; + timeout->arg = arg; + timeout->time = msecs; +#if LWIP_DEBUG_TIMERNAMES + timeout->handler_name = handler_name; + LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" handler=%s arg=%p\n", + (void *)timeout, msecs, handler_name, (void *)arg)); +#endif /* LWIP_DEBUG_TIMERNAMES */ + + if (next_timeout == NULL) { + next_timeout = timeout; + return; + } + + if (next_timeout->time > msecs) { + next_timeout->time -= msecs; + timeout->next = next_timeout; + next_timeout = timeout; + } else { + for(t = next_timeout; t != NULL; t = t->next) { + timeout->time -= t->time; + if (t->next == NULL || t->next->time > timeout->time) { + if (t->next != NULL) { + t->next->time -= timeout->time; + } + timeout->next = t->next; + t->next = timeout; + break; + } + } + } +} + +/** + * Go through timeout list (for this task only) and remove the first matching + * entry, even though the timeout has not triggered yet. + * + * @note This function only works as expected if there is only one timeout + * calling 'handler' in the list of timeouts. + * + * @param handler callback function that would be called by the timeout + * @param arg callback argument that would be passed to handler +*/ +void +sys_untimeout(sys_timeout_handler handler, void *arg) +{ + struct sys_timeo *prev_t, *t; + + if (next_timeout == NULL) { + return; + } + + for (t = next_timeout, prev_t = NULL; t != NULL; prev_t = t, t = t->next) { + if ((t->h == handler) && (t->arg == arg)) { + /* We have a match */ + /* Unlink from previous in list */ + if (prev_t == NULL) { + next_timeout = t->next; + } else { + prev_t->next = t->next; + } + /* If not the last one, add time of this one back to next */ + if (t->next != NULL) { + t->next->time += t->time; + } + memp_free(MEMP_SYS_TIMEOUT, t); + return; + } + } + return; +} + +#if NO_SYS + +/** Handle timeouts for NO_SYS==1 (i.e. without using + * tcpip_thread/sys_timeouts_mbox_fetch(). Uses sys_now() to call timeout + * handler functions when timeouts expire. + * + * Must be called periodically from your main loop. + */ +void +sys_check_timeouts(void) +{ + struct sys_timeo *tmptimeout; + u32_t diff; + sys_timeout_handler handler; + void *arg; + int had_one; + u32_t now; + + now = sys_now(); + if (next_timeout) { + /* this cares for wraparounds */ + diff = LWIP_U32_DIFF(now, timeouts_last_time); + do + { + had_one = 0; + tmptimeout = next_timeout; + if (tmptimeout->time <= diff) { + /* timeout has expired */ + had_one = 1; + timeouts_last_time = now; + diff -= tmptimeout->time; + next_timeout = tmptimeout->next; + handler = tmptimeout->h; + arg = tmptimeout->arg; +#if LWIP_DEBUG_TIMERNAMES + if (handler != NULL) { + LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s arg=%p\n", + tmptimeout->handler_name, arg)); + } +#endif /* LWIP_DEBUG_TIMERNAMES */ + memp_free(MEMP_SYS_TIMEOUT, tmptimeout); + if (handler != NULL) { + handler(arg); + } + } + /* repeat until all expired timers have been called */ + }while(had_one); + } +} + +/** Set back the timestamp of the last call to sys_check_timeouts() + * This is necessary if sys_check_timeouts() hasn't been called for a long + * time (e.g. while saving energy) to prevent all timer functions of that + * period being called. + */ +void +sys_restart_timeouts(void) +{ + timeouts_last_time = sys_now(); +} + +#else /* NO_SYS */ + +/** + * Wait (forever) for a message to arrive in an mbox. + * While waiting, timeouts are processed. + * + * @param mbox the mbox to fetch the message from + * @param msg the place to store the message + */ +void +sys_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg) +{ + u32_t time_needed; + struct sys_timeo *tmptimeout; + sys_timeout_handler handler; + void *arg; + + again: + if (!next_timeout) { + time_needed = sys_arch_mbox_fetch(mbox, msg, 0); + } else { + if (next_timeout->time > 0) { + time_needed = sys_arch_mbox_fetch(mbox, msg, next_timeout->time); + } else { + time_needed = SYS_ARCH_TIMEOUT; + } + + if (time_needed == SYS_ARCH_TIMEOUT) { + /* If time == SYS_ARCH_TIMEOUT, a timeout occurred before a message + could be fetched. We should now call the timeout handler and + deallocate the memory allocated for the timeout. */ + tmptimeout = next_timeout; + next_timeout = tmptimeout->next; + handler = tmptimeout->h; + arg = tmptimeout->arg; +#if LWIP_DEBUG_TIMERNAMES + if (handler != NULL) { + LWIP_DEBUGF(TIMERS_DEBUG, ("stmf calling h=%s arg=%p\n", + tmptimeout->handler_name, arg)); + } +#endif /* LWIP_DEBUG_TIMERNAMES */ + memp_free(MEMP_SYS_TIMEOUT, tmptimeout); + if (handler != NULL) { + /* For LWIP_TCPIP_CORE_LOCKING, lock the core before calling the + timeout handler function. */ + LOCK_TCPIP_CORE(); + handler(arg); + UNLOCK_TCPIP_CORE(); + } + LWIP_TCPIP_THREAD_ALIVE(); + + /* We try again to fetch a message from the mbox. */ + goto again; + } else { + /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout + occured. The time variable is set to the number of + milliseconds we waited for the message. */ + if (time_needed < next_timeout->time) { + next_timeout->time -= time_needed; + } else { + next_timeout->time = 0; + } + } + } +} + +#endif /* NO_SYS */ + +#else /* LWIP_TIMERS */ +/* Satisfy the TCP code which calls this function */ +void +tcp_timer_needed(void) +{ +} +#endif /* LWIP_TIMERS */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/mem.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/mem.c new file mode 100644 index 0000000..9837555 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/mem.c @@ -0,0 +1,642 @@ +/** + * @file + * Dynamic memory manager + * + * This is a lightweight replacement for the standard C library malloc(). + * + * If you want to use the standard C library malloc() instead, define + * MEM_LIBC_MALLOC to 1 in your lwipopts.h + * + * To let mem_malloc() use pools (prevents fragmentation and is much faster than + * a heap but might waste some memory), define MEM_USE_POOLS to 1, define + * MEM_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list + * of pools like this (more pools can be added between _START and _END): + * + * Define three pools with sizes 256, 512, and 1512 bytes + * LWIP_MALLOC_MEMPOOL_START + * LWIP_MALLOC_MEMPOOL(20, 256) + * LWIP_MALLOC_MEMPOOL(10, 512) + * LWIP_MALLOC_MEMPOOL(5, 1512) + * LWIP_MALLOC_MEMPOOL_END + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * Simon Goldschmidt + * + */ + +#include "lwip/opt.h" + +#if !MEM_LIBC_MALLOC /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/sys.h" +#include "lwip/stats.h" +#include "lwip/err.h" + +#include + +#if MEM_USE_POOLS +/* lwIP head implemented with different sized pools */ + +/** + * Allocate memory: determine the smallest pool that is big enough + * to contain an element of 'size' and get an element from that pool. + * + * @param size the size in bytes of the memory needed + * @return a pointer to the allocated memory or NULL if the pool is empty + */ +void * +mem_malloc(mem_size_t size) +{ + struct memp_malloc_helper *element; + memp_t poolnr; + mem_size_t required_size = size + sizeof(struct memp_malloc_helper); + + for (poolnr = MEMP_POOL_FIRST; poolnr <= MEMP_POOL_LAST; poolnr = (memp_t)(poolnr + 1)) { +#if MEM_USE_POOLS_TRY_BIGGER_POOL +again: +#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */ + /* is this pool big enough to hold an element of the required size + plus a struct memp_malloc_helper that saves the pool this element came from? */ + if (required_size <= memp_sizes[poolnr]) { + break; + } + } + if (poolnr > MEMP_POOL_LAST) { + LWIP_ASSERT("mem_malloc(): no pool is that big!", 0); + return NULL; + } + element = (struct memp_malloc_helper*)memp_malloc(poolnr); + if (element == NULL) { + /* No need to DEBUGF or ASSERT: This error is already + taken care of in memp.c */ +#if MEM_USE_POOLS_TRY_BIGGER_POOL + /** Try a bigger pool if this one is empty! */ + if (poolnr < MEMP_POOL_LAST) { + poolnr++; + goto again; + } +#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */ + return NULL; + } + + /* save the pool number this element came from */ + element->poolnr = poolnr; + /* and return a pointer to the memory directly after the struct memp_malloc_helper */ + element++; + + return element; +} + +/** + * Free memory previously allocated by mem_malloc. Loads the pool number + * and calls memp_free with that pool number to put the element back into + * its pool + * + * @param rmem the memory element to free + */ +void +mem_free(void *rmem) +{ + struct memp_malloc_helper *hmem = (struct memp_malloc_helper*)rmem; + + LWIP_ASSERT("rmem != NULL", (rmem != NULL)); + LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem))); + + /* get the original struct memp_malloc_helper */ + hmem--; + + LWIP_ASSERT("hmem != NULL", (hmem != NULL)); + LWIP_ASSERT("hmem == MEM_ALIGN(hmem)", (hmem == LWIP_MEM_ALIGN(hmem))); + LWIP_ASSERT("hmem->poolnr < MEMP_MAX", (hmem->poolnr < MEMP_MAX)); + + /* and put it in the pool we saved earlier */ + memp_free(hmem->poolnr, hmem); +} + +#else /* MEM_USE_POOLS */ +/* lwIP replacement for your libc malloc() */ + +/** + * The heap is made up as a list of structs of this type. + * This does not have to be aligned since for getting its size, + * we only use the macro SIZEOF_STRUCT_MEM, which automatically alignes. + */ +struct mem { + /** index (-> ram[next]) of the next struct */ + mem_size_t next; + /** index (-> ram[prev]) of the previous struct */ + mem_size_t prev; + /** 1: this area is used; 0: this area is unused */ + u8_t used; +}; + +/** All allocated blocks will be MIN_SIZE bytes big, at least! + * MIN_SIZE can be overridden to suit your needs. Smaller values save space, + * larger values could prevent too small blocks to fragment the RAM too much. */ +#ifndef MIN_SIZE +#define MIN_SIZE 12 +#endif /* MIN_SIZE */ +/* some alignment macros: we define them here for better source code layout */ +#define MIN_SIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(MIN_SIZE) +#define SIZEOF_STRUCT_MEM LWIP_MEM_ALIGN_SIZE(sizeof(struct mem)) +#define MEM_SIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(MEM_SIZE) + +/** If you want to relocate the heap to external memory, simply define + * LWIP_RAM_HEAP_POINTER as a void-pointer to that location. + * If so, make sure the memory at that location is big enough (see below on + * how that space is calculated). */ +#ifndef LWIP_RAM_HEAP_POINTER +/** the heap. we need one struct mem at the end and some room for alignment */ +u8_t ram_heap[MEM_SIZE_ALIGNED + (2*SIZEOF_STRUCT_MEM) + MEM_ALIGNMENT]; +#define LWIP_RAM_HEAP_POINTER ram_heap +#endif /* LWIP_RAM_HEAP_POINTER */ + +/** pointer to the heap (ram_heap): for alignment, ram is now a pointer instead of an array */ +static u8_t *ram; +/** the last entry, always unused! */ +static struct mem *ram_end; +/** pointer to the lowest free block, this is used for faster search */ +static struct mem *lfree; + +/** concurrent access protection */ +static sys_mutex_t mem_mutex; + +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + +static volatile u8_t mem_free_count; + +/* Allow mem_free from other (e.g. interrupt) context */ +#define LWIP_MEM_FREE_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_free) +#define LWIP_MEM_FREE_PROTECT() SYS_ARCH_PROTECT(lev_free) +#define LWIP_MEM_FREE_UNPROTECT() SYS_ARCH_UNPROTECT(lev_free) +#define LWIP_MEM_ALLOC_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_alloc) +#define LWIP_MEM_ALLOC_PROTECT() SYS_ARCH_PROTECT(lev_alloc) +#define LWIP_MEM_ALLOC_UNPROTECT() SYS_ARCH_UNPROTECT(lev_alloc) + +#else /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + +/* Protect the heap only by using a semaphore */ +#define LWIP_MEM_FREE_DECL_PROTECT() +#define LWIP_MEM_FREE_PROTECT() sys_mutex_lock(&mem_mutex) +#define LWIP_MEM_FREE_UNPROTECT() sys_mutex_unlock(&mem_mutex) +/* mem_malloc is protected using semaphore AND LWIP_MEM_ALLOC_PROTECT */ +#define LWIP_MEM_ALLOC_DECL_PROTECT() +#define LWIP_MEM_ALLOC_PROTECT() +#define LWIP_MEM_ALLOC_UNPROTECT() + +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + + +/** + * "Plug holes" by combining adjacent empty struct mems. + * After this function is through, there should not exist + * one empty struct mem pointing to another empty struct mem. + * + * @param mem this points to a struct mem which just has been freed + * @internal this function is only called by mem_free() and mem_trim() + * + * This assumes access to the heap is protected by the calling function + * already. + */ +static void +plug_holes(struct mem *mem) +{ + struct mem *nmem; + struct mem *pmem; + + LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); + LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); + LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); + + /* plug hole forward */ + LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED); + + nmem = (struct mem *)(void *)&ram[mem->next]; + if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { + /* if mem->next is unused and not end of ram, combine mem and mem->next */ + if (lfree == nmem) { + lfree = mem; + } + mem->next = nmem->next; + ((struct mem *)(void *)&ram[nmem->next])->prev = (mem_size_t)((u8_t *)mem - ram); + } + + /* plug hole backward */ + pmem = (struct mem *)(void *)&ram[mem->prev]; + if (pmem != mem && pmem->used == 0) { + /* if mem->prev is unused, combine mem and mem->prev */ + if (lfree == mem) { + lfree = pmem; + } + pmem->next = mem->next; + ((struct mem *)(void *)&ram[mem->next])->prev = (mem_size_t)((u8_t *)pmem - ram); + } +} + +/** + * Zero the heap and initialize start, end and lowest-free + */ +void +mem_init(void) +{ + struct mem *mem; + + LWIP_ASSERT("Sanity check alignment", + (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT-1)) == 0); + + /* align the heap */ + ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER); + /* initialize the start of the heap */ + mem = (struct mem *)(void *)ram; + mem->next = MEM_SIZE_ALIGNED; + mem->prev = 0; + mem->used = 0; + /* initialize the end of the heap */ + ram_end = (struct mem *)(void *)&ram[MEM_SIZE_ALIGNED]; + ram_end->used = 1; + ram_end->next = MEM_SIZE_ALIGNED; + ram_end->prev = MEM_SIZE_ALIGNED; + + /* initialize the lowest-free pointer to the start of the heap */ + lfree = (struct mem *)(void *)ram; + + MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED); + + if(sys_mutex_new(&mem_mutex) != ERR_OK) { + LWIP_ASSERT("failed to create mem_mutex", 0); + } +} + +/** + * Put a struct mem back on the heap + * + * @param rmem is the data portion of a struct mem as returned by a previous + * call to mem_malloc() + */ +void +mem_free(void *rmem) +{ + struct mem *mem; + LWIP_MEM_FREE_DECL_PROTECT(); + + if (rmem == NULL) { + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n")); + return; + } + LWIP_ASSERT("mem_free: sanity check alignment", (((mem_ptr_t)rmem) & (MEM_ALIGNMENT-1)) == 0); + + LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram && + (u8_t *)rmem < (u8_t *)ram_end); + + if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { + SYS_ARCH_DECL_PROTECT(lev); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n")); + /* protect mem stats from concurrent access */ + SYS_ARCH_PROTECT(lev); + MEM_STATS_INC(illegal); + SYS_ARCH_UNPROTECT(lev); + return; + } + /* protect the heap from concurrent access */ + LWIP_MEM_FREE_PROTECT(); + /* Get the corresponding struct mem ... */ + mem = (struct mem *)(void *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); + /* ... which has to be in a used state ... */ + LWIP_ASSERT("mem_free: mem->used", mem->used); + /* ... and is now unused. */ + mem->used = 0; + + if (mem < lfree) { + /* the newly freed struct is now the lowest */ + lfree = mem; + } + + MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram))); + + /* finally, see if prev or next are free also */ + plug_holes(mem); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 1; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_FREE_UNPROTECT(); +} + +/** + * Shrink memory returned by mem_malloc(). + * + * @param rmem pointer to memory allocated by mem_malloc the is to be shrinked + * @param newsize required size after shrinking (needs to be smaller than or + * equal to the previous size) + * @return for compatibility reasons: is always == rmem, at the moment + * or NULL if newsize is > old size, in which case rmem is NOT touched + * or freed! + */ +void * +mem_trim(void *rmem, mem_size_t newsize) +{ + mem_size_t size; + mem_size_t ptr, ptr2; + struct mem *mem, *mem2; + /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */ + LWIP_MEM_FREE_DECL_PROTECT(); + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + newsize = LWIP_MEM_ALIGN_SIZE(newsize); + + if(newsize < MIN_SIZE_ALIGNED) { + /* every data block must be at least MIN_SIZE_ALIGNED long */ + newsize = MIN_SIZE_ALIGNED; + } + + if (newsize > MEM_SIZE_ALIGNED) { + return NULL; + } + + LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram && + (u8_t *)rmem < (u8_t *)ram_end); + + if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { + SYS_ARCH_DECL_PROTECT(lev); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n")); + /* protect mem stats from concurrent access */ + SYS_ARCH_PROTECT(lev); + MEM_STATS_INC(illegal); + SYS_ARCH_UNPROTECT(lev); + return rmem; + } + /* Get the corresponding struct mem ... */ + mem = (struct mem *)(void *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); + /* ... and its offset pointer */ + ptr = (mem_size_t)((u8_t *)mem - ram); + + size = mem->next - ptr - SIZEOF_STRUCT_MEM; + LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size); + if (newsize > size) { + /* not supported */ + return NULL; + } + if (newsize == size) { + /* No change in size, simply return */ + return rmem; + } + + /* protect the heap from concurrent access */ + LWIP_MEM_FREE_PROTECT(); + + mem2 = (struct mem *)(void *)&ram[mem->next]; + if(mem2->used == 0) { + /* The next struct is unused, we can simply move it at little */ + mem_size_t next; + /* remember the old next pointer */ + next = mem2->next; + /* create new struct mem which is moved directly after the shrinked mem */ + ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; + if (lfree == mem2) { + lfree = (struct mem *)(void *)&ram[ptr2]; + } + mem2 = (struct mem *)(void *)&ram[ptr2]; + mem2->used = 0; + /* restore the next pointer */ + mem2->next = next; + /* link it back to mem */ + mem2->prev = ptr; + /* link mem to it */ + mem->next = ptr2; + /* last thing to restore linked list: as we have moved mem2, + * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not + * the end of the heap */ + if (mem2->next != MEM_SIZE_ALIGNED) { + ((struct mem *)(void *)&ram[mem2->next])->prev = ptr2; + } + MEM_STATS_DEC_USED(used, (size - newsize)); + /* no need to plug holes, we've already done that */ + } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) { + /* Next struct is used but there's room for another struct mem with + * at least MIN_SIZE_ALIGNED of data. + * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem + * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED'). + * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty + * region that couldn't hold data, but when mem->next gets freed, + * the 2 regions would be combined, resulting in more free memory */ + ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; + mem2 = (struct mem *)(void *)&ram[ptr2]; + if (mem2 < lfree) { + lfree = mem2; + } + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; + mem->next = ptr2; + if (mem2->next != MEM_SIZE_ALIGNED) { + ((struct mem *)(void *)&ram[mem2->next])->prev = ptr2; + } + MEM_STATS_DEC_USED(used, (size - newsize)); + /* the original mem->next is used, so no need to plug holes! */ + } + /* else { + next struct mem is used but size between mem and mem2 is not big enough + to create another struct mem + -> don't do anyhting. + -> the remaining space stays unused since it is too small + } */ +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 1; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_FREE_UNPROTECT(); + return rmem; +} + +/** + * Adam's mem_malloc() plus solution for bug #17922 + * Allocate a block of memory with a minimum of 'size' bytes. + * + * @param size is the minimum size of the requested block in bytes. + * @return pointer to allocated memory or NULL if no free memory was found. + * + * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT). + */ +void * +mem_malloc(mem_size_t size) +{ + mem_size_t ptr, ptr2; + struct mem *mem, *mem2; +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + u8_t local_mem_free_count = 0; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_ALLOC_DECL_PROTECT(); + + if (size == 0) { + return NULL; + } + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + size = LWIP_MEM_ALIGN_SIZE(size); + + if(size < MIN_SIZE_ALIGNED) { + /* every data block must be at least MIN_SIZE_ALIGNED long */ + size = MIN_SIZE_ALIGNED; + } + + if (size > MEM_SIZE_ALIGNED) { + return NULL; + } + + /* protect the heap from concurrent access */ + sys_mutex_lock(&mem_mutex); + LWIP_MEM_ALLOC_PROTECT(); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + /* run as long as a mem_free disturbed mem_malloc */ + do { + local_mem_free_count = 0; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + + /* Scan through the heap searching for a free block that is big enough, + * beginning with the lowest free block. + */ + for (ptr = (mem_size_t)((u8_t *)lfree - ram); ptr < MEM_SIZE_ALIGNED - size; + ptr = ((struct mem *)(void *)&ram[ptr])->next) { + mem = (struct mem *)(void *)&ram[ptr]; +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 0; + LWIP_MEM_ALLOC_UNPROTECT(); + /* allow mem_free to run */ + LWIP_MEM_ALLOC_PROTECT(); + if (mem_free_count != 0) { + local_mem_free_count = mem_free_count; + } + mem_free_count = 0; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + + if ((!mem->used) && + (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) { + /* mem is not used and at least perfect fit is possible: + * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */ + + if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) { + /* (in addition to the above, we test if another struct mem (SIZEOF_STRUCT_MEM) containing + * at least MIN_SIZE_ALIGNED of data also fits in the 'user data space' of 'mem') + * -> split large block, create empty remainder, + * remainder must be large enough to contain MIN_SIZE_ALIGNED data: if + * mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) == size, + * struct mem would fit in but no data between mem2 and mem2->next + * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty + * region that couldn't hold data, but when mem->next gets freed, + * the 2 regions would be combined, resulting in more free memory + */ + ptr2 = ptr + SIZEOF_STRUCT_MEM + size; + /* create mem2 struct */ + mem2 = (struct mem *)(void *)&ram[ptr2]; + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; + /* and insert it between mem and mem->next */ + mem->next = ptr2; + mem->used = 1; + + if (mem2->next != MEM_SIZE_ALIGNED) { + ((struct mem *)(void *)&ram[mem2->next])->prev = ptr2; + } + MEM_STATS_INC_USED(used, (size + SIZEOF_STRUCT_MEM)); + } else { + /* (a mem2 struct does no fit into the user data space of mem and mem->next will always + * be used at this point: if not we have 2 unused structs in a row, plug_holes should have + * take care of this). + * -> near fit or excact fit: do not split, no mem2 creation + * also can't move mem->next directly behind mem, since mem->next + * will always be used at this point! + */ + mem->used = 1; + MEM_STATS_INC_USED(used, mem->next - (mem_size_t)((u8_t *)mem - ram)); + } + + if (mem == lfree) { + /* Find next free block after mem and update lowest free pointer */ + while (lfree->used && lfree != ram_end) { + LWIP_MEM_ALLOC_UNPROTECT(); + /* prevent high interrupt latency... */ + LWIP_MEM_ALLOC_PROTECT(); + lfree = (struct mem *)(void *)&ram[lfree->next]; + } + LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used))); + } + LWIP_MEM_ALLOC_UNPROTECT(); + sys_mutex_unlock(&mem_mutex); + LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", + (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); + LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", + ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); + LWIP_ASSERT("mem_malloc: sanity check alignment", + (((mem_ptr_t)mem) & (MEM_ALIGNMENT-1)) == 0); + + return (u8_t *)mem + SIZEOF_STRUCT_MEM; + } + } +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + /* if we got interrupted by a mem_free, try again */ + } while(local_mem_free_count != 0); +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); + MEM_STATS_INC(err); + LWIP_MEM_ALLOC_UNPROTECT(); + sys_mutex_unlock(&mem_mutex); + return NULL; +} + +#endif /* MEM_USE_POOLS */ +/** + * Contiguously allocates enough space for count objects that are size bytes + * of memory each and returns a pointer to the allocated memory. + * + * The allocated memory is filled with bytes of value zero. + * + * @param count number of objects to allocate + * @param size size of the objects to allocate + * @return pointer to allocated memory / NULL pointer if there is an error + */ +void *mem_calloc(mem_size_t count, mem_size_t size) +{ + void *p; + + /* allocate 'count' objects of size 'size' */ + p = mem_malloc(count * size); + if (p) { + /* zero the memory */ + memset(p, 0, count * size); + } + return p; +} + +#endif /* !MEM_LIBC_MALLOC */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/memp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/memp.c new file mode 100644 index 0000000..4da879a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/memp.c @@ -0,0 +1,469 @@ +/** + * @file + * Dynamic pool memory manager + * + * lwIP has dedicated pools for many structures (netconn, protocol control blocks, + * packet buffers, ...). All these pools are managed here. + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/udp.h" +#include "lwip/raw.h" +#include "lwip/tcp_impl.h" +#include "lwip/igmp.h" +#include "lwip/api.h" +#include "lwip/api_msg.h" +#include "lwip/tcpip.h" +#include "lwip/sys.h" +#include "lwip/timers.h" +#include "lwip/stats.h" +#include "netif/etharp.h" +#include "lwip/ip_frag.h" +#include "lwip/snmp_structs.h" +#include "lwip/snmp_msg.h" +#include "lwip/dns.h" +#include "netif/ppp_oe.h" + +#include + +#if !MEMP_MEM_MALLOC /* don't build if not configured for use in lwipopts.h */ + +struct memp { + struct memp *next; +#if MEMP_OVERFLOW_CHECK + const char *file; + int line; +#endif /* MEMP_OVERFLOW_CHECK */ +}; + +#if MEMP_OVERFLOW_CHECK +/* if MEMP_OVERFLOW_CHECK is turned on, we reserve some bytes at the beginning + * and at the end of each element, initialize them as 0xcd and check + * them later. */ +/* If MEMP_OVERFLOW_CHECK is >= 2, on every call to memp_malloc or memp_free, + * every single element in each pool is checked! + * This is VERY SLOW but also very helpful. */ +/* MEMP_SANITY_REGION_BEFORE and MEMP_SANITY_REGION_AFTER can be overridden in + * lwipopts.h to change the amount reserved for checking. */ +#ifndef MEMP_SANITY_REGION_BEFORE +#define MEMP_SANITY_REGION_BEFORE 16 +#endif /* MEMP_SANITY_REGION_BEFORE*/ +#if MEMP_SANITY_REGION_BEFORE > 0 +#define MEMP_SANITY_REGION_BEFORE_ALIGNED LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_BEFORE) +#else +#define MEMP_SANITY_REGION_BEFORE_ALIGNED 0 +#endif /* MEMP_SANITY_REGION_BEFORE*/ +#ifndef MEMP_SANITY_REGION_AFTER +#define MEMP_SANITY_REGION_AFTER 16 +#endif /* MEMP_SANITY_REGION_AFTER*/ +#if MEMP_SANITY_REGION_AFTER > 0 +#define MEMP_SANITY_REGION_AFTER_ALIGNED LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_AFTER) +#else +#define MEMP_SANITY_REGION_AFTER_ALIGNED 0 +#endif /* MEMP_SANITY_REGION_AFTER*/ + +/* MEMP_SIZE: save space for struct memp and for sanity check */ +#define MEMP_SIZE (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEMP_SANITY_REGION_BEFORE_ALIGNED) +#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEMP_SANITY_REGION_AFTER_ALIGNED) + +#else /* MEMP_OVERFLOW_CHECK */ + +/* No sanity checks + * We don't need to preserve the struct memp while not allocated, so we + * can save a little space and set MEMP_SIZE to 0. + */ +#define MEMP_SIZE 0 +#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x)) + +#endif /* MEMP_OVERFLOW_CHECK */ + +/** This array holds the first free element of each pool. + * Elements form a linked list. */ +static struct memp *memp_tab[MEMP_MAX]; + +#else /* MEMP_MEM_MALLOC */ + +#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x)) + +#endif /* MEMP_MEM_MALLOC */ + +/** This array holds the element sizes of each pool. */ +#if !MEM_USE_POOLS && !MEMP_MEM_MALLOC +static +#endif +const u16_t memp_sizes[MEMP_MAX] = { +#define LWIP_MEMPOOL(name,num,size,desc) LWIP_MEM_ALIGN_SIZE(size), +#include "lwip/memp_std.h" +}; + +#if !MEMP_MEM_MALLOC /* don't build if not configured for use in lwipopts.h */ + +/** This array holds the number of elements in each pool. */ +static const u16_t memp_num[MEMP_MAX] = { +#define LWIP_MEMPOOL(name,num,size,desc) (num), +#include "lwip/memp_std.h" +}; + +/** This array holds a textual description of each pool. */ +#ifdef LWIP_DEBUG +static const char *memp_desc[MEMP_MAX] = { +#define LWIP_MEMPOOL(name,num,size,desc) (desc), +#include "lwip/memp_std.h" +}; +#endif /* LWIP_DEBUG */ + +#if MEMP_SEPARATE_POOLS + +/** This creates each memory pool. These are named memp_memory_XXX_base (where + * XXX is the name of the pool defined in memp_std.h). + * To relocate a pool, declare it as extern in cc.h. Example for GCC: + * extern u8_t __attribute__((section(".onchip_mem"))) memp_memory_UDP_PCB_base[]; + */ +#define LWIP_MEMPOOL(name,num,size,desc) u8_t memp_memory_ ## name ## _base \ + [((num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size)))]; +#include "lwip/memp_std.h" + +/** This array holds the base of each memory pool. */ +static u8_t *const memp_bases[] = { +#define LWIP_MEMPOOL(name,num,size,desc) memp_memory_ ## name ## _base, +#include "lwip/memp_std.h" +}; + +#else /* MEMP_SEPARATE_POOLS */ + +/** This is the actual memory used by the pools (all pools in one big block). */ +static u8_t memp_memory[MEM_ALIGNMENT - 1 +#define LWIP_MEMPOOL(name,num,size,desc) + ( (num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size) ) ) +#include "lwip/memp_std.h" +]; + +#endif /* MEMP_SEPARATE_POOLS */ + +#if MEMP_SANITY_CHECK +/** + * Check that memp-lists don't form a circle + */ +static int +memp_sanity(void) +{ + s16_t i, c; + struct memp *m, *n; + + for (i = 0; i < MEMP_MAX; i++) { + for (m = memp_tab[i]; m != NULL; m = m->next) { + c = 1; + for (n = memp_tab[i]; n != NULL; n = n->next) { + if (n == m && --c < 0) { + return 0; + } + } + } + } + return 1; +} +#endif /* MEMP_SANITY_CHECK*/ +#if MEMP_OVERFLOW_CHECK +#if defined(LWIP_DEBUG) && MEMP_STATS +static const char * memp_overflow_names[] = { +#define LWIP_MEMPOOL(name,num,size,desc) "/"desc, +#include "lwip/memp_std.h" + }; +#endif + +/** + * Check if a memp element was victim of an overflow + * (e.g. the restricted area after it has been altered) + * + * @param p the memp element to check + * @param memp_type the pool p comes from + */ +static void +memp_overflow_check_element_overflow(struct memp *p, u16_t memp_type) +{ + u16_t k; + u8_t *m; +#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0 + m = (u8_t*)p + MEMP_SIZE + memp_sizes[memp_type]; + for (k = 0; k < MEMP_SANITY_REGION_AFTER_ALIGNED; k++) { + if (m[k] != 0xcd) { + char errstr[128] = "detected memp overflow in pool "; + char digit[] = "0"; + if(memp_type >= 10) { + digit[0] = '0' + (memp_type/10); + strcat(errstr, digit); + } + digit[0] = '0' + (memp_type%10); + strcat(errstr, digit); +#if defined(LWIP_DEBUG) && MEMP_STATS + strcat(errstr, memp_overflow_names[memp_type]); +#endif + LWIP_ASSERT(errstr, 0); + } + } +#endif +} + +/** + * Check if a memp element was victim of an underflow + * (e.g. the restricted area before it has been altered) + * + * @param p the memp element to check + * @param memp_type the pool p comes from + */ +static void +memp_overflow_check_element_underflow(struct memp *p, u16_t memp_type) +{ + u16_t k; + u8_t *m; +#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 + m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED; + for (k = 0; k < MEMP_SANITY_REGION_BEFORE_ALIGNED; k++) { + if (m[k] != 0xcd) { + char errstr[128] = "detected memp underflow in pool "; + char digit[] = "0"; + if(memp_type >= 10) { + digit[0] = '0' + (memp_type/10); + strcat(errstr, digit); + } + digit[0] = '0' + (memp_type%10); + strcat(errstr, digit); +#if defined(LWIP_DEBUG) && MEMP_STATS + strcat(errstr, memp_overflow_names[memp_type]); +#endif + LWIP_ASSERT(errstr, 0); + } + } +#endif +} + +/** + * Do an overflow check for all elements in every pool. + * + * @see memp_overflow_check_element for a description of the check + */ +static void +memp_overflow_check_all(void) +{ + u16_t i, j; + struct memp *p; + + p = (struct memp *)LWIP_MEM_ALIGN(memp_memory); + for (i = 0; i < MEMP_MAX; ++i) { + p = p; + for (j = 0; j < memp_num[i]; ++j) { + memp_overflow_check_element_overflow(p, i); + p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED); + } + } + p = (struct memp *)LWIP_MEM_ALIGN(memp_memory); + for (i = 0; i < MEMP_MAX; ++i) { + p = p; + for (j = 0; j < memp_num[i]; ++j) { + memp_overflow_check_element_underflow(p, i); + p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED); + } + } +} + +/** + * Initialize the restricted areas of all memp elements in every pool. + */ +static void +memp_overflow_init(void) +{ + u16_t i, j; + struct memp *p; + u8_t *m; + + p = (struct memp *)LWIP_MEM_ALIGN(memp_memory); + for (i = 0; i < MEMP_MAX; ++i) { + p = p; + for (j = 0; j < memp_num[i]; ++j) { +#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0 + m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED; + memset(m, 0xcd, MEMP_SANITY_REGION_BEFORE_ALIGNED); +#endif +#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0 + m = (u8_t*)p + MEMP_SIZE + memp_sizes[i]; + memset(m, 0xcd, MEMP_SANITY_REGION_AFTER_ALIGNED); +#endif + p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED); + } + } +} +#endif /* MEMP_OVERFLOW_CHECK */ + +/** + * Initialize this module. + * + * Carves out memp_memory into linked lists for each pool-type. + */ +void +memp_init(void) +{ + struct memp *memp; + u16_t i, j; + + for (i = 0; i < MEMP_MAX; ++i) { + MEMP_STATS_AVAIL(used, i, 0); + MEMP_STATS_AVAIL(max, i, 0); + MEMP_STATS_AVAIL(err, i, 0); + MEMP_STATS_AVAIL(avail, i, memp_num[i]); + } + +#if !MEMP_SEPARATE_POOLS + memp = (struct memp *)LWIP_MEM_ALIGN(memp_memory); +#endif /* !MEMP_SEPARATE_POOLS */ + /* for every pool: */ + for (i = 0; i < MEMP_MAX; ++i) { + memp_tab[i] = NULL; +#if MEMP_SEPARATE_POOLS + memp = (struct memp*)memp_bases[i]; +#endif /* MEMP_SEPARATE_POOLS */ + /* create a linked list of memp elements */ + for (j = 0; j < memp_num[i]; ++j) { + memp->next = memp_tab[i]; + memp_tab[i] = memp; + memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + memp_sizes[i] +#if MEMP_OVERFLOW_CHECK + + MEMP_SANITY_REGION_AFTER_ALIGNED +#endif + ); + } + } +#if MEMP_OVERFLOW_CHECK + memp_overflow_init(); + /* check everything a first time to see if it worked */ + memp_overflow_check_all(); +#endif /* MEMP_OVERFLOW_CHECK */ +} + +/** + * Get an element from a specific pool. + * + * @param type the pool to get an element from + * + * the debug version has two more parameters: + * @param file file name calling this function + * @param line number of line where this function is called + * + * @return a pointer to the allocated memory or a NULL pointer on error + */ +void * +#if !MEMP_OVERFLOW_CHECK +memp_malloc(memp_t type) +#else +memp_malloc_fn(memp_t type, const char* file, const int line) +#endif +{ + struct memp *memp; + SYS_ARCH_DECL_PROTECT(old_level); + + LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;); + + SYS_ARCH_PROTECT(old_level); +#if MEMP_OVERFLOW_CHECK >= 2 + memp_overflow_check_all(); +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ + + memp = memp_tab[type]; + + if (memp != NULL) { + memp_tab[type] = memp->next; +#if MEMP_OVERFLOW_CHECK + memp->next = NULL; + memp->file = file; + memp->line = line; +#endif /* MEMP_OVERFLOW_CHECK */ + MEMP_STATS_INC_USED(used, type); + LWIP_ASSERT("memp_malloc: memp properly aligned", + ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0); + memp = (struct memp*)(void *)((u8_t*)memp + MEMP_SIZE); + } else { + LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", memp_desc[type])); + MEMP_STATS_INC(err, type); + } + + SYS_ARCH_UNPROTECT(old_level); + + return memp; +} + +/** + * Put an element back into its pool. + * + * @param type the pool where to put mem + * @param mem the memp element to free + */ +void +memp_free(memp_t type, void *mem) +{ + struct memp *memp; + SYS_ARCH_DECL_PROTECT(old_level); + + if (mem == NULL) { + return; + } + LWIP_ASSERT("memp_free: mem properly aligned", + ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0); + + memp = (struct memp *)(void *)((u8_t*)mem - MEMP_SIZE); + + SYS_ARCH_PROTECT(old_level); +#if MEMP_OVERFLOW_CHECK +#if MEMP_OVERFLOW_CHECK >= 2 + memp_overflow_check_all(); +#else + memp_overflow_check_element_overflow(memp, type); + memp_overflow_check_element_underflow(memp, type); +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ +#endif /* MEMP_OVERFLOW_CHECK */ + + MEMP_STATS_DEC(used, type); + + memp->next = memp_tab[type]; + memp_tab[type] = memp; + +#if MEMP_SANITY_CHECK + LWIP_ASSERT("memp sanity", memp_sanity()); +#endif /* MEMP_SANITY_CHECK */ + + SYS_ARCH_UNPROTECT(old_level); +} + +#endif /* MEMP_MEM_MALLOC */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/netif.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/netif.c new file mode 100644 index 0000000..f190b1f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/netif.c @@ -0,0 +1,752 @@ +/** + * @file + * lwIP network interface abstraction + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/tcp_impl.h" +#include "lwip/snmp.h" +#include "lwip/igmp.h" +#include "netif/etharp.h" +#include "lwip/stats.h" +#if ENABLE_LOOPBACK +#include "lwip/sys.h" +#if LWIP_NETIF_LOOPBACK_MULTITHREADING +#include "lwip/tcpip.h" +#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ +#endif /* ENABLE_LOOPBACK */ + +#if LWIP_AUTOIP +#include "lwip/autoip.h" +#endif /* LWIP_AUTOIP */ +#if LWIP_DHCP +#include "lwip/dhcp.h" +#endif /* LWIP_DHCP */ + +#if LWIP_NETIF_STATUS_CALLBACK +#define NETIF_STATUS_CALLBACK(n) do{ if (n->status_callback) { (n->status_callback)(n); }}while(0) +#else +#define NETIF_STATUS_CALLBACK(n) +#endif /* LWIP_NETIF_STATUS_CALLBACK */ + +#if LWIP_NETIF_LINK_CALLBACK +#define NETIF_LINK_CALLBACK(n) do{ if (n->link_callback) { (n->link_callback)(n); }}while(0) +#else +#define NETIF_LINK_CALLBACK(n) +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +struct netif *netif_list; +struct netif *netif_default; + +#if LWIP_HAVE_LOOPIF +static struct netif loop_netif; + +/** + * Initialize a lwip network interface structure for a loopback interface + * + * @param netif the lwip network interface structure for this loopif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + */ +static err_t +netif_loopif_init(struct netif *netif) +{ + /* initialize the snmp variables and counters inside the struct netif + * ifSpeed: no assumption can be made! + */ + NETIF_INIT_SNMP(netif, snmp_ifType_softwareLoopback, 0); + + netif->name[0] = 'l'; + netif->name[1] = 'o'; + netif->output = netif_loop_output; + return ERR_OK; +} +#endif /* LWIP_HAVE_LOOPIF */ + +void +netif_init(void) +{ +#if LWIP_HAVE_LOOPIF + ip_addr_t loop_ipaddr, loop_netmask, loop_gw; + IP4_ADDR(&loop_gw, 127,0,0,1); + IP4_ADDR(&loop_ipaddr, 127,0,0,1); + IP4_ADDR(&loop_netmask, 255,0,0,0); + +#if NO_SYS + netif_add(&loop_netif, &loop_ipaddr, &loop_netmask, &loop_gw, NULL, netif_loopif_init, ip_input); +#else /* NO_SYS */ + netif_add(&loop_netif, &loop_ipaddr, &loop_netmask, &loop_gw, NULL, netif_loopif_init, tcpip_input); +#endif /* NO_SYS */ + netif_set_up(&loop_netif); + +#endif /* LWIP_HAVE_LOOPIF */ +} + +/** + * Add a network interface to the list of lwIP netifs. + * + * @param netif a pre-allocated netif structure + * @param ipaddr IP address for the new netif + * @param netmask network mask for the new netif + * @param gw default gateway IP address for the new netif + * @param state opaque data passed to the new netif + * @param init callback function that initializes the interface + * @param input callback function that is called to pass + * ingress packets up in the protocol layer stack. + * + * @return netif, or NULL if failed. + */ +struct netif * +netif_add(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask, + ip_addr_t *gw, void *state, netif_init_fn init, netif_input_fn input) +{ + static u8_t netifnum = 0; + + LWIP_ASSERT("No init function given", init != NULL); + + /* reset new interface configuration state */ + ip_addr_set_zero(&netif->ip_addr); + ip_addr_set_zero(&netif->netmask); + ip_addr_set_zero(&netif->gw); + netif->flags = 0; +#if LWIP_DHCP + /* netif not under DHCP control by default */ + netif->dhcp = NULL; +#endif /* LWIP_DHCP */ +#if LWIP_AUTOIP + /* netif not under AutoIP control by default */ + netif->autoip = NULL; +#endif /* LWIP_AUTOIP */ +#if LWIP_NETIF_STATUS_CALLBACK + netif->status_callback = NULL; +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK + netif->link_callback = NULL; +#endif /* LWIP_NETIF_LINK_CALLBACK */ +#if LWIP_IGMP + netif->igmp_mac_filter = NULL; +#endif /* LWIP_IGMP */ +#if ENABLE_LOOPBACK + netif->loop_first = NULL; + netif->loop_last = NULL; +#endif /* ENABLE_LOOPBACK */ + + /* remember netif specific state information data */ + netif->state = state; + netif->num = netifnum++; + netif->input = input; +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = NULL; +#endif /* LWIP_NETIF_HWADDRHINT*/ +#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS + netif->loop_cnt_current = 0; +#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */ + + netif_set_addr(netif, ipaddr, netmask, gw); + + /* call user specified initialization function for netif */ + if (init(netif) != ERR_OK) { + return NULL; + } + + /* add this netif to the list */ + netif->next = netif_list; + netif_list = netif; + snmp_inc_iflist(); + +#if LWIP_IGMP + /* start IGMP processing */ + if (netif->flags & NETIF_FLAG_IGMP) { + igmp_start(netif); + } +#endif /* LWIP_IGMP */ + + LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ", + netif->name[0], netif->name[1])); + ip_addr_debug_print(NETIF_DEBUG, ipaddr); + LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); + ip_addr_debug_print(NETIF_DEBUG, netmask); + LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); + ip_addr_debug_print(NETIF_DEBUG, gw); + LWIP_DEBUGF(NETIF_DEBUG, ("\n")); + return netif; +} + +/** + * Change IP address configuration for a network interface (including netmask + * and default gateway). + * + * @param netif the network interface to change + * @param ipaddr the new IP address + * @param netmask the new netmask + * @param gw the new default gateway + */ +void +netif_set_addr(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask, + ip_addr_t *gw) +{ + netif_set_ipaddr(netif, ipaddr); + netif_set_netmask(netif, netmask); + netif_set_gw(netif, gw); +} + +/** + * Remove a network interface from the list of lwIP netifs. + * + * @param netif the network interface to remove + */ +void +netif_remove(struct netif *netif) +{ + if (netif == NULL) { + return; + } + +#if LWIP_IGMP + /* stop IGMP processing */ + if (netif->flags & NETIF_FLAG_IGMP) { + igmp_stop(netif); + } +#endif /* LWIP_IGMP */ + if (netif_is_up(netif)) { + /* set netif down before removing (call callback function) */ + netif_set_down(netif); + } + + snmp_delete_ipaddridx_tree(netif); + + /* is it the first netif? */ + if (netif_list == netif) { + netif_list = netif->next; + } else { + /* look for netif further down the list */ + struct netif * tmpNetif; + for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) { + if (tmpNetif->next == netif) { + tmpNetif->next = netif->next; + break; + } + } + if (tmpNetif == NULL) + return; /* we didn't find any netif today */ + } + snmp_dec_iflist(); + /* this netif is default? */ + if (netif_default == netif) { + /* reset default netif */ + netif_set_default(NULL); + } + LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") ); +} + +/** + * Find a network interface by searching for its name + * + * @param name the name of the netif (like netif->name) plus concatenated number + * in ascii representation (e.g. 'en0') + */ +struct netif * +netif_find(char *name) +{ + struct netif *netif; + u8_t num; + + if (name == NULL) { + return NULL; + } + + num = name[2] - '0'; + + for(netif = netif_list; netif != NULL; netif = netif->next) { + if (num == netif->num && + name[0] == netif->name[0] && + name[1] == netif->name[1]) { + LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1])); + return netif; + } + } + LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1])); + return NULL; +} + +/** + * Change the IP address of a network interface + * + * @param netif the network interface to change + * @param ipaddr the new IP address + * + * @note call netif_set_addr() if you also want to change netmask and + * default gateway + */ +void +netif_set_ipaddr(struct netif *netif, ip_addr_t *ipaddr) +{ + /* TODO: Handling of obsolete pcbs */ + /* See: http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */ +#if LWIP_TCP + struct tcp_pcb *pcb; + struct tcp_pcb_listen *lpcb; + + /* address is actually being changed? */ + if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0) { + /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */ + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n")); + pcb = tcp_active_pcbs; + while (pcb != NULL) { + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr)) +#if LWIP_AUTOIP + /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */ + && !ip_addr_islinklocal(&(pcb->local_ip)) +#endif /* LWIP_AUTOIP */ + ) { + /* this connection must be aborted */ + struct tcp_pcb *next = pcb->next; + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); + tcp_abort(pcb); + pcb = next; + } else { + pcb = pcb->next; + } + } + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + /* PCB bound to current local interface address? */ + if ((!(ip_addr_isany(&(lpcb->local_ip)))) && + (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr)))) { + /* The PCB is listening to the old ipaddr and + * is set to listen to the new one instead */ + ip_addr_set(&(lpcb->local_ip), ipaddr); + } + } + } +#endif + snmp_delete_ipaddridx_tree(netif); + snmp_delete_iprteidx_tree(0,netif); + /* set new IP address to netif */ + ip_addr_set(&(netif->ip_addr), ipaddr); + snmp_insert_ipaddridx_tree(netif); + snmp_insert_iprteidx_tree(0,netif); + + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1_16(&netif->ip_addr), + ip4_addr2_16(&netif->ip_addr), + ip4_addr3_16(&netif->ip_addr), + ip4_addr4_16(&netif->ip_addr))); +} + +/** + * Change the default gateway for a network interface + * + * @param netif the network interface to change + * @param gw the new default gateway + * + * @note call netif_set_addr() if you also want to change ip address and netmask + */ +void +netif_set_gw(struct netif *netif, ip_addr_t *gw) +{ + ip_addr_set(&(netif->gw), gw); + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1_16(&netif->gw), + ip4_addr2_16(&netif->gw), + ip4_addr3_16(&netif->gw), + ip4_addr4_16(&netif->gw))); +} + +/** + * Change the netmask of a network interface + * + * @param netif the network interface to change + * @param netmask the new netmask + * + * @note call netif_set_addr() if you also want to change ip address and + * default gateway + */ +void +netif_set_netmask(struct netif *netif, ip_addr_t *netmask) +{ + snmp_delete_iprteidx_tree(0, netif); + /* set new netmask to netif */ + ip_addr_set(&(netif->netmask), netmask); + snmp_insert_iprteidx_tree(0, netif); + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1_16(&netif->netmask), + ip4_addr2_16(&netif->netmask), + ip4_addr3_16(&netif->netmask), + ip4_addr4_16(&netif->netmask))); +} + +/** + * Set a network interface as the default network interface + * (used to output all packets for which no specific route is found) + * + * @param netif the default network interface + */ +void +netif_set_default(struct netif *netif) +{ + if (netif == NULL) { + /* remove default route */ + snmp_delete_iprteidx_tree(1, netif); + } else { + /* install default route */ + snmp_insert_iprteidx_tree(1, netif); + } + netif_default = netif; + LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", + netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); +} + +/** + * Bring an interface up, available for processing + * traffic. + * + * @note: Enabling DHCP on a down interface will make it come + * up once configured. + * + * @see dhcp_start() + */ +void netif_set_up(struct netif *netif) +{ + if (!(netif->flags & NETIF_FLAG_UP)) { + netif->flags |= NETIF_FLAG_UP; + +#if LWIP_SNMP + snmp_get_sysuptime(&netif->ts); +#endif /* LWIP_SNMP */ + + NETIF_STATUS_CALLBACK(netif); + + if (netif->flags & NETIF_FLAG_LINK_UP) { +#if LWIP_ARP + /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ + if (netif->flags & (NETIF_FLAG_ETHARP)) { + etharp_gratuitous(netif); + } +#endif /* LWIP_ARP */ + +#if LWIP_IGMP + /* resend IGMP memberships */ + if (netif->flags & NETIF_FLAG_IGMP) { + igmp_report_groups( netif); + } +#endif /* LWIP_IGMP */ + } + } +} + +/** + * Bring an interface down, disabling any traffic processing. + * + * @note: Enabling DHCP on a down interface will make it come + * up once configured. + * + * @see dhcp_start() + */ +void netif_set_down(struct netif *netif) +{ + if (netif->flags & NETIF_FLAG_UP) { + netif->flags &= ~NETIF_FLAG_UP; +#if LWIP_SNMP + snmp_get_sysuptime(&netif->ts); +#endif + + NETIF_STATUS_CALLBACK(netif); + } +} + +#if LWIP_NETIF_STATUS_CALLBACK +/** + * Set callback to be called when interface is brought up/down + */ +void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback) +{ + if (netif) { + netif->status_callback = status_callback; + } +} +#endif /* LWIP_NETIF_STATUS_CALLBACK */ + +/** + * Called by a driver when its link goes up + */ +void netif_set_link_up(struct netif *netif ) +{ + if (!(netif->flags & NETIF_FLAG_LINK_UP)) { + netif->flags |= NETIF_FLAG_LINK_UP; + +#if LWIP_DHCP + if (netif->dhcp) { + dhcp_network_changed(netif); + } +#endif /* LWIP_DHCP */ + +#if LWIP_AUTOIP + if (netif->autoip) { + autoip_network_changed(netif); + } +#endif /* LWIP_AUTOIP */ + + if (netif->flags & NETIF_FLAG_UP) { +#if LWIP_ARP + /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ + if (netif->flags & NETIF_FLAG_ETHARP) { + etharp_gratuitous(netif); + } +#endif /* LWIP_ARP */ + +#if LWIP_IGMP + /* resend IGMP memberships */ + if (netif->flags & NETIF_FLAG_IGMP) { + igmp_report_groups( netif); + } +#endif /* LWIP_IGMP */ + } + NETIF_LINK_CALLBACK(netif); + } +} + +/** + * Called by a driver when its link goes down + */ +void netif_set_link_down(struct netif *netif ) +{ + if (netif->flags & NETIF_FLAG_LINK_UP) { + netif->flags &= ~NETIF_FLAG_LINK_UP; + NETIF_LINK_CALLBACK(netif); + } +} + +#if LWIP_NETIF_LINK_CALLBACK +/** + * Set callback to be called when link is brought up/down + */ +void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback) +{ + if (netif) { + netif->link_callback = link_callback; + } +} +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#if ENABLE_LOOPBACK +/** + * Send an IP packet to be received on the same netif (loopif-like). + * The pbuf is simply copied and handed back to netif->input. + * In multithreaded mode, this is done directly since netif->input must put + * the packet on a queue. + * In callback mode, the packet is put on an internal queue and is fed to + * netif->input by netif_poll(). + * + * @param netif the lwip network interface structure + * @param p the (IP) packet to 'send' + * @param ipaddr the ip address to send the packet to (not used) + * @return ERR_OK if the packet has been sent + * ERR_MEM if the pbuf used to copy the packet couldn't be allocated + */ +err_t +netif_loop_output(struct netif *netif, struct pbuf *p, + ip_addr_t *ipaddr) +{ + struct pbuf *r; + err_t err; + struct pbuf *last; +#if LWIP_LOOPBACK_MAX_PBUFS + u8_t clen = 0; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ + /* If we have a loopif, SNMP counters are adjusted for it, + * if not they are adjusted for 'netif'. */ +#if LWIP_SNMP +#if LWIP_HAVE_LOOPIF + struct netif *stats_if = &loop_netif; +#else /* LWIP_HAVE_LOOPIF */ + struct netif *stats_if = netif; +#endif /* LWIP_HAVE_LOOPIF */ +#endif /* LWIP_SNMP */ + SYS_ARCH_DECL_PROTECT(lev); + LWIP_UNUSED_ARG(ipaddr); + + /* Allocate a new pbuf */ + r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM); + if (r == NULL) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + snmp_inc_ifoutdiscards(stats_if); + return ERR_MEM; + } +#if LWIP_LOOPBACK_MAX_PBUFS + clen = pbuf_clen(r); + /* check for overflow or too many pbuf on queue */ + if(((netif->loop_cnt_current + clen) < netif->loop_cnt_current) || + ((netif->loop_cnt_current + clen) > LWIP_LOOPBACK_MAX_PBUFS)) { + pbuf_free(r); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + snmp_inc_ifoutdiscards(stats_if); + return ERR_MEM; + } + netif->loop_cnt_current += clen; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ + + /* Copy the whole pbuf queue p into the single pbuf r */ + if ((err = pbuf_copy(r, p)) != ERR_OK) { + pbuf_free(r); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + snmp_inc_ifoutdiscards(stats_if); + return err; + } + + /* Put the packet on a linked list which gets emptied through calling + netif_poll(). */ + + /* let last point to the last pbuf in chain r */ + for (last = r; last->next != NULL; last = last->next); + + SYS_ARCH_PROTECT(lev); + if(netif->loop_first != NULL) { + LWIP_ASSERT("if first != NULL, last must also be != NULL", netif->loop_last != NULL); + netif->loop_last->next = r; + netif->loop_last = last; + } else { + netif->loop_first = r; + netif->loop_last = last; + } + SYS_ARCH_UNPROTECT(lev); + + LINK_STATS_INC(link.xmit); + snmp_add_ifoutoctets(stats_if, p->tot_len); + snmp_inc_ifoutucastpkts(stats_if); + +#if LWIP_NETIF_LOOPBACK_MULTITHREADING + /* For multithreading environment, schedule a call to netif_poll */ + tcpip_callback((tcpip_callback_fn)netif_poll, netif); +#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ + + return ERR_OK; +} + +/** + * Call netif_poll() in the main loop of your application. This is to prevent + * reentering non-reentrant functions like tcp_input(). Packets passed to + * netif_loop_output() are put on a list that is passed to netif->input() by + * netif_poll(). + */ +void +netif_poll(struct netif *netif) +{ + struct pbuf *in; + /* If we have a loopif, SNMP counters are adjusted for it, + * if not they are adjusted for 'netif'. */ +#if LWIP_SNMP +#if LWIP_HAVE_LOOPIF + struct netif *stats_if = &loop_netif; +#else /* LWIP_HAVE_LOOPIF */ + struct netif *stats_if = netif; +#endif /* LWIP_HAVE_LOOPIF */ +#endif /* LWIP_SNMP */ + SYS_ARCH_DECL_PROTECT(lev); + + do { + /* Get a packet from the list. With SYS_LIGHTWEIGHT_PROT=1, this is protected */ + SYS_ARCH_PROTECT(lev); + in = netif->loop_first; + if (in != NULL) { + struct pbuf *in_end = in; +#if LWIP_LOOPBACK_MAX_PBUFS + u8_t clen = pbuf_clen(in); + /* adjust the number of pbufs on queue */ + LWIP_ASSERT("netif->loop_cnt_current underflow", + ((netif->loop_cnt_current - clen) < netif->loop_cnt_current)); + netif->loop_cnt_current -= clen; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ + while (in_end->len != in_end->tot_len) { + LWIP_ASSERT("bogus pbuf: len != tot_len but next == NULL!", in_end->next != NULL); + in_end = in_end->next; + } + /* 'in_end' now points to the last pbuf from 'in' */ + if (in_end == netif->loop_last) { + /* this was the last pbuf in the list */ + netif->loop_first = netif->loop_last = NULL; + } else { + /* pop the pbuf off the list */ + netif->loop_first = in_end->next; + LWIP_ASSERT("should not be null since first != last!", netif->loop_first != NULL); + } + /* De-queue the pbuf from its successors on the 'loop_' list. */ + in_end->next = NULL; + } + SYS_ARCH_UNPROTECT(lev); + + if (in != NULL) { + LINK_STATS_INC(link.recv); + snmp_add_ifinoctets(stats_if, in->tot_len); + snmp_inc_ifinucastpkts(stats_if); + /* loopback packets are always IP packets! */ + if (ip_input(in, netif) != ERR_OK) { + pbuf_free(in); + } + /* Don't reference the packet any more! */ + in = NULL; + } + /* go on while there is a packet on the list */ + } while (netif->loop_first != NULL); +} + +#if !LWIP_NETIF_LOOPBACK_MULTITHREADING +/** + * Calls netif_poll() for every netif on the netif_list. + */ +void +netif_poll_all(void) +{ + struct netif *netif = netif_list; + /* loop through netifs */ + while (netif != NULL) { + netif_poll(netif); + /* proceed to next network interface */ + netif = netif->next; + } +} +#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ +#endif /* ENABLE_LOOPBACK */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/pbuf.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/pbuf.c new file mode 100644 index 0000000..dd9ff64 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/pbuf.c @@ -0,0 +1,1156 @@ +/** + * @file + * Packet buffer management + * + * Packets are built from the pbuf data structure. It supports dynamic + * memory allocation for packet contents or can reference externally + * managed packet contents both in RAM and ROM. Quick allocation for + * incoming packets is provided through pools with fixed sized pbufs. + * + * A packet may span over multiple pbufs, chained as a singly linked + * list. This is called a "pbuf chain". + * + * Multiple packets may be queued, also using this singly linked list. + * This is called a "packet queue". + * + * So, a packet queue consists of one or more pbuf chains, each of + * which consist of one or more pbufs. CURRENTLY, PACKET QUEUES ARE + * NOT SUPPORTED!!! Use helper structs to queue multiple packets. + * + * The differences between a pbuf chain and a packet queue are very + * precise but subtle. + * + * The last pbuf of a packet has a ->tot_len field that equals the + * ->len field. It can be found by traversing the list. If the last + * pbuf of a packet has a ->next field other than NULL, more packets + * are on the queue. + * + * Therefore, looping through a pbuf of a single packet, has an + * loop end condition (tot_len == p->len), NOT (next == NULL). + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/stats.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "arch/perf.h" +#if TCP_QUEUE_OOSEQ +#include "lwip/tcp_impl.h" +#endif +#if LWIP_CHECKSUM_ON_COPY +#include "lwip/inet_chksum.h" +#endif + +#include + +#define SIZEOF_STRUCT_PBUF LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf)) +/* Since the pool is created in memp, PBUF_POOL_BUFSIZE will be automatically + aligned there. Therefore, PBUF_POOL_BUFSIZE_ALIGNED can be used here. */ +#define PBUF_POOL_BUFSIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE) + +#if !LWIP_TCP || !TCP_QUEUE_OOSEQ || NO_SYS +#define PBUF_POOL_IS_EMPTY() +#else /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || NO_SYS */ +/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */ +#ifndef PBUF_POOL_FREE_OOSEQ +#define PBUF_POOL_FREE_OOSEQ 1 +#endif /* PBUF_POOL_FREE_OOSEQ */ + +#if PBUF_POOL_FREE_OOSEQ +#include "lwip/tcpip.h" +#define PBUF_POOL_IS_EMPTY() pbuf_pool_is_empty() +static u8_t pbuf_free_ooseq_queued; +/** + * Attempt to reclaim some memory from queued out-of-sequence TCP segments + * if we run out of pool pbufs. It's better to give priority to new packets + * if we're running out. + * + * This must be done in the correct thread context therefore this function + * can only be used with NO_SYS=0 and through tcpip_callback. + */ +static void +pbuf_free_ooseq(void* arg) +{ + struct tcp_pcb* pcb; + SYS_ARCH_DECL_PROTECT(old_level); + LWIP_UNUSED_ARG(arg); + + SYS_ARCH_PROTECT(old_level); + pbuf_free_ooseq_queued = 0; + SYS_ARCH_UNPROTECT(old_level); + + for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { + if (NULL != pcb->ooseq) { + /** Free the ooseq pbufs of one PCB only */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n")); + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; + return; + } + } +} + +/** Queue a call to pbuf_free_ooseq if not already queued. */ +static void +pbuf_pool_is_empty(void) +{ + u8_t queued; + SYS_ARCH_DECL_PROTECT(old_level); + + SYS_ARCH_PROTECT(old_level); + queued = pbuf_free_ooseq_queued; + pbuf_free_ooseq_queued = 1; + SYS_ARCH_UNPROTECT(old_level); + + if(!queued) { + /* queue a call to pbuf_free_ooseq if not already queued */ + if(tcpip_callback_with_block(pbuf_free_ooseq, NULL, 0) != ERR_OK) { + SYS_ARCH_PROTECT(old_level); + pbuf_free_ooseq_queued = 0; + SYS_ARCH_UNPROTECT(old_level); + } + } +} +#endif /* PBUF_POOL_FREE_OOSEQ */ +#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || NO_SYS */ + +/** + * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). + * + * The actual memory allocated for the pbuf is determined by the + * layer at which the pbuf is allocated and the requested size + * (from the size parameter). + * + * @param layer flag to define header size + * @param length size of the pbuf's payload + * @param type this parameter decides how and where the pbuf + * should be allocated as follows: + * + * - PBUF_RAM: buffer memory for pbuf is allocated as one large + * chunk. This includes protocol headers as well. + * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for + * protocol headers. Additional headers must be prepended + * by allocating another pbuf and chain in to the front of + * the ROM pbuf. It is assumed that the memory used is really + * similar to ROM in that it is immutable and will not be + * changed. Memory which is dynamic should generally not + * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. + * - PBUF_REF: no buffer memory is allocated for the pbuf, even for + * protocol headers. It is assumed that the pbuf is only + * being used in a single thread. If the pbuf gets queued, + * then pbuf_take should be called to copy the buffer. + * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from + * the pbuf pool that is allocated during pbuf_init(). + * + * @return the allocated pbuf. If multiple pbufs where allocated, this + * is the first pbuf of a pbuf chain. + */ +struct pbuf * +pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type) +{ + struct pbuf *p, *q, *r; + u16_t offset; + s32_t rem_len; /* remaining length */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length)); + + /* determine header offset */ + offset = 0; + switch (layer) { + case PBUF_TRANSPORT: + /* add room for transport (often TCP) layer header */ + offset += PBUF_TRANSPORT_HLEN; + /* FALLTHROUGH */ + case PBUF_IP: + /* add room for IP layer header */ + offset += PBUF_IP_HLEN; + /* FALLTHROUGH */ + case PBUF_LINK: + /* add room for link layer header */ + offset += PBUF_LINK_HLEN; + break; + case PBUF_RAW: + break; + default: + LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0); + return NULL; + } + + switch (type) { + case PBUF_POOL: + /* allocate head of pbuf chain into p */ + p = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL); + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc: allocated pbuf %p\n", (void *)p)); + if (p == NULL) { + PBUF_POOL_IS_EMPTY(); + return NULL; + } + p->type = type; + p->next = NULL; + + /* make the payload pointer point 'offset' bytes into pbuf data memory */ + p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + (SIZEOF_STRUCT_PBUF + offset))); + LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + /* the total length of the pbuf chain is the requested size */ + p->tot_len = length; + /* set the length of the first pbuf in the chain */ + p->len = LWIP_MIN(length, PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)); + LWIP_ASSERT("check p->payload + p->len does not overflow pbuf", + ((u8_t*)p->payload + p->len <= + (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED)); + LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT", + (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 ); + /* set reference count (needed here in case we fail) */ + p->ref = 1; + + /* now allocate the tail of the pbuf chain */ + + /* remember first pbuf for linkage in next iteration */ + r = p; + /* remaining length to be allocated */ + rem_len = length - p->len; + /* any remaining pbufs to be allocated? */ + while (rem_len > 0) { + q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL); + if (q == NULL) { + PBUF_POOL_IS_EMPTY(); + /* free chain so far allocated */ + pbuf_free(p); + /* bail out unsuccesfully */ + return NULL; + } + q->type = type; + q->flags = 0; + q->next = NULL; + /* make previous pbuf point to this pbuf */ + r->next = q; + /* set total length of this pbuf and next in chain */ + LWIP_ASSERT("rem_len < max_u16_t", rem_len < 0xffff); + q->tot_len = (u16_t)rem_len; + /* this pbuf length is pool size, unless smaller sized tail */ + q->len = LWIP_MIN((u16_t)rem_len, PBUF_POOL_BUFSIZE_ALIGNED); + q->payload = (void *)((u8_t *)q + SIZEOF_STRUCT_PBUF); + LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", + ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); + LWIP_ASSERT("check p->payload + p->len does not overflow pbuf", + ((u8_t*)p->payload + p->len <= + (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED)); + q->ref = 1; + /* calculate remaining length to be allocated */ + rem_len -= q->len; + /* remember this pbuf for linkage in next iteration */ + r = q; + } + /* end of chain */ + /*r->next = NULL;*/ + + break; + case PBUF_RAM: + /* If pbuf is to be allocated in RAM, allocate memory for it. */ + p = (struct pbuf*)mem_malloc(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF + offset) + LWIP_MEM_ALIGN_SIZE(length)); + if (p == NULL) { + return NULL; + } + /* Set up internal structure of the pbuf. */ + p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)); + p->len = p->tot_len = length; + p->next = NULL; + p->type = type; + + LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + break; + /* pbuf references existing (non-volatile static constant) ROM payload? */ + case PBUF_ROM: + /* pbuf references existing (externally allocated) RAM payload? */ + case PBUF_REF: + /* only allocate memory for the pbuf structure */ + p = (struct pbuf *)memp_malloc(MEMP_PBUF); + if (p == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", + (type == PBUF_ROM) ? "ROM" : "REF")); + return NULL; + } + /* caller must set this field properly, afterwards */ + p->payload = NULL; + p->len = p->tot_len = length; + p->next = NULL; + p->type = type; + break; + default: + LWIP_ASSERT("pbuf_alloc: erroneous type", 0); + return NULL; + } + /* set reference count */ + p->ref = 1; + /* set flags */ + p->flags = 0; + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); + return p; +} + +#if LWIP_SUPPORT_CUSTOM_PBUF +/** Initialize a custom pbuf (already allocated). + * + * @param layer flag to define header size + * @param length size of the pbuf's payload + * @param type type of the pbuf (only used to treat the pbuf accordingly, as + * this function allocates no memory) + * @param p pointer to the custom pbuf to initialize (already allocated) + * @param payload_mem pointer to the buffer that is used for payload and headers, + * must be at least big enough to hold 'length' plus the header size, + * may be NULL if set later + * @param payload_mem_len the size of the 'payload_mem' buffer, must be at least + * big enough to hold 'length' plus the header size + */ +struct pbuf* +pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p, + void *payload_mem, u16_t payload_mem_len) +{ + u16_t offset; + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length)); + + /* determine header offset */ + offset = 0; + switch (l) { + case PBUF_TRANSPORT: + /* add room for transport (often TCP) layer header */ + offset += PBUF_TRANSPORT_HLEN; + /* FALLTHROUGH */ + case PBUF_IP: + /* add room for IP layer header */ + offset += PBUF_IP_HLEN; + /* FALLTHROUGH */ + case PBUF_LINK: + /* add room for link layer header */ + offset += PBUF_LINK_HLEN; + break; + case PBUF_RAW: + break; + default: + LWIP_ASSERT("pbuf_alloced_custom: bad pbuf layer", 0); + return NULL; + } + + if (LWIP_MEM_ALIGN_SIZE(offset) + length < payload_mem_len) { + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length)); + return NULL; + } + + p->pbuf.next = NULL; + if (payload_mem != NULL) { + p->pbuf.payload = LWIP_MEM_ALIGN((void *)((u8_t *)payload_mem + offset)); + } else { + p->pbuf.payload = NULL; + } + p->pbuf.flags = PBUF_FLAG_IS_CUSTOM; + p->pbuf.len = p->pbuf.tot_len = length; + p->pbuf.type = type; + p->pbuf.ref = 1; + return &p->pbuf; +} +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + +/** + * Shrink a pbuf chain to a desired length. + * + * @param p pbuf to shrink. + * @param new_len desired new length of pbuf chain + * + * Depending on the desired length, the first few pbufs in a chain might + * be skipped and left unchanged. The new last pbuf in the chain will be + * resized, and any remaining pbufs will be freed. + * + * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted. + * @note May not be called on a packet queue. + * + * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain). + */ +void +pbuf_realloc(struct pbuf *p, u16_t new_len) +{ + struct pbuf *q; + u16_t rem_len; /* remaining length */ + s32_t grow; + + LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL); + LWIP_ASSERT("pbuf_realloc: sane p->type", p->type == PBUF_POOL || + p->type == PBUF_ROM || + p->type == PBUF_RAM || + p->type == PBUF_REF); + + /* desired length larger than current length? */ + if (new_len >= p->tot_len) { + /* enlarging not yet supported */ + return; + } + + /* the pbuf chain grows by (new_len - p->tot_len) bytes + * (which may be negative in case of shrinking) */ + grow = new_len - p->tot_len; + + /* first, step over any pbufs that should remain in the chain */ + rem_len = new_len; + q = p; + /* should this pbuf be kept? */ + while (rem_len > q->len) { + /* decrease remaining length by pbuf length */ + rem_len -= q->len; + /* decrease total length indicator */ + LWIP_ASSERT("grow < max_u16_t", grow < 0xffff); + q->tot_len += (u16_t)grow; + /* proceed to next pbuf in chain */ + q = q->next; + LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL); + } + /* we have now reached the new last pbuf (in q) */ + /* rem_len == desired length for pbuf q */ + + /* shrink allocated memory for PBUF_RAM */ + /* (other types merely adjust their length fields */ + if ((q->type == PBUF_RAM) && (rem_len != q->len)) { + /* reallocate and adjust the length of the pbuf that will be split */ + q = (struct pbuf *)mem_trim(q, (u16_t)((u8_t *)q->payload - (u8_t *)q) + rem_len); + LWIP_ASSERT("mem_trim returned q == NULL", q != NULL); + } + /* adjust length fields for new last pbuf */ + q->len = rem_len; + q->tot_len = q->len; + + /* any remaining pbufs in chain? */ + if (q->next != NULL) { + /* free remaining pbufs in chain */ + pbuf_free(q->next); + } + /* q is last packet in chain */ + q->next = NULL; + +} + +/** + * Adjusts the payload pointer to hide or reveal headers in the payload. + * + * Adjusts the ->payload pointer so that space for a header + * (dis)appears in the pbuf payload. + * + * The ->payload, ->tot_len and ->len fields are adjusted. + * + * @param p pbuf to change the header size. + * @param header_size_increment Number of bytes to increment header size which + * increases the size of the pbuf. New space is on the front. + * (Using a negative value decreases the header size.) + * If hdr_size_inc is 0, this function does nothing and returns succesful. + * + * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so + * the call will fail. A check is made that the increase in header size does + * not move the payload pointer in front of the start of the buffer. + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_header(struct pbuf *p, s16_t header_size_increment) +{ + u16_t type; + void *payload; + u16_t increment_magnitude; + + LWIP_ASSERT("p != NULL", p != NULL); + if ((header_size_increment == 0) || (p == NULL)) { + return 0; + } + + if (header_size_increment < 0){ + increment_magnitude = -header_size_increment; + /* Check that we aren't going to move off the end of the pbuf */ + LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;); + } else { + increment_magnitude = header_size_increment; +#if 0 + /* Can't assert these as some callers speculatively call + pbuf_header() to see if it's OK. Will return 1 below instead. */ + /* Check that we've got the correct type of pbuf to work with */ + LWIP_ASSERT("p->type == PBUF_RAM || p->type == PBUF_POOL", + p->type == PBUF_RAM || p->type == PBUF_POOL); + /* Check that we aren't going to move off the beginning of the pbuf */ + LWIP_ASSERT("p->payload - increment_magnitude >= p + SIZEOF_STRUCT_PBUF", + (u8_t *)p->payload - increment_magnitude >= (u8_t *)p + SIZEOF_STRUCT_PBUF); +#endif + } + + type = p->type; + /* remember current payload pointer */ + payload = p->payload; + + /* pbuf types containing payloads? */ + if (type == PBUF_RAM || type == PBUF_POOL) { + /* set new payload pointer */ + p->payload = (u8_t *)p->payload - header_size_increment; + /* boundary check fails? */ + if ((u8_t *)p->payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) { + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_header: failed as %p < %p (not enough space for new header size)\n", + (void *)p->payload, (void *)(p + 1))); + /* restore old payload pointer */ + p->payload = payload; + /* bail out unsuccesfully */ + return 1; + } + /* pbuf types refering to external payloads? */ + } else if (type == PBUF_REF || type == PBUF_ROM) { + /* hide a header in the payload? */ + if ((header_size_increment < 0) && (increment_magnitude <= p->len)) { + /* increase payload pointer */ + p->payload = (u8_t *)p->payload - header_size_increment; + } else { + /* cannot expand payload to front (yet!) + * bail out unsuccesfully */ + return 1; + } + } else { + /* Unknown type */ + LWIP_ASSERT("bad pbuf type", 0); + return 1; + } + /* modify pbuf length fields */ + p->len += header_size_increment; + p->tot_len += header_size_increment; + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_header: old %p new %p (%"S16_F")\n", + (void *)payload, (void *)p->payload, header_size_increment)); + + return 0; +} + +/** + * Dereference a pbuf chain or queue and deallocate any no-longer-used + * pbufs at the head of this chain or queue. + * + * Decrements the pbuf reference count. If it reaches zero, the pbuf is + * deallocated. + * + * For a pbuf chain, this is repeated for each pbuf in the chain, + * up to the first pbuf which has a non-zero reference count after + * decrementing. So, when all reference counts are one, the whole + * chain is free'd. + * + * @param p The pbuf (chain) to be dereferenced. + * + * @return the number of pbufs that were de-allocated + * from the head of the chain. + * + * @note MUST NOT be called on a packet queue (Not verified to work yet). + * @note the reference counter of a pbuf equals the number of pointers + * that refer to the pbuf (or into the pbuf). + * + * @internal examples: + * + * Assuming existing chains a->b->c with the following reference + * counts, calling pbuf_free(a) results in: + * + * 1->2->3 becomes ...1->3 + * 3->3->3 becomes 2->3->3 + * 1->1->2 becomes ......1 + * 2->1->1 becomes 1->1->1 + * 1->1->1 becomes ....... + * + */ +u8_t +pbuf_free(struct pbuf *p) +{ + u16_t type; + struct pbuf *q; + u8_t count; + + if (p == NULL) { + LWIP_ASSERT("p != NULL", p != NULL); + /* if assertions are disabled, proceed with debug output */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_free(p == NULL) was called.\n")); + return 0; + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p)); + + PERF_START; + + LWIP_ASSERT("pbuf_free: sane type", + p->type == PBUF_RAM || p->type == PBUF_ROM || + p->type == PBUF_REF || p->type == PBUF_POOL); + + count = 0; + /* de-allocate all consecutive pbufs from the head of the chain that + * obtain a zero reference count after decrementing*/ + while (p != NULL) { + u16_t ref; + SYS_ARCH_DECL_PROTECT(old_level); + /* Since decrementing ref cannot be guaranteed to be a single machine operation + * we must protect it. We put the new ref into a local variable to prevent + * further protection. */ + SYS_ARCH_PROTECT(old_level); + /* all pbufs in a chain are referenced at least once */ + LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); + /* decrease reference count (number of pointers to pbuf) */ + ref = --(p->ref); + SYS_ARCH_UNPROTECT(old_level); + /* this pbuf is no longer referenced to? */ + if (ref == 0) { + /* remember next pbuf in chain for next iteration */ + q = p->next; + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p)); + type = p->type; +#if LWIP_SUPPORT_CUSTOM_PBUF + /* is this a custom pbuf? */ + if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) { + struct pbuf_custom *pc = (struct pbuf_custom*)p; + LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL); + pc->custom_free_function(p); + } else +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + { + /* is this a pbuf from the pool? */ + if (type == PBUF_POOL) { + memp_free(MEMP_PBUF_POOL, p); + /* is this a ROM or RAM referencing pbuf? */ + } else if (type == PBUF_ROM || type == PBUF_REF) { + memp_free(MEMP_PBUF, p); + /* type == PBUF_RAM */ + } else { + mem_free(p); + } + } + count++; + /* proceed to next pbuf */ + p = q; + /* p->ref > 0, this pbuf is still referenced to */ + /* (and so the remaining pbufs in chain as well) */ + } else { + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, ref)); + /* stop walking through the chain */ + p = NULL; + } + } + PERF_STOP("pbuf_free"); + /* return number of de-allocated pbufs */ + return count; +} + +/** + * Count number of pbufs in a chain + * + * @param p first pbuf of chain + * @return the number of pbufs in a chain + */ + +u8_t +pbuf_clen(struct pbuf *p) +{ + u8_t len; + + len = 0; + while (p != NULL) { + ++len; + p = p->next; + } + return len; +} + +/** + * Increment the reference count of the pbuf. + * + * @param p pbuf to increase reference counter of + * + */ +void +pbuf_ref(struct pbuf *p) +{ + SYS_ARCH_DECL_PROTECT(old_level); + /* pbuf given? */ + if (p != NULL) { + SYS_ARCH_PROTECT(old_level); + ++(p->ref); + SYS_ARCH_UNPROTECT(old_level); + } +} + +/** + * Concatenate two pbufs (each may be a pbuf chain) and take over + * the caller's reference of the tail pbuf. + * + * @note The caller MAY NOT reference the tail pbuf afterwards. + * Use pbuf_chain() for that purpose. + * + * @see pbuf_chain() + */ + +void +pbuf_cat(struct pbuf *h, struct pbuf *t) +{ + struct pbuf *p; + + LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)", + ((h != NULL) && (t != NULL)), return;); + + /* proceed to last pbuf of chain */ + for (p = h; p->next != NULL; p = p->next) { + /* add total length of second chain to all totals of first chain */ + p->tot_len += t->tot_len; + } + /* { p is last pbuf of first h chain, p->next == NULL } */ + LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); + LWIP_ASSERT("p->next == NULL", p->next == NULL); + /* add total length of second chain to last pbuf total of first chain */ + p->tot_len += t->tot_len; + /* chain last pbuf of head (p) with first of tail (t) */ + p->next = t; + /* p->next now references t, but the caller will drop its reference to t, + * so netto there is no change to the reference count of t. + */ +} + +/** + * Chain two pbufs (or pbuf chains) together. + * + * The caller MUST call pbuf_free(t) once it has stopped + * using it. Use pbuf_cat() instead if you no longer use t. + * + * @param h head pbuf (chain) + * @param t tail pbuf (chain) + * @note The pbufs MUST belong to the same packet. + * @note MAY NOT be called on a packet queue. + * + * The ->tot_len fields of all pbufs of the head chain are adjusted. + * The ->next field of the last pbuf of the head chain is adjusted. + * The ->ref field of the first pbuf of the tail chain is adjusted. + * + */ +void +pbuf_chain(struct pbuf *h, struct pbuf *t) +{ + pbuf_cat(h, t); + /* t is now referenced by h */ + pbuf_ref(t); + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); +} + +/** + * Dechains the first pbuf from its succeeding pbufs in the chain. + * + * Makes p->tot_len field equal to p->len. + * @param p pbuf to dechain + * @return remainder of the pbuf chain, or NULL if it was de-allocated. + * @note May not be called on a packet queue. + */ +struct pbuf * +pbuf_dechain(struct pbuf *p) +{ + struct pbuf *q; + u8_t tail_gone = 1; + /* tail */ + q = p->next; + /* pbuf has successor in chain? */ + if (q != NULL) { + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len); + /* enforce invariant if assertion is disabled */ + q->tot_len = p->tot_len - p->len; + /* decouple pbuf from remainder */ + p->next = NULL; + /* total length of pbuf p is its own length only */ + p->tot_len = p->len; + /* q is no longer referenced by p, free it */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); + tail_gone = pbuf_free(q); + if (tail_gone > 0) { + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, + ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); + } + /* return remaining tail or NULL if deallocated */ + } + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len); + return ((tail_gone > 0) ? NULL : q); +} + +/** + * + * Create PBUF_RAM copies of pbufs. + * + * Used to queue packets on behalf of the lwIP stack, such as + * ARP based queueing. + * + * @note You MUST explicitly use p = pbuf_take(p); + * + * @note Only one packet is copied, no packet queue! + * + * @param p_to pbuf destination of the copy + * @param p_from pbuf source of the copy + * + * @return ERR_OK if pbuf was copied + * ERR_ARG if one of the pbufs is NULL or p_to is not big + * enough to hold p_from + */ +err_t +pbuf_copy(struct pbuf *p_to, struct pbuf *p_from) +{ + u16_t offset_to=0, offset_from=0, len; + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n", + (void*)p_to, (void*)p_from)); + + /* is the target big enough to hold the source? */ + LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) && + (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;); + + /* iterate through pbuf chain */ + do + { + LWIP_ASSERT("p_to != NULL", p_to != NULL); + /* copy one part of the original chain */ + if ((p_to->len - offset_to) >= (p_from->len - offset_from)) { + /* complete current p_from fits into current p_to */ + len = p_from->len - offset_from; + } else { + /* current p_from does not fit into current p_to */ + len = p_to->len - offset_to; + } + MEMCPY((u8_t*)p_to->payload + offset_to, (u8_t*)p_from->payload + offset_from, len); + offset_to += len; + offset_from += len; + LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len); + if (offset_to == p_to->len) { + /* on to next p_to (if any) */ + offset_to = 0; + p_to = p_to->next; + } + LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len); + if (offset_from >= p_from->len) { + /* on to next p_from (if any) */ + offset_from = 0; + p_from = p_from->next; + } + + if((p_from != NULL) && (p_from->len == p_from->tot_len)) { + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!\n", + (p_from->next == NULL), return ERR_VAL;); + } + if((p_to != NULL) && (p_to->len == p_to->tot_len)) { + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!\n", + (p_to->next == NULL), return ERR_VAL;); + } + } while (p_from); + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n")); + return ERR_OK; +} + +/** + * Copy (part of) the contents of a packet buffer + * to an application supplied buffer. + * + * @param buf the pbuf from which to copy data + * @param dataptr the application supplied buffer + * @param len length of data to copy (dataptr must be big enough). No more + * than buf->tot_len will be copied, irrespective of len + * @param offset offset into the packet buffer from where to begin copying len bytes + * @return the number of bytes copied, or 0 on failure + */ +u16_t +pbuf_copy_partial(struct pbuf *buf, void *dataptr, u16_t len, u16_t offset) +{ + struct pbuf *p; + u16_t left; + u16_t buf_copy_len; + u16_t copied_total = 0; + + LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;); + LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;); + + left = 0; + + if((buf == NULL) || (dataptr == NULL)) { + return 0; + } + + /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ + for(p = buf; len != 0 && p != NULL; p = p->next) { + if ((offset != 0) && (offset >= p->len)) { + /* don't copy from this buffer -> on to the next */ + offset -= p->len; + } else { + /* copy from this buffer. maybe only partially. */ + buf_copy_len = p->len - offset; + if (buf_copy_len > len) + buf_copy_len = len; + /* copy the necessary parts of the buffer */ + MEMCPY(&((char*)dataptr)[left], &((char*)p->payload)[offset], buf_copy_len); + copied_total += buf_copy_len; + left += buf_copy_len; + len -= buf_copy_len; + offset = 0; + } + } + return copied_total; +} + +/** + * Copy application supplied data into a pbuf. + * This function can only be used to copy the equivalent of buf->tot_len data. + * + * @param buf pbuf to fill with data + * @param dataptr application supplied data buffer + * @param len length of the application supplied data buffer + * + * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough + */ +err_t +pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len) +{ + struct pbuf *p; + u16_t buf_copy_len; + u16_t total_copy_len = len; + u16_t copied_total = 0; + + LWIP_ERROR("pbuf_take: invalid buf", (buf != NULL), return 0;); + LWIP_ERROR("pbuf_take: invalid dataptr", (dataptr != NULL), return 0;); + + if ((buf == NULL) || (dataptr == NULL) || (buf->tot_len < len)) { + return ERR_ARG; + } + + /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ + for(p = buf; total_copy_len != 0; p = p->next) { + LWIP_ASSERT("pbuf_take: invalid pbuf", p != NULL); + buf_copy_len = total_copy_len; + if (buf_copy_len > p->len) { + /* this pbuf cannot hold all remaining data */ + buf_copy_len = p->len; + } + /* copy the necessary parts of the buffer */ + MEMCPY(p->payload, &((char*)dataptr)[copied_total], buf_copy_len); + total_copy_len -= buf_copy_len; + copied_total += buf_copy_len; + } + LWIP_ASSERT("did not copy all data", total_copy_len == 0 && copied_total == len); + return ERR_OK; +} + +/** + * Creates a single pbuf out of a queue of pbufs. + * + * @remark: Either the source pbuf 'p' is freed by this function or the original + * pbuf 'p' is returned, therefore the caller has to check the result! + * + * @param p the source pbuf + * @param layer pbuf_layer of the new pbuf + * + * @return a new, single pbuf (p->next is NULL) + * or the old pbuf if allocation fails + */ +struct pbuf* +pbuf_coalesce(struct pbuf *p, pbuf_layer layer) +{ + struct pbuf *q; + err_t err; + if (p->next == NULL) { + return p; + } + q = pbuf_alloc(layer, p->tot_len, PBUF_RAM); + if (q == NULL) { + /* @todo: what do we do now? */ + return p; + } + err = pbuf_copy(q, p); + LWIP_ASSERT("pbuf_copy failed", err == ERR_OK); + pbuf_free(p); + return q; +} + +#if LWIP_CHECKSUM_ON_COPY +/** + * Copies data into a single pbuf (*not* into a pbuf queue!) and updates + * the checksum while copying + * + * @param p the pbuf to copy data into + * @param start_offset offset of p->payload where to copy the data to + * @param dataptr data to copy into the pbuf + * @param len length of data to copy into the pbuf + * @param chksum pointer to the checksum which is updated + * @return ERR_OK if successful, another error if the data does not fit + * within the (first) pbuf (no pbuf queues!) + */ +err_t +pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr, + u16_t len, u16_t *chksum) +{ + u32_t acc; + u16_t copy_chksum; + char *dst_ptr; + LWIP_ASSERT("p != NULL", p != NULL); + LWIP_ASSERT("dataptr != NULL", dataptr != NULL); + LWIP_ASSERT("chksum != NULL", chksum != NULL); + LWIP_ASSERT("len != 0", len != 0); + + if ((start_offset >= p->len) || (start_offset + len > p->len)) { + return ERR_ARG; + } + + dst_ptr = ((char*)p->payload) + start_offset; + copy_chksum = LWIP_CHKSUM_COPY(dst_ptr, dataptr, len); + if ((start_offset & 1) != 0) { + copy_chksum = SWAP_BYTES_IN_WORD(copy_chksum); + } + acc = *chksum; + acc += copy_chksum; + *chksum = FOLD_U32T(acc); + return ERR_OK; +} +#endif /* LWIP_CHECKSUM_ON_COPY */ + + /** Get one byte from the specified position in a pbuf + * WARNING: returns zero for offset >= p->tot_len + * + * @param p pbuf to parse + * @param offset offset into p of the byte to return + * @return byte at an offset into p OR ZERO IF 'offset' >= p->tot_len + */ +u8_t +pbuf_get_at(struct pbuf* p, u16_t offset) +{ + u16_t copy_from = offset; + struct pbuf* q = p; + + /* get the correct pbuf */ + while ((q != NULL) && (q->len <= copy_from)) { + copy_from -= q->len; + q = q->next; + } + /* return requested data if pbuf is OK */ + if ((q != NULL) && (q->len > copy_from)) { + return ((u8_t*)q->payload)[copy_from]; + } + return 0; +} + +/** Compare pbuf contents at specified offset with memory s2, both of length n + * + * @param p pbuf to compare + * @param offset offset into p at wich to start comparing + * @param s2 buffer to compare + * @param n length of buffer to compare + * @return zero if equal, nonzero otherwise + * (0xffff if p is too short, diffoffset+1 otherwise) + */ +u16_t +pbuf_memcmp(struct pbuf* p, u16_t offset, const void* s2, u16_t n) +{ + u16_t start = offset; + struct pbuf* q = p; + + /* get the correct pbuf */ + while ((q != NULL) && (q->len <= start)) { + start -= q->len; + q = q->next; + } + /* return requested data if pbuf is OK */ + if ((q != NULL) && (q->len > start)) { + u16_t i; + for(i = 0; i < n; i++) { + u8_t a = pbuf_get_at(q, start + i); + u8_t b = ((u8_t*)s2)[i]; + if (a != b) { + return i+1; + } + } + return 0; + } + return 0xffff; +} + +/** Find occurrence of mem (with length mem_len) in pbuf p, starting at offset + * start_offset. + * + * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as + * return value 'not found' + * @param mem search for the contents of this buffer + * @param mem_len length of 'mem' + * @param start_offset offset into p at which to start searching + * @return 0xFFFF if substr was not found in p or the index where it was found + */ +u16_t +pbuf_memfind(struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset) +{ + u16_t i; + u16_t max = p->tot_len - mem_len; + if (p->tot_len >= mem_len + start_offset) { + for(i = start_offset; i <= max; ) { + u16_t plus = pbuf_memcmp(p, i, mem, mem_len); + if (plus == 0) { + return i; + } else { + i += plus; + } + } + } + return 0xFFFF; +} + +/** Find occurrence of substr with length substr_len in pbuf p, start at offset + * start_offset + * WARNING: in contrast to strstr(), this one does not stop at the first \0 in + * the pbuf/source string! + * + * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as + * return value 'not found' + * @param substr string to search for in p, maximum length is 0xFFFE + * @return 0xFFFF if substr was not found in p or the index where it was found + */ +u16_t +pbuf_strstr(struct pbuf* p, const char* substr) +{ + size_t substr_len; + if ((substr == NULL) || (substr[0] == 0) || (p->tot_len == 0xFFFF)) { + return 0xFFFF; + } + substr_len = strlen(substr); + if (substr_len >= 0xFFFF) { + return 0xFFFF; + } + return pbuf_memfind(p, substr, (u16_t)substr_len, 0); +} diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/raw.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/raw.c new file mode 100644 index 0000000..9fcb100 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/raw.c @@ -0,0 +1,354 @@ +/** + * @file + * Implementation of raw protocol PCBs for low-level handling of + * different types of protocols besides (or overriding) those + * already available in lwIP. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/raw.h" +#include "lwip/stats.h" +#include "arch/perf.h" + +#include + +/** The list of RAW PCBs */ +static struct raw_pcb *raw_pcbs; + +/** + * Determine if in incoming IP packet is covered by a RAW PCB + * and if so, pass it to a user-provided receive callback function. + * + * Given an incoming IP datagram (as a chain of pbufs) this function + * finds a corresponding RAW PCB and calls the corresponding receive + * callback function. + * + * @param p pbuf to be demultiplexed to a RAW PCB. + * @param inp network interface on which the datagram was received. + * @return - 1 if the packet has been eaten by a RAW PCB receive + * callback function. The caller MAY NOT not reference the + * packet any longer, and MAY NOT call pbuf_free(). + * @return - 0 if packet is not eaten (pbuf is still referenced by the + * caller). + * + */ +u8_t +raw_input(struct pbuf *p, struct netif *inp) +{ + struct raw_pcb *pcb, *prev; + struct ip_hdr *iphdr; + s16_t proto; + u8_t eaten = 0; + + LWIP_UNUSED_ARG(inp); + + iphdr = (struct ip_hdr *)p->payload; + proto = IPH_PROTO(iphdr); + + prev = NULL; + pcb = raw_pcbs; + /* loop through all raw pcbs until the packet is eaten by one */ + /* this allows multiple pcbs to match against the packet by design */ + while ((eaten == 0) && (pcb != NULL)) { + if ((pcb->protocol == proto) && + (ip_addr_isany(&pcb->local_ip) || + ip_addr_cmp(&(pcb->local_ip), ¤t_iphdr_dest))) { +#if IP_SOF_BROADCAST_RECV + /* broadcast filter? */ + if ((pcb->so_options & SOF_BROADCAST) || !ip_addr_isbroadcast(¤t_iphdr_dest, inp)) +#endif /* IP_SOF_BROADCAST_RECV */ + { + /* receive callback function available? */ + if (pcb->recv != NULL) { + /* the receive callback function did not eat the packet? */ + if (pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr()) != 0) { + /* receive function ate the packet */ + p = NULL; + eaten = 1; + if (prev != NULL) { + /* move the pcb to the front of raw_pcbs so that is + found faster next time */ + prev->next = pcb->next; + pcb->next = raw_pcbs; + raw_pcbs = pcb; + } + } + } + /* no receive callback function was set for this raw PCB */ + } + /* drop the packet */ + } + prev = pcb; + pcb = pcb->next; + } + return eaten; +} + +/** + * Bind a RAW PCB. + * + * @param pcb RAW PCB to be bound with a local address ipaddr. + * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to + * bind to all local interfaces. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_USE. The specified IP address is already bound to by + * another RAW PCB. + * + * @see raw_disconnect() + */ +err_t +raw_bind(struct raw_pcb *pcb, ip_addr_t *ipaddr) +{ + ip_addr_set(&pcb->local_ip, ipaddr); + return ERR_OK; +} + +/** + * Connect an RAW PCB. This function is required by upper layers + * of lwip. Using the raw api you could use raw_sendto() instead + * + * This will associate the RAW PCB with the remote address. + * + * @param pcb RAW PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * + * @return lwIP error code + * + * @see raw_disconnect() and raw_sendto() + */ +err_t +raw_connect(struct raw_pcb *pcb, ip_addr_t *ipaddr) +{ + ip_addr_set(&pcb->remote_ip, ipaddr); + return ERR_OK; +} + + +/** + * Set the callback function for received packets that match the + * raw PCB's protocol and binding. + * + * The callback function MUST either + * - eat the packet by calling pbuf_free() and returning non-zero. The + * packet will not be passed to other raw PCBs or other protocol layers. + * - not free the packet, and return zero. The packet will be matched + * against further PCBs and/or forwarded to another protocol layers. + * + * @return non-zero if the packet was free()d, zero if the packet remains + * available for others. + */ +void +raw_recv(struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg) +{ + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * Send the raw IP packet to the given address. Note that actually you cannot + * modify the IP headers (this is inconsistent with the receive callback where + * you actually get the IP headers), you can only specify the IP payload here. + * It requires some more changes in lwIP. (there will be a raw_send() function + * then.) + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * @param ipaddr the destination address of the IP packet + * + */ +err_t +raw_sendto(struct raw_pcb *pcb, struct pbuf *p, ip_addr_t *ipaddr) +{ + err_t err; + struct netif *netif; + ip_addr_t *src_ip; + struct pbuf *q; /* q will be sent down the stack */ + + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_sendto\n")); + + /* not enough space to add an IP header to first pbuf in given p chain? */ + if (pbuf_header(p, IP_HLEN)) { + /* allocate header in new pbuf */ + q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("raw_sendto: could not allocate header\n")); + return ERR_MEM; + } + if (p->tot_len != 0) { + /* chain header q in front of given pbuf p */ + pbuf_chain(q, p); + } + /* { first pbuf q points to header pbuf } */ + LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* first pbuf q equals given pbuf */ + q = p; + if(pbuf_header(q, -IP_HLEN)) { + LWIP_ASSERT("Can't restore header we just removed!", 0); + return ERR_MEM; + } + } + + if ((netif = ip_route(ipaddr)) == NULL) { + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr))); + /* free any temporary header pbuf allocated by pbuf_header() */ + if (q != p) { + pbuf_free(q); + } + return ERR_RTE; + } + +#if IP_SOF_BROADCAST + /* broadcast filter? */ + if (((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(ipaddr, netif)) { + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); + /* free any temporary header pbuf allocated by pbuf_header() */ + if (q != p) { + pbuf_free(q); + } + return ERR_VAL; + } +#endif /* IP_SOF_BROADCAST */ + + if (ip_addr_isany(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ + src_ip = &(netif->ip_addr); + } else { + /* use RAW PCB local IP address as source address */ + src_ip = &(pcb->local_ip); + } + +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = &(pcb->addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT*/ + err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif); +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = NULL; +#endif /* LWIP_NETIF_HWADDRHINT*/ + + /* did we chain a header earlier? */ + if (q != p) { + /* free the header */ + pbuf_free(q); + } + return err; +} + +/** + * Send the raw IP packet to the address given by raw_connect() + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * + */ +err_t +raw_send(struct raw_pcb *pcb, struct pbuf *p) +{ + return raw_sendto(pcb, p, &pcb->remote_ip); +} + +/** + * Remove an RAW PCB. + * + * @param pcb RAW PCB to be removed. The PCB is removed from the list of + * RAW PCB's and the data structure is freed from memory. + * + * @see raw_new() + */ +void +raw_remove(struct raw_pcb *pcb) +{ + struct raw_pcb *pcb2; + /* pcb to be removed is first in list? */ + if (raw_pcbs == pcb) { + /* make list start at 2nd pcb */ + raw_pcbs = raw_pcbs->next; + /* pcb not 1st in list */ + } else { + for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in raw_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + } + } + } + memp_free(MEMP_RAW_PCB, pcb); +} + +/** + * Create a RAW PCB. + * + * @return The RAW PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP) + * + * @see raw_remove() + */ +struct raw_pcb * +raw_new(u8_t proto) +{ + struct raw_pcb *pcb; + + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_new\n")); + + pcb = (struct raw_pcb *)memp_malloc(MEMP_RAW_PCB); + /* could allocate RAW PCB? */ + if (pcb != NULL) { + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct raw_pcb)); + pcb->protocol = proto; + pcb->ttl = RAW_TTL; + pcb->next = raw_pcbs; + raw_pcbs = pcb; + } + return pcb; +} + +#endif /* LWIP_RAW */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_dec.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_dec.c new file mode 100644 index 0000000..1d56582 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_dec.c @@ -0,0 +1,657 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) decoding + * + * @todo not optimised (yet), favor correctness over speed, favor speed over size + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/snmp_asn1.h" + +/** + * Retrieves type field from incoming pbuf chain. + * + * @param p points to a pbuf holding an ASN1 coded type field + * @param ofs points to the offset within the pbuf chain of the ASN1 coded type field + * @param type return ASN1 type + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + *type = *msg_ptr; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes length field from incoming pbuf chain into host length. + * + * @param p points to a pbuf holding an ASN1 coded length + * @param ofs points to the offset within the pbuf chain of the ASN1 coded length + * @param octets_used returns number of octets used by the length code + * @param length return host order length, upto 64k + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + + if (*msg_ptr < 0x80) + { + /* primitive definite length format */ + *octets_used = 1; + *length = *msg_ptr; + return ERR_OK; + } + else if (*msg_ptr == 0x80) + { + /* constructed indefinite length format, termination with two zero octets */ + u8_t zeros; + u8_t i; + + *length = 0; + zeros = 0; + while (zeros != 2) + { + i = 2; + while (i > 0) + { + i--; + (*length) += 1; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + if (*msg_ptr == 0) + { + zeros++; + if (zeros == 2) + { + /* stop while (i > 0) */ + i = 0; + } + } + else + { + zeros = 0; + } + } + } + *octets_used = 1; + return ERR_OK; + } + else if (*msg_ptr == 0x81) + { + /* constructed definite length format, one octet */ + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + *length = *msg_ptr; + *octets_used = 2; + return ERR_OK; + } + else if (*msg_ptr == 0x82) + { + u8_t i; + + /* constructed definite length format, two octets */ + i = 2; + while (i > 0) + { + i--; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + if (i == 0) + { + /* least significant length octet */ + *length |= *msg_ptr; + } + else + { + /* most significant length octet */ + *length = (*msg_ptr) << 8; + } + } + *octets_used = 3; + return ERR_OK; + } + else + { + /* constructed definite length format 3..127 octets, this is too big (>64k) */ + /** @todo: do we need to accept inefficient codings with many leading zero's? */ + *octets_used = 1 + ((*msg_ptr) & 0x7f); + return ERR_ARG; + } + } + p = p->next; + } + + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes positive integer (counter, gauge, timeticks) into u32_t. + * + * @param p points to a pbuf holding an ASN1 coded integer + * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer + * @param len length of the coded integer field + * @param value return host order integer + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + * + * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded + * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value + * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! + */ +err_t +snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + if ((len > 0) && (len < 6)) + { + /* start from zero */ + *value = 0; + if (*msg_ptr & 0x80) + { + /* negative, expecting zero sign bit! */ + return ERR_ARG; + } + else + { + /* positive */ + if ((len > 1) && (*msg_ptr == 0)) + { + /* skip leading "sign byte" octet 0x00 */ + len--; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + } + /* OR octets with value */ + while (len > 1) + { + len--; + *value |= *msg_ptr; + *value <<= 8; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + *value |= *msg_ptr; + return ERR_OK; + } + else + { + return ERR_ARG; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes integer into s32_t. + * + * @param p points to a pbuf holding an ASN1 coded integer + * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer + * @param len length of the coded integer field + * @param value return host order integer + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + * + * @note ASN coded integers are _always_ signed! + */ +err_t +snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value) +{ + u16_t plen, base; + u8_t *msg_ptr; +#if BYTE_ORDER == LITTLE_ENDIAN + u8_t *lsb_ptr = (u8_t*)value; +#endif +#if BYTE_ORDER == BIG_ENDIAN + u8_t *lsb_ptr = (u8_t*)value + sizeof(s32_t) - 1; +#endif + u8_t sign; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + if ((len > 0) && (len < 5)) + { + if (*msg_ptr & 0x80) + { + /* negative, start from -1 */ + *value = -1; + sign = 1; + } + else + { + /* positive, start from 0 */ + *value = 0; + sign = 0; + } + /* OR/AND octets with value */ + while (len > 1) + { + len--; + if (sign) + { + *lsb_ptr &= *msg_ptr; + *value <<= 8; + *lsb_ptr |= 255; + } + else + { + *lsb_ptr |= *msg_ptr; + *value <<= 8; + } + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + if (sign) + { + *lsb_ptr &= *msg_ptr; + } + else + { + *lsb_ptr |= *msg_ptr; + } + return ERR_OK; + } + else + { + return ERR_ARG; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes object identifier from incoming message into array of s32_t. + * + * @param p points to a pbuf holding an ASN1 coded object identifier + * @param ofs points to the offset within the pbuf chain of the ASN1 coded object identifier + * @param len length of the coded object identifier + * @param oid return object identifier struct + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid) +{ + u16_t plen, base; + u8_t *msg_ptr; + s32_t *oid_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + + oid->len = 0; + oid_ptr = &oid->id[0]; + if (len > 0) + { + /* first compressed octet */ + if (*msg_ptr == 0x2B) + { + /* (most) common case 1.3 (iso.org) */ + *oid_ptr = 1; + oid_ptr++; + *oid_ptr = 3; + oid_ptr++; + } + else if (*msg_ptr < 40) + { + *oid_ptr = 0; + oid_ptr++; + *oid_ptr = *msg_ptr; + oid_ptr++; + } + else if (*msg_ptr < 80) + { + *oid_ptr = 1; + oid_ptr++; + *oid_ptr = (*msg_ptr) - 40; + oid_ptr++; + } + else + { + *oid_ptr = 2; + oid_ptr++; + *oid_ptr = (*msg_ptr) - 80; + oid_ptr++; + } + oid->len = 2; + } + else + { + /* accepting zero length identifiers e.g. for + getnext operation. uncommon but valid */ + return ERR_OK; + } + len--; + if (len > 0) + { + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + while ((len > 0) && (oid->len < LWIP_SNMP_OBJ_ID_LEN)) + { + /* sub-identifier uses multiple octets */ + if (*msg_ptr & 0x80) + { + s32_t sub_id = 0; + + while ((*msg_ptr & 0x80) && (len > 1)) + { + len--; + sub_id = (sub_id << 7) + (*msg_ptr & ~0x80); + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + if (!(*msg_ptr & 0x80) && (len > 0)) + { + /* last octet sub-identifier */ + len--; + sub_id = (sub_id << 7) + *msg_ptr; + *oid_ptr = sub_id; + } + } + else + { + /* !(*msg_ptr & 0x80) sub-identifier uses single octet */ + len--; + *oid_ptr = *msg_ptr; + } + if (len > 0) + { + /* remaining oid bytes available ... */ + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + oid_ptr++; + oid->len++; + } + if (len == 0) + { + /* len == 0, end of oid */ + return ERR_OK; + } + else + { + /* len > 0, oid->len == LWIP_SNMP_OBJ_ID_LEN or malformed encoding */ + return ERR_ARG; + } + + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding) + * from incoming message into array. + * + * @param p points to a pbuf holding an ASN1 coded raw data + * @param ofs points to the offset within the pbuf chain of the ASN1 coded raw data + * @param len length of the coded raw data (zero is valid, e.g. empty string!) + * @param raw_len length of the raw return value + * @param raw return raw bytes + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw) +{ + u16_t plen, base; + u8_t *msg_ptr; + + if (len > 0) + { + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + if (raw_len >= len) + { + while (len > 1) + { + /* copy len - 1 octets */ + len--; + *raw = *msg_ptr; + raw++; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* copy last octet */ + *raw = *msg_ptr; + return ERR_OK; + } + else + { + /* raw_len < len, not enough dst space */ + return ERR_ARG; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; + } + else + { + /* len == 0, empty string */ + return ERR_OK; + } +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_enc.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_enc.c new file mode 100644 index 0000000..64dfc5f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_enc.c @@ -0,0 +1,611 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) encoding + * + * @todo not optimised (yet), favor correctness over speed, favor speed over size + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/snmp_asn1.h" + +/** + * Returns octet count for length. + * + * @param length + * @param octets_needed points to the return value + */ +void +snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed) +{ + if (length < 0x80U) + { + *octets_needed = 1; + } + else if (length < 0x100U) + { + *octets_needed = 2; + } + else + { + *octets_needed = 3; + } +} + +/** + * Returns octet count for an u32_t. + * + * @param value + * @param octets_needed points to the return value + * + * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded + * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value + * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! + */ +void +snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed) +{ + if (value < 0x80UL) + { + *octets_needed = 1; + } + else if (value < 0x8000UL) + { + *octets_needed = 2; + } + else if (value < 0x800000UL) + { + *octets_needed = 3; + } + else if (value < 0x80000000UL) + { + *octets_needed = 4; + } + else + { + *octets_needed = 5; + } +} + +/** + * Returns octet count for an s32_t. + * + * @param value + * @param octets_needed points to the return value + * + * @note ASN coded integers are _always_ signed. + */ +void +snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed) +{ + if (value < 0) + { + value = ~value; + } + if (value < 0x80L) + { + *octets_needed = 1; + } + else if (value < 0x8000L) + { + *octets_needed = 2; + } + else if (value < 0x800000L) + { + *octets_needed = 3; + } + else + { + *octets_needed = 4; + } +} + +/** + * Returns octet count for an object identifier. + * + * @param ident_len object identifier array length + * @param ident points to object identifier array + * @param octets_needed points to the return value + */ +void +snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed) +{ + s32_t sub_id; + u8_t cnt; + + cnt = 0; + if (ident_len > 1) + { + /* compressed prefix in one octet */ + cnt++; + ident_len -= 2; + ident += 2; + } + while(ident_len > 0) + { + ident_len--; + sub_id = *ident; + + sub_id >>= 7; + cnt++; + while(sub_id > 0) + { + sub_id >>= 7; + cnt++; + } + ident++; + } + *octets_needed = cnt; +} + +/** + * Encodes ASN type field into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode value into + * @param ofs points to the offset within the pbuf chain + * @param type input ASN1 type + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + *msg_ptr = type; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes host order length field into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode length into + * @param ofs points to the offset within the pbuf chain + * @param length is the host order length to be encoded + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + + if (length < 0x80) + { + *msg_ptr = (u8_t)length; + return ERR_OK; + } + else if (length < 0x100) + { + *msg_ptr = 0x81; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + *msg_ptr = (u8_t)length; + return ERR_OK; + } + else + { + u8_t i; + + /* length >= 0x100 && length <= 0xFFFF */ + *msg_ptr = 0x82; + i = 2; + while (i > 0) + { + i--; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + if (i == 0) + { + /* least significant length octet */ + *msg_ptr = (u8_t)length; + } + else + { + /* most significant length octet */ + *msg_ptr = (u8_t)(length >> 8); + } + } + return ERR_OK; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes u32_t (counter, gauge, timeticks) into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode value into + * @param ofs points to the offset within the pbuf chain + * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt()) + * @param value is the host order u32_t value to be encoded + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + * + * @see snmp_asn1_enc_u32t_cnt() + */ +err_t +snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, u32_t value) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + + if (octets_needed == 5) + { + /* not enough bits in 'value' add leading 0x00 */ + octets_needed--; + *msg_ptr = 0x00; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + while (octets_needed > 1) + { + octets_needed--; + *msg_ptr = (u8_t)(value >> (octets_needed << 3)); + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* (only) one least significant octet */ + *msg_ptr = (u8_t)value; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes s32_t integer into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode value into + * @param ofs points to the offset within the pbuf chain + * @param octets_needed encoding length (from snmp_asn1_enc_s32t_cnt()) + * @param value is the host order s32_t value to be encoded + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + * + * @see snmp_asn1_enc_s32t_cnt() + */ +err_t +snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, s32_t value) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + + while (octets_needed > 1) + { + octets_needed--; + *msg_ptr = (u8_t)(value >> (octets_needed << 3)); + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* (only) one least significant octet */ + *msg_ptr = (u8_t)value; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes object identifier into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode oid into + * @param ofs points to the offset within the pbuf chain + * @param ident_len object identifier array length + * @param ident points to object identifier array + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + + if (ident_len > 1) + { + if ((ident[0] == 1) && (ident[1] == 3)) + { + /* compressed (most common) prefix .iso.org */ + *msg_ptr = 0x2b; + } + else + { + /* calculate prefix */ + *msg_ptr = (u8_t)((ident[0] * 40) + ident[1]); + } + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + ident_len -= 2; + ident += 2; + } + else + { +/* @bug: allow empty varbinds for symmetry (we must decode them for getnext), allow partial compression?? */ + /* ident_len <= 1, at least we need zeroDotZero (0.0) (ident_len == 2) */ + return ERR_ARG; + } + while (ident_len > 0) + { + s32_t sub_id; + u8_t shift, tail; + + ident_len--; + sub_id = *ident; + tail = 0; + shift = 28; + while(shift > 0) + { + u8_t code; + + code = (u8_t)(sub_id >> shift); + if ((code != 0) || (tail != 0)) + { + tail = 1; + *msg_ptr = code | 0x80; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + shift -= 7; + } + *msg_ptr = (u8_t)sub_id & 0x7F; + if (ident_len > 0) + { + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* proceed to next sub-identifier */ + ident++; + } + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes raw data (octet string, opaque) into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode raw data into + * @param ofs points to the offset within the pbuf chain + * @param raw_len raw data length + * @param raw points raw data + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u16_t raw_len, u8_t *raw) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = (u8_t*)p->payload; + msg_ptr += ofs - base; + + while (raw_len > 1) + { + /* copy raw_len - 1 octets */ + raw_len--; + *msg_ptr = *raw; + raw++; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = (u8_t*)p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + if (raw_len > 0) + { + /* copy last or single octet */ + *msg_ptr = *raw; + } + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/mib2.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/mib2.c new file mode 100644 index 0000000..29decd3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/mib2.c @@ -0,0 +1,4146 @@ +/** + * @file + * Management Information Base II (RFC1213) objects and functions. + * + * @note the object identifiers for this MIB-2 and private MIB tree + * must be kept in sorted ascending order. This to ensure correct getnext operation. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/snmp.h" +#include "lwip/netif.h" +#include "lwip/ip.h" +#include "lwip/ip_frag.h" +#include "lwip/mem.h" +#include "lwip/tcp_impl.h" +#include "lwip/udp.h" +#include "lwip/snmp_asn1.h" +#include "lwip/snmp_structs.h" +#include "lwip/sys.h" +#include "netif/etharp.h" + +/** + * IANA assigned enterprise ID for lwIP is 26381 + * @see http://www.iana.org/assignments/enterprise-numbers + * + * @note this enterprise ID is assigned to the lwIP project, + * all object identifiers living under this ID are assigned + * by the lwIP maintainers (contact Christiaan Simons)! + * @note don't change this define, use snmp_set_sysobjid() + * + * If you need to create your own private MIB you'll need + * to apply for your own enterprise ID with IANA: + * http://www.iana.org/numbers.html + */ +#define SNMP_ENTERPRISE_ID 26381 +#define SNMP_SYSOBJID_LEN 7 +#define SNMP_SYSOBJID {1, 3, 6, 1, 4, 1, SNMP_ENTERPRISE_ID} + +#ifndef SNMP_SYSSERVICES +#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2)) +#endif + +#ifndef SNMP_GET_SYSUPTIME +#define SNMP_GET_SYSUPTIME(sysuptime) +#endif + +static void system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void system_get_value(struct obj_def *od, u16_t len, void *value); +static u8_t system_set_test(struct obj_def *od, u16_t len, void *value); +static void system_set_value(struct obj_def *od, u16_t len, void *value); +static void interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void interfaces_get_value(struct obj_def *od, u16_t len, void *value); +static void ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ifentry_get_value(struct obj_def *od, u16_t len, void *value); +#if !SNMP_SAFE_REQUESTS +static u8_t ifentry_set_test (struct obj_def *od, u16_t len, void *value); +static void ifentry_set_value (struct obj_def *od, u16_t len, void *value); +#endif /* SNMP_SAFE_REQUESTS */ +static void atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void atentry_get_value(struct obj_def *od, u16_t len, void *value); +static void ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_get_value(struct obj_def *od, u16_t len, void *value); +static u8_t ip_set_test(struct obj_def *od, u16_t len, void *value); +static void ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value); +static void ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value); +static void ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value); +static void icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void icmp_get_value(struct obj_def *od, u16_t len, void *value); +#if LWIP_TCP +static void tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void tcp_get_value(struct obj_def *od, u16_t len, void *value); +#ifdef THIS_SEEMS_UNUSED +static void tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value); +#endif +#endif +static void udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void udp_get_value(struct obj_def *od, u16_t len, void *value); +static void udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void udpentry_get_value(struct obj_def *od, u16_t len, void *value); +static void snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void snmp_get_value(struct obj_def *od, u16_t len, void *value); +static u8_t snmp_set_test(struct obj_def *od, u16_t len, void *value); +static void snmp_set_value(struct obj_def *od, u16_t len, void *value); + + +/* snmp .1.3.6.1.2.1.11 */ +const mib_scalar_node snmp_scalar = { + &snmp_get_object_def, + &snmp_get_value, + &snmp_set_test, + &snmp_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t snmp_ids[28] = { + 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30 +}; +struct mib_node* const snmp_nodes[28] = { + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar, + (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar +}; +const struct mib_array_node snmp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 28, + snmp_ids, + snmp_nodes +}; + +/* dot3 and EtherLike MIB not planned. (transmission .1.3.6.1.2.1.10) */ +/* historical (some say hysterical). (cmot .1.3.6.1.2.1.9) */ +/* lwIP has no EGP, thus may not implement it. (egp .1.3.6.1.2.1.8) */ + +/* udp .1.3.6.1.2.1.7 */ +/** index root node for udpTable */ +struct mib_list_rootnode udp_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t udpentry_ids[2] = { 1, 2 }; +struct mib_node* const udpentry_nodes[2] = { + (struct mib_node*)&udp_root, (struct mib_node*)&udp_root, +}; +const struct mib_array_node udpentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 2, + udpentry_ids, + udpentry_nodes +}; + +s32_t udptable_id = 1; +struct mib_node* udptable_node = (struct mib_node*)&udpentry; +struct mib_ram_array_node udptable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &udptable_id, + &udptable_node +}; + +const mib_scalar_node udp_scalar = { + &udp_get_object_def, + &udp_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t udp_ids[5] = { 1, 2, 3, 4, 5 }; +struct mib_node* const udp_nodes[5] = { + (struct mib_node*)&udp_scalar, (struct mib_node*)&udp_scalar, + (struct mib_node*)&udp_scalar, (struct mib_node*)&udp_scalar, + (struct mib_node*)&udptable +}; +const struct mib_array_node udp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 5, + udp_ids, + udp_nodes +}; + +/* tcp .1.3.6.1.2.1.6 */ +#if LWIP_TCP +/* only if the TCP protocol is available may implement this group */ +/** index root node for tcpConnTable */ +struct mib_list_rootnode tcpconntree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t tcpconnentry_ids[5] = { 1, 2, 3, 4, 5 }; +struct mib_node* const tcpconnentry_nodes[5] = { + (struct mib_node*)&tcpconntree_root, (struct mib_node*)&tcpconntree_root, + (struct mib_node*)&tcpconntree_root, (struct mib_node*)&tcpconntree_root, + (struct mib_node*)&tcpconntree_root +}; +const struct mib_array_node tcpconnentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 5, + tcpconnentry_ids, + tcpconnentry_nodes +}; + +s32_t tcpconntable_id = 1; +struct mib_node* tcpconntable_node = (struct mib_node*)&tcpconnentry; +struct mib_ram_array_node tcpconntable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, +/** @todo update maxlength when inserting / deleting from table + 0 when table is empty, 1 when more than one entry */ + 0, + &tcpconntable_id, + &tcpconntable_node +}; + +const mib_scalar_node tcp_scalar = { + &tcp_get_object_def, + &tcp_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t tcp_ids[15] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; +struct mib_node* const tcp_nodes[15] = { + (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, + (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, + (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, + (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, + (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, + (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar, + (struct mib_node*)&tcpconntable, (struct mib_node*)&tcp_scalar, + (struct mib_node*)&tcp_scalar +}; +const struct mib_array_node tcp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 15, + tcp_ids, + tcp_nodes +}; +#endif + +/* icmp .1.3.6.1.2.1.5 */ +const mib_scalar_node icmp_scalar = { + &icmp_get_object_def, + &icmp_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t icmp_ids[26] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; +struct mib_node* const icmp_nodes[26] = { + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar, + (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar +}; +const struct mib_array_node icmp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 26, + icmp_ids, + icmp_nodes +}; + +/** index root node for ipNetToMediaTable */ +struct mib_list_rootnode ipntomtree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t ipntomentry_ids[4] = { 1, 2, 3, 4 }; +struct mib_node* const ipntomentry_nodes[4] = { + (struct mib_node*)&ipntomtree_root, (struct mib_node*)&ipntomtree_root, + (struct mib_node*)&ipntomtree_root, (struct mib_node*)&ipntomtree_root +}; +const struct mib_array_node ipntomentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 4, + ipntomentry_ids, + ipntomentry_nodes +}; + +s32_t ipntomtable_id = 1; +struct mib_node* ipntomtable_node = (struct mib_node*)&ipntomentry; +struct mib_ram_array_node ipntomtable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &ipntomtable_id, + &ipntomtable_node +}; + +/** index root node for ipRouteTable */ +struct mib_list_rootnode iprtetree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t iprteentry_ids[13] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }; +struct mib_node* const iprteentry_nodes[13] = { + (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, + (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, + (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, + (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, + (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, + (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root, + (struct mib_node*)&iprtetree_root +}; +const struct mib_array_node iprteentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 13, + iprteentry_ids, + iprteentry_nodes +}; + +s32_t iprtetable_id = 1; +struct mib_node* iprtetable_node = (struct mib_node*)&iprteentry; +struct mib_ram_array_node iprtetable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &iprtetable_id, + &iprtetable_node +}; + +/** index root node for ipAddrTable */ +struct mib_list_rootnode ipaddrtree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t ipaddrentry_ids[5] = { 1, 2, 3, 4, 5 }; +struct mib_node* const ipaddrentry_nodes[5] = { + (struct mib_node*)&ipaddrtree_root, + (struct mib_node*)&ipaddrtree_root, + (struct mib_node*)&ipaddrtree_root, + (struct mib_node*)&ipaddrtree_root, + (struct mib_node*)&ipaddrtree_root +}; +const struct mib_array_node ipaddrentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 5, + ipaddrentry_ids, + ipaddrentry_nodes +}; + +s32_t ipaddrtable_id = 1; +struct mib_node* ipaddrtable_node = (struct mib_node*)&ipaddrentry; +struct mib_ram_array_node ipaddrtable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &ipaddrtable_id, + &ipaddrtable_node +}; + +/* ip .1.3.6.1.2.1.4 */ +const mib_scalar_node ip_scalar = { + &ip_get_object_def, + &ip_get_value, + &ip_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t ip_ids[23] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; +struct mib_node* const ip_nodes[23] = { + (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, + (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, + (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, + (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, + (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, + (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, + (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, + (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, + (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar, + (struct mib_node*)&ip_scalar, (struct mib_node*)&ipaddrtable, + (struct mib_node*)&iprtetable, (struct mib_node*)&ipntomtable, + (struct mib_node*)&ip_scalar +}; +const struct mib_array_node mib2_ip = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 23, + ip_ids, + ip_nodes +}; + +/** index root node for atTable */ +struct mib_list_rootnode arptree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t atentry_ids[3] = { 1, 2, 3 }; +struct mib_node* const atentry_nodes[3] = { + (struct mib_node*)&arptree_root, + (struct mib_node*)&arptree_root, + (struct mib_node*)&arptree_root +}; +const struct mib_array_node atentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 3, + atentry_ids, + atentry_nodes +}; + +const s32_t attable_id = 1; +struct mib_node* const attable_node = (struct mib_node*)&atentry; +const struct mib_array_node attable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 1, + &attable_id, + &attable_node +}; + +/* at .1.3.6.1.2.1.3 */ +s32_t at_id = 1; +struct mib_node* mib2_at_node = (struct mib_node*)&attable; +struct mib_ram_array_node at = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &at_id, + &mib2_at_node +}; + +/** index root node for ifTable */ +struct mib_list_rootnode iflist_root = { + &ifentry_get_object_def, + &ifentry_get_value, +#if SNMP_SAFE_REQUESTS + &noleafs_set_test, + &noleafs_set_value, +#else /* SNMP_SAFE_REQUESTS */ + &ifentry_set_test, + &ifentry_set_value, +#endif /* SNMP_SAFE_REQUESTS */ + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t ifentry_ids[22] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 }; +struct mib_node* const ifentry_nodes[22] = { + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root, + (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root +}; +const struct mib_array_node ifentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 22, + ifentry_ids, + ifentry_nodes +}; + +s32_t iftable_id = 1; +struct mib_node* iftable_node = (struct mib_node*)&ifentry; +struct mib_ram_array_node iftable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &iftable_id, + &iftable_node +}; + +/* interfaces .1.3.6.1.2.1.2 */ +const mib_scalar_node interfaces_scalar = { + &interfaces_get_object_def, + &interfaces_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t interfaces_ids[2] = { 1, 2 }; +struct mib_node* const interfaces_nodes[2] = { + (struct mib_node*)&interfaces_scalar, (struct mib_node*)&iftable +}; +const struct mib_array_node interfaces = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 2, + interfaces_ids, + interfaces_nodes +}; + + +/* 0 1 2 3 4 5 6 */ +/* system .1.3.6.1.2.1.1 */ +const mib_scalar_node sys_tem_scalar = { + &system_get_object_def, + &system_get_value, + &system_set_test, + &system_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t sys_tem_ids[7] = { 1, 2, 3, 4, 5, 6, 7 }; +struct mib_node* const sys_tem_nodes[7] = { + (struct mib_node*)&sys_tem_scalar, (struct mib_node*)&sys_tem_scalar, + (struct mib_node*)&sys_tem_scalar, (struct mib_node*)&sys_tem_scalar, + (struct mib_node*)&sys_tem_scalar, (struct mib_node*)&sys_tem_scalar, + (struct mib_node*)&sys_tem_scalar +}; +/* work around name issue with 'sys_tem', some compiler(s?) seem to reserve 'system' */ +const struct mib_array_node sys_tem = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 7, + sys_tem_ids, + sys_tem_nodes +}; + +/* mib-2 .1.3.6.1.2.1 */ +#if LWIP_TCP +#define MIB2_GROUPS 8 +#else +#define MIB2_GROUPS 7 +#endif +const s32_t mib2_ids[MIB2_GROUPS] = +{ + 1, + 2, + 3, + 4, + 5, +#if LWIP_TCP + 6, +#endif + 7, + 11 +}; +struct mib_node* const mib2_nodes[MIB2_GROUPS] = { + (struct mib_node*)&sys_tem, + (struct mib_node*)&interfaces, + (struct mib_node*)&at, + (struct mib_node*)&mib2_ip, + (struct mib_node*)&icmp, +#if LWIP_TCP + (struct mib_node*)&tcp, +#endif + (struct mib_node*)&udp, + (struct mib_node*)&snmp +}; + +const struct mib_array_node mib2 = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + MIB2_GROUPS, + mib2_ids, + mib2_nodes +}; + +/* mgmt .1.3.6.1.2 */ +const s32_t mgmt_ids[1] = { 1 }; +struct mib_node* const mgmt_nodes[1] = { (struct mib_node*)&mib2 }; +const struct mib_array_node mgmt = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 1, + mgmt_ids, + mgmt_nodes +}; + +/* internet .1.3.6.1 */ +#if SNMP_PRIVATE_MIB +/* When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. */ +s32_t internet_ids[2] = { 2, 4 }; +struct mib_node* const internet_nodes[2] = { (struct mib_node*)&mgmt, (struct mib_node*)&mib_private }; +const struct mib_array_node internet = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 2, + internet_ids, + internet_nodes +}; +#else +const s32_t internet_ids[1] = { 2 }; +struct mib_node* const internet_nodes[1] = { (struct mib_node*)&mgmt }; +const struct mib_array_node internet = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 1, + internet_ids, + internet_nodes +}; +#endif + +/** mib-2.system.sysObjectID */ +static struct snmp_obj_id sysobjid = {SNMP_SYSOBJID_LEN, SNMP_SYSOBJID}; +/** enterprise ID for generic TRAPs, .iso.org.dod.internet.mgmt.mib-2.snmp */ +static struct snmp_obj_id snmpgrp_id = {7,{1,3,6,1,2,1,11}}; +/** mib-2.system.sysServices */ +static const s32_t sysservices = SNMP_SYSSERVICES; + +/** mib-2.system.sysDescr */ +static const u8_t sysdescr_len_default = 4; +static const u8_t sysdescr_default[] = "lwIP"; +static u8_t* sysdescr_len_ptr = (u8_t*)&sysdescr_len_default; +static u8_t* sysdescr_ptr = (u8_t*)&sysdescr_default[0]; +/** mib-2.system.sysContact */ +static const u8_t syscontact_len_default = 0; +static const u8_t syscontact_default[] = ""; +static u8_t* syscontact_len_ptr = (u8_t*)&syscontact_len_default; +static u8_t* syscontact_ptr = (u8_t*)&syscontact_default[0]; +/** mib-2.system.sysName */ +static const u8_t sysname_len_default = 8; +static const u8_t sysname_default[] = "FQDN-unk"; +static u8_t* sysname_len_ptr = (u8_t*)&sysname_len_default; +static u8_t* sysname_ptr = (u8_t*)&sysname_default[0]; +/** mib-2.system.sysLocation */ +static const u8_t syslocation_len_default = 0; +static const u8_t syslocation_default[] = ""; +static u8_t* syslocation_len_ptr = (u8_t*)&syslocation_len_default; +static u8_t* syslocation_ptr = (u8_t*)&syslocation_default[0]; +/** mib-2.snmp.snmpEnableAuthenTraps */ +static const u8_t snmpenableauthentraps_default = 2; /* disabled */ +static u8_t* snmpenableauthentraps_ptr = (u8_t*)&snmpenableauthentraps_default; + +/** mib-2.interfaces.ifTable.ifEntry.ifSpecific (zeroDotZero) */ +static const struct snmp_obj_id ifspecific = {2, {0, 0}}; +/** mib-2.ip.ipRouteTable.ipRouteEntry.ipRouteInfo (zeroDotZero) */ +static const struct snmp_obj_id iprouteinfo = {2, {0, 0}}; + + + +/* mib-2.system counter(s) */ +static u32_t sysuptime = 0; + +/* mib-2.ip counter(s) */ +static u32_t ipinreceives = 0, + ipinhdrerrors = 0, + ipinaddrerrors = 0, + ipforwdatagrams = 0, + ipinunknownprotos = 0, + ipindiscards = 0, + ipindelivers = 0, + ipoutrequests = 0, + ipoutdiscards = 0, + ipoutnoroutes = 0, + ipreasmreqds = 0, + ipreasmoks = 0, + ipreasmfails = 0, + ipfragoks = 0, + ipfragfails = 0, + ipfragcreates = 0, + iproutingdiscards = 0; +/* mib-2.icmp counter(s) */ +static u32_t icmpinmsgs = 0, + icmpinerrors = 0, + icmpindestunreachs = 0, + icmpintimeexcds = 0, + icmpinparmprobs = 0, + icmpinsrcquenchs = 0, + icmpinredirects = 0, + icmpinechos = 0, + icmpinechoreps = 0, + icmpintimestamps = 0, + icmpintimestampreps = 0, + icmpinaddrmasks = 0, + icmpinaddrmaskreps = 0, + icmpoutmsgs = 0, + icmpouterrors = 0, + icmpoutdestunreachs = 0, + icmpouttimeexcds = 0, + icmpoutparmprobs = 0, + icmpoutsrcquenchs = 0, + icmpoutredirects = 0, + icmpoutechos = 0, + icmpoutechoreps = 0, + icmpouttimestamps = 0, + icmpouttimestampreps = 0, + icmpoutaddrmasks = 0, + icmpoutaddrmaskreps = 0; +/* mib-2.tcp counter(s) */ +static u32_t tcpactiveopens = 0, + tcppassiveopens = 0, + tcpattemptfails = 0, + tcpestabresets = 0, + tcpinsegs = 0, + tcpoutsegs = 0, + tcpretranssegs = 0, + tcpinerrs = 0, + tcpoutrsts = 0; +/* mib-2.udp counter(s) */ +static u32_t udpindatagrams = 0, + udpnoports = 0, + udpinerrors = 0, + udpoutdatagrams = 0; +/* mib-2.snmp counter(s) */ +static u32_t snmpinpkts = 0, + snmpoutpkts = 0, + snmpinbadversions = 0, + snmpinbadcommunitynames = 0, + snmpinbadcommunityuses = 0, + snmpinasnparseerrs = 0, + snmpintoobigs = 0, + snmpinnosuchnames = 0, + snmpinbadvalues = 0, + snmpinreadonlys = 0, + snmpingenerrs = 0, + snmpintotalreqvars = 0, + snmpintotalsetvars = 0, + snmpingetrequests = 0, + snmpingetnexts = 0, + snmpinsetrequests = 0, + snmpingetresponses = 0, + snmpintraps = 0, + snmpouttoobigs = 0, + snmpoutnosuchnames = 0, + snmpoutbadvalues = 0, + snmpoutgenerrs = 0, + snmpoutgetrequests = 0, + snmpoutgetnexts = 0, + snmpoutsetrequests = 0, + snmpoutgetresponses = 0, + snmpouttraps = 0; + + + +/* prototypes of the following functions are in lwip/src/include/lwip/snmp.h */ +/** + * Copy octet string. + * + * @param dst points to destination + * @param src points to source + * @param n number of octets to copy. + */ +static void ocstrncpy(u8_t *dst, u8_t *src, u16_t n) +{ + u16_t i = n; + while (i > 0) { + i--; + *dst++ = *src++; + } +} + +/** + * Copy object identifier (s32_t) array. + * + * @param dst points to destination + * @param src points to source + * @param n number of sub identifiers to copy. + */ +void objectidncpy(s32_t *dst, s32_t *src, u8_t n) +{ + u8_t i = n; + while(i > 0) { + i--; + *dst++ = *src++; + } +} + +/** + * Initializes sysDescr pointers. + * + * @param str if non-NULL then copy str pointer + * @param len points to string length, excluding zero terminator + */ +void snmp_set_sysdesr(u8_t *str, u8_t *len) +{ + if (str != NULL) + { + sysdescr_ptr = str; + sysdescr_len_ptr = len; + } +} + +void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid) +{ + *oid = &sysobjid; +} + +/** + * Initializes sysObjectID value. + * + * @param oid points to stuct snmp_obj_id to copy + */ +void snmp_set_sysobjid(struct snmp_obj_id *oid) +{ + sysobjid = *oid; +} + +/** + * Must be called at regular 10 msec interval from a timer interrupt + * or signal handler depending on your runtime environment. + */ +void snmp_inc_sysuptime(void) +{ + sysuptime++; +} + +void snmp_add_sysuptime(u32_t value) +{ + sysuptime+=value; +} + +void snmp_get_sysuptime(u32_t *value) +{ + SNMP_GET_SYSUPTIME(sysuptime); + *value = sysuptime; +} + +/** + * Initializes sysContact pointers, + * e.g. ptrs to non-volatile memory external to lwIP. + * + * @param ocstr if non-NULL then copy str pointer + * @param ocstrlen points to string length, excluding zero terminator + */ +void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen) +{ + if (ocstr != NULL) + { + syscontact_ptr = ocstr; + syscontact_len_ptr = ocstrlen; + } +} + +/** + * Initializes sysName pointers, + * e.g. ptrs to non-volatile memory external to lwIP. + * + * @param ocstr if non-NULL then copy str pointer + * @param ocstrlen points to string length, excluding zero terminator + */ +void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen) +{ + if (ocstr != NULL) + { + sysname_ptr = ocstr; + sysname_len_ptr = ocstrlen; + } +} + +/** + * Initializes sysLocation pointers, + * e.g. ptrs to non-volatile memory external to lwIP. + * + * @param ocstr if non-NULL then copy str pointer + * @param ocstrlen points to string length, excluding zero terminator + */ +void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen) +{ + if (ocstr != NULL) + { + syslocation_ptr = ocstr; + syslocation_len_ptr = ocstrlen; + } +} + + +void snmp_add_ifinoctets(struct netif *ni, u32_t value) +{ + ni->ifinoctets += value; +} + +void snmp_inc_ifinucastpkts(struct netif *ni) +{ + (ni->ifinucastpkts)++; +} + +void snmp_inc_ifinnucastpkts(struct netif *ni) +{ + (ni->ifinnucastpkts)++; +} + +void snmp_inc_ifindiscards(struct netif *ni) +{ + (ni->ifindiscards)++; +} + +void snmp_add_ifoutoctets(struct netif *ni, u32_t value) +{ + ni->ifoutoctets += value; +} + +void snmp_inc_ifoutucastpkts(struct netif *ni) +{ + (ni->ifoutucastpkts)++; +} + +void snmp_inc_ifoutnucastpkts(struct netif *ni) +{ + (ni->ifoutnucastpkts)++; +} + +void snmp_inc_ifoutdiscards(struct netif *ni) +{ + (ni->ifoutdiscards)++; +} + +void snmp_inc_iflist(void) +{ + struct mib_list_node *if_node = NULL; + + snmp_mib_node_insert(&iflist_root, iflist_root.count + 1, &if_node); + /* enable getnext traversal on filled table */ + iftable.maxlength = 1; +} + +void snmp_dec_iflist(void) +{ + snmp_mib_node_delete(&iflist_root, iflist_root.tail); + /* disable getnext traversal on empty table */ + if(iflist_root.count == 0) iftable.maxlength = 0; +} + +/** + * Inserts ARP table indexes (.xIfIndex.xNetAddress) + * into arp table index trees (both atTable and ipNetToMediaTable). + */ +void snmp_insert_arpidx_tree(struct netif *ni, ip_addr_t *ip) +{ + struct mib_list_rootnode *at_rn; + struct mib_list_node *at_node; + s32_t arpidx[5]; + u8_t level, tree; + + LWIP_ASSERT("ni != NULL", ni != NULL); + snmp_netiftoifindex(ni, &arpidx[0]); + snmp_iptooid(ip, &arpidx[1]); + + for (tree = 0; tree < 2; tree++) + { + if (tree == 0) + { + at_rn = &arptree_root; + } + else + { + at_rn = &ipntomtree_root; + } + for (level = 0; level < 5; level++) + { + at_node = NULL; + snmp_mib_node_insert(at_rn, arpidx[level], &at_node); + if ((level != 4) && (at_node != NULL)) + { + if (at_node->nptr == NULL) + { + at_rn = snmp_mib_lrn_alloc(); + at_node->nptr = (struct mib_node*)at_rn; + if (at_rn != NULL) + { + if (level == 3) + { + if (tree == 0) + { + at_rn->get_object_def = atentry_get_object_def; + at_rn->get_value = atentry_get_value; + } + else + { + at_rn->get_object_def = ip_ntomentry_get_object_def; + at_rn->get_value = ip_ntomentry_get_value; + } + at_rn->set_test = noleafs_set_test; + at_rn->set_value = noleafs_set_value; + } + } + else + { + /* at_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_arpidx_tree() insert failed, mem full")); + break; + } + } + else + { + at_rn = (struct mib_list_rootnode*)at_node->nptr; + } + } + } + } + /* enable getnext traversal on filled tables */ + at.maxlength = 1; + ipntomtable.maxlength = 1; +} + +/** + * Removes ARP table indexes (.xIfIndex.xNetAddress) + * from arp table index trees. + */ +void snmp_delete_arpidx_tree(struct netif *ni, ip_addr_t *ip) +{ + struct mib_list_rootnode *at_rn, *next, *del_rn[5]; + struct mib_list_node *at_n, *del_n[5]; + s32_t arpidx[5]; + u8_t fc, tree, level, del_cnt; + + snmp_netiftoifindex(ni, &arpidx[0]); + snmp_iptooid(ip, &arpidx[1]); + + for (tree = 0; tree < 2; tree++) + { + /* mark nodes for deletion */ + if (tree == 0) + { + at_rn = &arptree_root; + } + else + { + at_rn = &ipntomtree_root; + } + level = 0; + del_cnt = 0; + while ((level < 5) && (at_rn != NULL)) + { + fc = snmp_mib_node_find(at_rn, arpidx[level], &at_n); + if (fc == 0) + { + /* arpidx[level] does not exist */ + del_cnt = 0; + at_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = at_rn; + del_n[del_cnt] = at_n; + del_cnt++; + at_rn = (struct mib_list_rootnode*)(at_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + at_rn = (struct mib_list_rootnode*)(at_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + at_rn = del_rn[del_cnt]; + at_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(at_rn, at_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + } + /* disable getnext traversal on empty tables */ + if(arptree_root.count == 0) at.maxlength = 0; + if(ipntomtree_root.count == 0) ipntomtable.maxlength = 0; +} + +void snmp_inc_ipinreceives(void) +{ + ipinreceives++; +} + +void snmp_inc_ipinhdrerrors(void) +{ + ipinhdrerrors++; +} + +void snmp_inc_ipinaddrerrors(void) +{ + ipinaddrerrors++; +} + +void snmp_inc_ipforwdatagrams(void) +{ + ipforwdatagrams++; +} + +void snmp_inc_ipinunknownprotos(void) +{ + ipinunknownprotos++; +} + +void snmp_inc_ipindiscards(void) +{ + ipindiscards++; +} + +void snmp_inc_ipindelivers(void) +{ + ipindelivers++; +} + +void snmp_inc_ipoutrequests(void) +{ + ipoutrequests++; +} + +void snmp_inc_ipoutdiscards(void) +{ + ipoutdiscards++; +} + +void snmp_inc_ipoutnoroutes(void) +{ + ipoutnoroutes++; +} + +void snmp_inc_ipreasmreqds(void) +{ + ipreasmreqds++; +} + +void snmp_inc_ipreasmoks(void) +{ + ipreasmoks++; +} + +void snmp_inc_ipreasmfails(void) +{ + ipreasmfails++; +} + +void snmp_inc_ipfragoks(void) +{ + ipfragoks++; +} + +void snmp_inc_ipfragfails(void) +{ + ipfragfails++; +} + +void snmp_inc_ipfragcreates(void) +{ + ipfragcreates++; +} + +void snmp_inc_iproutingdiscards(void) +{ + iproutingdiscards++; +} + +/** + * Inserts ipAddrTable indexes (.ipAdEntAddr) + * into index tree. + */ +void snmp_insert_ipaddridx_tree(struct netif *ni) +{ + struct mib_list_rootnode *ipa_rn; + struct mib_list_node *ipa_node; + s32_t ipaddridx[4]; + u8_t level; + + LWIP_ASSERT("ni != NULL", ni != NULL); + snmp_iptooid(&ni->ip_addr, &ipaddridx[0]); + + level = 0; + ipa_rn = &ipaddrtree_root; + while (level < 4) + { + ipa_node = NULL; + snmp_mib_node_insert(ipa_rn, ipaddridx[level], &ipa_node); + if ((level != 3) && (ipa_node != NULL)) + { + if (ipa_node->nptr == NULL) + { + ipa_rn = snmp_mib_lrn_alloc(); + ipa_node->nptr = (struct mib_node*)ipa_rn; + if (ipa_rn != NULL) + { + if (level == 2) + { + ipa_rn->get_object_def = ip_addrentry_get_object_def; + ipa_rn->get_value = ip_addrentry_get_value; + ipa_rn->set_test = noleafs_set_test; + ipa_rn->set_value = noleafs_set_value; + } + } + else + { + /* ipa_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_ipaddridx_tree() insert failed, mem full")); + break; + } + } + else + { + ipa_rn = (struct mib_list_rootnode*)ipa_node->nptr; + } + } + level++; + } + /* enable getnext traversal on filled table */ + ipaddrtable.maxlength = 1; +} + +/** + * Removes ipAddrTable indexes (.ipAdEntAddr) + * from index tree. + */ +void snmp_delete_ipaddridx_tree(struct netif *ni) +{ + struct mib_list_rootnode *ipa_rn, *next, *del_rn[4]; + struct mib_list_node *ipa_n, *del_n[4]; + s32_t ipaddridx[4]; + u8_t fc, level, del_cnt; + + LWIP_ASSERT("ni != NULL", ni != NULL); + snmp_iptooid(&ni->ip_addr, &ipaddridx[0]); + + /* mark nodes for deletion */ + level = 0; + del_cnt = 0; + ipa_rn = &ipaddrtree_root; + while ((level < 4) && (ipa_rn != NULL)) + { + fc = snmp_mib_node_find(ipa_rn, ipaddridx[level], &ipa_n); + if (fc == 0) + { + /* ipaddridx[level] does not exist */ + del_cnt = 0; + ipa_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = ipa_rn; + del_n[del_cnt] = ipa_n; + del_cnt++; + ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + ipa_rn = del_rn[del_cnt]; + ipa_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(ipa_rn, ipa_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + /* disable getnext traversal on empty table */ + if (ipaddrtree_root.count == 0) ipaddrtable.maxlength = 0; +} + +/** + * Inserts ipRouteTable indexes (.ipRouteDest) + * into index tree. + * + * @param dflt non-zero for the default rte, zero for network rte + * @param ni points to network interface for this rte + * + * @todo record sysuptime for _this_ route when it is installed + * (needed for ipRouteAge) in the netif. + */ +void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni) +{ + u8_t insert = 0; + ip_addr_t dst; + + if (dflt != 0) + { + /* the default route 0.0.0.0 */ + ip_addr_set_any(&dst); + insert = 1; + } + else + { + /* route to the network address */ + ip_addr_get_network(&dst, &ni->ip_addr, &ni->netmask); + /* exclude 0.0.0.0 network (reserved for default rte) */ + if (!ip_addr_isany(&dst)) { + insert = 1; + } + } + if (insert) + { + struct mib_list_rootnode *iprte_rn; + struct mib_list_node *iprte_node; + s32_t iprteidx[4]; + u8_t level; + + snmp_iptooid(&dst, &iprteidx[0]); + level = 0; + iprte_rn = &iprtetree_root; + while (level < 4) + { + iprte_node = NULL; + snmp_mib_node_insert(iprte_rn, iprteidx[level], &iprte_node); + if ((level != 3) && (iprte_node != NULL)) + { + if (iprte_node->nptr == NULL) + { + iprte_rn = snmp_mib_lrn_alloc(); + iprte_node->nptr = (struct mib_node*)iprte_rn; + if (iprte_rn != NULL) + { + if (level == 2) + { + iprte_rn->get_object_def = ip_rteentry_get_object_def; + iprte_rn->get_value = ip_rteentry_get_value; + iprte_rn->set_test = noleafs_set_test; + iprte_rn->set_value = noleafs_set_value; + } + } + else + { + /* iprte_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_iprteidx_tree() insert failed, mem full")); + break; + } + } + else + { + iprte_rn = (struct mib_list_rootnode*)iprte_node->nptr; + } + } + level++; + } + } + /* enable getnext traversal on filled table */ + iprtetable.maxlength = 1; +} + +/** + * Removes ipRouteTable indexes (.ipRouteDest) + * from index tree. + * + * @param dflt non-zero for the default rte, zero for network rte + * @param ni points to network interface for this rte or NULL + * for default route to be removed. + */ +void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni) +{ + u8_t del = 0; + ip_addr_t dst; + + if (dflt != 0) + { + /* the default route 0.0.0.0 */ + ip_addr_set_any(&dst); + del = 1; + } + else + { + /* route to the network address */ + ip_addr_get_network(&dst, &ni->ip_addr, &ni->netmask); + /* exclude 0.0.0.0 network (reserved for default rte) */ + if (!ip_addr_isany(&dst)) { + del = 1; + } + } + if (del) + { + struct mib_list_rootnode *iprte_rn, *next, *del_rn[4]; + struct mib_list_node *iprte_n, *del_n[4]; + s32_t iprteidx[4]; + u8_t fc, level, del_cnt; + + snmp_iptooid(&dst, &iprteidx[0]); + /* mark nodes for deletion */ + level = 0; + del_cnt = 0; + iprte_rn = &iprtetree_root; + while ((level < 4) && (iprte_rn != NULL)) + { + fc = snmp_mib_node_find(iprte_rn, iprteidx[level], &iprte_n); + if (fc == 0) + { + /* iprteidx[level] does not exist */ + del_cnt = 0; + iprte_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = iprte_rn; + del_n[del_cnt] = iprte_n; + del_cnt++; + iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + iprte_rn = del_rn[del_cnt]; + iprte_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(iprte_rn, iprte_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + } + /* disable getnext traversal on empty table */ + if (iprtetree_root.count == 0) iprtetable.maxlength = 0; +} + + +void snmp_inc_icmpinmsgs(void) +{ + icmpinmsgs++; +} + +void snmp_inc_icmpinerrors(void) +{ + icmpinerrors++; +} + +void snmp_inc_icmpindestunreachs(void) +{ + icmpindestunreachs++; +} + +void snmp_inc_icmpintimeexcds(void) +{ + icmpintimeexcds++; +} + +void snmp_inc_icmpinparmprobs(void) +{ + icmpinparmprobs++; +} + +void snmp_inc_icmpinsrcquenchs(void) +{ + icmpinsrcquenchs++; +} + +void snmp_inc_icmpinredirects(void) +{ + icmpinredirects++; +} + +void snmp_inc_icmpinechos(void) +{ + icmpinechos++; +} + +void snmp_inc_icmpinechoreps(void) +{ + icmpinechoreps++; +} + +void snmp_inc_icmpintimestamps(void) +{ + icmpintimestamps++; +} + +void snmp_inc_icmpintimestampreps(void) +{ + icmpintimestampreps++; +} + +void snmp_inc_icmpinaddrmasks(void) +{ + icmpinaddrmasks++; +} + +void snmp_inc_icmpinaddrmaskreps(void) +{ + icmpinaddrmaskreps++; +} + +void snmp_inc_icmpoutmsgs(void) +{ + icmpoutmsgs++; +} + +void snmp_inc_icmpouterrors(void) +{ + icmpouterrors++; +} + +void snmp_inc_icmpoutdestunreachs(void) +{ + icmpoutdestunreachs++; +} + +void snmp_inc_icmpouttimeexcds(void) +{ + icmpouttimeexcds++; +} + +void snmp_inc_icmpoutparmprobs(void) +{ + icmpoutparmprobs++; +} + +void snmp_inc_icmpoutsrcquenchs(void) +{ + icmpoutsrcquenchs++; +} + +void snmp_inc_icmpoutredirects(void) +{ + icmpoutredirects++; +} + +void snmp_inc_icmpoutechos(void) +{ + icmpoutechos++; +} + +void snmp_inc_icmpoutechoreps(void) +{ + icmpoutechoreps++; +} + +void snmp_inc_icmpouttimestamps(void) +{ + icmpouttimestamps++; +} + +void snmp_inc_icmpouttimestampreps(void) +{ + icmpouttimestampreps++; +} + +void snmp_inc_icmpoutaddrmasks(void) +{ + icmpoutaddrmasks++; +} + +void snmp_inc_icmpoutaddrmaskreps(void) +{ + icmpoutaddrmaskreps++; +} + +void snmp_inc_tcpactiveopens(void) +{ + tcpactiveopens++; +} + +void snmp_inc_tcppassiveopens(void) +{ + tcppassiveopens++; +} + +void snmp_inc_tcpattemptfails(void) +{ + tcpattemptfails++; +} + +void snmp_inc_tcpestabresets(void) +{ + tcpestabresets++; +} + +void snmp_inc_tcpinsegs(void) +{ + tcpinsegs++; +} + +void snmp_inc_tcpoutsegs(void) +{ + tcpoutsegs++; +} + +void snmp_inc_tcpretranssegs(void) +{ + tcpretranssegs++; +} + +void snmp_inc_tcpinerrs(void) +{ + tcpinerrs++; +} + +void snmp_inc_tcpoutrsts(void) +{ + tcpoutrsts++; +} + +void snmp_inc_udpindatagrams(void) +{ + udpindatagrams++; +} + +void snmp_inc_udpnoports(void) +{ + udpnoports++; +} + +void snmp_inc_udpinerrors(void) +{ + udpinerrors++; +} + +void snmp_inc_udpoutdatagrams(void) +{ + udpoutdatagrams++; +} + +/** + * Inserts udpTable indexes (.udpLocalAddress.udpLocalPort) + * into index tree. + */ +void snmp_insert_udpidx_tree(struct udp_pcb *pcb) +{ + struct mib_list_rootnode *udp_rn; + struct mib_list_node *udp_node; + s32_t udpidx[5]; + u8_t level; + + LWIP_ASSERT("pcb != NULL", pcb != NULL); + snmp_iptooid(&pcb->local_ip, &udpidx[0]); + udpidx[4] = pcb->local_port; + + udp_rn = &udp_root; + for (level = 0; level < 5; level++) + { + udp_node = NULL; + snmp_mib_node_insert(udp_rn, udpidx[level], &udp_node); + if ((level != 4) && (udp_node != NULL)) + { + if (udp_node->nptr == NULL) + { + udp_rn = snmp_mib_lrn_alloc(); + udp_node->nptr = (struct mib_node*)udp_rn; + if (udp_rn != NULL) + { + if (level == 3) + { + udp_rn->get_object_def = udpentry_get_object_def; + udp_rn->get_value = udpentry_get_value; + udp_rn->set_test = noleafs_set_test; + udp_rn->set_value = noleafs_set_value; + } + } + else + { + /* udp_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_udpidx_tree() insert failed, mem full")); + break; + } + } + else + { + udp_rn = (struct mib_list_rootnode*)udp_node->nptr; + } + } + } + udptable.maxlength = 1; +} + +/** + * Removes udpTable indexes (.udpLocalAddress.udpLocalPort) + * from index tree. + */ +void snmp_delete_udpidx_tree(struct udp_pcb *pcb) +{ + struct udp_pcb *npcb; + struct mib_list_rootnode *udp_rn, *next, *del_rn[5]; + struct mib_list_node *udp_n, *del_n[5]; + s32_t udpidx[5]; + u8_t bindings, fc, level, del_cnt; + + LWIP_ASSERT("pcb != NULL", pcb != NULL); + snmp_iptooid(&pcb->local_ip, &udpidx[0]); + udpidx[4] = pcb->local_port; + + /* count PCBs for a given binding + (e.g. when reusing ports or for temp output PCBs) */ + bindings = 0; + npcb = udp_pcbs; + while ((npcb != NULL)) + { + if (ip_addr_cmp(&npcb->local_ip, &pcb->local_ip) && + (npcb->local_port == udpidx[4])) + { + bindings++; + } + npcb = npcb->next; + } + if (bindings == 1) + { + /* selectively remove */ + /* mark nodes for deletion */ + level = 0; + del_cnt = 0; + udp_rn = &udp_root; + while ((level < 5) && (udp_rn != NULL)) + { + fc = snmp_mib_node_find(udp_rn, udpidx[level], &udp_n); + if (fc == 0) + { + /* udpidx[level] does not exist */ + del_cnt = 0; + udp_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = udp_rn; + del_n[del_cnt] = udp_n; + del_cnt++; + udp_rn = (struct mib_list_rootnode*)(udp_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + udp_rn = (struct mib_list_rootnode*)(udp_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + udp_rn = del_rn[del_cnt]; + udp_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(udp_rn, udp_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + } + /* disable getnext traversal on empty table */ + if (udp_root.count == 0) udptable.maxlength = 0; +} + + +void snmp_inc_snmpinpkts(void) +{ + snmpinpkts++; +} + +void snmp_inc_snmpoutpkts(void) +{ + snmpoutpkts++; +} + +void snmp_inc_snmpinbadversions(void) +{ + snmpinbadversions++; +} + +void snmp_inc_snmpinbadcommunitynames(void) +{ + snmpinbadcommunitynames++; +} + +void snmp_inc_snmpinbadcommunityuses(void) +{ + snmpinbadcommunityuses++; +} + +void snmp_inc_snmpinasnparseerrs(void) +{ + snmpinasnparseerrs++; +} + +void snmp_inc_snmpintoobigs(void) +{ + snmpintoobigs++; +} + +void snmp_inc_snmpinnosuchnames(void) +{ + snmpinnosuchnames++; +} + +void snmp_inc_snmpinbadvalues(void) +{ + snmpinbadvalues++; +} + +void snmp_inc_snmpinreadonlys(void) +{ + snmpinreadonlys++; +} + +void snmp_inc_snmpingenerrs(void) +{ + snmpingenerrs++; +} + +void snmp_add_snmpintotalreqvars(u8_t value) +{ + snmpintotalreqvars += value; +} + +void snmp_add_snmpintotalsetvars(u8_t value) +{ + snmpintotalsetvars += value; +} + +void snmp_inc_snmpingetrequests(void) +{ + snmpingetrequests++; +} + +void snmp_inc_snmpingetnexts(void) +{ + snmpingetnexts++; +} + +void snmp_inc_snmpinsetrequests(void) +{ + snmpinsetrequests++; +} + +void snmp_inc_snmpingetresponses(void) +{ + snmpingetresponses++; +} + +void snmp_inc_snmpintraps(void) +{ + snmpintraps++; +} + +void snmp_inc_snmpouttoobigs(void) +{ + snmpouttoobigs++; +} + +void snmp_inc_snmpoutnosuchnames(void) +{ + snmpoutnosuchnames++; +} + +void snmp_inc_snmpoutbadvalues(void) +{ + snmpoutbadvalues++; +} + +void snmp_inc_snmpoutgenerrs(void) +{ + snmpoutgenerrs++; +} + +void snmp_inc_snmpoutgetrequests(void) +{ + snmpoutgetrequests++; +} + +void snmp_inc_snmpoutgetnexts(void) +{ + snmpoutgetnexts++; +} + +void snmp_inc_snmpoutsetrequests(void) +{ + snmpoutsetrequests++; +} + +void snmp_inc_snmpoutgetresponses(void) +{ + snmpoutgetresponses++; +} + +void snmp_inc_snmpouttraps(void) +{ + snmpouttraps++; +} + +void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid) +{ + *oid = &snmpgrp_id; +} + +void snmp_set_snmpenableauthentraps(u8_t *value) +{ + if (value != NULL) + { + snmpenableauthentraps_ptr = value; + } +} + +void snmp_get_snmpenableauthentraps(u8_t *value) +{ + *value = *snmpenableauthentraps_ptr; +} + +void +noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + LWIP_UNUSED_ARG(ident_len); + LWIP_UNUSED_ARG(ident); + od->instance = MIB_OBJECT_NONE; +} + +void +noleafs_get_value(struct obj_def *od, u16_t len, void *value) +{ + LWIP_UNUSED_ARG(od); + LWIP_UNUSED_ARG(len); + LWIP_UNUSED_ARG(value); +} + +u8_t +noleafs_set_test(struct obj_def *od, u16_t len, void *value) +{ + LWIP_UNUSED_ARG(od); + LWIP_UNUSED_ARG(len); + LWIP_UNUSED_ARG(value); + /* can't set */ + return 0; +} + +void +noleafs_set_value(struct obj_def *od, u16_t len, void *value) +{ + LWIP_UNUSED_ARG(od); + LWIP_UNUSED_ARG(len); + LWIP_UNUSED_ARG(value); +} + + +/** + * Returns systems object definitions. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param od points to object definition. + */ +static void +system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff)); + id = (u8_t)ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def system.%"U16_F".0\n",(u16_t)id)); + switch (id) + { + case 1: /* sysDescr */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *sysdescr_len_ptr; + break; + case 2: /* sysObjectID */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); + od->v_len = sysobjid.len * sizeof(s32_t); + break; + case 3: /* sysUpTime */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS); + od->v_len = sizeof(u32_t); + break; + case 4: /* sysContact */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *syscontact_len_ptr; + break; + case 5: /* sysName */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *sysname_len_ptr; + break; + case 6: /* sysLocation */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *syslocation_len_ptr; + break; + case 7: /* sysServices */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +/** + * Returns system object value. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value into. + */ +static void +system_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* sysDescr */ + ocstrncpy((u8_t*)value, sysdescr_ptr, len); + break; + case 2: /* sysObjectID */ + objectidncpy((s32_t*)value, (s32_t*)sysobjid.id, (u8_t)(len / sizeof(s32_t))); + break; + case 3: /* sysUpTime */ + { + snmp_get_sysuptime((u32_t*)value); + } + break; + case 4: /* sysContact */ + ocstrncpy((u8_t*)value, syscontact_ptr, len); + break; + case 5: /* sysName */ + ocstrncpy((u8_t*)value, sysname_ptr, len); + break; + case 6: /* sysLocation */ + ocstrncpy((u8_t*)value, syslocation_ptr, len); + break; + case 7: /* sysServices */ + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = sysservices; + } + break; + }; +} + +static u8_t +system_set_test(struct obj_def *od, u16_t len, void *value) +{ + u8_t id, set_ok; + + LWIP_UNUSED_ARG(value); + set_ok = 0; + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 4: /* sysContact */ + if ((syscontact_ptr != syscontact_default) && + (len <= 255)) + { + set_ok = 1; + } + break; + case 5: /* sysName */ + if ((sysname_ptr != sysname_default) && + (len <= 255)) + { + set_ok = 1; + } + break; + case 6: /* sysLocation */ + if ((syslocation_ptr != syslocation_default) && + (len <= 255)) + { + set_ok = 1; + } + break; + }; + return set_ok; +} + +static void +system_set_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + LWIP_ASSERT("invalid len", len <= 0xff); + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 4: /* sysContact */ + ocstrncpy(syscontact_ptr, (u8_t*)value, len); + *syscontact_len_ptr = (u8_t)len; + break; + case 5: /* sysName */ + ocstrncpy(sysname_ptr, (u8_t*)value, len); + *sysname_len_ptr = (u8_t)len; + break; + case 6: /* sysLocation */ + ocstrncpy(syslocation_ptr, (u8_t*)value, len); + *syslocation_len_ptr = (u8_t)len; + break; + }; +} + +/** + * Returns interfaces.ifnumber object definition. + * + * @param ident_len the address length (2) + * @param ident points to objectname.index + * @param od points to object definition. + */ +static void +interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("interfaces_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +/** + * Returns interfaces.ifnumber object value. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value into. + */ +static void +interfaces_get_value(struct obj_def *od, u16_t len, void *value) +{ + LWIP_UNUSED_ARG(len); + if (od->id_inst_ptr[0] == 1) + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = iflist_root.count; + } +} + +/** + * Returns ifentry object definitions. + * + * @param ident_len the address length (2) + * @param ident points to objectname.index + * @param od points to object definition. + */ +static void +ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff)); + id = (u8_t)ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ifentry.%"U16_F"\n",(u16_t)id)); + switch (id) + { + case 1: /* ifIndex */ + case 3: /* ifType */ + case 4: /* ifMtu */ + case 8: /* ifOperStatus */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* ifDescr */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + /** @todo this should be some sort of sizeof(struct netif.name) */ + od->v_len = 2; + break; + case 5: /* ifSpeed */ + case 21: /* ifOutQLen */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE); + od->v_len = sizeof(u32_t); + break; + case 6: /* ifPhysAddress */ + { + struct netif *netif; + + snmp_ifindextonetif(ident[1], &netif); + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = netif->hwaddr_len; + } + break; + case 7: /* ifAdminStatus */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 9: /* ifLastChange */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS); + od->v_len = sizeof(u32_t); + break; + case 10: /* ifInOctets */ + case 11: /* ifInUcastPkts */ + case 12: /* ifInNUcastPkts */ + case 13: /* ifInDiscarts */ + case 14: /* ifInErrors */ + case 15: /* ifInUnkownProtos */ + case 16: /* ifOutOctets */ + case 17: /* ifOutUcastPkts */ + case 18: /* ifOutNUcastPkts */ + case 19: /* ifOutDiscarts */ + case 20: /* ifOutErrors */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 22: /* ifSpecific */ + /** @note returning zeroDotZero (0.0) no media specific MIB support */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); + od->v_len = ifspecific.len * sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +/** + * Returns ifentry object value. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value into. + */ +static void +ifentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + struct netif *netif; + u8_t id; + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ifIndex */ + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = od->id_inst_ptr[1]; + } + break; + case 2: /* ifDescr */ + ocstrncpy((u8_t*)value, (u8_t*)netif->name, len); + break; + case 3: /* ifType */ + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = netif->link_type; + } + break; + case 4: /* ifMtu */ + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = netif->mtu; + } + break; + case 5: /* ifSpeed */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->link_speed; + } + break; + case 6: /* ifPhysAddress */ + ocstrncpy((u8_t*)value, netif->hwaddr, len); + break; + case 7: /* ifAdminStatus */ + { + s32_t *sint_ptr = (s32_t*)value; + if (netif_is_up(netif)) + { + if (netif_is_link_up(netif)) + { + *sint_ptr = 1; /* up */ + } + else + { + *sint_ptr = 7; /* lowerLayerDown */ + } + } + else + { + *sint_ptr = 2; /* down */ + } + } + break; + case 8: /* ifOperStatus */ + { + s32_t *sint_ptr = (s32_t*)value; + if (netif_is_up(netif)) + { + *sint_ptr = 1; + } + else + { + *sint_ptr = 2; + } + } + break; + case 9: /* ifLastChange */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->ts; + } + break; + case 10: /* ifInOctets */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->ifinoctets; + } + break; + case 11: /* ifInUcastPkts */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->ifinucastpkts; + } + break; + case 12: /* ifInNUcastPkts */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->ifinnucastpkts; + } + break; + case 13: /* ifInDiscarts */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->ifindiscards; + } + break; + case 14: /* ifInErrors */ + case 15: /* ifInUnkownProtos */ + /** @todo add these counters! */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = 0; + } + break; + case 16: /* ifOutOctets */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->ifoutoctets; + } + break; + case 17: /* ifOutUcastPkts */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->ifoutucastpkts; + } + break; + case 18: /* ifOutNUcastPkts */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->ifoutnucastpkts; + } + break; + case 19: /* ifOutDiscarts */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = netif->ifoutdiscards; + } + break; + case 20: /* ifOutErrors */ + /** @todo add this counter! */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = 0; + } + break; + case 21: /* ifOutQLen */ + /** @todo figure out if this must be 0 (no queue) or 1? */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = 0; + } + break; + case 22: /* ifSpecific */ + objectidncpy((s32_t*)value, (s32_t*)ifspecific.id, (u8_t)(len / sizeof(s32_t))); + break; + }; +} + +#if !SNMP_SAFE_REQUESTS +static u8_t +ifentry_set_test(struct obj_def *od, u16_t len, void *value) +{ + struct netif *netif; + u8_t id, set_ok; + LWIP_UNUSED_ARG(len); + + set_ok = 0; + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 7: /* ifAdminStatus */ + { + s32_t *sint_ptr = (s32_t*)value; + if (*sint_ptr == 1 || *sint_ptr == 2) + set_ok = 1; + } + break; + } + return set_ok; +} + +static void +ifentry_set_value(struct obj_def *od, u16_t len, void *value) +{ + struct netif *netif; + u8_t id; + LWIP_UNUSED_ARG(len); + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 7: /* ifAdminStatus */ + { + s32_t *sint_ptr = (s32_t*)value; + if (*sint_ptr == 1) + { + netif_set_up(netif); + } + else if (*sint_ptr == 2) + { + netif_set_down(netif); + } + } + break; + } +} +#endif /* SNMP_SAFE_REQUESTS */ + +/** + * Returns atentry object definitions. + * + * @param ident_len the address length (6) + * @param ident points to objectname.atifindex.atnetaddress + * @param od points to object definition. + */ +static void +atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (5) */ + ident_len += 5; + ident -= 5; + + if (ident_len == 6) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + switch (ident[0]) + { + case 1: /* atIfIndex */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* atPhysAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = 6; /** @todo try to use netif::hwaddr_len */ + break; + case 3: /* atNetAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +atentry_get_value(struct obj_def *od, u16_t len, void *value) +{ +#if LWIP_ARP + u8_t id; + struct eth_addr* ethaddr_ret; + ip_addr_t* ipaddr_ret; +#endif /* LWIP_ARP */ + ip_addr_t ip; + struct netif *netif; + + LWIP_UNUSED_ARG(len); + LWIP_UNUSED_ARG(value);/* if !LWIP_ARP */ + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + snmp_oidtoip(&od->id_inst_ptr[2], &ip); + +#if LWIP_ARP /** @todo implement a netif_find_addr */ + if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1) + { + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* atIfIndex */ + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = od->id_inst_ptr[1]; + } + break; + case 2: /* atPhysAddress */ + { + struct eth_addr *dst = (struct eth_addr*)value; + + *dst = *ethaddr_ret; + } + break; + case 3: /* atNetAddress */ + { + ip_addr_t *dst = (ip_addr_t*)value; + + *dst = *ipaddr_ret; + } + break; + } + } +#endif /* LWIP_ARP */ +} + +static void +ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff)); + id = (u8_t)ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ip.%"U16_F".0\n",(u16_t)id)); + switch (id) + { + case 1: /* ipForwarding */ + case 2: /* ipDefaultTTL */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 3: /* ipInReceives */ + case 4: /* ipInHdrErrors */ + case 5: /* ipInAddrErrors */ + case 6: /* ipForwDatagrams */ + case 7: /* ipInUnknownProtos */ + case 8: /* ipInDiscards */ + case 9: /* ipInDelivers */ + case 10: /* ipOutRequests */ + case 11: /* ipOutDiscards */ + case 12: /* ipOutNoRoutes */ + case 14: /* ipReasmReqds */ + case 15: /* ipReasmOKs */ + case 16: /* ipReasmFails */ + case 17: /* ipFragOKs */ + case 18: /* ipFragFails */ + case 19: /* ipFragCreates */ + case 23: /* ipRoutingDiscards */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 13: /* ipReasmTimeout */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + LWIP_UNUSED_ARG(len); + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipForwarding */ + { + s32_t *sint_ptr = (s32_t*)value; +#if IP_FORWARD + /* forwarding */ + *sint_ptr = 1; +#else + /* not-forwarding */ + *sint_ptr = 2; +#endif + } + break; + case 2: /* ipDefaultTTL */ + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = IP_DEFAULT_TTL; + } + break; + case 3: /* ipInReceives */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipinreceives; + } + break; + case 4: /* ipInHdrErrors */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipinhdrerrors; + } + break; + case 5: /* ipInAddrErrors */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipinaddrerrors; + } + break; + case 6: /* ipForwDatagrams */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipforwdatagrams; + } + break; + case 7: /* ipInUnknownProtos */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipinunknownprotos; + } + break; + case 8: /* ipInDiscards */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipindiscards; + } + break; + case 9: /* ipInDelivers */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipindelivers; + } + break; + case 10: /* ipOutRequests */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipoutrequests; + } + break; + case 11: /* ipOutDiscards */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipoutdiscards; + } + break; + case 12: /* ipOutNoRoutes */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipoutnoroutes; + } + break; + case 13: /* ipReasmTimeout */ + { + s32_t *sint_ptr = (s32_t*)value; +#if IP_REASSEMBLY + *sint_ptr = IP_REASS_MAXAGE; +#else + *sint_ptr = 0; +#endif + } + break; + case 14: /* ipReasmReqds */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipreasmreqds; + } + break; + case 15: /* ipReasmOKs */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipreasmoks; + } + break; + case 16: /* ipReasmFails */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipreasmfails; + } + break; + case 17: /* ipFragOKs */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipfragoks; + } + break; + case 18: /* ipFragFails */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipfragfails; + } + break; + case 19: /* ipFragCreates */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = ipfragcreates; + } + break; + case 23: /* ipRoutingDiscards */ + /** @todo can lwIP discard routes at all?? hardwire this to 0?? */ + { + u32_t *uint_ptr = (u32_t*)value; + *uint_ptr = iproutingdiscards; + } + break; + }; +} + +/** + * Test ip object value before setting. + * + * @param od is the object definition + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value from. + * + * @note we allow set if the value matches the hardwired value, + * otherwise return badvalue. + */ +static u8_t +ip_set_test(struct obj_def *od, u16_t len, void *value) +{ + u8_t id, set_ok; + s32_t *sint_ptr = (s32_t*)value; + + LWIP_UNUSED_ARG(len); + set_ok = 0; + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipForwarding */ +#if IP_FORWARD + /* forwarding */ + if (*sint_ptr == 1) +#else + /* not-forwarding */ + if (*sint_ptr == 2) +#endif + { + set_ok = 1; + } + break; + case 2: /* ipDefaultTTL */ + if (*sint_ptr == IP_DEFAULT_TTL) + { + set_ok = 1; + } + break; + }; + return set_ok; +} + +static void +ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (4) */ + ident_len += 4; + ident -= 4; + + if (ident_len == 5) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff)); + id = (u8_t)ident[0]; + switch (id) + { + case 1: /* ipAdEntAddr */ + case 3: /* ipAdEntNetMask */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 2: /* ipAdEntIfIndex */ + case 4: /* ipAdEntBcastAddr */ + case 5: /* ipAdEntReasmMaxSize */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + u16_t ifidx; + ip_addr_t ip; + struct netif *netif = netif_list; + + LWIP_UNUSED_ARG(len); + snmp_oidtoip(&od->id_inst_ptr[1], &ip); + ifidx = 0; + while ((netif != NULL) && !ip_addr_cmp(&ip, &netif->ip_addr)) + { + netif = netif->next; + ifidx++; + } + + if (netif != NULL) + { + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipAdEntAddr */ + { + ip_addr_t *dst = (ip_addr_t*)value; + *dst = netif->ip_addr; + } + break; + case 2: /* ipAdEntIfIndex */ + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = ifidx + 1; + } + break; + case 3: /* ipAdEntNetMask */ + { + ip_addr_t *dst = (ip_addr_t*)value; + *dst = netif->netmask; + } + break; + case 4: /* ipAdEntBcastAddr */ + { + s32_t *sint_ptr = (s32_t*)value; + + /* lwIP oddity, there's no broadcast + address in the netif we can rely on */ + *sint_ptr = IPADDR_BROADCAST & 1; + } + break; + case 5: /* ipAdEntReasmMaxSize */ + { + s32_t *sint_ptr = (s32_t*)value; +#if IP_REASSEMBLY + /* @todo The theoretical maximum is IP_REASS_MAX_PBUFS * size of the pbufs, + * but only if receiving one fragmented packet at a time. + * The current solution is to calculate for 2 simultaneous packets... + */ + *sint_ptr = (IP_HLEN + ((IP_REASS_MAX_PBUFS/2) * + (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN - IP_HLEN))); +#else + /** @todo returning MTU would be a bad thing and + returning a wild guess like '576' isn't good either */ + *sint_ptr = 0; +#endif + } + break; + } + } +} + +/** + * @note + * lwIP IP routing is currently using the network addresses in netif_list. + * if no suitable network IP is found in netif_list, the default_netif is used. + */ +static void +ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (4) */ + ident_len += 4; + ident -= 4; + + if (ident_len == 5) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff)); + id = (u8_t)ident[0]; + switch (id) + { + case 1: /* ipRouteDest */ + case 7: /* ipRouteNextHop */ + case 11: /* ipRouteMask */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 2: /* ipRouteIfIndex */ + case 3: /* ipRouteMetric1 */ + case 4: /* ipRouteMetric2 */ + case 5: /* ipRouteMetric3 */ + case 6: /* ipRouteMetric4 */ + case 8: /* ipRouteType */ + case 10: /* ipRouteAge */ + case 12: /* ipRouteMetric5 */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 9: /* ipRouteProto */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 13: /* ipRouteInfo */ + /** @note returning zeroDotZero (0.0) no routing protocol specific MIB */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); + od->v_len = iprouteinfo.len * sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + struct netif *netif; + ip_addr_t dest; + s32_t *ident; + u8_t id; + + ident = od->id_inst_ptr; + snmp_oidtoip(&ident[1], &dest); + + if (ip_addr_isany(&dest)) + { + /* ip_route() uses default netif for default route */ + netif = netif_default; + } + else + { + /* not using ip_route(), need exact match! */ + netif = netif_list; + while ((netif != NULL) && + !ip_addr_netcmp(&dest, &(netif->ip_addr), &(netif->netmask)) ) + { + netif = netif->next; + } + } + if (netif != NULL) + { + LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff)); + id = (u8_t)ident[0]; + switch (id) + { + case 1: /* ipRouteDest */ + { + ip_addr_t *dst = (ip_addr_t*)value; + + if (ip_addr_isany(&dest)) + { + /* default rte has 0.0.0.0 dest */ + ip_addr_set_zero(dst); + } + else + { + /* netifs have netaddress dest */ + ip_addr_get_network(dst, &netif->ip_addr, &netif->netmask); + } + } + break; + case 2: /* ipRouteIfIndex */ + { + s32_t *sint_ptr = (s32_t*)value; + + snmp_netiftoifindex(netif, sint_ptr); + } + break; + case 3: /* ipRouteMetric1 */ + { + s32_t *sint_ptr = (s32_t*)value; + + if (ip_addr_isany(&dest)) + { + /* default rte has metric 1 */ + *sint_ptr = 1; + } + else + { + /* other rtes have metric 0 */ + *sint_ptr = 0; + } + } + break; + case 4: /* ipRouteMetric2 */ + case 5: /* ipRouteMetric3 */ + case 6: /* ipRouteMetric4 */ + case 12: /* ipRouteMetric5 */ + { + s32_t *sint_ptr = (s32_t*)value; + /* not used */ + *sint_ptr = -1; + } + break; + case 7: /* ipRouteNextHop */ + { + ip_addr_t *dst = (ip_addr_t*)value; + + if (ip_addr_isany(&dest)) + { + /* default rte: gateway */ + *dst = netif->gw; + } + else + { + /* other rtes: netif ip_addr */ + *dst = netif->ip_addr; + } + } + break; + case 8: /* ipRouteType */ + { + s32_t *sint_ptr = (s32_t*)value; + + if (ip_addr_isany(&dest)) + { + /* default rte is indirect */ + *sint_ptr = 4; + } + else + { + /* other rtes are direct */ + *sint_ptr = 3; + } + } + break; + case 9: /* ipRouteProto */ + { + s32_t *sint_ptr = (s32_t*)value; + /* locally defined routes */ + *sint_ptr = 2; + } + break; + case 10: /* ipRouteAge */ + { + s32_t *sint_ptr = (s32_t*)value; + /** @todo (sysuptime - timestamp last change) / 100 + @see snmp_insert_iprteidx_tree() */ + *sint_ptr = 0; + } + break; + case 11: /* ipRouteMask */ + { + ip_addr_t *dst = (ip_addr_t*)value; + + if (ip_addr_isany(&dest)) + { + /* default rte use 0.0.0.0 mask */ + ip_addr_set_zero(dst); + } + else + { + /* other rtes use netmask */ + *dst = netif->netmask; + } + } + break; + case 13: /* ipRouteInfo */ + objectidncpy((s32_t*)value, (s32_t*)iprouteinfo.id, (u8_t)(len / sizeof(s32_t))); + break; + } + } +} + +static void +ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (5) */ + ident_len += 5; + ident -= 5; + + if (ident_len == 6) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff)); + id = (u8_t)ident[0]; + switch (id) + { + case 1: /* ipNetToMediaIfIndex */ + case 4: /* ipNetToMediaType */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* ipNetToMediaPhysAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = 6; /** @todo try to use netif::hwaddr_len */ + break; + case 3: /* ipNetToMediaNetAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value) +{ +#if LWIP_ARP + u8_t id; + struct eth_addr* ethaddr_ret; + ip_addr_t* ipaddr_ret; +#endif /* LWIP_ARP */ + ip_addr_t ip; + struct netif *netif; + + LWIP_UNUSED_ARG(len); + LWIP_UNUSED_ARG(value);/* if !LWIP_ARP */ + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + snmp_oidtoip(&od->id_inst_ptr[2], &ip); + +#if LWIP_ARP /** @todo implement a netif_find_addr */ + if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1) + { + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipNetToMediaIfIndex */ + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = od->id_inst_ptr[1]; + } + break; + case 2: /* ipNetToMediaPhysAddress */ + { + struct eth_addr *dst = (struct eth_addr*)value; + + *dst = *ethaddr_ret; + } + break; + case 3: /* ipNetToMediaNetAddress */ + { + ip_addr_t *dst = (ip_addr_t*)value; + + *dst = *ipaddr_ret; + } + break; + case 4: /* ipNetToMediaType */ + { + s32_t *sint_ptr = (s32_t*)value; + /* dynamic (?) */ + *sint_ptr = 3; + } + break; + } + } +#endif /* LWIP_ARP */ +} + +static void +icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if ((ident_len == 2) && + (ident[0] > 0) && (ident[0] < 27)) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("icmp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +icmp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = (u32_t*)value; + u8_t id; + + LWIP_UNUSED_ARG(len); + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* icmpInMsgs */ + *uint_ptr = icmpinmsgs; + break; + case 2: /* icmpInErrors */ + *uint_ptr = icmpinerrors; + break; + case 3: /* icmpInDestUnreachs */ + *uint_ptr = icmpindestunreachs; + break; + case 4: /* icmpInTimeExcds */ + *uint_ptr = icmpintimeexcds; + break; + case 5: /* icmpInParmProbs */ + *uint_ptr = icmpinparmprobs; + break; + case 6: /* icmpInSrcQuenchs */ + *uint_ptr = icmpinsrcquenchs; + break; + case 7: /* icmpInRedirects */ + *uint_ptr = icmpinredirects; + break; + case 8: /* icmpInEchos */ + *uint_ptr = icmpinechos; + break; + case 9: /* icmpInEchoReps */ + *uint_ptr = icmpinechoreps; + break; + case 10: /* icmpInTimestamps */ + *uint_ptr = icmpintimestamps; + break; + case 11: /* icmpInTimestampReps */ + *uint_ptr = icmpintimestampreps; + break; + case 12: /* icmpInAddrMasks */ + *uint_ptr = icmpinaddrmasks; + break; + case 13: /* icmpInAddrMaskReps */ + *uint_ptr = icmpinaddrmaskreps; + break; + case 14: /* icmpOutMsgs */ + *uint_ptr = icmpoutmsgs; + break; + case 15: /* icmpOutErrors */ + *uint_ptr = icmpouterrors; + break; + case 16: /* icmpOutDestUnreachs */ + *uint_ptr = icmpoutdestunreachs; + break; + case 17: /* icmpOutTimeExcds */ + *uint_ptr = icmpouttimeexcds; + break; + case 18: /* icmpOutParmProbs */ + *uint_ptr = icmpoutparmprobs; + break; + case 19: /* icmpOutSrcQuenchs */ + *uint_ptr = icmpoutsrcquenchs; + break; + case 20: /* icmpOutRedirects */ + *uint_ptr = icmpoutredirects; + break; + case 21: /* icmpOutEchos */ + *uint_ptr = icmpoutechos; + break; + case 22: /* icmpOutEchoReps */ + *uint_ptr = icmpoutechoreps; + break; + case 23: /* icmpOutTimestamps */ + *uint_ptr = icmpouttimestamps; + break; + case 24: /* icmpOutTimestampReps */ + *uint_ptr = icmpouttimestampreps; + break; + case 25: /* icmpOutAddrMasks */ + *uint_ptr = icmpoutaddrmasks; + break; + case 26: /* icmpOutAddrMaskReps */ + *uint_ptr = icmpoutaddrmaskreps; + break; + } +} + +#if LWIP_TCP +/** @todo tcp grp */ +static void +tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff)); + id = (u8_t)ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id)); + + switch (id) + { + case 1: /* tcpRtoAlgorithm */ + case 2: /* tcpRtoMin */ + case 3: /* tcpRtoMax */ + case 4: /* tcpMaxConn */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 5: /* tcpActiveOpens */ + case 6: /* tcpPassiveOpens */ + case 7: /* tcpAttemptFails */ + case 8: /* tcpEstabResets */ + case 10: /* tcpInSegs */ + case 11: /* tcpOutSegs */ + case 12: /* tcpRetransSegs */ + case 14: /* tcpInErrs */ + case 15: /* tcpOutRsts */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 9: /* tcpCurrEstab */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE); + od->v_len = sizeof(u32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +tcp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = (u32_t*)value; + s32_t *sint_ptr = (s32_t*)value; + u8_t id; + + LWIP_UNUSED_ARG(len); + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* tcpRtoAlgorithm, vanj(4) */ + *sint_ptr = 4; + break; + case 2: /* tcpRtoMin */ + /* @todo not the actual value, a guess, + needs to be calculated */ + *sint_ptr = 1000; + break; + case 3: /* tcpRtoMax */ + /* @todo not the actual value, a guess, + needs to be calculated */ + *sint_ptr = 60000; + break; + case 4: /* tcpMaxConn */ + *sint_ptr = MEMP_NUM_TCP_PCB; + break; + case 5: /* tcpActiveOpens */ + *uint_ptr = tcpactiveopens; + break; + case 6: /* tcpPassiveOpens */ + *uint_ptr = tcppassiveopens; + break; + case 7: /* tcpAttemptFails */ + *uint_ptr = tcpattemptfails; + break; + case 8: /* tcpEstabResets */ + *uint_ptr = tcpestabresets; + break; + case 9: /* tcpCurrEstab */ + { + u16_t tcpcurrestab = 0; + struct tcp_pcb *pcb = tcp_active_pcbs; + while (pcb != NULL) + { + if ((pcb->state == ESTABLISHED) || + (pcb->state == CLOSE_WAIT)) + { + tcpcurrestab++; + } + pcb = pcb->next; + } + *uint_ptr = tcpcurrestab; + } + break; + case 10: /* tcpInSegs */ + *uint_ptr = tcpinsegs; + break; + case 11: /* tcpOutSegs */ + *uint_ptr = tcpoutsegs; + break; + case 12: /* tcpRetransSegs */ + *uint_ptr = tcpretranssegs; + break; + case 14: /* tcpInErrs */ + *uint_ptr = tcpinerrs; + break; + case 15: /* tcpOutRsts */ + *uint_ptr = tcpoutrsts; + break; + } +} +#ifdef THIS_SEEMS_UNUSED +static void +tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (10) */ + ident_len += 10; + ident -= 10; + + if (ident_len == 11) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id)); + + switch (id) + { + case 1: /* tcpConnState */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* tcpConnLocalAddress */ + case 4: /* tcpConnRemAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 3: /* tcpConnLocalPort */ + case 5: /* tcpConnRemPort */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + ip_addr_t lip, rip; + u16_t lport, rport; + s32_t *ident; + + ident = od->id_inst_ptr; + snmp_oidtoip(&ident[1], &lip); + lport = ident[5]; + snmp_oidtoip(&ident[6], &rip); + rport = ident[10]; + + /** @todo find matching PCB */ +} +#endif /* if 0 */ +#endif + +static void +udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if ((ident_len == 2) && + (ident[0] > 0) && (ident[0] < 6)) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("udp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +udp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = (u32_t*)value; + u8_t id; + + LWIP_UNUSED_ARG(len); + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* udpInDatagrams */ + *uint_ptr = udpindatagrams; + break; + case 2: /* udpNoPorts */ + *uint_ptr = udpnoports; + break; + case 3: /* udpInErrors */ + *uint_ptr = udpinerrors; + break; + case 4: /* udpOutDatagrams */ + *uint_ptr = udpoutdatagrams; + break; + } +} + +static void +udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (5) */ + ident_len += 5; + ident -= 5; + + if (ident_len == 6) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + switch (ident[0]) + { + case 1: /* udpLocalAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 2: /* udpLocalPort */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +udpentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + struct udp_pcb *pcb; + ip_addr_t ip; + u16_t port; + + LWIP_UNUSED_ARG(len); + snmp_oidtoip(&od->id_inst_ptr[1], &ip); + LWIP_ASSERT("invalid port", (od->id_inst_ptr[5] >= 0) && (od->id_inst_ptr[5] <= 0xffff)); + port = (u16_t)od->id_inst_ptr[5]; + + pcb = udp_pcbs; + while ((pcb != NULL) && + !(ip_addr_cmp(&pcb->local_ip, &ip) && + (pcb->local_port == port))) + { + pcb = pcb->next; + } + + if (pcb != NULL) + { + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* udpLocalAddress */ + { + ip_addr_t *dst = (ip_addr_t*)value; + *dst = pcb->local_ip; + } + break; + case 2: /* udpLocalPort */ + { + s32_t *sint_ptr = (s32_t*)value; + *sint_ptr = pcb->local_port; + } + break; + } + } +} + +static void +snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff)); + id = (u8_t)ident[0]; + switch (id) + { + case 1: /* snmpInPkts */ + case 2: /* snmpOutPkts */ + case 3: /* snmpInBadVersions */ + case 4: /* snmpInBadCommunityNames */ + case 5: /* snmpInBadCommunityUses */ + case 6: /* snmpInASNParseErrs */ + case 8: /* snmpInTooBigs */ + case 9: /* snmpInNoSuchNames */ + case 10: /* snmpInBadValues */ + case 11: /* snmpInReadOnlys */ + case 12: /* snmpInGenErrs */ + case 13: /* snmpInTotalReqVars */ + case 14: /* snmpInTotalSetVars */ + case 15: /* snmpInGetRequests */ + case 16: /* snmpInGetNexts */ + case 17: /* snmpInSetRequests */ + case 18: /* snmpInGetResponses */ + case 19: /* snmpInTraps */ + case 20: /* snmpOutTooBigs */ + case 21: /* snmpOutNoSuchNames */ + case 22: /* snmpOutBadValues */ + case 24: /* snmpOutGenErrs */ + case 25: /* snmpOutGetRequests */ + case 26: /* snmpOutGetNexts */ + case 27: /* snmpOutSetRequests */ + case 28: /* snmpOutGetResponses */ + case 29: /* snmpOutTraps */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 30: /* snmpEnableAuthenTraps */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +snmp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = (u32_t*)value; + u8_t id; + + LWIP_UNUSED_ARG(len); + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + switch (id) + { + case 1: /* snmpInPkts */ + *uint_ptr = snmpinpkts; + break; + case 2: /* snmpOutPkts */ + *uint_ptr = snmpoutpkts; + break; + case 3: /* snmpInBadVersions */ + *uint_ptr = snmpinbadversions; + break; + case 4: /* snmpInBadCommunityNames */ + *uint_ptr = snmpinbadcommunitynames; + break; + case 5: /* snmpInBadCommunityUses */ + *uint_ptr = snmpinbadcommunityuses; + break; + case 6: /* snmpInASNParseErrs */ + *uint_ptr = snmpinasnparseerrs; + break; + case 8: /* snmpInTooBigs */ + *uint_ptr = snmpintoobigs; + break; + case 9: /* snmpInNoSuchNames */ + *uint_ptr = snmpinnosuchnames; + break; + case 10: /* snmpInBadValues */ + *uint_ptr = snmpinbadvalues; + break; + case 11: /* snmpInReadOnlys */ + *uint_ptr = snmpinreadonlys; + break; + case 12: /* snmpInGenErrs */ + *uint_ptr = snmpingenerrs; + break; + case 13: /* snmpInTotalReqVars */ + *uint_ptr = snmpintotalreqvars; + break; + case 14: /* snmpInTotalSetVars */ + *uint_ptr = snmpintotalsetvars; + break; + case 15: /* snmpInGetRequests */ + *uint_ptr = snmpingetrequests; + break; + case 16: /* snmpInGetNexts */ + *uint_ptr = snmpingetnexts; + break; + case 17: /* snmpInSetRequests */ + *uint_ptr = snmpinsetrequests; + break; + case 18: /* snmpInGetResponses */ + *uint_ptr = snmpingetresponses; + break; + case 19: /* snmpInTraps */ + *uint_ptr = snmpintraps; + break; + case 20: /* snmpOutTooBigs */ + *uint_ptr = snmpouttoobigs; + break; + case 21: /* snmpOutNoSuchNames */ + *uint_ptr = snmpoutnosuchnames; + break; + case 22: /* snmpOutBadValues */ + *uint_ptr = snmpoutbadvalues; + break; + case 24: /* snmpOutGenErrs */ + *uint_ptr = snmpoutgenerrs; + break; + case 25: /* snmpOutGetRequests */ + *uint_ptr = snmpoutgetrequests; + break; + case 26: /* snmpOutGetNexts */ + *uint_ptr = snmpoutgetnexts; + break; + case 27: /* snmpOutSetRequests */ + *uint_ptr = snmpoutsetrequests; + break; + case 28: /* snmpOutGetResponses */ + *uint_ptr = snmpoutgetresponses; + break; + case 29: /* snmpOutTraps */ + *uint_ptr = snmpouttraps; + break; + case 30: /* snmpEnableAuthenTraps */ + *uint_ptr = *snmpenableauthentraps_ptr; + break; + }; +} + +/** + * Test snmp object value before setting. + * + * @param od is the object definition + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value from. + */ +static u8_t +snmp_set_test(struct obj_def *od, u16_t len, void *value) +{ + u8_t id, set_ok; + + LWIP_UNUSED_ARG(len); + set_ok = 0; + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + if (id == 30) + { + /* snmpEnableAuthenTraps */ + s32_t *sint_ptr = (s32_t*)value; + + if (snmpenableauthentraps_ptr != &snmpenableauthentraps_default) + { + /* we should have writable non-volatile mem here */ + if ((*sint_ptr == 1) || (*sint_ptr == 2)) + { + set_ok = 1; + } + } + else + { + /* const or hardwired value */ + if (*sint_ptr == snmpenableauthentraps_default) + { + set_ok = 1; + } + } + } + return set_ok; +} + +static void +snmp_set_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + LWIP_UNUSED_ARG(len); + LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff)); + id = (u8_t)od->id_inst_ptr[0]; + if (id == 30) + { + /* snmpEnableAuthenTraps */ + /* @todo @fixme: which kind of pointer is 'value'? s32_t or u8_t??? */ + u8_t *ptr = (u8_t*)value; + *snmpenableauthentraps_ptr = *ptr; + } +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/mib_structs.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/mib_structs.c new file mode 100644 index 0000000..2f185cb --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/mib_structs.c @@ -0,0 +1,1174 @@ +/** + * @file + * MIB tree access/construction functions. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/snmp_structs.h" +#include "lwip/memp.h" +#include "lwip/netif.h" + +/** .iso.org.dod.internet address prefix, @see snmp_iso_*() */ +const s32_t prefix[4] = {1, 3, 6, 1}; + +#define NODE_STACK_SIZE (LWIP_SNMP_OBJ_ID_LEN) +/** node stack entry (old news?) */ +struct nse +{ + /** right child */ + struct mib_node* r_ptr; + /** right child identifier */ + s32_t r_id; + /** right child next level */ + u8_t r_nl; +}; +static u8_t node_stack_cnt; +static struct nse node_stack[NODE_STACK_SIZE]; + +/** + * Pushes nse struct onto stack. + */ +static void +push_node(struct nse* node) +{ + LWIP_ASSERT("node_stack_cnt < NODE_STACK_SIZE",node_stack_cnt < NODE_STACK_SIZE); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("push_node() node=%p id=%"S32_F"\n",(void*)(node->r_ptr),node->r_id)); + if (node_stack_cnt < NODE_STACK_SIZE) + { + node_stack[node_stack_cnt] = *node; + node_stack_cnt++; + } +} + +/** + * Pops nse struct from stack. + */ +static void +pop_node(struct nse* node) +{ + if (node_stack_cnt > 0) + { + node_stack_cnt--; + *node = node_stack[node_stack_cnt]; + } + LWIP_DEBUGF(SNMP_MIB_DEBUG,("pop_node() node=%p id=%"S32_F"\n",(void *)(node->r_ptr),node->r_id)); +} + +/** + * Conversion from ifIndex to lwIP netif + * @param ifindex is a s32_t object sub-identifier + * @param netif points to returned netif struct pointer + */ +void +snmp_ifindextonetif(s32_t ifindex, struct netif **netif) +{ + struct netif *nif = netif_list; + s32_t i, ifidx; + + ifidx = ifindex - 1; + i = 0; + while ((nif != NULL) && (i < ifidx)) + { + nif = nif->next; + i++; + } + *netif = nif; +} + +/** + * Conversion from lwIP netif to ifIndex + * @param netif points to a netif struct + * @param ifidx points to s32_t object sub-identifier + */ +void +snmp_netiftoifindex(struct netif *netif, s32_t *ifidx) +{ + struct netif *nif = netif_list; + u16_t i; + + i = 0; + while ((nif != NULL) && (nif != netif)) + { + nif = nif->next; + i++; + } + *ifidx = i+1; +} + +/** + * Conversion from oid to lwIP ip_addr + * @param ident points to s32_t ident[4] input + * @param ip points to output struct + */ +void +snmp_oidtoip(s32_t *ident, ip_addr_t *ip) +{ + IP4_ADDR(ip, ident[0], ident[1], ident[2], ident[3]); +} + +/** + * Conversion from lwIP ip_addr to oid + * @param ip points to input struct + * @param ident points to s32_t ident[4] output + */ +void +snmp_iptooid(ip_addr_t *ip, s32_t *ident) +{ + ident[0] = ip4_addr1(ip); + ident[1] = ip4_addr2(ip); + ident[2] = ip4_addr3(ip); + ident[3] = ip4_addr4(ip); +} + +struct mib_list_node * +snmp_mib_ln_alloc(s32_t id) +{ + struct mib_list_node *ln; + + ln = (struct mib_list_node *)memp_malloc(MEMP_SNMP_NODE); + if (ln != NULL) + { + ln->prev = NULL; + ln->next = NULL; + ln->objid = id; + ln->nptr = NULL; + } + return ln; +} + +void +snmp_mib_ln_free(struct mib_list_node *ln) +{ + memp_free(MEMP_SNMP_NODE, ln); +} + +struct mib_list_rootnode * +snmp_mib_lrn_alloc(void) +{ + struct mib_list_rootnode *lrn; + + lrn = (struct mib_list_rootnode*)memp_malloc(MEMP_SNMP_ROOTNODE); + if (lrn != NULL) + { + lrn->get_object_def = noleafs_get_object_def; + lrn->get_value = noleafs_get_value; + lrn->set_test = noleafs_set_test; + lrn->set_value = noleafs_set_value; + lrn->node_type = MIB_NODE_LR; + lrn->maxlength = 0; + lrn->head = NULL; + lrn->tail = NULL; + lrn->count = 0; + } + return lrn; +} + +void +snmp_mib_lrn_free(struct mib_list_rootnode *lrn) +{ + memp_free(MEMP_SNMP_ROOTNODE, lrn); +} + +/** + * Inserts node in idx list in a sorted + * (ascending order) fashion and + * allocates the node if needed. + * + * @param rn points to the root node + * @param objid is the object sub identifier + * @param insn points to a pointer to the inserted node + * used for constructing the tree. + * @return -1 if failed, 1 if inserted, 2 if present. + */ +s8_t +snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn) +{ + struct mib_list_node *nn; + s8_t insert; + + LWIP_ASSERT("rn != NULL",rn != NULL); + + /* -1 = malloc failure, 0 = not inserted, 1 = inserted, 2 = was present */ + insert = 0; + if (rn->head == NULL) + { + /* empty list, add first node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc empty list objid==%"S32_F"\n",objid)); + nn = snmp_mib_ln_alloc(objid); + if (nn != NULL) + { + rn->head = nn; + rn->tail = nn; + *insn = nn; + insert = 1; + } + else + { + insert = -1; + } + } + else + { + struct mib_list_node *n; + /* at least one node is present */ + n = rn->head; + while ((n != NULL) && (insert == 0)) + { + if (n->objid == objid) + { + /* node is already there */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("node already there objid==%"S32_F"\n",objid)); + *insn = n; + insert = 2; + } + else if (n->objid < objid) + { + if (n->next == NULL) + { + /* alloc and insert at the tail */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins tail objid==%"S32_F"\n",objid)); + nn = snmp_mib_ln_alloc(objid); + if (nn != NULL) + { + nn->next = NULL; + nn->prev = n; + n->next = nn; + rn->tail = nn; + *insn = nn; + insert = 1; + } + else + { + /* insertion failure */ + insert = -1; + } + } + else + { + /* there's more to explore: traverse list */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("traverse list\n")); + n = n->next; + } + } + else + { + /* n->objid > objid */ + /* alloc and insert between n->prev and n */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins n->prev, objid==%"S32_F", n\n",objid)); + nn = snmp_mib_ln_alloc(objid); + if (nn != NULL) + { + if (n->prev == NULL) + { + /* insert at the head */ + nn->next = n; + nn->prev = NULL; + rn->head = nn; + n->prev = nn; + } + else + { + /* insert in the middle */ + nn->next = n; + nn->prev = n->prev; + n->prev->next = nn; + n->prev = nn; + } + *insn = nn; + insert = 1; + } + else + { + /* insertion failure */ + insert = -1; + } + } + } + } + if (insert == 1) + { + rn->count += 1; + } + LWIP_ASSERT("insert != 0",insert != 0); + return insert; +} + +/** + * Finds node in idx list and returns deletion mark. + * + * @param rn points to the root node + * @param objid is the object sub identifier + * @param fn returns pointer to found node + * @return 0 if not found, 1 if deletable, + * 2 can't delete (2 or more children), 3 not a list_node + */ +s8_t +snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn) +{ + s8_t fc; + struct mib_list_node *n; + + LWIP_ASSERT("rn != NULL",rn != NULL); + n = rn->head; + while ((n != NULL) && (n->objid != objid)) + { + n = n->next; + } + if (n == NULL) + { + fc = 0; + } + else if (n->nptr == NULL) + { + /* leaf, can delete node */ + fc = 1; + } + else + { + struct mib_list_rootnode *r; + + if (n->nptr->node_type == MIB_NODE_LR) + { + r = (struct mib_list_rootnode *)n->nptr; + if (r->count > 1) + { + /* can't delete node */ + fc = 2; + } + else + { + /* count <= 1, can delete node */ + fc = 1; + } + } + else + { + /* other node type */ + fc = 3; + } + } + *fn = n; + return fc; +} + +/** + * Removes node from idx list + * if it has a single child left. + * + * @param rn points to the root node + * @param n points to the node to delete + * @return the nptr to be freed by caller + */ +struct mib_list_rootnode * +snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n) +{ + struct mib_list_rootnode *next; + + LWIP_ASSERT("rn != NULL",rn != NULL); + LWIP_ASSERT("n != NULL",n != NULL); + + /* caller must remove this sub-tree */ + next = (struct mib_list_rootnode*)(n->nptr); + rn->count -= 1; + + if (n == rn->head) + { + rn->head = n->next; + if (n->next != NULL) + { + /* not last node, new list begin */ + n->next->prev = NULL; + } + } + else if (n == rn->tail) + { + rn->tail = n->prev; + if (n->prev != NULL) + { + /* not last node, new list end */ + n->prev->next = NULL; + } + } + else + { + /* node must be in the middle */ + n->prev->next = n->next; + n->next->prev = n->prev; + } + LWIP_DEBUGF(SNMP_MIB_DEBUG,("free list objid==%"S32_F"\n",n->objid)); + snmp_mib_ln_free(n); + if (rn->count == 0) + { + rn->head = NULL; + rn->tail = NULL; + } + return next; +} + + + +/** + * Searches tree for the supplied (scalar?) object identifier. + * + * @param node points to the root of the tree ('.internet') + * @param ident_len the length of the supplied object identifier + * @param ident points to the array of sub identifiers + * @param np points to the found object instance (return) + * @return pointer to the requested parent (!) node if success, NULL otherwise + */ +struct mib_node * +snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np) +{ + u8_t node_type, ext_level; + + ext_level = 0; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("node==%p *ident==%"S32_F"\n",(void*)node,*ident)); + while (node != NULL) + { + node_type = node->node_type; + if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) + { + struct mib_array_node *an; + u16_t i; + + if (ident_len > 0) + { + /* array node (internal ROM or RAM, fixed length) */ + an = (struct mib_array_node *)node; + i = 0; + while ((i < an->maxlength) && (an->objid[i] != *ident)) + { + i++; + } + if (i < an->maxlength) + { + /* found it, if available proceed to child, otherwise inspect leaf */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident)); + if (an->nptr[i] == NULL) + { + /* a scalar leaf OR table, + inspect remaining instance number / table index */ + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)an; + } + else + { + /* follow next child pointer */ + ident++; + ident_len--; + node = an->nptr[i]; + } + } + else + { + /* search failed, identifier mismatch (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed *ident==%"S32_F"\n",*ident)); + return NULL; + } + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed, short object identifier\n")); + return NULL; + } + } + else if(node_type == MIB_NODE_LR) + { + struct mib_list_rootnode *lrn; + struct mib_list_node *ln; + + if (ident_len > 0) + { + /* list root node (internal 'RAM', variable length) */ + lrn = (struct mib_list_rootnode *)node; + ln = lrn->head; + /* iterate over list, head to tail */ + while ((ln != NULL) && (ln->objid != *ident)) + { + ln = ln->next; + } + if (ln != NULL) + { + /* found it, proceed to child */; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident)); + if (ln->nptr == NULL) + { + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)lrn; + } + else + { + /* follow next child pointer */ + ident_len--; + ident++; + node = ln->nptr; + } + } + else + { + /* search failed */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed *ident==%"S32_F"\n",*ident)); + return NULL; + } + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed, short object identifier\n")); + return NULL; + } + } + else if(node_type == MIB_NODE_EX) + { + struct mib_external_node *en; + u16_t i, len; + + if (ident_len > 0) + { + /* external node (addressing and access via functions) */ + en = (struct mib_external_node *)node; + + i = 0; + len = en->level_length(en->addr_inf,ext_level); + while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) != 0)) + { + i++; + } + if (i < len) + { + s32_t debug_id; + + en->get_objid(en->addr_inf,ext_level,i,&debug_id); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid==%"S32_F" *ident==%"S32_F"\n",debug_id,*ident)); + if ((ext_level + 1) == en->tree_levels) + { + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)en; + } + else + { + /* found it, proceed to child */ + ident_len--; + ident++; + ext_level++; + } + } + else + { + /* search failed */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed *ident==%"S32_F"\n",*ident)); + return NULL; + } + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed, short object identifier\n")); + return NULL; + } + } + else if (node_type == MIB_NODE_SC) + { + mib_scalar_node *sn; + + sn = (mib_scalar_node *)node; + if ((ident_len == 1) && (*ident == 0)) + { + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)sn; + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed, invalid object identifier length\n")); + return NULL; + } + } + else + { + /* unknown node_type */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node_type %"U16_F" unkown\n",(u16_t)node_type)); + return NULL; + } + } + /* done, found nothing */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node==%p\n",(void*)node)); + return NULL; +} + +/** + * Test table for presence of at least one table entry. + */ +static u8_t +empty_table(struct mib_node *node) +{ + u8_t node_type; + u8_t empty = 0; + + if (node != NULL) + { + node_type = node->node_type; + if (node_type == MIB_NODE_LR) + { + struct mib_list_rootnode *lrn; + lrn = (struct mib_list_rootnode *)node; + if ((lrn->count == 0) || (lrn->head == NULL)) + { + empty = 1; + } + } + else if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) + { + struct mib_array_node *an; + an = (struct mib_array_node *)node; + if ((an->maxlength == 0) || (an->nptr == NULL)) + { + empty = 1; + } + } + else if (node_type == MIB_NODE_EX) + { + struct mib_external_node *en; + en = (struct mib_external_node *)node; + if (en->tree_levels == 0) + { + empty = 1; + } + } + } + return empty; +} + +/** + * Tree expansion. + */ +struct mib_node * +snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret) +{ + u8_t node_type, ext_level, climb_tree; + + ext_level = 0; + /* reset node stack */ + node_stack_cnt = 0; + while (node != NULL) + { + climb_tree = 0; + node_type = node->node_type; + if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) + { + struct mib_array_node *an; + u16_t i; + + /* array node (internal ROM or RAM, fixed length) */ + an = (struct mib_array_node *)node; + if (ident_len > 0) + { + i = 0; + while ((i < an->maxlength) && (an->objid[i] < *ident)) + { + i++; + } + if (i < an->maxlength) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident)); + /* add identifier to oidret */ + oidret->id[oidret->len] = an->objid[i]; + (oidret->len)++; + + if (an->nptr[i] == NULL) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n")); + /* leaf node (e.g. in a fixed size table) */ + if (an->objid[i] > *ident) + { + return (struct mib_node*)an; + } + else if ((i + 1) < an->maxlength) + { + /* an->objid[i] == *ident */ + (oidret->len)--; + oidret->id[oidret->len] = an->objid[i + 1]; + (oidret->len)++; + return (struct mib_node*)an; + } + else + { + /* (i + 1) == an->maxlength */ + (oidret->len)--; + climb_tree = 1; + } + } + else + { + u8_t j; + struct nse cur_node; + + LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n")); + /* non-leaf, store right child ptr and id */ + LWIP_ASSERT("i < 0xff", i < 0xff); + j = (u8_t)i + 1; + while ((j < an->maxlength) && (empty_table(an->nptr[j]))) + { + j++; + } + if (j < an->maxlength) + { + cur_node.r_ptr = an->nptr[j]; + cur_node.r_id = an->objid[j]; + cur_node.r_nl = 0; + } + else + { + cur_node.r_ptr = NULL; + } + push_node(&cur_node); + if (an->objid[i] == *ident) + { + ident_len--; + ident++; + } + else + { + /* an->objid[i] < *ident */ + ident_len = 0; + } + /* follow next child pointer */ + node = an->nptr[i]; + } + } + else + { + /* i == an->maxlength */ + climb_tree = 1; + } + } + else + { + u8_t j; + /* ident_len == 0, complete with leftmost '.thing' */ + j = 0; + while ((j < an->maxlength) && empty_table(an->nptr[j])) + { + j++; + } + if (j < an->maxlength) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("left an->objid[j]==%"S32_F"\n",an->objid[j])); + oidret->id[oidret->len] = an->objid[j]; + (oidret->len)++; + if (an->nptr[j] == NULL) + { + /* leaf node */ + return (struct mib_node*)an; + } + else + { + /* no leaf, continue */ + node = an->nptr[j]; + } + } + else + { + /* j == an->maxlength */ + climb_tree = 1; + } + } + } + else if(node_type == MIB_NODE_LR) + { + struct mib_list_rootnode *lrn; + struct mib_list_node *ln; + + /* list root node (internal 'RAM', variable length) */ + lrn = (struct mib_list_rootnode *)node; + if (ident_len > 0) + { + ln = lrn->head; + /* iterate over list, head to tail */ + while ((ln != NULL) && (ln->objid < *ident)) + { + ln = ln->next; + } + if (ln != NULL) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident)); + oidret->id[oidret->len] = ln->objid; + (oidret->len)++; + if (ln->nptr == NULL) + { + /* leaf node */ + if (ln->objid > *ident) + { + return (struct mib_node*)lrn; + } + else if (ln->next != NULL) + { + /* ln->objid == *ident */ + (oidret->len)--; + oidret->id[oidret->len] = ln->next->objid; + (oidret->len)++; + return (struct mib_node*)lrn; + } + else + { + /* ln->next == NULL */ + (oidret->len)--; + climb_tree = 1; + } + } + else + { + struct mib_list_node *jn; + struct nse cur_node; + + /* non-leaf, store right child ptr and id */ + jn = ln->next; + while ((jn != NULL) && empty_table(jn->nptr)) + { + jn = jn->next; + } + if (jn != NULL) + { + cur_node.r_ptr = jn->nptr; + cur_node.r_id = jn->objid; + cur_node.r_nl = 0; + } + else + { + cur_node.r_ptr = NULL; + } + push_node(&cur_node); + if (ln->objid == *ident) + { + ident_len--; + ident++; + } + else + { + /* ln->objid < *ident */ + ident_len = 0; + } + /* follow next child pointer */ + node = ln->nptr; + } + + } + else + { + /* ln == NULL */ + climb_tree = 1; + } + } + else + { + struct mib_list_node *jn; + /* ident_len == 0, complete with leftmost '.thing' */ + jn = lrn->head; + while ((jn != NULL) && empty_table(jn->nptr)) + { + jn = jn->next; + } + if (jn != NULL) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("left jn->objid==%"S32_F"\n",jn->objid)); + oidret->id[oidret->len] = jn->objid; + (oidret->len)++; + if (jn->nptr == NULL) + { + /* leaf node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("jn->nptr == NULL\n")); + return (struct mib_node*)lrn; + } + else + { + /* no leaf, continue */ + node = jn->nptr; + } + } + else + { + /* jn == NULL */ + climb_tree = 1; + } + } + } + else if(node_type == MIB_NODE_EX) + { + struct mib_external_node *en; + s32_t ex_id; + + /* external node (addressing and access via functions) */ + en = (struct mib_external_node *)node; + if (ident_len > 0) + { + u16_t i, len; + + i = 0; + len = en->level_length(en->addr_inf,ext_level); + while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) < 0)) + { + i++; + } + if (i < len) + { + /* add identifier to oidret */ + en->get_objid(en->addr_inf,ext_level,i,&ex_id); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,ex_id,*ident)); + oidret->id[oidret->len] = ex_id; + (oidret->len)++; + + if ((ext_level + 1) == en->tree_levels) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n")); + /* leaf node */ + if (ex_id > *ident) + { + return (struct mib_node*)en; + } + else if ((i + 1) < len) + { + /* ex_id == *ident */ + en->get_objid(en->addr_inf,ext_level,i + 1,&ex_id); + (oidret->len)--; + oidret->id[oidret->len] = ex_id; + (oidret->len)++; + return (struct mib_node*)en; + } + else + { + /* (i + 1) == len */ + (oidret->len)--; + climb_tree = 1; + } + } + else + { + u8_t j; + struct nse cur_node; + + LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n")); + /* non-leaf, store right child ptr and id */ + LWIP_ASSERT("i < 0xff", i < 0xff); + j = (u8_t)i + 1; + if (j < len) + { + /* right node is the current external node */ + cur_node.r_ptr = node; + en->get_objid(en->addr_inf,ext_level,j,&cur_node.r_id); + cur_node.r_nl = ext_level + 1; + } + else + { + cur_node.r_ptr = NULL; + } + push_node(&cur_node); + if (en->ident_cmp(en->addr_inf,ext_level,i,*ident) == 0) + { + ident_len--; + ident++; + } + else + { + /* external id < *ident */ + ident_len = 0; + } + /* proceed to child */ + ext_level++; + } + } + else + { + /* i == len (en->level_len()) */ + climb_tree = 1; + } + } + else + { + /* ident_len == 0, complete with leftmost '.thing' */ + en->get_objid(en->addr_inf,ext_level,0,&ex_id); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("left en->objid==%"S32_F"\n",ex_id)); + oidret->id[oidret->len] = ex_id; + (oidret->len)++; + if ((ext_level + 1) == en->tree_levels) + { + /* leaf node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("(ext_level + 1) == en->tree_levels\n")); + return (struct mib_node*)en; + } + else + { + /* no leaf, proceed to child */ + ext_level++; + } + } + } + else if(node_type == MIB_NODE_SC) + { + mib_scalar_node *sn; + + /* scalar node */ + sn = (mib_scalar_node *)node; + if (ident_len > 0) + { + /* at .0 */ + climb_tree = 1; + } + else + { + /* ident_len == 0, complete object identifier */ + oidret->id[oidret->len] = 0; + (oidret->len)++; + /* leaf node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("completed scalar leaf\n")); + return (struct mib_node*)sn; + } + } + else + { + /* unknown/unhandled node_type */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node_type %"U16_F" unkown\n",(u16_t)node_type)); + return NULL; + } + + if (climb_tree) + { + struct nse child; + + /* find right child ptr */ + child.r_ptr = NULL; + child.r_id = 0; + child.r_nl = 0; + while ((node_stack_cnt > 0) && (child.r_ptr == NULL)) + { + pop_node(&child); + /* trim returned oid */ + (oidret->len)--; + } + if (child.r_ptr != NULL) + { + /* incoming ident is useless beyond this point */ + ident_len = 0; + oidret->id[oidret->len] = child.r_id; + oidret->len++; + node = child.r_ptr; + ext_level = child.r_nl; + } + else + { + /* tree ends here ... */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed, tree ends here\n")); + return NULL; + } + } + } + /* done, found nothing */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node==%p\n",(void*)node)); + return NULL; +} + +/** + * Test object identifier for the iso.org.dod.internet prefix. + * + * @param ident_len the length of the supplied object identifier + * @param ident points to the array of sub identifiers + * @return 1 if it matches, 0 otherwise + */ +u8_t +snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident) +{ + if ((ident_len > 3) && + (ident[0] == 1) && (ident[1] == 3) && + (ident[2] == 6) && (ident[3] == 1)) + { + return 1; + } + else + { + return 0; + } +} + +/** + * Expands object identifier to the iso.org.dod.internet + * prefix for use in getnext operation. + * + * @param ident_len the length of the supplied object identifier + * @param ident points to the array of sub identifiers + * @param oidret points to returned expanded object identifier + * @return 1 if it matches, 0 otherwise + * + * @note ident_len 0 is allowed, expanding to the first known object id!! + */ +u8_t +snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret) +{ + const s32_t *prefix_ptr; + s32_t *ret_ptr; + u8_t i; + + i = 0; + prefix_ptr = &prefix[0]; + ret_ptr = &oidret->id[0]; + ident_len = ((ident_len < 4)?ident_len:4); + while ((i < ident_len) && ((*ident) <= (*prefix_ptr))) + { + *ret_ptr++ = *prefix_ptr++; + ident++; + i++; + } + if (i == ident_len) + { + /* match, complete missing bits */ + while (i < 4) + { + *ret_ptr++ = *prefix_ptr++; + i++; + } + oidret->len = i; + return 1; + } + else + { + /* i != ident_len */ + return 0; + } +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_in.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_in.c new file mode 100644 index 0000000..2dfb55b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_in.c @@ -0,0 +1,1437 @@ +/** + * @file + * SNMP input message processing (RFC1157). + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/snmp.h" +#include "lwip/snmp_asn1.h" +#include "lwip/snmp_msg.h" +#include "lwip/snmp_structs.h" +#include "lwip/ip_addr.h" +#include "lwip/memp.h" +#include "lwip/udp.h" +#include "lwip/stats.h" + +#include + +/* public (non-static) constants */ +/** SNMP v1 == 0 */ +const s32_t snmp_version = 0; +/** default SNMP community string */ +const char snmp_publiccommunity[7] = "public"; + +/* statically allocated buffers for SNMP_CONCURRENT_REQUESTS */ +struct snmp_msg_pstat msg_input_list[SNMP_CONCURRENT_REQUESTS]; +/* UDP Protocol Control Block */ +struct udp_pcb *snmp1_pcb; + +static void snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port); +static err_t snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat); +static err_t snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat); + + +/** + * Starts SNMP Agent. + * Allocates UDP pcb and binds it to IP_ADDR_ANY port 161. + */ +void +snmp_init(void) +{ + struct snmp_msg_pstat *msg_ps; + u8_t i; + + snmp1_pcb = udp_new(); + if (snmp1_pcb != NULL) + { + udp_recv(snmp1_pcb, snmp_recv, (void *)SNMP_IN_PORT); + udp_bind(snmp1_pcb, IP_ADDR_ANY, SNMP_IN_PORT); + } + msg_ps = &msg_input_list[0]; + for (i=0; istate = SNMP_MSG_EMPTY; + msg_ps->error_index = 0; + msg_ps->error_status = SNMP_ES_NOERROR; + msg_ps++; + } + trap_msg.pcb = snmp1_pcb; + +#ifdef SNMP_PRIVATE_MIB_INIT + /* If defined, rhis must be a function-like define to initialize the + * private MIB after the stack has been initialized. + * The private MIB can also be initialized in tcpip_callback (or after + * the stack is initialized), this define is only for convenience. */ + SNMP_PRIVATE_MIB_INIT(); +#endif /* SNMP_PRIVATE_MIB_INIT */ + + /* The coldstart trap will only be output + if our outgoing interface is up & configured */ + snmp_coldstart_trap(); +} + +static void +snmp_error_response(struct snmp_msg_pstat *msg_ps, u8_t error) +{ + snmp_varbind_list_free(&msg_ps->outvb); + msg_ps->outvb = msg_ps->invb; + msg_ps->invb.head = NULL; + msg_ps->invb.tail = NULL; + msg_ps->invb.count = 0; + msg_ps->error_status = error; + msg_ps->error_index = 1 + msg_ps->vb_idx; + snmp_send_response(msg_ps); + snmp_varbind_list_free(&msg_ps->outvb); + msg_ps->state = SNMP_MSG_EMPTY; +} + +static void +snmp_ok_response(struct snmp_msg_pstat *msg_ps) +{ + err_t err_ret; + + err_ret = snmp_send_response(msg_ps); + if (err_ret == ERR_MEM) + { + /* serious memory problem, can't return tooBig */ + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event = %"S32_F"\n",msg_ps->error_status)); + } + /* free varbinds (if available) */ + snmp_varbind_list_free(&msg_ps->invb); + snmp_varbind_list_free(&msg_ps->outvb); + msg_ps->state = SNMP_MSG_EMPTY; +} + +/** + * Service an internal or external event for SNMP GET. + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + * @param msg_ps points to the assosicated message process state + */ +static void +snmp_msg_get_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) +{ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_get_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); + + if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); + if ((msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) && + (msg_ps->ext_object_def.access & MIB_ACCESS_READ)) + { + msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE; + en->get_value_q(request_id, &msg_ps->ext_object_def); + } + else + { + en->get_object_def_pc(request_id, np.ident_len, np.ident); + /* search failed, object id points to unknown object (nosuchname) */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE) + { + struct mib_external_node *en; + struct snmp_varbind *vb; + + /* get_value() answer */ + en = msg_ps->ext_mib_node; + + /* allocate output varbind */ + vb = (struct snmp_varbind *)memp_malloc(MEMP_SNMP_VARBIND); + LWIP_ASSERT("vb != NULL",vb != NULL); + if (vb != NULL) + { + vb->next = NULL; + vb->prev = NULL; + + /* move name from invb to outvb */ + vb->ident = msg_ps->vb_ptr->ident; + vb->ident_len = msg_ps->vb_ptr->ident_len; + /* ensure this memory is refereced once only */ + msg_ps->vb_ptr->ident = NULL; + msg_ps->vb_ptr->ident_len = 0; + + vb->value_type = msg_ps->ext_object_def.asn_type; + LWIP_ASSERT("invalid length", msg_ps->ext_object_def.v_len <= 0xff); + vb->value_len = (u8_t)msg_ps->ext_object_def.v_len; + if (vb->value_len > 0) + { + LWIP_ASSERT("SNMP_MAX_OCTET_STRING_LEN is configured too low", vb->value_len <= SNMP_MAX_VALUE_SIZE); + vb->value = memp_malloc(MEMP_SNMP_VALUE); + LWIP_ASSERT("vb->value != NULL",vb->value != NULL); + if (vb->value != NULL) + { + en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + /* search again (if vb_idx < msg_ps->invb.count) */ + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + en->get_value_pc(request_id, &msg_ps->ext_object_def); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no variable space\n")); + msg_ps->vb_ptr->ident = vb->ident; + msg_ps->vb_ptr->ident_len = vb->ident_len; + memp_free(MEMP_SNMP_VARBIND, vb); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + else + { + /* vb->value_len == 0, empty value (e.g. empty string) */ + en->get_value_a(request_id, &msg_ps->ext_object_def, 0, NULL); + vb->value = NULL; + snmp_varbind_tail_add(&msg_ps->outvb, vb); + /* search again (if vb_idx < msg_ps->invb.count) */ + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + } + else + { + en->get_value_pc(request_id, &msg_ps->ext_object_def); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + + while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_name_ptr np; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + /** test object identifier for .iso.org.dod.internet prefix */ + if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident)) + { + mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &np); + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_name_ptr = np; + + en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); + } + else + { + /* internal object */ + struct obj_def object_def; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; + mn->get_object_def(np.ident_len, np.ident, &object_def); + if ((object_def.instance != MIB_OBJECT_NONE) && + (object_def.access & MIB_ACCESS_READ)) + { + mn = mn; + } + else + { + /* search failed, object id points to unknown object (nosuchname) */ + mn = NULL; + } + if (mn != NULL) + { + struct snmp_varbind *vb; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE; + /* allocate output varbind */ + vb = (struct snmp_varbind *)memp_malloc(MEMP_SNMP_VARBIND); + LWIP_ASSERT("vb != NULL",vb != NULL); + if (vb != NULL) + { + vb->next = NULL; + vb->prev = NULL; + + /* move name from invb to outvb */ + vb->ident = msg_ps->vb_ptr->ident; + vb->ident_len = msg_ps->vb_ptr->ident_len; + /* ensure this memory is refereced once only */ + msg_ps->vb_ptr->ident = NULL; + msg_ps->vb_ptr->ident_len = 0; + + vb->value_type = object_def.asn_type; + LWIP_ASSERT("invalid length", object_def.v_len <= 0xff); + vb->value_len = (u8_t)object_def.v_len; + if (vb->value_len > 0) + { + LWIP_ASSERT("SNMP_MAX_OCTET_STRING_LEN is configured too low", + vb->value_len <= SNMP_MAX_VALUE_SIZE); + vb->value = memp_malloc(MEMP_SNMP_VALUE); + LWIP_ASSERT("vb->value != NULL",vb->value != NULL); + if (vb->value != NULL) + { + mn->get_value(&object_def, vb->value_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate variable space\n")); + msg_ps->vb_ptr->ident = vb->ident; + msg_ps->vb_ptr->ident_len = vb->ident_len; + memp_free(MEMP_SNMP_VARBIND, vb); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + else + { + /* vb->value_len == 0, empty value (e.g. empty string) */ + vb->value = NULL; + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + } + } + } + else + { + mn = NULL; + } + if (mn == NULL) + { + /* mn == NULL, noSuchName */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + snmp_ok_response(msg_ps); + } +} + +/** + * Service an internal or external event for SNMP GETNEXT. + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + * @param msg_ps points to the assosicated message process state + */ +static void +snmp_msg_getnext_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) +{ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); + + if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) + { + struct mib_external_node *en; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1], &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE; + en->get_value_q(request_id, &msg_ps->ext_object_def); + } + else + { + en->get_object_def_pc(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1]); + /* search failed, object id points to unknown object (nosuchname) */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE) + { + struct mib_external_node *en; + struct snmp_varbind *vb; + + /* get_value() answer */ + en = msg_ps->ext_mib_node; + + LWIP_ASSERT("invalid length", msg_ps->ext_object_def.v_len <= 0xff); + vb = snmp_varbind_alloc(&msg_ps->ext_oid, + msg_ps->ext_object_def.asn_type, + (u8_t)msg_ps->ext_object_def.v_len); + if (vb != NULL) + { + en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + en->get_value_pc(request_id, &msg_ps->ext_object_def); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: couldn't allocate outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + + while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_obj_id oid; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + if (snmp_iso_prefix_expand(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident, &oid)) + { + if (msg_ps->vb_ptr->ident_len > 3) + { + /* can offset ident_len and ident */ + mn = snmp_expand_tree((struct mib_node*)&internet, + msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &oid); + } + else + { + /* can't offset ident_len -4, ident + 4 */ + mn = snmp_expand_tree((struct mib_node*)&internet, 0, NULL, &oid); + } + } + else + { + mn = NULL; + } + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_oid = oid; + + en->get_object_def_q(en->addr_inf, request_id, 1, &oid.id[oid.len - 1]); + } + else + { + /* internal object */ + struct obj_def object_def; + struct snmp_varbind *vb; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; + mn->get_object_def(1, &oid.id[oid.len - 1], &object_def); + + LWIP_ASSERT("invalid length", object_def.v_len <= 0xff); + vb = snmp_varbind_alloc(&oid, object_def.asn_type, (u8_t)object_def.v_len); + if (vb != NULL) + { + msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE; + mn->get_value(&object_def, object_def.v_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv couldn't allocate outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + } + if (mn == NULL) + { + /* mn == NULL, noSuchName */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + snmp_ok_response(msg_ps); + } +} + +/** + * Service an internal or external event for SNMP SET. + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + * @param msg_ps points to the assosicated message process state + */ +static void +snmp_msg_set_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) +{ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_set_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); + + if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_SET_TEST; + en->set_test_q(request_id, &msg_ps->ext_object_def); + } + else + { + en->get_object_def_pc(request_id, np.ident_len, np.ident); + /* search failed, object id points to unknown object (nosuchname) */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_TEST) + { + struct mib_external_node *en; + + /* set_test() answer*/ + en = msg_ps->ext_mib_node; + + if (msg_ps->ext_object_def.access & MIB_ACCESS_WRITE) + { + if ((msg_ps->ext_object_def.asn_type == msg_ps->vb_ptr->value_type) && + (en->set_test_a(request_id,&msg_ps->ext_object_def, + msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0)) + { + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + en->set_test_pc(request_id,&msg_ps->ext_object_def); + /* bad value */ + snmp_error_response(msg_ps,SNMP_ES_BADVALUE); + } + } + else + { + en->set_test_pc(request_id,&msg_ps->ext_object_def); + /* object not available for set */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF_S) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_SET_VALUE; + en->set_value_q(request_id, &msg_ps->ext_object_def, + msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value); + } + else + { + en->get_object_def_pc(request_id, np.ident_len, np.ident); + /* set_value failed, object has disappeared for some odd reason?? */ + snmp_error_response(msg_ps,SNMP_ES_GENERROR); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_VALUE) + { + struct mib_external_node *en; + + /** set_value_a() */ + en = msg_ps->ext_mib_node; + en->set_value_a(request_id, &msg_ps->ext_object_def, + msg_ps->vb_ptr->value_len, msg_ps->vb_ptr->value); + + /** @todo use set_value_pc() if toobig */ + msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; + msg_ps->vb_idx += 1; + } + + /* test all values before setting */ + while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_name_ptr np; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + /** test object identifier for .iso.org.dod.internet prefix */ + if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident)) + { + mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &np); + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_name_ptr = np; + + en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); + } + else + { + /* internal object */ + struct obj_def object_def; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; + mn->get_object_def(np.ident_len, np.ident, &object_def); + if (object_def.instance != MIB_OBJECT_NONE) + { + mn = mn; + } + else + { + /* search failed, object id points to unknown object (nosuchname) */ + mn = NULL; + } + if (mn != NULL) + { + msg_ps->state = SNMP_MSG_INTERNAL_SET_TEST; + + if (object_def.access & MIB_ACCESS_WRITE) + { + if ((object_def.asn_type == msg_ps->vb_ptr->value_type) && + (mn->set_test(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0)) + { + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + /* bad value */ + snmp_error_response(msg_ps,SNMP_ES_BADVALUE); + } + } + else + { + /* object not available for set */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + } + } + } + else + { + mn = NULL; + } + if (mn == NULL) + { + /* mn == NULL, noSuchName */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + + if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + msg_ps->vb_idx = 0; + msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; + } + + /* set all values "atomically" (be as "atomic" as possible) */ + while ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_name_ptr np; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + /* skip iso prefix test, was done previously while settesting() */ + mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &np); + /* check if object is still available + (e.g. external hot-plug thingy present?) */ + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF_S; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_name_ptr = np; + + en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); + } + else + { + /* internal object */ + struct obj_def object_def; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF_S; + mn->get_object_def(np.ident_len, np.ident, &object_def); + msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; + mn->set_value(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value); + msg_ps->vb_idx += 1; + } + } + } + if ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + /* simply echo the input if we can set it + @todo do we need to return the actual value? + e.g. if value is silently modified or behaves sticky? */ + msg_ps->outvb = msg_ps->invb; + msg_ps->invb.head = NULL; + msg_ps->invb.tail = NULL; + msg_ps->invb.count = 0; + snmp_ok_response(msg_ps); + } +} + + +/** + * Handle one internal or external event. + * Called for one async event. (recv external/private answer) + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + */ +void +snmp_msg_event(u8_t request_id) +{ + struct snmp_msg_pstat *msg_ps; + + if (request_id < SNMP_CONCURRENT_REQUESTS) + { + msg_ps = &msg_input_list[request_id]; + if (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) + { + snmp_msg_getnext_event(request_id, msg_ps); + } + else if (msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) + { + snmp_msg_get_event(request_id, msg_ps); + } + else if(msg_ps->rt == SNMP_ASN1_PDU_SET_REQ) + { + snmp_msg_set_event(request_id, msg_ps); + } + } +} + + +/* lwIP UDP receive callback function */ +static void +snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port) +{ + struct snmp_msg_pstat *msg_ps; + u8_t req_idx; + err_t err_ret; + u16_t payload_len = p->tot_len; + u16_t payload_ofs = 0; + u16_t varbind_ofs = 0; + + /* suppress unused argument warning */ + LWIP_UNUSED_ARG(arg); + + /* traverse input message process list, look for SNMP_MSG_EMPTY */ + msg_ps = &msg_input_list[0]; + req_idx = 0; + while ((req_idx < SNMP_CONCURRENT_REQUESTS) && (msg_ps->state != SNMP_MSG_EMPTY)) + { + req_idx++; + msg_ps++; + } + if (req_idx == SNMP_CONCURRENT_REQUESTS) + { + /* exceeding number of concurrent requests */ + pbuf_free(p); + return; + } + + /* accepting request */ + snmp_inc_snmpinpkts(); + /* record used 'protocol control block' */ + msg_ps->pcb = pcb; + /* source address (network order) */ + msg_ps->sip = *addr; + /* source port (host order (lwIP oddity)) */ + msg_ps->sp = port; + + /* check total length, version, community, pdu type */ + err_ret = snmp_pdu_header_check(p, payload_ofs, payload_len, &varbind_ofs, msg_ps); + /* Only accept requests and requests without error (be robust) */ + /* Reject response and trap headers or error requests as input! */ + if ((err_ret != ERR_OK) || + ((msg_ps->rt != SNMP_ASN1_PDU_GET_REQ) && + (msg_ps->rt != SNMP_ASN1_PDU_GET_NEXT_REQ) && + (msg_ps->rt != SNMP_ASN1_PDU_SET_REQ)) || + ((msg_ps->error_status != SNMP_ES_NOERROR) || + (msg_ps->error_index != 0)) ) + { + /* header check failed drop request silently, do not return error! */ + pbuf_free(p); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_header_check() failed\n")); + return; + } + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv ok, community %s\n", msg_ps->community)); + + /* Builds a list of variable bindings. Copy the varbinds from the pbuf + chain to glue them when these are divided over two or more pbuf's. */ + err_ret = snmp_pdu_dec_varbindlist(p, varbind_ofs, &varbind_ofs, msg_ps); + /* we've decoded the incoming message, release input msg now */ + pbuf_free(p); + if ((err_ret != ERR_OK) || (msg_ps->invb.count == 0)) + { + /* varbind-list decode failed, or varbind list empty. + drop request silently, do not return error! + (errors are only returned for a specific varbind failure) */ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_dec_varbindlist() failed\n")); + return; + } + + msg_ps->error_status = SNMP_ES_NOERROR; + msg_ps->error_index = 0; + /* find object for each variable binding */ + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + /* first variable binding from list to inspect */ + msg_ps->vb_idx = 0; + + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv varbind cnt=%"U16_F"\n",(u16_t)msg_ps->invb.count)); + + /* handle input event and as much objects as possible in one go */ + snmp_msg_event(req_idx); +} + +/** + * Checks and decodes incoming SNMP message header, logs header errors. + * + * @param p points to pbuf chain of SNMP message (UDP payload) + * @param ofs points to first octet of SNMP message + * @param pdu_len the length of the UDP payload + * @param ofs_ret returns the ofset of the variable bindings + * @param m_stat points to the current message request state return + * @return + * - ERR_OK SNMP header is sane and accepted + * - ERR_ARG SNMP header is either malformed or rejected + */ +static err_t +snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat) +{ + err_t derr; + u16_t len, ofs_base; + u8_t len_octets; + u8_t type; + s32_t version; + + ofs_base = ofs; + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || + (pdu_len != (1 + len_octets + len)) || + (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ))) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (version) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &version); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + if (version != 0) + { + /* not version 1 */ + snmp_inc_snmpinbadversions(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR))) + { + /* can't decode or no octet string (community) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, SNMP_COMMUNITY_STR_LEN, m_stat->community); + if (derr != ERR_OK) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + /* add zero terminator */ + len = ((len < (SNMP_COMMUNITY_STR_LEN))?(len):(SNMP_COMMUNITY_STR_LEN)); + m_stat->community[len] = 0; + m_stat->com_strlen = (u8_t)len; + if (strncmp(snmp_publiccommunity, (const char*)m_stat->community, SNMP_COMMUNITY_STR_LEN) != 0) + { + /** @todo: move this if we need to check more names */ + snmp_inc_snmpinbadcommunitynames(); + snmp_authfail_trap(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if (derr != ERR_OK) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + switch(type) + { + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_REQ): + /* GetRequest PDU */ + snmp_inc_snmpingetrequests(); + derr = ERR_OK; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_NEXT_REQ): + /* GetNextRequest PDU */ + snmp_inc_snmpingetnexts(); + derr = ERR_OK; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP): + /* GetResponse PDU */ + snmp_inc_snmpingetresponses(); + derr = ERR_ARG; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_SET_REQ): + /* SetRequest PDU */ + snmp_inc_snmpinsetrequests(); + derr = ERR_OK; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP): + /* Trap PDU */ + snmp_inc_snmpintraps(); + derr = ERR_ARG; + break; + default: + snmp_inc_snmpinasnparseerrs(); + derr = ERR_ARG; + break; + } + if (derr != ERR_OK) + { + /* unsupported input PDU for this agent (no parse error) */ + return ERR_ARG; + } + m_stat->rt = type & 0x1F; + ofs += (1 + len_octets); + if (len != (pdu_len - (ofs - ofs_base))) + { + /* decoded PDU length does not equal actual payload length */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (request ID) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->rid); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (error-status) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + /* must be noError (0) for incoming requests. + log errors for mib-2 completeness and for debug purposes */ + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_status); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + switch (m_stat->error_status) + { + case SNMP_ES_TOOBIG: + snmp_inc_snmpintoobigs(); + break; + case SNMP_ES_NOSUCHNAME: + snmp_inc_snmpinnosuchnames(); + break; + case SNMP_ES_BADVALUE: + snmp_inc_snmpinbadvalues(); + break; + case SNMP_ES_READONLY: + snmp_inc_snmpinreadonlys(); + break; + case SNMP_ES_GENERROR: + snmp_inc_snmpingenerrs(); + break; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (error-index) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + /* must be 0 for incoming requests. + decode anyway to catch bad integers (and dirty tricks) */ + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_index); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + *ofs_ret = ofs; + return ERR_OK; +} + +static err_t +snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat) +{ + err_t derr; + u16_t len, vb_len; + u8_t len_octets; + u8_t type; + + /* variable binding list */ + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &vb_len); + if ((derr != ERR_OK) || + (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ))) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets); + + /* start with empty list */ + m_stat->invb.count = 0; + m_stat->invb.head = NULL; + m_stat->invb.tail = NULL; + + while (vb_len > 0) + { + struct snmp_obj_id oid, oid_value; + struct snmp_varbind *vb; + + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || + (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)) || + (len == 0) || (len > vb_len)) + { + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + ofs += (1 + len_octets); + vb_len -= (1 + len_octets); + + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID))) + { + /* can't decode object name length */ + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid); + if (derr != ERR_OK) + { + /* can't decode object name */ + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + vb_len -= (1 + len_octets + len); + + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if (derr != ERR_OK) + { + /* can't decode object value length */ + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + + switch (type) + { + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): + vb = snmp_varbind_alloc(&oid, type, sizeof(s32_t)); + if (vb != NULL) + { + s32_t *vptr = (s32_t*)vb->value; + + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, vptr); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): + vb = snmp_varbind_alloc(&oid, type, sizeof(u32_t)); + if (vb != NULL) + { + u32_t *vptr = (u32_t*)vb->value; + + derr = snmp_asn1_dec_u32t(p, ofs + 1 + len_octets, len, vptr); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): + LWIP_ASSERT("invalid length", len <= 0xff); + vb = snmp_varbind_alloc(&oid, type, (u8_t)len); + if (vb != NULL) + { + derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, (u8_t*)vb->value); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): + vb = snmp_varbind_alloc(&oid, type, 0); + if (vb != NULL) + { + snmp_varbind_tail_add(&m_stat->invb, vb); + derr = ERR_OK; + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): + derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid_value); + if (derr == ERR_OK) + { + vb = snmp_varbind_alloc(&oid, type, oid_value.len * sizeof(s32_t)); + if (vb != NULL) + { + u8_t i = oid_value.len; + s32_t *vptr = (s32_t*)vb->value; + + while(i > 0) + { + i--; + vptr[i] = oid_value.id[i]; + } + snmp_varbind_tail_add(&m_stat->invb, vb); + derr = ERR_OK; + } + else + { + derr = ERR_ARG; + } + } + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): + if (len == 4) + { + /* must be exactly 4 octets! */ + vb = snmp_varbind_alloc(&oid, type, 4); + if (vb != NULL) + { + derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, (u8_t*)vb->value); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + } + else + { + derr = ERR_ARG; + } + break; + default: + derr = ERR_ARG; + break; + } + if (derr != ERR_OK) + { + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + vb_len -= (1 + len_octets + len); + } + + if (m_stat->rt == SNMP_ASN1_PDU_SET_REQ) + { + snmp_add_snmpintotalsetvars(m_stat->invb.count); + } + else + { + snmp_add_snmpintotalreqvars(m_stat->invb.count); + } + + *ofs_ret = ofs; + return ERR_OK; +} + +struct snmp_varbind* +snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len) +{ + struct snmp_varbind *vb; + + vb = (struct snmp_varbind *)memp_malloc(MEMP_SNMP_VARBIND); + LWIP_ASSERT("vb != NULL",vb != NULL); + if (vb != NULL) + { + u8_t i; + + vb->next = NULL; + vb->prev = NULL; + i = oid->len; + vb->ident_len = i; + if (i > 0) + { + LWIP_ASSERT("SNMP_MAX_TREE_DEPTH is configured too low", i <= SNMP_MAX_TREE_DEPTH); + /* allocate array of s32_t for our object identifier */ + vb->ident = (s32_t*)memp_malloc(MEMP_SNMP_VALUE); + LWIP_ASSERT("vb->ident != NULL",vb->ident != NULL); + if (vb->ident == NULL) + { + memp_free(MEMP_SNMP_VARBIND, vb); + return NULL; + } + while(i > 0) + { + i--; + vb->ident[i] = oid->id[i]; + } + } + else + { + /* i == 0, pass zero length object identifier */ + vb->ident = NULL; + } + vb->value_type = type; + vb->value_len = len; + if (len > 0) + { + LWIP_ASSERT("SNMP_MAX_OCTET_STRING_LEN is configured too low", vb->value_len <= SNMP_MAX_VALUE_SIZE); + /* allocate raw bytes for our object value */ + vb->value = memp_malloc(MEMP_SNMP_VALUE); + LWIP_ASSERT("vb->value != NULL",vb->value != NULL); + if (vb->value == NULL) + { + if (vb->ident != NULL) + { + memp_free(MEMP_SNMP_VALUE, vb->ident); + } + memp_free(MEMP_SNMP_VARBIND, vb); + return NULL; + } + } + else + { + /* ASN1_NUL type, or zero length ASN1_OC_STR */ + vb->value = NULL; + } + } + return vb; +} + +void +snmp_varbind_free(struct snmp_varbind *vb) +{ + if (vb->value != NULL ) + { + memp_free(MEMP_SNMP_VALUE, vb->value); + } + if (vb->ident != NULL ) + { + memp_free(MEMP_SNMP_VALUE, vb->ident); + } + memp_free(MEMP_SNMP_VARBIND, vb); +} + +void +snmp_varbind_list_free(struct snmp_varbind_root *root) +{ + struct snmp_varbind *vb, *prev; + + vb = root->tail; + while ( vb != NULL ) + { + prev = vb->prev; + snmp_varbind_free(vb); + vb = prev; + } + root->count = 0; + root->head = NULL; + root->tail = NULL; +} + +void +snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb) +{ + if (root->count == 0) + { + /* add first varbind to list */ + root->head = vb; + root->tail = vb; + } + else + { + /* add nth varbind to list tail */ + root->tail->next = vb; + vb->prev = root->tail; + root->tail = vb; + } + root->count += 1; +} + +struct snmp_varbind* +snmp_varbind_tail_remove(struct snmp_varbind_root *root) +{ + struct snmp_varbind* vb; + + if (root->count > 0) + { + /* remove tail varbind */ + vb = root->tail; + root->tail = vb->prev; + vb->prev->next = NULL; + root->count -= 1; + } + else + { + /* nothing to remove */ + vb = NULL; + } + return vb; +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_out.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_out.c new file mode 100644 index 0000000..4778bee --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_out.c @@ -0,0 +1,681 @@ +/** + * @file + * SNMP output message processing (RFC1157). + * + * Output responses and traps are build in two passes: + * + * Pass 0: iterate over the output message backwards to determine encoding lengths + * Pass 1: the actual forward encoding of internal form into ASN1 + * + * The single-pass encoding method described by Comer & Stevens + * requires extra buffer space and copying for reversal of the packet. + * The buffer requirement can be prohibitively large for big payloads + * (>= 484) therefore we use the two encoding passes. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/udp.h" +#include "lwip/netif.h" +#include "lwip/snmp.h" +#include "lwip/snmp_asn1.h" +#include "lwip/snmp_msg.h" + +struct snmp_trap_dst +{ + /* destination IP address in network order */ + ip_addr_t dip; + /* set to 0 when disabled, >0 when enabled */ + u8_t enable; +}; +struct snmp_trap_dst trap_dst[SNMP_TRAP_DESTINATIONS]; + +/** TRAP message structure */ +struct snmp_msg_trap trap_msg; + +static u16_t snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len); +static u16_t snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len); +static u16_t snmp_varbind_list_sum(struct snmp_varbind_root *root); + +static u16_t snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p); +static u16_t snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p); +static u16_t snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs); + +/** + * Sets enable switch for this trap destination. + * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 + * @param enable switch if 0 destination is disabled >0 enabled. + */ +void +snmp_trap_dst_enable(u8_t dst_idx, u8_t enable) +{ + if (dst_idx < SNMP_TRAP_DESTINATIONS) + { + trap_dst[dst_idx].enable = enable; + } +} + +/** + * Sets IPv4 address for this trap destination. + * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 + * @param dst IPv4 address in host order. + */ +void +snmp_trap_dst_ip_set(u8_t dst_idx, ip_addr_t *dst) +{ + if (dst_idx < SNMP_TRAP_DESTINATIONS) + { + ip_addr_set(&trap_dst[dst_idx].dip, dst); + } +} + +/** + * Sends a 'getresponse' message to the request originator. + * + * @param m_stat points to the current message request state source + * @return ERR_OK when success, ERR_MEM if we're out of memory + * + * @note the caller is responsible for filling in outvb in the m_stat + * and provide error-status and index (except for tooBig errors) ... + */ +err_t +snmp_send_response(struct snmp_msg_pstat *m_stat) +{ + struct snmp_varbind_root emptyvb = {NULL, NULL, 0, 0, 0}; + struct pbuf *p; + u16_t tot_len; + err_t err; + + /* pass 0, calculate length fields */ + tot_len = snmp_varbind_list_sum(&m_stat->outvb); + tot_len = snmp_resp_header_sum(m_stat, tot_len); + + /* try allocating pbuf(s) for complete response */ + p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); + if (p == NULL) + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() tooBig\n")); + + /* can't construct reply, return error-status tooBig */ + m_stat->error_status = SNMP_ES_TOOBIG; + m_stat->error_index = 0; + /* pass 0, recalculate lengths, for empty varbind-list */ + tot_len = snmp_varbind_list_sum(&emptyvb); + tot_len = snmp_resp_header_sum(m_stat, tot_len); + /* retry allocation once for header and empty varbind-list */ + p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); + } + if (p != NULL) + { + /* first pbuf alloc try or retry alloc success */ + u16_t ofs; + + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() p != NULL\n")); + + /* pass 1, size error, encode packet ino the pbuf(s) */ + ofs = snmp_resp_header_enc(m_stat, p); + if (m_stat->error_status == SNMP_ES_TOOBIG) + { + snmp_varbind_list_enc(&emptyvb, p, ofs); + } + else + { + snmp_varbind_list_enc(&m_stat->outvb, p, ofs); + } + + switch (m_stat->error_status) + { + case SNMP_ES_TOOBIG: + snmp_inc_snmpouttoobigs(); + break; + case SNMP_ES_NOSUCHNAME: + snmp_inc_snmpoutnosuchnames(); + break; + case SNMP_ES_BADVALUE: + snmp_inc_snmpoutbadvalues(); + break; + case SNMP_ES_GENERROR: + snmp_inc_snmpoutgenerrs(); + break; + } + snmp_inc_snmpoutgetresponses(); + snmp_inc_snmpoutpkts(); + + /** @todo do we need separate rx and tx pcbs for threaded case? */ + /** connect to the originating source */ + udp_connect(m_stat->pcb, &m_stat->sip, m_stat->sp); + err = udp_send(m_stat->pcb, p); + if (err == ERR_MEM) + { + /** @todo release some memory, retry and return tooBig? tooMuchHassle? */ + err = ERR_MEM; + } + else + { + err = ERR_OK; + } + /** disassociate remote address and port with this pcb */ + udp_disconnect(m_stat->pcb); + + pbuf_free(p); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() done\n")); + return err; + } + else + { + /* first pbuf alloc try or retry alloc failed + very low on memory, couldn't return tooBig */ + return ERR_MEM; + } +} + + +/** + * Sends an generic or enterprise specific trap message. + * + * @param generic_trap is the trap code + * @param eoid points to enterprise object identifier + * @param specific_trap used for enterprise traps when generic_trap == 6 + * @return ERR_OK when success, ERR_MEM if we're out of memory + * + * @note the caller is responsible for filling in outvb in the trap_msg + * @note the use of the enterpise identifier field + * is per RFC1215. + * Use .iso.org.dod.internet.mgmt.mib-2.snmp for generic traps + * and .iso.org.dod.internet.private.enterprises.yourenterprise + * (sysObjectID) for specific traps. + */ +err_t +snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap) +{ + struct snmp_trap_dst *td; + struct netif *dst_if; + ip_addr_t dst_ip; + struct pbuf *p; + u16_t i,tot_len; + + for (i=0, td = &trap_dst[0]; ienable != 0) && !ip_addr_isany(&td->dip)) + { + /* network order trap destination */ + ip_addr_copy(trap_msg.dip, td->dip); + /* lookup current source address for this dst */ + dst_if = ip_route(&td->dip); + ip_addr_copy(dst_ip, dst_if->ip_addr); + /* @todo: what about IPv6? */ + trap_msg.sip_raw[0] = ip4_addr1(&dst_ip); + trap_msg.sip_raw[1] = ip4_addr2(&dst_ip); + trap_msg.sip_raw[2] = ip4_addr3(&dst_ip); + trap_msg.sip_raw[3] = ip4_addr4(&dst_ip); + trap_msg.gen_trap = generic_trap; + trap_msg.spc_trap = specific_trap; + if (generic_trap == SNMP_GENTRAP_ENTERPRISESPC) + { + /* enterprise-Specific trap */ + trap_msg.enterprise = eoid; + } + else + { + /* generic (MIB-II) trap */ + snmp_get_snmpgrpid_ptr(&trap_msg.enterprise); + } + snmp_get_sysuptime(&trap_msg.ts); + + /* pass 0, calculate length fields */ + tot_len = snmp_varbind_list_sum(&trap_msg.outvb); + tot_len = snmp_trap_header_sum(&trap_msg, tot_len); + + /* allocate pbuf(s) */ + p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); + if (p != NULL) + { + u16_t ofs; + + /* pass 1, encode packet ino the pbuf(s) */ + ofs = snmp_trap_header_enc(&trap_msg, p); + snmp_varbind_list_enc(&trap_msg.outvb, p, ofs); + + snmp_inc_snmpouttraps(); + snmp_inc_snmpoutpkts(); + + /** send to the TRAP destination */ + udp_sendto(trap_msg.pcb, p, &trap_msg.dip, SNMP_TRAP_PORT); + + pbuf_free(p); + } + else + { + return ERR_MEM; + } + } + } + return ERR_OK; +} + +void +snmp_coldstart_trap(void) +{ + trap_msg.outvb.head = NULL; + trap_msg.outvb.tail = NULL; + trap_msg.outvb.count = 0; + snmp_send_trap(SNMP_GENTRAP_COLDSTART, NULL, 0); +} + +void +snmp_authfail_trap(void) +{ + u8_t enable; + snmp_get_snmpenableauthentraps(&enable); + if (enable == 1) + { + trap_msg.outvb.head = NULL; + trap_msg.outvb.tail = NULL; + trap_msg.outvb.count = 0; + snmp_send_trap(SNMP_GENTRAP_AUTHFAIL, NULL, 0); + } +} + +/** + * Sums response header field lengths from tail to head and + * returns resp_header_lengths for second encoding pass. + * + * @param vb_len varbind-list length + * @param rhl points to returned header lengths + * @return the required lenght for encoding the response header + */ +static u16_t +snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len) +{ + u16_t tot_len; + struct snmp_resp_header_lengths *rhl; + + rhl = &m_stat->rhl; + tot_len = vb_len; + snmp_asn1_enc_s32t_cnt(m_stat->error_index, &rhl->erridxlen); + snmp_asn1_enc_length_cnt(rhl->erridxlen, &rhl->erridxlenlen); + tot_len += 1 + rhl->erridxlenlen + rhl->erridxlen; + + snmp_asn1_enc_s32t_cnt(m_stat->error_status, &rhl->errstatlen); + snmp_asn1_enc_length_cnt(rhl->errstatlen, &rhl->errstatlenlen); + tot_len += 1 + rhl->errstatlenlen + rhl->errstatlen; + + snmp_asn1_enc_s32t_cnt(m_stat->rid, &rhl->ridlen); + snmp_asn1_enc_length_cnt(rhl->ridlen, &rhl->ridlenlen); + tot_len += 1 + rhl->ridlenlen + rhl->ridlen; + + rhl->pdulen = tot_len; + snmp_asn1_enc_length_cnt(rhl->pdulen, &rhl->pdulenlen); + tot_len += 1 + rhl->pdulenlen; + + rhl->comlen = m_stat->com_strlen; + snmp_asn1_enc_length_cnt(rhl->comlen, &rhl->comlenlen); + tot_len += 1 + rhl->comlenlen + rhl->comlen; + + snmp_asn1_enc_s32t_cnt(snmp_version, &rhl->verlen); + snmp_asn1_enc_length_cnt(rhl->verlen, &rhl->verlenlen); + tot_len += 1 + rhl->verlen + rhl->verlenlen; + + rhl->seqlen = tot_len; + snmp_asn1_enc_length_cnt(rhl->seqlen, &rhl->seqlenlen); + tot_len += 1 + rhl->seqlenlen; + + return tot_len; +} + +/** + * Sums trap header field lengths from tail to head and + * returns trap_header_lengths for second encoding pass. + * + * @param vb_len varbind-list length + * @param thl points to returned header lengths + * @return the required lenght for encoding the trap header + */ +static u16_t +snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len) +{ + u16_t tot_len; + struct snmp_trap_header_lengths *thl; + + thl = &m_trap->thl; + tot_len = vb_len; + + snmp_asn1_enc_u32t_cnt(m_trap->ts, &thl->tslen); + snmp_asn1_enc_length_cnt(thl->tslen, &thl->tslenlen); + tot_len += 1 + thl->tslen + thl->tslenlen; + + snmp_asn1_enc_s32t_cnt(m_trap->spc_trap, &thl->strplen); + snmp_asn1_enc_length_cnt(thl->strplen, &thl->strplenlen); + tot_len += 1 + thl->strplen + thl->strplenlen; + + snmp_asn1_enc_s32t_cnt(m_trap->gen_trap, &thl->gtrplen); + snmp_asn1_enc_length_cnt(thl->gtrplen, &thl->gtrplenlen); + tot_len += 1 + thl->gtrplen + thl->gtrplenlen; + + thl->aaddrlen = 4; + snmp_asn1_enc_length_cnt(thl->aaddrlen, &thl->aaddrlenlen); + tot_len += 1 + thl->aaddrlen + thl->aaddrlenlen; + + snmp_asn1_enc_oid_cnt(m_trap->enterprise->len, &m_trap->enterprise->id[0], &thl->eidlen); + snmp_asn1_enc_length_cnt(thl->eidlen, &thl->eidlenlen); + tot_len += 1 + thl->eidlen + thl->eidlenlen; + + thl->pdulen = tot_len; + snmp_asn1_enc_length_cnt(thl->pdulen, &thl->pdulenlen); + tot_len += 1 + thl->pdulenlen; + + thl->comlen = sizeof(snmp_publiccommunity) - 1; + snmp_asn1_enc_length_cnt(thl->comlen, &thl->comlenlen); + tot_len += 1 + thl->comlenlen + thl->comlen; + + snmp_asn1_enc_s32t_cnt(snmp_version, &thl->verlen); + snmp_asn1_enc_length_cnt(thl->verlen, &thl->verlenlen); + tot_len += 1 + thl->verlen + thl->verlenlen; + + thl->seqlen = tot_len; + snmp_asn1_enc_length_cnt(thl->seqlen, &thl->seqlenlen); + tot_len += 1 + thl->seqlenlen; + + return tot_len; +} + +/** + * Sums varbind lengths from tail to head and + * annotates lengths in varbind for second encoding pass. + * + * @param root points to the root of the variable binding list + * @return the required lenght for encoding the variable bindings + */ +static u16_t +snmp_varbind_list_sum(struct snmp_varbind_root *root) +{ + struct snmp_varbind *vb; + u32_t *uint_ptr; + s32_t *sint_ptr; + u16_t tot_len; + + tot_len = 0; + vb = root->tail; + while ( vb != NULL ) + { + /* encoded value lenght depends on type */ + switch (vb->value_type) + { + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): + sint_ptr = (s32_t*)vb->value; + snmp_asn1_enc_s32t_cnt(*sint_ptr, &vb->vlen); + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): + uint_ptr = (u32_t*)vb->value; + snmp_asn1_enc_u32t_cnt(*uint_ptr, &vb->vlen); + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): + vb->vlen = vb->value_len; + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): + sint_ptr = (s32_t*)vb->value; + snmp_asn1_enc_oid_cnt(vb->value_len / sizeof(s32_t), sint_ptr, &vb->vlen); + break; + default: + /* unsupported type */ + vb->vlen = 0; + break; + }; + /* encoding length of value length field */ + snmp_asn1_enc_length_cnt(vb->vlen, &vb->vlenlen); + snmp_asn1_enc_oid_cnt(vb->ident_len, vb->ident, &vb->olen); + snmp_asn1_enc_length_cnt(vb->olen, &vb->olenlen); + + vb->seqlen = 1 + vb->vlenlen + vb->vlen; + vb->seqlen += 1 + vb->olenlen + vb->olen; + snmp_asn1_enc_length_cnt(vb->seqlen, &vb->seqlenlen); + + /* varbind seq */ + tot_len += 1 + vb->seqlenlen + vb->seqlen; + + vb = vb->prev; + } + + /* varbind-list seq */ + root->seqlen = tot_len; + snmp_asn1_enc_length_cnt(root->seqlen, &root->seqlenlen); + tot_len += 1 + root->seqlenlen; + + return tot_len; +} + +/** + * Encodes response header from head to tail. + */ +static u16_t +snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p) +{ + u16_t ofs; + + ofs = 0; + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.seqlen); + ofs += m_stat->rhl.seqlenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.verlen); + ofs += m_stat->rhl.verlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.verlen, snmp_version); + ofs += m_stat->rhl.verlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.comlen); + ofs += m_stat->rhl.comlenlen; + snmp_asn1_enc_raw(p, ofs, m_stat->rhl.comlen, m_stat->community); + ofs += m_stat->rhl.comlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.pdulen); + ofs += m_stat->rhl.pdulenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.ridlen); + ofs += m_stat->rhl.ridlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.ridlen, m_stat->rid); + ofs += m_stat->rhl.ridlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.errstatlen); + ofs += m_stat->rhl.errstatlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.errstatlen, m_stat->error_status); + ofs += m_stat->rhl.errstatlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.erridxlen); + ofs += m_stat->rhl.erridxlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.erridxlen, m_stat->error_index); + ofs += m_stat->rhl.erridxlen; + + return ofs; +} + +/** + * Encodes trap header from head to tail. + */ +static u16_t +snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p) +{ + u16_t ofs; + + ofs = 0; + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.seqlen); + ofs += m_trap->thl.seqlenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.verlen); + ofs += m_trap->thl.verlenlen; + snmp_asn1_enc_s32t(p, ofs, m_trap->thl.verlen, snmp_version); + ofs += m_trap->thl.verlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.comlen); + ofs += m_trap->thl.comlenlen; + snmp_asn1_enc_raw(p, ofs, m_trap->thl.comlen, (u8_t *)&snmp_publiccommunity[0]); + ofs += m_trap->thl.comlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.pdulen); + ofs += m_trap->thl.pdulenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.eidlen); + ofs += m_trap->thl.eidlenlen; + snmp_asn1_enc_oid(p, ofs, m_trap->enterprise->len, &m_trap->enterprise->id[0]); + ofs += m_trap->thl.eidlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.aaddrlen); + ofs += m_trap->thl.aaddrlenlen; + snmp_asn1_enc_raw(p, ofs, m_trap->thl.aaddrlen, &m_trap->sip_raw[0]); + ofs += m_trap->thl.aaddrlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.gtrplen); + ofs += m_trap->thl.gtrplenlen; + snmp_asn1_enc_u32t(p, ofs, m_trap->thl.gtrplen, m_trap->gen_trap); + ofs += m_trap->thl.gtrplen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.strplen); + ofs += m_trap->thl.strplenlen; + snmp_asn1_enc_u32t(p, ofs, m_trap->thl.strplen, m_trap->spc_trap); + ofs += m_trap->thl.strplen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.tslen); + ofs += m_trap->thl.tslenlen; + snmp_asn1_enc_u32t(p, ofs, m_trap->thl.tslen, m_trap->ts); + ofs += m_trap->thl.tslen; + + return ofs; +} + +/** + * Encodes varbind list from head to tail. + */ +static u16_t +snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs) +{ + struct snmp_varbind *vb; + s32_t *sint_ptr; + u32_t *uint_ptr; + u8_t *raw_ptr; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, root->seqlen); + ofs += root->seqlenlen; + + vb = root->head; + while ( vb != NULL ) + { + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, vb->seqlen); + ofs += vb->seqlenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, vb->olen); + ofs += vb->olenlen; + snmp_asn1_enc_oid(p, ofs, vb->ident_len, &vb->ident[0]); + ofs += vb->olen; + + snmp_asn1_enc_type(p, ofs, vb->value_type); + ofs += 1; + snmp_asn1_enc_length(p, ofs, vb->vlen); + ofs += vb->vlenlen; + + switch (vb->value_type) + { + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): + sint_ptr = (s32_t*)vb->value; + snmp_asn1_enc_s32t(p, ofs, vb->vlen, *sint_ptr); + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): + uint_ptr = (u32_t*)vb->value; + snmp_asn1_enc_u32t(p, ofs, vb->vlen, *uint_ptr); + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): + raw_ptr = (u8_t*)vb->value; + snmp_asn1_enc_raw(p, ofs, vb->vlen, raw_ptr); + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): + sint_ptr = (s32_t*)vb->value; + snmp_asn1_enc_oid(p, ofs, vb->value_len / sizeof(s32_t), sint_ptr); + break; + default: + /* unsupported type */ + break; + }; + ofs += vb->vlen; + vb = vb->next; + } + return ofs; +} + +#endif /* LWIP_SNMP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/stats.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/stats.c new file mode 100644 index 0000000..69f97d4 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/stats.c @@ -0,0 +1,176 @@ +/** + * @file + * Statistics module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_STATS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/stats.h" +#include "lwip/mem.h" + +#include + +struct stats_ lwip_stats; + +void stats_init(void) +{ +#ifdef LWIP_DEBUG +#if MEMP_STATS + const char * memp_names[] = { +#define LWIP_MEMPOOL(name,num,size,desc) desc, +#include "lwip/memp_std.h" + }; + int i; + for (i = 0; i < MEMP_MAX; i++) { + lwip_stats.memp[i].name = memp_names[i]; + } +#endif /* MEMP_STATS */ +#if MEM_STATS + lwip_stats.mem.name = "MEM"; +#endif /* MEM_STATS */ +#endif /* LWIP_DEBUG */ +} + +#if LWIP_STATS_DISPLAY +void +stats_display_proto(struct stats_proto *proto, char *name) +{ + LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); + LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", proto->xmit)); + LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", proto->recv)); + LWIP_PLATFORM_DIAG(("fw: %"STAT_COUNTER_F"\n\t", proto->fw)); + LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", proto->drop)); + LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", proto->chkerr)); + LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", proto->lenerr)); + LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", proto->memerr)); + LWIP_PLATFORM_DIAG(("rterr: %"STAT_COUNTER_F"\n\t", proto->rterr)); + LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", proto->proterr)); + LWIP_PLATFORM_DIAG(("opterr: %"STAT_COUNTER_F"\n\t", proto->opterr)); + LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n\t", proto->err)); + LWIP_PLATFORM_DIAG(("cachehit: %"STAT_COUNTER_F"\n", proto->cachehit)); +} + +#if IGMP_STATS +void +stats_display_igmp(struct stats_igmp *igmp) +{ + LWIP_PLATFORM_DIAG(("\nIGMP\n\t")); + LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", igmp->xmit)); + LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", igmp->recv)); + LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", igmp->drop)); + LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", igmp->chkerr)); + LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", igmp->lenerr)); + LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", igmp->memerr)); + LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", igmp->proterr)); + LWIP_PLATFORM_DIAG(("rx_v1: %"STAT_COUNTER_F"\n\t", igmp->rx_v1)); + LWIP_PLATFORM_DIAG(("rx_group: %"STAT_COUNTER_F"\n", igmp->rx_group)); + LWIP_PLATFORM_DIAG(("rx_general: %"STAT_COUNTER_F"\n", igmp->rx_general)); + LWIP_PLATFORM_DIAG(("rx_report: %"STAT_COUNTER_F"\n\t", igmp->rx_report)); + LWIP_PLATFORM_DIAG(("tx_join: %"STAT_COUNTER_F"\n\t", igmp->tx_join)); + LWIP_PLATFORM_DIAG(("tx_leave: %"STAT_COUNTER_F"\n\t", igmp->tx_leave)); + LWIP_PLATFORM_DIAG(("tx_report: %"STAT_COUNTER_F"\n\t", igmp->tx_report)); +} +#endif /* IGMP_STATS */ + +#if MEM_STATS || MEMP_STATS +void +stats_display_mem(struct stats_mem *mem, char *name) +{ + LWIP_PLATFORM_DIAG(("\nMEM %s\n\t", name)); + LWIP_PLATFORM_DIAG(("avail: %"U32_F"\n\t", (u32_t)mem->avail)); + LWIP_PLATFORM_DIAG(("used: %"U32_F"\n\t", (u32_t)mem->used)); + LWIP_PLATFORM_DIAG(("max: %"U32_F"\n\t", (u32_t)mem->max)); + LWIP_PLATFORM_DIAG(("err: %"U32_F"\n", (u32_t)mem->err)); +} + +#if MEMP_STATS +void +stats_display_memp(struct stats_mem *mem, int index) +{ + char * memp_names[] = { +#define LWIP_MEMPOOL(name,num,size,desc) desc, +#include "lwip/memp_std.h" + }; + if(index < MEMP_MAX) { + stats_display_mem(mem, memp_names[index]); + } +} +#endif /* MEMP_STATS */ +#endif /* MEM_STATS || MEMP_STATS */ + +#if SYS_STATS +void +stats_display_sys(struct stats_sys *sys) +{ + LWIP_PLATFORM_DIAG(("\nSYS\n\t")); + LWIP_PLATFORM_DIAG(("sem.used: %"U32_F"\n\t", (u32_t)sys->sem.used)); + LWIP_PLATFORM_DIAG(("sem.max: %"U32_F"\n\t", (u32_t)sys->sem.max)); + LWIP_PLATFORM_DIAG(("sem.err: %"U32_F"\n\t", (u32_t)sys->sem.err)); + LWIP_PLATFORM_DIAG(("mutex.used: %"U32_F"\n\t", (u32_t)sys->mutex.used)); + LWIP_PLATFORM_DIAG(("mutex.max: %"U32_F"\n\t", (u32_t)sys->mutex.max)); + LWIP_PLATFORM_DIAG(("mutex.err: %"U32_F"\n\t", (u32_t)sys->mutex.err)); + LWIP_PLATFORM_DIAG(("mbox.used: %"U32_F"\n\t", (u32_t)sys->mbox.used)); + LWIP_PLATFORM_DIAG(("mbox.max: %"U32_F"\n\t", (u32_t)sys->mbox.max)); + LWIP_PLATFORM_DIAG(("mbox.err: %"U32_F"\n\t", (u32_t)sys->mbox.err)); +} +#endif /* SYS_STATS */ + +void +stats_display(void) +{ + s16_t i; + + LINK_STATS_DISPLAY(); + ETHARP_STATS_DISPLAY(); + IPFRAG_STATS_DISPLAY(); + IP_STATS_DISPLAY(); + IGMP_STATS_DISPLAY(); + ICMP_STATS_DISPLAY(); + UDP_STATS_DISPLAY(); + TCP_STATS_DISPLAY(); + MEM_STATS_DISPLAY(); + for (i = 0; i < MEMP_MAX; i++) { + MEMP_STATS_DISPLAY(i); + } + SYS_STATS_DISPLAY(); +} +#endif /* LWIP_STATS_DISPLAY */ + +#endif /* LWIP_STATS */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/sys.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/sys.c new file mode 100644 index 0000000..d3a77de --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/sys.c @@ -0,0 +1,66 @@ +/** + * @file + * lwIP Operating System abstraction + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/sys.h" + +/* Most of the functions defined in sys.h must be implemented in the + * architecture-dependent file sys_arch.c */ + +#if !NO_SYS + +/** + * Sleep for some ms. Timeouts are NOT processed while sleeping. + * + * @param ms number of milliseconds to sleep + */ +void +sys_msleep(u32_t ms) +{ + if (ms > 0) { + sys_sem_t delaysem; + err_t err = sys_sem_new(&delaysem, 0); + if (err == ERR_OK) { + sys_arch_sem_wait(&delaysem, ms); + sys_sem_free(&delaysem); + } + } +} + +#endif /* !NO_SYS */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/tcp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/tcp.c new file mode 100644 index 0000000..c629bc4 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/tcp.c @@ -0,0 +1,1635 @@ +/** + * @file + * Transmission Control Protocol for IP + * + * This file contains common functions for the TCP implementation, such as functinos + * for manipulating the data structures and the TCP timer functions. TCP functions + * related to input and output is found in tcp_in.c and tcp_out.c respectively. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/snmp.h" +#include "lwip/tcp.h" +#include "lwip/tcp_impl.h" +#include "lwip/debug.h" +#include "lwip/stats.h" + +#include + +const char * const tcp_state_str[] = { + "CLOSED", + "LISTEN", + "SYN_SENT", + "SYN_RCVD", + "ESTABLISHED", + "FIN_WAIT_1", + "FIN_WAIT_2", + "CLOSE_WAIT", + "CLOSING", + "LAST_ACK", + "TIME_WAIT" +}; + +/* Incremented every coarse grained timer shot (typically every 500 ms). */ +u32_t tcp_ticks; +const u8_t tcp_backoff[13] = + { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7}; + /* Times per slowtmr hits */ +const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 }; + +/* The TCP PCB lists. */ + +/** List of all TCP PCBs bound but not yet (connected || listening) */ +struct tcp_pcb *tcp_bound_pcbs; +/** List of all TCP PCBs in LISTEN state */ +union tcp_listen_pcbs_t tcp_listen_pcbs; +/** List of all TCP PCBs that are in a state in which + * they accept or send data. */ +struct tcp_pcb *tcp_active_pcbs; +/** List of all TCP PCBs in TIME-WAIT state */ +struct tcp_pcb *tcp_tw_pcbs; + +#define NUM_TCP_PCB_LISTS 4 +#define NUM_TCP_PCB_LISTS_NO_TIME_WAIT 3 +/** An array with all (non-temporary) PCB lists, mainly used for smaller code size */ +struct tcp_pcb ** const tcp_pcb_lists[] = {&tcp_listen_pcbs.pcbs, &tcp_bound_pcbs, + &tcp_active_pcbs, &tcp_tw_pcbs}; + +/** Only used for temporary storage. */ +struct tcp_pcb *tcp_tmp_pcb; + +/** Timer counter to handle calling slow-timer from tcp_tmr() */ +static u8_t tcp_timer; +static u16_t tcp_new_port(void); + +/** + * Called periodically to dispatch TCP timers. + * + */ +void +tcp_tmr(void) +{ + /* Call tcp_fasttmr() every 250 ms */ + tcp_fasttmr(); + + if (++tcp_timer & 1) { + /* Call tcp_tmr() every 500 ms, i.e., every other timer + tcp_tmr() is called. */ + tcp_slowtmr(); + } +} + +/** + * Closes the TX side of a connection held by the PCB. + * For tcp_close(), a RST is sent if the application didn't receive all data + * (tcp_recved() not called for all data passed to recv callback). + * + * Listening pcbs are freed and may not be referenced any more. + * Connection pcbs are freed if not yet connected and may not be referenced + * any more. If a connection is established (at least SYN received or in + * a closing state), the connection is closed, and put in a closing state. + * The pcb is then automatically freed in tcp_slowtmr(). It is therefore + * unsafe to reference it. + * + * @param pcb the tcp_pcb to close + * @return ERR_OK if connection has been closed + * another err_t if closing failed and pcb is not freed + */ +static err_t +tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data) +{ + err_t err; + + if (rst_on_unacked_data && (pcb->state != LISTEN)) { + if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND)) { + /* Not all data received by application, send RST to tell the remote + side about this. */ + LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED); + + /* don't call tcp_abort here: we must not deallocate the pcb since + that might not be expected when calling tcp_close */ + tcp_rst(pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, + pcb->local_port, pcb->remote_port); + + tcp_pcb_purge(pcb); + + /* TODO: to which state do we move now? */ + + /* move to TIME_WAIT since we close actively */ + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + + return ERR_OK; + } + } + + switch (pcb->state) { + case CLOSED: + /* Closing a pcb in the CLOSED state might seem erroneous, + * however, it is in this state once allocated and as yet unused + * and the user needs some way to free it should the need arise. + * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) + * or for a pcb that has been used and then entered the CLOSED state + * is erroneous, but this should never happen as the pcb has in those cases + * been freed, and so any remaining handles are bogus. */ + err = ERR_OK; + if (pcb->local_port != 0) { + TCP_RMV(&tcp_bound_pcbs, pcb); + } + memp_free(MEMP_TCP_PCB, pcb); + pcb = NULL; + break; + case LISTEN: + err = ERR_OK; + tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb); + memp_free(MEMP_TCP_PCB_LISTEN, pcb); + pcb = NULL; + break; + case SYN_SENT: + err = ERR_OK; + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + pcb = NULL; + snmp_inc_tcpattemptfails(); + break; + case SYN_RCVD: + err = tcp_send_fin(pcb); + if (err == ERR_OK) { + snmp_inc_tcpattemptfails(); + pcb->state = FIN_WAIT_1; + } + break; + case ESTABLISHED: + err = tcp_send_fin(pcb); + if (err == ERR_OK) { + snmp_inc_tcpestabresets(); + pcb->state = FIN_WAIT_1; + } + break; + case CLOSE_WAIT: + err = tcp_send_fin(pcb); + if (err == ERR_OK) { + snmp_inc_tcpestabresets(); + pcb->state = LAST_ACK; + } + break; + default: + /* Has already been closed, do nothing. */ + err = ERR_OK; + pcb = NULL; + break; + } + + if (pcb != NULL && err == ERR_OK) { + /* To ensure all data has been sent when tcp_close returns, we have + to make sure tcp_output doesn't fail. + Since we don't really have to ensure all data has been sent when tcp_close + returns (unsent data is sent from tcp timer functions, also), we don't care + for the return value of tcp_output for now. */ + /* @todo: When implementing SO_LINGER, this must be changed somehow: + If SOF_LINGER is set, the data should be sent and acked before close returns. + This can only be valid for sequential APIs, not for the raw API. */ + tcp_output(pcb); + } + return err; +} + +/** + * Closes the connection held by the PCB. + * + * Listening pcbs are freed and may not be referenced any more. + * Connection pcbs are freed if not yet connected and may not be referenced + * any more. If a connection is established (at least SYN received or in + * a closing state), the connection is closed, and put in a closing state. + * The pcb is then automatically freed in tcp_slowtmr(). It is therefore + * unsafe to reference it (unless an error is returned). + * + * @param pcb the tcp_pcb to close + * @return ERR_OK if connection has been closed + * another err_t if closing failed and pcb is not freed + */ +err_t +tcp_close(struct tcp_pcb *pcb) +{ +#if TCP_DEBUG + LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ + + if (pcb->state != LISTEN) { + /* Set a flag not to receive any more data... */ + pcb->flags |= TF_RXCLOSED; + } + /* ... and close */ + return tcp_close_shutdown(pcb, 1); +} + +/** + * Causes all or part of a full-duplex connection of this PCB to be shut down. + * This doesn't deallocate the PCB! + * + * @param pcb PCB to shutdown + * @param shut_rx shut down receive side if this is != 0 + * @param shut_tx shut down send side if this is != 0 + * @return ERR_OK if shutdown succeeded (or the PCB has already been shut down) + * another err_t on error. + */ +err_t +tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx) +{ + if (pcb->state == LISTEN) { + return ERR_CONN; + } + if (shut_rx) { + /* shut down the receive side: free buffered data... */ + if (pcb->refused_data != NULL) { + pbuf_free(pcb->refused_data); + pcb->refused_data = NULL; + } + /* ... and set a flag not to receive any more data */ + pcb->flags |= TF_RXCLOSED; + } + if (shut_tx) { + /* This can't happen twice since if it succeeds, the pcb's state is changed. + Only close in these states as the others directly deallocate the PCB */ + switch (pcb->state) { + case SYN_RCVD: + case ESTABLISHED: + case CLOSE_WAIT: + return tcp_close_shutdown(pcb, 0); + default: + /* don't shut down other states */ + break; + } + } + /* @todo: return another err_t if not in correct state or already shut? */ + return ERR_OK; +} + +/** + * Abandons a connection and optionally sends a RST to the remote + * host. Deletes the local protocol control block. This is done when + * a connection is killed because of shortage of memory. + * + * @param pcb the tcp_pcb to abort + * @param reset boolean to indicate whether a reset should be sent + */ +void +tcp_abandon(struct tcp_pcb *pcb, int reset) +{ + u32_t seqno, ackno; + u16_t remote_port, local_port; + ip_addr_t remote_ip, local_ip; +#if LWIP_CALLBACK_API + tcp_err_fn errf; +#endif /* LWIP_CALLBACK_API */ + void *errf_arg; + + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs", + pcb->state != LISTEN); + /* Figure out on which TCP PCB list we are, and remove us. If we + are in an active state, call the receive function associated with + the PCB with a NULL argument, and send an RST to the remote end. */ + if (pcb->state == TIME_WAIT) { + tcp_pcb_remove(&tcp_tw_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else { + seqno = pcb->snd_nxt; + ackno = pcb->rcv_nxt; + ip_addr_copy(local_ip, pcb->local_ip); + ip_addr_copy(remote_ip, pcb->remote_ip); + local_port = pcb->local_port; + remote_port = pcb->remote_port; +#if LWIP_CALLBACK_API + errf = pcb->errf; +#endif /* LWIP_CALLBACK_API */ + errf_arg = pcb->callback_arg; + tcp_pcb_remove(&tcp_active_pcbs, pcb); + if (pcb->unacked != NULL) { + tcp_segs_free(pcb->unacked); + } + if (pcb->unsent != NULL) { + tcp_segs_free(pcb->unsent); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + tcp_segs_free(pcb->ooseq); + } +#endif /* TCP_QUEUE_OOSEQ */ + memp_free(MEMP_TCP_PCB, pcb); + TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT); + if (reset) { + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n")); + tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port); + } + } +} + +/** + * Aborts the connection by sending a RST (reset) segment to the remote + * host. The pcb is deallocated. This function never fails. + * + * ATTENTION: When calling this from one of the TCP callbacks, make + * sure you always return ERR_ABRT (and never return ERR_ABRT otherwise + * or you will risk accessing deallocated memory or memory leaks! + * + * @param pcb the tcp pcb to abort + */ +void +tcp_abort(struct tcp_pcb *pcb) +{ + tcp_abandon(pcb, 1); +} + +/** + * Binds the connection to a local portnumber and IP address. If the + * IP address is not given (i.e., ipaddr == NULL), the IP address of + * the outgoing network interface is used instead. + * + * @param pcb the tcp_pcb to bind (no check is done whether this pcb is + * already bound!) + * @param ipaddr the local ip address to bind to (use IP_ADDR_ANY to bind + * to any local address + * @param port the local port to bind to + * @return ERR_USE if the port is already in use + * ERR_VAL if bind failed because the PCB is not in a valid state + * ERR_OK if bound + */ +err_t +tcp_bind(struct tcp_pcb *pcb, ip_addr_t *ipaddr, u16_t port) +{ + int i; + int max_pcb_list = NUM_TCP_PCB_LISTS; + struct tcp_pcb *cpcb; + + LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_VAL); + +#if SO_REUSE + /* Unless the REUSEADDR flag is set, + we have to check the pcbs in TIME-WAIT state, also. + We do not dump TIME_WAIT pcb's; they can still be matched by incoming + packets using both local and remote IP addresses and ports to distinguish. + */ + if ((pcb->so_options & SOF_REUSEADDR) != 0) { + max_pcb_list = NUM_TCP_PCB_LISTS_NO_TIME_WAIT; + } +#endif /* SO_REUSE */ + + if (port == 0) { + port = tcp_new_port(); + } + + /* Check if the address already is in use (on all lists) */ + for (i = 0; i < max_pcb_list; i++) { + for(cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { +#if SO_REUSE + /* Omit checking for the same port if both pcbs have REUSEADDR set. + For SO_REUSEADDR, the duplicate-check for a 5-tuple is done in + tcp_connect. */ + if (((pcb->so_options & SOF_REUSEADDR) == 0) || + ((cpcb->so_options & SOF_REUSEADDR) == 0)) +#endif /* SO_REUSE */ + { + if (ip_addr_isany(&(cpcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { + return ERR_USE; + } + } + } + } + } + + if (!ip_addr_isany(ipaddr)) { + pcb->local_ip = *ipaddr; + } + pcb->local_port = port; + TCP_REG(&tcp_bound_pcbs, pcb); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); + return ERR_OK; +} +#if LWIP_CALLBACK_API +/** + * Default accept callback if no accept callback is specified by the user. + */ +static err_t +tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err) +{ + LWIP_UNUSED_ARG(arg); + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(err); + + return ERR_ABRT; +} +#endif /* LWIP_CALLBACK_API */ + +/** + * Set the state of the connection to be LISTEN, which means that it + * is able to accept incoming connections. The protocol control block + * is reallocated in order to consume less memory. Setting the + * connection to LISTEN is an irreversible process. + * + * @param pcb the original tcp_pcb + * @param backlog the incoming connections queue limit + * @return tcp_pcb used for listening, consumes less memory. + * + * @note The original tcp_pcb is freed. This function therefore has to be + * called like this: + * tpcb = tcp_listen(tpcb); + */ +struct tcp_pcb * +tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog) +{ + struct tcp_pcb_listen *lpcb; + + LWIP_UNUSED_ARG(backlog); + LWIP_ERROR("tcp_listen: pcb already connected", pcb->state == CLOSED, return NULL); + + /* already listening? */ + if (pcb->state == LISTEN) { + return pcb; + } +#if SO_REUSE + if ((pcb->so_options & SOF_REUSEADDR) != 0) { + /* Since SOF_REUSEADDR allows reusing a local address before the pcb's usage + is declared (listen-/connection-pcb), we have to make sure now that + this port is only used once for every local IP. */ + for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + if (lpcb->local_port == pcb->local_port) { + if (ip_addr_cmp(&lpcb->local_ip, &pcb->local_ip)) { + /* this address/port is already used */ + return NULL; + } + } + } + } +#endif /* SO_REUSE */ + lpcb = (struct tcp_pcb_listen *)memp_malloc(MEMP_TCP_PCB_LISTEN); + if (lpcb == NULL) { + return NULL; + } + lpcb->callback_arg = pcb->callback_arg; + lpcb->local_port = pcb->local_port; + lpcb->state = LISTEN; + lpcb->prio = pcb->prio; + lpcb->so_options = pcb->so_options; + lpcb->so_options |= SOF_ACCEPTCONN; + lpcb->ttl = pcb->ttl; + lpcb->tos = pcb->tos; + ip_addr_copy(lpcb->local_ip, pcb->local_ip); + if (pcb->local_port != 0) { + TCP_RMV(&tcp_bound_pcbs, pcb); + } + memp_free(MEMP_TCP_PCB, pcb); +#if LWIP_CALLBACK_API + lpcb->accept = tcp_accept_null; +#endif /* LWIP_CALLBACK_API */ +#if TCP_LISTEN_BACKLOG + lpcb->accepts_pending = 0; + lpcb->backlog = (backlog ? backlog : 1); +#endif /* TCP_LISTEN_BACKLOG */ + TCP_REG(&tcp_listen_pcbs.pcbs, (struct tcp_pcb *)lpcb); + return (struct tcp_pcb *)lpcb; +} + +/** + * Update the state that tracks the available window space to advertise. + * + * Returns how much extra window would be advertised if we sent an + * update now. + */ +u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb) +{ + u32_t new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd; + + if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) { + /* we can advertise more window */ + pcb->rcv_ann_wnd = pcb->rcv_wnd; + return new_right_edge - pcb->rcv_ann_right_edge; + } else { + if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) { + /* Can happen due to other end sending out of advertised window, + * but within actual available (but not yet advertised) window */ + pcb->rcv_ann_wnd = 0; + } else { + /* keep the right edge of window constant */ + u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt; + LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff); + pcb->rcv_ann_wnd = (u16_t)new_rcv_ann_wnd; + } + return 0; + } +} + +/** + * This function should be called by the application when it has + * processed the data. The purpose is to advertise a larger window + * when the data has been processed. + * + * @param pcb the tcp_pcb for which data is read + * @param len the amount of bytes that have been read by the application + */ +void +tcp_recved(struct tcp_pcb *pcb, u16_t len) +{ + int wnd_inflation; + + LWIP_ASSERT("tcp_recved: len would wrap rcv_wnd\n", + len <= 0xffff - pcb->rcv_wnd ); + + pcb->rcv_wnd += len; + if (pcb->rcv_wnd > TCP_WND) { + pcb->rcv_wnd = TCP_WND; + } + + wnd_inflation = tcp_update_rcv_ann_wnd(pcb); + + /* If the change in the right edge of window is significant (default + * watermark is TCP_WND/4), then send an explicit update now. + * Otherwise wait for a packet to be sent in the normal course of + * events (or more window to be available later) */ + if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) { + tcp_ack_now(pcb); + tcp_output(pcb); + } + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n", + len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd)); +} + +/** + * A nastly hack featuring 'goto' statements that allocates a + * new TCP local port. + * + * @return a new (free) local TCP port number + */ +static u16_t +tcp_new_port(void) +{ + int i; + struct tcp_pcb *pcb; +#ifndef TCP_LOCAL_PORT_RANGE_START +/* From http://www.iana.org/assignments/port-numbers: + "The Dynamic and/or Private Ports are those from 49152 through 65535" */ +#define TCP_LOCAL_PORT_RANGE_START 0xc000 +#define TCP_LOCAL_PORT_RANGE_END 0xffff +#endif + static u16_t port = TCP_LOCAL_PORT_RANGE_START; + + again: + if (port++ >= TCP_LOCAL_PORT_RANGE_END) { + port = TCP_LOCAL_PORT_RANGE_START; + } + /* Check all PCB lists. */ + for (i = 0; i < NUM_TCP_PCB_LISTS; i++) { + for(pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + } + return port; +} + +/** + * Connects to another host. The function given as the "connected" + * argument will be called when the connection has been established. + * + * @param pcb the tcp_pcb used to establish the connection + * @param ipaddr the remote ip address to connect to + * @param port the remote tcp port to connect to + * @param connected callback function to call when connected (or on error) + * @return ERR_VAL if invalid arguments are given + * ERR_OK if connect request has been sent + * other err_t values if connect request couldn't be sent + */ +err_t +tcp_connect(struct tcp_pcb *pcb, ip_addr_t *ipaddr, u16_t port, + tcp_connected_fn connected) +{ + err_t ret; + u32_t iss; + u16_t old_local_port; + + LWIP_ERROR("tcp_connect: can only connect from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); + if (ipaddr != NULL) { + pcb->remote_ip = *ipaddr; + } else { + return ERR_VAL; + } + pcb->remote_port = port; + + /* check if we have a route to the remote host */ + if (ip_addr_isany(&(pcb->local_ip))) { + /* no local IP address set, yet. */ + struct netif *netif = ip_route(&(pcb->remote_ip)); + if (netif == NULL) { + /* Don't even try to send a SYN packet if we have no route + since that will fail. */ + return ERR_RTE; + } + /* Use the netif's IP address as local address. */ + ip_addr_copy(pcb->local_ip, netif->ip_addr); + } + + old_local_port = pcb->local_port; + if (pcb->local_port == 0) { + pcb->local_port = tcp_new_port(); + } +#if SO_REUSE + if ((pcb->so_options & SOF_REUSEADDR) != 0) { + /* Since SOF_REUSEADDR allows reusing a local address, we have to make sure + now that the 5-tuple is unique. */ + struct tcp_pcb *cpcb; + int i; + /* Don't check listen- and bound-PCBs, check active- and TIME-WAIT PCBs. */ + for (i = 2; i < NUM_TCP_PCB_LISTS; i++) { + for(cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) { + if ((cpcb->local_port == pcb->local_port) && + (cpcb->remote_port == port) && + ip_addr_cmp(&cpcb->local_ip, &pcb->local_ip) && + ip_addr_cmp(&cpcb->remote_ip, ipaddr)) { + /* linux returns EISCONN here, but ERR_USE should be OK for us */ + return ERR_USE; + } + } + } + } +#endif /* SO_REUSE */ + iss = tcp_next_iss(); + pcb->rcv_nxt = 0; + pcb->snd_nxt = iss; + pcb->lastack = iss - 1; + pcb->snd_lbb = iss - 1; + pcb->rcv_wnd = TCP_WND; + pcb->rcv_ann_wnd = TCP_WND; + pcb->rcv_ann_right_edge = pcb->rcv_nxt; + pcb->snd_wnd = TCP_WND; + /* As initial send MSS, we use TCP_MSS but limit it to 536. + The send MSS is updated when an MSS option is received. */ + pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS; +#if TCP_CALCULATE_EFF_SEND_MSS + pcb->mss = tcp_eff_send_mss(pcb->mss, ipaddr); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + pcb->cwnd = 1; + pcb->ssthresh = pcb->mss * 10; +#if LWIP_CALLBACK_API + pcb->connected = connected; +#else /* LWIP_CALLBACK_API */ + LWIP_UNUSED_ARG(connected); +#endif /* LWIP_CALLBACK_API */ + + /* Send a SYN together with the MSS option. */ + ret = tcp_enqueue_flags(pcb, TCP_SYN); + if (ret == ERR_OK) { + /* SYN segment was enqueued, changed the pcbs state now */ + pcb->state = SYN_SENT; + if (old_local_port != 0) { + TCP_RMV(&tcp_bound_pcbs, pcb); + } + TCP_REG(&tcp_active_pcbs, pcb); + snmp_inc_tcpactiveopens(); + + tcp_output(pcb); + } + return ret; +} + +/** + * Called every 500 ms and implements the retransmission timer and the timer that + * removes PCBs that have been in TIME-WAIT for enough time. It also increments + * various timers such as the inactivity timer in each PCB. + * + * Automatically called from tcp_tmr(). + */ +void +tcp_slowtmr(void) +{ + struct tcp_pcb *pcb, *prev; + u16_t eff_wnd; + u8_t pcb_remove; /* flag if a PCB should be removed */ + u8_t pcb_reset; /* flag if a RST should be sent when removing */ + err_t err; + + err = ERR_OK; + + ++tcp_ticks; + + /* Steps through all of the active PCBs. */ + prev = NULL; + pcb = tcp_active_pcbs; + if (pcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); + } + while (pcb != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); + + pcb_remove = 0; + pcb_reset = 0; + + if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); + } + else if (pcb->nrtx == TCP_MAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); + } else { + if (pcb->persist_backoff > 0) { + /* If snd_wnd is zero, use persist timer to send 1 byte probes + * instead of using the standard retransmission mechanism. */ + pcb->persist_cnt++; + if (pcb->persist_cnt >= tcp_persist_backoff[pcb->persist_backoff-1]) { + pcb->persist_cnt = 0; + if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) { + pcb->persist_backoff++; + } + tcp_zero_window_probe(pcb); + } + } else { + /* Increase the retransmission timer if it is running */ + if(pcb->rtime >= 0) + ++pcb->rtime; + + if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) { + /* Time for a retransmission. */ + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"S16_F + " pcb->rto %"S16_F"\n", + pcb->rtime, pcb->rto)); + + /* Double retransmission time-out unless we are trying to + * connect to somebody (i.e., we are in SYN_SENT). */ + if (pcb->state != SYN_SENT) { + pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx]; + } + + /* Reset the retransmission timer. */ + pcb->rtime = 0; + + /* Reduce congestion window and ssthresh. */ + eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); + pcb->ssthresh = eff_wnd >> 1; + if (pcb->ssthresh < (pcb->mss << 1)) { + pcb->ssthresh = (pcb->mss << 1); + } + pcb->cwnd = pcb->mss; + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F + " ssthresh %"U16_F"\n", + pcb->cwnd, pcb->ssthresh)); + + /* The following needs to be called AFTER cwnd is set to one + mss - STJ */ + tcp_rexmit_rto(pcb); + } + } + } + /* Check if this PCB has stayed too long in FIN-WAIT-2 */ + if (pcb->state == FIN_WAIT_2) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n")); + } + } + + /* Check if KEEPALIVE should be sent */ + if((pcb->so_options & SOF_KEEPALIVE) && + ((pcb->state == ESTABLISHED) || + (pcb->state == CLOSE_WAIT))) { +#if LWIP_TCP_KEEPALIVE + if((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + (pcb->keep_cnt*pcb->keep_intvl)) + / TCP_SLOW_INTERVAL) +#else + if((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + TCP_MAXIDLE) / TCP_SLOW_INTERVAL) +#endif /* LWIP_TCP_KEEPALIVE */ + { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n", + ip4_addr1_16(&pcb->remote_ip), ip4_addr2_16(&pcb->remote_ip), + ip4_addr3_16(&pcb->remote_ip), ip4_addr4_16(&pcb->remote_ip))); + + ++pcb_remove; + ++pcb_reset; + } +#if LWIP_TCP_KEEPALIVE + else if((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + pcb->keep_cnt_sent * pcb->keep_intvl) + / TCP_SLOW_INTERVAL) +#else + else if((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEPINTVL_DEFAULT) + / TCP_SLOW_INTERVAL) +#endif /* LWIP_TCP_KEEPALIVE */ + { + tcp_keepalive(pcb); + pcb->keep_cnt_sent++; + } + } + + /* If this PCB has queued out of sequence data, but has been + inactive for too long, will drop the data (it will eventually + be retransmitted). */ +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL && + (u32_t)tcp_ticks - pcb->tmr >= pcb->rto * TCP_OOSEQ_TIMEOUT) { + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Check if this PCB has stayed too long in SYN-RCVD */ + if (pcb->state == SYN_RCVD) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); + } + } + + /* Check if this PCB has stayed too long in LAST-ACK */ + if (pcb->state == LAST_ACK) { + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); + } + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + struct tcp_pcb *pcb2; + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_active_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); + tcp_active_pcbs = pcb->next; + } + + TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT); + if (pcb_reset) { + tcp_rst(pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, + pcb->local_port, pcb->remote_port); + } + + pcb2 = pcb; + pcb = pcb->next; + memp_free(MEMP_TCP_PCB, pcb2); + } else { + /* get the 'next' element now and work with 'prev' below (in case of abort) */ + prev = pcb; + pcb = pcb->next; + + /* We check if we should poll the connection. */ + ++prev->polltmr; + if (prev->polltmr >= prev->pollinterval) { + prev->polltmr = 0; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); + TCP_EVENT_POLL(prev, err); + /* if err == ERR_ABRT, 'prev' is already deallocated */ + if (err == ERR_OK) { + tcp_output(prev); + } + } + } + } + + + /* Steps through all of the TIME-WAIT PCBs. */ + prev = NULL; + pcb = tcp_tw_pcbs; + while (pcb != NULL) { + LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + pcb_remove = 0; + + /* Check if this PCB has stayed long enough in TIME-WAIT */ + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + } + + + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + struct tcp_pcb *pcb2; + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_tw_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); + tcp_tw_pcbs = pcb->next; + } + pcb2 = pcb; + pcb = pcb->next; + memp_free(MEMP_TCP_PCB, pcb2); + } else { + prev = pcb; + pcb = pcb->next; + } + } +} + +/** + * Is called every TCP_FAST_INTERVAL (250 ms) and process data previously + * "refused" by upper layer (application) and sends delayed ACKs. + * + * Automatically called from tcp_tmr(). + */ +void +tcp_fasttmr(void) +{ + struct tcp_pcb *pcb = tcp_active_pcbs; + + while(pcb != NULL) { + struct tcp_pcb *next = pcb->next; + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + /* Notify again application with data previously received. */ + err_t err; + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_fasttmr: notify kept packet\n")); + TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err); + if (err == ERR_OK) { + pcb->refused_data = NULL; + } else if (err == ERR_ABRT) { + /* if err == ERR_ABRT, 'pcb' is already deallocated */ + pcb = NULL; + } + } + + /* send delayed ACKs */ + if (pcb && (pcb->flags & TF_ACK_DELAY)) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); + tcp_ack_now(pcb); + tcp_output(pcb); + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + } + + pcb = next; + } +} + +/** + * Deallocates a list of TCP segments (tcp_seg structures). + * + * @param seg tcp_seg list of TCP segments to free + */ +void +tcp_segs_free(struct tcp_seg *seg) +{ + while (seg != NULL) { + struct tcp_seg *next = seg->next; + tcp_seg_free(seg); + seg = next; + } +} + +/** + * Frees a TCP segment (tcp_seg structure). + * + * @param seg single tcp_seg to free + */ +void +tcp_seg_free(struct tcp_seg *seg) +{ + if (seg != NULL) { + if (seg->p != NULL) { + pbuf_free(seg->p); +#if TCP_DEBUG + seg->p = NULL; +#endif /* TCP_DEBUG */ + } + memp_free(MEMP_TCP_SEG, seg); + } +} + +/** + * Sets the priority of a connection. + * + * @param pcb the tcp_pcb to manipulate + * @param prio new priority + */ +void +tcp_setprio(struct tcp_pcb *pcb, u8_t prio) +{ + pcb->prio = prio; +} + +#if TCP_QUEUE_OOSEQ +/** + * Returns a copy of the given TCP segment. + * The pbuf and data are not copied, only the pointers + * + * @param seg the old tcp_seg + * @return a copy of seg + */ +struct tcp_seg * +tcp_seg_copy(struct tcp_seg *seg) +{ + struct tcp_seg *cseg; + + cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG); + if (cseg == NULL) { + return NULL; + } + SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); + pbuf_ref(cseg->p); + return cseg; +} +#endif /* TCP_QUEUE_OOSEQ */ + +#if LWIP_CALLBACK_API +/** + * Default receive callback that is called if the user didn't register + * a recv callback for the pcb. + */ +err_t +tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + LWIP_UNUSED_ARG(arg); + if (p != NULL) { + tcp_recved(pcb, p->tot_len); + pbuf_free(p); + } else if (err == ERR_OK) { + return tcp_close(pcb); + } + return ERR_OK; +} +#endif /* LWIP_CALLBACK_API */ + +/** + * Kills the oldest active connection that has lower priority than prio. + * + * @param prio minimum priority + */ +static void +tcp_kill_prio(u8_t prio) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + u8_t mprio; + + + mprio = TCP_PRIO_MAX; + + /* We kill the oldest active connection that has lower priority than prio. */ + inactivity = 0; + inactive = NULL; + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->prio <= prio && + pcb->prio <= mprio && + (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + mprio = pcb->prio; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + +/** + * Kills the oldest connection that is in TIME_WAIT state. + * Called from tcp_alloc() if no more connections are available. + */ +static void +tcp_kill_timewait(void) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + inactivity = 0; + inactive = NULL; + /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */ + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + +/** + * Allocate a new tcp_pcb structure. + * + * @param prio priority for the new pcb + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_alloc(u8_t prio) +{ + struct tcp_pcb *pcb; + u32_t iss; + + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try killing oldest connection in TIME-WAIT. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); + tcp_kill_timewait(); + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try killing active connections with lower priority than the new one. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing connection with prio lower than %d\n", prio)); + tcp_kill_prio(prio); + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + if (pcb != NULL) { + /* adjust err stats: memp_malloc failed twice before */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + /* adjust err stats: timewait PCB was freed above */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + memset(pcb, 0, sizeof(struct tcp_pcb)); + pcb->prio = prio; + pcb->snd_buf = TCP_SND_BUF; + pcb->snd_queuelen = 0; + pcb->rcv_wnd = TCP_WND; + pcb->rcv_ann_wnd = TCP_WND; + pcb->tos = 0; + pcb->ttl = TCP_TTL; + /* As initial send MSS, we use TCP_MSS but limit it to 536. + The send MSS is updated when an MSS option is received. */ + pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS; + pcb->rto = 3000 / TCP_SLOW_INTERVAL; + pcb->sa = 0; + pcb->sv = 3000 / TCP_SLOW_INTERVAL; + pcb->rtime = -1; + pcb->cwnd = 1; + iss = tcp_next_iss(); + pcb->snd_wl2 = iss; + pcb->snd_nxt = iss; + pcb->lastack = iss; + pcb->snd_lbb = iss; + pcb->tmr = tcp_ticks; + + pcb->polltmr = 0; + +#if LWIP_CALLBACK_API + pcb->recv = tcp_recv_null; +#endif /* LWIP_CALLBACK_API */ + + /* Init KEEPALIVE timer */ + pcb->keep_idle = TCP_KEEPIDLE_DEFAULT; + +#if LWIP_TCP_KEEPALIVE + pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT; + pcb->keep_cnt = TCP_KEEPCNT_DEFAULT; +#endif /* LWIP_TCP_KEEPALIVE */ + + pcb->keep_cnt_sent = 0; + } + return pcb; +} + +/** + * Creates a new TCP protocol control block but doesn't place it on + * any of the TCP PCB lists. + * The pcb is not put on any list until binding using tcp_bind(). + * + * @internal: Maybe there should be a idle TCP PCB list where these + * PCBs are put on. Port reservation using tcp_bind() is implemented but + * allocated pcbs that are not bound can't be killed automatically if wanting + * to allocate a pcb with higher prio (@see tcp_kill_prio()) + * + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_new(void) +{ + return tcp_alloc(TCP_PRIO_NORMAL); +} + +/** + * Used to specify the argument that should be passed callback + * functions. + * + * @param pcb tcp_pcb to set the callback argument + * @param arg void pointer argument to pass to callback functions + */ +void +tcp_arg(struct tcp_pcb *pcb, void *arg) +{ + pcb->callback_arg = arg; +} +#if LWIP_CALLBACK_API + +/** + * Used to specify the function that should be called when a TCP + * connection receives data. + * + * @param pcb tcp_pcb to set the recv callback + * @param recv callback function to call for this pcb when data is received + */ +void +tcp_recv(struct tcp_pcb *pcb, tcp_recv_fn recv) +{ + pcb->recv = recv; +} + +/** + * Used to specify the function that should be called when TCP data + * has been successfully delivered to the remote host. + * + * @param pcb tcp_pcb to set the sent callback + * @param sent callback function to call for this pcb when data is successfully sent + */ +void +tcp_sent(struct tcp_pcb *pcb, tcp_sent_fn sent) +{ + pcb->sent = sent; +} + +/** + * Used to specify the function that should be called when a fatal error + * has occured on the connection. + * + * @param pcb tcp_pcb to set the err callback + * @param err callback function to call for this pcb when a fatal error + * has occured on the connection + */ +void +tcp_err(struct tcp_pcb *pcb, tcp_err_fn err) +{ + pcb->errf = err; +} + +/** + * Used for specifying the function that should be called when a + * LISTENing connection has been connected to another host. + * + * @param pcb tcp_pcb to set the accept callback + * @param accept callback function to call for this pcb when LISTENing + * connection has been connected to another host + */ +void +tcp_accept(struct tcp_pcb *pcb, tcp_accept_fn accept) +{ + pcb->accept = accept; +} +#endif /* LWIP_CALLBACK_API */ + + +/** + * Used to specify the function that should be called periodically + * from TCP. The interval is specified in terms of the TCP coarse + * timer interval, which is called twice a second. + * + */ +void +tcp_poll(struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval) +{ +#if LWIP_CALLBACK_API + pcb->poll = poll; +#else /* LWIP_CALLBACK_API */ + LWIP_UNUSED_ARG(poll); +#endif /* LWIP_CALLBACK_API */ + pcb->pollinterval = interval; +} + +/** + * Purges a TCP PCB. Removes any buffered data and frees the buffer memory + * (pcb->ooseq, pcb->unsent and pcb->unacked are freed). + * + * @param pcb tcp_pcb to purge. The pcb itself is not deallocated! + */ +void +tcp_pcb_purge(struct tcp_pcb *pcb) +{ + if (pcb->state != CLOSED && + pcb->state != TIME_WAIT && + pcb->state != LISTEN) { + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); + +#if TCP_LISTEN_BACKLOG + if (pcb->state == SYN_RCVD) { + /* Need to find the corresponding listen_pcb and decrease its accepts_pending */ + struct tcp_pcb_listen *lpcb; + LWIP_ASSERT("tcp_pcb_purge: pcb->state == SYN_RCVD but tcp_listen_pcbs is NULL", + tcp_listen_pcbs.listen_pcbs != NULL); + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + if ((lpcb->local_port == pcb->local_port) && + (ip_addr_isany(&lpcb->local_ip) || + ip_addr_cmp(&pcb->local_ip, &lpcb->local_ip))) { + /* port and address of the listen pcb match the timed-out pcb */ + LWIP_ASSERT("tcp_pcb_purge: listen pcb does not have accepts pending", + lpcb->accepts_pending > 0); + lpcb->accepts_pending--; + break; + } + } + } +#endif /* TCP_LISTEN_BACKLOG */ + + + if (pcb->refused_data != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n")); + pbuf_free(pcb->refused_data); + pcb->refused_data = NULL; + } + if (pcb->unsent != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n")); + } + if (pcb->unacked != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); + } + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; +#endif /* TCP_QUEUE_OOSEQ */ + + /* Stop the retransmission timer as it will expect data on unacked + queue if it fires */ + pcb->rtime = -1; + + tcp_segs_free(pcb->unsent); + tcp_segs_free(pcb->unacked); + pcb->unacked = pcb->unsent = NULL; +#if TCP_OVERSIZE + pcb->unsent_oversize = 0; +#endif /* TCP_OVERSIZE */ + } +} + +/** + * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first. + * + * @param pcblist PCB list to purge. + * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated! + */ +void +tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) +{ + TCP_RMV(pcblist, pcb); + + tcp_pcb_purge(pcb); + + /* if there is an outstanding delayed ACKs, send it */ + if (pcb->state != TIME_WAIT && + pcb->state != LISTEN && + pcb->flags & TF_ACK_DELAY) { + pcb->flags |= TF_ACK_NOW; + tcp_output(pcb); + } + + if (pcb->state != LISTEN) { + LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL); + LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL); +#if TCP_QUEUE_OOSEQ + LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL); +#endif /* TCP_QUEUE_OOSEQ */ + } + + pcb->state = CLOSED; + + LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); +} + +/** + * Calculates a new initial sequence number for new connections. + * + * @return u32_t pseudo random sequence number + */ +u32_t +tcp_next_iss(void) +{ + static u32_t iss = 6510; + + iss += tcp_ticks; /* XXX */ + return iss; +} + +#if TCP_CALCULATE_EFF_SEND_MSS +/** + * Calcluates the effective send mss that can be used for a specific IP address + * by using ip_route to determin the netif used to send to the address and + * calculating the minimum of TCP_MSS and that netif's mtu (if set). + */ +u16_t +tcp_eff_send_mss(u16_t sendmss, ip_addr_t *addr) +{ + u16_t mss_s; + struct netif *outif; + + outif = ip_route(addr); + if ((outif != NULL) && (outif->mtu != 0)) { + mss_s = outif->mtu - IP_HLEN - TCP_HLEN; + /* RFC 1122, chap 4.2.2.6: + * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize + * We correct for TCP options in tcp_write(), and don't support IP options. + */ + sendmss = LWIP_MIN(sendmss, mss_s); + } + return sendmss; +} +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +const char* +tcp_debug_state_str(enum tcp_state s) +{ + return tcp_state_str[s]; +} + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +/** + * Print a tcp header for debugging purposes. + * + * @param tcphdr pointer to a struct tcp_hdr + */ +void +tcp_debug_print(struct tcp_hdr *tcphdr) +{ + LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + ntohs(tcphdr->src), ntohs(tcphdr->dest))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", + ntohl(tcphdr->seqno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", + ntohl(tcphdr->ackno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", + TCPH_HDRLEN(tcphdr), + TCPH_FLAGS(tcphdr) >> 5 & 1, + TCPH_FLAGS(tcphdr) >> 4 & 1, + TCPH_FLAGS(tcphdr) >> 3 & 1, + TCPH_FLAGS(tcphdr) >> 2 & 1, + TCPH_FLAGS(tcphdr) >> 1 & 1, + TCPH_FLAGS(tcphdr) & 1, + ntohs(tcphdr->wnd))); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", + ntohs(tcphdr->chksum), ntohs(tcphdr->urgp))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +} + +/** + * Print a tcp state for debugging purposes. + * + * @param s enum tcp_state to print + */ +void +tcp_debug_print_state(enum tcp_state s) +{ + LWIP_DEBUGF(TCP_DEBUG, ("State: %s\n", tcp_state_str[s])); +} + +/** + * Print tcp flags for debugging purposes. + * + * @param flags tcp flags, all active flags are printed + */ +void +tcp_debug_print_flags(u8_t flags) +{ + if (flags & TCP_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("FIN ")); + } + if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("SYN ")); + } + if (flags & TCP_RST) { + LWIP_DEBUGF(TCP_DEBUG, ("RST ")); + } + if (flags & TCP_PSH) { + LWIP_DEBUGF(TCP_DEBUG, ("PSH ")); + } + if (flags & TCP_ACK) { + LWIP_DEBUGF(TCP_DEBUG, ("ACK ")); + } + if (flags & TCP_URG) { + LWIP_DEBUGF(TCP_DEBUG, ("URG ")); + } + if (flags & TCP_ECE) { + LWIP_DEBUGF(TCP_DEBUG, ("ECE ")); + } + if (flags & TCP_CWR) { + LWIP_DEBUGF(TCP_DEBUG, ("CWR ")); + } + LWIP_DEBUGF(TCP_DEBUG, ("\n")); +} + +/** + * Print all tcp_pcbs in every list for debugging purposes. + */ +void +tcp_debug_print_pcbs(void) +{ + struct tcp_pcb *pcb; + LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); + for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } +} + +/** + * Check state consistency of the tcp_pcb lists. + */ +s16_t +tcp_pcbs_sane(void) +{ + struct tcp_pcb *pcb; + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + } + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + } + return 1; +} +#endif /* TCP_DEBUG */ + +#endif /* LWIP_TCP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/tcp_in.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/tcp_in.c new file mode 100644 index 0000000..9095264 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/tcp_in.c @@ -0,0 +1,1567 @@ +/** + * @file + * Transmission Control Protocol, incoming traffic + * + * The input processing functions of the TCP layer. + * + * These functions are generally called in the order (ip_input() ->) + * tcp_input() -> * tcp_process() -> tcp_receive() (-> application). + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcp_impl.h" +#include "lwip/def.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/inet_chksum.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "arch/perf.h" + +/* These variables are global to all functions involved in the input + processing of TCP segments. They are set by the tcp_input() + function. */ +static struct tcp_seg inseg; +static struct tcp_hdr *tcphdr; +static struct ip_hdr *iphdr; +static u32_t seqno, ackno; +static u8_t flags; +static u16_t tcplen; + +static u8_t recv_flags; +static struct pbuf *recv_data; + +struct tcp_pcb *tcp_input_pcb; + +/* Forward declarations. */ +static err_t tcp_process(struct tcp_pcb *pcb); +static void tcp_receive(struct tcp_pcb *pcb); +static void tcp_parseopt(struct tcp_pcb *pcb); + +static err_t tcp_listen_input(struct tcp_pcb_listen *pcb); +static err_t tcp_timewait_input(struct tcp_pcb *pcb); + +/** + * The initial input processing of TCP. It verifies the TCP header, demultiplexes + * the segment between the PCBs and passes it on to tcp_process(), which implements + * the TCP finite state machine. This function is called by the IP layer (in + * ip_input()). + * + * @param p received TCP segment to process (p->payload pointing to the IP header) + * @param inp network interface on which this segment was received + */ +void +tcp_input(struct pbuf *p, struct netif *inp) +{ + struct tcp_pcb *pcb, *prev; + struct tcp_pcb_listen *lpcb; +#if SO_REUSE + struct tcp_pcb *lpcb_prev = NULL; + struct tcp_pcb_listen *lpcb_any = NULL; +#endif /* SO_REUSE */ + u8_t hdrlen; + err_t err; + + PERF_START; + + TCP_STATS_INC(tcp.recv); + snmp_inc_tcpinsegs(); + + iphdr = (struct ip_hdr *)p->payload; + tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4); + +#if TCP_INPUT_DEBUG + tcp_debug_print(tcphdr); +#endif + + /* remove header from payload */ + if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) { + /* drop short packets */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); + TCP_STATS_INC(tcp.lenerr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + + /* Don't even process incoming broadcasts/multicasts. */ + if (ip_addr_isbroadcast(¤t_iphdr_dest, inp) || + ip_addr_ismulticast(¤t_iphdr_dest)) { + TCP_STATS_INC(tcp.proterr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + +#if CHECKSUM_CHECK_TCP + /* Verify TCP checksum. */ + if (inet_chksum_pseudo(p, ip_current_src_addr(), ip_current_dest_addr(), + IP_PROTO_TCP, p->tot_len) != 0) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", + inet_chksum_pseudo(p, ip_current_src_addr(), ip_current_dest_addr(), + IP_PROTO_TCP, p->tot_len))); +#if TCP_DEBUG + tcp_debug_print(tcphdr); +#endif /* TCP_DEBUG */ + TCP_STATS_INC(tcp.chkerr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } +#endif + + /* Move the payload pointer in the pbuf so that it points to the + TCP data instead of the TCP header. */ + hdrlen = TCPH_HDRLEN(tcphdr); + if(pbuf_header(p, -(hdrlen * 4))){ + /* drop short packets */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet\n")); + TCP_STATS_INC(tcp.lenerr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + + /* Convert fields in TCP header to host byte order. */ + tcphdr->src = ntohs(tcphdr->src); + tcphdr->dest = ntohs(tcphdr->dest); + seqno = tcphdr->seqno = ntohl(tcphdr->seqno); + ackno = tcphdr->ackno = ntohl(tcphdr->ackno); + tcphdr->wnd = ntohs(tcphdr->wnd); + + flags = TCPH_FLAGS(tcphdr); + tcplen = p->tot_len + ((flags & (TCP_FIN | TCP_SYN)) ? 1 : 0); + + /* Demultiplex an incoming segment. First, we check if it is destined + for an active connection. */ + prev = NULL; + + + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&(pcb->remote_ip), ¤t_iphdr_src) && + ip_addr_cmp(&(pcb->local_ip), ¤t_iphdr_dest)) { + + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); + if (prev != NULL) { + prev->next = pcb->next; + pcb->next = tcp_active_pcbs; + tcp_active_pcbs = pcb; + } + LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); + break; + } + prev = pcb; + } + + if (pcb == NULL) { + /* If it did not go to an active connection, we check the connections + in the TIME-WAIT state. */ + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&(pcb->remote_ip), ¤t_iphdr_src) && + ip_addr_cmp(&(pcb->local_ip), ¤t_iphdr_dest)) { + /* We don't really care enough to move this PCB to the front + of the list since we are not very likely to receive that + many segments for connections in TIME-WAIT. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n")); + tcp_timewait_input(pcb); + pbuf_free(p); + return; + } + } + + /* Finally, if we still did not get a match, we check all PCBs that + are LISTENing for incoming connections. */ + prev = NULL; + for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + if (lpcb->local_port == tcphdr->dest) { +#if SO_REUSE + if (ip_addr_cmp(&(lpcb->local_ip), ¤t_iphdr_dest)) { + /* found an exact match */ + break; + } else if(ip_addr_isany(&(lpcb->local_ip))) { + /* found an ANY-match */ + lpcb_any = lpcb; + lpcb_prev = prev; + } +#else /* SO_REUSE */ + if (ip_addr_cmp(&(lpcb->local_ip), ¤t_iphdr_dest) || + ip_addr_isany(&(lpcb->local_ip))) { + /* found a match */ + break; + } +#endif /* SO_REUSE */ + } + prev = (struct tcp_pcb *)lpcb; + } +#if SO_REUSE + /* first try specific local IP */ + if (lpcb == NULL) { + /* only pass to ANY if no specific local IP has been found */ + lpcb = lpcb_any; + prev = lpcb_prev; + } +#endif /* SO_REUSE */ + if (lpcb != NULL) { + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + if (prev != NULL) { + ((struct tcp_pcb_listen *)prev)->next = lpcb->next; + /* our successor is the remainder of the listening list */ + lpcb->next = tcp_listen_pcbs.listen_pcbs; + /* put this listening pcb at the head of the listening list */ + tcp_listen_pcbs.listen_pcbs = lpcb; + } + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n")); + tcp_listen_input(lpcb); + pbuf_free(p); + return; + } + } + +#if TCP_INPUT_DEBUG + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags ")); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n")); +#endif /* TCP_INPUT_DEBUG */ + + + if (pcb != NULL) { + /* The incoming segment belongs to a connection. */ +#if TCP_INPUT_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ +#endif /* TCP_INPUT_DEBUG */ + + /* Set up a tcp_seg structure. */ + inseg.next = NULL; + inseg.len = p->tot_len; + inseg.p = p; + inseg.tcphdr = tcphdr; + + recv_data = NULL; + recv_flags = 0; + + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + /* Notify again application with data previously received. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n")); + TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err); + if (err == ERR_OK) { + pcb->refused_data = NULL; + } else if ((err == ERR_ABRT) || (tcplen > 0)) { + /* if err == ERR_ABRT, 'pcb' is already deallocated */ + /* Drop incoming packets because pcb is "full" (only if the incoming + segment contains data). */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n")); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + } + tcp_input_pcb = pcb; + err = tcp_process(pcb); + /* A return value of ERR_ABRT means that tcp_abort() was called + and that the pcb has been freed. If so, we don't do anything. */ + if (err != ERR_ABRT) { + if (recv_flags & TF_RESET) { + /* TF_RESET means that the connection was reset by the other + end. We then call the error callback to inform the + application that the connection is dead before we + deallocate the PCB. */ + TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST); + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else if (recv_flags & TF_CLOSED) { + /* The connection has been closed and we will deallocate the + PCB. */ + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else { + err = ERR_OK; + /* If the application has registered a "sent" function to be + called when new send buffer space is available, we call it + now. */ + if (pcb->acked > 0) { + TCP_EVENT_SENT(pcb, pcb->acked, err); + if (err == ERR_ABRT) { + goto aborted; + } + } + + if (recv_data != NULL) { + LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL); + if (pcb->flags & TF_RXCLOSED) { + /* received data although already closed -> abort (send RST) to + notify the remote host that not all data has been processed */ + pbuf_free(recv_data); + tcp_abort(pcb); + goto aborted; + } + if (flags & TCP_PSH) { + recv_data->flags |= PBUF_FLAG_PUSH; + } + + /* Notify application that data has been received. */ + TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); + if (err == ERR_ABRT) { + goto aborted; + } + + /* If the upper layer can't receive this data, store it */ + if (err != ERR_OK) { + pcb->refused_data = recv_data; + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: keep incoming packet, because pcb is \"full\"\n")); + } + } + + /* If a FIN segment was received, we call the callback + function with a NULL buffer to indicate EOF. */ + if (recv_flags & TF_GOT_FIN) { + /* correct rcv_wnd as the application won't call tcp_recved() + for the FIN's seqno */ + if (pcb->rcv_wnd != TCP_WND) { + pcb->rcv_wnd++; + } + TCP_EVENT_CLOSED(pcb, err); + if (err == ERR_ABRT) { + goto aborted; + } + } + + tcp_input_pcb = NULL; + /* Try to send something out. */ + tcp_output(pcb); +#if TCP_INPUT_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ +#endif /* TCP_INPUT_DEBUG */ + } + } + /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()). + Below this line, 'pcb' may not be dereferenced! */ +aborted: + tcp_input_pcb = NULL; + recv_data = NULL; + + /* give up our reference to inseg.p */ + if (inseg.p != NULL) + { + pbuf_free(inseg.p); + inseg.p = NULL; + } + } else { + + /* If no matching PCB was found, send a TCP RST (reset) to the + sender. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); + if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { + TCP_STATS_INC(tcp.proterr); + TCP_STATS_INC(tcp.drop); + tcp_rst(ackno, seqno + tcplen, + ip_current_dest_addr(), ip_current_src_addr(), + tcphdr->dest, tcphdr->src); + } + pbuf_free(p); + } + + LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); + PERF_STOP("tcp_input"); +} + +/** + * Called by tcp_input() when a segment arrives for a listening + * connection (from tcp_input()). + * + * @param pcb the tcp_pcb_listen for which a segment arrived + * @return ERR_OK if the segment was processed + * another err_t on error + * + * @note the return value is not (yet?) used in tcp_input() + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static err_t +tcp_listen_input(struct tcp_pcb_listen *pcb) +{ + struct tcp_pcb *npcb; + err_t rc; + + /* In the LISTEN state, we check for incoming SYN segments, + creates a new PCB, and responds with a SYN|ACK. */ + if (flags & TCP_ACK) { + /* For incoming segments with the ACK flag set, respond with a + RST. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); + tcp_rst(ackno + 1, seqno + tcplen, + ip_current_dest_addr(), ip_current_src_addr(), + tcphdr->dest, tcphdr->src); + } else if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); +#if TCP_LISTEN_BACKLOG + if (pcb->accepts_pending >= pcb->backlog) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: listen backlog exceeded for port %"U16_F"\n", tcphdr->dest)); + return ERR_ABRT; + } +#endif /* TCP_LISTEN_BACKLOG */ + npcb = tcp_alloc(pcb->prio); + /* If a new PCB could not be created (probably due to lack of memory), + we don't do anything, but rely on the sender will retransmit the + SYN at a time when we have more memory available. */ + if (npcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n")); + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } +#if TCP_LISTEN_BACKLOG + pcb->accepts_pending++; +#endif /* TCP_LISTEN_BACKLOG */ + /* Set up the new PCB. */ + ip_addr_copy(npcb->local_ip, current_iphdr_dest); + npcb->local_port = pcb->local_port; + ip_addr_copy(npcb->remote_ip, current_iphdr_src); + npcb->remote_port = tcphdr->src; + npcb->state = SYN_RCVD; + npcb->rcv_nxt = seqno + 1; + npcb->rcv_ann_right_edge = npcb->rcv_nxt; + npcb->snd_wnd = tcphdr->wnd; + npcb->ssthresh = npcb->snd_wnd; + npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ + npcb->callback_arg = pcb->callback_arg; +#if LWIP_CALLBACK_API + npcb->accept = pcb->accept; +#endif /* LWIP_CALLBACK_API */ + /* inherit socket options */ + npcb->so_options = pcb->so_options & SOF_INHERITED; + /* Register the new PCB so that we can begin receiving segments + for it. */ + TCP_REG(&tcp_active_pcbs, npcb); + + /* Parse any options in the SYN. */ + tcp_parseopt(npcb); +#if TCP_CALCULATE_EFF_SEND_MSS + npcb->mss = tcp_eff_send_mss(npcb->mss, &(npcb->remote_ip)); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + + snmp_inc_tcppassiveopens(); + + /* Send a SYN|ACK together with the MSS option. */ + rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK); + if (rc != ERR_OK) { + tcp_abandon(npcb, 0); + return rc; + } + return tcp_output(npcb); + } + return ERR_OK; +} + +/** + * Called by tcp_input() when a segment arrives for a connection in + * TIME_WAIT. + * + * @param pcb the tcp_pcb for which a segment arrived + * + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static err_t +tcp_timewait_input(struct tcp_pcb *pcb) +{ + /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */ + /* RFC 793 3.9 Event Processing - Segment Arrives: + * - first check sequence number - we skip that one in TIME_WAIT (always + * acceptable since we only send ACKs) + * - second check the RST bit (... return) */ + if (flags & TCP_RST) { + return ERR_OK; + } + /* - fourth, check the SYN bit, */ + if (flags & TCP_SYN) { + /* If an incoming segment is not acceptable, an acknowledgment + should be sent in reply */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) { + /* If the SYN is in the window it is an error, send a reset */ + tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), ip_current_src_addr(), + tcphdr->dest, tcphdr->src); + return ERR_OK; + } + } else if (flags & TCP_FIN) { + /* - eighth, check the FIN bit: Remain in the TIME-WAIT state. + Restart the 2 MSL time-wait timeout.*/ + pcb->tmr = tcp_ticks; + } + + if ((tcplen > 0)) { + /* Acknowledge data, FIN or out-of-window SYN */ + pcb->flags |= TF_ACK_NOW; + return tcp_output(pcb); + } + return ERR_OK; +} + +/** + * Implements the TCP state machine. Called by tcp_input. In some + * states tcp_receive() is called to receive data. The tcp_seg + * argument will be freed by the caller (tcp_input()) unless the + * recv_data pointer in the pcb is set. + * + * @param pcb the tcp_pcb for which a segment arrived + * + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static err_t +tcp_process(struct tcp_pcb *pcb) +{ + struct tcp_seg *rseg; + u8_t acceptable = 0; + err_t err; + + err = ERR_OK; + + /* Process incoming RST segments. */ + if (flags & TCP_RST) { + /* First, determine if the reset is acceptable. */ + if (pcb->state == SYN_SENT) { + if (ackno == pcb->snd_nxt) { + acceptable = 1; + } + } else { + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + pcb->rcv_nxt+pcb->rcv_wnd)) { + acceptable = 1; + } + } + + if (acceptable) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); + LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); + recv_flags |= TF_RESET; + pcb->flags &= ~TF_ACK_DELAY; + return ERR_RST; + } else { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + return ERR_OK; + } + } + + if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { + /* Cope with new connection attempt after remote end crashed */ + tcp_ack_now(pcb); + return ERR_OK; + } + + if ((pcb->flags & TF_RXCLOSED) == 0) { + /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */ + pcb->tmr = tcp_ticks; + } + pcb->keep_cnt_sent = 0; + + tcp_parseopt(pcb); + + /* Do different things depending on the TCP state. */ + switch (pcb->state) { + case SYN_SENT: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, + pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno))); + /* received SYN ACK with expected sequence number? */ + if ((flags & TCP_ACK) && (flags & TCP_SYN) + && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) { + pcb->snd_buf++; + pcb->rcv_nxt = seqno + 1; + pcb->rcv_ann_right_edge = pcb->rcv_nxt; + pcb->lastack = ackno; + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ + pcb->state = ESTABLISHED; + +#if TCP_CALCULATE_EFF_SEND_MSS + pcb->mss = tcp_eff_send_mss(pcb->mss, &(pcb->remote_ip)); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + + /* Set ssthresh again after changing pcb->mss (already set in tcp_connect + * but for the default value of pcb->mss) */ + pcb->ssthresh = pcb->mss * 10; + + pcb->cwnd = ((pcb->cwnd == 1) ? (pcb->mss * 2) : pcb->mss); + LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0)); + --pcb->snd_queuelen; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + rseg = pcb->unacked; + pcb->unacked = rseg->next; + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if(pcb->unacked == NULL) + pcb->rtime = -1; + else { + pcb->rtime = 0; + pcb->nrtx = 0; + } + + tcp_seg_free(rseg); + + /* Call the user specified function to call when sucessfully + * connected. */ + TCP_EVENT_CONNECTED(pcb, ERR_OK, err); + if (err == ERR_ABRT) { + return ERR_ABRT; + } + tcp_ack_now(pcb); + } + /* received ACK? possibly a half-open connection */ + else if (flags & TCP_ACK) { + /* send a RST to bring the other side in a non-synchronized state. */ + tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), ip_current_src_addr(), + tcphdr->dest, tcphdr->src); + } + break; + case SYN_RCVD: + if (flags & TCP_ACK) { + /* expected ACK number? */ + if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { + u16_t old_cwnd; + pcb->state = ESTABLISHED; + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); +#if LWIP_CALLBACK_API + LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL); +#endif + /* Call the accept function. */ + TCP_EVENT_ACCEPT(pcb, ERR_OK, err); + if (err != ERR_OK) { + /* If the accept function returns with an error, we abort + * the connection. */ + /* Already aborted? */ + if (err != ERR_ABRT) { + tcp_abort(pcb); + } + return ERR_ABRT; + } + old_cwnd = pcb->cwnd; + /* If there was any data contained within this ACK, + * we'd better pass it on to the application as well. */ + tcp_receive(pcb); + + /* Prevent ACK for SYN to generate a sent event */ + if (pcb->acked != 0) { + pcb->acked--; + } + + pcb->cwnd = ((old_cwnd == 1) ? (pcb->mss * 2) : pcb->mss); + + if (recv_flags & TF_GOT_FIN) { + tcp_ack_now(pcb); + pcb->state = CLOSE_WAIT; + } + } else { + /* incorrect ACK number, send RST */ + tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), ip_current_src_addr(), + tcphdr->dest, tcphdr->src); + } + } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { + /* Looks like another copy of the SYN - retransmit our SYN-ACK */ + tcp_rexmit(pcb); + } + break; + case CLOSE_WAIT: + /* FALLTHROUGH */ + case ESTABLISHED: + tcp_receive(pcb); + if (recv_flags & TF_GOT_FIN) { /* passive close */ + tcp_ack_now(pcb); + pcb->state = CLOSE_WAIT; + } + break; + case FIN_WAIT_1: + tcp_receive(pcb); + if (recv_flags & TF_GOT_FIN) { + if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) { + LWIP_DEBUGF(TCP_DEBUG, + ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } else { + tcp_ack_now(pcb); + pcb->state = CLOSING; + } + } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) { + pcb->state = FIN_WAIT_2; + } + break; + case FIN_WAIT_2: + tcp_receive(pcb); + if (recv_flags & TF_GOT_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case CLOSING: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case LAST_ACK: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */ + recv_flags |= TF_CLOSED; + } + break; + default: + break; + } + return ERR_OK; +} + +#if TCP_QUEUE_OOSEQ +/** + * Insert segment into the list (segments covered with new one will be deleted) + * + * Called from tcp_receive() + */ +static void +tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next) +{ + struct tcp_seg *old_seg; + + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + /* received segment overlaps all following segments */ + tcp_segs_free(next); + next = NULL; + } + else { + /* delete some following segments + oos queue may have segments with FIN flag */ + while (next && + TCP_SEQ_GEQ((seqno + cseg->len), + (next->tcphdr->seqno + next->len))) { + /* cseg with FIN already processed */ + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN); + } + old_seg = next; + next = next->next; + tcp_seg_free(old_seg); + } + if (next && + TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) { + /* We need to trim the incoming segment. */ + cseg->len = (u16_t)(next->tcphdr->seqno - seqno); + pbuf_realloc(cseg->p, cseg->len); + } + } + cseg->next = next; +} +#endif /* TCP_QUEUE_OOSEQ */ + +/** + * Called by tcp_process. Checks if the given segment is an ACK for outstanding + * data, and if so frees the memory of the buffered data. Next, is places the + * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment + * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until + * i it has been removed from the buffer. + * + * If the incoming segment constitutes an ACK for a segment that was used for RTT + * estimation, the RTT is estimated here as well. + * + * Called from tcp_process(). + */ +static void +tcp_receive(struct tcp_pcb *pcb) +{ + struct tcp_seg *next; +#if TCP_QUEUE_OOSEQ + struct tcp_seg *prev, *cseg; +#endif /* TCP_QUEUE_OOSEQ */ + struct pbuf *p; + s32_t off; + s16_t m; + u32_t right_wnd_edge; + u16_t new_tot_len; + int found_dupack = 0; + + if (flags & TCP_ACK) { + right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2; + + /* Update window. */ + if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) { + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wl1 = seqno; + pcb->snd_wl2 = ackno; + if (pcb->snd_wnd > 0 && pcb->persist_backoff > 0) { + pcb->persist_backoff = 0; + } + LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U16_F"\n", pcb->snd_wnd)); +#if TCP_WND_DEBUG + } else { + if (pcb->snd_wnd != tcphdr->wnd) { + LWIP_DEBUGF(TCP_WND_DEBUG, + ("tcp_receive: no window update lastack %"U32_F" ackno %" + U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", + pcb->lastack, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); + } +#endif /* TCP_WND_DEBUG */ + } + + /* (From Stevens TCP/IP Illustrated Vol II, p970.) Its only a + * duplicate ack if: + * 1) It doesn't ACK new data + * 2) length of received packet is zero (i.e. no payload) + * 3) the advertised window hasn't changed + * 4) There is outstanding unacknowledged data (retransmission timer running) + * 5) The ACK is == biggest ACK sequence number so far seen (snd_una) + * + * If it passes all five, should process as a dupack: + * a) dupacks < 3: do nothing + * b) dupacks == 3: fast retransmit + * c) dupacks > 3: increase cwnd + * + * If it only passes 1-3, should reset dupack counter (and add to + * stats, which we don't do in lwIP) + * + * If it only passes 1, should reset dupack counter + * + */ + + /* Clause 1 */ + if (TCP_SEQ_LEQ(ackno, pcb->lastack)) { + pcb->acked = 0; + /* Clause 2 */ + if (tcplen == 0) { + /* Clause 3 */ + if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge){ + /* Clause 4 */ + if (pcb->rtime >= 0) { + /* Clause 5 */ + if (pcb->lastack == ackno) { + found_dupack = 1; + if (pcb->dupacks + 1 > pcb->dupacks) + ++pcb->dupacks; + if (pcb->dupacks > 3) { + /* Inflate the congestion window, but not if it means that + the value overflows. */ + if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { + pcb->cwnd += pcb->mss; + } + } else if (pcb->dupacks == 3) { + /* Do fast retransmit */ + tcp_rexmit_fast(pcb); + } + } + } + } + } + /* If Clause (1) or more is true, but not a duplicate ack, reset + * count of consecutive duplicate acks */ + if (!found_dupack) { + pcb->dupacks = 0; + } + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)){ + /* We come here when the ACK acknowledges new data. */ + + /* Reset the "IN Fast Retransmit" flag, since we are no longer + in fast retransmit. Also reset the congestion window to the + slow start threshold. */ + if (pcb->flags & TF_INFR) { + pcb->flags &= ~TF_INFR; + pcb->cwnd = pcb->ssthresh; + } + + /* Reset the number of retransmissions. */ + pcb->nrtx = 0; + + /* Reset the retransmission time-out. */ + pcb->rto = (pcb->sa >> 3) + pcb->sv; + + /* Update the send buffer space. Diff between the two can never exceed 64K? */ + pcb->acked = (u16_t)(ackno - pcb->lastack); + + pcb->snd_buf += pcb->acked; + + /* Reset the fast retransmit variables. */ + pcb->dupacks = 0; + pcb->lastack = ackno; + + /* Update the congestion control variables (cwnd and + ssthresh). */ + if (pcb->state >= ESTABLISHED) { + if (pcb->cwnd < pcb->ssthresh) { + if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { + pcb->cwnd += pcb->mss; + } + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd)); + } else { + u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); + if (new_cwnd > pcb->cwnd) { + pcb->cwnd = new_cwnd; + } + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd)); + } + } + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", + ackno, + pcb->unacked != NULL? + ntohl(pcb->unacked->tcphdr->seqno): 0, + pcb->unacked != NULL? + ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); + + /* Remove segment from the unacknowledged list if the incoming + ACK acknowlegdes them. */ + while (pcb->unacked != NULL && + TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) + + TCP_TCPLEN(pcb->unacked), ackno)) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n", + ntohl(pcb->unacked->tcphdr->seqno), + ntohl(pcb->unacked->tcphdr->seqno) + + TCP_TCPLEN(pcb->unacked))); + + next = pcb->unacked; + pcb->unacked = pcb->unacked->next; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); + LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p))); + /* Prevent ACK for FIN to generate a sent event */ + if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) { + pcb->acked--; + } + + pcb->snd_queuelen -= pbuf_clen(next->p); + tcp_seg_free(next); + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); + } + } + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if(pcb->unacked == NULL) + pcb->rtime = -1; + else + pcb->rtime = 0; + + pcb->polltmr = 0; + } else { + /* Fix bug bug #21582: out of sequence ACK, didn't really ack anything */ + pcb->acked = 0; + } + + /* We go through the ->unsent list to see if any of the segments + on the list are acknowledged by the ACK. This may seem + strange since an "unsent" segment shouldn't be acked. The + rationale is that lwIP puts all outstanding segments on the + ->unsent list after a retransmission, so these segments may + in fact have been sent once. */ + while (pcb->unsent != NULL && + TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + + TCP_TCPLEN(pcb->unsent), pcb->snd_nxt)) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n", + ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) + + TCP_TCPLEN(pcb->unsent))); + + next = pcb->unsent; + pcb->unsent = pcb->unsent->next; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); + LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p))); + /* Prevent ACK for FIN to generate a sent event */ + if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) { + pcb->acked--; + } + pcb->snd_queuelen -= pbuf_clen(next->p); + tcp_seg_free(next); + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_receive: valid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + } + /* End of ACK for new data processing. */ + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", + pcb->rttest, pcb->rtseq, ackno)); + + /* RTT estimation calculations. This is done by checking if the + incoming segment acknowledges the segment we use to take a + round-trip time measurement. */ + if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { + /* diff between this shouldn't exceed 32K since this are tcp timer ticks + and a round-trip shouldn't be that long... */ + m = (s16_t)(tcp_ticks - pcb->rttest); + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", + m, m * TCP_SLOW_INTERVAL)); + + /* This is taken directly from VJs original code in his paper */ + m = m - (pcb->sa >> 3); + pcb->sa += m; + if (m < 0) { + m = -m; + } + m = m - (pcb->sv >> 2); + pcb->sv += m; + pcb->rto = (pcb->sa >> 3) + pcb->sv; + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n", + pcb->rto, pcb->rto * TCP_SLOW_INTERVAL)); + + pcb->rttest = 0; + } + } + + /* If the incoming segment contains data, we must process it + further. */ + if (tcplen > 0) { + /* This code basically does three things: + + +) If the incoming segment contains data that is the next + in-sequence data, this data is passed to the application. This + might involve trimming the first edge of the data. The rcv_nxt + variable and the advertised window are adjusted. + + +) If the incoming segment has data that is above the next + sequence number expected (->rcv_nxt), the segment is placed on + the ->ooseq queue. This is done by finding the appropriate + place in the ->ooseq queue (which is ordered by sequence + number) and trim the segment in both ends if needed. An + immediate ACK is sent to indicate that we received an + out-of-sequence segment. + + +) Finally, we check if the first segment on the ->ooseq queue + now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If + rcv_nxt > ooseq->seqno, we must trim the first edge of the + segment on ->ooseq before we adjust rcv_nxt. The data in the + segments that are now on sequence are chained onto the + incoming segment so that we only need to call the application + once. + */ + + /* First, we check if we must trim the first edge. We have to do + this if the sequence number of the incoming segment is less + than rcv_nxt, and the sequence number plus the length of the + segment is larger than rcv_nxt. */ + /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ + if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ + if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)){ + /* Trimming the first edge is done by pushing the payload + pointer in the pbuf downwards. This is somewhat tricky since + we do not want to discard the full contents of the pbuf up to + the new starting point of the data since we have to keep the + TCP header which is present in the first pbuf in the chain. + + What is done is really quite a nasty hack: the first pbuf in + the pbuf chain is pointed to by inseg.p. Since we need to be + able to deallocate the whole pbuf, we cannot change this + inseg.p pointer to point to any of the later pbufs in the + chain. Instead, we point the ->payload pointer in the first + pbuf to data in one of the later pbufs. We also set the + inseg.data pointer to point to the right place. This way, the + ->p pointer will still point to the first pbuf, but the + ->p->payload pointer will point to data in another pbuf. + + After we are done with adjusting the pbuf pointers we must + adjust the ->data pointer in the seg and the segment + length.*/ + + off = pcb->rcv_nxt - seqno; + p = inseg.p; + LWIP_ASSERT("inseg.p != NULL", inseg.p); + LWIP_ASSERT("insane offset!", (off < 0x7fff)); + if (inseg.p->len < off) { + LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off)); + new_tot_len = (u16_t)(inseg.p->tot_len - off); + while (p->len < off) { + off -= p->len; + /* KJM following line changed (with addition of new_tot_len var) + to fix bug #9076 + inseg.p->tot_len -= p->len; */ + p->tot_len = new_tot_len; + p->len = 0; + p = p->next; + } + if(pbuf_header(p, (s16_t)-off)) { + /* Do we need to cope with this failing? Assert for now */ + LWIP_ASSERT("pbuf_header failed", 0); + } + } else { + if(pbuf_header(inseg.p, (s16_t)-off)) { + /* Do we need to cope with this failing? Assert for now */ + LWIP_ASSERT("pbuf_header failed", 0); + } + } + inseg.len -= (u16_t)(pcb->rcv_nxt - seqno); + inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; + } + else { + if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ + /* the whole segment is < rcv_nxt */ + /* must be a duplicate of a packet that has already been correctly handled */ + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); + tcp_ack_now(pcb); + } + } + + /* The sequence number must be within the window (above rcv_nxt + and below rcv_nxt + rcv_wnd) in order to be further + processed. */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + pcb->rcv_nxt + pcb->rcv_wnd - 1)){ + if (pcb->rcv_nxt == seqno) { + /* The incoming segment is the next in sequence. We check if + we have to trim the end of the segment and update rcv_nxt + and pass the data to the application. */ + tcplen = TCP_TCPLEN(&inseg); + + if (tcplen > pcb->rcv_wnd) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: other end overran receive window" + "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", + seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + /* Must remove the FIN from the header as we're trimming + * that byte of sequence-space from the packet */ + TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) &~ TCP_FIN); + } + /* Adjust length of segment to fit in the window. */ + inseg.len = pcb->rcv_wnd; + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + inseg.len -= 1; + } + pbuf_realloc(inseg.p, inseg.len); + tcplen = TCP_TCPLEN(&inseg); + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", + (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); + } +#if TCP_QUEUE_OOSEQ + /* Received in-sequence data, adjust ooseq data if: + - FIN has been received or + - inseq overlaps with ooseq */ + if (pcb->ooseq != NULL) { + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: received in-order FIN, binning ooseq queue\n")); + /* Received in-order FIN means anything that was received + * out of order must now have been received in-order, so + * bin the ooseq queue */ + while (pcb->ooseq != NULL) { + struct tcp_seg *old_ooseq = pcb->ooseq; + pcb->ooseq = pcb->ooseq->next; + tcp_seg_free(old_ooseq); + } + } + else { + next = pcb->ooseq; + /* Remove all segments on ooseq that are covered by inseg already. + * FIN is copied from ooseq to inseg if present. */ + while (next && + TCP_SEQ_GEQ(seqno + tcplen, + next->tcphdr->seqno + next->len)) { + /* inseg cannot have FIN here (already processed above) */ + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN && + (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) { + TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN); + tcplen = TCP_TCPLEN(&inseg); + } + prev = next; + next = next->next; + tcp_seg_free(prev); + } + /* Now trim right side of inseg if it overlaps with the first + * segment on ooseq */ + if (next && + TCP_SEQ_GT(seqno + tcplen, + next->tcphdr->seqno)) { + /* inseg cannot have FIN here (already processed above) */ + inseg.len = (u16_t)(next->tcphdr->seqno - seqno); + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + inseg.len -= 1; + } + pbuf_realloc(inseg.p, inseg.len); + tcplen = TCP_TCPLEN(&inseg); + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n", + (seqno + tcplen) == next->tcphdr->seqno); + } + pcb->ooseq = next; + } + } +#endif /* TCP_QUEUE_OOSEQ */ + + pcb->rcv_nxt = seqno + tcplen; + + /* Update the receiver's (our) window. */ + LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen); + pcb->rcv_wnd -= tcplen; + + tcp_update_rcv_ann_wnd(pcb); + + /* If there is data in the segment, we make preparations to + pass this up to the application. The ->recv_data variable + is used for holding the pbuf that goes to the + application. The code for reassembling out-of-sequence data + chains its data on this pbuf as well. + + If the segment was a FIN, we set the TF_GOT_FIN flag that will + be used to indicate to the application that the remote side has + closed its end of the connection. */ + if (inseg.p->tot_len > 0) { + recv_data = inseg.p; + /* Since this pbuf now is the responsibility of the + application, we delete our reference to it so that we won't + (mistakingly) deallocate it. */ + inseg.p = NULL; + } + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); + recv_flags |= TF_GOT_FIN; + } + +#if TCP_QUEUE_OOSEQ + /* We now check if we have segments on the ->ooseq queue that + are now in sequence. */ + while (pcb->ooseq != NULL && + pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + + cseg = pcb->ooseq; + seqno = pcb->ooseq->tcphdr->seqno; + + pcb->rcv_nxt += TCP_TCPLEN(cseg); + LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n", + pcb->rcv_wnd >= TCP_TCPLEN(cseg)); + pcb->rcv_wnd -= TCP_TCPLEN(cseg); + + tcp_update_rcv_ann_wnd(pcb); + + if (cseg->p->tot_len > 0) { + /* Chain this pbuf onto the pbuf that we will pass to + the application. */ + if (recv_data) { + pbuf_cat(recv_data, cseg->p); + } else { + recv_data = cseg->p; + } + cseg->p = NULL; + } + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); + recv_flags |= TF_GOT_FIN; + if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ + pcb->state = CLOSE_WAIT; + } + } + + pcb->ooseq = cseg->next; + tcp_seg_free(cseg); + } +#endif /* TCP_QUEUE_OOSEQ */ + + + /* Acknowledge the segment(s). */ + tcp_ack(pcb); + + } else { + /* We get here if the incoming segment is out-of-sequence. */ + tcp_send_empty_ack(pcb); +#if TCP_QUEUE_OOSEQ + /* We queue the segment on the ->ooseq queue. */ + if (pcb->ooseq == NULL) { + pcb->ooseq = tcp_seg_copy(&inseg); + } else { + /* If the queue is not empty, we walk through the queue and + try to find a place where the sequence number of the + incoming segment is between the sequence numbers of the + previous and the next segment on the ->ooseq queue. That is + the place where we put the incoming segment. If needed, we + trim the second edges of the previous and the incoming + segment so that it will fit into the sequence. + + If the incoming segment has the same sequence number as a + segment on the ->ooseq queue, we discard the segment that + contains less data. */ + + prev = NULL; + for(next = pcb->ooseq; next != NULL; next = next->next) { + if (seqno == next->tcphdr->seqno) { + /* The sequence number of the incoming segment is the + same as the sequence number of the segment on + ->ooseq. We check the lengths to see which one to + discard. */ + if (inseg.len > next->len) { + /* The incoming segment is larger than the old + segment. We replace some segments with the new + one. */ + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + if (prev != NULL) { + prev->next = cseg; + } else { + pcb->ooseq = cseg; + } + tcp_oos_insert_segment(cseg, next); + } + break; + } else { + /* Either the lenghts are the same or the incoming + segment was smaller than the old one; in either + case, we ditch the incoming segment. */ + break; + } + } else { + if (prev == NULL) { + if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { + /* The sequence number of the incoming segment is lower + than the sequence number of the first segment on the + queue. We put the incoming segment first on the + queue. */ + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + pcb->ooseq = cseg; + tcp_oos_insert_segment(cseg, next); + } + break; + } + } else { + /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && + TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ + if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)) { + /* The sequence number of the incoming segment is in + between the sequence numbers of the previous and + the next segment on ->ooseq. We trim trim the previous + segment, delete next segments that included in received segment + and trim received, if needed. */ + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { + /* We need to trim the prev segment. */ + prev->len = (u16_t)(seqno - prev->tcphdr->seqno); + pbuf_realloc(prev->p, prev->len); + } + prev->next = cseg; + tcp_oos_insert_segment(cseg, next); + } + break; + } + } + /* If the "next" segment is the last segment on the + ooseq queue, we add the incoming segment to the end + of the list. */ + if (next->next == NULL && + TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + /* segment "next" already contains all data */ + break; + } + next->next = tcp_seg_copy(&inseg); + if (next->next != NULL) { + if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { + /* We need to trim the last segment. */ + next->len = (u16_t)(seqno - next->tcphdr->seqno); + pbuf_realloc(next->p, next->len); + } + /* check if the remote side overruns our receive window */ + if ((u32_t)tcplen + seqno > pcb->rcv_nxt + (u32_t)pcb->rcv_wnd) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: other end overran receive window" + "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", + seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); + if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) { + /* Must remove the FIN from the header as we're trimming + * that byte of sequence-space from the packet */ + TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) &~ TCP_FIN); + } + /* Adjust length of segment to fit in the window. */ + next->next->len = pcb->rcv_nxt + pcb->rcv_wnd - seqno; + pbuf_realloc(next->next->p, next->next->len); + tcplen = TCP_TCPLEN(next->next); + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", + (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); + } + } + break; + } + } + prev = next; + } + } +#endif /* TCP_QUEUE_OOSEQ */ + + } + } else { + /* The incoming segment is not withing the window. */ + tcp_send_empty_ack(pcb); + } + } else { + /* Segments with length 0 is taken care of here. Segments that + fall out of the window are ACKed. */ + /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || + TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ + if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ + tcp_ack_now(pcb); + } + } +} + +/** + * Parses the options contained in the incoming segment. + * + * Called from tcp_listen_input() and tcp_process(). + * Currently, only the MSS option is supported! + * + * @param pcb the tcp_pcb for which a segment arrived + */ +static void +tcp_parseopt(struct tcp_pcb *pcb) +{ + u16_t c, max_c; + u16_t mss; + u8_t *opts, opt; +#if LWIP_TCP_TIMESTAMPS + u32_t tsval; +#endif + + opts = (u8_t *)tcphdr + TCP_HLEN; + + /* Parse the TCP MSS option, if present. */ + if(TCPH_HDRLEN(tcphdr) > 0x5) { + max_c = (TCPH_HDRLEN(tcphdr) - 5) << 2; + for (c = 0; c < max_c; ) { + opt = opts[c]; + switch (opt) { + case 0x00: + /* End of options. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n")); + return; + case 0x01: + /* NOP option. */ + ++c; + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n")); + break; + case 0x02: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n")); + if (opts[c + 1] != 0x04 || c + 0x04 > max_c) { + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* An MSS option with the right option length. */ + mss = (opts[c + 2] << 8) | opts[c + 3]; + /* Limit the mss to the configured TCP_MSS and prevent division by zero */ + pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss; + /* Advance to next option */ + c += 0x04; + break; +#if LWIP_TCP_TIMESTAMPS + case 0x08: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: TS\n")); + if (opts[c + 1] != 0x0A || c + 0x0A > max_c) { + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* TCP timestamp option with valid length */ + tsval = (opts[c+2]) | (opts[c+3] << 8) | + (opts[c+4] << 16) | (opts[c+5] << 24); + if (flags & TCP_SYN) { + pcb->ts_recent = ntohl(tsval); + pcb->flags |= TF_TIMESTAMP; + } else if (TCP_SEQ_BETWEEN(pcb->ts_lastacksent, seqno, seqno+tcplen)) { + pcb->ts_recent = ntohl(tsval); + } + /* Advance to next option */ + c += 0x0A; + break; +#endif + default: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n")); + if (opts[c + 1] == 0) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + /* If the length field is zero, the options are malformed + and we don't process them further. */ + return; + } + /* All other options have a length field, so that we easily + can skip past them. */ + c += opts[c + 1]; + } + } + } +} + +#endif /* LWIP_TCP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/tcp_out.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/tcp_out.c new file mode 100644 index 0000000..1b8308d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/tcp_out.c @@ -0,0 +1,1468 @@ +/** + * @file + * Transmission Control Protocol, outgoing traffic + * + * The output functions of TCP. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcp_impl.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/sys.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/inet_chksum.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +#include + +/* Define some copy-macros for checksum-on-copy so that the code looks + nicer by preventing too many ifdef's. */ +#if TCP_CHECKSUM_ON_COPY +#define TCP_DATA_COPY(dst, src, len, seg) do { \ + tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), \ + len, &seg->chksum, &seg->chksum_swapped); \ + seg->flags |= TF_SEG_DATA_CHECKSUMMED; } while(0) +#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped) \ + tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), len, chksum, chksum_swapped); +#else /* TCP_CHECKSUM_ON_COPY*/ +#define TCP_DATA_COPY(dst, src, len, seg) MEMCPY(dst, src, len) +#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped) MEMCPY(dst, src, len) +#endif /* TCP_CHECKSUM_ON_COPY*/ + +/** Define this to 1 for an extra check that the output checksum is valid + * (usefule when the checksum is generated by the application, not the stack) */ +#ifndef TCP_CHECKSUM_ON_COPY_SANITY_CHECK +#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK 0 +#endif + +/* Forward declarations.*/ +static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb); + +/** Allocate a pbuf and create a tcphdr at p->payload, used for output + * functions other than the default tcp_output -> tcp_output_segment + * (e.g. tcp_send_empty_ack, etc.) + * + * @param pcb tcp pcb for which to send a packet (used to initialize tcp_hdr) + * @param optlen length of header-options + * @param datalen length of tcp data to reserve in pbuf + * @param seqno_be seqno in network byte order (big-endian) + * @return pbuf with p->payload being the tcp_hdr + */ +static struct pbuf * +tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen, + u32_t seqno_be /* already in network byte order */) +{ + struct tcp_hdr *tcphdr; + struct pbuf *p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM); + if (p != NULL) { + LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", + (p->len >= TCP_HLEN + optlen)); + tcphdr = (struct tcp_hdr *)p->payload; + tcphdr->src = htons(pcb->local_port); + tcphdr->dest = htons(pcb->remote_port); + tcphdr->seqno = seqno_be; + tcphdr->ackno = htonl(pcb->rcv_nxt); + TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), TCP_ACK); + tcphdr->wnd = htons(pcb->rcv_ann_wnd); + tcphdr->chksum = 0; + tcphdr->urgp = 0; + + /* If we're sending a packet, update the announced right window edge */ + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + } + return p; +} + +/** + * Called by tcp_close() to send a segment including FIN flag but not data. + * + * @param pcb the tcp_pcb over which to send a segment + * @return ERR_OK if sent, another err_t otherwise + */ +err_t +tcp_send_fin(struct tcp_pcb *pcb) +{ + /* first, try to add the fin to the last unsent segment */ + if (pcb->unsent != NULL) { + struct tcp_seg *last_unsent; + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + last_unsent = last_unsent->next); + + if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) { + /* no SYN/FIN/RST flag in the header, we can add the FIN flag */ + TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN); + return ERR_OK; + } + } + /* no data, no length, flags, copy=1, no optdata */ + return tcp_enqueue_flags(pcb, TCP_FIN); +} + +/** + * Create a TCP segment with prefilled header. + * + * Called by tcp_write and tcp_enqueue_flags. + * + * @param pcb Protocol control block for the TCP connection. + * @param p pbuf that is used to hold the TCP header. + * @param flags TCP flags for header. + * @param seqno TCP sequence number of this packet + * @param optflags options to include in TCP header + * @return a new tcp_seg pointing to p, or NULL. + * The TCP header is filled in except ackno and wnd. + * p is freed on failure. + */ +static struct tcp_seg * +tcp_create_segment(struct tcp_pcb *pcb, struct pbuf *p, u8_t flags, u32_t seqno, u8_t optflags) +{ + struct tcp_seg *seg; + u8_t optlen = LWIP_TCP_OPT_LENGTH(optflags); + + if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_create_segment: no memory.\n")); + pbuf_free(p); + return NULL; + } + seg->flags = optflags; + seg->next = NULL; + seg->p = p; + seg->len = p->tot_len - optlen; +#if TCP_OVERSIZE_DBGCHECK + seg->oversize_left = 0; +#endif /* TCP_OVERSIZE_DBGCHECK */ +#if TCP_CHECKSUM_ON_COPY + seg->chksum = 0; + seg->chksum_swapped = 0; + /* check optflags */ + LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED", + (optflags & TF_SEG_DATA_CHECKSUMMED) == 0); +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* build TCP header */ + if (pbuf_header(p, TCP_HLEN)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_create_segment: no room for TCP header in pbuf.\n")); + TCP_STATS_INC(tcp.err); + tcp_seg_free(seg); + return NULL; + } + seg->tcphdr = (struct tcp_hdr *)seg->p->payload; + seg->tcphdr->src = htons(pcb->local_port); + seg->tcphdr->dest = htons(pcb->remote_port); + seg->tcphdr->seqno = htonl(seqno); + /* ackno is set in tcp_output */ + TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), flags); + /* wnd and chksum are set in tcp_output */ + seg->tcphdr->urgp = 0; + return seg; +} + +/** + * Allocate a PBUF_RAM pbuf, perhaps with extra space at the end. + * + * This function is like pbuf_alloc(layer, length, PBUF_RAM) except + * there may be extra bytes available at the end. + * + * @param layer flag to define header size. + * @param length size of the pbuf's payload. + * @param max_length maximum usable size of payload+oversize. + * @param oversize pointer to a u16_t that will receive the number of usable tail bytes. + * @param pcb The TCP connection that willo enqueue the pbuf. + * @param apiflags API flags given to tcp_write. + * @param first_seg true when this pbuf will be used in the first enqueued segment. + * @param + */ +#if TCP_OVERSIZE +static struct pbuf * +tcp_pbuf_prealloc(pbuf_layer layer, u16_t length, u16_t max_length, + u16_t *oversize, struct tcp_pcb *pcb, u8_t apiflags, + u8_t first_seg) +{ + struct pbuf *p; + u16_t alloc = length; + +#if LWIP_NETIF_TX_SINGLE_PBUF + LWIP_UNUSED_ARG(max_length); + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(apiflags); + LWIP_UNUSED_ARG(first_seg); + /* always create MSS-sized pbufs */ + alloc = TCP_MSS; +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + if (length < max_length) { + /* Should we allocate an oversized pbuf, or just the minimum + * length required? If tcp_write is going to be called again + * before this segment is transmitted, we want the oversized + * buffer. If the segment will be transmitted immediately, we can + * save memory by allocating only length. We use a simple + * heuristic based on the following information: + * + * Did the user set TCP_WRITE_FLAG_MORE? + * + * Will the Nagle algorithm defer transmission of this segment? + */ + if ((apiflags & TCP_WRITE_FLAG_MORE) || + (!(pcb->flags & TF_NODELAY) && + (!first_seg || + pcb->unsent != NULL || + pcb->unacked != NULL))) { + alloc = LWIP_MIN(max_length, LWIP_MEM_ALIGN_SIZE(length + TCP_OVERSIZE)); + } + } +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + p = pbuf_alloc(layer, alloc, PBUF_RAM); + if (p == NULL) { + return NULL; + } + LWIP_ASSERT("need unchained pbuf", p->next == NULL); + *oversize = p->len - length; + /* trim p->len to the currently used size */ + p->len = p->tot_len = length; + return p; +} +#else /* TCP_OVERSIZE */ +#define tcp_pbuf_prealloc(layer, length, mx, os, pcb, api, fst) pbuf_alloc((layer), (length), PBUF_RAM) +#endif /* TCP_OVERSIZE */ + +#if TCP_CHECKSUM_ON_COPY +/** Add a checksum of newly added data to the segment */ +static void +tcp_seg_add_chksum(u16_t chksum, u16_t len, u16_t *seg_chksum, + u8_t *seg_chksum_swapped) +{ + u32_t helper; + /* add chksum to old chksum and fold to u16_t */ + helper = chksum + *seg_chksum; + chksum = FOLD_U32T(helper); + if ((len & 1) != 0) { + *seg_chksum_swapped = 1 - *seg_chksum_swapped; + chksum = SWAP_BYTES_IN_WORD(chksum); + } + *seg_chksum = chksum; +} +#endif /* TCP_CHECKSUM_ON_COPY */ + +/** Checks if tcp_write is allowed or not (checks state, snd_buf and snd_queuelen). + * + * @param pcb the tcp pcb to check for + * @param len length of data to send (checked agains snd_buf) + * @return ERR_OK if tcp_write is allowed to proceed, another err_t otherwise + */ +static err_t +tcp_write_checks(struct tcp_pcb *pcb, u16_t len) +{ + /* connection is in invalid state for data transmission? */ + if ((pcb->state != ESTABLISHED) && + (pcb->state != CLOSE_WAIT) && + (pcb->state != SYN_SENT) && + (pcb->state != SYN_RCVD)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n")); + return ERR_CONN; + } else if (len == 0) { + return ERR_OK; + } + + /* fail on too much data */ + if (len > pcb->snd_buf) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_write: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", + len, pcb->snd_buf)); + pcb->flags |= TF_NAGLEMEMERR; + return ERR_MEM; + } + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + + /* If total number of pbufs on the unsent/unacked queues exceeds the + * configured maximum, return an error */ + /* check for configured max queuelen and possible overflow */ + if ((pcb->snd_queuelen >= TCP_SND_QUEUELEN) || (pcb->snd_queuelen > TCP_SNDQUEUELEN_OVERFLOW)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_write: too long queue %"U16_F" (max %"U16_F")\n", + pcb->snd_queuelen, TCP_SND_QUEUELEN)); + TCP_STATS_INC(tcp.memerr); + pcb->flags |= TF_NAGLEMEMERR; + return ERR_MEM; + } + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_write: pbufs on queue => at least one queue non-empty", + pcb->unacked != NULL || pcb->unsent != NULL); + } else { + LWIP_ASSERT("tcp_write: no pbufs on queue => both queues empty", + pcb->unacked == NULL && pcb->unsent == NULL); + } + return ERR_OK; +} + +/** + * Write data for sending (but does not send it immediately). + * + * It waits in the expectation of more data being sent soon (as + * it can send them more efficiently by combining them together). + * To prompt the system to send data now, call tcp_output() after + * calling tcp_write(). + * + * @param pcb Protocol control block for the TCP connection to enqueue data for. + * @param arg Pointer to the data to be enqueued for sending. + * @param len Data length in bytes + * @param apiflags combination of following flags : + * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack + * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent, + * @return ERR_OK if enqueued, another err_t on error + */ +err_t +tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t apiflags) +{ + struct pbuf *concat_p = NULL; + struct tcp_seg *last_unsent = NULL, *seg = NULL, *prev_seg = NULL, *queue = NULL; + u16_t pos = 0; /* position in 'arg' data */ + u16_t queuelen; + u8_t optlen = 0; + u8_t optflags = 0; +#if TCP_OVERSIZE + u16_t oversize = 0; + u16_t oversize_used = 0; +#endif /* TCP_OVERSIZE */ +#if TCP_CHECKSUM_ON_COPY + u16_t concat_chksum = 0; + u8_t concat_chksum_swapped = 0; + u16_t concat_chksummed = 0; +#endif /* TCP_CHECKSUM_ON_COPY */ + err_t err; + +#if LWIP_NETIF_TX_SINGLE_PBUF + /* Always copy to try to create single pbufs for TX */ + apiflags |= TCP_WRITE_FLAG_COPY; +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n", + (void *)pcb, arg, len, (u16_t)apiflags)); + LWIP_ERROR("tcp_write: arg == NULL (programmer violates API)", + arg != NULL, return ERR_ARG;); + + err = tcp_write_checks(pcb, len); + if (err != ERR_OK) { + return err; + } + queuelen = pcb->snd_queuelen; + +#if LWIP_TCP_TIMESTAMPS + if ((pcb->flags & TF_TIMESTAMP)) { + optflags = TF_SEG_OPTS_TS; + optlen = LWIP_TCP_OPT_LENGTH(TF_SEG_OPTS_TS); + } +#endif /* LWIP_TCP_TIMESTAMPS */ + + + /* + * TCP segmentation is done in three phases with increasing complexity: + * + * 1. Copy data directly into an oversized pbuf. + * 2. Chain a new pbuf to the end of pcb->unsent. + * 3. Create new segments. + * + * We may run out of memory at any point. In that case we must + * return ERR_MEM and not change anything in pcb. Therefore, all + * changes are recorded in local variables and committed at the end + * of the function. Some pcb fields are maintained in local copies: + * + * queuelen = pcb->snd_queuelen + * oversize = pcb->unsent_oversize + * + * These variables are set consistently by the phases: + * + * seg points to the last segment tampered with. + * + * pos records progress as data is segmented. + */ + + /* Find the tail of the unsent queue. */ + if (pcb->unsent != NULL) { + u16_t space; + u16_t unsent_optlen; + + /* @todo: this could be sped up by keeping last_unsent in the pcb */ + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + last_unsent = last_unsent->next); + + /* Usable space at the end of the last unsent segment */ + unsent_optlen = LWIP_TCP_OPT_LENGTH(last_unsent->flags); + space = pcb->mss - (last_unsent->len + unsent_optlen); + + /* + * Phase 1: Copy data directly into an oversized pbuf. + * + * The number of bytes copied is recorded in the oversize_used + * variable. The actual copying is done at the bottom of the + * function. + */ +#if TCP_OVERSIZE +#if TCP_OVERSIZE_DBGCHECK + /* check that pcb->unsent_oversize matches last_unsent->unsent_oversize */ + LWIP_ASSERT("unsent_oversize mismatch (pcb vs. last_unsent)", + pcb->unsent_oversize == last_unsent->oversize_left); +#endif /* TCP_OVERSIZE_DBGCHECK */ + oversize = pcb->unsent_oversize; + if (oversize > 0) { + LWIP_ASSERT("inconsistent oversize vs. space", oversize_used <= space); + seg = last_unsent; + oversize_used = oversize < len ? oversize : len; + pos += oversize_used; + oversize -= oversize_used; + space -= oversize_used; + } + /* now we are either finished or oversize is zero */ + LWIP_ASSERT("inconsistend oversize vs. len", (oversize == 0) || (pos == len)); +#endif /* TCP_OVERSIZE */ + + /* + * Phase 2: Chain a new pbuf to the end of pcb->unsent. + * + * We don't extend segments containing SYN/FIN flags or options + * (len==0). The new pbuf is kept in concat_p and pbuf_cat'ed at + * the end. + */ + if ((pos < len) && (space > 0) && (last_unsent->len > 0)) { + u16_t seglen = space < len - pos ? space : len - pos; + seg = last_unsent; + + /* Create a pbuf with a copy or reference to seglen bytes. We + * can use PBUF_RAW here since the data appears in the middle of + * a segment. A header will never be prepended. */ + if (apiflags & TCP_WRITE_FLAG_COPY) { + /* Data is copied */ + if ((concat_p = tcp_pbuf_prealloc(PBUF_RAW, seglen, space, &oversize, pcb, apiflags, 1)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, + ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", + seglen)); + goto memerr; + } +#if TCP_OVERSIZE_DBGCHECK + last_unsent->oversize_left = oversize; +#endif /* TCP_OVERSIZE_DBGCHECK */ + TCP_DATA_COPY2(concat_p->payload, (u8_t*)arg + pos, seglen, &concat_chksum, &concat_chksum_swapped); +#if TCP_CHECKSUM_ON_COPY + concat_chksummed += seglen; +#endif /* TCP_CHECKSUM_ON_COPY */ + } else { + /* Data is not copied */ + if ((concat_p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, + ("tcp_write: could not allocate memory for zero-copy pbuf\n")); + goto memerr; + } +#if TCP_CHECKSUM_ON_COPY + /* calculate the checksum of nocopy-data */ + tcp_seg_add_chksum(~inet_chksum((u8_t*)arg + pos, seglen), seglen, + &concat_chksum, &concat_chksum_swapped); + concat_chksummed += seglen; +#endif /* TCP_CHECKSUM_ON_COPY */ + /* reference the non-volatile payload data */ + concat_p->payload = (u8_t*)arg + pos; + } + + pos += seglen; + queuelen += pbuf_clen(concat_p); + } + } else { +#if TCP_OVERSIZE + LWIP_ASSERT("unsent_oversize mismatch (pcb->unsent is NULL)", + pcb->unsent_oversize == 0); +#endif /* TCP_OVERSIZE */ + } + + /* + * Phase 3: Create new segments. + * + * The new segments are chained together in the local 'queue' + * variable, ready to be appended to pcb->unsent. + */ + while (pos < len) { + struct pbuf *p; + u16_t left = len - pos; + u16_t max_len = pcb->mss - optlen; + u16_t seglen = left > max_len ? max_len : left; +#if TCP_CHECKSUM_ON_COPY + u16_t chksum = 0; + u8_t chksum_swapped = 0; +#endif /* TCP_CHECKSUM_ON_COPY */ + + if (apiflags & TCP_WRITE_FLAG_COPY) { + /* If copy is set, memory should be allocated and data copied + * into pbuf */ + if ((p = tcp_pbuf_prealloc(PBUF_TRANSPORT, seglen + optlen, pcb->mss, &oversize, pcb, apiflags, queue == NULL)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); + goto memerr; + } + LWIP_ASSERT("tcp_write: check that first pbuf can hold the complete seglen", + (p->len >= seglen)); + TCP_DATA_COPY2((char *)p->payload + optlen, (u8_t*)arg + pos, seglen, &chksum, &chksum_swapped); + } else { + /* Copy is not set: First allocate a pbuf for holding the data. + * Since the referenced data is available at least until it is + * sent out on the link (as it has to be ACKed by the remote + * party) we can safely use PBUF_ROM instead of PBUF_REF here. + */ + struct pbuf *p2; +#if TCP_OVERSIZE + LWIP_ASSERT("oversize == 0", oversize == 0); +#endif /* TCP_OVERSIZE */ + if ((p2 = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_write: could not allocate memory for zero-copy pbuf\n")); + goto memerr; + } +#if TCP_CHECKSUM_ON_COPY + /* calculate the checksum of nocopy-data */ + chksum = ~inet_chksum((u8_t*)arg + pos, seglen); +#endif /* TCP_CHECKSUM_ON_COPY */ + /* reference the non-volatile payload data */ + p2->payload = (u8_t*)arg + pos; + + /* Second, allocate a pbuf for the headers. */ + if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + /* If allocation fails, we have to deallocate the data pbuf as + * well. */ + pbuf_free(p2); + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_write: could not allocate memory for header pbuf\n")); + goto memerr; + } + /* Concatenate the headers and data pbufs together. */ + pbuf_cat(p/*header*/, p2/*data*/); + } + + queuelen += pbuf_clen(p); + + /* Now that there are more segments queued, we check again if the + * length of the queue exceeds the configured maximum or + * overflows. */ + if ((queuelen > TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_write: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); + pbuf_free(p); + goto memerr; + } + + if ((seg = tcp_create_segment(pcb, p, 0, pcb->snd_lbb + pos, optflags)) == NULL) { + goto memerr; + } +#if TCP_OVERSIZE_DBGCHECK + seg->oversize_left = oversize; +#endif /* TCP_OVERSIZE_DBGCHECK */ +#if TCP_CHECKSUM_ON_COPY + seg->chksum = chksum; + seg->chksum_swapped = chksum_swapped; + seg->flags |= TF_SEG_DATA_CHECKSUMMED; +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* first segment of to-be-queued data? */ + if (queue == NULL) { + queue = seg; + } else { + /* Attach the segment to the end of the queued segments */ + LWIP_ASSERT("prev_seg != NULL", prev_seg != NULL); + prev_seg->next = seg; + } + /* remember last segment of to-be-queued data for next iteration */ + prev_seg = seg; + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_write: queueing %"U32_F":%"U32_F"\n", + ntohl(seg->tcphdr->seqno), + ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg))); + + pos += seglen; + } + + /* + * All three segmentation phases were successful. We can commit the + * transaction. + */ + + /* + * Phase 1: If data has been added to the preallocated tail of + * last_unsent, we update the length fields of the pbuf chain. + */ +#if TCP_OVERSIZE + if (oversize_used > 0) { + struct pbuf *p; + /* Bump tot_len of whole chain, len of tail */ + for (p = last_unsent->p; p; p = p->next) { + p->tot_len += oversize_used; + if (p->next == NULL) { + TCP_DATA_COPY((char *)p->payload + p->len, arg, oversize_used, last_unsent); + p->len += oversize_used; + } + } + last_unsent->len += oversize_used; +#if TCP_OVERSIZE_DBGCHECK + last_unsent->oversize_left -= oversize_used; +#endif /* TCP_OVERSIZE_DBGCHECK */ + } + pcb->unsent_oversize = oversize; +#endif /* TCP_OVERSIZE */ + + /* + * Phase 2: concat_p can be concatenated onto last_unsent->p + */ + if (concat_p != NULL) { + LWIP_ASSERT("tcp_write: cannot concatenate when pcb->unsent is empty", + (last_unsent != NULL)); + pbuf_cat(last_unsent->p, concat_p); + last_unsent->len += concat_p->tot_len; +#if TCP_CHECKSUM_ON_COPY + if (concat_chksummed) { + tcp_seg_add_chksum(concat_chksum, concat_chksummed, &last_unsent->chksum, + &last_unsent->chksum_swapped); + last_unsent->flags |= TF_SEG_DATA_CHECKSUMMED; + } +#endif /* TCP_CHECKSUM_ON_COPY */ + } + + /* + * Phase 3: Append queue to pcb->unsent. Queue may be NULL, but that + * is harmless + */ + if (last_unsent == NULL) { + pcb->unsent = queue; + } else { + last_unsent->next = queue; + } + + /* + * Finally update the pcb state. + */ + pcb->snd_lbb += len; + pcb->snd_buf -= len; + pcb->snd_queuelen = queuelen; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: %"S16_F" (after enqueued)\n", + pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_write: valid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + + /* Set the PSH flag in the last segment that we enqueued. */ + if (seg != NULL && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE)==0)) { + TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); + } + + return ERR_OK; +memerr: + pcb->flags |= TF_NAGLEMEMERR; + TCP_STATS_INC(tcp.memerr); + + if (concat_p != NULL) { + pbuf_free(concat_p); + } + if (queue != NULL) { + tcp_segs_free(queue); + } + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_write: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); + } + LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_write: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); + return ERR_MEM; +} + +/** + * Enqueue TCP options for transmission. + * + * Called by tcp_connect(), tcp_listen_input(), and tcp_send_ctrl(). + * + * @param pcb Protocol control block for the TCP connection. + * @param flags TCP header flags to set in the outgoing segment. + * @param optdata pointer to TCP options, or NULL. + * @param optlen length of TCP options in bytes. + */ +err_t +tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags) +{ + struct pbuf *p; + struct tcp_seg *seg; + u8_t optflags = 0; + u8_t optlen = 0; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + + LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)", + (flags & (TCP_SYN | TCP_FIN)) != 0); + + /* check for configured max queuelen and possible overflow */ + if ((pcb->snd_queuelen >= TCP_SND_QUEUELEN) || (pcb->snd_queuelen > TCP_SNDQUEUELEN_OVERFLOW)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue_flags: too long queue %"U16_F" (max %"U16_F")\n", + pcb->snd_queuelen, TCP_SND_QUEUELEN)); + TCP_STATS_INC(tcp.memerr); + pcb->flags |= TF_NAGLEMEMERR; + return ERR_MEM; + } + + if (flags & TCP_SYN) { + optflags = TF_SEG_OPTS_MSS; + } +#if LWIP_TCP_TIMESTAMPS + if ((pcb->flags & TF_TIMESTAMP)) { + optflags |= TF_SEG_OPTS_TS; + } +#endif /* LWIP_TCP_TIMESTAMPS */ + optlen = LWIP_TCP_OPT_LENGTH(optflags); + + /* tcp_enqueue_flags is always called with either SYN or FIN in flags. + * We need one available snd_buf byte to do that. + * This means we can't send FIN while snd_buf==0. A better fix would be to + * not include SYN and FIN sequence numbers in the snd_buf count. */ + if (pcb->snd_buf == 0) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue_flags: no send buffer available\n")); + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } + + /* Allocate pbuf with room for TCP header + options */ + if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + pcb->flags |= TF_NAGLEMEMERR; + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } + LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen", + (p->len >= optlen)); + + /* Allocate memory for tcp_seg, and fill in fields. */ + if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) { + pcb->flags |= TF_NAGLEMEMERR; + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } +//_RB_ Triggers with MEM_ALIGNMENT is 64 LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % MEM_ALIGNMENT) == 0); + LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0); + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, + ("tcp_enqueue_flags: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", + ntohl(seg->tcphdr->seqno), + ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), + (u16_t)flags)); + + /* Now append seg to pcb->unsent queue */ + if (pcb->unsent == NULL) { + pcb->unsent = seg; + } else { + struct tcp_seg *useg; + for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); + useg->next = seg; + } +#if TCP_OVERSIZE + /* The new unsent tail has no space */ + pcb->unsent_oversize = 0; +#endif /* TCP_OVERSIZE */ + + /* SYN and FIN bump the sequence number */ + if ((flags & TCP_SYN) || (flags & TCP_FIN)) { + pcb->snd_lbb++; + /* optlen does not influence snd_buf */ + pcb->snd_buf--; + } + if (flags & TCP_FIN) { + pcb->flags |= TF_FIN; + } + + /* update number of segments on the queues */ + pcb->snd_queuelen += pbuf_clen(seg->p); + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_enqueue_flags: invalid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + + return ERR_OK; +} + + +#if LWIP_TCP_TIMESTAMPS +/* Build a timestamp option (12 bytes long) at the specified options pointer) + * + * @param pcb tcp_pcb + * @param opts option pointer where to store the timestamp option + */ +static void +tcp_build_timestamp_option(struct tcp_pcb *pcb, u32_t *opts) +{ + /* Pad with two NOP options to make everything nicely aligned */ + opts[0] = PP_HTONL(0x0101080A); + opts[1] = htonl(sys_now()); + opts[2] = htonl(pcb->ts_recent); +} +#endif + +/** Send an ACK without data. + * + * @param pcb Protocol control block for the TCP connection to send the ACK + */ +err_t +tcp_send_empty_ack(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + u8_t optlen = 0; + +#if LWIP_TCP_TIMESTAMPS + if (pcb->flags & TF_TIMESTAMP) { + optlen = LWIP_TCP_OPT_LENGTH(TF_SEG_OPTS_TS); + } +#endif + + p = tcp_output_alloc_header(pcb, optlen, 0, htonl(pcb->snd_nxt)); + if (p == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); + return ERR_BUF; + } + tcphdr = (struct tcp_hdr *)p->payload; + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, + ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); + /* remove ACK flags from the PCB, as we send an empty ACK now */ + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + + /* NB. MSS option is only sent on SYNs, so ignore it here */ +#if LWIP_TCP_TIMESTAMPS + pcb->ts_lastacksent = pcb->rcv_nxt; + + if (pcb->flags & TF_TIMESTAMP) { + tcp_build_timestamp_option(pcb, (u32_t *)(tcphdr + 1)); + } +#endif + +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip), + IP_PROTO_TCP, p->tot_len); +#endif +#if LWIP_NETIF_HWADDRHINT + ip_output_hinted(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP, &(pcb->addr_hint)); +#else /* LWIP_NETIF_HWADDRHINT*/ + ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP); +#endif /* LWIP_NETIF_HWADDRHINT*/ + pbuf_free(p); + + return ERR_OK; +} + +/** + * Find out what we can send and send it + * + * @param pcb Protocol control block for the TCP connection to send data + * @return ERR_OK if data has been sent or nothing to send + * another err_t on error + */ +err_t +tcp_output(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg, *useg; + u32_t wnd, snd_nxt; +#if TCP_CWND_DEBUG + s16_t i = 0; +#endif /* TCP_CWND_DEBUG */ + + /* First, check if we are invoked by the TCP input processing + code. If so, we do not output anything. Instead, we rely on the + input processing code to call us when input processing is done + with. */ + if (tcp_input_pcb == pcb) { + return ERR_OK; + } + + wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); + + seg = pcb->unsent; + + /* If the TF_ACK_NOW flag is set and no data will be sent (either + * because the ->unsent queue is empty or because the window does + * not allow it), construct an empty ACK segment and send it. + * + * If data is to be sent, we will just piggyback the ACK (see below). + */ + if (pcb->flags & TF_ACK_NOW && + (seg == NULL || + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) { + return tcp_send_empty_ack(pcb); + } + + /* useg should point to last segment on unacked queue */ + useg = pcb->unacked; + if (useg != NULL) { + for (; useg->next != NULL; useg = useg->next); + } + +#if TCP_OUTPUT_DEBUG + if (seg == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", + (void*)pcb->unsent)); + } +#endif /* TCP_OUTPUT_DEBUG */ +#if TCP_CWND_DEBUG + if (seg == NULL) { + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F + ", cwnd %"U16_F", wnd %"U32_F + ", seg == NULL, ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack)); + } else { + LWIP_DEBUGF(TCP_CWND_DEBUG, + ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F + ", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, + ntohl(seg->tcphdr->seqno), pcb->lastack)); + } +#endif /* TCP_CWND_DEBUG */ + /* data available and window allows it to be sent? */ + while (seg != NULL && + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { + LWIP_ASSERT("RST not expected here!", + (TCPH_FLAGS(seg->tcphdr) & TCP_RST) == 0); + /* Stop sending if the nagle algorithm would prevent it + * Don't stop: + * - if tcp_write had a memory error before (prevent delayed ACK timeout) or + * - if FIN was already enqueued for this PCB (SYN is always alone in a segment - + * either seg->next != NULL or pcb->unacked == NULL; + * RST is no sent using tcp_write/tcp_output. + */ + if((tcp_do_output_nagle(pcb) == 0) && + ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)){ + break; + } +#if TCP_CWND_DEBUG + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) + seg->len - + pcb->lastack, + ntohl(seg->tcphdr->seqno), pcb->lastack, i)); + ++i; +#endif /* TCP_CWND_DEBUG */ + + pcb->unsent = seg->next; + + if (pcb->state != SYN_SENT) { + TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + } + + tcp_output_segment(seg, pcb); + snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { + pcb->snd_nxt = snd_nxt; + } + /* put segment on unacknowledged list if length > 0 */ + if (TCP_TCPLEN(seg) > 0) { + seg->next = NULL; + /* unacked list is empty? */ + if (pcb->unacked == NULL) { + pcb->unacked = seg; + useg = seg; + /* unacked list is not empty? */ + } else { + /* In the case of fast retransmit, the packet should not go to the tail + * of the unacked queue, but rather somewhere before it. We need to check for + * this case. -STJ Jul 27, 2004 */ + if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))) { + /* add segment to before tail of unacked list, keeping the list sorted */ + struct tcp_seg **cur_seg = &(pcb->unacked); + while (*cur_seg && + TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + } + seg->next = (*cur_seg); + (*cur_seg) = seg; + } else { + /* add segment to tail of unacked list */ + useg->next = seg; + useg = useg->next; + } + } + /* do not queue empty segments on the unacked list */ + } else { + tcp_seg_free(seg); + } + seg = pcb->unsent; + } +#if TCP_OVERSIZE + if (pcb->unsent == NULL) { + /* last unsent has been removed, reset unsent_oversize */ + pcb->unsent_oversize = 0; + } +#endif /* TCP_OVERSIZE */ + + if (seg != NULL && pcb->persist_backoff == 0 && + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > pcb->snd_wnd) { + /* prepare for persist timer */ + pcb->persist_cnt = 0; + pcb->persist_backoff = 1; + } + + pcb->flags &= ~TF_NAGLEMEMERR; + return ERR_OK; +} + +/** + * Called by tcp_output() to actually send a TCP segment over IP. + * + * @param seg the tcp_seg to send + * @param pcb the tcp_pcb for the TCP connection used to send the segment + */ +static void +tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb) +{ + u16_t len; + struct netif *netif; + u32_t *opts; + + /** @bug Exclude retransmitted segments from this count. */ + snmp_inc_tcpoutsegs(); + + /* The TCP header has already been constructed, but the ackno and + wnd fields remain. */ + seg->tcphdr->ackno = htonl(pcb->rcv_nxt); + + /* advertise our receive window size in this TCP segment */ + seg->tcphdr->wnd = htons(pcb->rcv_ann_wnd); + + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + + /* Add any requested options. NB MSS option is only set on SYN + packets, so ignore it here */ +//_RB_ LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % MEM_ALIGNMENT) == 0); + opts = (u32_t *)(void *)(seg->tcphdr + 1); + if (seg->flags & TF_SEG_OPTS_MSS) { + TCP_BUILD_MSS_OPTION(*opts); + opts += 1; + } +#if LWIP_TCP_TIMESTAMPS + pcb->ts_lastacksent = pcb->rcv_nxt; + + if (seg->flags & TF_SEG_OPTS_TS) { + tcp_build_timestamp_option(pcb, opts); + opts += 3; + } +#endif + + /* Set retransmission timer running if it is not currently enabled + This must be set before checking the route. */ + if (pcb->rtime == -1) { + pcb->rtime = 0; + } + + /* If we don't have a local IP address, we get one by + calling ip_route(). */ + if (ip_addr_isany(&(pcb->local_ip))) { + netif = ip_route(&(pcb->remote_ip)); + if (netif == NULL) { + return; + } + ip_addr_copy(pcb->local_ip, netif->ip_addr); + } + + if (pcb->rttest == 0) { + pcb->rttest = tcp_ticks; + pcb->rtseq = ntohl(seg->tcphdr->seqno); + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", + htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) + + seg->len)); + + len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); + + seg->p->len -= len; + seg->p->tot_len -= len; + + seg->p->payload = seg->tcphdr; + + seg->tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP +#if TCP_CHECKSUM_ON_COPY + { + u32_t acc; +#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK + u16_t chksum_slow = inet_chksum_pseudo(seg->p, &(pcb->local_ip), + &(pcb->remote_ip), + IP_PROTO_TCP, seg->p->tot_len); +#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */ + if ((seg->flags & TF_SEG_DATA_CHECKSUMMED) == 0) { + LWIP_ASSERT("data included but not checksummed", + seg->p->tot_len == (TCPH_HDRLEN(seg->tcphdr) * 4)); + } + + /* rebuild TCP header checksum (TCP header changes for retransmissions!) */ + acc = inet_chksum_pseudo_partial(seg->p, &(pcb->local_ip), + &(pcb->remote_ip), + IP_PROTO_TCP, seg->p->tot_len, TCPH_HDRLEN(seg->tcphdr) * 4); + /* add payload checksum */ + if (seg->chksum_swapped) { + seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum); + seg->chksum_swapped = 0; + } + acc += (u16_t)~(seg->chksum); + seg->tcphdr->chksum = FOLD_U32T(acc); +#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK + if (chksum_slow != seg->tcphdr->chksum) { + LWIP_DEBUGF(TCP_DEBUG | LWIP_DBG_LEVEL_WARNING, + ("tcp_output_segment: calculated checksum is %"X16_F" instead of %"X16_F"\n", + seg->tcphdr->chksum, chksum_slow)); + seg->tcphdr->chksum = chksum_slow; + } +#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */ + } +#else /* TCP_CHECKSUM_ON_COPY */ + seg->tcphdr->chksum = inet_chksum_pseudo(seg->p, &(pcb->local_ip), + &(pcb->remote_ip), + IP_PROTO_TCP, seg->p->tot_len); +#endif /* TCP_CHECKSUM_ON_COPY */ +#endif /* CHECKSUM_GEN_TCP */ + TCP_STATS_INC(tcp.xmit); + +#if LWIP_NETIF_HWADDRHINT + ip_output_hinted(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP, &(pcb->addr_hint)); +#else /* LWIP_NETIF_HWADDRHINT*/ + ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP); +#endif /* LWIP_NETIF_HWADDRHINT*/ +} + +/** + * Send a TCP RESET packet (empty segment with RST flag set) either to + * abort a connection or to show that there is no matching local connection + * for a received segment. + * + * Called by tcp_abort() (to abort a local connection), tcp_input() (if no + * matching local pcb was found), tcp_listen_input() (if incoming segment + * has ACK flag set) and tcp_process() (received segment in the wrong state) + * + * Since a RST segment is in most cases not sent for an active connection, + * tcp_rst() has a number of arguments that are taken from a tcp_pcb for + * most other segment output functions. + * + * @param seqno the sequence number to use for the outgoing segment + * @param ackno the acknowledge number to use for the outgoing segment + * @param local_ip the local IP address to send the segment from + * @param remote_ip the remote IP address to send the segment to + * @param local_port the local TCP port to send the segment from + * @param remote_port the remote TCP port to send the segment to + */ +void +tcp_rst(u32_t seqno, u32_t ackno, + ip_addr_t *local_ip, ip_addr_t *remote_ip, + u16_t local_port, u16_t remote_port) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); + return; + } + LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", + (p->len >= sizeof(struct tcp_hdr))); + + tcphdr = (struct tcp_hdr *)p->payload; + tcphdr->src = htons(local_port); + tcphdr->dest = htons(remote_port); + tcphdr->seqno = htonl(seqno); + tcphdr->ackno = htonl(ackno); + TCPH_HDRLEN_FLAGS_SET(tcphdr, TCP_HLEN/4, TCP_RST | TCP_ACK); + tcphdr->wnd = PP_HTONS(TCP_WND); + tcphdr->chksum = 0; + tcphdr->urgp = 0; + +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip, + IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + snmp_inc_tcpoutrsts(); + /* Send output with hardcoded TTL since we have no access to the pcb */ + ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP); + pbuf_free(p); + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); +} + +/** + * Requeue all unacked segments for retransmission + * + * Called by tcp_slowtmr() for slow retransmission. + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +void +tcp_rexmit_rto(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + + if (pcb->unacked == NULL) { + return; + } + + /* Move all unacked segments to the head of the unsent queue */ + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next); + /* concatenate unsent queue after unacked queue */ + seg->next = pcb->unsent; + /* unsent queue is the concatenated queue (of unacked, unsent) */ + pcb->unsent = pcb->unacked; + /* unacked queue is now empty */ + pcb->unacked = NULL; + + /* increment number of retransmissions */ + ++pcb->nrtx; + + /* Don't take any RTT measurements after retransmitting. */ + pcb->rttest = 0; + + /* Do the actual retransmission */ + tcp_output(pcb); +} + +/** + * Requeue the first unacked segment for retransmission + * + * Called by tcp_receive() for fast retramsmit. + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +void +tcp_rexmit(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + struct tcp_seg **cur_seg; + + if (pcb->unacked == NULL) { + return; + } + + /* Move the first unacked segment to the unsent queue */ + /* Keep the unsent queue sorted. */ + seg = pcb->unacked; + pcb->unacked = seg->next; + + cur_seg = &(pcb->unsent); + while (*cur_seg && + TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + } + seg->next = *cur_seg; + *cur_seg = seg; + + ++pcb->nrtx; + + /* Don't take any rtt measurements after retransmitting. */ + pcb->rttest = 0; + + /* Do the actual retransmission. */ + snmp_inc_tcpretranssegs(); + /* No need to call tcp_output: we are always called from tcp_input() + and thus tcp_output directly returns. */ +} + + +/** + * Handle retransmission after three dupacks received + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +void +tcp_rexmit_fast(struct tcp_pcb *pcb) +{ + if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) { + /* This is fast retransmit. Retransmit the first unacked segment. */ + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: dupacks %"U16_F" (%"U32_F + "), fast retransmit %"U32_F"\n", + (u16_t)pcb->dupacks, pcb->lastack, + ntohl(pcb->unacked->tcphdr->seqno))); + tcp_rexmit(pcb); + + /* Set ssthresh to half of the minimum of the current + * cwnd and the advertised window */ + if (pcb->cwnd > pcb->snd_wnd) { + pcb->ssthresh = pcb->snd_wnd / 2; + } else { + pcb->ssthresh = pcb->cwnd / 2; + } + + /* The minimum value for ssthresh should be 2 MSS */ + if (pcb->ssthresh < 2*pcb->mss) { + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: The minimum value for ssthresh %"U16_F + " should be min 2 mss %"U16_F"...\n", + pcb->ssthresh, 2*pcb->mss)); + pcb->ssthresh = 2*pcb->mss; + } + + pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; + pcb->flags |= TF_INFR; + } +} + + +/** + * Send keepalive packets to keep a connection active although + * no data is sent over it. + * + * Called by tcp_slowtmr() + * + * @param pcb the tcp_pcb for which to send a keepalive packet + */ +void +tcp_keepalive(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(&pcb->remote_ip), ip4_addr2_16(&pcb->remote_ip), + ip4_addr3_16(&pcb->remote_ip), ip4_addr4_16(&pcb->remote_ip))); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, pcb->keep_cnt_sent)); + + p = tcp_output_alloc_header(pcb, 0, 0, htonl(pcb->snd_nxt - 1)); + if(p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_keepalive: could not allocate memory for pbuf\n")); + return; + } + tcphdr = (struct tcp_hdr *)p->payload; + +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, + IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + + /* Send output to IP */ +#if LWIP_NETIF_HWADDRHINT + ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP, + &(pcb->addr_hint)); +#else /* LWIP_NETIF_HWADDRHINT*/ + ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); +#endif /* LWIP_NETIF_HWADDRHINT*/ + + pbuf_free(p); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", + pcb->snd_nxt - 1, pcb->rcv_nxt)); +} + + +/** + * Send persist timer zero-window probes to keep a connection active + * when a window update is lost. + * + * Called by tcp_slowtmr() + * + * @param pcb the tcp_pcb for which to send a zero-window probe packet + */ +void +tcp_zero_window_probe(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + struct tcp_seg *seg; + u16_t len; + u8_t is_fin; + + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_zero_window_probe: sending ZERO WINDOW probe to %" + U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(&pcb->remote_ip), ip4_addr2_16(&pcb->remote_ip), + ip4_addr3_16(&pcb->remote_ip), ip4_addr4_16(&pcb->remote_ip))); + + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_zero_window_probe: tcp_ticks %"U32_F + " pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, pcb->keep_cnt_sent)); + + seg = pcb->unacked; + + if(seg == NULL) { + seg = pcb->unsent; + } + if(seg == NULL) { + return; + } + + is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0); + /* we want to send one seqno: either FIN or data (no options) */ + len = is_fin ? 0 : 1; + + p = tcp_output_alloc_header(pcb, 0, len, seg->tcphdr->seqno); + if(p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n")); + return; + } + tcphdr = (struct tcp_hdr *)p->payload; + + if (is_fin) { + /* FIN segment, no data */ + TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN); + } else { + /* Data segment, copy in one byte from the head of the unacked queue */ + struct tcp_hdr *thdr = (struct tcp_hdr *)seg->p->payload; + char *d = ((char *)p->payload + TCP_HLEN); + pbuf_copy_partial(seg->p, d, 1, TCPH_HDRLEN(thdr) * 4); + } + +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, + IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + + /* Send output to IP */ +#if LWIP_NETIF_HWADDRHINT + ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP, + &(pcb->addr_hint)); +#else /* LWIP_NETIF_HWADDRHINT*/ + ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); +#endif /* LWIP_NETIF_HWADDRHINT*/ + + pbuf_free(p); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F + " ackno %"U32_F".\n", + pcb->snd_nxt - 1, pcb->rcv_nxt)); +} +#endif /* LWIP_TCP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/udp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/udp.c new file mode 100644 index 0000000..4596ba2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/core/udp.c @@ -0,0 +1,966 @@ +/** + * @file + * User Datagram Protocol module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +/* udp.c + * + * The code for the User Datagram Protocol UDP & UDPLite (RFC 3828). + * + */ + +/* @todo Check the use of '(struct udp_pcb).chksum_len_rx'! + */ + +#include "lwip/opt.h" + +#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/udp.h" +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/inet_chksum.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/icmp.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "arch/perf.h" +#include "lwip/dhcp.h" + +#include + +/* The list of UDP PCBs */ +/* exported in udp.h (was static) */ +struct udp_pcb *udp_pcbs; + +/** + * Process an incoming UDP datagram. + * + * Given an incoming UDP datagram (as a chain of pbufs) this function + * finds a corresponding UDP PCB and hands over the pbuf to the pcbs + * recv function. If no pcb is found or the datagram is incorrect, the + * pbuf is freed. + * + * @param p pbuf to be demultiplexed to a UDP PCB. + * @param inp network interface on which the datagram was received. + * + */ +void +udp_input(struct pbuf *p, struct netif *inp) +{ + struct udp_hdr *udphdr; + struct udp_pcb *pcb, *prev; + struct udp_pcb *uncon_pcb; + struct ip_hdr *iphdr; + u16_t src, dest; + u8_t local_match; + u8_t broadcast; + + PERF_START; + + UDP_STATS_INC(udp.recv); + + iphdr = (struct ip_hdr *)p->payload; + + /* Check minimum length (IP header + UDP header) + * and move payload pointer to UDP header */ + if (p->tot_len < (IPH_HL(iphdr) * 4 + UDP_HLEN) || pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4))) { + /* drop short packets */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); + UDP_STATS_INC(udp.lenerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + + udphdr = (struct udp_hdr *)p->payload; + + /* is broadcast packet ? */ + broadcast = ip_addr_isbroadcast(¤t_iphdr_dest, inp); + + LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); + + /* convert src and dest ports to host byte order */ + src = ntohs(udphdr->src); + dest = ntohs(udphdr->dest); + + udp_debug_print(udphdr); + + /* print the UDP source and destination */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- " + "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", + ip4_addr1_16(&iphdr->dest), ip4_addr2_16(&iphdr->dest), + ip4_addr3_16(&iphdr->dest), ip4_addr4_16(&iphdr->dest), ntohs(udphdr->dest), + ip4_addr1_16(&iphdr->src), ip4_addr2_16(&iphdr->src), + ip4_addr3_16(&iphdr->src), ip4_addr4_16(&iphdr->src), ntohs(udphdr->src))); + +#if LWIP_DHCP + pcb = NULL; + /* when LWIP_DHCP is active, packets to DHCP_CLIENT_PORT may only be processed by + the dhcp module, no other UDP pcb may use the local UDP port DHCP_CLIENT_PORT */ + if (dest == DHCP_CLIENT_PORT) { + /* all packets for DHCP_CLIENT_PORT not coming from DHCP_SERVER_PORT are dropped! */ + if (src == DHCP_SERVER_PORT) { + if ((inp->dhcp != NULL) && (inp->dhcp->pcb != NULL)) { + /* accept the packe if + (- broadcast or directed to us) -> DHCP is link-layer-addressed, local ip is always ANY! + - inp->dhcp->pcb->remote == ANY or iphdr->src */ + if ((ip_addr_isany(&inp->dhcp->pcb->remote_ip) || + ip_addr_cmp(&(inp->dhcp->pcb->remote_ip), ¤t_iphdr_src))) { + pcb = inp->dhcp->pcb; + } + } + } + } else +#endif /* LWIP_DHCP */ + { + prev = NULL; + local_match = 0; + uncon_pcb = NULL; + /* Iterate through the UDP pcb list for a matching pcb. + * 'Perfect match' pcbs (connected to the remote port & ip address) are + * preferred. If no perfect match is found, the first unconnected pcb that + * matches the local port and ip address gets the datagram. */ + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + local_match = 0; + /* print the PCB local and remote address */ + LWIP_DEBUGF(UDP_DEBUG, + ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- " + "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", + ip4_addr1_16(&pcb->local_ip), ip4_addr2_16(&pcb->local_ip), + ip4_addr3_16(&pcb->local_ip), ip4_addr4_16(&pcb->local_ip), pcb->local_port, + ip4_addr1_16(&pcb->remote_ip), ip4_addr2_16(&pcb->remote_ip), + ip4_addr3_16(&pcb->remote_ip), ip4_addr4_16(&pcb->remote_ip), pcb->remote_port)); + + /* compare PCB local addr+port to UDP destination addr+port */ + if ((pcb->local_port == dest) && + ((!broadcast && ip_addr_isany(&pcb->local_ip)) || + ip_addr_cmp(&(pcb->local_ip), ¤t_iphdr_dest) || +#if LWIP_IGMP + ip_addr_ismulticast(¤t_iphdr_dest) || +#endif /* LWIP_IGMP */ +#if IP_SOF_BROADCAST_RECV + (broadcast && (pcb->so_options & SOF_BROADCAST)))) { +#else /* IP_SOF_BROADCAST_RECV */ + (broadcast))) { +#endif /* IP_SOF_BROADCAST_RECV */ + local_match = 1; + if ((uncon_pcb == NULL) && + ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) { + /* the first unconnected matching PCB */ + uncon_pcb = pcb; + } + } + /* compare PCB remote addr+port to UDP source addr+port */ + if ((local_match != 0) && + (pcb->remote_port == src) && + (ip_addr_isany(&pcb->remote_ip) || + ip_addr_cmp(&(pcb->remote_ip), ¤t_iphdr_src))) { + /* the first fully matching PCB */ + if (prev != NULL) { + /* move the pcb to the front of udp_pcbs so that is + found faster next time */ + prev->next = pcb->next; + pcb->next = udp_pcbs; + udp_pcbs = pcb; + } else { + UDP_STATS_INC(udp.cachehit); + } + break; + } + prev = pcb; + } + /* no fully matching pcb found? then look for an unconnected pcb */ + if (pcb == NULL) { + pcb = uncon_pcb; + } + } + + /* Check checksum if this is a match or if it was directed at us. */ + if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, ¤t_iphdr_dest)) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: calculating checksum\n")); +#if LWIP_UDPLITE + if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) { + /* Do the UDP Lite checksum */ +#if CHECKSUM_CHECK_UDP + u16_t chklen = ntohs(udphdr->len); + if (chklen < sizeof(struct udp_hdr)) { + if (chklen == 0) { + /* For UDP-Lite, checksum length of 0 means checksum + over the complete packet (See RFC 3828 chap. 3.1) */ + chklen = p->tot_len; + } else { + /* At least the UDP-Lite header must be covered by the + checksum! (Again, see RFC 3828 chap. 3.1) */ + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + } + if (inet_chksum_pseudo_partial(p, ¤t_iphdr_src, ¤t_iphdr_dest, + IP_PROTO_UDPLITE, p->tot_len, chklen) != 0) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("udp_input: UDP Lite datagram discarded due to failing checksum\n")); + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } +#endif /* CHECKSUM_CHECK_UDP */ + } else +#endif /* LWIP_UDPLITE */ + { +#if CHECKSUM_CHECK_UDP + if (udphdr->chksum != 0) { + if (inet_chksum_pseudo(p, ip_current_src_addr(), ip_current_dest_addr(), + IP_PROTO_UDP, p->tot_len) != 0) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("udp_input: UDP datagram discarded due to failing checksum\n")); + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + } +#endif /* CHECKSUM_CHECK_UDP */ + } + if(pbuf_header(p, -UDP_HLEN)) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_header failed\n", 0); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + if (pcb != NULL) { + snmp_inc_udpindatagrams(); +#if SO_REUSE && SO_REUSE_RXTOALL + if ((broadcast || ip_addr_ismulticast(¤t_iphdr_dest)) && + ((pcb->so_options & SOF_REUSEADDR) != 0)) { + /* pass broadcast- or multicast packets to all multicast pcbs + if SOF_REUSEADDR is set on the first match */ + struct udp_pcb *mpcb; + u8_t p_header_changed = 0; + for (mpcb = udp_pcbs; mpcb != NULL; mpcb = mpcb->next) { + if (mpcb != pcb) { + /* compare PCB local addr+port to UDP destination addr+port */ + if ((mpcb->local_port == dest) && + ((!broadcast && ip_addr_isany(&mpcb->local_ip)) || + ip_addr_cmp(&(mpcb->local_ip), ¤t_iphdr_dest) || +#if LWIP_IGMP + ip_addr_ismulticast(¤t_iphdr_dest) || +#endif /* LWIP_IGMP */ +#if IP_SOF_BROADCAST_RECV + (broadcast && (mpcb->so_options & SOF_BROADCAST)))) { +#else /* IP_SOF_BROADCAST_RECV */ + (broadcast))) { +#endif /* IP_SOF_BROADCAST_RECV */ + /* pass a copy of the packet to all local matches */ + if (mpcb->recv != NULL) { + struct pbuf *q; + /* for that, move payload to IP header again */ + if (p_header_changed == 0) { + pbuf_header(p, (s16_t)((IPH_HL(iphdr) * 4) + UDP_HLEN)); + p_header_changed = 1; + } + q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if (q != NULL) { + err_t err = pbuf_copy(q, p); + if (err == ERR_OK) { + /* move payload to UDP data */ + pbuf_header(q, -(s16_t)((IPH_HL(iphdr) * 4) + UDP_HLEN)); + mpcb->recv(mpcb->recv_arg, mpcb, q, ip_current_src_addr(), src); + } + } + } + } + } + } + if (p_header_changed) { + /* and move payload to UDP data again */ + pbuf_header(p, -(s16_t)((IPH_HL(iphdr) * 4) + UDP_HLEN)); + } + } +#endif /* SO_REUSE && SO_REUSE_RXTOALL */ + /* callback */ + if (pcb->recv != NULL) { + /* now the recv function is responsible for freeing p */ + pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src); + } else { + /* no recv function registered? then we have to free the pbuf! */ + pbuf_free(p); + goto end; + } + } else { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: not for us.\n")); + +#if LWIP_ICMP + /* No match was found, send ICMP destination port unreachable unless + destination address was broadcast/multicast. */ + if (!broadcast && + !ip_addr_ismulticast(¤t_iphdr_dest)) { + /* move payload pointer back to ip header */ + pbuf_header(p, (IPH_HL(iphdr) * 4) + UDP_HLEN); + LWIP_ASSERT("p->payload == iphdr", (p->payload == iphdr)); + icmp_dest_unreach(p, ICMP_DUR_PORT); + } +#endif /* LWIP_ICMP */ + UDP_STATS_INC(udp.proterr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpnoports(); + pbuf_free(p); + } + } else { + pbuf_free(p); + } +end: + PERF_STOP("udp_input"); +} + +/** + * Send data using UDP. + * + * @param pcb UDP PCB used to send the data. + * @param p chain of pbuf's to be sent. + * + * The datagram will be sent to the current remote_ip & remote_port + * stored in pcb. If the pcb is not bound to a port, it will + * automatically be bound to a random port. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_MEM. Out of memory. + * - ERR_RTE. Could not find route to destination address. + * - More errors could be returned by lower protocol layers. + * + * @see udp_disconnect() udp_sendto() + */ +err_t +udp_send(struct udp_pcb *pcb, struct pbuf *p) +{ + /* send to the packet using remote ip and port stored in the pcb */ + return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port); +} + +#if LWIP_CHECKSUM_ON_COPY +/** Same as udp_send() but with checksum + */ +err_t +udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p, + u8_t have_chksum, u16_t chksum) +{ + /* send to the packet using remote ip and port stored in the pcb */ + return udp_sendto_chksum(pcb, p, &pcb->remote_ip, pcb->remote_port, + have_chksum, chksum); +} +#endif /* LWIP_CHECKSUM_ON_COPY */ + +/** + * Send data to a specified address using UDP. + * + * @param pcb UDP PCB used to send the data. + * @param p chain of pbuf's to be sent. + * @param dst_ip Destination IP address. + * @param dst_port Destination UDP port. + * + * dst_ip & dst_port are expected to be in the same byte order as in the pcb. + * + * If the PCB already has a remote address association, it will + * be restored after the data is sent. + * + * @return lwIP error code (@see udp_send for possible error codes) + * + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto(struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port) +{ +#if LWIP_CHECKSUM_ON_COPY + return udp_sendto_chksum(pcb, p, dst_ip, dst_port, 0, 0); +} + +/** Same as udp_sendto(), but with checksum */ +err_t +udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *dst_ip, + u16_t dst_port, u8_t have_chksum, u16_t chksum) +{ +#endif /* LWIP_CHECKSUM_ON_COPY */ + struct netif *netif; + + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send\n")); + + /* find the outgoing network interface for this packet */ +#if LWIP_IGMP + netif = ip_route((ip_addr_ismulticast(dst_ip))?(&(pcb->multicast_ip)):(dst_ip)); +#else + netif = ip_route(dst_ip); +#endif /* LWIP_IGMP */ + + /* no outgoing network interface could be found? */ + if (netif == NULL) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(dst_ip), ip4_addr2_16(dst_ip), ip4_addr3_16(dst_ip), ip4_addr4_16(dst_ip))); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + } +#if LWIP_CHECKSUM_ON_COPY + return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum); +#else /* LWIP_CHECKSUM_ON_COPY */ + return udp_sendto_if(pcb, p, dst_ip, dst_port, netif); +#endif /* LWIP_CHECKSUM_ON_COPY */ +} + +/** + * Send data to a specified address using UDP. + * The netif used for sending can be specified. + * + * This function exists mainly for DHCP, to be able to send UDP packets + * on a netif that is still down. + * + * @param pcb UDP PCB used to send the data. + * @param p chain of pbuf's to be sent. + * @param dst_ip Destination IP address. + * @param dst_port Destination UDP port. + * @param netif the netif used for sending. + * + * dst_ip & dst_port are expected to be in the same byte order as in the pcb. + * + * @return lwIP error code (@see udp_send for possible error codes) + * + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif) +{ +#if LWIP_CHECKSUM_ON_COPY + return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, 0, 0); +} + +/** Same as udp_sendto_if(), but with checksum */ +err_t +udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *dst_ip, + u16_t dst_port, struct netif *netif, u8_t have_chksum, + u16_t chksum) +{ +#endif /* LWIP_CHECKSUM_ON_COPY */ + struct udp_hdr *udphdr; + ip_addr_t *src_ip; + err_t err; + struct pbuf *q; /* q will be sent down the stack */ + +#if IP_SOF_BROADCAST + /* broadcast filter? */ + if ( ((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(dst_ip, netif) ) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("udp_sendto_if: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); + return ERR_VAL; + } +#endif /* IP_SOF_BROADCAST */ + + /* if the PCB is not yet bound to a port, bind it here */ + if (pcb->local_port == 0) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n")); + err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n")); + return err; + } + } + + /* not enough space to add an UDP header to first pbuf in given p chain? */ + if (pbuf_header(p, UDP_HLEN)) { + /* allocate header in a separate new pbuf */ + q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n")); + return ERR_MEM; + } + if (p->tot_len != 0) { + /* chain header q in front of given pbuf p (only if p contains data) */ + pbuf_chain(q, p); + } + /* first pbuf q points to header pbuf */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* adding space for header within p succeeded */ + /* first pbuf q equals given pbuf */ + q = p; + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); + } + LWIP_ASSERT("check that first pbuf can hold struct udp_hdr", + (q->len >= sizeof(struct udp_hdr))); + /* q now represents the packet to be sent */ + udphdr = (struct udp_hdr *)q->payload; + udphdr->src = htons(pcb->local_port); + udphdr->dest = htons(dst_port); + /* in UDP, 0 checksum means 'no checksum' */ + udphdr->chksum = 0x0000; + + /* Multicast Loop? */ +#if LWIP_IGMP + if (ip_addr_ismulticast(dst_ip) && ((pcb->flags & UDP_FLAGS_MULTICAST_LOOP) != 0)) { + q->flags |= PBUF_FLAG_MCASTLOOP; + } +#endif /* LWIP_IGMP */ + + + /* PCB local address is IP_ANY_ADDR? */ + if (ip_addr_isany(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ + src_ip = &(netif->ip_addr); + } else { + /* check if UDP PCB local IP address is correct + * this could be an old address if netif->ip_addr has changed */ + if (!ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) { + /* local_ip doesn't match, drop the packet */ + if (q != p) { + /* free the header pbuf */ + pbuf_free(q); + q = NULL; + /* p is still referenced by the caller, and will live on */ + } + return ERR_VAL; + } + /* use UDP PCB local IP address as source address */ + src_ip = &(pcb->local_ip); + } + + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); + +#if LWIP_UDPLITE + /* UDP Lite protocol? */ + if (pcb->flags & UDP_FLAGS_UDPLITE) { + u16_t chklen, chklen_hdr; + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); + /* set UDP message length in UDP header */ + chklen_hdr = chklen = pcb->chksum_len_tx; + if ((chklen < sizeof(struct udp_hdr)) || (chklen > q->tot_len)) { + if (chklen != 0) { + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE pcb->chksum_len is illegal: %"U16_F"\n", chklen)); + } + /* For UDP-Lite, checksum length of 0 means checksum + over the complete packet. (See RFC 3828 chap. 3.1) + At least the UDP-Lite header must be covered by the + checksum, therefore, if chksum_len has an illegal + value, we generate the checksum over the complete + packet to be safe. */ + chklen_hdr = 0; + chklen = q->tot_len; + } + udphdr->len = htons(chklen_hdr); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + udphdr->chksum = inet_chksum_pseudo_partial(q, src_ip, dst_ip, + IP_PROTO_UDPLITE, q->tot_len, +#if !LWIP_CHECKSUM_ON_COPY + chklen); +#else /* !LWIP_CHECKSUM_ON_COPY */ + (have_chksum ? UDP_HLEN : chklen)); + if (have_chksum) { + u32_t acc; + acc = udphdr->chksum + (u16_t)~(chksum); + udphdr->chksum = FOLD_U32T(acc); + } +#endif /* !LWIP_CHECKSUM_ON_COPY */ + + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udphdr->chksum == 0x0000) { + udphdr->chksum = 0xffff; + } +#endif /* CHECKSUM_GEN_UDP */ + /* output to IP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n")); +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = &(pcb->addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT*/ + err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif); +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = NULL; +#endif /* LWIP_NETIF_HWADDRHINT*/ + } else +#endif /* LWIP_UDPLITE */ + { /* UDP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); + udphdr->len = htons(q->tot_len); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) { + u16_t udpchksum; +#if LWIP_CHECKSUM_ON_COPY + if (have_chksum) { + u32_t acc; + udpchksum = inet_chksum_pseudo_partial(q, src_ip, dst_ip, IP_PROTO_UDP, + q->tot_len, UDP_HLEN); + acc = udpchksum + (u16_t)~(chksum); + udpchksum = FOLD_U32T(acc); + } else +#endif /* LWIP_CHECKSUM_ON_COPY */ + { + udpchksum = inet_chksum_pseudo(q, src_ip, dst_ip, IP_PROTO_UDP, q->tot_len); + } + + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udpchksum == 0x0000) { + udpchksum = 0xffff; + } + udphdr->chksum = udpchksum; + } +#endif /* CHECKSUM_GEN_UDP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n")); + /* output to IP */ +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = &(pcb->addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT*/ + err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif); +#if LWIP_NETIF_HWADDRHINT + netif->addr_hint = NULL; +#endif /* LWIP_NETIF_HWADDRHINT*/ + } + /* TODO: must this be increased even if error occured? */ + snmp_inc_udpoutdatagrams(); + + /* did we chain a separate header pbuf earlier? */ + if (q != p) { + /* free the header pbuf */ + pbuf_free(q); + q = NULL; + /* p is still referenced by the caller, and will live on */ + } + + UDP_STATS_INC(udp.xmit); + return err; +} + +/** + * Bind an UDP PCB. + * + * @param pcb UDP PCB to be bound with a local address ipaddr and port. + * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to + * bind to all local interfaces. + * @param port local UDP port to bind with. Use 0 to automatically bind + * to a random port between UDP_LOCAL_PORT_RANGE_START and + * UDP_LOCAL_PORT_RANGE_END. + * + * ipaddr & port are expected to be in the same byte order as in the pcb. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_USE. The specified ipaddr and port are already bound to by + * another UDP PCB. + * + * @see udp_disconnect() + */ +err_t +udp_bind(struct udp_pcb *pcb, ip_addr_t *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + u8_t rebind; + + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = ")); + ip_addr_debug_print(UDP_DEBUG, ipaddr); + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port)); + + rebind = 0; + /* Check for double bind and rebind of the same pcb */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + /* is this UDP PCB already on active list? */ + if (pcb == ipcb) { + /* pcb may occur at most once in active list */ + LWIP_ASSERT("rebind == 0", rebind == 0); + /* pcb already in list, just rebind */ + rebind = 1; + } + + /* By default, we don't allow to bind to a port that any other udp + PCB is alread bound to, unless *all* PCBs with that port have tha + REUSEADDR flag set. */ +#if SO_REUSE + else if (((pcb->so_options & SOF_REUSEADDR) == 0) && + ((ipcb->so_options & SOF_REUSEADDR) == 0)) { +#else /* SO_REUSE */ + /* port matches that of PCB in list and REUSEADDR not set -> reject */ + else { +#endif /* SO_REUSE */ + if ((ipcb->local_port == port) && + /* IP address matches, or one is IP_ADDR_ANY? */ + (ip_addr_isany(&(ipcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(ipcb->local_ip), ipaddr))) { + /* other PCB already binds to this local IP and port */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); + return ERR_USE; + } + } + } + + ip_addr_set(&pcb->local_ip, ipaddr); + + /* no port specified? */ + if (port == 0) { +#ifndef UDP_LOCAL_PORT_RANGE_START +/* From http://www.iana.org/assignments/port-numbers: + "The Dynamic and/or Private Ports are those from 49152 through 65535" */ +#define UDP_LOCAL_PORT_RANGE_START 0xc000 +#define UDP_LOCAL_PORT_RANGE_END 0xffff +#endif + port = UDP_LOCAL_PORT_RANGE_START; + ipcb = udp_pcbs; + while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) { + if (ipcb->local_port == port) { + /* port is already used by another udp_pcb */ + port++; + /* restart scanning all udp pcbs */ + ipcb = udp_pcbs; + } else { + /* go on with next udp pcb */ + ipcb = ipcb->next; + } + } + if (ipcb != NULL) { + /* no more ports available in local range */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); + return ERR_USE; + } + } + pcb->local_port = port; + snmp_insert_udpidx_tree(pcb); + /* pcb not active yet? */ + if (rebind == 0) { + /* place the PCB on the active list if not already there */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + } + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n", + ip4_addr1_16(&pcb->local_ip), ip4_addr2_16(&pcb->local_ip), + ip4_addr3_16(&pcb->local_ip), ip4_addr4_16(&pcb->local_ip), + pcb->local_port)); + return ERR_OK; +} +/** + * Connect an UDP PCB. + * + * This will associate the UDP PCB with the remote address. + * + * @param pcb UDP PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * @param port remote UDP port to connect with. + * + * @return lwIP error code + * + * ipaddr & port are expected to be in the same byte order as in the pcb. + * + * The udp pcb is bound to a random local port if not already bound. + * + * @see udp_disconnect() + */ +err_t +udp_connect(struct udp_pcb *pcb, ip_addr_t *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + + if (pcb->local_port == 0) { + err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) { + return err; + } + } + + ip_addr_set(&pcb->remote_ip, ipaddr); + pcb->remote_port = port; + pcb->flags |= UDP_FLAGS_CONNECTED; +/** TODO: this functionality belongs in upper layers */ +#ifdef LWIP_UDP_TODO + /* Nail down local IP for netconn_addr()/getsockname() */ + if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) { + struct netif *netif; + + if ((netif = ip_route(&(pcb->remote_ip))) == NULL) { + LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr)); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + } + /** TODO: this will bind the udp pcb locally, to the interface which + is used to route output packets to the remote address. However, we + might want to accept incoming packets on any interface! */ + pcb->local_ip = netif->ip_addr; + } else if (ip_addr_isany(&pcb->remote_ip)) { + pcb->local_ip.addr = 0; + } +#endif + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n", + ip4_addr1_16(&pcb->local_ip), ip4_addr2_16(&pcb->local_ip), + ip4_addr3_16(&pcb->local_ip), ip4_addr4_16(&pcb->local_ip), + pcb->local_port)); + + /* Insert UDP PCB into the list of active UDP PCBs. */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + if (pcb == ipcb) { + /* already on the list, just return */ + return ERR_OK; + } + } + /* PCB not yet on the list, add PCB now */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + return ERR_OK; +} + +/** + * Disconnect a UDP PCB + * + * @param pcb the udp pcb to disconnect. + */ +void +udp_disconnect(struct udp_pcb *pcb) +{ + /* reset remote address association */ + ip_addr_set_any(&pcb->remote_ip); + pcb->remote_port = 0; + /* mark PCB as unconnected */ + pcb->flags &= ~UDP_FLAGS_CONNECTED; +} + +/** + * Set a receive callback for a UDP PCB + * + * This callback will be called when receiving a datagram for the pcb. + * + * @param pcb the pcb for wich to set the recv callback + * @param recv function pointer of the callback function + * @param recv_arg additional argument to pass to the callback function + */ +void +udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg) +{ + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * Remove an UDP PCB. + * + * @param pcb UDP PCB to be removed. The PCB is removed from the list of + * UDP PCB's and the data structure is freed from memory. + * + * @see udp_new() + */ +void +udp_remove(struct udp_pcb *pcb) +{ + struct udp_pcb *pcb2; + + snmp_delete_udpidx_tree(pcb); + /* pcb to be removed is first in list? */ + if (udp_pcbs == pcb) { + /* make list start at 2nd pcb */ + udp_pcbs = udp_pcbs->next; + /* pcb not 1st in list */ + } else { + for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in udp_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + } + } + } + memp_free(MEMP_UDP_PCB, pcb); +} + +/** + * Create a UDP PCB. + * + * @return The UDP PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @see udp_remove() + */ +struct udp_pcb * +udp_new(void) +{ + struct udp_pcb *pcb; + pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB); + /* could allocate UDP PCB? */ + if (pcb != NULL) { + /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0 + * which means checksum is generated over the whole datagram per default + * (recommended as default by RFC 3828). */ + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct udp_pcb)); + pcb->ttl = UDP_TTL; + } + return pcb; +} + +#if UDP_DEBUG +/** + * Print UDP header information for debug purposes. + * + * @param udphdr pointer to the udp header in memory. + */ +void +udp_debug_print(struct udp_hdr *udphdr) +{ + LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + ntohs(udphdr->src), ntohs(udphdr->dest))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", + ntohs(udphdr->len), ntohs(udphdr->chksum))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* UDP_DEBUG */ + +#endif /* LWIP_UDP */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/autoip.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/autoip.h new file mode 100644 index 0000000..23c264a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/autoip.h @@ -0,0 +1,119 @@ +/** + * @file + * + * AutoIP Automatic LinkLocal IP Configuration + */ + +/* + * + * Copyright (c) 2007 Dominik Spies + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Dominik Spies + * + * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform + * with RFC 3927. + * + * + * Please coordinate changes and requests with Dominik Spies + * + */ + +#ifndef __LWIP_AUTOIP_H__ +#define __LWIP_AUTOIP_H__ + +#include "lwip/opt.h" + +#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +#include "lwip/udp.h" +#include "netif/etharp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* AutoIP Timing */ +#define AUTOIP_TMR_INTERVAL 100 +#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL) + +/* RFC 3927 Constants */ +#define PROBE_WAIT 1 /* second (initial random delay) */ +#define PROBE_MIN 1 /* second (minimum delay till repeated probe) */ +#define PROBE_MAX 2 /* seconds (maximum delay till repeated probe) */ +#define PROBE_NUM 3 /* (number of probe packets) */ +#define ANNOUNCE_NUM 2 /* (number of announcement packets) */ +#define ANNOUNCE_INTERVAL 2 /* seconds (time between announcement packets) */ +#define ANNOUNCE_WAIT 2 /* seconds (delay before announcing) */ +#define MAX_CONFLICTS 10 /* (max conflicts before rate limiting) */ +#define RATE_LIMIT_INTERVAL 60 /* seconds (delay between successive attempts) */ +#define DEFEND_INTERVAL 10 /* seconds (min. wait between defensive ARPs) */ + +/* AutoIP client states */ +#define AUTOIP_STATE_OFF 0 +#define AUTOIP_STATE_PROBING 1 +#define AUTOIP_STATE_ANNOUNCING 2 +#define AUTOIP_STATE_BOUND 3 + +struct autoip +{ + ip_addr_t llipaddr; /* the currently selected, probed, announced or used LL IP-Address */ + u8_t state; /* current AutoIP state machine state */ + u8_t sent_num; /* sent number of probes or announces, dependent on state */ + u16_t ttw; /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */ + u8_t lastconflict; /* ticks until a conflict can be solved by defending */ + u8_t tried_llipaddr; /* total number of probed/used Link Local IP-Addresses */ +}; + + +/** Init srand, has to be called before entering mainloop */ +void autoip_init(void); + +/** Set a struct autoip allocated by the application to work with */ +void autoip_set_struct(struct netif *netif, struct autoip *autoip); + +/** Start AutoIP client */ +err_t autoip_start(struct netif *netif); + +/** Stop AutoIP client */ +err_t autoip_stop(struct netif *netif); + +/** Handles every incoming ARP Packet, called by etharp_arp_input */ +void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr); + +/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */ +void autoip_tmr(void); + +/** Handle a possible change in the network configuration */ +void autoip_network_changed(struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_AUTOIP */ + +#endif /* __LWIP_AUTOIP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/icmp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/icmp.h new file mode 100644 index 0000000..d47a7d8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/icmp.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ICMP_H__ +#define __LWIP_ICMP_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ICMP_ER 0 /* echo reply */ +#define ICMP_DUR 3 /* destination unreachable */ +#define ICMP_SQ 4 /* source quench */ +#define ICMP_RD 5 /* redirect */ +#define ICMP_ECHO 8 /* echo */ +#define ICMP_TE 11 /* time exceeded */ +#define ICMP_PP 12 /* parameter problem */ +#define ICMP_TS 13 /* timestamp */ +#define ICMP_TSR 14 /* timestamp reply */ +#define ICMP_IRQ 15 /* information request */ +#define ICMP_IR 16 /* information reply */ + +enum icmp_dur_type { + ICMP_DUR_NET = 0, /* net unreachable */ + ICMP_DUR_HOST = 1, /* host unreachable */ + ICMP_DUR_PROTO = 2, /* protocol unreachable */ + ICMP_DUR_PORT = 3, /* port unreachable */ + ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ + ICMP_DUR_SR = 5 /* source route failed */ +}; + +enum icmp_te_type { + ICMP_TE_TTL = 0, /* time to live exceeded in transit */ + ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ +}; + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +/** This is the standard ICMP header only that the u32_t data + * is splitted to two u16_t like ICMP echo needs it. + * This header is also used for other ICMP types that do not + * use the data part. + */ +PACK_STRUCT_BEGIN +struct icmp_echo_hdr { + PACK_STRUCT_FIELD(u8_t type); + PACK_STRUCT_FIELD(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FIELD(u16_t seqno); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define ICMPH_TYPE(hdr) ((hdr)->type) +#define ICMPH_CODE(hdr) ((hdr)->code) + +/** Combines type and code to an u16_t */ +#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t)) +#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c)) + + +#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +void icmp_input(struct pbuf *p, struct netif *inp); +void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); +void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); + +#endif /* LWIP_ICMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ICMP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/igmp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/igmp.h new file mode 100644 index 0000000..8aabac2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/igmp.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2002 CITEL Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. +*/ + +#ifndef __LWIP_IGMP_H__ +#define __LWIP_IGMP_H__ + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/pbuf.h" + +#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* IGMP timer */ +#define IGMP_TMR_INTERVAL 100 /* Milliseconds */ +#define IGMP_V1_DELAYING_MEMBER_TMR (1000/IGMP_TMR_INTERVAL) +#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL) + +/* MAC Filter Actions, these are passed to a netif's + * igmp_mac_filter callback function. */ +#define IGMP_DEL_MAC_FILTER 0 +#define IGMP_ADD_MAC_FILTER 1 + + +/** + * igmp group structure - there is + * a list of groups for each interface + * these should really be linked from the interface, but + * if we keep them separate we will not affect the lwip original code + * too much + * + * There will be a group for the all systems group address but this + * will not run the state machine as it is used to kick off reports + * from all the other groups + */ +struct igmp_group { + /** next link */ + struct igmp_group *next; + /** interface on which the group is active */ + struct netif *netif; + /** multicast address */ + ip_addr_t group_address; + /** signifies we were the last person to report */ + u8_t last_reporter_flag; + /** current state of the group */ + u8_t group_state; + /** timer for reporting, negative is OFF */ + u16_t timer; + /** counter of simultaneous uses */ + u8_t use; +}; + +/* Prototypes */ +void igmp_init(void); +err_t igmp_start(struct netif *netif); +err_t igmp_stop(struct netif *netif); +void igmp_report_groups(struct netif *netif); +struct igmp_group *igmp_lookfor_group(struct netif *ifp, ip_addr_t *addr); +void igmp_input(struct pbuf *p, struct netif *inp, ip_addr_t *dest); +err_t igmp_joingroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr); +err_t igmp_leavegroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr); +void igmp_tmr(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IGMP */ + +#endif /* __LWIP_IGMP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet.h new file mode 100644 index 0000000..7bff49b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_H__ +#define __LWIP_INET_H__ + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** For compatibility with BSD code */ +struct in_addr { + u32_t s_addr; +}; + +/** 255.255.255.255 */ +#define INADDR_NONE IPADDR_NONE +/** 127.0.0.1 */ +#define INADDR_LOOPBACK IPADDR_LOOPBACK +/** 0.0.0.0 */ +#define INADDR_ANY IPADDR_ANY +/** 255.255.255.255 */ +#define INADDR_BROADCAST IPADDR_BROADCAST + +/* Definitions of the bits in an Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ +#define IN_CLASSA(a) IP_CLASSA(a) +#define IN_CLASSA_NET IP_CLASSA_NET +#define IN_CLASSA_NSHIFT IP_CLASSA_NSHIFT +#define IN_CLASSA_HOST IP_CLASSA_HOST +#define IN_CLASSA_MAX IP_CLASSA_MAX + +#define IN_CLASSB(b) IP_CLASSB(b) +#define IN_CLASSB_NET IP_CLASSB_NET +#define IN_CLASSB_NSHIFT IP_CLASSB_NSHIFT +#define IN_CLASSB_HOST IP_CLASSB_HOST +#define IN_CLASSB_MAX IP_CLASSB_MAX + +#define IN_CLASSC(c) IP_CLASSC(c) +#define IN_CLASSC_NET IP_CLASSC_NET +#define IN_CLASSC_NSHIFT IP_CLASSC_NSHIFT +#define IN_CLASSC_HOST IP_CLASSC_HOST +#define IN_CLASSC_MAX IP_CLASSC_MAX + +#define IN_CLASSD(d) IP_CLASSD(d) +#define IN_CLASSD_NET IP_CLASSD_NET /* These ones aren't really */ +#define IN_CLASSD_NSHIFT IP_CLASSD_NSHIFT /* net and host fields, but */ +#define IN_CLASSD_HOST IP_CLASSD_HOST /* routing needn't know. */ +#define IN_CLASSD_MAX IP_CLASSD_MAX + +#define IN_MULTICAST(a) IP_MULTICAST(a) + +#define IN_EXPERIMENTAL(a) IP_EXPERIMENTAL(a) +#define IN_BADCLASS(a) IP_BADCLASS(a) + +#define IN_LOOPBACKNET IP_LOOPBACKNET + +#define inet_addr_from_ipaddr(target_inaddr, source_ipaddr) ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr)) +#define inet_addr_to_ipaddr(target_ipaddr, source_inaddr) (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr)) +/* ATTENTION: the next define only works because both s_addr and ip_addr_t are an u32_t effectively! */ +#define inet_addr_to_ipaddr_p(target_ipaddr_p, source_inaddr) ((target_ipaddr_p) = (ip_addr_t*)&((source_inaddr)->s_addr)) + +/* directly map this to the lwip internal functions */ +#define inet_addr(cp) ipaddr_addr(cp) +#define inet_aton(cp, addr) ipaddr_aton(cp, (ip_addr_t*)addr) +#define inet_ntoa(addr) ipaddr_ntoa((ip_addr_t*)&(addr)) +#define inet_ntoa_r(addr, buf, buflen) ipaddr_ntoa_r((ip_addr_t*)&(addr), buf, buflen) + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet_chksum.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet_chksum.h new file mode 100644 index 0000000..79a2d90 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet_chksum.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_CHKSUM_H__ +#define __LWIP_INET_CHKSUM_H__ + +#include "lwip/opt.h" + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +/** Swap the bytes in an u16_t: much like htons() for little-endian */ +#ifndef SWAP_BYTES_IN_WORD +#if LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN) +/* little endian and PLATFORM_BYTESWAP defined */ +#define SWAP_BYTES_IN_WORD(w) LWIP_PLATFORM_HTONS(w) +#else /* LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN) */ +/* can't use htons on big endian (or PLATFORM_BYTESWAP not defined)... */ +#define SWAP_BYTES_IN_WORD(w) (((w) & 0xff) << 8) | (((w) & 0xff00) >> 8) +#endif /* LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN)*/ +#endif /* SWAP_BYTES_IN_WORD */ + +/** Split an u32_t in two u16_ts and add them up */ +#ifndef FOLD_U32T +#define FOLD_U32T(u) (((u) >> 16) + ((u) & 0x0000ffffUL)) +#endif + +#if LWIP_CHECKSUM_ON_COPY +/** Function-like macro: same as MEMCPY but returns the checksum of copied data + as u16_t */ +#ifndef LWIP_CHKSUM_COPY +#define LWIP_CHKSUM_COPY(dst, src, len) lwip_chksum_copy(dst, src, len) +#ifndef LWIP_CHKSUM_COPY_ALGORITHM +#define LWIP_CHKSUM_COPY_ALGORITHM 1 +#endif /* LWIP_CHKSUM_COPY_ALGORITHM */ +#endif /* LWIP_CHKSUM_COPY */ +#else /* LWIP_CHECKSUM_ON_COPY */ +#define LWIP_CHKSUM_COPY_ALGORITHM 0 +#endif /* LWIP_CHECKSUM_ON_COPY */ + +#ifdef __cplusplus +extern "C" { +#endif + +u16_t inet_chksum(void *dataptr, u16_t len); +u16_t inet_chksum_pbuf(struct pbuf *p); +u16_t inet_chksum_pseudo(struct pbuf *p, + ip_addr_t *src, ip_addr_t *dest, + u8_t proto, u16_t proto_len); +u16_t inet_chksum_pseudo_partial(struct pbuf *p, + ip_addr_t *src, ip_addr_t *dest, + u8_t proto, u16_t proto_len, u16_t chksum_len); +#if LWIP_CHKSUM_COPY_ALGORITHM +u16_t lwip_chksum_copy(void *dst, const void *src, u16_t len); +#endif /* LWIP_CHKSUM_COPY_ALGORITHM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip.h new file mode 100644 index 0000000..74f501d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_H__ +#define __LWIP_IP_H__ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Currently, the function ip_output_if_opt() is only used with IGMP */ +#define IP_OPTIONS_SEND LWIP_IGMP + +#define IP_HLEN 20 + +#define IP_PROTO_ICMP 1 +#define IP_PROTO_IGMP 2 +#define IP_PROTO_UDP 17 +#define IP_PROTO_UDPLITE 136 +#define IP_PROTO_TCP 6 + +/* This is passed as the destination address to ip_output_if (not + to ip_output), meaning that an IP header already is constructed + in the pbuf. This is used when TCP retransmits. */ +#ifdef IP_HDRINCL +#undef IP_HDRINCL +#endif /* IP_HDRINCL */ +#define IP_HDRINCL NULL + +#if LWIP_NETIF_HWADDRHINT +#define IP_PCB_ADDRHINT ;u8_t addr_hint +#else +#define IP_PCB_ADDRHINT +#endif /* LWIP_NETIF_HWADDRHINT */ + +/* This is the common part of all PCB types. It needs to be at the + beginning of a PCB type definition. It is located here so that + changes to this common part are made in one location instead of + having to change all PCB structs. */ +#define IP_PCB \ + /* ip addresses in network byte order */ \ + ip_addr_t local_ip; \ + ip_addr_t remote_ip; \ + /* Socket options */ \ + u8_t so_options; \ + /* Type Of Service */ \ + u8_t tos; \ + /* Time To Live */ \ + u8_t ttl \ + /* link layer address resolution hint */ \ + IP_PCB_ADDRHINT + +struct ip_pcb { +/* Common members of all PCB types */ + IP_PCB; +}; + +/* + * Option flags per-socket. These are the same like SO_XXX. + */ +/*#define SOF_DEBUG (u8_t)0x01U Unimplemented: turn on debugging info recording */ +#define SOF_ACCEPTCONN (u8_t)0x02U /* socket has had listen() */ +#define SOF_REUSEADDR (u8_t)0x04U /* allow local address reuse */ +#define SOF_KEEPALIVE (u8_t)0x08U /* keep connections alive */ +/*#define SOF_DONTROUTE (u8_t)0x10U Unimplemented: just use interface addresses */ +#define SOF_BROADCAST (u8_t)0x20U /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ +/*#define SOF_USELOOPBACK (u8_t)0x40U Unimplemented: bypass hardware when possible */ +#define SOF_LINGER (u8_t)0x80U /* linger on close if data present */ +/*#define SOF_OOBINLINE (u16_t)0x0100U Unimplemented: leave received OOB data in line */ +/*#define SOF_REUSEPORT (u16_t)0x0200U Unimplemented: allow local address & port reuse */ + +/* These flags are inherited (e.g. from a listen-pcb to a connection-pcb): */ +#define SOF_INHERITED (SOF_REUSEADDR|SOF_KEEPALIVE|SOF_LINGER/*|SOF_DEBUG|SOF_DONTROUTE|SOF_OOBINLINE*/) + + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_hdr { + /* version / header length / type of service */ + PACK_STRUCT_FIELD(u16_t _v_hl_tos); + /* total length */ + PACK_STRUCT_FIELD(u16_t _len); + /* identification */ + PACK_STRUCT_FIELD(u16_t _id); + /* fragment offset field */ + PACK_STRUCT_FIELD(u16_t _offset); +#define IP_RF 0x8000U /* reserved fragment flag */ +#define IP_DF 0x4000U /* dont fragment flag */ +#define IP_MF 0x2000U /* more fragments flag */ +#define IP_OFFMASK 0x1fffU /* mask for fragmenting bits */ + /* time to live */ + PACK_STRUCT_FIELD(u8_t _ttl); + /* protocol*/ + PACK_STRUCT_FIELD(u8_t _proto); + /* checksum */ + PACK_STRUCT_FIELD(u16_t _chksum); + /* source and destination IP addresses */ + PACK_STRUCT_FIELD(ip_addr_p_t src); + PACK_STRUCT_FIELD(ip_addr_p_t dest); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12) +#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f) +#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff) +#define IPH_LEN(hdr) ((hdr)->_len) +#define IPH_ID(hdr) ((hdr)->_id) +#define IPH_OFFSET(hdr) ((hdr)->_offset) +#define IPH_TTL(hdr) ((hdr)->_ttl) +#define IPH_PROTO(hdr) ((hdr)->_proto) +#define IPH_CHKSUM(hdr) ((hdr)->_chksum) + +#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos))) +#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) +#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) +#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) +#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl = (u8_t)(ttl) +#define IPH_PROTO_SET(hdr, proto) (hdr)->_proto = (u8_t)(proto) +#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) + +/** The interface that provided the packet for the current callback invocation. */ +extern struct netif *current_netif; +/** Header of the input packet currently being processed. */ +extern const struct ip_hdr *current_header; +/** Source IP address of current_header */ +extern ip_addr_t current_iphdr_src; +/** Destination IP address of current_header */ +extern ip_addr_t current_iphdr_dest; + +#define ip_init() /* Compatibility define, not init needed. */ +struct netif *ip_route(ip_addr_t *dest); +err_t ip_input(struct pbuf *p, struct netif *inp); +err_t ip_output(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto); +err_t ip_output_if(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, + struct netif *netif); +#if LWIP_NETIF_HWADDRHINT +err_t ip_output_hinted(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT */ +#if IP_OPTIONS_SEND +err_t ip_output_if_opt(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen); +#endif /* IP_OPTIONS_SEND */ +/** Get the interface that received the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip_current_netif() (current_netif) +/** Get the IP header of the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip_current_header() (current_header) +/** Source IP address of current_header */ +#define ip_current_src_addr() (¤t_iphdr_src) +/** Destination IP address of current_header */ +#define ip_current_dest_addr() (¤t_iphdr_dest) + +#if IP_DEBUG +void ip_debug_print(struct pbuf *p); +#else +#define ip_debug_print(p) +#endif /* IP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_H__ */ + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_addr.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_addr.h new file mode 100644 index 0000000..77f84e0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_addr.h @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_ADDR_H__ +#define __LWIP_IP_ADDR_H__ + +#include "lwip/opt.h" +#include "lwip/def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* This is the aligned version of ip_addr_t, + used as local variable, on the stack, etc. */ +struct ip_addr { + u32_t addr; +}; + +/* This is the packed version of ip_addr_t, + used in network headers that are itself packed */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr_packed { + PACK_STRUCT_FIELD(u32_t addr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** ip_addr_t uses a struct for convenience only, so that the same defines can + * operate both on ip_addr_t as well as on ip_addr_p_t. */ +typedef struct ip_addr ip_addr_t; +typedef struct ip_addr_packed ip_addr_p_t; + +/* + * struct ipaddr2 is used in the definition of the ARP packet format in + * order to support compilers that don't have structure packing. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr2 { + PACK_STRUCT_FIELD(u16_t addrw[2]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* Forward declaration to not include netif.h */ +struct netif; + +extern const ip_addr_t ip_addr_any; +extern const ip_addr_t ip_addr_broadcast; + +/** IP_ADDR_ can be used as a fixed IP address + * for the wildcard and the broadcast address + */ +#define IP_ADDR_ANY ((ip_addr_t *)&ip_addr_any) +#define IP_ADDR_BROADCAST ((ip_addr_t *)&ip_addr_broadcast) + +/** 255.255.255.255 */ +#define IPADDR_NONE ((u32_t)0xffffffffUL) +/** 127.0.0.1 */ +#define IPADDR_LOOPBACK ((u32_t)0x7f000001UL) +/** 0.0.0.0 */ +#define IPADDR_ANY ((u32_t)0x00000000UL) +/** 255.255.255.255 */ +#define IPADDR_BROADCAST ((u32_t)0xffffffffUL) + +/* Definitions of the bits in an Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ +#define IP_CLASSA(a) ((((u32_t)(a)) & 0x80000000UL) == 0) +#define IP_CLASSA_NET 0xff000000 +#define IP_CLASSA_NSHIFT 24 +#define IP_CLASSA_HOST (0xffffffff & ~IP_CLASSA_NET) +#define IP_CLASSA_MAX 128 + +#define IP_CLASSB(a) ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL) +#define IP_CLASSB_NET 0xffff0000 +#define IP_CLASSB_NSHIFT 16 +#define IP_CLASSB_HOST (0xffffffff & ~IP_CLASSB_NET) +#define IP_CLASSB_MAX 65536 + +#define IP_CLASSC(a) ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL) +#define IP_CLASSC_NET 0xffffff00 +#define IP_CLASSC_NSHIFT 8 +#define IP_CLASSC_HOST (0xffffffff & ~IP_CLASSC_NET) + +#define IP_CLASSD(a) (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL) +#define IP_CLASSD_NET 0xf0000000 /* These ones aren't really */ +#define IP_CLASSD_NSHIFT 28 /* net and host fields, but */ +#define IP_CLASSD_HOST 0x0fffffff /* routing needn't know. */ +#define IP_MULTICAST(a) IP_CLASSD(a) + +#define IP_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) +#define IP_BADCLASS(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) + +#define IP_LOOPBACKNET 127 /* official! */ + + +#if BYTE_ORDER == BIG_ENDIAN +/** Set an IP address given by the four byte-parts */ +#define IP4_ADDR(ipaddr, a,b,c,d) \ + (ipaddr)->addr = ((u32_t)((a) & 0xff) << 24) | \ + ((u32_t)((b) & 0xff) << 16) | \ + ((u32_t)((c) & 0xff) << 8) | \ + (u32_t)((d) & 0xff) +#else +/** Set an IP address given by the four byte-parts. + Little-endian version that prevents the use of htonl. */ +#define IP4_ADDR(ipaddr, a,b,c,d) \ + (ipaddr)->addr = ((u32_t)((d) & 0xff) << 24) | \ + ((u32_t)((c) & 0xff) << 16) | \ + ((u32_t)((b) & 0xff) << 8) | \ + (u32_t)((a) & 0xff) +#endif + +/** MEMCPY-like copying of IP addresses where addresses are known to be + * 16-bit-aligned if the port is correctly configured (so a port could define + * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */ +#ifndef IPADDR2_COPY +#define IPADDR2_COPY(dest, src) SMEMCPY(dest, src, sizeof(ip_addr_t)) +#endif + +/** Copy IP address - faster than ip_addr_set: no NULL check */ +#define ip_addr_copy(dest, src) ((dest).addr = (src).addr) +/** Safely copy one IP address to another (src may be NULL) */ +#define ip_addr_set(dest, src) ((dest)->addr = \ + ((src) == NULL ? 0 : \ + (src)->addr)) +/** Set complete address to zero */ +#define ip_addr_set_zero(ipaddr) ((ipaddr)->addr = 0) +/** Set address to IPADDR_ANY (no need for htonl()) */ +#define ip_addr_set_any(ipaddr) ((ipaddr)->addr = IPADDR_ANY) +/** Set address to loopback address */ +#define ip_addr_set_loopback(ipaddr) ((ipaddr)->addr = PP_HTONL(IPADDR_LOOPBACK)) +/** Safely copy one IP address to another and change byte order + * from host- to network-order. */ +#define ip_addr_set_hton(dest, src) ((dest)->addr = \ + ((src) == NULL ? 0:\ + htonl((src)->addr))) +/** IPv4 only: set the IP address given as an u32_t */ +#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32)) +/** IPv4 only: get the IP address as an u32_t */ +#define ip4_addr_get_u32(src_ipaddr) ((src_ipaddr)->addr) + +/** Get the network address by combining host address with netmask */ +#define ip_addr_get_network(target, host, netmask) ((target)->addr = ((host)->addr) & ((netmask)->addr)) + +/** + * Determine if two address are on the same network. + * + * @arg addr1 IP address 1 + * @arg addr2 IP address 2 + * @arg mask network identifier mask + * @return !0 if the network identifiers of both address match + */ +#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ + (mask)->addr) == \ + ((addr2)->addr & \ + (mask)->addr)) +#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) + +#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == IPADDR_ANY) + +#define ip_addr_isbroadcast(ipaddr, netif) ip4_addr_isbroadcast((ipaddr)->addr, (netif)) +u8_t ip4_addr_isbroadcast(u32_t addr, const struct netif *netif); + +#define ip_addr_netmask_valid(netmask) ip4_addr_netmask_valid((netmask)->addr) +u8_t ip4_addr_netmask_valid(u32_t netmask); + +#define ip_addr_ismulticast(addr1) (((addr1)->addr & PP_HTONL(0xf0000000UL)) == PP_HTONL(0xe0000000UL)) + +#define ip_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL)) + +#define ip_addr_debug_print(debug, ipaddr) \ + LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \ + ipaddr != NULL ? ip4_addr1_16(ipaddr) : 0, \ + ipaddr != NULL ? ip4_addr2_16(ipaddr) : 0, \ + ipaddr != NULL ? ip4_addr3_16(ipaddr) : 0, \ + ipaddr != NULL ? ip4_addr4_16(ipaddr) : 0)) + +/* Get one byte from the 4-byte address */ +#define ip4_addr1(ipaddr) (((u8_t*)(ipaddr))[0]) +#define ip4_addr2(ipaddr) (((u8_t*)(ipaddr))[1]) +#define ip4_addr3(ipaddr) (((u8_t*)(ipaddr))[2]) +#define ip4_addr4(ipaddr) (((u8_t*)(ipaddr))[3]) +/* These are cast to u16_t, with the intent that they are often arguments + * to printf using the U16_F format from cc.h. */ +#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr)) +#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr)) +#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr)) +#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr)) + +/** For backwards compatibility */ +#define ip_ntoa(ipaddr) ipaddr_ntoa(ipaddr) + +u32_t ipaddr_addr(const char *cp); +int ipaddr_aton(const char *cp, ip_addr_t *addr); +/** returns ptr to static buffer; not reentrant! */ +char *ipaddr_ntoa(const ip_addr_t *addr); +char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_frag.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_frag.h new file mode 100644 index 0000000..77b5eb1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_frag.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * + */ + +#ifndef __LWIP_IP_FRAG_H__ +#define __LWIP_IP_FRAG_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if IP_REASSEMBLY +/* The IP reassembly timer interval in milliseconds. */ +#define IP_TMR_INTERVAL 1000 + +/* IP reassembly helper struct. + * This is exported because memp needs to know the size. + */ +struct ip_reassdata { + struct ip_reassdata *next; + struct pbuf *p; + struct ip_hdr iphdr; + u16_t datagram_len; + u8_t flags; + u8_t timer; +}; + +void ip_reass_init(void); +void ip_reass_tmr(void); +struct pbuf * ip_reass(struct pbuf *p); +#endif /* IP_REASSEMBLY */ + +#if IP_FRAG +#if !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF +/** A custom pbuf that holds a reference to another pbuf, which is freed + * when this custom pbuf is freed. This is used to create a custom PBUF_REF + * that points into the original pbuf. */ +struct pbuf_custom_ref { + /** 'base class' */ + struct pbuf_custom pc; + /** pointer to the original pbuf that is referenced */ + struct pbuf *original; +}; +#endif /* !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF */ + +err_t ip_frag(struct pbuf *p, struct netif *netif, ip_addr_t *dest); +#endif /* IP_FRAG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_FRAG_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/icmp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/icmp.h new file mode 100644 index 0000000..87e9ffd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/icmp.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ICMP_H__ +#define __LWIP_ICMP_H__ + +#include "lwip/opt.h" + +#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ICMP6_DUR 1 +#define ICMP6_TE 3 +#define ICMP6_ECHO 128 /* echo */ +#define ICMP6_ER 129 /* echo reply */ + + +enum icmp_dur_type { + ICMP_DUR_NET = 0, /* net unreachable */ + ICMP_DUR_HOST = 1, /* host unreachable */ + ICMP_DUR_PROTO = 2, /* protocol unreachable */ + ICMP_DUR_PORT = 3, /* port unreachable */ + ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ + ICMP_DUR_SR = 5 /* source route failed */ +}; + +enum icmp_te_type { + ICMP_TE_TTL = 0, /* time to live exceeded in transit */ + ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ +}; + +void icmp_input(struct pbuf *p, struct netif *inp); + +void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); +void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); + +struct icmp_echo_hdr { + u8_t type; + u8_t icode; + u16_t chksum; + u16_t id; + u16_t seqno; +}; + +struct icmp_dur_hdr { + u8_t type; + u8_t icode; + u16_t chksum; + u32_t unused; +}; + +struct icmp_te_hdr { + u8_t type; + u8_t icode; + u16_t chksum; + u32_t unused; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_ICMP */ + +#endif /* __LWIP_ICMP_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/inet.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/inet.h new file mode 100644 index 0000000..de1a0b6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/inet.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_H__ +#define __LWIP_INET_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +u16_t inet_chksum(void *data, u16_t len); +u16_t inet_chksum_pbuf(struct pbuf *p); +u16_t inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u32_t proto_len); + +u32_t inet_addr(const char *cp); +s8_t inet_aton(const char *cp, struct in_addr *addr); + +#ifndef _MACHINE_ENDIAN_H_ +#ifndef _NETINET_IN_H +#ifndef _LINUX_BYTEORDER_GENERIC_H +u16_t htons(u16_t n); +u16_t ntohs(u16_t n); +u32_t htonl(u32_t n); +u32_t ntohl(u32_t n); +#endif /* _LINUX_BYTEORDER_GENERIC_H */ +#endif /* _NETINET_IN_H */ +#endif /* _MACHINE_ENDIAN_H_ */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip.h new file mode 100644 index 0000000..a01cfc6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_H__ +#define __LWIP_IP_H__ + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define IP_HLEN 40 + +#define IP_PROTO_ICMP 58 +#define IP_PROTO_UDP 17 +#define IP_PROTO_UDPLITE 136 +#define IP_PROTO_TCP 6 + +/* This is passed as the destination address to ip_output_if (not + to ip_output), meaning that an IP header already is constructed + in the pbuf. This is used when TCP retransmits. */ +#ifdef IP_HDRINCL +#undef IP_HDRINCL +#endif /* IP_HDRINCL */ +#define IP_HDRINCL NULL + +#if LWIP_NETIF_HWADDRHINT +#define IP_PCB_ADDRHINT ;u8_t addr_hint +#else +#define IP_PCB_ADDRHINT +#endif /* LWIP_NETIF_HWADDRHINT */ + +/* This is the common part of all PCB types. It needs to be at the + beginning of a PCB type definition. It is located here so that + changes to this common part are made in one location instead of + having to change all PCB structs. */ +#define IP_PCB struct ip_addr local_ip; \ + struct ip_addr remote_ip; \ + /* Socket options */ \ + u16_t so_options; \ + /* Type Of Service */ \ + u8_t tos; \ + /* Time To Live */ \ + u8_t ttl; \ + /* link layer address resolution hint */ \ + IP_PCB_ADDRHINT + + +/* The IPv6 header. */ +struct ip_hdr { +#if BYTE_ORDER == LITTLE_ENDIAN + u8_t tclass1:4, v:4; + u8_t flow1:4, tclass2:4; +#else + u8_t v:4, tclass1:4; + u8_t tclass2:8, flow1:4; +#endif + u16_t flow2; + u16_t len; /* payload length */ + u8_t nexthdr; /* next header */ + u8_t hoplim; /* hop limit (TTL) */ + struct ip_addr src, dest; /* source and destination IP addresses */ +}; + +#define IPH_PROTO(hdr) (iphdr->nexthdr) + +void ip_init(void); + +#include "lwip/netif.h" + +struct netif *ip_route(struct ip_addr *dest); + +void ip_input(struct pbuf *p, struct netif *inp); + +/* source and destination addresses in network byte order, please */ +err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t proto); + +err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t proto, + struct netif *netif); + +#define ip_current_netif() NULL +#define ip_current_header() NULL + +#if IP_DEBUG +void ip_debug_print(struct pbuf *p); +#endif /* IP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_H__ */ + + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip_addr.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip_addr.h new file mode 100644 index 0000000..b2d8ae5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip_addr.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_ADDR_H__ +#define __LWIP_IP_ADDR_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define IP_ADDR_ANY 0 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN + struct ip_addr { + PACK_STRUCT_FIELD(u32_t addr[4]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* + * struct ipaddr2 is used in the definition of the ARP packet format in + * order to support compilers that don't have structure packing. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr2 { + PACK_STRUCT_FIELD(u16_t addrw[2]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \ + (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \ + (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \ + (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0) + +u8_t ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2, + struct ip_addr *mask); +u8_t ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2); +void ip_addr_set(struct ip_addr *dest, struct ip_addr *src); +u8_t ip_addr_isany(struct ip_addr *addr); + +#define ip_addr_debug_print(debug, ipaddr) \ + LWIP_DEBUGF(debug, ("%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F"\n", \ + (ntohl(ipaddr->addr[0]) >> 16) & 0xffff, \ + ntohl(ipaddr->addr[0]) & 0xffff, \ + (ntohl(ipaddr->addr[1]) >> 16) & 0xffff, \ + ntohl(ipaddr->addr[1]) & 0xffff, \ + (ntohl(ipaddr->addr[2]) >> 16) & 0xffff, \ + ntohl(ipaddr->addr[2]) & 0xffff, \ + (ntohl(ipaddr->addr[3]) >> 16) & 0xffff, \ + ntohl(ipaddr->addr[3]) & 0xffff)); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/api.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/api.h new file mode 100644 index 0000000..91b9e5d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/api.h @@ -0,0 +1,284 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_H__ +#define __LWIP_API_H__ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include /* for size_t */ + +#include "lwip/netbuf.h" +#include "lwip/sys.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ + +/* Flags for netconn_write (u8_t) */ +#define NETCONN_NOFLAG 0x00 +#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */ +#define NETCONN_COPY 0x01 +#define NETCONN_MORE 0x02 +#define NETCONN_DONTBLOCK 0x04 + +/* Flags for struct netconn.flags (u8_t) */ +/** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores whether to wake up the original application task + if data couldn't be sent in the first try. */ +#define NETCONN_FLAG_WRITE_DELAYED 0x01 +/** Should this netconn avoid blocking? */ +#define NETCONN_FLAG_NON_BLOCKING 0x02 +/** Was the last connect action a non-blocking one? */ +#define NETCONN_FLAG_IN_NONBLOCKING_CONNECT 0x04 +/** If this is set, a TCP netconn must call netconn_recved() to update + the TCP receive window (done automatically if not set). */ +#define NETCONN_FLAG_NO_AUTO_RECVED 0x08 +/** If a nonblocking write has been rejected before, poll_tcp needs to + check if the netconn is writable again */ +#define NETCONN_FLAG_CHECK_WRITESPACE 0x10 + + +/* Helpers to process several netconn_types by the same code */ +#define NETCONNTYPE_GROUP(t) (t&0xF0) +#define NETCONNTYPE_DATAGRAM(t) (t&0xE0) + +/** Protocol family and type of the netconn */ +enum netconn_type { + NETCONN_INVALID = 0, + /* NETCONN_TCP Group */ + NETCONN_TCP = 0x10, + /* NETCONN_UDP Group */ + NETCONN_UDP = 0x20, + NETCONN_UDPLITE = 0x21, + NETCONN_UDPNOCHKSUM= 0x22, + /* NETCONN_RAW Group */ + NETCONN_RAW = 0x40 +}; + +/** Current state of the netconn. Non-TCP netconns are always + * in state NETCONN_NONE! */ +enum netconn_state { + NETCONN_NONE, + NETCONN_WRITE, + NETCONN_LISTEN, + NETCONN_CONNECT, + NETCONN_CLOSE +}; + +/** Use to inform the callback function about changes */ +enum netconn_evt { + NETCONN_EVT_RCVPLUS, + NETCONN_EVT_RCVMINUS, + NETCONN_EVT_SENDPLUS, + NETCONN_EVT_SENDMINUS, + NETCONN_EVT_ERROR +}; + +#if LWIP_IGMP +/** Used for netconn_join_leave_group() */ +enum netconn_igmp { + NETCONN_JOIN, + NETCONN_LEAVE +}; +#endif /* LWIP_IGMP */ + +/* forward-declare some structs to avoid to include their headers */ +struct ip_pcb; +struct tcp_pcb; +struct udp_pcb; +struct raw_pcb; +struct netconn; +struct api_msg_msg; + +/** A callback prototype to inform about events for a netconn */ +typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len); + +/** A netconn descriptor */ +struct netconn { + /** type of the netconn (TCP, UDP or RAW) */ + enum netconn_type type; + /** current state of the netconn */ + enum netconn_state state; + /** the lwIP internal protocol control block */ + union { + struct ip_pcb *ip; + struct tcp_pcb *tcp; + struct udp_pcb *udp; + struct raw_pcb *raw; + } pcb; + /** the last error this netconn had */ + err_t last_err; + /** sem that is used to synchroneously execute functions in the core context */ + sys_sem_t op_completed; + /** mbox where received packets are stored until they are fetched + by the netconn application thread (can grow quite big) */ + sys_mbox_t recvmbox; +#if LWIP_TCP + /** mbox where new connections are stored until processed + by the application thread */ + sys_mbox_t acceptmbox; +#endif /* LWIP_TCP */ + /** only used for socket layer */ +#if LWIP_SOCKET + int socket; +#endif /* LWIP_SOCKET */ +#if LWIP_SO_RCVTIMEO + /** timeout to wait for new data to be received + (or connections to arrive for listening netconns) */ + int recv_timeout; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + /** maximum amount of bytes queued in recvmbox + not used for TCP: adjust TCP_WND instead! */ + int recv_bufsize; + /** number of bytes currently in recvmbox to be received, + tested against recv_bufsize to limit bytes on recvmbox + for UDP and RAW, used for FIONREAD */ + s16_t recv_avail; +#endif /* LWIP_SO_RCVBUF */ + /** flags holding more netconn-internal state, see NETCONN_FLAG_* defines */ + u8_t flags; +#if LWIP_TCP + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores how much is already sent. */ + size_t write_offset; + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores the message. + Also used during connect and close. */ + struct api_msg_msg *current_msg; +#endif /* LWIP_TCP */ + /** A callback function that is informed about events for this netconn */ + netconn_callback callback; +}; + +/** Register an Network connection event */ +#define API_EVENT(c,e,l) if (c->callback) { \ + (*c->callback)(c, e, l); \ + } + +/** Set conn->last_err to err but don't overwrite fatal errors */ +#define NETCONN_SET_SAFE_ERR(conn, err) do { \ + SYS_ARCH_DECL_PROTECT(lev); \ + SYS_ARCH_PROTECT(lev); \ + if (!ERR_IS_FATAL((conn)->last_err)) { \ + (conn)->last_err = err; \ + } \ + SYS_ARCH_UNPROTECT(lev); \ +} while(0); + +/* Network connection functions: */ +#define netconn_new(t) netconn_new_with_proto_and_callback(t, 0, NULL) +#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c) +struct +netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, + netconn_callback callback); +err_t netconn_delete(struct netconn *conn); +/** Get the type of a netconn (as enum netconn_type). */ +#define netconn_type(conn) (conn->type) + +err_t netconn_getaddr(struct netconn *conn, ip_addr_t *addr, + u16_t *port, u8_t local); +#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0) +#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1) + +err_t netconn_bind(struct netconn *conn, ip_addr_t *addr, u16_t port); +err_t netconn_connect(struct netconn *conn, ip_addr_t *addr, u16_t port); +err_t netconn_disconnect (struct netconn *conn); +err_t netconn_listen_with_backlog(struct netconn *conn, u8_t backlog); +#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG) +err_t netconn_accept(struct netconn *conn, struct netconn **new_conn); +err_t netconn_recv(struct netconn *conn, struct netbuf **new_buf); +err_t netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf); +void netconn_recved(struct netconn *conn, u32_t length); +err_t netconn_sendto(struct netconn *conn, struct netbuf *buf, + ip_addr_t *addr, u16_t port); +err_t netconn_send(struct netconn *conn, struct netbuf *buf); +err_t netconn_write(struct netconn *conn, const void *dataptr, size_t size, + u8_t apiflags); +err_t netconn_close(struct netconn *conn); +err_t netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx); + +#if LWIP_IGMP +err_t netconn_join_leave_group(struct netconn *conn, ip_addr_t *multiaddr, + ip_addr_t *netif_addr, enum netconn_igmp join_or_leave); +#endif /* LWIP_IGMP */ +#if LWIP_DNS +err_t netconn_gethostbyname(const char *name, ip_addr_t *addr); +#endif /* LWIP_DNS */ + +#define netconn_err(conn) ((conn)->last_err) +#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize) + +/** Set the blocking status of netconn calls (@todo: write/send is missing) */ +#define netconn_set_nonblocking(conn, val) do { if(val) { \ + (conn)->flags |= NETCONN_FLAG_NON_BLOCKING; \ +} else { \ + (conn)->flags &= ~ NETCONN_FLAG_NON_BLOCKING; }} while(0) +/** Get the blocking status of netconn calls (@todo: write/send is missing) */ +#define netconn_is_nonblocking(conn) (((conn)->flags & NETCONN_FLAG_NON_BLOCKING) != 0) + +/** TCP: Set the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */ +#define netconn_set_noautorecved(conn, val) do { if(val) { \ + (conn)->flags |= NETCONN_FLAG_NO_AUTO_RECVED; \ +} else { \ + (conn)->flags &= ~ NETCONN_FLAG_NO_AUTO_RECVED; }} while(0) +/** TCP: Get the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */ +#define netconn_get_noautorecved(conn) (((conn)->flags & NETCONN_FLAG_NO_AUTO_RECVED) != 0) + +#if LWIP_SO_RCVTIMEO +/** Set the receive timeout in milliseconds */ +#define netconn_set_recvtimeout(conn, timeout) ((conn)->recv_timeout = (timeout)) +/** Get the receive timeout in milliseconds */ +#define netconn_get_recvtimeout(conn) ((conn)->recv_timeout) +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF +/** Set the receive buffer in bytes */ +#define netconn_set_recvbufsize(conn, recvbufsize) ((conn)->recv_bufsize = (recvbufsize)) +/** Get the receive buffer in bytes */ +#define netconn_get_recvbufsize(conn) ((conn)->recv_bufsize) +#endif /* LWIP_SO_RCVBUF*/ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN */ + +#endif /* __LWIP_API_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/api_msg.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/api_msg.h new file mode 100644 index 0000000..f99d8c3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/api_msg.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_MSG_H__ +#define __LWIP_API_MSG_H__ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include /* for size_t */ + +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/sys.h" +#include "lwip/igmp.h" +#include "lwip/api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* For the netconn API, these values are use as a bitmask! */ +#define NETCONN_SHUT_RD 1 +#define NETCONN_SHUT_WR 2 +#define NETCONN_SHUT_RDWR (NETCONN_SHUT_RD | NETCONN_SHUT_WR) + +/* IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ +/** This struct includes everything that is necessary to execute a function + for a netconn in another thread context (mainly used to process netconns + in the tcpip_thread context to be thread safe). */ +struct api_msg_msg { + /** The netconn which to process - always needed: it includes the semaphore + which is used to block the application thread until the function finished. */ + struct netconn *conn; + /** The return value of the function executed in tcpip_thread. */ + err_t err; + /** Depending on the executed function, one of these union members is used */ + union { + /** used for do_send */ + struct netbuf *b; + /** used for do_newconn */ + struct { + u8_t proto; + } n; + /** used for do_bind and do_connect */ + struct { + ip_addr_t *ipaddr; + u16_t port; + } bc; + /** used for do_getaddr */ + struct { + ip_addr_t *ipaddr; + u16_t *port; + u8_t local; + } ad; + /** used for do_write */ + struct { + const void *dataptr; + size_t len; + u8_t apiflags; + } w; + /** used for do_recv */ + struct { + u32_t len; + } r; + /** used for do_close (/shutdown) */ + struct { + u8_t shut; + } sd; +#if LWIP_IGMP + /** used for do_join_leave_group */ + struct { + ip_addr_t *multiaddr; + ip_addr_t *netif_addr; + enum netconn_igmp join_or_leave; + } jl; +#endif /* LWIP_IGMP */ +#if TCP_LISTEN_BACKLOG + struct { + u8_t backlog; + } lb; +#endif /* TCP_LISTEN_BACKLOG */ + } msg; +}; + +/** This struct contains a function to execute in another thread context and + a struct api_msg_msg that serves as an argument for this function. + This is passed to tcpip_apimsg to execute functions in tcpip_thread context. */ +struct api_msg { + /** function to execute in tcpip_thread context */ + void (* function)(struct api_msg_msg *msg); + /** arguments for this function */ + struct api_msg_msg msg; +}; + +#if LWIP_DNS +/** As do_gethostbyname requires more arguments but doesn't require a netconn, + it has its own struct (to avoid struct api_msg getting bigger than necessary). + do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg + (see netconn_gethostbyname). */ +struct dns_api_msg { + /** Hostname to query or dotted IP address string */ + const char *name; + /** Rhe resolved address is stored here */ + ip_addr_t *addr; + /** This semaphore is posted when the name is resolved, the application thread + should wait on it. */ + sys_sem_t *sem; + /** Errors are given back here */ + err_t *err; +}; +#endif /* LWIP_DNS */ + +void do_newconn ( struct api_msg_msg *msg); +void do_delconn ( struct api_msg_msg *msg); +void do_bind ( struct api_msg_msg *msg); +void do_connect ( struct api_msg_msg *msg); +void do_disconnect ( struct api_msg_msg *msg); +void do_listen ( struct api_msg_msg *msg); +void do_send ( struct api_msg_msg *msg); +void do_recv ( struct api_msg_msg *msg); +void do_write ( struct api_msg_msg *msg); +void do_getaddr ( struct api_msg_msg *msg); +void do_close ( struct api_msg_msg *msg); +void do_shutdown ( struct api_msg_msg *msg); +#if LWIP_IGMP +void do_join_leave_group( struct api_msg_msg *msg); +#endif /* LWIP_IGMP */ + +#if LWIP_DNS +void do_gethostbyname(void *arg); +#endif /* LWIP_DNS */ + +struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback); +void netconn_free(struct netconn *conn); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN */ + +#endif /* __LWIP_API_MSG_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/arch.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/arch.h new file mode 100644 index 0000000..524af6b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/arch.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ARCH_H__ +#define __LWIP_ARCH_H__ + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 1234 +#endif + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 4321 +#endif + +#include "arch/cc.h" + +/** Temporary: define format string for size_t if not defined in cc.h */ +#ifndef SZT_F +#define SZT_F U32_F +#endif /* SZT_F */ +/** Temporary upgrade helper: define format string for u8_t as hex if not + defined in cc.h */ +#ifndef X8_F +#define X8_F "02x" +#endif /* X8_F */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef PACK_STRUCT_BEGIN +#define PACK_STRUCT_BEGIN +#endif /* PACK_STRUCT_BEGIN */ + +#ifndef PACK_STRUCT_END +#define PACK_STRUCT_END +#endif /* PACK_STRUCT_END */ + +#ifndef PACK_STRUCT_FIELD +#define PACK_STRUCT_FIELD(x) x +#endif /* PACK_STRUCT_FIELD */ + + +#ifndef LWIP_UNUSED_ARG +#define LWIP_UNUSED_ARG(x) (void)x +#endif /* LWIP_UNUSED_ARG */ + + +#ifdef LWIP_PROVIDE_ERRNO + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + + +#define ENSROK 0 /* DNS server returned answer with no data */ +#define ENSRNODATA 160 /* DNS server returned answer with no data */ +#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ +#define ENSRSERVFAIL 162 /* DNS server returned general failure */ +#define ENSRNOTFOUND 163 /* Domain name not found */ +#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ +#define ENSRREFUSED 165 /* DNS server refused query */ +#define ENSRBADQUERY 166 /* Misformatted DNS query */ +#define ENSRBADNAME 167 /* Misformatted domain name */ +#define ENSRBADFAMILY 168 /* Unsupported address family */ +#define ENSRBADRESP 169 /* Misformatted DNS reply */ +#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ +#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ +#define ENSROF 172 /* End of file */ +#define ENSRFILE 173 /* Error reading file */ +#define ENSRNOMEM 174 /* Out of memory */ +#define ENSRDESTRUCTION 175 /* Application terminated lookup */ +#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ +#define ENSRCNAMELOOP 177 /* Domain name is too long */ + +#ifndef errno +extern int errno; +#endif + +#endif /* LWIP_PROVIDE_ERRNO */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ARCH_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/debug.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/debug.h new file mode 100644 index 0000000..1950a3e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/debug.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEBUG_H__ +#define __LWIP_DEBUG_H__ + +#include "lwip/arch.h" + +/** lower two bits indicate debug level + * - 0 all + * - 1 warning + * - 2 serious + * - 3 severe + */ +#define LWIP_DBG_LEVEL_ALL 0x00 +#define LWIP_DBG_LEVEL_OFF LWIP_DBG_LEVEL_ALL /* compatibility define only */ +#define LWIP_DBG_LEVEL_WARNING 0x01 /* bad checksums, dropped packets, ... */ +#define LWIP_DBG_LEVEL_SERIOUS 0x02 /* memory allocation failures, ... */ +#define LWIP_DBG_LEVEL_SEVERE 0x03 +#define LWIP_DBG_MASK_LEVEL 0x03 + +/** flag for LWIP_DEBUGF to enable that debug message */ +#define LWIP_DBG_ON 0x80U +/** flag for LWIP_DEBUGF to disable that debug message */ +#define LWIP_DBG_OFF 0x00U + +/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ +#define LWIP_DBG_TRACE 0x40U +/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ +#define LWIP_DBG_STATE 0x20U +/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ +#define LWIP_DBG_FRESH 0x10U +/** flag for LWIP_DEBUGF to halt after printing this debug message */ +#define LWIP_DBG_HALT 0x08U + +#ifndef LWIP_NOASSERT +#define LWIP_ASSERT(message, assertion) do { if(!(assertion)) \ + { LWIP_PLATFORM_ASSERT(message); } } while(0) +#else /* LWIP_NOASSERT */ +#define LWIP_ASSERT(message, assertion) +#endif /* LWIP_NOASSERT */ + +/** if "expression" isn't true, then print "message" and execute "handler" expression */ +#ifndef LWIP_ERROR +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + LWIP_PLATFORM_ASSERT(message); handler;}} while(0) +#endif /* LWIP_ERROR */ + +#ifdef LWIP_DEBUG +/** print debug message only if debug message type is enabled... + * AND is of correct type AND is at least LWIP_DBG_LEVEL + */ +#define LWIP_DEBUGF(debug, message) do { \ + if ( \ + ((debug) & LWIP_DBG_ON) && \ + ((debug) & LWIP_DBG_TYPES_ON) && \ + ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \ + LWIP_PLATFORM_DIAG(message); \ + if ((debug) & LWIP_DBG_HALT) { \ + while(1); \ + } \ + } \ + } while(0) + +#else /* LWIP_DEBUG */ +#define LWIP_DEBUGF(debug, message) +#endif /* LWIP_DEBUG */ + +#endif /* __LWIP_DEBUG_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/def.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/def.h new file mode 100644 index 0000000..9b6de6a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/def.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEF_H__ +#define __LWIP_DEF_H__ + +/* arch.h might define NULL already */ +#include "lwip/arch.h" +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LWIP_MAX(x , y) (((x) > (y)) ? (x) : (y)) +#define LWIP_MIN(x , y) (((x) < (y)) ? (x) : (y)) + +#ifndef NULL +#define NULL ((void *)0) +#endif + +/** Get the absolute difference between 2 u32_t values (correcting overflows) + * 'a' is expected to be 'higher' (without overflow) than 'b'. */ +#define LWIP_U32_DIFF(a, b) (((a) >= (b)) ? ((a) - (b)) : (((a) + ((b) ^ 0xFFFFFFFF) + 1))) + +/* Endianess-optimized shifting of two u8_t to create one u16_t */ +#if BYTE_ORDER == LITTLE_ENDIAN +#define LWIP_MAKE_U16(a, b) ((a << 8) | b) +#else +#define LWIP_MAKE_U16(a, b) ((b << 8) | a) +#endif + +#ifndef LWIP_PLATFORM_BYTESWAP +#define LWIP_PLATFORM_BYTESWAP 0 +#endif + +#ifndef LWIP_PREFIX_BYTEORDER_FUNCS +/* workaround for naming collisions on some platforms */ + +#ifdef htons +#undef htons +#endif /* htons */ +#ifdef htonl +#undef htonl +#endif /* htonl */ +#ifdef ntohs +#undef ntohs +#endif /* ntohs */ +#ifdef ntohl +#undef ntohl +#endif /* ntohl */ + +#define htons(x) lwip_htons(x) +#define ntohs(x) lwip_ntohs(x) +#define htonl(x) lwip_htonl(x) +#define ntohl(x) lwip_ntohl(x) +#endif /* LWIP_PREFIX_BYTEORDER_FUNCS */ + +#if BYTE_ORDER == BIG_ENDIAN +#define lwip_htons(x) (x) +#define lwip_ntohs(x) (x) +#define lwip_htonl(x) (x) +#define lwip_ntohl(x) (x) +#define PP_HTONS(x) (x) +#define PP_NTOHS(x) (x) +#define PP_HTONL(x) (x) +#define PP_NTOHL(x) (x) +#else /* BYTE_ORDER != BIG_ENDIAN */ +#if LWIP_PLATFORM_BYTESWAP +#define lwip_htons(x) LWIP_PLATFORM_HTONS(x) +#define lwip_ntohs(x) LWIP_PLATFORM_HTONS(x) +#define lwip_htonl(x) LWIP_PLATFORM_HTONL(x) +#define lwip_ntohl(x) LWIP_PLATFORM_HTONL(x) +#else /* LWIP_PLATFORM_BYTESWAP */ +u16_t lwip_htons(u16_t x); +u16_t lwip_ntohs(u16_t x); +u32_t lwip_htonl(u32_t x); +u32_t lwip_ntohl(u32_t x); +#endif /* LWIP_PLATFORM_BYTESWAP */ + +/* These macros should be calculated by the preprocessor and are used + with compile-time constants only (so that there is no little-endian + overhead at runtime). */ +#define PP_HTONS(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8)) +#define PP_NTOHS(x) PP_HTONS(x) +#define PP_HTONL(x) ((((x) & 0xff) << 24) | \ + (((x) & 0xff00) << 8) | \ + (((x) & 0xff0000UL) >> 8) | \ + (((x) & 0xff000000UL) >> 24)) +#define PP_NTOHL(x) PP_HTONL(x) + +#endif /* BYTE_ORDER == BIG_ENDIAN */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_DEF_H__ */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/dhcp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/dhcp.h new file mode 100644 index 0000000..32d9338 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/dhcp.h @@ -0,0 +1,242 @@ +/** @file + */ + +#ifndef __LWIP_DHCP_H__ +#define __LWIP_DHCP_H__ + +#include "lwip/opt.h" + +#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +#include "lwip/udp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** period (in seconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_SECS 60 +/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL) +/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ +#define DHCP_FINE_TIMER_MSECS 500 + +#define DHCP_CHADDR_LEN 16U +#define DHCP_SNAME_LEN 64U +#define DHCP_FILE_LEN 128U + +struct dhcp +{ + /** transaction identifier of last sent request */ + u32_t xid; + /** our connection to the DHCP server */ + struct udp_pcb *pcb; + /** incoming msg */ + struct dhcp_msg *msg_in; + /** current DHCP state machine state */ + u8_t state; + /** retries of current request */ + u8_t tries; +#if LWIP_DHCP_AUTOIP_COOP + u8_t autoip_coop_state; +#endif + u8_t subnet_mask_given; + + struct pbuf *p_out; /* pbuf of outcoming msg */ + struct dhcp_msg *msg_out; /* outgoing msg */ + u16_t options_out_len; /* outgoing msg options length */ + u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ + u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ + u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ + ip_addr_t server_ip_addr; /* dhcp server address that offered this lease */ + ip_addr_t offered_ip_addr; + ip_addr_t offered_sn_mask; + ip_addr_t offered_gw_addr; + + u32_t offered_t0_lease; /* lease period (in seconds) */ + u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ + u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */ + /* @todo: LWIP_DHCP_BOOTP_FILE configuration option? + integrate with possible TFTP-client for booting? */ +#if LWIP_DHCP_BOOTP_FILE + ip_addr_t offered_si_addr; + char boot_file_name[DHCP_FILE_LEN]; +#endif /* LWIP_DHCP_BOOTPFILE */ +}; + +/* MUST be compiled with "pack structs" or equivalent! */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** minimum set of fields of any DHCP message */ +struct dhcp_msg +{ + PACK_STRUCT_FIELD(u8_t op); + PACK_STRUCT_FIELD(u8_t htype); + PACK_STRUCT_FIELD(u8_t hlen); + PACK_STRUCT_FIELD(u8_t hops); + PACK_STRUCT_FIELD(u32_t xid); + PACK_STRUCT_FIELD(u16_t secs); + PACK_STRUCT_FIELD(u16_t flags); + PACK_STRUCT_FIELD(ip_addr_p_t ciaddr); + PACK_STRUCT_FIELD(ip_addr_p_t yiaddr); + PACK_STRUCT_FIELD(ip_addr_p_t siaddr); + PACK_STRUCT_FIELD(ip_addr_p_t giaddr); + PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]); + PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]); + PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]); + PACK_STRUCT_FIELD(u32_t cookie); +#define DHCP_MIN_OPTIONS_LEN 68U +/** make sure user does not configure this too small */ +#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) +# undef DHCP_OPTIONS_LEN +#endif +/** allow this to be configured in lwipopts.h, but not too small */ +#if (!defined(DHCP_OPTIONS_LEN)) +/** set this to be sufficient for your options in outgoing DHCP msgs */ +# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN +#endif + PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp); +/** Remove a struct dhcp previously set to the netif using dhcp_set_struct() */ +#define dhcp_remove_struct(netif) do { (netif)->dhcp = NULL; } while(0) +void dhcp_cleanup(struct netif *netif); +/** start DHCP configuration */ +err_t dhcp_start(struct netif *netif); +/** enforce early lease renewal (not needed normally)*/ +err_t dhcp_renew(struct netif *netif); +/** release the DHCP lease, usually called before dhcp_stop()*/ +err_t dhcp_release(struct netif *netif); +/** stop DHCP configuration */ +void dhcp_stop(struct netif *netif); +/** inform server of our manual IP address */ +void dhcp_inform(struct netif *netif); +/** Handle a possible change in the network configuration */ +void dhcp_network_changed(struct netif *netif); + +/** if enabled, check whether the offered IP address is not in use, using ARP */ +#if DHCP_DOES_ARP_CHECK +void dhcp_arp_reply(struct netif *netif, ip_addr_t *addr); +#endif + +/** to be called every minute */ +void dhcp_coarse_tmr(void); +/** to be called every half second */ +void dhcp_fine_tmr(void); + +/** DHCP message item offsets and length */ +#define DHCP_OP_OFS 0 +#define DHCP_HTYPE_OFS 1 +#define DHCP_HLEN_OFS 2 +#define DHCP_HOPS_OFS 3 +#define DHCP_XID_OFS 4 +#define DHCP_SECS_OFS 8 +#define DHCP_FLAGS_OFS 10 +#define DHCP_CIADDR_OFS 12 +#define DHCP_YIADDR_OFS 16 +#define DHCP_SIADDR_OFS 20 +#define DHCP_GIADDR_OFS 24 +#define DHCP_CHADDR_OFS 28 +#define DHCP_SNAME_OFS 44 +#define DHCP_FILE_OFS 108 +#define DHCP_MSG_LEN 236 + +#define DHCP_COOKIE_OFS DHCP_MSG_LEN +#define DHCP_OPTIONS_OFS (DHCP_MSG_LEN + 4) + +#define DHCP_CLIENT_PORT 68 +#define DHCP_SERVER_PORT 67 + +/** DHCP client states */ +#define DHCP_OFF 0 +#define DHCP_REQUESTING 1 +#define DHCP_INIT 2 +#define DHCP_REBOOTING 3 +#define DHCP_REBINDING 4 +#define DHCP_RENEWING 5 +#define DHCP_SELECTING 6 +#define DHCP_INFORMING 7 +#define DHCP_CHECKING 8 +#define DHCP_PERMANENT 9 +#define DHCP_BOUND 10 +/** not yet implemented #define DHCP_RELEASING 11 */ +#define DHCP_BACKING_OFF 12 + +/** AUTOIP cooperatation flags */ +#define DHCP_AUTOIP_COOP_STATE_OFF 0 +#define DHCP_AUTOIP_COOP_STATE_ON 1 + +#define DHCP_BOOTREQUEST 1 +#define DHCP_BOOTREPLY 2 + +/** DHCP message types */ +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 +#define DHCP_INFORM 8 + +/** DHCP hardware type, currently only ethernet is supported */ +#define DHCP_HTYPE_ETH 1 + +#define DHCP_MAGIC_COOKIE 0x63825363UL + +/* This is a list of options for BOOTP and DHCP, see RFC 2132 for descriptions */ + +/** BootP options */ +#define DHCP_OPTION_PAD 0 +#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ +#define DHCP_OPTION_ROUTER 3 +#define DHCP_OPTION_DNS_SERVER 6 +#define DHCP_OPTION_HOSTNAME 12 +#define DHCP_OPTION_IP_TTL 23 +#define DHCP_OPTION_MTU 26 +#define DHCP_OPTION_BROADCAST 28 +#define DHCP_OPTION_TCP_TTL 37 +#define DHCP_OPTION_END 255 + +/** DHCP options */ +#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ +#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ +#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ + +#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ +#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 + +#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ +#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ + +#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ +#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 + +#define DHCP_OPTION_T1 58 /* T1 renewal time */ +#define DHCP_OPTION_T2 59 /* T2 rebinding time */ +#define DHCP_OPTION_US 60 +#define DHCP_OPTION_CLIENT_ID 61 +#define DHCP_OPTION_TFTP_SERVERNAME 66 +#define DHCP_OPTION_BOOTFILE 67 + +/** possible combinations of overloading the file and sname fields with options */ +#define DHCP_OVERLOAD_NONE 0 +#define DHCP_OVERLOAD_FILE 1 +#define DHCP_OVERLOAD_SNAME 2 +#define DHCP_OVERLOAD_SNAME_FILE 3 + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DHCP */ + +#endif /*__LWIP_DHCP_H__*/ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/dns.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/dns.h new file mode 100644 index 0000000..6c7d9b0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/dns.h @@ -0,0 +1,124 @@ +/** + * lwip DNS resolver header file. + + * Author: Jim Pettinato + * April 2007 + + * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __LWIP_DNS_H__ +#define __LWIP_DNS_H__ + +#include "lwip/opt.h" + +#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** DNS timer period */ +#define DNS_TMR_INTERVAL 1000 + +/** DNS field TYPE used for "Resource Records" */ +#define DNS_RRTYPE_A 1 /* a host address */ +#define DNS_RRTYPE_NS 2 /* an authoritative name server */ +#define DNS_RRTYPE_MD 3 /* a mail destination (Obsolete - use MX) */ +#define DNS_RRTYPE_MF 4 /* a mail forwarder (Obsolete - use MX) */ +#define DNS_RRTYPE_CNAME 5 /* the canonical name for an alias */ +#define DNS_RRTYPE_SOA 6 /* marks the start of a zone of authority */ +#define DNS_RRTYPE_MB 7 /* a mailbox domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_MG 8 /* a mail group member (EXPERIMENTAL) */ +#define DNS_RRTYPE_MR 9 /* a mail rename domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_NULL 10 /* a null RR (EXPERIMENTAL) */ +#define DNS_RRTYPE_WKS 11 /* a well known service description */ +#define DNS_RRTYPE_PTR 12 /* a domain name pointer */ +#define DNS_RRTYPE_HINFO 13 /* host information */ +#define DNS_RRTYPE_MINFO 14 /* mailbox or mail list information */ +#define DNS_RRTYPE_MX 15 /* mail exchange */ +#define DNS_RRTYPE_TXT 16 /* text strings */ + +/** DNS field CLASS used for "Resource Records" */ +#define DNS_RRCLASS_IN 1 /* the Internet */ +#define DNS_RRCLASS_CS 2 /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */ +#define DNS_RRCLASS_CH 3 /* the CHAOS class */ +#define DNS_RRCLASS_HS 4 /* Hesiod [Dyer 87] */ +#define DNS_RRCLASS_FLUSH 0x800 /* Flush bit */ + +/* The size used for the next line is rather a hack, but it prevents including socket.h in all files + that include memp.h, and that would possibly break portability (since socket.h defines some types + and constants possibly already define by the OS). + Calculation rule: + sizeof(struct addrinfo) + sizeof(struct sockaddr_in) + DNS_MAX_NAME_LENGTH + 1 byte zero-termination */ +#define NETDB_ELEM_SIZE (32 + 16 + DNS_MAX_NAME_LENGTH + 1) + +#if DNS_LOCAL_HOSTLIST +/** struct used for local host-list */ +struct local_hostlist_entry { + /** static hostname */ + const char *name; + /** static host address in network byteorder */ + ip_addr_t addr; + struct local_hostlist_entry *next; +}; +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#ifndef DNS_LOCAL_HOSTLIST_MAX_NAMELEN +#define DNS_LOCAL_HOSTLIST_MAX_NAMELEN DNS_MAX_NAME_LENGTH +#endif +#define LOCALHOSTLIST_ELEM_SIZE ((sizeof(struct local_hostlist_entry) + DNS_LOCAL_HOSTLIST_MAX_NAMELEN + 1)) +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ +#endif /* DNS_LOCAL_HOSTLIST */ + +/** Callback which is invoked when a hostname is found. + * A function of this type must be implemented by the application using the DNS resolver. + * @param name pointer to the name that was looked up. + * @param ipaddr pointer to an ip_addr_t containing the IP address of the hostname, + * or NULL if the name could not be found (or on any other error). + * @param callback_arg a user-specified callback argument passed to dns_gethostbyname +*/ +typedef void (*dns_found_callback)(const char *name, ip_addr_t *ipaddr, void *callback_arg); + +void dns_init(void); +void dns_tmr(void); +void dns_setserver(u8_t numdns, ip_addr_t *dnsserver); +ip_addr_t dns_getserver(u8_t numdns); +err_t dns_gethostbyname(const char *hostname, ip_addr_t *addr, + dns_found_callback found, void *callback_arg); + +#if DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC +int dns_local_removehost(const char *hostname, const ip_addr_t *addr); +err_t dns_local_addhost(const char *hostname, const ip_addr_t *addr); +#endif /* DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DNS */ + +#endif /* __LWIP_DNS_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/err.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/err.h new file mode 100644 index 0000000..ac90772 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/err.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ERR_H__ +#define __LWIP_ERR_H__ + +#include "lwip/opt.h" +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Define LWIP_ERR_T in cc.h if you want to use + * a different type for your platform (must be signed). */ +#ifdef LWIP_ERR_T +typedef LWIP_ERR_T err_t; +#else /* LWIP_ERR_T */ +typedef s8_t err_t; +#endif /* LWIP_ERR_T*/ + +/* Definitions for error constants. */ + +#define ERR_OK 0 /* No error, everything OK. */ +#define ERR_MEM -1 /* Out of memory error. */ +#define ERR_BUF -2 /* Buffer error. */ +#define ERR_TIMEOUT -3 /* Timeout. */ +#define ERR_RTE -4 /* Routing problem. */ +#define ERR_INPROGRESS -5 /* Operation in progress */ +#define ERR_VAL -6 /* Illegal value. */ +#define ERR_WOULDBLOCK -7 /* Operation would block. */ +#define ERR_USE -8 /* Address in use. */ +#define ERR_ISCONN -9 /* Already connected. */ + +#define ERR_IS_FATAL(e) ((e) < ERR_ISCONN) + +#define ERR_ABRT -10 /* Connection aborted. */ +#define ERR_RST -11 /* Connection reset. */ +#define ERR_CLSD -12 /* Connection closed. */ +#define ERR_CONN -13 /* Not connected. */ + +#define ERR_ARG -14 /* Illegal argument. */ + +#define ERR_IF -15 /* Low-level netif error */ + + +#ifdef LWIP_DEBUG +extern const char *lwip_strerr(err_t err); +#else +#define lwip_strerr(x) "" +#endif /* LWIP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ERR_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/init.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/init.h new file mode 100644 index 0000000..77dcdfc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/init.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INIT_H__ +#define __LWIP_INIT_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** X.x.x: Major version of the stack */ +#define LWIP_VERSION_MAJOR 1U +/** x.X.x: Minor version of the stack */ +#define LWIP_VERSION_MINOR 4U +/** x.x.X: Revision of the stack */ +#define LWIP_VERSION_REVISION 0U +/** For release candidates, this is set to 1..254 + * For official releases, this is set to 255 (LWIP_RC_RELEASE) + * For development versions (CVS), this is set to 0 (LWIP_RC_DEVELOPMENT) */ +#define LWIP_VERSION_RC 255U + +/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */ +#define LWIP_RC_RELEASE 255U +/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for CVS versions */ +#define LWIP_RC_DEVELOPMENT 0U + +#define LWIP_VERSION_IS_RELEASE (LWIP_VERSION_RC == LWIP_RC_RELEASE) +#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT) +#define LWIP_VERSION_IS_RC ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT)) + +/** Provides the version of the stack */ +#define LWIP_VERSION (LWIP_VERSION_MAJOR << 24 | LWIP_VERSION_MINOR << 16 | \ + LWIP_VERSION_REVISION << 8 | LWIP_VERSION_RC) + +/* Modules initialization */ +void lwip_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INIT_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/mem.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/mem.h new file mode 100644 index 0000000..9507c0a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/mem.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_MEM_H__ +#define __LWIP_MEM_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if MEM_LIBC_MALLOC + +#include /* for size_t */ + +typedef size_t mem_size_t; + +/* aliases for C library malloc() */ +#define mem_init() +/* in case C library malloc() needs extra protection, + * allow these defines to be overridden. + */ +#ifndef mem_free +#define mem_free free +#endif +#ifndef mem_malloc +#define mem_malloc malloc +#endif +#ifndef mem_calloc +#define mem_calloc calloc +#endif +/* Since there is no C library allocation function to shrink memory without + moving it, define this to nothing. */ +#ifndef mem_trim +#define mem_trim(mem, size) (mem) +#endif +#else /* MEM_LIBC_MALLOC */ + +/* MEM_SIZE would have to be aligned, but using 64000 here instead of + * 65535 leaves some room for alignment... + */ +#if MEM_SIZE > 64000L +typedef u32_t mem_size_t; +#define MEM_SIZE_F U32_F +#else +typedef u16_t mem_size_t; +#define MEM_SIZE_F U16_F +#endif /* MEM_SIZE > 64000 */ + +#if MEM_USE_POOLS +/** mem_init is not used when using pools instead of a heap */ +#define mem_init() +/** mem_trim is not used when using pools instead of a heap: + we can't free part of a pool element and don't want to copy the rest */ +#define mem_trim(mem, size) (mem) +#else /* MEM_USE_POOLS */ +/* lwIP alternative malloc */ +void mem_init(void); +void *mem_trim(void *mem, mem_size_t size); +#endif /* MEM_USE_POOLS */ +void *mem_malloc(mem_size_t size); +void *mem_calloc(mem_size_t count, mem_size_t size); +void mem_free(void *mem); +#endif /* MEM_LIBC_MALLOC */ + +/** Calculate memory size for an aligned buffer - returns the next highest + * multiple of MEM_ALIGNMENT (e.g. LWIP_MEM_ALIGN_SIZE(3) and + * LWIP_MEM_ALIGN_SIZE(4) will both yield 4 for MEM_ALIGNMENT == 4). + */ +#ifndef LWIP_MEM_ALIGN_SIZE +#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1)) +#endif + +/** Calculate safe memory size for an aligned buffer when using an unaligned + * type as storage. This includes a safety-margin on (MEM_ALIGNMENT - 1) at the + * start (e.g. if buffer is u8_t[] and actual data will be u32_t*) + */ +#ifndef LWIP_MEM_ALIGN_BUFFER +#define LWIP_MEM_ALIGN_BUFFER(size) (((size) + MEM_ALIGNMENT - 1)) +#endif + +/** Align a memory pointer to the alignment defined by MEM_ALIGNMENT + * so that ADDR % MEM_ALIGNMENT == 0 + */ +#ifndef LWIP_MEM_ALIGN +#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_MEM_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/memp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/memp.h new file mode 100644 index 0000000..f0d0739 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/memp.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_MEMP_H__ +#define __LWIP_MEMP_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */ +typedef enum { +#define LWIP_MEMPOOL(name,num,size,desc) MEMP_##name, +#include "lwip/memp_std.h" + MEMP_MAX +} memp_t; + +#if MEM_USE_POOLS +/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */ +typedef enum { + /* Get the first (via: + MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/ + MEMP_POOL_HELPER_FIRST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START 1 +#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0 +#define LWIP_MALLOC_MEMPOOL_END +#include "lwip/memp_std.h" + ) , + /* Get the last (via: + MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */ + MEMP_POOL_HELPER_LAST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size * +#define LWIP_MALLOC_MEMPOOL_END 1 +#include "lwip/memp_std.h" + ) +} memp_pool_helper_t; + +/* The actual start and stop values are here (cast them over) + We use this helper type and these defines so we can avoid using const memp_t values */ +#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST) +#define MEMP_POOL_LAST ((memp_t) MEMP_POOL_HELPER_LAST) +#endif /* MEM_USE_POOLS */ + +#if MEMP_MEM_MALLOC || MEM_USE_POOLS +extern const u16_t memp_sizes[MEMP_MAX]; +#endif /* MEMP_MEM_MALLOC || MEM_USE_POOLS */ + +#if MEMP_MEM_MALLOC + +#include "mem.h" + +#define memp_init() +#define memp_malloc(type) mem_malloc(memp_sizes[type]) +#define memp_free(type, mem) mem_free(mem) + +#else /* MEMP_MEM_MALLOC */ + +#if MEM_USE_POOLS +/** This structure is used to save the pool one element came from. */ +struct memp_malloc_helper +{ + memp_t poolnr; +}; +#endif /* MEM_USE_POOLS */ + +void memp_init(void); + +#if MEMP_OVERFLOW_CHECK +void *memp_malloc_fn(memp_t type, const char* file, const int line); +#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__) +#else +void *memp_malloc(memp_t type); +#endif +void memp_free(memp_t type, void *mem); + +#endif /* MEMP_MEM_MALLOC */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_MEMP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/memp_std.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/memp_std.h new file mode 100644 index 0000000..6ce408f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/memp_std.h @@ -0,0 +1,122 @@ +/* + * SETUP: Make sure we define everything we will need. + * + * We have create three types of pools: + * 1) MEMPOOL - standard pools + * 2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c + * 3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct + * + * If the include'r doesn't require any special treatment of each of the types + * above, then will declare #2 & #3 to be just standard mempools. + */ +#ifndef LWIP_MALLOC_MEMPOOL +/* This treats "malloc pools" just like any other pool. + The pools are a little bigger to provide 'size' as the amount of user data. */ +#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + sizeof(struct memp_malloc_helper)), "MALLOC_"#size) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL_END +#endif /* LWIP_MALLOC_MEMPOOL */ + +#ifndef LWIP_PBUF_MEMPOOL +/* This treats "pbuf pools" just like any other pool. + * Allocates buffers for a pbuf struct AND a payload size */ +#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc) +#endif /* LWIP_PBUF_MEMPOOL */ + + +/* + * A list of internal pools used by LWIP. + * + * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + */ +#if LWIP_RAW +LWIP_MEMPOOL(RAW_PCB, MEMP_NUM_RAW_PCB, sizeof(struct raw_pcb), "RAW_PCB") +#endif /* LWIP_RAW */ + +#if LWIP_UDP +LWIP_MEMPOOL(UDP_PCB, MEMP_NUM_UDP_PCB, sizeof(struct udp_pcb), "UDP_PCB") +#endif /* LWIP_UDP */ + +#if LWIP_TCP +LWIP_MEMPOOL(TCP_PCB, MEMP_NUM_TCP_PCB, sizeof(struct tcp_pcb), "TCP_PCB") +LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN, sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN") +LWIP_MEMPOOL(TCP_SEG, MEMP_NUM_TCP_SEG, sizeof(struct tcp_seg), "TCP_SEG") +#endif /* LWIP_TCP */ + +#if IP_REASSEMBLY +LWIP_MEMPOOL(REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip_reassdata), "REASSDATA") +#endif /* IP_REASSEMBLY */ +#if IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF +LWIP_MEMPOOL(FRAG_PBUF, MEMP_NUM_FRAG_PBUF, sizeof(struct pbuf_custom_ref),"FRAG_PBUF") +#endif /* IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF */ + +#if LWIP_NETCONN +LWIP_MEMPOOL(NETBUF, MEMP_NUM_NETBUF, sizeof(struct netbuf), "NETBUF") +LWIP_MEMPOOL(NETCONN, MEMP_NUM_NETCONN, sizeof(struct netconn), "NETCONN") +#endif /* LWIP_NETCONN */ + +#if NO_SYS==0 +LWIP_MEMPOOL(TCPIP_MSG_API, MEMP_NUM_TCPIP_MSG_API, sizeof(struct tcpip_msg), "TCPIP_MSG_API") +#if !LWIP_TCPIP_CORE_LOCKING_INPUT +LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg), "TCPIP_MSG_INPKT") +#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */ +#endif /* NO_SYS==0 */ + +#if ARP_QUEUEING +LWIP_MEMPOOL(ARP_QUEUE, MEMP_NUM_ARP_QUEUE, sizeof(struct etharp_q_entry), "ARP_QUEUE") +#endif /* ARP_QUEUEING */ + +#if LWIP_IGMP +LWIP_MEMPOOL(IGMP_GROUP, MEMP_NUM_IGMP_GROUP, sizeof(struct igmp_group), "IGMP_GROUP") +#endif /* LWIP_IGMP */ + +#if (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS)) /* LWIP_TIMERS */ +LWIP_MEMPOOL(SYS_TIMEOUT, MEMP_NUM_SYS_TIMEOUT, sizeof(struct sys_timeo), "SYS_TIMEOUT") +#endif /* LWIP_TIMERS */ + +#if LWIP_SNMP +LWIP_MEMPOOL(SNMP_ROOTNODE, MEMP_NUM_SNMP_ROOTNODE, sizeof(struct mib_list_rootnode), "SNMP_ROOTNODE") +LWIP_MEMPOOL(SNMP_NODE, MEMP_NUM_SNMP_NODE, sizeof(struct mib_list_node), "SNMP_NODE") +LWIP_MEMPOOL(SNMP_VARBIND, MEMP_NUM_SNMP_VARBIND, sizeof(struct snmp_varbind), "SNMP_VARBIND") +LWIP_MEMPOOL(SNMP_VALUE, MEMP_NUM_SNMP_VALUE, SNMP_MAX_VALUE_SIZE, "SNMP_VALUE") +#endif /* LWIP_SNMP */ +#if LWIP_DNS && LWIP_SOCKET +LWIP_MEMPOOL(NETDB, MEMP_NUM_NETDB, NETDB_ELEM_SIZE, "NETDB") +#endif /* LWIP_DNS && LWIP_SOCKET */ +#if LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC +LWIP_MEMPOOL(LOCALHOSTLIST, MEMP_NUM_LOCALHOSTLIST, LOCALHOSTLIST_ELEM_SIZE, "LOCALHOSTLIST") +#endif /* LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ +#if PPP_SUPPORT && PPPOE_SUPPORT +LWIP_MEMPOOL(PPPOE_IF, MEMP_NUM_PPPOE_INTERFACES, sizeof(struct pppoe_softc), "PPPOE_IF") +#endif /* PPP_SUPPORT && PPPOE_SUPPORT */ + +/* + * A list of pools of pbuf's used by LWIP. + * + * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + * This allocates enough space for the pbuf struct and a payload. + * (Example: pbuf_payload_size=0 allocates only size for the struct) + */ +LWIP_PBUF_MEMPOOL(PBUF, MEMP_NUM_PBUF, 0, "PBUF_REF/ROM") +LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE, PBUF_POOL_BUFSIZE, "PBUF_POOL") + + +/* + * Allow for user-defined pools; this must be explicitly set in lwipopts.h + * since the default is to NOT look for lwippools.h + */ +#if MEMP_USE_CUSTOM_POOLS +#include "lwippools.h" +#endif /* MEMP_USE_CUSTOM_POOLS */ + +/* + * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later + * (#undef is ignored for something that is not defined) + */ +#undef LWIP_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL_START +#undef LWIP_MALLOC_MEMPOOL_END +#undef LWIP_PBUF_MEMPOOL diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netbuf.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netbuf.h new file mode 100644 index 0000000..7d247d7 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netbuf.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_NETBUF_H__ +#define __LWIP_NETBUF_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** This netbuf has dest-addr/port set */ +#define NETBUF_FLAG_DESTADDR 0x01 +/** This netbuf includes a checksum */ +#define NETBUF_FLAG_CHKSUM 0x02 + +struct netbuf { + struct pbuf *p, *ptr; + ip_addr_t addr; + u16_t port; +#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY +#if LWIP_CHECKSUM_ON_COPY + u8_t flags; +#endif /* LWIP_CHECKSUM_ON_COPY */ + u16_t toport_chksum; +#if LWIP_NETBUF_RECVINFO + ip_addr_t toaddr; +#endif /* LWIP_NETBUF_RECVINFO */ +#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */ +}; + +/* Network buffer functions: */ +struct netbuf * netbuf_new (void); +void netbuf_delete (struct netbuf *buf); +void * netbuf_alloc (struct netbuf *buf, u16_t size); +void netbuf_free (struct netbuf *buf); +err_t netbuf_ref (struct netbuf *buf, + const void *dataptr, u16_t size); +void netbuf_chain (struct netbuf *head, + struct netbuf *tail); + +err_t netbuf_data (struct netbuf *buf, + void **dataptr, u16_t *len); +s8_t netbuf_next (struct netbuf *buf); +void netbuf_first (struct netbuf *buf); + + +#define netbuf_copy_partial(buf, dataptr, len, offset) \ + pbuf_copy_partial((buf)->p, (dataptr), (len), (offset)) +#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0) +#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len) +#define netbuf_len(buf) ((buf)->p->tot_len) +#define netbuf_fromaddr(buf) (&((buf)->addr)) +#define netbuf_set_fromaddr(buf, fromaddr) ip_addr_set((&(buf)->addr), fromaddr) +#define netbuf_fromport(buf) ((buf)->port) +#if LWIP_NETBUF_RECVINFO +#define netbuf_destaddr(buf) (&((buf)->toaddr)) +#define netbuf_set_destaddr(buf, destaddr) ip_addr_set((&(buf)->addr), destaddr) +#define netbuf_destport(buf) (((buf)->flags & NETBUF_FLAG_DESTADDR) ? (buf)->toport_chksum : 0) +#endif /* LWIP_NETBUF_RECVINFO */ +#if LWIP_CHECKSUM_ON_COPY +#define netbuf_set_chksum(buf, chksum) do { (buf)->flags = NETBUF_FLAG_CHKSUM; \ + (buf)->toport_chksum = chksum; } while(0) +#endif /* LWIP_CHECKSUM_ON_COPY */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_NETBUF_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netdb.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netdb.h new file mode 100644 index 0000000..7587e2f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netdb.h @@ -0,0 +1,124 @@ +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef __LWIP_NETDB_H__ +#define __LWIP_NETDB_H__ + +#include "lwip/opt.h" + +#if LWIP_DNS && LWIP_SOCKET + +#include /* for size_t */ + +#include "lwip/inet.h" +#include "lwip/sockets.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* some rarely used options */ +#ifndef LWIP_DNS_API_DECLARE_H_ERRNO +#define LWIP_DNS_API_DECLARE_H_ERRNO 1 +#endif + +#ifndef LWIP_DNS_API_DEFINE_ERRORS +#define LWIP_DNS_API_DEFINE_ERRORS 1 +#endif + +#ifndef LWIP_DNS_API_DECLARE_STRUCTS +#define LWIP_DNS_API_DECLARE_STRUCTS 1 +#endif + +#if LWIP_DNS_API_DEFINE_ERRORS +/** Errors used by the DNS API functions, h_errno can be one of them */ +#define EAI_NONAME 200 +#define EAI_SERVICE 201 +#define EAI_FAIL 202 +#define EAI_MEMORY 203 + +#define HOST_NOT_FOUND 210 +#define NO_DATA 211 +#define NO_RECOVERY 212 +#define TRY_AGAIN 213 +#endif /* LWIP_DNS_API_DEFINE_ERRORS */ + +#if LWIP_DNS_API_DECLARE_STRUCTS +struct hostent { + char *h_name; /* Official name of the host. */ + char **h_aliases; /* A pointer to an array of pointers to alternative host names, + terminated by a null pointer. */ + int h_addrtype; /* Address type. */ + int h_length; /* The length, in bytes, of the address. */ + char **h_addr_list; /* A pointer to an array of pointers to network addresses (in + network byte order) for the host, terminated by a null pointer. */ +#define h_addr h_addr_list[0] /* for backward compatibility */ +}; + +struct addrinfo { + int ai_flags; /* Input flags. */ + int ai_family; /* Address family of socket. */ + int ai_socktype; /* Socket type. */ + int ai_protocol; /* Protocol of socket. */ + socklen_t ai_addrlen; /* Length of socket address. */ + struct sockaddr *ai_addr; /* Socket address of socket. */ + char *ai_canonname; /* Canonical name of service location. */ + struct addrinfo *ai_next; /* Pointer to next in list. */ +}; +#endif /* LWIP_DNS_API_DECLARE_STRUCTS */ + +#if LWIP_DNS_API_DECLARE_H_ERRNO +/* application accessable error code set by the DNS API functions */ +extern int h_errno; +#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/ + +struct hostent *lwip_gethostbyname(const char *name); +int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf, + size_t buflen, struct hostent **result, int *h_errnop); +void lwip_freeaddrinfo(struct addrinfo *ai); +int lwip_getaddrinfo(const char *nodename, + const char *servname, + const struct addrinfo *hints, + struct addrinfo **res); + +#if LWIP_COMPAT_SOCKETS +#define gethostbyname(name) lwip_gethostbyname(name) +#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \ + lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop) +#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo) +#define getaddrinfo(nodname, servname, hints, res) \ + lwip_getaddrinfo(nodname, servname, hints, res) +#endif /* LWIP_COMPAT_SOCKETS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DNS && LWIP_SOCKET */ + +#endif /* __LWIP_NETDB_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netif.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netif.h new file mode 100644 index 0000000..a8790b5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netif.h @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_NETIF_H__ +#define __LWIP_NETIF_H__ + +#include "lwip/opt.h" + +#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF) + +#include "lwip/err.h" + +#include "lwip/ip_addr.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#if LWIP_DHCP +struct dhcp; +#endif +#if LWIP_AUTOIP +struct autoip; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses are expected to be in + * the same byte order as in IP_PCB. */ + +/** must be the maximum of all used hardware address lengths + across all types of interfaces in use */ +#define NETIF_MAX_HWADDR_LEN 6U + +/** Whether the network interface is 'up'. This is + * a software flag used to control whether this network + * interface is enabled and processes traffic. + * It is set by the startup code (for static IP configuration) or + * by dhcp/autoip when an address has been assigned. + */ +#define NETIF_FLAG_UP 0x01U +/** If set, the netif has broadcast capability. + * Set by the netif driver in its init function. */ +#define NETIF_FLAG_BROADCAST 0x02U +/** If set, the netif is one end of a point-to-point connection. + * Set by the netif driver in its init function. */ +#define NETIF_FLAG_POINTTOPOINT 0x04U +/** If set, the interface is configured using DHCP. + * Set by the DHCP code when starting or stopping DHCP. */ +#define NETIF_FLAG_DHCP 0x08U +/** If set, the interface has an active link + * (set by the network interface driver). + * Either set by the netif driver in its init function (if the link + * is up at that time) or at a later point once the link comes up + * (if link detection is supported by the hardware). */ +#define NETIF_FLAG_LINK_UP 0x10U +/** If set, the netif is an ethernet device using ARP. + * Set by the netif driver in its init function. + * Used to check input packet types and use of DHCP. */ +#define NETIF_FLAG_ETHARP 0x20U +/** If set, the netif is an ethernet device. It might not use + * ARP or TCP/IP if it is used for PPPoE only. + */ +#define NETIF_FLAG_ETHERNET 0x40U +/** If set, the netif has IGMP capability. + * Set by the netif driver in its init function. */ +#define NETIF_FLAG_IGMP 0x80U + +/** Function prototype for netif init functions. Set up flags and output/linkoutput + * callback functions in this function. + * + * @param netif The netif to initialize + */ +typedef err_t (*netif_init_fn)(struct netif *netif); +/** Function prototype for netif->input functions. This function is saved as 'input' + * callback function in the netif struct. Call it when a packet has been received. + * + * @param p The received packet, copied into a pbuf + * @param inp The netif which received the packet + */ +typedef err_t (*netif_input_fn)(struct pbuf *p, struct netif *inp); +/** Function prototype for netif->output functions. Called by lwIP when a packet + * shall be sent. For ethernet netif, set this to 'etharp_output' and set + * 'linkoutput'. + * + * @param netif The netif which shall send a packet + * @param p The packet to send (p->payload points to IP header) + * @param ipaddr The IP address to which the packet shall be sent + */ +typedef err_t (*netif_output_fn)(struct netif *netif, struct pbuf *p, + ip_addr_t *ipaddr); +/** Function prototype for netif->linkoutput functions. Only used for ethernet + * netifs. This function is called by ARP when a packet shall be sent. + * + * @param netif The netif which shall send a packet + * @param p The packet to send (raw ethernet packet) + */ +typedef err_t (*netif_linkoutput_fn)(struct netif *netif, struct pbuf *p); +/** Function prototype for netif status- or link-callback functions. */ +typedef void (*netif_status_callback_fn)(struct netif *netif); +/** Function prototype for netif igmp_mac_filter functions */ +typedef err_t (*netif_igmp_mac_filter_fn)(struct netif *netif, + ip_addr_t *group, u8_t action); + +/** Generic data structure used for all lwIP network interfaces. + * The following fields should be filled in by the initialization + * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ +struct netif { + /** pointer to next in linked list */ + struct netif *next; + + /** IP address configuration in network byte order */ + ip_addr_t ip_addr; + ip_addr_t netmask; + ip_addr_t gw; + + /** This function is called by the network device driver + * to pass a packet up the TCP/IP stack. */ + netif_input_fn input; + /** This function is called by the IP module when it wants + * to send a packet on the interface. This function typically + * first resolves the hardware address, then sends the packet. */ + netif_output_fn output; + /** This function is called by the ARP module when it wants + * to send a packet on the interface. This function outputs + * the pbuf as-is on the link medium. */ + netif_linkoutput_fn linkoutput; +#if LWIP_NETIF_STATUS_CALLBACK + /** This function is called when the netif state is set to up or down + */ + netif_status_callback_fn status_callback; +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK + /** This function is called when the netif link is set to up or down + */ + netif_status_callback_fn link_callback; +#endif /* LWIP_NETIF_LINK_CALLBACK */ + /** This field can be set by the device driver and could point + * to state information for the device. */ + void *state; +#if LWIP_DHCP + /** the DHCP client state information for this netif */ + struct dhcp *dhcp; +#endif /* LWIP_DHCP */ +#if LWIP_AUTOIP + /** the AutoIP client state information for this netif */ + struct autoip *autoip; +#endif +#if LWIP_NETIF_HOSTNAME + /* the hostname for this netif, NULL is a valid value */ + char* hostname; +#endif /* LWIP_NETIF_HOSTNAME */ + /** maximum transfer unit (in bytes) */ + u16_t mtu; + /** number of bytes used in hwaddr */ + u8_t hwaddr_len; + /** link level hardware address of this interface */ + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + /** flags (see NETIF_FLAG_ above) */ + u8_t flags; + /** descriptive abbreviation */ + char name[2]; + /** number of this interface */ + u8_t num; +#if LWIP_SNMP + /** link type (from "snmp_ifType" enum from snmp.h) */ + u8_t link_type; + /** (estimate) link speed */ + u32_t link_speed; + /** timestamp at last change made (up/down) */ + u32_t ts; + /** counters */ + u32_t ifinoctets; + u32_t ifinucastpkts; + u32_t ifinnucastpkts; + u32_t ifindiscards; + u32_t ifoutoctets; + u32_t ifoutucastpkts; + u32_t ifoutnucastpkts; + u32_t ifoutdiscards; +#endif /* LWIP_SNMP */ +#if LWIP_IGMP + /** This function could be called to add or delete a entry in the multicast + filter table of the ethernet MAC.*/ + netif_igmp_mac_filter_fn igmp_mac_filter; +#endif /* LWIP_IGMP */ +#if LWIP_NETIF_HWADDRHINT + u8_t *addr_hint; +#endif /* LWIP_NETIF_HWADDRHINT */ +#if ENABLE_LOOPBACK + /* List of packets to be queued for ourselves. */ + struct pbuf *loop_first; + struct pbuf *loop_last; +#if LWIP_LOOPBACK_MAX_PBUFS + u16_t loop_cnt_current; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ +#endif /* ENABLE_LOOPBACK */ +}; + +#if LWIP_SNMP +#define NETIF_INIT_SNMP(netif, type, speed) \ + /* use "snmp_ifType" enum from snmp.h for "type", snmp_ifType_ethernet_csmacd by example */ \ + (netif)->link_type = (type); \ + /* your link speed here (units: bits per second) */ \ + (netif)->link_speed = (speed); \ + (netif)->ts = 0; \ + (netif)->ifinoctets = 0; \ + (netif)->ifinucastpkts = 0; \ + (netif)->ifinnucastpkts = 0; \ + (netif)->ifindiscards = 0; \ + (netif)->ifoutoctets = 0; \ + (netif)->ifoutucastpkts = 0; \ + (netif)->ifoutnucastpkts = 0; \ + (netif)->ifoutdiscards = 0 +#else /* LWIP_SNMP */ +#define NETIF_INIT_SNMP(netif, type, speed) +#endif /* LWIP_SNMP */ + + +/** The list of network interfaces. */ +extern struct netif *netif_list; +/** The default network interface. */ +extern struct netif *netif_default; + +void netif_init(void); + +struct netif *netif_add(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask, + ip_addr_t *gw, void *state, netif_init_fn init, netif_input_fn input); + +void +netif_set_addr(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask, + ip_addr_t *gw); +void netif_remove(struct netif * netif); + +/* Returns a network interface given its name. The name is of the form + "et0", where the first two letters are the "name" field in the + netif structure, and the digit is in the num field in the same + structure. */ +struct netif *netif_find(char *name); + +void netif_set_default(struct netif *netif); + +void netif_set_ipaddr(struct netif *netif, ip_addr_t *ipaddr); +void netif_set_netmask(struct netif *netif, ip_addr_t *netmask); +void netif_set_gw(struct netif *netif, ip_addr_t *gw); + +void netif_set_up(struct netif *netif); +void netif_set_down(struct netif *netif); +/** Ask if an interface is up */ +#define netif_is_up(netif) (((netif)->flags & NETIF_FLAG_UP) ? (u8_t)1 : (u8_t)0) + +#if LWIP_NETIF_STATUS_CALLBACK +void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback); +#endif /* LWIP_NETIF_STATUS_CALLBACK */ + +void netif_set_link_up(struct netif *netif); +void netif_set_link_down(struct netif *netif); +/** Ask if a link is up */ +#define netif_is_link_up(netif) (((netif)->flags & NETIF_FLAG_LINK_UP) ? (u8_t)1 : (u8_t)0) + +#if LWIP_NETIF_LINK_CALLBACK +void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback); +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#if LWIP_NETIF_HOSTNAME +#define netif_set_hostname(netif, name) do { if((netif) != NULL) { (netif)->hostname = name; }}while(0) +#define netif_get_hostname(netif) (((netif) != NULL) ? ((netif)->hostname) : NULL) +#endif /* LWIP_NETIF_HOSTNAME */ + +#if LWIP_IGMP +#define netif_set_igmp_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->igmp_mac_filter = function; }}while(0) +#define netif_get_igmp_mac_filter(netif) (((netif) != NULL) ? ((netif)->igmp_mac_filter) : NULL) +#endif /* LWIP_IGMP */ + +#if ENABLE_LOOPBACK +err_t netif_loop_output(struct netif *netif, struct pbuf *p, ip_addr_t *dest_ip); +void netif_poll(struct netif *netif); +#if !LWIP_NETIF_LOOPBACK_MULTITHREADING +void netif_poll_all(void); +#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ +#endif /* ENABLE_LOOPBACK */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_NETIF_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netifapi.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netifapi.h new file mode 100644 index 0000000..33318ef --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/netifapi.h @@ -0,0 +1,108 @@ +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#ifndef __LWIP_NETIFAPI_H__ +#define __LWIP_NETIFAPI_H__ + +#include "lwip/opt.h" + +#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/netif.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*netifapi_void_fn)(struct netif *netif); +typedef err_t (*netifapi_errt_fn)(struct netif *netif); + +struct netifapi_msg_msg { +#if !LWIP_TCPIP_CORE_LOCKING + sys_sem_t sem; +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + err_t err; + struct netif *netif; + union { + struct { + ip_addr_t *ipaddr; + ip_addr_t *netmask; + ip_addr_t *gw; + void *state; + netif_init_fn init; + netif_input_fn input; + } add; + struct { + netifapi_void_fn voidfunc; + netifapi_errt_fn errtfunc; + } common; + } msg; +}; + +struct netifapi_msg { + void (* function)(struct netifapi_msg_msg *msg); + struct netifapi_msg_msg msg; +}; + + +/* API for application */ +err_t netifapi_netif_add ( struct netif *netif, + ip_addr_t *ipaddr, + ip_addr_t *netmask, + ip_addr_t *gw, + void *state, + netif_init_fn init, + netif_input_fn input); + +err_t netifapi_netif_set_addr ( struct netif *netif, + ip_addr_t *ipaddr, + ip_addr_t *netmask, + ip_addr_t *gw ); + +err_t netifapi_netif_common ( struct netif *netif, + netifapi_void_fn voidfunc, + netifapi_errt_fn errtfunc); + +#define netifapi_netif_remove(n) netifapi_netif_common(n, netif_remove, NULL) +#define netifapi_netif_set_up(n) netifapi_netif_common(n, netif_set_up, NULL) +#define netifapi_netif_set_down(n) netifapi_netif_common(n, netif_set_down, NULL) +#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL) +#define netifapi_dhcp_start(n) netifapi_netif_common(n, NULL, dhcp_start) +#define netifapi_dhcp_stop(n) netifapi_netif_common(n, dhcp_stop, NULL) +#define netifapi_autoip_start(n) netifapi_netif_common(n, NULL, autoip_start) +#define netifapi_autoip_stop(n) netifapi_netif_common(n, NULL, autoip_stop) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETIF_API */ + +#endif /* __LWIP_NETIFAPI_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/opt.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/opt.h new file mode 100644 index 0000000..a1b8765 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/opt.h @@ -0,0 +1,2043 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_OPT_H__ +#define __LWIP_OPT_H__ + +/* + * Include user defined options first. Anything not defined in these files + * will be set to standard values. Override anything you dont like! + */ +#include "lwipopts.h" +#include "lwip/debug.h" + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 1 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT 3 +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 536 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF 256 +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT ((TCP_SND_BUF)/2) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be grater + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT ((TCP_SND_QUEUELEN)/2) +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. + */ +#ifndef LWIP_EVENT_API +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#else +#define LWIP_EVENT_API 1 +#define LWIP_CALLBACK_API 0 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 0 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO 1 +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE 0 +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 0 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO 1 +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 0 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 0 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 0 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIP_OPT_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/pbuf.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/pbuf.h new file mode 100644 index 0000000..3b1d608 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/pbuf.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_PBUF_H__ +#define __LWIP_PBUF_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Currently, the pbuf_custom code is only needed for one specific configuration + * of IP_FRAG */ +#define LWIP_SUPPORT_CUSTOM_PBUF (IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF) + +#define PBUF_TRANSPORT_HLEN 20 +#define PBUF_IP_HLEN 20 + +typedef enum { + PBUF_TRANSPORT, + PBUF_IP, + PBUF_LINK, + PBUF_RAW +} pbuf_layer; + +typedef enum { + PBUF_RAM, /* pbuf data is stored in RAM */ + PBUF_ROM, /* pbuf data is stored in ROM */ + PBUF_REF, /* pbuf comes from the pbuf pool */ + PBUF_POOL /* pbuf payload refers to RAM */ +} pbuf_type; + + +/** indicates this packet's data should be immediately passed to the application */ +#define PBUF_FLAG_PUSH 0x01U +/** indicates this is a custom pbuf: pbuf_free and pbuf_header handle such a + a pbuf differently */ +#define PBUF_FLAG_IS_CUSTOM 0x02U +/** indicates this pbuf is UDP multicast to be looped back */ +#define PBUF_FLAG_MCASTLOOP 0x04U + +struct pbuf { + /** next pbuf in singly linked pbuf chain */ + struct pbuf *next; + + /** pointer to the actual data in the buffer */ + void *payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + u16_t tot_len; + + /** length of this buffer */ + u16_t len; + + /** pbuf_type as u8_t instead of enum to save space */ + u8_t /*pbuf_type*/ type; + + /** misc flags */ + u8_t flags; + + /** + * the reference count always equals the number of pointers + * that refer to this pbuf. This can be pointers from an application, + * the stack itself, or pbuf->next pointers from a chain. + */ + u16_t ref; +}; + +#if LWIP_SUPPORT_CUSTOM_PBUF +/** Prototype for a function to free a custom pbuf */ +typedef void (*pbuf_free_custom_fn)(struct pbuf *p); + +/** A custom pbuf: like a pbuf, but following a function pointer to free it. */ +struct pbuf_custom { + /** The actual pbuf */ + struct pbuf pbuf; + /** This function is called when pbuf_free deallocates this pbuf(_custom) */ + pbuf_free_custom_fn custom_free_function; +}; +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + +/* Initializes the pbuf module. This call is empty for now, but may not be in future. */ +#define pbuf_init() + +struct pbuf *pbuf_alloc(pbuf_layer l, u16_t length, pbuf_type type); +#if LWIP_SUPPORT_CUSTOM_PBUF +struct pbuf *pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, + struct pbuf_custom *p, void *payload_mem, + u16_t payload_mem_len); +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ +void pbuf_realloc(struct pbuf *p, u16_t size); +u8_t pbuf_header(struct pbuf *p, s16_t header_size); +void pbuf_ref(struct pbuf *p); +u8_t pbuf_free(struct pbuf *p); +u8_t pbuf_clen(struct pbuf *p); +void pbuf_cat(struct pbuf *head, struct pbuf *tail); +void pbuf_chain(struct pbuf *head, struct pbuf *tail); +struct pbuf *pbuf_dechain(struct pbuf *p); +err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from); +u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset); +err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len); +struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer); +#if LWIP_CHECKSUM_ON_COPY +err_t pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr, + u16_t len, u16_t *chksum); +#endif /* LWIP_CHECKSUM_ON_COPY */ + +u8_t pbuf_get_at(struct pbuf* p, u16_t offset); +u16_t pbuf_memcmp(struct pbuf* p, u16_t offset, const void* s2, u16_t n); +u16_t pbuf_memfind(struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset); +u16_t pbuf_strstr(struct pbuf* p, const char* substr); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_PBUF_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/raw.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/raw.h new file mode 100644 index 0000000..17d0a1c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/raw.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_RAW_H__ +#define __LWIP_RAW_H__ + +#include "lwip/opt.h" + +#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/def.h" +#include "lwip/ip.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct raw_pcb; + +/** Function prototype for raw pcb receive callback functions. + * @param arg user supplied argument (raw_pcb.recv_arg) + * @param pcb the raw_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @return 1 if the packet was 'eaten' (aka. deleted), + * 0 if the packet lives on + * If returning 1, the callback is responsible for freeing the pbuf + * if it's not used any more. + */ +typedef u8_t (*raw_recv_fn)(void *arg, struct raw_pcb *pcb, struct pbuf *p, + ip_addr_t *addr); + +struct raw_pcb { + /* Common members of all PCB types */ + IP_PCB; + + struct raw_pcb *next; + + u8_t protocol; + + /** receive callback function */ + raw_recv_fn recv; + /* user-supplied argument for the recv callback */ + void *recv_arg; +}; + +/* The following functions is the application layer interface to the + RAW code. */ +struct raw_pcb * raw_new (u8_t proto); +void raw_remove (struct raw_pcb *pcb); +err_t raw_bind (struct raw_pcb *pcb, ip_addr_t *ipaddr); +err_t raw_connect (struct raw_pcb *pcb, ip_addr_t *ipaddr); + +void raw_recv (struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg); +err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, ip_addr_t *ipaddr); +err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); + +/* The following functions are the lower layer interface to RAW. */ +u8_t raw_input (struct pbuf *p, struct netif *inp); +#define raw_init() /* Compatibility define, not init needed. */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_RAW */ + +#endif /* __LWIP_RAW_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/sio.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/sio.h new file mode 100644 index 0000000..28ae2f2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/sio.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + */ + +/* + * This is the interface to the platform specific serial IO module + * It needs to be implemented by those platforms which need SLIP or PPP + */ + +#ifndef __SIO_H__ +#define __SIO_H__ + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* If you want to define sio_fd_t elsewhere or differently, + define this in your cc.h file. */ +#ifndef __sio_fd_t_defined +typedef void * sio_fd_t; +#endif + +/* The following functions can be defined to something else in your cc.h file + or be implemented in your custom sio.c file. */ + +#ifndef sio_open +/** + * Opens a serial device for communication. + * + * @param devnum device number + * @return handle to serial device if successful, NULL otherwise + */ +sio_fd_t sio_open(u8_t devnum); +#endif + +#ifndef sio_send +/** + * Sends a single character to the serial device. + * + * @param c character to send + * @param fd serial device handle + * + * @note This function will block until the character can be sent. + */ +void sio_send(u8_t c, sio_fd_t fd); +#endif + +#ifndef sio_recv +/** + * Receives a single character from the serial device. + * + * @param fd serial device handle + * + * @note This function will block until a character is received. + */ +u8_t sio_recv(sio_fd_t fd); +#endif + +#ifndef sio_read +/** + * Reads from the serial device. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received - may be 0 if aborted by sio_read_abort + * + * @note This function will block until data can be received. The blocking + * can be cancelled by calling sio_read_abort(). + */ +u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_tryread +/** + * Tries to read from the serial device. Same as sio_read but returns + * immediately if no data is available and never blocks. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received + */ +u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_write +/** + * Writes to the serial device. + * + * @param fd serial device handle + * @param data pointer to data to send + * @param len length (in bytes) of data to send + * @return number of bytes actually sent + * + * @note This function will block until all data can be sent. + */ +u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_read_abort +/** + * Aborts a blocking sio_read() call. + * + * @param fd serial device handle + */ +void sio_read_abort(sio_fd_t fd); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __SIO_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp.h new file mode 100644 index 0000000..2ed043d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2001, 2002 Leon Woestenberg + * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Leon Woestenberg + * + */ +#ifndef __LWIP_SNMP_H__ +#define __LWIP_SNMP_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lwip/ip_addr.h" + +struct udp_pcb; +struct netif; + +/** + * @see RFC1213, "MIB-II, 6. Definitions" + */ +enum snmp_ifType { + snmp_ifType_other=1, /* none of the following */ + snmp_ifType_regular1822, + snmp_ifType_hdh1822, + snmp_ifType_ddn_x25, + snmp_ifType_rfc877_x25, + snmp_ifType_ethernet_csmacd, + snmp_ifType_iso88023_csmacd, + snmp_ifType_iso88024_tokenBus, + snmp_ifType_iso88025_tokenRing, + snmp_ifType_iso88026_man, + snmp_ifType_starLan, + snmp_ifType_proteon_10Mbit, + snmp_ifType_proteon_80Mbit, + snmp_ifType_hyperchannel, + snmp_ifType_fddi, + snmp_ifType_lapb, + snmp_ifType_sdlc, + snmp_ifType_ds1, /* T-1 */ + snmp_ifType_e1, /* european equiv. of T-1 */ + snmp_ifType_basicISDN, + snmp_ifType_primaryISDN, /* proprietary serial */ + snmp_ifType_propPointToPointSerial, + snmp_ifType_ppp, + snmp_ifType_softwareLoopback, + snmp_ifType_eon, /* CLNP over IP [11] */ + snmp_ifType_ethernet_3Mbit, + snmp_ifType_nsip, /* XNS over IP */ + snmp_ifType_slip, /* generic SLIP */ + snmp_ifType_ultra, /* ULTRA technologies */ + snmp_ifType_ds3, /* T-3 */ + snmp_ifType_sip, /* SMDS */ + snmp_ifType_frame_relay +}; + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +/** SNMP "sysuptime" Interval */ +#define SNMP_SYSUPTIME_INTERVAL 10 + +/** fixed maximum length for object identifier type */ +#define LWIP_SNMP_OBJ_ID_LEN 32 + +/** internal object identifier representation */ +struct snmp_obj_id +{ + u8_t len; + s32_t id[LWIP_SNMP_OBJ_ID_LEN]; +}; + +/* system */ +void snmp_set_sysdesr(u8_t* str, u8_t* len); +void snmp_set_sysobjid(struct snmp_obj_id *oid); +void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid); +void snmp_inc_sysuptime(void); +void snmp_add_sysuptime(u32_t value); +void snmp_get_sysuptime(u32_t *value); +void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen); + +/* network interface */ +void snmp_add_ifinoctets(struct netif *ni, u32_t value); +void snmp_inc_ifinucastpkts(struct netif *ni); +void snmp_inc_ifinnucastpkts(struct netif *ni); +void snmp_inc_ifindiscards(struct netif *ni); +void snmp_add_ifoutoctets(struct netif *ni, u32_t value); +void snmp_inc_ifoutucastpkts(struct netif *ni); +void snmp_inc_ifoutnucastpkts(struct netif *ni); +void snmp_inc_ifoutdiscards(struct netif *ni); +void snmp_inc_iflist(void); +void snmp_dec_iflist(void); + +/* ARP (for atTable and ipNetToMediaTable) */ +void snmp_insert_arpidx_tree(struct netif *ni, ip_addr_t *ip); +void snmp_delete_arpidx_tree(struct netif *ni, ip_addr_t *ip); + +/* IP */ +void snmp_inc_ipinreceives(void); +void snmp_inc_ipinhdrerrors(void); +void snmp_inc_ipinaddrerrors(void); +void snmp_inc_ipforwdatagrams(void); +void snmp_inc_ipinunknownprotos(void); +void snmp_inc_ipindiscards(void); +void snmp_inc_ipindelivers(void); +void snmp_inc_ipoutrequests(void); +void snmp_inc_ipoutdiscards(void); +void snmp_inc_ipoutnoroutes(void); +void snmp_inc_ipreasmreqds(void); +void snmp_inc_ipreasmoks(void); +void snmp_inc_ipreasmfails(void); +void snmp_inc_ipfragoks(void); +void snmp_inc_ipfragfails(void); +void snmp_inc_ipfragcreates(void); +void snmp_inc_iproutingdiscards(void); +void snmp_insert_ipaddridx_tree(struct netif *ni); +void snmp_delete_ipaddridx_tree(struct netif *ni); +void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni); +void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni); + +/* ICMP */ +void snmp_inc_icmpinmsgs(void); +void snmp_inc_icmpinerrors(void); +void snmp_inc_icmpindestunreachs(void); +void snmp_inc_icmpintimeexcds(void); +void snmp_inc_icmpinparmprobs(void); +void snmp_inc_icmpinsrcquenchs(void); +void snmp_inc_icmpinredirects(void); +void snmp_inc_icmpinechos(void); +void snmp_inc_icmpinechoreps(void); +void snmp_inc_icmpintimestamps(void); +void snmp_inc_icmpintimestampreps(void); +void snmp_inc_icmpinaddrmasks(void); +void snmp_inc_icmpinaddrmaskreps(void); +void snmp_inc_icmpoutmsgs(void); +void snmp_inc_icmpouterrors(void); +void snmp_inc_icmpoutdestunreachs(void); +void snmp_inc_icmpouttimeexcds(void); +void snmp_inc_icmpoutparmprobs(void); +void snmp_inc_icmpoutsrcquenchs(void); +void snmp_inc_icmpoutredirects(void); +void snmp_inc_icmpoutechos(void); +void snmp_inc_icmpoutechoreps(void); +void snmp_inc_icmpouttimestamps(void); +void snmp_inc_icmpouttimestampreps(void); +void snmp_inc_icmpoutaddrmasks(void); +void snmp_inc_icmpoutaddrmaskreps(void); + +/* TCP */ +void snmp_inc_tcpactiveopens(void); +void snmp_inc_tcppassiveopens(void); +void snmp_inc_tcpattemptfails(void); +void snmp_inc_tcpestabresets(void); +void snmp_inc_tcpinsegs(void); +void snmp_inc_tcpoutsegs(void); +void snmp_inc_tcpretranssegs(void); +void snmp_inc_tcpinerrs(void); +void snmp_inc_tcpoutrsts(void); + +/* UDP */ +void snmp_inc_udpindatagrams(void); +void snmp_inc_udpnoports(void); +void snmp_inc_udpinerrors(void); +void snmp_inc_udpoutdatagrams(void); +void snmp_insert_udpidx_tree(struct udp_pcb *pcb); +void snmp_delete_udpidx_tree(struct udp_pcb *pcb); + +/* SNMP */ +void snmp_inc_snmpinpkts(void); +void snmp_inc_snmpoutpkts(void); +void snmp_inc_snmpinbadversions(void); +void snmp_inc_snmpinbadcommunitynames(void); +void snmp_inc_snmpinbadcommunityuses(void); +void snmp_inc_snmpinasnparseerrs(void); +void snmp_inc_snmpintoobigs(void); +void snmp_inc_snmpinnosuchnames(void); +void snmp_inc_snmpinbadvalues(void); +void snmp_inc_snmpinreadonlys(void); +void snmp_inc_snmpingenerrs(void); +void snmp_add_snmpintotalreqvars(u8_t value); +void snmp_add_snmpintotalsetvars(u8_t value); +void snmp_inc_snmpingetrequests(void); +void snmp_inc_snmpingetnexts(void); +void snmp_inc_snmpinsetrequests(void); +void snmp_inc_snmpingetresponses(void); +void snmp_inc_snmpintraps(void); +void snmp_inc_snmpouttoobigs(void); +void snmp_inc_snmpoutnosuchnames(void); +void snmp_inc_snmpoutbadvalues(void); +void snmp_inc_snmpoutgenerrs(void); +void snmp_inc_snmpoutgetrequests(void); +void snmp_inc_snmpoutgetnexts(void); +void snmp_inc_snmpoutsetrequests(void); +void snmp_inc_snmpoutgetresponses(void); +void snmp_inc_snmpouttraps(void); +void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid); +void snmp_set_snmpenableauthentraps(u8_t *value); +void snmp_get_snmpenableauthentraps(u8_t *value); + +/* LWIP_SNMP support not available */ +/* define everything to be empty */ +#else + +/* system */ +#define snmp_set_sysdesr(str, len) +#define snmp_set_sysobjid(oid); +#define snmp_get_sysobjid_ptr(oid) +#define snmp_inc_sysuptime() +#define snmp_add_sysuptime(value) +#define snmp_get_sysuptime(value) +#define snmp_set_syscontact(ocstr, ocstrlen); +#define snmp_set_sysname(ocstr, ocstrlen); +#define snmp_set_syslocation(ocstr, ocstrlen); + +/* network interface */ +#define snmp_add_ifinoctets(ni,value) +#define snmp_inc_ifinucastpkts(ni) +#define snmp_inc_ifinnucastpkts(ni) +#define snmp_inc_ifindiscards(ni) +#define snmp_add_ifoutoctets(ni,value) +#define snmp_inc_ifoutucastpkts(ni) +#define snmp_inc_ifoutnucastpkts(ni) +#define snmp_inc_ifoutdiscards(ni) +#define snmp_inc_iflist() +#define snmp_dec_iflist() + +/* ARP */ +#define snmp_insert_arpidx_tree(ni,ip) +#define snmp_delete_arpidx_tree(ni,ip) + +/* IP */ +#define snmp_inc_ipinreceives() +#define snmp_inc_ipinhdrerrors() +#define snmp_inc_ipinaddrerrors() +#define snmp_inc_ipforwdatagrams() +#define snmp_inc_ipinunknownprotos() +#define snmp_inc_ipindiscards() +#define snmp_inc_ipindelivers() +#define snmp_inc_ipoutrequests() +#define snmp_inc_ipoutdiscards() +#define snmp_inc_ipoutnoroutes() +#define snmp_inc_ipreasmreqds() +#define snmp_inc_ipreasmoks() +#define snmp_inc_ipreasmfails() +#define snmp_inc_ipfragoks() +#define snmp_inc_ipfragfails() +#define snmp_inc_ipfragcreates() +#define snmp_inc_iproutingdiscards() +#define snmp_insert_ipaddridx_tree(ni) +#define snmp_delete_ipaddridx_tree(ni) +#define snmp_insert_iprteidx_tree(dflt, ni) +#define snmp_delete_iprteidx_tree(dflt, ni) + +/* ICMP */ +#define snmp_inc_icmpinmsgs() +#define snmp_inc_icmpinerrors() +#define snmp_inc_icmpindestunreachs() +#define snmp_inc_icmpintimeexcds() +#define snmp_inc_icmpinparmprobs() +#define snmp_inc_icmpinsrcquenchs() +#define snmp_inc_icmpinredirects() +#define snmp_inc_icmpinechos() +#define snmp_inc_icmpinechoreps() +#define snmp_inc_icmpintimestamps() +#define snmp_inc_icmpintimestampreps() +#define snmp_inc_icmpinaddrmasks() +#define snmp_inc_icmpinaddrmaskreps() +#define snmp_inc_icmpoutmsgs() +#define snmp_inc_icmpouterrors() +#define snmp_inc_icmpoutdestunreachs() +#define snmp_inc_icmpouttimeexcds() +#define snmp_inc_icmpoutparmprobs() +#define snmp_inc_icmpoutsrcquenchs() +#define snmp_inc_icmpoutredirects() +#define snmp_inc_icmpoutechos() +#define snmp_inc_icmpoutechoreps() +#define snmp_inc_icmpouttimestamps() +#define snmp_inc_icmpouttimestampreps() +#define snmp_inc_icmpoutaddrmasks() +#define snmp_inc_icmpoutaddrmaskreps() +/* TCP */ +#define snmp_inc_tcpactiveopens() +#define snmp_inc_tcppassiveopens() +#define snmp_inc_tcpattemptfails() +#define snmp_inc_tcpestabresets() +#define snmp_inc_tcpinsegs() +#define snmp_inc_tcpoutsegs() +#define snmp_inc_tcpretranssegs() +#define snmp_inc_tcpinerrs() +#define snmp_inc_tcpoutrsts() + +/* UDP */ +#define snmp_inc_udpindatagrams() +#define snmp_inc_udpnoports() +#define snmp_inc_udpinerrors() +#define snmp_inc_udpoutdatagrams() +#define snmp_insert_udpidx_tree(pcb) +#define snmp_delete_udpidx_tree(pcb) + +/* SNMP */ +#define snmp_inc_snmpinpkts() +#define snmp_inc_snmpoutpkts() +#define snmp_inc_snmpinbadversions() +#define snmp_inc_snmpinbadcommunitynames() +#define snmp_inc_snmpinbadcommunityuses() +#define snmp_inc_snmpinasnparseerrs() +#define snmp_inc_snmpintoobigs() +#define snmp_inc_snmpinnosuchnames() +#define snmp_inc_snmpinbadvalues() +#define snmp_inc_snmpinreadonlys() +#define snmp_inc_snmpingenerrs() +#define snmp_add_snmpintotalreqvars(value) +#define snmp_add_snmpintotalsetvars(value) +#define snmp_inc_snmpingetrequests() +#define snmp_inc_snmpingetnexts() +#define snmp_inc_snmpinsetrequests() +#define snmp_inc_snmpingetresponses() +#define snmp_inc_snmpintraps() +#define snmp_inc_snmpouttoobigs() +#define snmp_inc_snmpoutnosuchnames() +#define snmp_inc_snmpoutbadvalues() +#define snmp_inc_snmpoutgenerrs() +#define snmp_inc_snmpoutgetrequests() +#define snmp_inc_snmpoutgetnexts() +#define snmp_inc_snmpoutsetrequests() +#define snmp_inc_snmpoutgetresponses() +#define snmp_inc_snmpouttraps() +#define snmp_get_snmpgrpid_ptr(oid) +#define snmp_set_snmpenableauthentraps(value) +#define snmp_get_snmpenableauthentraps(value) + +#endif /* LWIP_SNMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_SNMP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_asn1.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_asn1.h new file mode 100644 index 0000000..605fa3f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_asn1.h @@ -0,0 +1,101 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) codec. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_ASN1_H__ +#define __LWIP_SNMP_ASN1_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/snmp.h" + +#if LWIP_SNMP + +#ifdef __cplusplus +extern "C" { +#endif + +#define SNMP_ASN1_UNIV (0) /* (!0x80 | !0x40) */ +#define SNMP_ASN1_APPLIC (0x40) /* (!0x80 | 0x40) */ +#define SNMP_ASN1_CONTXT (0x80) /* ( 0x80 | !0x40) */ + +#define SNMP_ASN1_CONSTR (0x20) /* ( 0x20) */ +#define SNMP_ASN1_PRIMIT (0) /* (!0x20) */ + +/* universal tags */ +#define SNMP_ASN1_INTEG 2 +#define SNMP_ASN1_OC_STR 4 +#define SNMP_ASN1_NUL 5 +#define SNMP_ASN1_OBJ_ID 6 +#define SNMP_ASN1_SEQ 16 + +/* application specific (SNMP) tags */ +#define SNMP_ASN1_IPADDR 0 /* octet string size(4) */ +#define SNMP_ASN1_COUNTER 1 /* u32_t */ +#define SNMP_ASN1_GAUGE 2 /* u32_t */ +#define SNMP_ASN1_TIMETICKS 3 /* u32_t */ +#define SNMP_ASN1_OPAQUE 4 /* octet string */ + +/* context specific (SNMP) tags */ +#define SNMP_ASN1_PDU_GET_REQ 0 +#define SNMP_ASN1_PDU_GET_NEXT_REQ 1 +#define SNMP_ASN1_PDU_GET_RESP 2 +#define SNMP_ASN1_PDU_SET_REQ 3 +#define SNMP_ASN1_PDU_TRAP 4 + +err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type); +err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length); +err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value); +err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value); +err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid); +err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw); + +void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed); +void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed); +void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed); +void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed); +err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type); +err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length); +err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, u32_t value); +err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, s32_t value); +err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident); +err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u16_t raw_len, u8_t *raw); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_ASN1_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_msg.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_msg.h new file mode 100644 index 0000000..1183e3a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_msg.h @@ -0,0 +1,315 @@ +/** + * @file + * SNMP Agent message handling structures. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_MSG_H__ +#define __LWIP_SNMP_MSG_H__ + +#include "lwip/opt.h" +#include "lwip/snmp.h" +#include "lwip/snmp_structs.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" + +#if LWIP_SNMP + +#if SNMP_PRIVATE_MIB +/* When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. */ +#include "private_mib.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* The listen port of the SNMP agent. Clients have to make their requests to + this port. Most standard clients won't work if you change this! */ +#ifndef SNMP_IN_PORT +#define SNMP_IN_PORT 161 +#endif +/* The remote port the SNMP agent sends traps to. Most standard trap sinks won't + work if you change this! */ +#ifndef SNMP_TRAP_PORT +#define SNMP_TRAP_PORT 162 +#endif + +#define SNMP_ES_NOERROR 0 +#define SNMP_ES_TOOBIG 1 +#define SNMP_ES_NOSUCHNAME 2 +#define SNMP_ES_BADVALUE 3 +#define SNMP_ES_READONLY 4 +#define SNMP_ES_GENERROR 5 + +#define SNMP_GENTRAP_COLDSTART 0 +#define SNMP_GENTRAP_WARMSTART 1 +#define SNMP_GENTRAP_AUTHFAIL 4 +#define SNMP_GENTRAP_ENTERPRISESPC 6 + +struct snmp_varbind +{ + /* next pointer, NULL for last in list */ + struct snmp_varbind *next; + /* previous pointer, NULL for first in list */ + struct snmp_varbind *prev; + + /* object identifier length (in s32_t) */ + u8_t ident_len; + /* object identifier array */ + s32_t *ident; + + /* object value ASN1 type */ + u8_t value_type; + /* object value length (in u8_t) */ + u8_t value_len; + /* object value */ + void *value; + + /* encoding varbind seq length length */ + u8_t seqlenlen; + /* encoding object identifier length length */ + u8_t olenlen; + /* encoding object value length length */ + u8_t vlenlen; + /* encoding varbind seq length */ + u16_t seqlen; + /* encoding object identifier length */ + u16_t olen; + /* encoding object value length */ + u16_t vlen; +}; + +struct snmp_varbind_root +{ + struct snmp_varbind *head; + struct snmp_varbind *tail; + /* number of variable bindings in list */ + u8_t count; + /* encoding varbind-list seq length length */ + u8_t seqlenlen; + /* encoding varbind-list seq length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_resp_header_lengths +{ + /* encoding error-index length length */ + u8_t erridxlenlen; + /* encoding error-status length length */ + u8_t errstatlenlen; + /* encoding request id length length */ + u8_t ridlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding error-index length */ + u16_t erridxlen; + /* encoding error-status length */ + u16_t errstatlen; + /* encoding request id length */ + u16_t ridlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_trap_header_lengths +{ + /* encoding timestamp length length */ + u8_t tslenlen; + /* encoding specific-trap length length */ + u8_t strplenlen; + /* encoding generic-trap length length */ + u8_t gtrplenlen; + /* encoding agent-addr length length */ + u8_t aaddrlenlen; + /* encoding enterprise-id length length */ + u8_t eidlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding timestamp length */ + u16_t tslen; + /* encoding specific-trap length */ + u16_t strplen; + /* encoding generic-trap length */ + u16_t gtrplen; + /* encoding agent-addr length */ + u16_t aaddrlen; + /* encoding enterprise-id length */ + u16_t eidlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/* Accepting new SNMP messages. */ +#define SNMP_MSG_EMPTY 0 +/* Search for matching object for variable binding. */ +#define SNMP_MSG_SEARCH_OBJ 1 +/* Perform SNMP operation on in-memory object. + Pass-through states, for symmetry only. */ +#define SNMP_MSG_INTERNAL_GET_OBJDEF 2 +#define SNMP_MSG_INTERNAL_GET_VALUE 3 +#define SNMP_MSG_INTERNAL_SET_TEST 4 +#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5 +#define SNMP_MSG_INTERNAL_SET_VALUE 6 +/* Perform SNMP operation on object located externally. + In theory this could be used for building a proxy agent. + Practical use is for an enterprise spc. app. gateway. */ +#define SNMP_MSG_EXTERNAL_GET_OBJDEF 7 +#define SNMP_MSG_EXTERNAL_GET_VALUE 8 +#define SNMP_MSG_EXTERNAL_SET_TEST 9 +#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10 +#define SNMP_MSG_EXTERNAL_SET_VALUE 11 + +#define SNMP_COMMUNITY_STR_LEN 64 +struct snmp_msg_pstat +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* source IP address */ + ip_addr_t sip; + /* source UDP port */ + u16_t sp; + /* request type */ + u8_t rt; + /* request ID */ + s32_t rid; + /* error status */ + s32_t error_status; + /* error index */ + s32_t error_index; + /* community name (zero terminated) */ + u8_t community[SNMP_COMMUNITY_STR_LEN + 1]; + /* community string length (exclusive zero term) */ + u8_t com_strlen; + /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */ + u8_t state; + /* saved arguments for MSG_EXTERNAL_x */ + struct mib_external_node *ext_mib_node; + struct snmp_name_ptr ext_name_ptr; + struct obj_def ext_object_def; + struct snmp_obj_id ext_oid; + /* index into input variable binding list */ + u8_t vb_idx; + /* ptr into input variable binding list */ + struct snmp_varbind *vb_ptr; + /* list of variable bindings from input */ + struct snmp_varbind_root invb; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output response lengths used in ASN encoding */ + struct snmp_resp_header_lengths rhl; +}; + +struct snmp_msg_trap +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* destination IP address in network order */ + ip_addr_t dip; + + /* source enterprise ID (sysObjectID) */ + struct snmp_obj_id *enterprise; + /* source IP address, raw network order format */ + u8_t sip_raw[4]; + /* generic trap code */ + u32_t gen_trap; + /* specific trap code */ + u32_t spc_trap; + /* timestamp */ + u32_t ts; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output trap lengths used in ASN encoding */ + struct snmp_trap_header_lengths thl; +}; + +/** Agent Version constant, 0 = v1 oddity */ +extern const s32_t snmp_version; +/** Agent default "public" community string */ +extern const char snmp_publiccommunity[7]; + +extern struct snmp_msg_trap trap_msg; + +/** Agent setup, start listening to port 161. */ +void snmp_init(void); +void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable); +void snmp_trap_dst_ip_set(u8_t dst_idx, ip_addr_t *dst); + +/** Varbind-list functions. */ +struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len); +void snmp_varbind_free(struct snmp_varbind *vb); +void snmp_varbind_list_free(struct snmp_varbind_root *root); +void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb); +struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root); + +/** Handle an internal (recv) or external (private response) event. */ +void snmp_msg_event(u8_t request_id); +err_t snmp_send_response(struct snmp_msg_pstat *m_stat); +err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap); +void snmp_coldstart_trap(void); +void snmp_authfail_trap(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_MSG_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_structs.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_structs.h new file mode 100644 index 0000000..0d3b46a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_structs.h @@ -0,0 +1,268 @@ +/** + * @file + * Generic MIB tree structures. + * + * @todo namespace prefixes + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_STRUCTS_H__ +#define __LWIP_SNMP_STRUCTS_H__ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/snmp.h" + +#if SNMP_PRIVATE_MIB +/* When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. */ +#include "private_mib.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* MIB object instance */ +#define MIB_OBJECT_NONE 0 +#define MIB_OBJECT_SCALAR 1 +#define MIB_OBJECT_TAB 2 + +/* MIB access types */ +#define MIB_ACCESS_READ 1 +#define MIB_ACCESS_WRITE 2 + +/* MIB object access */ +#define MIB_OBJECT_READ_ONLY MIB_ACCESS_READ +#define MIB_OBJECT_READ_WRITE (MIB_ACCESS_READ | MIB_ACCESS_WRITE) +#define MIB_OBJECT_WRITE_ONLY MIB_ACCESS_WRITE +#define MIB_OBJECT_NOT_ACCESSIBLE 0 + +/** object definition returned by (get_object_def)() */ +struct obj_def +{ + /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */ + u8_t instance; + /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */ + u8_t access; + /* ASN type for this object */ + u8_t asn_type; + /* value length (host length) */ + u16_t v_len; + /* length of instance part of supplied object identifier */ + u8_t id_inst_len; + /* instance part of supplied object identifier */ + s32_t *id_inst_ptr; +}; + +struct snmp_name_ptr +{ + u8_t ident_len; + s32_t *ident; +}; + +/** MIB const scalar (.0) node */ +#define MIB_NODE_SC 0x01 +/** MIB const array node */ +#define MIB_NODE_AR 0x02 +/** MIB array node (mem_malloced from RAM) */ +#define MIB_NODE_RA 0x03 +/** MIB list root node (mem_malloced from RAM) */ +#define MIB_NODE_LR 0x04 +/** MIB node for external objects */ +#define MIB_NODE_EX 0x05 + +/** node "base class" layout, the mandatory fields for a node */ +struct mib_node +{ + /** returns struct obj_def for the given object identifier */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + /** returns object value for the given object identifier, + @note the caller must allocate at least len bytes for the value */ + void (*get_value)(struct obj_def *od, u16_t len, void *value); + /** tests length and/or range BEFORE setting */ + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + /** sets object value, only to be called when set_test() */ + void (*set_value)(struct obj_def *od, u16_t len, void *value); + /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */ + u8_t node_type; + /* array or max list length */ + u16_t maxlength; +}; + +/** derived node for scalars .0 index */ +typedef struct mib_node mib_scalar_node; + +/** derived node, points to a fixed size const array + of sub-identifiers plus a 'child' pointer */ +struct mib_array_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* additional struct members */ + const s32_t *objid; + struct mib_node* const *nptr; +}; + +/** derived node, points to a fixed size mem_malloced array + of sub-identifiers plus a 'child' pointer */ +struct mib_ram_array_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + s32_t *objid; + struct mib_node **nptr; +}; + +struct mib_list_node +{ + struct mib_list_node *prev; + struct mib_list_node *next; + s32_t objid; + struct mib_node *nptr; +}; + +/** derived node, points to a doubly linked list + of sub-identifiers plus a 'child' pointer */ +struct mib_list_rootnode +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* additional struct members */ + struct mib_list_node *head; + struct mib_list_node *tail; + /* counts list nodes in list */ + u16_t count; +}; + +/** derived node, has access functions for mib object in external memory or device + using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */ +struct mib_external_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* additional struct members */ + /** points to an external (in memory) record of some sort of addressing + information, passed to and interpreted by the funtions below */ + void* addr_inf; + /** tree levels under this node */ + u8_t tree_levels; + /** number of objects at this level */ + u16_t (*level_length)(void* addr_inf, u8_t level); + /** compares object sub identifier with external id + return zero when equal, nonzero when unequal */ + s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id); + void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id); + + /** async Questions */ + void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_q)(u8_t rid, struct obj_def *od); + void (*set_test_q)(u8_t rid, struct obj_def *od); + void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Answers */ + void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Panic Close (agent returns error reply, + e.g. used for external transaction cleanup) */ + void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_pc)(u8_t rid, struct obj_def *od); + void (*set_test_pc)(u8_t rid, struct obj_def *od); + void (*set_value_pc)(u8_t rid, struct obj_def *od); +}; + +/** export MIB tree from mib2.c */ +extern const struct mib_array_node internet; + +/** dummy function pointers for non-leaf MIB nodes from mib2.c */ +void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +void noleafs_get_value(struct obj_def *od, u16_t len, void *value); +u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value); +void noleafs_set_value(struct obj_def *od, u16_t len, void *value); + +void snmp_oidtoip(s32_t *ident, ip_addr_t *ip); +void snmp_iptooid(ip_addr_t *ip, s32_t *ident); +void snmp_ifindextonetif(s32_t ifindex, struct netif **netif); +void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx); + +struct mib_list_node* snmp_mib_ln_alloc(s32_t id); +void snmp_mib_ln_free(struct mib_list_node *ln); +struct mib_list_rootnode* snmp_mib_lrn_alloc(void); +void snmp_mib_lrn_free(struct mib_list_rootnode *lrn); + +s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn); +s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn); +struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n); + +struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np); +struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); +u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident); +u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_STRUCTS_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/sockets.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/sockets.h new file mode 100644 index 0000000..3c8fed2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/sockets.h @@ -0,0 +1,376 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +#ifndef __LWIP_SOCKETS_H__ +#define __LWIP_SOCKETS_H__ + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include /* for size_t */ + +#include "lwip/ip_addr.h" +#include "lwip/inet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* members are in network byte order */ +struct sockaddr_in { + u8_t sin_len; + u8_t sin_family; + u16_t sin_port; + struct in_addr sin_addr; + char sin_zero[8]; +}; + +struct sockaddr { + u8_t sa_len; + u8_t sa_family; + char sa_data[14]; +}; + +#ifndef socklen_t +# define socklen_t u32_t +#endif + +/* Socket protocol types (TCP/UDP/RAW) */ +#define SOCK_STREAM 1 +#define SOCK_DGRAM 2 +#define SOCK_RAW 3 + +/* + * Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c) + */ +#define SO_DEBUG 0x0001 /* Unimplemented: turn on debugging info recording */ +#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ +#define SO_REUSEADDR 0x0004 /* Allow local address reuse */ +#define SO_KEEPALIVE 0x0008 /* keep connections alive */ +#define SO_DONTROUTE 0x0010 /* Unimplemented: just use interface addresses */ +#define SO_BROADCAST 0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ +#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */ +#define SO_LINGER 0x0080 /* linger on close if data present */ +#define SO_OOBINLINE 0x0100 /* Unimplemented: leave received OOB data in line */ +#define SO_REUSEPORT 0x0200 /* Unimplemented: allow local address & port reuse */ + +#define SO_DONTLINGER ((int)(~SO_LINGER)) + +/* + * Additional options, not kept in so_options. + */ +#define SO_SNDBUF 0x1001 /* Unimplemented: send buffer size */ +#define SO_RCVBUF 0x1002 /* receive buffer size */ +#define SO_SNDLOWAT 0x1003 /* Unimplemented: send low-water mark */ +#define SO_RCVLOWAT 0x1004 /* Unimplemented: receive low-water mark */ +#define SO_SNDTIMEO 0x1005 /* Unimplemented: send timeout */ +#define SO_RCVTIMEO 0x1006 /* receive timeout */ +#define SO_ERROR 0x1007 /* get error status and clear */ +#define SO_TYPE 0x1008 /* get socket type */ +#define SO_CONTIMEO 0x1009 /* Unimplemented: connect timeout */ +#define SO_NO_CHECK 0x100a /* don't create UDP checksum */ + + +/* + * Structure used for manipulating linger option. + */ +struct linger { + int l_onoff; /* option on/off */ + int l_linger; /* linger time */ +}; + +/* + * Level number for (get/set)sockopt() to apply to socket itself. + */ +#define SOL_SOCKET 0xfff /* options for socket level */ + + +#define AF_UNSPEC 0 +#define AF_INET 2 +#define PF_INET AF_INET +#define PF_UNSPEC AF_UNSPEC + +#define IPPROTO_IP 0 +#define IPPROTO_TCP 6 +#define IPPROTO_UDP 17 +#define IPPROTO_UDPLITE 136 + +/* Flags we can use with send and recv. */ +#define MSG_PEEK 0x01 /* Peeks at an incoming message */ +#define MSG_WAITALL 0x02 /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */ +#define MSG_OOB 0x04 /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */ +#define MSG_DONTWAIT 0x08 /* Nonblocking i/o for this operation only */ +#define MSG_MORE 0x10 /* Sender will send more */ + + +/* + * Options for level IPPROTO_IP + */ +#define IP_TOS 1 +#define IP_TTL 2 + +#if LWIP_TCP +/* + * Options for level IPPROTO_TCP + */ +#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ +#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */ +#define TCP_KEEPIDLE 0x03 /* set pcb->keep_idle - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */ +#define TCP_KEEPINTVL 0x04 /* set pcb->keep_intvl - Use seconds for get/setsockopt */ +#define TCP_KEEPCNT 0x05 /* set pcb->keep_cnt - Use number of probes sent for get/setsockopt */ +#endif /* LWIP_TCP */ + +#if LWIP_UDP && LWIP_UDPLITE +/* + * Options for level IPPROTO_UDPLITE + */ +#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */ +#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */ +#endif /* LWIP_UDP && LWIP_UDPLITE*/ + + +#if LWIP_IGMP +/* + * Options and types for UDP multicast traffic handling + */ +#define IP_ADD_MEMBERSHIP 3 +#define IP_DROP_MEMBERSHIP 4 +#define IP_MULTICAST_TTL 5 +#define IP_MULTICAST_IF 6 +#define IP_MULTICAST_LOOP 7 + +typedef struct ip_mreq { + struct in_addr imr_multiaddr; /* IP multicast address of group */ + struct in_addr imr_interface; /* local IP address of interface */ +} ip_mreq; +#endif /* LWIP_IGMP */ + +/* + * The Type of Service provides an indication of the abstract + * parameters of the quality of service desired. These parameters are + * to be used to guide the selection of the actual service parameters + * when transmitting a datagram through a particular network. Several + * networks offer service precedence, which somehow treats high + * precedence traffic as more important than other traffic (generally + * by accepting only traffic above a certain precedence at time of high + * load). The major choice is a three way tradeoff between low-delay, + * high-reliability, and high-throughput. + * The use of the Delay, Throughput, and Reliability indications may + * increase the cost (in some sense) of the service. In many networks + * better performance for one of these parameters is coupled with worse + * performance on another. Except for very unusual cases at most two + * of these three indications should be set. + */ +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_LOWCOST 0x02 +#define IPTOS_MINCOST IPTOS_LOWCOST + +/* + * The Network Control precedence designation is intended to be used + * within a network only. The actual use and control of that + * designation is up to each network. The Internetwork Control + * designation is intended for use by gateway control originators only. + * If the actual use of these precedence designations is of concern to + * a particular network, it is the responsibility of that network to + * control the access to, and use of, those precedence designations. + */ +#define IPTOS_PREC_MASK 0xe0 +#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + + +/* + * Commands for ioctlsocket(), taken from the BSD file fcntl.h. + * lwip_ioctl only supports FIONREAD and FIONBIO, for now + * + * Ioctl's have the command encoded in the lower word, + * and the size of any in or out parameters in the upper + * word. The high 2 bits of the upper word are used + * to encode the in/out status of the parameter; for now + * we restrict parameters to at most 128 bytes. + */ +#if !defined(FIONREAD) || !defined(FIONBIO) +#define IOCPARM_MASK 0x7fU /* parameters must be < 128 bytes */ +#define IOC_VOID 0x20000000UL /* no parameters */ +#define IOC_OUT 0x40000000UL /* copy out parameters */ +#define IOC_IN 0x80000000UL /* copy in parameters */ +#define IOC_INOUT (IOC_IN|IOC_OUT) + /* 0x20000000 distinguishes new & + old ioctl's */ +#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) + +#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) + +#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) +#endif /* !defined(FIONREAD) || !defined(FIONBIO) */ + +#ifndef FIONREAD +#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ +#endif +#ifndef FIONBIO +#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ +#endif + +/* Socket I/O Controls: unimplemented */ +#ifndef SIOCSHIWAT +#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ +#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ +#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ +#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ +#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ +#endif + +/* commands for fnctl */ +#ifndef F_GETFL +#define F_GETFL 3 +#endif +#ifndef F_SETFL +#define F_SETFL 4 +#endif + +/* File status flags and file access modes for fnctl, + these are bits in an int. */ +#ifndef O_NONBLOCK +#define O_NONBLOCK 1 /* nonblocking I/O */ +#endif +#ifndef O_NDELAY +#define O_NDELAY 1 /* same as O_NONBLOCK, for compatibility */ +#endif + +#ifndef SHUT_RD + #define SHUT_RD 0 + #define SHUT_WR 1 + #define SHUT_RDWR 2 +#endif + +/* FD_SET used for lwip_select */ +#ifndef FD_SET + #undef FD_SETSIZE + /* Make FD_SETSIZE match NUM_SOCKETS in socket.c */ + #define FD_SETSIZE MEMP_NUM_NETCONN + #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7))) + #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7))) + #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7))) + #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p))) + + typedef struct fd_set { + unsigned char fd_bits [(FD_SETSIZE+7)/8]; + } fd_set; + +#endif /* FD_SET */ + +/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided + * by your system, set this to 0 and include in cc.h */ +#ifndef LWIP_TIMEVAL_PRIVATE +#define LWIP_TIMEVAL_PRIVATE 1 +#endif + +#if LWIP_TIMEVAL_PRIVATE +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; +#endif /* LWIP_TIMEVAL_PRIVATE */ + +void lwip_socket_init(void); + +int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); +int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_shutdown(int s, int how); +int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); +int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); +int lwip_close(int s); +int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_listen(int s, int backlog); +int lwip_recv(int s, void *mem, size_t len, int flags); +int lwip_read(int s, void *mem, size_t len); +int lwip_recvfrom(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen); +int lwip_send(int s, const void *dataptr, size_t size, int flags); +int lwip_sendto(int s, const void *dataptr, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen); +int lwip_socket(int domain, int type, int protocol); +int lwip_write(int s, const void *dataptr, size_t size); +int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout); +int lwip_ioctl(int s, long cmd, void *argp); +int lwip_fcntl(int s, int cmd, int val); + +#if LWIP_COMPAT_SOCKETS +#define accept(a,b,c) lwip_accept(a,b,c) +#define bind(a,b,c) lwip_bind(a,b,c) +#define shutdown(a,b) lwip_shutdown(a,b) +#define closesocket(s) lwip_close(s) +#define connect(a,b,c) lwip_connect(a,b,c) +#define getsockname(a,b,c) lwip_getsockname(a,b,c) +#define getpeername(a,b,c) lwip_getpeername(a,b,c) +#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e) +#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e) +#define listen(a,b) lwip_listen(a,b) +#define recv(a,b,c,d) lwip_recv(a,b,c,d) +#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f) +#define send(a,b,c,d) lwip_send(a,b,c,d) +#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f) +#define socket(a,b,c) lwip_socket(a,b,c) +#define select(a,b,c,d,e) lwip_select(a,b,c,d,e) +#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c) + +#if LWIP_POSIX_SOCKETS_IO_NAMES +#define read(a,b,c) lwip_read(a,b,c) +#define write(a,b,c) lwip_write(a,b,c) +#define close(s) lwip_close(s) +#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */ + +#endif /* LWIP_COMPAT_SOCKETS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SOCKET */ + +#endif /* __LWIP_SOCKETS_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/stats.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/stats.h new file mode 100644 index 0000000..015b7ce --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/stats.h @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_STATS_H__ +#define __LWIP_STATS_H__ + +#include "lwip/opt.h" + +#include "lwip/mem.h" +#include "lwip/memp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_STATS + +#ifndef LWIP_STATS_LARGE +#define LWIP_STATS_LARGE 0 +#endif + +#if LWIP_STATS_LARGE +#define STAT_COUNTER u32_t +#define STAT_COUNTER_F U32_F +#else +#define STAT_COUNTER u16_t +#define STAT_COUNTER_F U16_F +#endif + +struct stats_proto { + STAT_COUNTER xmit; /* Transmitted packets. */ + STAT_COUNTER recv; /* Received packets. */ + STAT_COUNTER fw; /* Forwarded packets. */ + STAT_COUNTER drop; /* Dropped packets. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER memerr; /* Out of memory error. */ + STAT_COUNTER rterr; /* Routing error. */ + STAT_COUNTER proterr; /* Protocol error. */ + STAT_COUNTER opterr; /* Error in options. */ + STAT_COUNTER err; /* Misc error. */ + STAT_COUNTER cachehit; +}; + +struct stats_igmp { + STAT_COUNTER xmit; /* Transmitted packets. */ + STAT_COUNTER recv; /* Received packets. */ + STAT_COUNTER drop; /* Dropped packets. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER memerr; /* Out of memory error. */ + STAT_COUNTER proterr; /* Protocol error. */ + STAT_COUNTER rx_v1; /* Received v1 frames. */ + STAT_COUNTER rx_group; /* Received group-specific queries. */ + STAT_COUNTER rx_general; /* Received general queries. */ + STAT_COUNTER rx_report; /* Received reports. */ + STAT_COUNTER tx_join; /* Sent joins. */ + STAT_COUNTER tx_leave; /* Sent leaves. */ + STAT_COUNTER tx_report; /* Sent reports. */ +}; + +struct stats_mem { +#ifdef LWIP_DEBUG + const char *name; +#endif /* LWIP_DEBUG */ + mem_size_t avail; + mem_size_t used; + mem_size_t max; + STAT_COUNTER err; + STAT_COUNTER illegal; +}; + +struct stats_syselem { + STAT_COUNTER used; + STAT_COUNTER max; + STAT_COUNTER err; +}; + +struct stats_sys { + struct stats_syselem sem; + struct stats_syselem mutex; + struct stats_syselem mbox; +}; + +struct stats_ { +#if LINK_STATS + struct stats_proto link; +#endif +#if ETHARP_STATS + struct stats_proto etharp; +#endif +#if IPFRAG_STATS + struct stats_proto ip_frag; +#endif +#if IP_STATS + struct stats_proto ip; +#endif +#if ICMP_STATS + struct stats_proto icmp; +#endif +#if IGMP_STATS + struct stats_igmp igmp; +#endif +#if UDP_STATS + struct stats_proto udp; +#endif +#if TCP_STATS + struct stats_proto tcp; +#endif +#if MEM_STATS + struct stats_mem mem; +#endif +#if MEMP_STATS + struct stats_mem memp[MEMP_MAX]; +#endif +#if SYS_STATS + struct stats_sys sys; +#endif +}; + +extern struct stats_ lwip_stats; + +void stats_init(void); + +#define STATS_INC(x) ++lwip_stats.x +#define STATS_DEC(x) --lwip_stats.x +#define STATS_INC_USED(x, y) do { lwip_stats.x.used += y; \ + if (lwip_stats.x.max < lwip_stats.x.used) { \ + lwip_stats.x.max = lwip_stats.x.used; \ + } \ + } while(0) +#else /* LWIP_STATS */ +#define stats_init() +#define STATS_INC(x) +#define STATS_DEC(x) +#define STATS_INC_USED(x) +#endif /* LWIP_STATS */ + +#if TCP_STATS +#define TCP_STATS_INC(x) STATS_INC(x) +#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP") +#else +#define TCP_STATS_INC(x) +#define TCP_STATS_DISPLAY() +#endif + +#if UDP_STATS +#define UDP_STATS_INC(x) STATS_INC(x) +#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP") +#else +#define UDP_STATS_INC(x) +#define UDP_STATS_DISPLAY() +#endif + +#if ICMP_STATS +#define ICMP_STATS_INC(x) STATS_INC(x) +#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP") +#else +#define ICMP_STATS_INC(x) +#define ICMP_STATS_DISPLAY() +#endif + +#if IGMP_STATS +#define IGMP_STATS_INC(x) STATS_INC(x) +#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp) +#else +#define IGMP_STATS_INC(x) +#define IGMP_STATS_DISPLAY() +#endif + +#if IP_STATS +#define IP_STATS_INC(x) STATS_INC(x) +#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP") +#else +#define IP_STATS_INC(x) +#define IP_STATS_DISPLAY() +#endif + +#if IPFRAG_STATS +#define IPFRAG_STATS_INC(x) STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG") +#else +#define IPFRAG_STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() +#endif + +#if ETHARP_STATS +#define ETHARP_STATS_INC(x) STATS_INC(x) +#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP") +#else +#define ETHARP_STATS_INC(x) +#define ETHARP_STATS_DISPLAY() +#endif + +#if LINK_STATS +#define LINK_STATS_INC(x) STATS_INC(x) +#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK") +#else +#define LINK_STATS_INC(x) +#define LINK_STATS_DISPLAY() +#endif + +#if MEM_STATS +#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y +#define MEM_STATS_INC(x) STATS_INC(mem.x) +#define MEM_STATS_INC_USED(x, y) STATS_INC_USED(mem, y) +#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x -= y +#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP") +#else +#define MEM_STATS_AVAIL(x, y) +#define MEM_STATS_INC(x) +#define MEM_STATS_INC_USED(x, y) +#define MEM_STATS_DEC_USED(x, y) +#define MEM_STATS_DISPLAY() +#endif + +#if MEMP_STATS +#define MEMP_STATS_AVAIL(x, i, y) lwip_stats.memp[i].x = y +#define MEMP_STATS_INC(x, i) STATS_INC(memp[i].x) +#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i].x) +#define MEMP_STATS_INC_USED(x, i) STATS_INC_USED(memp[i], 1) +#define MEMP_STATS_DISPLAY(i) stats_display_memp(&lwip_stats.memp[i], i) +#else +#define MEMP_STATS_AVAIL(x, i, y) +#define MEMP_STATS_INC(x, i) +#define MEMP_STATS_DEC(x, i) +#define MEMP_STATS_INC_USED(x, i) +#define MEMP_STATS_DISPLAY(i) +#endif + +#if SYS_STATS +#define SYS_STATS_INC(x) STATS_INC(sys.x) +#define SYS_STATS_DEC(x) STATS_DEC(sys.x) +#define SYS_STATS_INC_USED(x) STATS_INC_USED(sys.x, 1) +#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys) +#else +#define SYS_STATS_INC(x) +#define SYS_STATS_DEC(x) +#define SYS_STATS_INC_USED(x) +#define SYS_STATS_DISPLAY() +#endif + +/* Display of statistics */ +#if LWIP_STATS_DISPLAY +void stats_display(void); +void stats_display_proto(struct stats_proto *proto, char *name); +void stats_display_igmp(struct stats_igmp *igmp); +void stats_display_mem(struct stats_mem *mem, char *name); +void stats_display_memp(struct stats_mem *mem, int index); +void stats_display_sys(struct stats_sys *sys); +#else /* LWIP_STATS_DISPLAY */ +#define stats_display() +#define stats_display_proto(proto, name) +#define stats_display_igmp(igmp) +#define stats_display_mem(mem, name) +#define stats_display_memp(mem, index) +#define stats_display_sys(sys) +#endif /* LWIP_STATS_DISPLAY */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_STATS_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/sys.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/sys.h new file mode 100644 index 0000000..9f62c75 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/sys.h @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_SYS_H__ +#define __LWIP_SYS_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if NO_SYS + +/* For a totally minimal and standalone system, we provide null + definitions of the sys_ functions. */ +typedef u8_t sys_sem_t; +typedef u8_t sys_mutex_t; +typedef u8_t sys_mbox_t; + +#define sys_sem_new(s, c) ERR_OK +#define sys_sem_signal(s) +#define sys_sem_wait(s) +#define sys_arch_sem_wait(s,t) +#define sys_sem_free(s) +#define sys_mutex_new(mu) ERR_OK +#define sys_mutex_lock(mu) +#define sys_mutex_unlock(mu) +#define sys_mutex_free(mu) +#define sys_mbox_new(m, s) ERR_OK +#define sys_mbox_fetch(m,d) +#define sys_mbox_tryfetch(m,d) +#define sys_mbox_post(m,d) +#define sys_mbox_trypost(m,d) +#define sys_mbox_free(m) + +#define sys_thread_new(n,t,a,s,p) + +#define sys_msleep(t) + +#else /* NO_SYS */ + +/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ +#define SYS_ARCH_TIMEOUT 0xffffffffUL + +/** sys_mbox_tryfetch() returns SYS_MBOX_EMPTY if appropriate. + * For now we use the same magic value, but we allow this to change in future. + */ +#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT + +#include "lwip/err.h" +#include "arch/sys_arch.h" + +/** Function prototype for thread functions */ +typedef void (*lwip_thread_fn)(void *arg); + +/* Function prototypes for functions to be implemented by platform ports + (in sys_arch.c) */ + +/* Mutex functions: */ + +/** Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores + should be used instead */ +#if LWIP_COMPAT_MUTEX +/* for old ports that don't have mutexes: define them to binary semaphores */ +#define sys_mutex_t sys_sem_t +#define sys_mutex_new(mutex) sys_sem_new(mutex, 1) +#define sys_mutex_lock(mutex) sys_sem_wait(mutex) +#define sys_mutex_unlock(mutex) sys_sem_signal(mutex) +#define sys_mutex_free(mutex) sys_sem_free(mutex) +#define sys_mutex_valid(mutex) sys_sem_valid(mutex) +#define sys_mutex_set_invalid(mutex) sys_sem_set_invalid(mutex) + +#else /* LWIP_COMPAT_MUTEX */ + +/** Create a new mutex + * @param mutex pointer to the mutex to create + * @return a new mutex */ +err_t sys_mutex_new(sys_mutex_t *mutex); +/** Lock a mutex + * @param mutex the mutex to lock */ +void sys_mutex_lock(sys_mutex_t *mutex); +/** Unlock a mutex + * @param mutex the mutex to unlock */ +void sys_mutex_unlock(sys_mutex_t *mutex); +/** Delete a semaphore + * @param mutex the mutex to delete */ +void sys_mutex_free(sys_mutex_t *mutex); +#ifndef sys_mutex_valid +/** Check if a mutex is valid/allocated: return 1 for valid, 0 for invalid */ +int sys_mutex_valid(sys_mutex_t *mutex); +#endif +#ifndef sys_mutex_set_invalid +/** Set a mutex invalid so that sys_mutex_valid returns 0 */ +void sys_mutex_set_invalid(sys_mutex_t *mutex); +#endif +#endif /* LWIP_COMPAT_MUTEX */ + +/* Semaphore functions: */ + +/** Create a new semaphore + * @param sem pointer to the semaphore to create + * @param count initial count of the semaphore + * @return ERR_OK if successful, another err_t otherwise */ +err_t sys_sem_new(sys_sem_t *sem, u8_t count); +/** Signals a semaphore + * @param sem the semaphore to signal */ +void sys_sem_signal(sys_sem_t *sem); +/** Wait for a semaphore for the specified timeout + * @param sem the semaphore to wait for + * @param timeout timeout in milliseconds to wait (0 = wait forever) + * @return time (in milliseconds) waited for the semaphore + * or SYS_ARCH_TIMEOUT on timeout */ +u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout); +/** Delete a semaphore + * @param sem semaphore to delete */ +void sys_sem_free(sys_sem_t *sem); +/** Wait for a semaphore - forever/no timeout */ +#define sys_sem_wait(sem) sys_arch_sem_wait(sem, 0) +#ifndef sys_sem_valid +/** Check if a sempahore is valid/allocated: return 1 for valid, 0 for invalid */ +int sys_sem_valid(sys_sem_t *sem); +#endif +#ifndef sys_sem_set_invalid +/** Set a semaphore invalid so that sys_sem_valid returns 0 */ +void sys_sem_set_invalid(sys_sem_t *sem); +#endif + +/* Time functions. */ +#ifndef sys_msleep +void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */ +#endif + +/* Mailbox functions. */ + +/** Create a new mbox of specified size + * @param mbox pointer to the mbox to create + * @param size (miminum) number of messages in this mbox + * @return ERR_OK if successful, another err_t otherwise */ +err_t sys_mbox_new(sys_mbox_t *mbox, int size); +/** Post a message to an mbox - may not fail + * -> blocks if full, only used from tasks not from ISR + * @param mbox mbox to posts the message + * @param msg message to post (ATTENTION: can be NULL) */ +void sys_mbox_post(sys_mbox_t *mbox, void *msg); +/** Try to post a message to an mbox - may fail if full or ISR + * @param mbox mbox to posts the message + * @param msg message to post (ATTENTION: can be NULL) */ +err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg); +/** Wait for a new message to arrive in the mbox + * @param mbox mbox to get a message from + * @param msg pointer where the message is stored + * @param timeout maximum time (in milliseconds) to wait for a message + * @return time (in milliseconds) waited for a message, may be 0 if not waited + or SYS_ARCH_TIMEOUT on timeout + * The returned time has to be accurate to prevent timer jitter! */ +u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout); +/* Allow port to override with a macro, e.g. special timout for sys_arch_mbox_fetch() */ +#ifndef sys_arch_mbox_tryfetch +/** Wait for a new message to arrive in the mbox + * @param mbox mbox to get a message from + * @param msg pointer where the message is stored + * @param timeout maximum time (in milliseconds) to wait for a message + * @return 0 (milliseconds) if a message has been received + * or SYS_MBOX_EMPTY if the mailbox is empty */ +u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg); +#endif +/** For now, we map straight to sys_arch implementation. */ +#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg) +/** Delete an mbox + * @param mbox mbox to delete */ +void sys_mbox_free(sys_mbox_t *mbox); +#define sys_mbox_fetch(mbox, msg) sys_arch_mbox_fetch(mbox, msg, 0) +#ifndef sys_mbox_valid +/** Check if an mbox is valid/allocated: return 1 for valid, 0 for invalid */ +int sys_mbox_valid(sys_mbox_t *mbox); +#endif +#ifndef sys_mbox_set_invalid +/** Set an mbox invalid so that sys_mbox_valid returns 0 */ +void sys_mbox_set_invalid(sys_mbox_t *mbox); +#endif + +/** The only thread function: + * Creates a new thread + * @param name human-readable name for the thread (used for debugging purposes) + * @param thread thread-function + * @param arg parameter passed to 'thread' + * @param stacksize stack size in bytes for the new thread (may be ignored by ports) + * @param prio priority of the new thread (may be ignored by ports) */ +sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio); + +#endif /* NO_SYS */ + +/* sys_init() must be called before anthing else. */ +void sys_init(void); + +#ifndef sys_jiffies +/** Ticks/jiffies since power up. */ +u32_t sys_jiffies(void); +#endif + +/** Returns the current time in milliseconds, + * may be the same as sys_jiffies or at least based on it. */ +u32_t sys_now(void); + +/* Critical Region Protection */ +/* These functions must be implemented in the sys_arch.c file. + In some implementations they can provide a more light-weight protection + mechanism than using semaphores. Otherwise semaphores can be used for + implementation */ +#ifndef SYS_ARCH_PROTECT +/** SYS_LIGHTWEIGHT_PROT + * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#if SYS_LIGHTWEIGHT_PROT + +/** SYS_ARCH_DECL_PROTECT + * declare a protection variable. This macro will default to defining a variable of + * type sys_prot_t. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h. + */ +#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev +/** SYS_ARCH_PROTECT + * Perform a "fast" protect. This could be implemented by + * disabling interrupts for an embedded system or by using a semaphore or + * mutex. The implementation should allow calling SYS_ARCH_PROTECT when + * already protected. The old protection level is returned in the variable + * "lev". This macro will default to calling the sys_arch_protect() function + * which should be implemented in sys_arch.c. If a particular port needs a + * different implementation, then this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() +/** SYS_ARCH_UNPROTECT + * Perform a "fast" set of the protection level to "lev". This could be + * implemented by setting the interrupt level to "lev" within the MACRO or by + * using a semaphore or mutex. This macro will default to calling the + * sys_arch_unprotect() function which should be implemented in + * sys_arch.c. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) +sys_prot_t sys_arch_protect(void); +void sys_arch_unprotect(sys_prot_t pval); + +#else + +#define SYS_ARCH_DECL_PROTECT(lev) +#define SYS_ARCH_PROTECT(lev) +#define SYS_ARCH_UNPROTECT(lev) + +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#endif /* SYS_ARCH_PROTECT */ + +/* + * Macros to set/get and increase/decrease variables in a thread-safe way. + * Use these for accessing variable that are used from more than one thread. + */ + +#ifndef SYS_ARCH_INC +#define SYS_ARCH_INC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var += val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_INC */ + +#ifndef SYS_ARCH_DEC +#define SYS_ARCH_DEC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var -= val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_DEC */ + +#ifndef SYS_ARCH_GET +#define SYS_ARCH_GET(var, ret) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + ret = var; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_GET */ + +#ifndef SYS_ARCH_SET +#define SYS_ARCH_SET(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var = val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_SET */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_SYS_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp.h new file mode 100644 index 0000000..07dcd10 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp.h @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCP_H__ +#define __LWIP_TCP_H__ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct tcp_pcb; + +/** Function prototype for tcp accept callback functions. Called when a new + * connection can be accepted on a listening pcb. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param newpcb The new connection pcb + * @param err An error code if there has been an error accepting. + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_accept_fn)(void *arg, struct tcp_pcb *newpcb, err_t err); + +/** Function prototype for tcp receive callback functions. Called when data has + * been received. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb The connection pcb which received data + * @param p The received data (or NULL when the connection has been closed!) + * @param err An error code if there has been an error receiving + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_recv_fn)(void *arg, struct tcp_pcb *tpcb, + struct pbuf *p, err_t err); + +/** Function prototype for tcp sent callback functions. Called when sent data has + * been acknowledged by the remote side. Use it to free corresponding resources. + * This also means that the pcb has now space available to send new data. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb The connection pcb for which data has been acknowledged + * @param len The amount of bytes acknowledged + * @return ERR_OK: try to send some data by calling tcp_output + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_sent_fn)(void *arg, struct tcp_pcb *tpcb, + u16_t len); + +/** Function prototype for tcp poll callback functions. Called periodically as + * specified by @see tcp_poll. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb tcp pcb + * @return ERR_OK: try to send some data by calling tcp_output + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_poll_fn)(void *arg, struct tcp_pcb *tpcb); + +/** Function prototype for tcp error callback functions. Called when the pcb + * receives a RST or is unexpectedly closed for any other reason. + * + * @note The corresponding pcb is already freed when this callback is called! + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param err Error code to indicate why the pcb has been closed + * ERR_ABRT: aborted through tcp_abort or by a TCP timer + * ERR_RST: the connection was reset by the remote host + */ +typedef void (*tcp_err_fn)(void *arg, err_t err); + +/** Function prototype for tcp connected callback functions. Called when a pcb + * is connected to the remote side after initiating a connection attempt by + * calling tcp_connect(). + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb The connection pcb which is connected + * @param err An unused error code, always ERR_OK currently ;-) TODO! + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + * + * @note When a connection attempt fails, the error callback is currently called! + */ +typedef err_t (*tcp_connected_fn)(void *arg, struct tcp_pcb *tpcb, err_t err); + +enum tcp_state { + CLOSED = 0, + LISTEN = 1, + SYN_SENT = 2, + SYN_RCVD = 3, + ESTABLISHED = 4, + FIN_WAIT_1 = 5, + FIN_WAIT_2 = 6, + CLOSE_WAIT = 7, + CLOSING = 8, + LAST_ACK = 9, + TIME_WAIT = 10 +}; + +#if LWIP_CALLBACK_API + /* Function to call when a listener has been connected. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb a new tcp_pcb that now is connected + * @param err an error argument (TODO: that is current always ERR_OK?) + * @return ERR_OK: accept the new connection, + * any other err_t abortsthe new connection + */ +#define DEF_ACCEPT_CALLBACK tcp_accept_fn accept; +#else /* LWIP_CALLBACK_API */ +#define DEF_ACCEPT_CALLBACK +#endif /* LWIP_CALLBACK_API */ + +/** + * members common to struct tcp_pcb and struct tcp_listen_pcb + */ +#define TCP_PCB_COMMON(type) \ + type *next; /* for the linked list */ \ + enum tcp_state state; /* TCP state */ \ + u8_t prio; \ + void *callback_arg; \ + /* the accept callback for listen- and normal pcbs, if LWIP_CALLBACK_API */ \ + DEF_ACCEPT_CALLBACK \ + /* ports are in host byte order */ \ + u16_t local_port + + +/* the TCP protocol control block */ +struct tcp_pcb { +/** common PCB members */ + IP_PCB; +/** protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb); + + /* ports are in host byte order */ + u16_t remote_port; + + u8_t flags; +#define TF_ACK_DELAY ((u8_t)0x01U) /* Delayed ACK. */ +#define TF_ACK_NOW ((u8_t)0x02U) /* Immediate ACK. */ +#define TF_INFR ((u8_t)0x04U) /* In fast recovery. */ +#define TF_TIMESTAMP ((u8_t)0x08U) /* Timestamp option enabled */ +#define TF_RXCLOSED ((u8_t)0x10U) /* rx closed by tcp_shutdown */ +#define TF_FIN ((u8_t)0x20U) /* Connection was closed locally (FIN segment enqueued). */ +#define TF_NODELAY ((u8_t)0x40U) /* Disable Nagle algorithm */ +#define TF_NAGLEMEMERR ((u8_t)0x80U) /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */ + + /* the rest of the fields are in host byte order + as we have to do some math with them */ + /* receiver variables */ + u32_t rcv_nxt; /* next seqno expected */ + u16_t rcv_wnd; /* receiver window available */ + u16_t rcv_ann_wnd; /* receiver window to announce */ + u32_t rcv_ann_right_edge; /* announced right edge of window */ + + /* Timers */ + u32_t tmr; + u8_t polltmr, pollinterval; + + /* Retransmission timer. */ + s16_t rtime; + + u16_t mss; /* maximum segment size */ + + /* RTT (round trip time) estimation variables */ + u32_t rttest; /* RTT estimate in 500ms ticks */ + u32_t rtseq; /* sequence number being timed */ + s16_t sa, sv; /* @todo document this */ + + s16_t rto; /* retransmission time-out */ + u8_t nrtx; /* number of retransmissions */ + + /* fast retransmit/recovery */ + u32_t lastack; /* Highest acknowledged seqno. */ + u8_t dupacks; + + /* congestion avoidance/control variables */ + u16_t cwnd; + u16_t ssthresh; + + /* sender variables */ + u32_t snd_nxt; /* next new seqno to be sent */ + u16_t snd_wnd; /* sender window */ + u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last + window update. */ + u32_t snd_lbb; /* Sequence number of next byte to be buffered. */ + + u16_t acked; + + u16_t snd_buf; /* Available buffer space for sending (in bytes). */ +#define TCP_SNDQUEUELEN_OVERFLOW (0xffffU-3) + u16_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */ + +#if TCP_OVERSIZE + /* Extra bytes available at the end of the last pbuf in unsent. */ + u16_t unsent_oversize; +#endif /* TCP_OVERSIZE */ + + /* These are ordered by sequence number: */ + struct tcp_seg *unsent; /* Unsent (queued) segments. */ + struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ +#if TCP_QUEUE_OOSEQ + struct tcp_seg *ooseq; /* Received out of sequence segments. */ +#endif /* TCP_QUEUE_OOSEQ */ + + struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */ + +#if LWIP_CALLBACK_API + /* Function to be called when more send buffer space is available. */ + tcp_sent_fn sent; + /* Function to be called when (in-sequence) data has arrived. */ + tcp_recv_fn recv; + /* Function to be called when a connection has been set up. */ + tcp_connected_fn connected; + /* Function which is called periodically. */ + tcp_poll_fn poll; + /* Function to be called whenever a fatal error occurs. */ + tcp_err_fn errf; +#endif /* LWIP_CALLBACK_API */ + +#if LWIP_TCP_TIMESTAMPS + u32_t ts_lastacksent; + u32_t ts_recent; +#endif /* LWIP_TCP_TIMESTAMPS */ + + /* idle time before KEEPALIVE is sent */ + u32_t keep_idle; +#if LWIP_TCP_KEEPALIVE + u32_t keep_intvl; + u32_t keep_cnt; +#endif /* LWIP_TCP_KEEPALIVE */ + + /* Persist timer counter */ + u32_t persist_cnt; + /* Persist timer back-off */ + u8_t persist_backoff; + + /* KEEPALIVE counter */ + u8_t keep_cnt_sent; +}; + +struct tcp_pcb_listen { +/* Common members of all PCB types */ + IP_PCB; +/* Protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb_listen); + +#if TCP_LISTEN_BACKLOG + u8_t backlog; + u8_t accepts_pending; +#endif /* TCP_LISTEN_BACKLOG */ +}; + +#if LWIP_EVENT_API + +enum lwip_event { + LWIP_EVENT_ACCEPT, + LWIP_EVENT_SENT, + LWIP_EVENT_RECV, + LWIP_EVENT_CONNECTED, + LWIP_EVENT_POLL, + LWIP_EVENT_ERR +}; + +err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, + enum lwip_event, + struct pbuf *p, + u16_t size, + err_t err); + +#endif /* LWIP_EVENT_API */ + +/* Application program's interface: */ +struct tcp_pcb * tcp_new (void); + +void tcp_arg (struct tcp_pcb *pcb, void *arg); +void tcp_accept (struct tcp_pcb *pcb, tcp_accept_fn accept); +void tcp_recv (struct tcp_pcb *pcb, tcp_recv_fn recv); +void tcp_sent (struct tcp_pcb *pcb, tcp_sent_fn sent); +void tcp_poll (struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval); +void tcp_err (struct tcp_pcb *pcb, tcp_err_fn err); + +#define tcp_mss(pcb) (((pcb)->flags & TF_TIMESTAMP) ? ((pcb)->mss - 12) : (pcb)->mss) +#define tcp_sndbuf(pcb) ((pcb)->snd_buf) +#define tcp_sndqueuelen(pcb) ((pcb)->snd_queuelen) +#define tcp_nagle_disable(pcb) ((pcb)->flags |= TF_NODELAY) +#define tcp_nagle_enable(pcb) ((pcb)->flags &= ~TF_NODELAY) +#define tcp_nagle_disabled(pcb) (((pcb)->flags & TF_NODELAY) != 0) + +#if TCP_LISTEN_BACKLOG +#define tcp_accepted(pcb) do { \ + LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", pcb->state == LISTEN); \ + (((struct tcp_pcb_listen *)(pcb))->accepts_pending--); } while(0) +#else /* TCP_LISTEN_BACKLOG */ +#define tcp_accepted(pcb) LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", \ + pcb->state == LISTEN) +#endif /* TCP_LISTEN_BACKLOG */ + +void tcp_recved (struct tcp_pcb *pcb, u16_t len); +err_t tcp_bind (struct tcp_pcb *pcb, ip_addr_t *ipaddr, + u16_t port); +err_t tcp_connect (struct tcp_pcb *pcb, ip_addr_t *ipaddr, + u16_t port, tcp_connected_fn connected); + +struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog); +#define tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG) + +void tcp_abort (struct tcp_pcb *pcb); +err_t tcp_close (struct tcp_pcb *pcb); +err_t tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx); + +/* Flags for "apiflags" parameter in tcp_write */ +#define TCP_WRITE_FLAG_COPY 0x01 +#define TCP_WRITE_FLAG_MORE 0x02 + +err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, + u8_t apiflags); + +void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); + +#define TCP_PRIO_MIN 1 +#define TCP_PRIO_NORMAL 64 +#define TCP_PRIO_MAX 127 + +err_t tcp_output (struct tcp_pcb *pcb); + + +const char* tcp_debug_state_str(enum tcp_state s); + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP */ + +#endif /* __LWIP_TCP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp_impl.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp_impl.h new file mode 100644 index 0000000..b4feec0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp_impl.h @@ -0,0 +1,471 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCP_IMPL_H__ +#define __LWIP_TCP_IMPL_H__ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcp.h" +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Functions for interfacing with TCP: */ + +/* Lower layer interface to TCP: */ +#define tcp_init() /* Compatibility define, no init needed. */ +void tcp_tmr (void); /* Must be called every + TCP_TMR_INTERVAL + ms. (Typically 250 ms). */ +/* It is also possible to call these two functions at the right + intervals (instead of calling tcp_tmr()). */ +void tcp_slowtmr (void); +void tcp_fasttmr (void); + + +/* Only used by IP to pass a TCP segment to TCP: */ +void tcp_input (struct pbuf *p, struct netif *inp); +/* Used within the TCP code only: */ +struct tcp_pcb * tcp_alloc (u8_t prio); +void tcp_abandon (struct tcp_pcb *pcb, int reset); +err_t tcp_send_empty_ack(struct tcp_pcb *pcb); +void tcp_rexmit (struct tcp_pcb *pcb); +void tcp_rexmit_rto (struct tcp_pcb *pcb); +void tcp_rexmit_fast (struct tcp_pcb *pcb); +u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb); + +/** + * This is the Nagle algorithm: try to combine user data to send as few TCP + * segments as possible. Only send if + * - no previously transmitted data on the connection remains unacknowledged or + * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or + * - the only unsent segment is at least pcb->mss bytes long (or there is more + * than one unsent segment - with lwIP, this can happen although unsent->len < mss) + * - or if we are in fast-retransmit (TF_INFR) + */ +#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \ + ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \ + (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \ + ((tpcb)->unsent->len >= (tpcb)->mss))) \ + ) ? 1 : 0) +#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK) + + +#define TCP_SEQ_LT(a,b) ((s32_t)((a)-(b)) < 0) +#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0) +#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0) +#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0) +/* is b<=a<=c? */ +#if 0 /* see bug #10548 */ +#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) +#endif +#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) +#define TCP_FIN 0x01U +#define TCP_SYN 0x02U +#define TCP_RST 0x04U +#define TCP_PSH 0x08U +#define TCP_ACK 0x10U +#define TCP_URG 0x20U +#define TCP_ECE 0x40U +#define TCP_CWR 0x80U + +#define TCP_FLAGS 0x3fU + +/* Length of the TCP header, excluding options. */ +#define TCP_HLEN 20 + +#ifndef TCP_TMR_INTERVAL +#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in milliseconds. */ +#endif /* TCP_TMR_INTERVAL */ + +#ifndef TCP_FAST_INTERVAL +#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */ +#endif /* TCP_FAST_INTERVAL */ + +#ifndef TCP_SLOW_INTERVAL +#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in milliseconds */ +#endif /* TCP_SLOW_INTERVAL */ + +#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ +#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ + +#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */ + +#ifndef TCP_MSL +#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */ +#endif + +/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */ +#ifndef TCP_KEEPIDLE_DEFAULT +#define TCP_KEEPIDLE_DEFAULT 7200000UL /* Default KEEPALIVE timer in milliseconds */ +#endif + +#ifndef TCP_KEEPINTVL_DEFAULT +#define TCP_KEEPINTVL_DEFAULT 75000UL /* Default Time between KEEPALIVE probes in milliseconds */ +#endif + +#ifndef TCP_KEEPCNT_DEFAULT +#define TCP_KEEPCNT_DEFAULT 9U /* Default Counter for KEEPALIVE probes */ +#endif + +#define TCP_MAXIDLE TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */ + +/* Fields are (of course) in network byte order. + * Some fields are converted to host byte order in tcp_input(). + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct tcp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); + PACK_STRUCT_FIELD(u32_t seqno); + PACK_STRUCT_FIELD(u32_t ackno); + PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); + PACK_STRUCT_FIELD(u16_t wnd); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t urgp); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8) +#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) +#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) + +#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr)) +#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) +#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS((u16_t)(~(u16_t)(TCP_FLAGS)))) | htons(flags)) +#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | (flags)) + +#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | htons(flags)) +#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) + +#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0)) + +/** Flags used on input processing, not on pcb->flags +*/ +#define TF_RESET (u8_t)0x08U /* Connection was reset. */ +#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */ +#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ + + +#if LWIP_EVENT_API + +#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_ACCEPT, NULL, 0, err) +#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_SENT, NULL, space, ERR_OK) +#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, (p), 0, (err)) +#define TCP_EVENT_CLOSED(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, NULL, 0, ERR_OK) +#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_CONNECTED, NULL, 0, (err)) +#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_POLL, NULL, 0, ERR_OK) +#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \ + LWIP_EVENT_ERR, NULL, 0, (err)) + +#else /* LWIP_EVENT_API */ + +#define TCP_EVENT_ACCEPT(pcb,err,ret) \ + do { \ + if((pcb)->accept != NULL) \ + (ret) = (pcb)->accept((pcb)->callback_arg,(pcb),(err)); \ + else (ret) = ERR_ARG; \ + } while (0) + +#define TCP_EVENT_SENT(pcb,space,ret) \ + do { \ + if((pcb)->sent != NULL) \ + (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_RECV(pcb,p,err,ret) \ + do { \ + if((pcb)->recv != NULL) { \ + (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err));\ + } else { \ + (ret) = tcp_recv_null(NULL, (pcb), (p), (err)); \ + } \ + } while (0) + +#define TCP_EVENT_CLOSED(pcb,ret) \ + do { \ + if(((pcb)->recv != NULL)) { \ + (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),NULL,ERR_OK);\ + } else { \ + (ret) = ERR_OK; \ + } \ + } while (0) + +#define TCP_EVENT_CONNECTED(pcb,err,ret) \ + do { \ + if((pcb)->connected != NULL) \ + (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_POLL(pcb,ret) \ + do { \ + if((pcb)->poll != NULL) \ + (ret) = (pcb)->poll((pcb)->callback_arg,(pcb)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_ERR(errf,arg,err) \ + do { \ + if((errf) != NULL) \ + (errf)((arg),(err)); \ + } while (0) + +#endif /* LWIP_EVENT_API */ + +/** Enabled extra-check for TCP_OVERSIZE if LWIP_DEBUG is enabled */ +#if TCP_OVERSIZE && defined(LWIP_DEBUG) +#define TCP_OVERSIZE_DBGCHECK 1 +#else +#define TCP_OVERSIZE_DBGCHECK 0 +#endif + +/** Don't generate checksum on copy if CHECKSUM_GEN_TCP is disabled */ +#define TCP_CHECKSUM_ON_COPY (LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_TCP) + +/* This structure represents a TCP segment on the unsent, unacked and ooseq queues */ +struct tcp_seg { + struct tcp_seg *next; /* used when putting segements on a queue */ + struct pbuf *p; /* buffer containing data + TCP header */ + u16_t len; /* the TCP length of this segment */ +#if TCP_OVERSIZE_DBGCHECK + u16_t oversize_left; /* Extra bytes available at the end of the last + pbuf in unsent (used for asserting vs. + tcp_pcb.unsent_oversized only) */ +#endif /* TCP_OVERSIZE_DBGCHECK */ +#if TCP_CHECKSUM_ON_COPY + u16_t chksum; + u8_t chksum_swapped; +#endif /* TCP_CHECKSUM_ON_COPY */ + u8_t flags; +#define TF_SEG_OPTS_MSS (u8_t)0x01U /* Include MSS option. */ +#define TF_SEG_OPTS_TS (u8_t)0x02U /* Include timestamp option. */ +#define TF_SEG_DATA_CHECKSUMMED (u8_t)0x04U /* ALL data (not the header) is + checksummed into 'chksum' */ + struct tcp_hdr *tcphdr; /* the TCP header */ +}; + +#define LWIP_TCP_OPT_LENGTH(flags) \ + (flags & TF_SEG_OPTS_MSS ? 4 : 0) + \ + (flags & TF_SEG_OPTS_TS ? 12 : 0) + +/** This returns a TCP header option for MSS in an u32_t */ +#define TCP_BUILD_MSS_OPTION(x) (x) = PP_HTONL(((u32_t)2 << 24) | \ + ((u32_t)4 << 16) | \ + (((u32_t)TCP_MSS / 256) << 8) | \ + (TCP_MSS & 255)) + +/* Global variables: */ +extern struct tcp_pcb *tcp_input_pcb; +extern u32_t tcp_ticks; + +/* The TCP PCB lists. */ +union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ + struct tcp_pcb_listen *listen_pcbs; + struct tcp_pcb *pcbs; +}; +extern struct tcp_pcb *tcp_bound_pcbs; +extern union tcp_listen_pcbs_t tcp_listen_pcbs; +extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a + state in which they accept or send + data. */ +extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ + +extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */ + +/* Axioms about the above lists: + 1) Every TCP PCB that is not CLOSED is in one of the lists. + 2) A PCB is only in one of the lists. + 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. + 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. +*/ +/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB + with a PCB list or removes a PCB from a list, respectively. */ +#ifndef TCP_DEBUG_PCB_LISTS +#define TCP_DEBUG_PCB_LISTS 0 +#endif +#if TCP_DEBUG_PCB_LISTS +#define TCP_REG(pcbs, npcb) do {\ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", (npcb), (npcb)->local_port)); \ + for(tcp_tmp_pcb = *(pcbs); \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != (npcb)); \ + } \ + LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", ((pcbs) == &tcp_bound_pcbs) || ((npcb)->state != CLOSED)); \ + (npcb)->next = *(pcbs); \ + LWIP_ASSERT("TCP_REG: npcb->next != npcb", (npcb)->next != (npcb)); \ + *(pcbs) = (npcb); \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + tcp_timer_needed(); \ + } while(0) +#define TCP_RMV(pcbs, npcb) do { \ + LWIP_ASSERT("TCP_RMV: pcbs != NULL", *(pcbs) != NULL); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", (npcb), *(pcbs))); \ + if(*(pcbs) == (npcb)) { \ + *(pcbs) = (*pcbs)->next; \ + } else for(tcp_tmp_pcb = *(pcbs); tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next == (npcb)) { \ + tcp_tmp_pcb->next = (npcb)->next; \ + break; \ + } \ + } \ + (npcb)->next = NULL; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", (npcb), *(pcbs))); \ + } while(0) + +#else /* LWIP_DEBUG */ + +#define TCP_REG(pcbs, npcb) \ + do { \ + (npcb)->next = *pcbs; \ + *(pcbs) = (npcb); \ + tcp_timer_needed(); \ + } while (0) + +#define TCP_RMV(pcbs, npcb) \ + do { \ + if(*(pcbs) == (npcb)) { \ + (*(pcbs)) = (*pcbs)->next; \ + } \ + else { \ + for(tcp_tmp_pcb = *pcbs; \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next == (npcb)) { \ + tcp_tmp_pcb->next = (npcb)->next; \ + break; \ + } \ + } \ + } \ + (npcb)->next = NULL; \ + } while(0) + +#endif /* LWIP_DEBUG */ + + +/* Internal functions: */ +struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); +void tcp_pcb_purge(struct tcp_pcb *pcb); +void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); + +void tcp_segs_free(struct tcp_seg *seg); +void tcp_seg_free(struct tcp_seg *seg); +struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); + +#define tcp_ack(pcb) \ + do { \ + if((pcb)->flags & TF_ACK_DELAY) { \ + (pcb)->flags &= ~TF_ACK_DELAY; \ + (pcb)->flags |= TF_ACK_NOW; \ + } \ + else { \ + (pcb)->flags |= TF_ACK_DELAY; \ + } \ + } while (0) + +#define tcp_ack_now(pcb) \ + do { \ + (pcb)->flags |= TF_ACK_NOW; \ + } while (0) + +err_t tcp_send_fin(struct tcp_pcb *pcb); +err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags); + +void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); + +void tcp_rst(u32_t seqno, u32_t ackno, + ip_addr_t *local_ip, ip_addr_t *remote_ip, + u16_t local_port, u16_t remote_port); + +u32_t tcp_next_iss(void); + +void tcp_keepalive(struct tcp_pcb *pcb); +void tcp_zero_window_probe(struct tcp_pcb *pcb); + +#if TCP_CALCULATE_EFF_SEND_MSS +u16_t tcp_eff_send_mss(u16_t sendmss, ip_addr_t *addr); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +#if LWIP_CALLBACK_API +err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); +#endif /* LWIP_CALLBACK_API */ + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +void tcp_debug_print(struct tcp_hdr *tcphdr); +void tcp_debug_print_flags(u8_t flags); +void tcp_debug_print_state(enum tcp_state s); +void tcp_debug_print_pcbs(void); +s16_t tcp_pcbs_sane(void); +#else +# define tcp_debug_print(tcphdr) +# define tcp_debug_print_flags(flags) +# define tcp_debug_print_state(s) +# define tcp_debug_print_pcbs() +# define tcp_pcbs_sane() 1 +#endif /* TCP_DEBUG */ + +/** External function (implemented in timers.c), called when TCP detects + * that a timer is needed (i.e. active- or time-wait-pcb found). */ +void tcp_timer_needed(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP */ + +#endif /* __LWIP_TCP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/tcpip.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/tcpip.h new file mode 100644 index 0000000..995ba8a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/tcpip.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCPIP_H__ +#define __LWIP_TCPIP_H__ + +#include "lwip/opt.h" + +#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/api_msg.h" +#include "lwip/netifapi.h" +#include "lwip/pbuf.h" +#include "lwip/api.h" +#include "lwip/sys.h" +#include "lwip/timers.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Define this to something that triggers a watchdog. This is called from + * tcpip_thread after processing a message. */ +#ifndef LWIP_TCPIP_THREAD_ALIVE +#define LWIP_TCPIP_THREAD_ALIVE() +#endif + +#if LWIP_TCPIP_CORE_LOCKING +/** The global semaphore to lock the stack. */ +extern sys_mutex_t lock_tcpip_core; +#define LOCK_TCPIP_CORE() sys_mutex_lock(&lock_tcpip_core) +#define UNLOCK_TCPIP_CORE() sys_mutex_unlock(&lock_tcpip_core) +#define TCPIP_APIMSG(m) tcpip_apimsg_lock(m) +#define TCPIP_APIMSG_ACK(m) +#define TCPIP_NETIFAPI(m) tcpip_netifapi_lock(m) +#define TCPIP_NETIFAPI_ACK(m) +#else /* LWIP_TCPIP_CORE_LOCKING */ +#define LOCK_TCPIP_CORE() +#define UNLOCK_TCPIP_CORE() +#define TCPIP_APIMSG(m) tcpip_apimsg(m) +#define TCPIP_APIMSG_ACK(m) sys_sem_signal(&m->conn->op_completed) +#define TCPIP_NETIFAPI(m) tcpip_netifapi(m) +#define TCPIP_NETIFAPI_ACK(m) sys_sem_signal(&m->sem) +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +/** Function prototype for the init_done function passed to tcpip_init */ +typedef void (*tcpip_init_done_fn)(void *arg); +/** Function prototype for functions passed to tcpip_callback() */ +typedef void (*tcpip_callback_fn)(void *ctx); + +void tcpip_init(tcpip_init_done_fn tcpip_init_done, void *arg); + +#if LWIP_NETCONN +err_t tcpip_apimsg(struct api_msg *apimsg); +#if LWIP_TCPIP_CORE_LOCKING +err_t tcpip_apimsg_lock(struct api_msg *apimsg); +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETCONN */ + +err_t tcpip_input(struct pbuf *p, struct netif *inp); + +#if LWIP_NETIF_API +err_t tcpip_netifapi(struct netifapi_msg *netifapimsg); +#if LWIP_TCPIP_CORE_LOCKING +err_t tcpip_netifapi_lock(struct netifapi_msg *netifapimsg); +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETIF_API */ + +err_t tcpip_callback_with_block(tcpip_callback_fn function, void *ctx, u8_t block); +#define tcpip_callback(f, ctx) tcpip_callback_with_block(f, ctx, 1) + +/* free pbufs or heap memory from another context without blocking */ +err_t pbuf_free_callback(struct pbuf *p); +err_t mem_free_callback(void *m); + +#if LWIP_TCPIP_TIMEOUT +err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg); +err_t tcpip_untimeout(sys_timeout_handler h, void *arg); +#endif /* LWIP_TCPIP_TIMEOUT */ + +enum tcpip_msg_type { +#if LWIP_NETCONN + TCPIP_MSG_API, +#endif /* LWIP_NETCONN */ + TCPIP_MSG_INPKT, +#if LWIP_NETIF_API + TCPIP_MSG_NETIFAPI, +#endif /* LWIP_NETIF_API */ +#if LWIP_TCPIP_TIMEOUT + TCPIP_MSG_TIMEOUT, + TCPIP_MSG_UNTIMEOUT, +#endif /* LWIP_TCPIP_TIMEOUT */ + TCPIP_MSG_CALLBACK +}; + +struct tcpip_msg { + enum tcpip_msg_type type; + sys_sem_t *sem; + union { +#if LWIP_NETCONN + struct api_msg *apimsg; +#endif /* LWIP_NETCONN */ +#if LWIP_NETIF_API + struct netifapi_msg *netifapimsg; +#endif /* LWIP_NETIF_API */ + struct { + struct pbuf *p; + struct netif *netif; + } inp; + struct { + tcpip_callback_fn function; + void *ctx; + } cb; +#if LWIP_TCPIP_TIMEOUT + struct { + u32_t msecs; + sys_timeout_handler h; + void *arg; + } tmo; +#endif /* LWIP_TCPIP_TIMEOUT */ + } msg; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* !NO_SYS */ + +#endif /* __LWIP_TCPIP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/timers.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/timers.h new file mode 100644 index 0000000..fb92b4b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/timers.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * Simon Goldschmidt + * + */ +#ifndef __LWIP_TIMERS_H__ +#define __LWIP_TIMERS_H__ + +#include "lwip/opt.h" + +/* Timers are not supported when NO_SYS==1 and NO_SYS_NO_TIMERS==1 */ +#define LWIP_TIMERS (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS)) + +#if LWIP_TIMERS + +#include "lwip/err.h" +#include "lwip/sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef LWIP_DEBUG_TIMERNAMES +#ifdef LWIP_DEBUG +#define LWIP_DEBUG_TIMERNAMES SYS_DEBUG +#else /* LWIP_DEBUG */ +#define LWIP_DEBUG_TIMERNAMES 0 +#endif /* LWIP_DEBUG*/ +#endif + +/** Function prototype for a timeout callback function. Register such a function + * using sys_timeout(). + * + * @param arg Additional argument to pass to the function - set up by sys_timeout() + */ +typedef void (* sys_timeout_handler)(void *arg); + +struct sys_timeo { + struct sys_timeo *next; + u32_t time; + sys_timeout_handler h; + void *arg; +#if LWIP_DEBUG_TIMERNAMES + const char* handler_name; +#endif /* LWIP_DEBUG_TIMERNAMES */ +}; + +void sys_timeouts_init(void); + +#if LWIP_DEBUG_TIMERNAMES +void sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name); +#define sys_timeout(msecs, handler, arg) sys_timeout_debug(msecs, handler, arg, #handler) +#else /* LWIP_DEBUG_TIMERNAMES */ +void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg); +#endif /* LWIP_DEBUG_TIMERNAMES */ + +void sys_untimeout(sys_timeout_handler handler, void *arg); +#if NO_SYS +void sys_check_timeouts(void); +void sys_restart_timeouts(void); +#else /* NO_SYS */ +void sys_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg); +#endif /* NO_SYS */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TIMERS */ +#endif /* __LWIP_TIMERS_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/udp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/udp.h new file mode 100644 index 0000000..c98c1b3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/lwip/udp.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_UDP_H__ +#define __LWIP_UDP_H__ + +#include "lwip/opt.h" + +#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define UDP_HLEN 8 + +/* Fields are (of course) in network byte order. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct udp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ + PACK_STRUCT_FIELD(u16_t len); + PACK_STRUCT_FIELD(u16_t chksum); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define UDP_FLAGS_NOCHKSUM 0x01U +#define UDP_FLAGS_UDPLITE 0x02U +#define UDP_FLAGS_CONNECTED 0x04U +#define UDP_FLAGS_MULTICAST_LOOP 0x08U + +struct udp_pcb; + +/** Function prototype for udp pcb receive callback functions + * addr and port are in same byte order as in the pcb + * The callback is responsible for freeing the pbuf + * if it's not used any more. + * + * ATTENTION: Be aware that 'addr' points into the pbuf 'p' so freeing this pbuf + * makes 'addr' invalid, too. + * + * @param arg user supplied argument (udp_pcb.recv_arg) + * @param pcb the udp_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @param port the remote port from which the packet was received + */ +typedef void (*udp_recv_fn)(void *arg, struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *addr, u16_t port); + + +struct udp_pcb { +/* Common members of all PCB types */ + IP_PCB; + +/* Protocol specific PCB members */ + + struct udp_pcb *next; + + u8_t flags; + /** ports are in host byte order */ + u16_t local_port, remote_port; + +#if LWIP_IGMP + /** outgoing network interface for multicast packets */ + ip_addr_t multicast_ip; +#endif /* LWIP_IGMP */ + +#if LWIP_UDPLITE + /** used for UDP_LITE only */ + u16_t chksum_len_rx, chksum_len_tx; +#endif /* LWIP_UDPLITE */ + + /** receive callback function */ + udp_recv_fn recv; + /** user-supplied argument for the recv callback */ + void *recv_arg; +}; +/* udp_pcbs export for exernal reference (e.g. SNMP agent) */ +extern struct udp_pcb *udp_pcbs; + +/* The following functions is the application layer interface to the + UDP code. */ +struct udp_pcb * udp_new (void); +void udp_remove (struct udp_pcb *pcb); +err_t udp_bind (struct udp_pcb *pcb, ip_addr_t *ipaddr, + u16_t port); +err_t udp_connect (struct udp_pcb *pcb, ip_addr_t *ipaddr, + u16_t port); +void udp_disconnect (struct udp_pcb *pcb); +void udp_recv (struct udp_pcb *pcb, udp_recv_fn recv, + void *recv_arg); +err_t udp_sendto_if (struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port, + struct netif *netif); +err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port); +err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); + +#if LWIP_CHECKSUM_ON_COPY +err_t udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port, + struct netif *netif, u8_t have_chksum, + u16_t chksum); +err_t udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p, + ip_addr_t *dst_ip, u16_t dst_port, + u8_t have_chksum, u16_t chksum); +err_t udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p, + u8_t have_chksum, u16_t chksum); +#endif /* LWIP_CHECKSUM_ON_COPY */ + +#define udp_flags(pcb) ((pcb)->flags) +#define udp_setflags(pcb, f) ((pcb)->flags = (f)) + +/* The following functions are the lower layer interface to UDP. */ +void udp_input (struct pbuf *p, struct netif *inp); + +#define udp_init() /* Compatibility define, not init needed. */ + +#if UDP_DEBUG +void udp_debug_print(struct udp_hdr *udphdr); +#else +#define udp_debug_print(udphdr) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_UDP */ + +#endif /* __LWIP_UDP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/netif/etharp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/netif/etharp.h new file mode 100644 index 0000000..691575f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/netif/etharp.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __NETIF_ETHARP_H__ +#define __NETIF_ETHARP_H__ + +#include "lwip/opt.h" + +#if LWIP_ARP || LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ETHARP_HWADDR_LEN +#define ETHARP_HWADDR_LEN 6 +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct eth_addr { + PACK_STRUCT_FIELD(u8_t addr[ETHARP_HWADDR_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** Ethernet header */ +struct eth_hdr { +#if ETH_PAD_SIZE + PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]); +#endif + PACK_STRUCT_FIELD(struct eth_addr dest); + PACK_STRUCT_FIELD(struct eth_addr src); + PACK_STRUCT_FIELD(u16_t type); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE) + +#if ETHARP_SUPPORT_VLAN + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** VLAN header inserted between ethernet header and payload + * if 'type' in ethernet header is ETHTYPE_VLAN. + * See IEEE802.Q */ +struct eth_vlan_hdr { + PACK_STRUCT_FIELD(u16_t prio_vid); + PACK_STRUCT_FIELD(u16_t tpid); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_VLAN_HDR 4 +#define VLAN_ID(vlan_hdr) (htons((vlan_hdr)->prio_vid) & 0xFFF) + +#endif /* ETHARP_SUPPORT_VLAN */ + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** the ARP message, see RFC 826 ("Packet format") */ +struct etharp_hdr { + PACK_STRUCT_FIELD(u16_t hwtype); + PACK_STRUCT_FIELD(u16_t proto); + PACK_STRUCT_FIELD(u8_t hwlen); + PACK_STRUCT_FIELD(u8_t protolen); + PACK_STRUCT_FIELD(u16_t opcode); + PACK_STRUCT_FIELD(struct eth_addr shwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 sipaddr); + PACK_STRUCT_FIELD(struct eth_addr dhwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 dipaddr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_ETHARP_HDR 28 +#define SIZEOF_ETHARP_PACKET (SIZEOF_ETH_HDR + SIZEOF_ETHARP_HDR) + +/** 5 seconds period */ +#define ARP_TMR_INTERVAL 5000 + +#define ETHTYPE_ARP 0x0806U +#define ETHTYPE_IP 0x0800U +#define ETHTYPE_VLAN 0x8100U +#define ETHTYPE_PPPOEDISC 0x8863U /* PPP Over Ethernet Discovery Stage */ +#define ETHTYPE_PPPOE 0x8864U /* PPP Over Ethernet Session Stage */ + +/** MEMCPY-like macro to copy to/from struct eth_addr's that are local variables + * or known to be 32-bit aligned within the protocol header. */ +#ifndef ETHADDR32_COPY +#define ETHADDR32_COPY(src, dst) SMEMCPY(src, dst, ETHARP_HWADDR_LEN) +#endif + +/** MEMCPY-like macro to copy to/from struct eth_addr's that are no local + * variables and known to be 16-bit aligned within the protocol header. */ +#ifndef ETHADDR16_COPY +#define ETHADDR16_COPY(src, dst) SMEMCPY(src, dst, ETHARP_HWADDR_LEN) +#endif + +#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */ + +/** ARP message types (opcodes) */ +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +/** Define this to 1 and define LWIP_ARP_FILTER_NETIF_FN(pbuf, netif, type) + * to a filter function that returns the correct netif when using multiple + * netifs on one hardware interface where the netif's low-level receive + * routine cannot decide for the correct netif (e.g. when mapping multiple + * IP addresses to one hardware interface). + */ +#ifndef LWIP_ARP_FILTER_NETIF +#define LWIP_ARP_FILTER_NETIF 0 +#endif + +#if ARP_QUEUEING +/** struct for queueing outgoing packets for unknown address + * defined here to be accessed by memp.h + */ +struct etharp_q_entry { + struct etharp_q_entry *next; + struct pbuf *p; +}; +#endif /* ARP_QUEUEING */ + +#define etharp_init() /* Compatibility define, not init needed. */ +void etharp_tmr(void); +s8_t etharp_find_addr(struct netif *netif, ip_addr_t *ipaddr, + struct eth_addr **eth_ret, ip_addr_t **ip_ret); +err_t etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr); +err_t etharp_query(struct netif *netif, ip_addr_t *ipaddr, struct pbuf *q); +err_t etharp_request(struct netif *netif, ip_addr_t *ipaddr); +/** For Ethernet network interfaces, we might want to send "gratuitous ARP"; + * this is an ARP packet sent by a node in order to spontaneously cause other + * nodes to update an entry in their ARP cache. + * From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */ +#define etharp_gratuitous(netif) etharp_request((netif), &(netif)->ip_addr) + +#if ETHARP_SUPPORT_STATIC_ENTRIES +err_t etharp_add_static_entry(ip_addr_t *ipaddr, struct eth_addr *ethaddr); +err_t etharp_remove_static_entry(ip_addr_t *ipaddr); +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + +#if LWIP_AUTOIP +err_t etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, + const struct eth_addr *ethdst_addr, + const struct eth_addr *hwsrc_addr, const ip_addr_t *ipsrc_addr, + const struct eth_addr *hwdst_addr, const ip_addr_t *ipdst_addr, + const u16_t opcode); +#endif /* LWIP_AUTOIP */ + +#endif /* LWIP_ARP */ + +err_t ethernet_input(struct pbuf *p, struct netif *netif); + +#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETHARP_HWADDR_LEN) == 0) + +extern const struct eth_addr ethbroadcast, ethzero; + +#endif /* LWIP_ARP || LWIP_ETHERNET */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NETIF_ARP_H__ */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/netif/ppp_oe.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/netif/ppp_oe.h new file mode 100644 index 0000000..e1cdfa5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/netif/ppp_oe.h @@ -0,0 +1,190 @@ +/***************************************************************************** +* ppp_oe.h - PPP Over Ethernet implementation for lwIP. +* +* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 06-01-01 Marc Boucher +* Ported to lwIP. +*****************************************************************************/ + + + +/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Martin Husemann . + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef PPP_OE_H +#define PPP_OE_H + +#include "lwip/opt.h" + +#if PPPOE_SUPPORT > 0 + +#include "netif/etharp.h" + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct pppoehdr { + PACK_STRUCT_FIELD(u8_t vertype); + PACK_STRUCT_FIELD(u8_t code); + PACK_STRUCT_FIELD(u16_t session); + PACK_STRUCT_FIELD(u16_t plen); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct pppoetag { + PACK_STRUCT_FIELD(u16_t tag); + PACK_STRUCT_FIELD(u16_t len); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + + +#define PPPOE_STATE_INITIAL 0 +#define PPPOE_STATE_PADI_SENT 1 +#define PPPOE_STATE_PADR_SENT 2 +#define PPPOE_STATE_SESSION 3 +#define PPPOE_STATE_CLOSING 4 +/* passive */ +#define PPPOE_STATE_PADO_SENT 1 + +#define PPPOE_HEADERLEN sizeof(struct pppoehdr) +#define PPPOE_VERTYPE 0x11 /* VER=1, TYPE = 1 */ + +#define PPPOE_TAG_EOL 0x0000 /* end of list */ +#define PPPOE_TAG_SNAME 0x0101 /* service name */ +#define PPPOE_TAG_ACNAME 0x0102 /* access concentrator name */ +#define PPPOE_TAG_HUNIQUE 0x0103 /* host unique */ +#define PPPOE_TAG_ACCOOKIE 0x0104 /* AC cookie */ +#define PPPOE_TAG_VENDOR 0x0105 /* vendor specific */ +#define PPPOE_TAG_RELAYSID 0x0110 /* relay session id */ +#define PPPOE_TAG_SNAME_ERR 0x0201 /* service name error */ +#define PPPOE_TAG_ACSYS_ERR 0x0202 /* AC system error */ +#define PPPOE_TAG_GENERIC_ERR 0x0203 /* gerneric error */ + +#define PPPOE_CODE_PADI 0x09 /* Active Discovery Initiation */ +#define PPPOE_CODE_PADO 0x07 /* Active Discovery Offer */ +#define PPPOE_CODE_PADR 0x19 /* Active Discovery Request */ +#define PPPOE_CODE_PADS 0x65 /* Active Discovery Session confirmation */ +#define PPPOE_CODE_PADT 0xA7 /* Active Discovery Terminate */ + +#ifndef ETHERMTU +#define ETHERMTU 1500 +#endif + +/* two byte PPP protocol discriminator, then IP data */ +#define PPPOE_MAXMTU (ETHERMTU-PPPOE_HEADERLEN-2) + +#ifndef PPPOE_MAX_AC_COOKIE_LEN +#define PPPOE_MAX_AC_COOKIE_LEN 64 +#endif + +struct pppoe_softc { + struct pppoe_softc *next; + struct netif *sc_ethif; /* ethernet interface we are using */ + int sc_pd; /* ppp unit number */ + void (*sc_linkStatusCB)(int pd, int up); + + int sc_state; /* discovery phase or session connected */ + struct eth_addr sc_dest; /* hardware address of concentrator */ + u16_t sc_session; /* PPPoE session id */ + +#ifdef PPPOE_TODO + char *sc_service_name; /* if != NULL: requested name of service */ + char *sc_concentrator_name; /* if != NULL: requested concentrator id */ +#endif /* PPPOE_TODO */ + u8_t sc_ac_cookie[PPPOE_MAX_AC_COOKIE_LEN]; /* content of AC cookie we must echo back */ + size_t sc_ac_cookie_len; /* length of cookie data */ +#ifdef PPPOE_SERVER + u8_t *sc_hunique; /* content of host unique we must echo back */ + size_t sc_hunique_len; /* length of host unique */ +#endif + int sc_padi_retried; /* number of PADI retries already done */ + int sc_padr_retried; /* number of PADR retries already done */ +}; + + +#define pppoe_init() /* compatibility define, no initialization needed */ + +err_t pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr); +err_t pppoe_destroy(struct netif *ifp); + +int pppoe_connect(struct pppoe_softc *sc); +void pppoe_disconnect(struct pppoe_softc *sc); + +void pppoe_disc_input(struct netif *netif, struct pbuf *p); +void pppoe_data_input(struct netif *netif, struct pbuf *p); + +err_t pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb); + +/** used in ppp.c */ +#define PPPOE_HDRLEN (sizeof(struct eth_hdr) + PPPOE_HEADERLEN) + +#endif /* PPPOE_SUPPORT */ + +#endif /* PPP_OE_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/netif/slipif.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/netif/slipif.h new file mode 100644 index 0000000..ccd03c8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/include/netif/slipif.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __NETIF_SLIPIF_H__ +#define __NETIF_SLIPIF_H__ + +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +err_t slipif_init(struct netif * netif); +void slipif_poll(struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/FILES b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/FILES new file mode 100644 index 0000000..099dbf3 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/FILES @@ -0,0 +1,29 @@ +This directory contains generic network interface device drivers that +do not contain any hardware or architecture specific code. The files +are: + +etharp.c + Implements the ARP (Address Resolution Protocol) over + Ethernet. The code in this file should be used together with + Ethernet device drivers. Note that this module has been + largely made Ethernet independent so you should be able to + adapt this for other link layers (such as Firewire). + +ethernetif.c + An example of how an Ethernet device driver could look. This + file can be used as a "skeleton" for developing new Ethernet + network device drivers. It uses the etharp.c ARP code. + +loopif.c + A "loopback" network interface driver. It requires configuration + through the define LWIP_LOOPIF_MULTITHREADING (see opt.h). + +slipif.c + A generic implementation of the SLIP (Serial Line IP) + protocol. It requires a sio (serial I/O) module to work. + +ppp/ Point-to-Point Protocol stack + The PPP stack has been ported from ucip (http://ucip.sourceforge.net). + It matches quite well to pppd 2.3.1 (http://ppp.samba.org), although + compared to that, it has some modifications for embedded systems and + the source code has been reordered a bit. \ No newline at end of file diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/etharp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/etharp.c new file mode 100644 index 0000000..b60dadd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/etharp.c @@ -0,0 +1,1318 @@ +/** + * @file + * Address Resolution Protocol module for IP over Ethernet + * + * Functionally, ARP is divided into two parts. The first maps an IP address + * to a physical address when sending a packet, and the second part answers + * requests from other machines for our physical address. + * + * This implementation complies with RFC 826 (Ethernet ARP). It supports + * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6 + * if an interface calls etharp_gratuitous(our_netif) upon address change. + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/opt.h" + +#if LWIP_ARP || LWIP_ETHERNET + +#include "lwip/ip_addr.h" +#include "lwip/def.h" +#include "lwip/ip.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" +#include "netif/etharp.h" + +#if PPPOE_SUPPORT +#include "netif/ppp_oe.h" +#endif /* PPPOE_SUPPORT */ + +#include + +const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; +const struct eth_addr ethzero = {{0,0,0,0,0,0}}; + +#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */ + +/** the time an ARP entry stays valid after its last update, + * for ARP_TMR_INTERVAL = 5000, this is + * (240 * 5) seconds = 20 minutes. + */ +#define ARP_MAXAGE 240 +/** the time an ARP entry stays pending after first request, + * for ARP_TMR_INTERVAL = 5000, this is + * (2 * 5) seconds = 10 seconds. + * + * @internal Keep this number at least 2, otherwise it might + * run out instantly if the timeout occurs directly after a request. + */ +#define ARP_MAXPENDING 2 + +#define HWTYPE_ETHERNET 1 + +enum etharp_state { + ETHARP_STATE_EMPTY = 0, + ETHARP_STATE_PENDING, + ETHARP_STATE_STABLE +}; + +struct etharp_entry { +#if ARP_QUEUEING + /** Pointer to queue of pending outgoing packets on this ARP entry. */ + struct etharp_q_entry *q; +#else /* ARP_QUEUEING */ + /** Pointer to a single pending outgoing packet on this ARP entry. */ + struct pbuf *q; +#endif /* ARP_QUEUEING */ + ip_addr_t ipaddr; + struct eth_addr ethaddr; +#if LWIP_SNMP + struct netif *netif; +#endif /* LWIP_SNMP */ + u8_t state; + u8_t ctime; +#if ETHARP_SUPPORT_STATIC_ENTRIES + u8_t static_entry; +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ +}; + +static struct etharp_entry arp_table[ARP_TABLE_SIZE]; + +#if !LWIP_NETIF_HWADDRHINT +static u8_t etharp_cached_entry; +#endif /* !LWIP_NETIF_HWADDRHINT */ + +/** Try hard to create a new entry - we want the IP address to appear in + the cache (even if this means removing an active entry or so). */ +#define ETHARP_FLAG_TRY_HARD 1 +#define ETHARP_FLAG_FIND_ONLY 2 +#define ETHARP_FLAG_STATIC_ENTRY 4 + +#if LWIP_NETIF_HWADDRHINT +#define ETHARP_SET_HINT(netif, hint) if (((netif) != NULL) && ((netif)->addr_hint != NULL)) \ + *((netif)->addr_hint) = (hint); +#else /* LWIP_NETIF_HWADDRHINT */ +#define ETHARP_SET_HINT(netif, hint) (etharp_cached_entry = (hint)) +#endif /* LWIP_NETIF_HWADDRHINT */ + +static err_t update_arp_entry(struct netif *netif, ip_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags); + + +/* Some checks, instead of etharp_init(): */ +#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f)) + #error "ARP_TABLE_SIZE must fit in an s8_t, you have to reduce it in your lwipopts.h" +#endif + + +#if ARP_QUEUEING +/** + * Free a complete queue of etharp entries + * + * @param q a qeueue of etharp_q_entry's to free + */ +static void +free_etharp_q(struct etharp_q_entry *q) +{ + struct etharp_q_entry *r; + LWIP_ASSERT("q != NULL", q != NULL); + LWIP_ASSERT("q->p != NULL", q->p != NULL); + while (q) { + r = q; + q = q->next; + LWIP_ASSERT("r->p != NULL", (r->p != NULL)); + pbuf_free(r->p); + memp_free(MEMP_ARP_QUEUE, r); + } +} +#else /* ARP_QUEUEING */ + +/** Compatibility define: free the queued pbuf */ +#define free_etharp_q(q) pbuf_free(q) + +#endif /* ARP_QUEUEING */ + +/** Clean up ARP table entries */ +static void +free_entry(int i) +{ + /* remove from SNMP ARP index tree */ + snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr); + /* and empty packet queue */ + if (arp_table[i].q != NULL) { + /* remove all queued packets */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q))); + free_etharp_q(arp_table[i].q); + arp_table[i].q = NULL; + } + /* recycle entry for re-use */ + arp_table[i].state = ETHARP_STATE_EMPTY; +#if ETHARP_SUPPORT_STATIC_ENTRIES + arp_table[i].static_entry = 0; +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ +#ifdef LWIP_DEBUG + /* for debugging, clean out the complete entry */ + arp_table[i].ctime = 0; +#if LWIP_SNMP + arp_table[i].netif = NULL; +#endif /* LWIP_SNMP */ + ip_addr_set_zero(&arp_table[i].ipaddr); + arp_table[i].ethaddr = ethzero; +#endif /* LWIP_DEBUG */ +} + +/** + * Clears expired entries in the ARP table. + * + * This function should be called every ETHARP_TMR_INTERVAL milliseconds (5 seconds), + * in order to expire entries in the ARP table. + */ +void +etharp_tmr(void) +{ + u8_t i; + + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); + /* remove expired entries from the ARP table */ + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + u8_t state = arp_table[i].state; + if (state != ETHARP_STATE_EMPTY +#if ETHARP_SUPPORT_STATIC_ENTRIES + && (arp_table[i].static_entry == 0) +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + ) { + arp_table[i].ctime++; + if ((arp_table[i].ctime >= ARP_MAXAGE) || + ((arp_table[i].state == ETHARP_STATE_PENDING) && + (arp_table[i].ctime >= ARP_MAXPENDING))) { + /* pending or stable entry has become old! */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %"U16_F".\n", + arp_table[i].state == ETHARP_STATE_STABLE ? "stable" : "pending", (u16_t)i)); + /* clean up entries that have just been expired */ + free_entry(i); + } +#if ARP_QUEUEING + /* still pending entry? (not expired) */ + if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* resend an ARP query here? */ + } +#endif /* ARP_QUEUEING */ + } + } +} + +/** + * Search the ARP table for a matching or new entry. + * + * If an IP address is given, return a pending or stable ARP entry that matches + * the address. If no match is found, create a new entry with this address set, + * but in state ETHARP_EMPTY. The caller must check and possibly change the + * state of the returned entry. + * + * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY. + * + * In all cases, attempt to create new entries from an empty entry. If no + * empty entries are available and ETHARP_FLAG_TRY_HARD flag is set, recycle + * old entries. Heuristic choose the least important entry for recycling. + * + * @param ipaddr IP address to find in ARP cache, or to add if not found. + * @param flags @see definition of ETHARP_FLAG_* + * @param netif netif related to this address (used for NETIF_HWADDRHINT) + * + * @return The ARP entry index that matched or is created, ERR_MEM if no + * entry is found or could be recycled. + */ +static s8_t +find_entry(ip_addr_t *ipaddr, u8_t flags) +{ + s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; + s8_t empty = ARP_TABLE_SIZE; + u8_t i = 0, age_pending = 0, age_stable = 0; + /* oldest entry with packets on queue */ + s8_t old_queue = ARP_TABLE_SIZE; + /* its age */ + u8_t age_queue = 0; + + /** + * a) do a search through the cache, remember candidates + * b) select candidate entry + * c) create new entry + */ + + /* a) in a single search sweep, do all of this + * 1) remember the first empty entry (if any) + * 2) remember the oldest stable entry (if any) + * 3) remember the oldest pending entry without queued packets (if any) + * 4) remember the oldest pending entry with queued packets (if any) + * 5) search for a matching IP entry, either pending or stable + * until 5 matches, or all entries are searched for. + */ + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + u8_t state = arp_table[i].state; + /* no empty entry found yet and now we do find one? */ + if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) { + LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i)); + /* remember first empty entry */ + empty = i; + } else if (state != ETHARP_STATE_EMPTY) { + LWIP_ASSERT("state == ETHARP_STATE_PENDING || state == ETHARP_STATE_STABLE", + state == ETHARP_STATE_PENDING || state == ETHARP_STATE_STABLE); + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching entry %"U16_F"\n", (u16_t)i)); + /* found exact IP address match, simply bail out */ + return i; + } + /* pending entry? */ + if (state == ETHARP_STATE_PENDING) { + /* pending with queued packets? */ + if (arp_table[i].q != NULL) { + if (arp_table[i].ctime >= age_queue) { + old_queue = i; + age_queue = arp_table[i].ctime; + } + } else + /* pending without queued packets? */ + { + if (arp_table[i].ctime >= age_pending) { + old_pending = i; + age_pending = arp_table[i].ctime; + } + } + /* stable entry? */ + } else if (state == ETHARP_STATE_STABLE) { +#if ETHARP_SUPPORT_STATIC_ENTRIES + /* don't record old_stable for static entries since they never expire */ + if (arp_table[i].static_entry == 0) +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + { + /* remember entry with oldest stable entry in oldest, its age in maxtime */ + if (arp_table[i].ctime >= age_stable) { + old_stable = i; + age_stable = arp_table[i].ctime; + } + } + } + } + } + /* { we have no match } => try to create a new entry */ + + /* don't create new entry, only search? */ + if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) || + /* or no empty entry found and not allowed to recycle? */ + ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: no empty entry found and not allowed to recycle\n")); + return (s8_t)ERR_MEM; + } + + /* b) choose the least destructive entry to recycle: + * 1) empty entry + * 2) oldest stable entry + * 3) oldest pending entry without queued packets + * 4) oldest pending entry with queued packets + * + * { ETHARP_FLAG_TRY_HARD is set at this point } + */ + + /* 1) empty entry available? */ + if (empty < ARP_TABLE_SIZE) { + i = empty; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i)); + } else { + /* 2) found recyclable stable entry? */ + if (old_stable < ARP_TABLE_SIZE) { + /* recycle oldest stable*/ + i = old_stable; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i)); + /* no queued packets should exist on stable entries */ + LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL); + /* 3) found recyclable pending entry without queued packets? */ + } else if (old_pending < ARP_TABLE_SIZE) { + /* recycle oldest pending */ + i = old_pending; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i)); + /* 4) found recyclable pending entry with queued packets? */ + } else if (old_queue < ARP_TABLE_SIZE) { + /* recycle oldest pending (queued packets are free in free_entry) */ + i = old_queue; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].q))); + /* no empty or recyclable entries found */ + } else { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: no empty or recyclable entries found\n")); + return (s8_t)ERR_MEM; + } + + /* { empty or recyclable entry found } */ + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + free_entry(i); + } + + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY", + arp_table[i].state == ETHARP_STATE_EMPTY); + + /* IP address given? */ + if (ipaddr != NULL) { + /* set IP address */ + ip_addr_copy(arp_table[i].ipaddr, *ipaddr); + } + arp_table[i].ctime = 0; +#if ETHARP_SUPPORT_STATIC_ENTRIES + arp_table[i].static_entry = 0; +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + return (err_t)i; +} + +/** + * Send an IP packet on the network using netif->linkoutput + * The ethernet header is filled in before sending. + * + * @params netif the lwIP network interface on which to send the packet + * @params p the packet to send, p->payload pointing to the (uninitialized) ethernet header + * @params src the source MAC address to be copied into the ethernet header + * @params dst the destination MAC address to be copied into the ethernet header + * @return ERR_OK if the packet was sent, any other err_t on failure + */ +static err_t +etharp_send_ip(struct netif *netif, struct pbuf *p, struct eth_addr *src, struct eth_addr *dst) +{ + struct eth_hdr *ethhdr = (struct eth_hdr *)p->payload; + + LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!", + (netif->hwaddr_len == ETHARP_HWADDR_LEN)); + ETHADDR32_COPY(ðhdr->dest, dst); + ETHADDR16_COPY(ðhdr->src, src); + ethhdr->type = PP_HTONS(ETHTYPE_IP); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_send_ip: sending packet %p\n", (void *)p)); + /* send the packet */ + return netif->linkoutput(netif, p); +} + +/** + * Update (or insert) a IP/MAC address pair in the ARP cache. + * + * If a pending entry is resolved, any queued packets will be sent + * at this point. + * + * @param netif netif related to this entry (used for NETIF_ADDRHINT) + * @param ipaddr IP address of the inserted ARP entry. + * @param ethaddr Ethernet address of the inserted ARP entry. + * @param flags @see definition of ETHARP_FLAG_* + * + * @return + * - ERR_OK Succesfully updated ARP cache. + * - ERR_MEM If we could not add a new ARP entry when ETHARP_FLAG_TRY_HARD was set. + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + * @see pbuf_free() + */ +static err_t +update_arp_entry(struct netif *netif, ip_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags) +{ + s8_t i; + LWIP_ASSERT("netif->hwaddr_len == ETHARP_HWADDR_LEN", netif->hwaddr_len == ETHARP_HWADDR_LEN); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", + ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr), + ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2], + ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5])); + /* non-unicast address? */ + if (ip_addr_isany(ipaddr) || + ip_addr_isbroadcast(ipaddr, netif) || + ip_addr_ismulticast(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + /* find or create ARP entry */ + i = find_entry(ipaddr, flags); + /* bail out if no entry could be found */ + if (i < 0) { + return (err_t)i; + } + +#if ETHARP_SUPPORT_STATIC_ENTRIES + if (flags & ETHARP_FLAG_STATIC_ENTRY) { + /* record static type */ + arp_table[i].static_entry = 1; + } +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + + /* mark it stable */ + arp_table[i].state = ETHARP_STATE_STABLE; + +#if LWIP_SNMP + /* record network interface */ + arp_table[i].netif = netif; +#endif /* LWIP_SNMP */ + /* insert in SNMP ARP index tree */ + snmp_insert_arpidx_tree(netif, &arp_table[i].ipaddr); + + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i)); + /* update address */ + ETHADDR32_COPY(&arp_table[i].ethaddr, ethaddr); + /* reset time stamp */ + arp_table[i].ctime = 0; + /* this is where we will send out queued packets! */ +#if ARP_QUEUEING + while (arp_table[i].q != NULL) { + struct pbuf *p; + /* remember remainder of queue */ + struct etharp_q_entry *q = arp_table[i].q; + /* pop first item off the queue */ + arp_table[i].q = q->next; + /* get the packet pointer */ + p = q->p; + /* now queue entry can be freed */ + memp_free(MEMP_ARP_QUEUE, q); +#else /* ARP_QUEUEING */ + if (arp_table[i].q != NULL) { + struct pbuf *p = arp_table[i].q; + arp_table[i].q = NULL; +#endif /* ARP_QUEUEING */ + /* send the queued IP packet */ + etharp_send_ip(netif, p, (struct eth_addr*)(netif->hwaddr), ethaddr); + /* free the queued IP packet */ + pbuf_free(p); + } + return ERR_OK; +} + +#if ETHARP_SUPPORT_STATIC_ENTRIES +/** Add a new static entry to the ARP table. If an entry exists for the + * specified IP address, this entry is overwritten. + * If packets are queued for the specified IP address, they are sent out. + * + * @param ipaddr IP address for the new static entry + * @param ethaddr ethernet address for the new static entry + * @return @see return values of etharp_add_static_entry + */ +err_t +etharp_add_static_entry(ip_addr_t *ipaddr, struct eth_addr *ethaddr) +{ + struct netif *netif; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_add_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", + ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr), + ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2], + ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5])); + + netif = ip_route(ipaddr); + if (netif == NULL) { + return ERR_RTE; + } + + return update_arp_entry(netif, ipaddr, ethaddr, ETHARP_FLAG_TRY_HARD | ETHARP_FLAG_STATIC_ENTRY); +} + +/** Remove a static entry from the ARP table previously added with a call to + * etharp_add_static_entry. + * + * @param ipaddr IP address of the static entry to remove + * @return ERR_OK: entry removed + * ERR_MEM: entry wasn't found + * ERR_ARG: entry wasn't a static entry but a dynamic one + */ +err_t +etharp_remove_static_entry(ip_addr_t *ipaddr) +{ + s8_t i; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_remove_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr))); + + /* find or create ARP entry */ + i = find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY); + /* bail out if no entry could be found */ + if (i < 0) { + return (err_t)i; + } + + if ((arp_table[i].state != ETHARP_STATE_STABLE) || + (arp_table[i].static_entry == 0)) { + /* entry wasn't a static entry, cannot remove it */ + return ERR_ARG; + } + /* entry found, free it */ + free_entry(i); + return ERR_OK; +} +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + +/** + * Finds (stable) ethernet/IP address pair from ARP table + * using interface and IP address index. + * @note the addresses in the ARP table are in network order! + * + * @param netif points to interface index + * @param ipaddr points to the (network order) IP address index + * @param eth_ret points to return pointer + * @param ip_ret points to return pointer + * @return table index if found, -1 otherwise + */ +s8_t +etharp_find_addr(struct netif *netif, ip_addr_t *ipaddr, + struct eth_addr **eth_ret, ip_addr_t **ip_ret) +{ + s8_t i; + + LWIP_ASSERT("eth_ret != NULL && ip_ret != NULL", + eth_ret != NULL && ip_ret != NULL); + + LWIP_UNUSED_ARG(netif); + + i = find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY); + if((i >= 0) && arp_table[i].state == ETHARP_STATE_STABLE) { + *eth_ret = &arp_table[i].ethaddr; + *ip_ret = &arp_table[i].ipaddr; + return i; + } + return -1; +} + +#if ETHARP_TRUST_IP_MAC +/** + * Updates the ARP table using the given IP packet. + * + * Uses the incoming IP packet's source address to update the + * ARP cache for the local network. The function does not alter + * or free the packet. This function must be called before the + * packet p is passed to the IP layer. + * + * @param netif The lwIP network interface on which the IP packet pbuf arrived. + * @param p The IP packet that arrived on netif. + * + * @return NULL + * + * @see pbuf_free() + */ +static void +etharp_ip_input(struct netif *netif, struct pbuf *p) +{ + struct eth_hdr *ethhdr; + struct ip_hdr *iphdr; + ip_addr_t iphdr_src; + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + + /* Only insert an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + ethhdr = (struct eth_hdr *)p->payload; + iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR); +#if ETHARP_SUPPORT_VLAN + if (ethhdr->type == PP_HTONS(ETHTYPE_VLAN)) { + iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR); + } +#endif /* ETHARP_SUPPORT_VLAN */ + + ip_addr_copy(iphdr_src, iphdr->src); + + /* source is not on the local network? */ + if (!ip_addr_netcmp(&iphdr_src, &(netif->ip_addr), &(netif->netmask))) { + /* do nothing */ + return; + } + + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n")); + /* update the source IP address in the cache, if present */ + /* @todo We could use ETHARP_FLAG_TRY_HARD if we think we are going to talk + * back soon (for example, if the destination IP address is ours. */ + update_arp_entry(netif, &iphdr_src, &(ethhdr->src), ETHARP_FLAG_FIND_ONLY); +} +#endif /* ETHARP_TRUST_IP_MAC */ + +/** + * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache + * send out queued IP packets. Updates cache with snooped address pairs. + * + * Should be called for incoming ARP packets. The pbuf in the argument + * is freed by this function. + * + * @param netif The lwIP network interface on which the ARP packet pbuf arrived. + * @param ethaddr Ethernet address of netif. + * @param p The ARP packet that arrived on netif. Is freed by this function. + * + * @return NULL + * + * @see pbuf_free() + */ +static void +etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p) +{ + struct etharp_hdr *hdr; + struct eth_hdr *ethhdr; + /* these are aligned properly, whereas the ARP header fields might not be */ + ip_addr_t sipaddr, dipaddr; + u8_t for_us; +#if LWIP_AUTOIP + const u8_t * ethdst_hwaddr; +#endif /* LWIP_AUTOIP */ + + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + + /* drop short ARP packets: we have to check for p->len instead of p->tot_len here + since a struct etharp_hdr is pointed to p->payload, so it musn't be chained! */ + if (p->len < SIZEOF_ETHARP_PACKET) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, + (s16_t)SIZEOF_ETHARP_PACKET)); + ETHARP_STATS_INC(etharp.lenerr); + ETHARP_STATS_INC(etharp.drop); + pbuf_free(p); + return; + } + + ethhdr = (struct eth_hdr *)p->payload; + hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR); +#if ETHARP_SUPPORT_VLAN + if (ethhdr->type == PP_HTONS(ETHTYPE_VLAN)) { + hdr = (struct etharp_hdr *)(((u8_t*)ethhdr) + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR); + } +#endif /* ETHARP_SUPPORT_VLAN */ + + /* RFC 826 "Packet Reception": */ + if ((hdr->hwtype != PP_HTONS(HWTYPE_ETHERNET)) || + (hdr->hwlen != ETHARP_HWADDR_LEN) || + (hdr->protolen != sizeof(ip_addr_t)) || + (hdr->proto != PP_HTONS(ETHTYPE_IP))) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("etharp_arp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n", + hdr->hwtype, hdr->hwlen, hdr->proto, hdr->protolen)); + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + pbuf_free(p); + return; + } + ETHARP_STATS_INC(etharp.recv); + +#if LWIP_AUTOIP + /* We have to check if a host already has configured our random + * created link local address and continously check if there is + * a host with this IP-address so we can detect collisions */ + autoip_arp_reply(netif, hdr); +#endif /* LWIP_AUTOIP */ + + /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without + * structure packing (not using structure copy which breaks strict-aliasing rules). */ + IPADDR2_COPY(&sipaddr, &hdr->sipaddr); + IPADDR2_COPY(&dipaddr, &hdr->dipaddr); + + /* this interface is not configured? */ + if (ip_addr_isany(&netif->ip_addr)) { + for_us = 0; + } else { + /* ARP packet directed to us? */ + for_us = (u8_t)ip_addr_cmp(&dipaddr, &(netif->ip_addr)); + } + + /* ARP message directed to us? + -> add IP address in ARP cache; assume requester wants to talk to us, + can result in directly sending the queued packets for this host. + ARP message not directed to us? + -> update the source IP address in the cache, if present */ + update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), + for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY); + + /* now act on the message itself */ + switch (hdr->opcode) { + /* ARP request? */ + case PP_HTONS(ARP_REQUEST): + /* ARP request. If it asked for our address, we send out a + * reply. In any case, we time-stamp any existing ARP entry, + * and possiby send out an IP packet that was queued on it. */ + + LWIP_DEBUGF (ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP request\n")); + /* ARP request for our address? */ + if (for_us) { + + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n")); + /* Re-use pbuf to send ARP reply. + Since we are re-using an existing pbuf, we can't call etharp_raw since + that would allocate a new pbuf. */ + hdr->opcode = htons(ARP_REPLY); + + IPADDR2_COPY(&hdr->dipaddr, &hdr->sipaddr); + IPADDR2_COPY(&hdr->sipaddr, &netif->ip_addr); + + LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!", + (netif->hwaddr_len == ETHARP_HWADDR_LEN)); +#if LWIP_AUTOIP + /* If we are using Link-Local, all ARP packets that contain a Link-Local + * 'sender IP address' MUST be sent using link-layer broadcast instead of + * link-layer unicast. (See RFC3927 Section 2.5, last paragraph) */ + ethdst_hwaddr = ip_addr_islinklocal(&netif->ip_addr) ? (u8_t*)(ethbroadcast.addr) : hdr->shwaddr.addr; +#endif /* LWIP_AUTOIP */ + + ETHADDR16_COPY(&hdr->dhwaddr, &hdr->shwaddr); +#if LWIP_AUTOIP + ETHADDR16_COPY(ðhdr->dest, ethdst_hwaddr); +#else /* LWIP_AUTOIP */ + ETHADDR16_COPY(ðhdr->dest, &hdr->shwaddr); +#endif /* LWIP_AUTOIP */ + ETHADDR16_COPY(&hdr->shwaddr, ethaddr); + ETHADDR16_COPY(ðhdr->src, ethaddr); + + /* hwtype, hwaddr_len, proto, protolen and the type in the ethernet header + are already correct, we tested that before */ + + /* return ARP reply */ + netif->linkoutput(netif, p); + /* we are not configured? */ + } else if (ip_addr_isany(&netif->ip_addr)) { + /* { for_us == 0 and netif->ip_addr.addr == 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n")); + /* request was not directed to us */ + } else { + /* { for_us == 0 and netif->ip_addr.addr != 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n")); + } + break; + case PP_HTONS(ARP_REPLY): + /* ARP reply. We already updated the ARP cache earlier. */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n")); +#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) + /* DHCP wants to know about ARP replies from any host with an + * IP address also offered to us by the DHCP server. We do not + * want to take a duplicate IP address on a single network. + * @todo How should we handle redundant (fail-over) interfaces? */ + dhcp_arp_reply(netif, &sipaddr); +#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */ + break; + default: + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode))); + ETHARP_STATS_INC(etharp.err); + break; + } + /* free ARP packet */ + pbuf_free(p); +} + +/** + * Resolve and fill-in Ethernet address header for outgoing IP packet. + * + * For IP multicast and broadcast, corresponding Ethernet addresses + * are selected and the packet is transmitted on the link. + * + * For unicast addresses, the packet is submitted to etharp_query(). In + * case the IP address is outside the local network, the IP address of + * the gateway is used. + * + * @param netif The lwIP network interface which the IP packet will be sent on. + * @param q The pbuf(s) containing the IP packet to be sent. + * @param ipaddr The IP address of the packet destination. + * + * @return + * - ERR_RTE No route to destination (no gateway to external networks), + * or the return type of either etharp_query() or etharp_send_ip(). + */ +err_t +etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr) +{ + struct eth_addr *dest, mcastaddr; + + /* make room for Ethernet header - should not fail */ + if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) { + /* bail out */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("etharp_output: could not allocate room for header.\n")); + LINK_STATS_INC(link.lenerr); + return ERR_BUF; + } + + /* assume unresolved Ethernet address */ + dest = NULL; + /* Determine on destination hardware address. Broadcasts and multicasts + * are special, other IP addresses are looked up in the ARP table. */ + + /* broadcast destination IP address? */ + if (ip_addr_isbroadcast(ipaddr, netif)) { + /* broadcast on Ethernet also */ + dest = (struct eth_addr *)ðbroadcast; + /* multicast destination IP address? */ + } else if (ip_addr_ismulticast(ipaddr)) { + /* Hash IP multicast address to MAC address.*/ + mcastaddr.addr[0] = 0x01; + mcastaddr.addr[1] = 0x00; + mcastaddr.addr[2] = 0x5e; + mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; + mcastaddr.addr[4] = ip4_addr3(ipaddr); + mcastaddr.addr[5] = ip4_addr4(ipaddr); + /* destination Ethernet address is multicast */ + dest = &mcastaddr; + /* unicast destination IP address? */ + } else { + /* outside local network? */ + if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask)) && + !ip_addr_islinklocal(ipaddr)) { +#if LWIP_AUTOIP + struct ip_hdr *iphdr = (struct ip_hdr*)((u8_t*)q->payload + + sizeof(struct eth_hdr)); + /* According to RFC 3297, chapter 2.6.2 (Forwarding Rules), a packet with + a link-local source address must always be "directly to its destination + on the same physical link. The host MUST NOT send the packet to any + router for forwarding". */ + if (!ip_addr_islinklocal(&iphdr->src)) +#endif /* LWIP_AUTOIP */ + { + /* interface has default gateway? */ + if (!ip_addr_isany(&netif->gw)) { + /* send to hardware address of default gateway IP address */ + ipaddr = &(netif->gw); + /* no default gateway available */ + } else { + /* no route to destination error (default gateway missing) */ + return ERR_RTE; + } + } + } +#if LWIP_NETIF_HWADDRHINT + if (netif->addr_hint != NULL) { + /* per-pcb cached entry was given */ + u8_t etharp_cached_entry = *(netif->addr_hint); + if (etharp_cached_entry < ARP_TABLE_SIZE) { +#endif /* LWIP_NETIF_HWADDRHINT */ + if ((arp_table[etharp_cached_entry].state == ETHARP_STATE_STABLE) && + (ip_addr_cmp(ipaddr, &arp_table[etharp_cached_entry].ipaddr))) { + /* the per-pcb-cached entry is stable and the right one! */ + ETHARP_STATS_INC(etharp.cachehit); + return etharp_send_ip(netif, q, (struct eth_addr*)(netif->hwaddr), + &arp_table[etharp_cached_entry].ethaddr); + } +#if LWIP_NETIF_HWADDRHINT + } + } +#endif /* LWIP_NETIF_HWADDRHINT */ + /* queue on destination Ethernet address belonging to ipaddr */ + return etharp_query(netif, ipaddr, q); + } + + /* continuation for multicast/broadcast destinations */ + /* obtain source Ethernet address of the given interface */ + /* send packet directly on the link */ + return etharp_send_ip(netif, q, (struct eth_addr*)(netif->hwaddr), dest); +} + +/** + * Send an ARP request for the given IP address and/or queue a packet. + * + * If the IP address was not yet in the cache, a pending ARP cache entry + * is added and an ARP request is sent for the given address. The packet + * is queued on this entry. + * + * If the IP address was already pending in the cache, a new ARP request + * is sent for the given address. The packet is queued on this entry. + * + * If the IP address was already stable in the cache, and a packet is + * given, it is directly sent and no ARP request is sent out. + * + * If the IP address was already stable in the cache, and no packet is + * given, an ARP request is sent out. + * + * @param netif The lwIP network interface on which ipaddr + * must be queried for. + * @param ipaddr The IP address to be resolved. + * @param q If non-NULL, a pbuf that must be delivered to the IP address. + * q is not freed by this function. + * + * @note q must only be ONE packet, not a packet queue! + * + * @return + * - ERR_BUF Could not make room for Ethernet header. + * - ERR_MEM Hardware address unknown, and no more ARP entries available + * to query for address or queue the packet. + * - ERR_MEM Could not queue packet due to memory shortage. + * - ERR_RTE No route to destination (no gateway to external networks). + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + */ +err_t +etharp_query(struct netif *netif, ip_addr_t *ipaddr, struct pbuf *q) +{ + struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; + err_t result = ERR_MEM; + s8_t i; /* ARP entry index */ + + /* non-unicast address? */ + if (ip_addr_isbroadcast(ipaddr, netif) || + ip_addr_ismulticast(ipaddr) || + ip_addr_isany(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + + /* find entry in ARP cache, ask to create entry if queueing packet */ + i = find_entry(ipaddr, ETHARP_FLAG_TRY_HARD); + + /* could not find or create entry? */ + if (i < 0) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n")); + if (q) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n")); + ETHARP_STATS_INC(etharp.memerr); + } + return (err_t)i; + } + + /* mark a fresh entry as pending (we just sent a request) */ + if (arp_table[i].state == ETHARP_STATE_EMPTY) { + arp_table[i].state = ETHARP_STATE_PENDING; + } + + /* { i is either a STABLE or (new or existing) PENDING entry } */ + LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", + ((arp_table[i].state == ETHARP_STATE_PENDING) || + (arp_table[i].state == ETHARP_STATE_STABLE))); + + /* do we have a pending entry? or an implicit query request? */ + if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) { + /* try to resolve it; send out ARP request */ + result = etharp_request(netif, ipaddr); + if (result != ERR_OK) { + /* ARP request couldn't be sent */ + /* We don't re-send arp request in etharp_tmr, but we still queue packets, + since this failure could be temporary, and the next packet calling + etharp_query again could lead to sending the queued packets. */ + } + if (q == NULL) { + return result; + } + } + + /* packet given? */ + LWIP_ASSERT("q != NULL", q != NULL); + /* stable entry? */ + if (arp_table[i].state == ETHARP_STATE_STABLE) { + /* we have a valid IP->Ethernet address mapping */ + ETHARP_SET_HINT(netif, i); + /* send the packet */ + result = etharp_send_ip(netif, q, srcaddr, &(arp_table[i].ethaddr)); + /* pending entry? (either just created or already pending */ + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* entry is still pending, queue the given packet 'q' */ + struct pbuf *p; + int copy_needed = 0; + /* IF q includes a PBUF_REF, PBUF_POOL or PBUF_RAM, we have no choice but + * to copy the whole queue into a new PBUF_RAM (see bug #11400) + * PBUF_ROMs can be left as they are, since ROM must not get changed. */ + p = q; + while (p) { + LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0)); + if(p->type != PBUF_ROM) { + copy_needed = 1; + break; + } + p = p->next; + } + if(copy_needed) { + /* copy the whole packet into new pbufs */ + p = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if(p != NULL) { + if (pbuf_copy(p, q) != ERR_OK) { + pbuf_free(p); + p = NULL; + } + } + } else { + /* referencing the old pbuf is enough */ + p = q; + pbuf_ref(p); + } + /* packet could be taken over? */ + if (p != NULL) { + /* queue packet ... */ +#if ARP_QUEUEING + struct etharp_q_entry *new_entry; + /* allocate a new arp queue entry */ + new_entry = (struct etharp_q_entry *)memp_malloc(MEMP_ARP_QUEUE); + if (new_entry != NULL) { + new_entry->next = 0; + new_entry->p = p; + if(arp_table[i].q != NULL) { + /* queue was already existent, append the new entry to the end */ + struct etharp_q_entry *r; + r = arp_table[i].q; + while (r->next != NULL) { + r = r->next; + } + r->next = new_entry; + } else { + /* queue did not exist, first item in queue */ + arp_table[i].q = new_entry; + } + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); + result = ERR_OK; + } else { + /* the pool MEMP_ARP_QUEUE is empty */ + pbuf_free(p); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + result = ERR_MEM; + } +#else /* ARP_QUEUEING */ + /* always queue one packet per ARP request only, freeing a previously queued packet */ + if (arp_table[i].q != NULL) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); + pbuf_free(arp_table[i].q); + } + arp_table[i].q = p; + result = ERR_OK; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); +#endif /* ARP_QUEUEING */ + } else { + ETHARP_STATS_INC(etharp.memerr); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + result = ERR_MEM; + } + } + return result; +} + +/** + * Send a raw ARP packet (opcode and all addresses can be modified) + * + * @param netif the lwip network interface on which to send the ARP packet + * @param ethsrc_addr the source MAC address for the ethernet header + * @param ethdst_addr the destination MAC address for the ethernet header + * @param hwsrc_addr the source MAC address for the ARP protocol header + * @param ipsrc_addr the source IP address for the ARP protocol header + * @param hwdst_addr the destination MAC address for the ARP protocol header + * @param ipdst_addr the destination IP address for the ARP protocol header + * @param opcode the type of the ARP packet + * @return ERR_OK if the ARP packet has been sent + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +#if !LWIP_AUTOIP +static +#endif /* LWIP_AUTOIP */ +err_t +etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, + const struct eth_addr *ethdst_addr, + const struct eth_addr *hwsrc_addr, const ip_addr_t *ipsrc_addr, + const struct eth_addr *hwdst_addr, const ip_addr_t *ipdst_addr, + const u16_t opcode) +{ + struct pbuf *p; + err_t result = ERR_OK; + struct eth_hdr *ethhdr; + struct etharp_hdr *hdr; +#if LWIP_AUTOIP + const u8_t * ethdst_hwaddr; +#endif /* LWIP_AUTOIP */ + + /* allocate a pbuf for the outgoing ARP request packet */ + p = pbuf_alloc(PBUF_RAW, SIZEOF_ETHARP_PACKET, PBUF_RAM); + /* could allocate a pbuf for an ARP request? */ + if (p == NULL) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("etharp_raw: could not allocate pbuf for ARP request.\n")); + ETHARP_STATS_INC(etharp.memerr); + return ERR_MEM; + } + LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr", + (p->len >= SIZEOF_ETHARP_PACKET)); + + ethhdr = (struct eth_hdr *)p->payload; + hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n")); + hdr->opcode = htons(opcode); + + LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!", + (netif->hwaddr_len == ETHARP_HWADDR_LEN)); +#if LWIP_AUTOIP + /* If we are using Link-Local, all ARP packets that contain a Link-Local + * 'sender IP address' MUST be sent using link-layer broadcast instead of + * link-layer unicast. (See RFC3927 Section 2.5, last paragraph) */ + ethdst_hwaddr = ip_addr_islinklocal(ipsrc_addr) ? (u8_t*)(ethbroadcast.addr) : ethdst_addr->addr; +#endif /* LWIP_AUTOIP */ + /* Write the ARP MAC-Addresses */ + ETHADDR16_COPY(&hdr->shwaddr, hwsrc_addr); + ETHADDR16_COPY(&hdr->dhwaddr, hwdst_addr); + /* Write the Ethernet MAC-Addresses */ +#if LWIP_AUTOIP + ETHADDR16_COPY(ðhdr->dest, ethdst_hwaddr); +#else /* LWIP_AUTOIP */ + ETHADDR16_COPY(ðhdr->dest, ethdst_addr); +#endif /* LWIP_AUTOIP */ + ETHADDR16_COPY(ðhdr->src, ethsrc_addr); + /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without + * structure packing. */ + IPADDR2_COPY(&hdr->sipaddr, ipsrc_addr); + IPADDR2_COPY(&hdr->dipaddr, ipdst_addr); + + hdr->hwtype = PP_HTONS(HWTYPE_ETHERNET); + hdr->proto = PP_HTONS(ETHTYPE_IP); + /* set hwlen and protolen */ + hdr->hwlen = ETHARP_HWADDR_LEN; + hdr->protolen = sizeof(ip_addr_t); + + ethhdr->type = PP_HTONS(ETHTYPE_ARP); + /* send ARP query */ + result = netif->linkoutput(netif, p); + ETHARP_STATS_INC(etharp.xmit); + /* free ARP query packet */ + pbuf_free(p); + p = NULL; + /* could not allocate pbuf for ARP request */ + + return result; +} + +/** + * Send an ARP request packet asking for ipaddr. + * + * @param netif the lwip network interface on which to send the request + * @param ipaddr the IP address for which to ask + * @return ERR_OK if the request has been sent + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +err_t +etharp_request(struct netif *netif, ip_addr_t *ipaddr) +{ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n")); + return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast, + (struct eth_addr *)netif->hwaddr, &netif->ip_addr, ðzero, + ipaddr, ARP_REQUEST); +} +#endif /* LWIP_ARP */ + +/** + * Process received ethernet frames. Using this function instead of directly + * calling ip_input and passing ARP frames through etharp in ethernetif_input, + * the ARP cache is protected from concurrent access. + * + * @param p the recevied packet, p->payload pointing to the ethernet header + * @param netif the network interface on which the packet was received + */ +err_t +ethernet_input(struct pbuf *p, struct netif *netif) +{ + struct eth_hdr* ethhdr; + u16_t type; + s16_t ip_hdr_offset = SIZEOF_ETH_HDR; + + if (p->len <= SIZEOF_ETH_HDR) { + /* a packet with only an ethernet header (or less) is not valid for us */ + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + goto free_and_return; + } + + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = (struct eth_hdr *)p->payload; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, + ("ethernet_input: dest:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", src:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", type:%"X16_F"\n", + (unsigned)ethhdr->dest.addr[0], (unsigned)ethhdr->dest.addr[1], (unsigned)ethhdr->dest.addr[2], + (unsigned)ethhdr->dest.addr[3], (unsigned)ethhdr->dest.addr[4], (unsigned)ethhdr->dest.addr[5], + (unsigned)ethhdr->src.addr[0], (unsigned)ethhdr->src.addr[1], (unsigned)ethhdr->src.addr[2], + (unsigned)ethhdr->src.addr[3], (unsigned)ethhdr->src.addr[4], (unsigned)ethhdr->src.addr[5], + (unsigned)htons(ethhdr->type))); + + type = ethhdr->type; +#if ETHARP_SUPPORT_VLAN + if (type == PP_HTONS(ETHTYPE_VLAN)) { + struct eth_vlan_hdr *vlan = (struct eth_vlan_hdr*)(((char*)ethhdr) + SIZEOF_ETH_HDR); + if (p->len <= SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR) { + /* a packet with only an ethernet/vlan header (or less) is not valid for us */ + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + goto free_and_return; + } +#ifdef ETHARP_VLAN_CHECK /* if not, allow all VLANs */ + if (VLAN_ID(vlan) != ETHARP_VLAN_CHECK) { + /* silently ignore this packet: not for our VLAN */ + pbuf_free(p); + return ERR_OK; + } +#endif /* ETHARP_VLAN_CHECK */ + type = vlan->tpid; + ip_hdr_offset = SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR; + } +#endif /* ETHARP_SUPPORT_VLAN */ + +#if LWIP_ARP_FILTER_NETIF + netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, htons(type)); +#endif /* LWIP_ARP_FILTER_NETIF*/ + + switch (type) { +#if LWIP_ARP + /* IP packet? */ + case PP_HTONS(ETHTYPE_IP): + if (!(netif->flags & NETIF_FLAG_ETHARP)) { + goto free_and_return; + } +#if ETHARP_TRUST_IP_MAC + /* update ARP table */ + etharp_ip_input(netif, p); +#endif /* ETHARP_TRUST_IP_MAC */ + /* skip Ethernet header */ + if(pbuf_header(p, -ip_hdr_offset)) { + LWIP_ASSERT("Can't move over header in packet", 0); + goto free_and_return; + } else { + /* pass to IP layer */ + ip_input(p, netif); + } + break; + + case PP_HTONS(ETHTYPE_ARP): + if (!(netif->flags & NETIF_FLAG_ETHARP)) { + goto free_and_return; + } + /* pass p to ARP module */ + etharp_arp_input(netif, (struct eth_addr*)(netif->hwaddr), p); + break; +#endif /* LWIP_ARP */ +#if PPPOE_SUPPORT + case PP_HTONS(ETHTYPE_PPPOEDISC): /* PPP Over Ethernet Discovery Stage */ + pppoe_disc_input(netif, p); + break; + + case PP_HTONS(ETHTYPE_PPPOE): /* PPP Over Ethernet Session Stage */ + pppoe_data_input(netif, p); + break; +#endif /* PPPOE_SUPPORT */ + + default: + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + goto free_and_return; + } + + /* This means the pbuf is freed or consumed, + so the caller doesn't have to free it again */ + return ERR_OK; + +free_and_return: + pbuf_free(p); + return ERR_OK; +} +#endif /* LWIP_ARP || LWIP_ETHERNET */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ethernetif.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ethernetif.c new file mode 100644 index 0000000..a5b7d99 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ethernetif.c @@ -0,0 +1,318 @@ +/** + * @file + * Ethernet Interface Skeleton + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * This file is a skeleton for developing Ethernet network interface + * drivers for lwIP. Add code to the low_level functions and do a + * search-and-replace for the word "ethernetif" to replace it with + * something that better describes your network interface. + */ + +#include "lwip/opt.h" + +#if 0 /* don't build, this is only a skeleton, see previous comment */ + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include +#include +#include "netif/etharp.h" +#include "netif/ppp_oe.h" + +/* Define those to better describe your network interface. */ +#define IFNAME0 'e' +#define IFNAME1 'n' + +/** + * Helper struct to hold private data used to operate your ethernet interface. + * Keeping the ethernet address of the MAC in this struct is not necessary + * as it is already kept in the struct netif. + * But this is only an example, anyway... + */ +struct ethernetif { + struct eth_addr *ethaddr; + /* Add whatever per-interface state that is needed here. */ +}; + +/* Forward declarations. */ +static void ethernetif_input(struct netif *netif); + +/** + * In this function, the hardware should be initialized. + * Called from ethernetif_init(). + * + * @param netif the already initialized lwip network interface structure + * for this ethernetif + */ +static void +low_level_init(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + + /* set MAC hardware address length */ + netif->hwaddr_len = ETHARP_HWADDR_LEN; + + /* set MAC hardware address */ + netif->hwaddr[0] = ; + ... + netif->hwaddr[5] = ; + + /* maximum transfer unit */ + netif->mtu = 1500; + + /* device capabilities */ + /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + + /* Do whatever else is needed to initialize interface. */ +} + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + * @param netif the lwip network interface structure for this ethernetif + * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) + * @return ERR_OK if the packet could be sent + * an err_t value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become availale since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ + +static err_t +low_level_output(struct netif *netif, struct pbuf *p) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *q; + + initiate transfer(); + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + for(q = p; q != NULL; q = q->next) { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + send data from(q->payload, q->len); + } + + signal that packet should be sent(); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.xmit); + + return ERR_OK; +} + +/** + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + * @param netif the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +static struct pbuf * +low_level_input(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *p, *q; + u16_t len; + + /* Obtain the size of the packet and put it into the "len" + variable. */ + len = ; + +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (p != NULL) { + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + for(q = p; q != NULL; q = q->next) { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. + * This does not necessarily have to be a memcpy, you can also preallocate + * pbufs for a DMA-enabled MAC and after receiving truncate it to the + * actually received size. In this case, ensure the tot_len member of the + * pbuf is the sum of the chained pbuf len members. + */ + read data into(q->payload, q->len); + } + acknowledge that packet has been read(); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.recv); + } else { + drop packet(); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + } + + return p; +} + +/** + * This function should be called when a packet is ready to be read + * from the interface. It uses the function low_level_input() that + * should handle the actual reception of bytes from the network + * interface. Then the type of the received packet is determined and + * the appropriate input function is called. + * + * @param netif the lwip network interface structure for this ethernetif + */ +static void +ethernetif_input(struct netif *netif) +{ + struct ethernetif *ethernetif; + struct eth_hdr *ethhdr; + struct pbuf *p; + + ethernetif = netif->state; + + /* move received packet into a new pbuf */ + p = low_level_input(netif); + /* no packet could be read, silently ignore this */ + if (p == NULL) return; + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = p->payload; + + switch (htons(ethhdr->type)) { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: +#if PPPOE_SUPPORT + /* PPPoE packet? */ + case ETHTYPE_PPPOEDISC: + case ETHTYPE_PPPOE: +#endif /* PPPOE_SUPPORT */ + /* full packet send to tcpip_thread to process */ + if (netif->input(p, netif)!=ERR_OK) + { LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); + pbuf_free(p); + p = NULL; + } + break; + + default: + pbuf_free(p); + p = NULL; + break; + } +} + +/** + * Should be called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netif_add(). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t +ethernetif_init(struct netif *netif) +{ + struct ethernetif *ethernetif; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + ethernetif = mem_malloc(sizeof(struct ethernetif)); + if (ethernetif == NULL) { + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); + return ERR_MEM; + } + +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + netif->hostname = "lwip"; +#endif /* LWIP_NETIF_HOSTNAME */ + + /* + * Initialize the snmp variables and counters inside the struct netif. + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS); + + netif->state = ethernetif; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ + netif->output = etharp_output; + netif->linkoutput = low_level_output; + + ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); + + /* initialize the hardware */ + low_level_init(netif); + + return ERR_OK; +} + +#endif /* 0 */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.c new file mode 100644 index 0000000..c3c49d2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.c @@ -0,0 +1,1334 @@ +/***************************************************************************** +* auth.c - Network Authentication and Phase Control program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-08 Guy Lancaster , Global Election Systems Inc. +* Ported from public pppd code. +*****************************************************************************/ +/* + * auth.c - PPP authentication and phase control. + * + * Copyright (c) 1993 The Australian National University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the Australian National University. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "ppp.h" +#include "pppdebug.h" + +#include "fsm.h" +#include "lcp.h" +#include "pap.h" +#include "chap.h" +#include "auth.h" +#include "ipcp.h" + +#if CBCP_SUPPORT +#include "cbcp.h" +#endif /* CBCP_SUPPORT */ + +#include "lwip/inet.h" + +#include + +#if 0 /* UNUSED */ +/* Bits in scan_authfile return value */ +#define NONWILD_SERVER 1 +#define NONWILD_CLIENT 2 + +#define ISWILD(word) (word[0] == '*' && word[1] == 0) +#endif /* UNUSED */ + +#if PAP_SUPPORT || CHAP_SUPPORT +/* The name by which the peer authenticated itself to us. */ +static char peer_authname[MAXNAMELEN]; +#endif /* PAP_SUPPORT || CHAP_SUPPORT */ + +/* Records which authentication operations haven't completed yet. */ +static int auth_pending[NUM_PPP]; + +/* Set if we have successfully called plogin() */ +static int logged_in; + +/* Set if we have run the /etc/ppp/auth-up script. */ +static int did_authup; /* @todo, we don't need this in lwip*/ + +/* List of addresses which the peer may use. */ +static struct wordlist *addresses[NUM_PPP]; + +#if 0 /* UNUSED */ +/* Wordlist giving addresses which the peer may use + without authenticating itself. */ +static struct wordlist *noauth_addrs; + +/* Extra options to apply, from the secrets file entry for the peer. */ +static struct wordlist *extra_options; +#endif /* UNUSED */ + +/* Number of network protocols which we have opened. */ +static int num_np_open; + +/* Number of network protocols which have come up. */ +static int num_np_up; + +#if PAP_SUPPORT || CHAP_SUPPORT +/* Set if we got the contents of passwd[] from the pap-secrets file. */ +static int passwd_from_file; +#endif /* PAP_SUPPORT || CHAP_SUPPORT */ + +#if 0 /* UNUSED */ +/* Set if we require authentication only because we have a default route. */ +static bool default_auth; + +/* Hook to enable a plugin to control the idle time limit */ +int (*idle_time_hook) __P((struct ppp_idle *)) = NULL; + +/* Hook for a plugin to say whether we can possibly authenticate any peer */ +int (*pap_check_hook) __P((void)) = NULL; + +/* Hook for a plugin to check the PAP user and password */ +int (*pap_auth_hook) __P((char *user, char *passwd, char **msgp, + struct wordlist **paddrs, + struct wordlist **popts)) = NULL; + +/* Hook for a plugin to know about the PAP user logout */ +void (*pap_logout_hook) __P((void)) = NULL; + +/* Hook for a plugin to get the PAP password for authenticating us */ +int (*pap_passwd_hook) __P((char *user, char *passwd)) = NULL; + +/* + * This is used to ensure that we don't start an auth-up/down + * script while one is already running. + */ +enum script_state { + s_down, + s_up +}; + +static enum script_state auth_state = s_down; +static enum script_state auth_script_state = s_down; +static pid_t auth_script_pid = 0; + +/* + * Option variables. + * lwip: some of these are present in the ppp_settings structure + */ +bool uselogin = 0; /* Use /etc/passwd for checking PAP */ +bool cryptpap = 0; /* Passwords in pap-secrets are encrypted */ +bool refuse_pap = 0; /* Don't wanna auth. ourselves with PAP */ +bool refuse_chap = 0; /* Don't wanna auth. ourselves with CHAP */ +bool usehostname = 0; /* Use hostname for our_name */ +bool auth_required = 0; /* Always require authentication from peer */ +bool allow_any_ip = 0; /* Allow peer to use any IP address */ +bool explicit_remote = 0; /* User specified explicit remote name */ +char remote_name[MAXNAMELEN]; /* Peer's name for authentication */ + +#endif /* UNUSED */ + +/* Bits in auth_pending[] */ +#define PAP_WITHPEER 1 +#define PAP_PEER 2 +#define CHAP_WITHPEER 4 +#define CHAP_PEER 8 + +/* @todo, move this somewhere */ +/* Used for storing a sequence of words. Usually malloced. */ +struct wordlist { + struct wordlist *next; + char word[1]; +}; + + +extern char *crypt (const char *, const char *); + +/* Prototypes for procedures local to this file. */ + +static void network_phase (int); +static void check_idle (void *); +static void connect_time_expired (void *); +#if 0 +static int plogin (char *, char *, char **, int *); +#endif +static void plogout (void); +static int null_login (int); +static int get_pap_passwd (int, char *, char *); +static int have_pap_secret (void); +static int have_chap_secret (char *, char *, u32_t); +static int ip_addr_check (u32_t, struct wordlist *); + +#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */ +static int scan_authfile (FILE *, char *, char *, char *, + struct wordlist **, struct wordlist **, + char *); +static void free_wordlist (struct wordlist *); +static void auth_script (char *); +static void auth_script_done (void *); +static void set_allowed_addrs (int unit, struct wordlist *addrs); +static int some_ip_ok (struct wordlist *); +static int setupapfile (char **); +static int privgroup (char **); +static int set_noauth_addr (char **); +static void check_access (FILE *, char *); +#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */ + +#if 0 /* UNUSED */ +/* + * Authentication-related options. + */ +option_t auth_options[] = { + { "require-pap", o_bool, &lcp_wantoptions[0].neg_upap, + "Require PAP authentication from peer", 1, &auth_required }, + { "+pap", o_bool, &lcp_wantoptions[0].neg_upap, + "Require PAP authentication from peer", 1, &auth_required }, + { "refuse-pap", o_bool, &refuse_pap, + "Don't agree to auth to peer with PAP", 1 }, + { "-pap", o_bool, &refuse_pap, + "Don't allow PAP authentication with peer", 1 }, + { "require-chap", o_bool, &lcp_wantoptions[0].neg_chap, + "Require CHAP authentication from peer", 1, &auth_required }, + { "+chap", o_bool, &lcp_wantoptions[0].neg_chap, + "Require CHAP authentication from peer", 1, &auth_required }, + { "refuse-chap", o_bool, &refuse_chap, + "Don't agree to auth to peer with CHAP", 1 }, + { "-chap", o_bool, &refuse_chap, + "Don't allow CHAP authentication with peer", 1 }, + { "name", o_string, our_name, + "Set local name for authentication", + OPT_PRIV|OPT_STATIC, NULL, MAXNAMELEN }, + { "user", o_string, user, + "Set name for auth with peer", OPT_STATIC, NULL, MAXNAMELEN }, + { "usehostname", o_bool, &usehostname, + "Must use hostname for authentication", 1 }, + { "remotename", o_string, remote_name, + "Set remote name for authentication", OPT_STATIC, + &explicit_remote, MAXNAMELEN }, + { "auth", o_bool, &auth_required, + "Require authentication from peer", 1 }, + { "noauth", o_bool, &auth_required, + "Don't require peer to authenticate", OPT_PRIV, &allow_any_ip }, + { "login", o_bool, &uselogin, + "Use system password database for PAP", 1 }, + { "papcrypt", o_bool, &cryptpap, + "PAP passwords are encrypted", 1 }, + { "+ua", o_special, (void *)setupapfile, + "Get PAP user and password from file" }, + { "password", o_string, passwd, + "Password for authenticating us to the peer", OPT_STATIC, + NULL, MAXSECRETLEN }, + { "privgroup", o_special, (void *)privgroup, + "Allow group members to use privileged options", OPT_PRIV }, + { "allow-ip", o_special, (void *)set_noauth_addr, + "Set IP address(es) which can be used without authentication", + OPT_PRIV }, + { NULL } +}; +#endif /* UNUSED */ +#if 0 /* UNUSED */ +/* + * setupapfile - specifies UPAP info for authenticating with peer. + */ +static int +setupapfile(char **argv) +{ + FILE * ufile; + int l; + + lcp_allowoptions[0].neg_upap = 1; + + /* open user info file */ + seteuid(getuid()); + ufile = fopen(*argv, "r"); + seteuid(0); + if (ufile == NULL) { + option_error("unable to open user login data file %s", *argv); + return 0; + } + check_access(ufile, *argv); + + /* get username */ + if (fgets(user, MAXNAMELEN - 1, ufile) == NULL + || fgets(passwd, MAXSECRETLEN - 1, ufile) == NULL){ + option_error("unable to read user login data file %s", *argv); + return 0; + } + fclose(ufile); + + /* get rid of newlines */ + l = strlen(user); + if (l > 0 && user[l-1] == '\n') + user[l-1] = 0; + l = strlen(passwd); + if (l > 0 && passwd[l-1] == '\n') + passwd[l-1] = 0; + + return (1); +} +#endif /* UNUSED */ + +#if 0 /* UNUSED */ +/* + * privgroup - allow members of the group to have privileged access. + */ +static int +privgroup(char **argv) +{ + struct group *g; + int i; + + g = getgrnam(*argv); + if (g == 0) { + option_error("group %s is unknown", *argv); + return 0; + } + for (i = 0; i < ngroups; ++i) { + if (groups[i] == g->gr_gid) { + privileged = 1; + break; + } + } + return 1; +} +#endif + +#if 0 /* UNUSED */ +/* + * set_noauth_addr - set address(es) that can be used without authentication. + * Equivalent to specifying an entry like `"" * "" addr' in pap-secrets. + */ +static int +set_noauth_addr(char **argv) +{ + char *addr = *argv; + int l = strlen(addr); + struct wordlist *wp; + + wp = (struct wordlist *) malloc(sizeof(struct wordlist) + l + 1); + if (wp == NULL) + novm("allow-ip argument"); + wp->word = (char *) (wp + 1); + wp->next = noauth_addrs; + BCOPY(addr, wp->word, l); + noauth_addrs = wp; + return 1; +} +#endif /* UNUSED */ + +/* + * An Open on LCP has requested a change from Dead to Establish phase. + * Do what's necessary to bring the physical layer up. + */ +void +link_required(int unit) +{ + LWIP_UNUSED_ARG(unit); + + AUTHDEBUG(LOG_INFO, ("link_required: %d\n", unit)); +} + +/* + * LCP has terminated the link; go to the Dead phase and take the + * physical layer down. + */ +void +link_terminated(int unit) +{ + AUTHDEBUG(LOG_INFO, ("link_terminated: %d\n", unit)); + if (lcp_phase[unit] == PHASE_DEAD) { + return; + } + if (logged_in) { + plogout(); + } + lcp_phase[unit] = PHASE_DEAD; + AUTHDEBUG(LOG_NOTICE, ("Connection terminated.\n")); + pppLinkTerminated(unit); +} + +/* + * LCP has gone down; it will either die or try to re-establish. + */ +void +link_down(int unit) +{ + int i; + struct protent *protp; + + AUTHDEBUG(LOG_INFO, ("link_down: %d\n", unit)); + + if (did_authup) { + /* XXX Do link down processing. */ + did_authup = 0; + } + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { + if (!protp->enabled_flag) { + continue; + } + if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) { + (*protp->lowerdown)(unit); + } + if (protp->protocol < 0xC000 && protp->close != NULL) { + (*protp->close)(unit, "LCP down"); + } + } + num_np_open = 0; /* number of network protocols we have opened */ + num_np_up = 0; /* Number of network protocols which have come up */ + + if (lcp_phase[unit] != PHASE_DEAD) { + lcp_phase[unit] = PHASE_TERMINATE; + } + pppLinkDown(unit); +} + +/* + * The link is established. + * Proceed to the Dead, Authenticate or Network phase as appropriate. + */ +void +link_established(int unit) +{ + int auth; + int i; + struct protent *protp; + lcp_options *wo = &lcp_wantoptions[unit]; + lcp_options *go = &lcp_gotoptions[unit]; +#if PAP_SUPPORT || CHAP_SUPPORT + lcp_options *ho = &lcp_hisoptions[unit]; +#endif /* PAP_SUPPORT || CHAP_SUPPORT */ + + AUTHDEBUG(LOG_INFO, ("link_established: unit %d; Lowering up all protocols...\n", unit)); + /* + * Tell higher-level protocols that LCP is up. + */ + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { + if (protp->protocol != PPP_LCP && protp->enabled_flag && protp->lowerup != NULL) { + (*protp->lowerup)(unit); + } + } + if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) { + /* + * We wanted the peer to authenticate itself, and it refused: + * treat it as though it authenticated with PAP using a username + * of "" and a password of "". If that's not OK, boot it out. + */ + if (!wo->neg_upap || !null_login(unit)) { + AUTHDEBUG(LOG_WARNING, ("peer refused to authenticate\n")); + lcp_close(unit, "peer refused to authenticate"); + return; + } + } + + lcp_phase[unit] = PHASE_AUTHENTICATE; + auth = 0; +#if CHAP_SUPPORT + if (go->neg_chap) { + ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype); + auth |= CHAP_PEER; + } +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT && CHAP_SUPPORT + else +#endif /* PAP_SUPPORT && CHAP_SUPPORT */ +#if PAP_SUPPORT + if (go->neg_upap) { + upap_authpeer(unit); + auth |= PAP_PEER; + } +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + if (ho->neg_chap) { + ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype); + auth |= CHAP_WITHPEER; + } +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT && CHAP_SUPPORT + else +#endif /* PAP_SUPPORT && CHAP_SUPPORT */ +#if PAP_SUPPORT + if (ho->neg_upap) { + if (ppp_settings.passwd[0] == 0) { + passwd_from_file = 1; + if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd)) { + AUTHDEBUG(LOG_ERR, ("No secret found for PAP login\n")); + } + } + upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd); + auth |= PAP_WITHPEER; + } +#endif /* PAP_SUPPORT */ + auth_pending[unit] = auth; + + if (!auth) { + network_phase(unit); + } +} + +/* + * Proceed to the network phase. + */ +static void +network_phase(int unit) +{ + int i; + struct protent *protp; + lcp_options *go = &lcp_gotoptions[unit]; + + /* + * If the peer had to authenticate, run the auth-up script now. + */ + if ((go->neg_chap || go->neg_upap) && !did_authup) { + /* XXX Do setup for peer authentication. */ + did_authup = 1; + } + +#if CBCP_SUPPORT + /* + * If we negotiated callback, do it now. + */ + if (go->neg_cbcp) { + lcp_phase[unit] = PHASE_CALLBACK; + (*cbcp_protent.open)(unit); + return; + } +#endif /* CBCP_SUPPORT */ + + lcp_phase[unit] = PHASE_NETWORK; + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { + if (protp->protocol < 0xC000 && protp->enabled_flag && protp->open != NULL) { + (*protp->open)(unit); + if (protp->protocol != PPP_CCP) { + ++num_np_open; + } + } + } + + if (num_np_open == 0) { + /* nothing to do */ + lcp_close(0, "No network protocols running"); + } +} +/* @todo: add void start_networks(void) here (pppd 2.3.11) */ + +/* + * The peer has failed to authenticate himself using `protocol'. + */ +void +auth_peer_fail(int unit, u16_t protocol) +{ + LWIP_UNUSED_ARG(protocol); + + AUTHDEBUG(LOG_INFO, ("auth_peer_fail: %d proto=%X\n", unit, protocol)); + /* + * Authentication failure: take the link down + */ + lcp_close(unit, "Authentication failed"); +} + + +#if PAP_SUPPORT || CHAP_SUPPORT +/* + * The peer has been successfully authenticated using `protocol'. + */ +void +auth_peer_success(int unit, u16_t protocol, char *name, int namelen) +{ + int pbit; + + AUTHDEBUG(LOG_INFO, ("auth_peer_success: %d proto=%X\n", unit, protocol)); + switch (protocol) { + case PPP_CHAP: + pbit = CHAP_PEER; + break; + case PPP_PAP: + pbit = PAP_PEER; + break; + default: + AUTHDEBUG(LOG_WARNING, ("auth_peer_success: unknown protocol %x\n", protocol)); + return; + } + + /* + * Save the authenticated name of the peer for later. + */ + if (namelen > (int)sizeof(peer_authname) - 1) { + namelen = sizeof(peer_authname) - 1; + } + BCOPY(name, peer_authname, namelen); + peer_authname[namelen] = 0; + + /* + * If there is no more authentication still to be done, + * proceed to the network (or callback) phase. + */ + if ((auth_pending[unit] &= ~pbit) == 0) { + network_phase(unit); + } +} + +/* + * We have failed to authenticate ourselves to the peer using `protocol'. + */ +void +auth_withpeer_fail(int unit, u16_t protocol) +{ + int errCode = PPPERR_AUTHFAIL; + + LWIP_UNUSED_ARG(protocol); + + AUTHDEBUG(LOG_INFO, ("auth_withpeer_fail: %d proto=%X\n", unit, protocol)); + if (passwd_from_file) { + BZERO(ppp_settings.passwd, MAXSECRETLEN); + } + + /* + * We've failed to authenticate ourselves to our peer. + * He'll probably take the link down, and there's not much + * we can do except wait for that. + */ + pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode); + lcp_close(unit, "Failed to authenticate ourselves to peer"); +} + +/* + * We have successfully authenticated ourselves with the peer using `protocol'. + */ +void +auth_withpeer_success(int unit, u16_t protocol) +{ + int pbit; + + AUTHDEBUG(LOG_INFO, ("auth_withpeer_success: %d proto=%X\n", unit, protocol)); + switch (protocol) { + case PPP_CHAP: + pbit = CHAP_WITHPEER; + break; + case PPP_PAP: + if (passwd_from_file) { + BZERO(ppp_settings.passwd, MAXSECRETLEN); + } + pbit = PAP_WITHPEER; + break; + default: + AUTHDEBUG(LOG_WARNING, ("auth_peer_success: unknown protocol %x\n", protocol)); + pbit = 0; + } + + /* + * If there is no more authentication still being done, + * proceed to the network (or callback) phase. + */ + if ((auth_pending[unit] &= ~pbit) == 0) { + network_phase(unit); + } +} +#endif /* PAP_SUPPORT || CHAP_SUPPORT */ + + +/* + * np_up - a network protocol has come up. + */ +void +np_up(int unit, u16_t proto) +{ + LWIP_UNUSED_ARG(unit); + LWIP_UNUSED_ARG(proto); + + AUTHDEBUG(LOG_INFO, ("np_up: %d proto=%X\n", unit, proto)); + if (num_np_up == 0) { + AUTHDEBUG(LOG_INFO, ("np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit)); + /* + * At this point we consider that the link has come up successfully. + */ + if (ppp_settings.idle_time_limit > 0) { + TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit); + } + + /* + * Set a timeout to close the connection once the maximum + * connect time has expired. + */ + if (ppp_settings.maxconnect > 0) { + TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect); + } + } + ++num_np_up; +} + +/* + * np_down - a network protocol has gone down. + */ +void +np_down(int unit, u16_t proto) +{ + LWIP_UNUSED_ARG(unit); + LWIP_UNUSED_ARG(proto); + + AUTHDEBUG(LOG_INFO, ("np_down: %d proto=%X\n", unit, proto)); + if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) { + UNTIMEOUT(check_idle, NULL); + } +} + +/* + * np_finished - a network protocol has finished using the link. + */ +void +np_finished(int unit, u16_t proto) +{ + LWIP_UNUSED_ARG(unit); + LWIP_UNUSED_ARG(proto); + + AUTHDEBUG(LOG_INFO, ("np_finished: %d proto=%X\n", unit, proto)); + if (--num_np_open <= 0) { + /* no further use for the link: shut up shop. */ + lcp_close(0, "No network protocols running"); + } +} + +/* + * check_idle - check whether the link has been idle for long + * enough that we can shut it down. + */ +static void +check_idle(void *arg) +{ + struct ppp_idle idle; + u_short itime; + + LWIP_UNUSED_ARG(arg); + if (!get_idle_time(0, &idle)) { + return; + } + itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle); + if (itime >= ppp_settings.idle_time_limit) { + /* link is idle: shut it down. */ + AUTHDEBUG(LOG_INFO, ("Terminating connection due to lack of activity.\n")); + lcp_close(0, "Link inactive"); + } else { + TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime); + } +} + +/* + * connect_time_expired - log a message and close the connection. + */ +static void +connect_time_expired(void *arg) +{ + LWIP_UNUSED_ARG(arg); + + AUTHDEBUG(LOG_INFO, ("Connect time expired\n")); + lcp_close(0, "Connect time expired"); /* Close connection */ +} + +#if 0 /* UNUSED */ +/* + * auth_check_options - called to check authentication options. + */ +void +auth_check_options(void) +{ + lcp_options *wo = &lcp_wantoptions[0]; + int can_auth; + ipcp_options *ipwo = &ipcp_wantoptions[0]; + u32_t remote; + + /* Default our_name to hostname, and user to our_name */ + if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname) { + strcpy(ppp_settings.our_name, ppp_settings.hostname); + } + + if (ppp_settings.user[0] == 0) { + strcpy(ppp_settings.user, ppp_settings.our_name); + } + + /* If authentication is required, ask peer for CHAP or PAP. */ + if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) { + wo->neg_chap = 1; + wo->neg_upap = 1; + } + + /* + * Check whether we have appropriate secrets to use + * to authenticate the peer. + */ + can_auth = wo->neg_upap && have_pap_secret(); + if (!can_auth && wo->neg_chap) { + remote = ipwo->accept_remote? 0: ipwo->hisaddr; + can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote); + } + + if (ppp_settings.auth_required && !can_auth) { + ppp_panic("No auth secret"); + } +} +#endif /* UNUSED */ + +/* + * auth_reset - called when LCP is starting negotiations to recheck + * authentication options, i.e. whether we have appropriate secrets + * to use for authenticating ourselves and/or the peer. + */ +void +auth_reset(int unit) +{ + lcp_options *go = &lcp_gotoptions[unit]; + lcp_options *ao = &lcp_allowoptions[0]; + ipcp_options *ipwo = &ipcp_wantoptions[0]; + u32_t remote; + + AUTHDEBUG(LOG_INFO, ("auth_reset: %d\n", unit)); + ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL)); + ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/; + + if (go->neg_upap && !have_pap_secret()) { + go->neg_upap = 0; + } + if (go->neg_chap) { + remote = ipwo->accept_remote? 0: ipwo->hisaddr; + if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote)) { + go->neg_chap = 0; + } + } +} + +#if PAP_SUPPORT +/* + * check_passwd - Check the user name and passwd against the PAP secrets + * file. If requested, also check against the system password database, + * and login the user if OK. + * + * returns: + * UPAP_AUTHNAK: Authentication failed. + * UPAP_AUTHACK: Authentication succeeded. + * In either case, msg points to an appropriate message. + */ +u_char +check_passwd( int unit, char *auser, int userlen, char *apasswd, int passwdlen, char **msg, int *msglen) +{ +#if 1 /* XXX Assume all entries OK. */ + LWIP_UNUSED_ARG(unit); + LWIP_UNUSED_ARG(auser); + LWIP_UNUSED_ARG(userlen); + LWIP_UNUSED_ARG(apasswd); + LWIP_UNUSED_ARG(passwdlen); + LWIP_UNUSED_ARG(msglen); + *msg = (char *) 0; + return UPAP_AUTHACK; /* XXX Assume all entries OK. */ +#else + u_char ret = 0; + struct wordlist *addrs = NULL; + char passwd[256], user[256]; + char secret[MAXWORDLEN]; + static u_short attempts = 0; + + /* + * Make copies of apasswd and auser, then null-terminate them. + */ + BCOPY(apasswd, passwd, passwdlen); + passwd[passwdlen] = '\0'; + BCOPY(auser, user, userlen); + user[userlen] = '\0'; + *msg = (char *) 0; + + /* XXX Validate user name and password. */ + ret = UPAP_AUTHACK; /* XXX Assume all entries OK. */ + + if (ret == UPAP_AUTHNAK) { + if (*msg == (char *) 0) { + *msg = "Login incorrect"; + } + *msglen = strlen(*msg); + /* + * Frustrate passwd stealer programs. + * Allow 10 tries, but start backing off after 3 (stolen from login). + * On 10'th, drop the connection. + */ + if (attempts++ >= 10) { + AUTHDEBUG(LOG_WARNING, ("%d LOGIN FAILURES BY %s\n", attempts, user)); + /*ppp_panic("Excess Bad Logins");*/ + } + if (attempts > 3) { + /* @todo: this was sleep(), i.e. seconds, not milliseconds + * I don't think we really need this in lwIP - we would block tcpip_thread! + */ + /*sys_msleep((attempts - 3) * 5);*/ + } + if (addrs != NULL) { + free_wordlist(addrs); + } + } else { + attempts = 0; /* Reset count */ + if (*msg == (char *) 0) { + *msg = "Login ok"; + } + *msglen = strlen(*msg); + set_allowed_addrs(unit, addrs); + } + + BZERO(passwd, sizeof(passwd)); + BZERO(secret, sizeof(secret)); + + return ret; +#endif +} +#endif /* PAP_SUPPORT */ + +#if 0 /* UNUSED */ +/* + * This function is needed for PAM. + */ + +#ifdef USE_PAM + +/* lwip does not support PAM*/ + +#endif /* USE_PAM */ + +#endif /* UNUSED */ + + +#if 0 /* UNUSED */ +/* + * plogin - Check the user name and password against the system + * password database, and login the user if OK. + * + * returns: + * UPAP_AUTHNAK: Login failed. + * UPAP_AUTHACK: Login succeeded. + * In either case, msg points to an appropriate message. + */ +static int +plogin(char *user, char *passwd, char **msg, int *msglen) +{ + + LWIP_UNUSED_ARG(user); + LWIP_UNUSED_ARG(passwd); + LWIP_UNUSED_ARG(msg); + LWIP_UNUSED_ARG(msglen); + + + /* The new lines are here align the file when + * compared against the pppd 2.3.11 code */ + + + + + + + + + + + + + + + + + /* XXX Fail until we decide that we want to support logins. */ + return (UPAP_AUTHNAK); +} +#endif + + + +/* + * plogout - Logout the user. + */ +static void +plogout(void) +{ + logged_in = 0; +} + +/* + * null_login - Check if a username of "" and a password of "" are + * acceptable, and iff so, set the list of acceptable IP addresses + * and return 1. + */ +static int +null_login(int unit) +{ + LWIP_UNUSED_ARG(unit); + /* XXX Fail until we decide that we want to support logins. */ + return 0; +} + + +/* + * get_pap_passwd - get a password for authenticating ourselves with + * our peer using PAP. Returns 1 on success, 0 if no suitable password + * could be found. + */ +static int +get_pap_passwd(int unit, char *user, char *passwd) +{ + LWIP_UNUSED_ARG(unit); +/* normally we would reject PAP if no password is provided, + but this causes problems with some providers (like CHT in Taiwan) + who incorrectly request PAP and expect a bogus/empty password, so + always provide a default user/passwd of "none"/"none" + + @todo: This should be configured by the user, instead of being hardcoded here! +*/ + if(user) { + strcpy(user, "none"); + } + if(passwd) { + strcpy(passwd, "none"); + } + return 1; +} + +/* + * have_pap_secret - check whether we have a PAP file with any + * secrets that we could possibly use for authenticating the peer. + */ +static int +have_pap_secret(void) +{ + /* XXX Fail until we set up our passwords. */ + return 0; +} + +/* + * have_chap_secret - check whether we have a CHAP file with a + * secret that we could possibly use for authenticating `client' + * on `server'. Either can be the null string, meaning we don't + * know the identity yet. + */ +static int +have_chap_secret(char *client, char *server, u32_t remote) +{ + LWIP_UNUSED_ARG(client); + LWIP_UNUSED_ARG(server); + LWIP_UNUSED_ARG(remote); + + /* XXX Fail until we set up our passwords. */ + return 0; +} +#if CHAP_SUPPORT + +/* + * get_secret - open the CHAP secret file and return the secret + * for authenticating the given client on the given server. + * (We could be either client or server). + */ +int +get_secret(int unit, char *client, char *server, char *secret, int *secret_len, int save_addrs) +{ +#if 1 + int len; + struct wordlist *addrs; + + LWIP_UNUSED_ARG(unit); + LWIP_UNUSED_ARG(server); + LWIP_UNUSED_ARG(save_addrs); + + addrs = NULL; + + if(!client || !client[0] || strcmp(client, ppp_settings.user)) { + return 0; + } + + len = (int)strlen(ppp_settings.passwd); + if (len > MAXSECRETLEN) { + AUTHDEBUG(LOG_ERR, ("Secret for %s on %s is too long\n", client, server)); + len = MAXSECRETLEN; + } + + BCOPY(ppp_settings.passwd, secret, len); + *secret_len = len; + + return 1; +#else + int ret = 0, len; + struct wordlist *addrs; + char secbuf[MAXWORDLEN]; + + addrs = NULL; + secbuf[0] = 0; + + /* XXX Find secret. */ + if (ret < 0) { + return 0; + } + + if (save_addrs) { + set_allowed_addrs(unit, addrs); + } + + len = strlen(secbuf); + if (len > MAXSECRETLEN) { + AUTHDEBUG(LOG_ERR, ("Secret for %s on %s is too long\n", client, server)); + len = MAXSECRETLEN; + } + + BCOPY(secbuf, secret, len); + BZERO(secbuf, sizeof(secbuf)); + *secret_len = len; + + return 1; +#endif +} +#endif /* CHAP_SUPPORT */ + + +#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */ +/* + * set_allowed_addrs() - set the list of allowed addresses. + */ +static void +set_allowed_addrs(int unit, struct wordlist *addrs) +{ + if (addresses[unit] != NULL) { + free_wordlist(addresses[unit]); + } + addresses[unit] = addrs; + +#if 0 + /* + * If there's only one authorized address we might as well + * ask our peer for that one right away + */ + if (addrs != NULL && addrs->next == NULL) { + char *p = addrs->word; + struct ipcp_options *wo = &ipcp_wantoptions[unit]; + u32_t a; + struct hostent *hp; + + if (wo->hisaddr == 0 && *p != '!' && *p != '-' && strchr(p, '/') == NULL) { + hp = gethostbyname(p); + if (hp != NULL && hp->h_addrtype == AF_INET) { + a = *(u32_t *)hp->h_addr; + } else { + a = inet_addr(p); + } + if (a != (u32_t) -1) { + wo->hisaddr = a; + } + } + } +#endif +} +#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */ + +/* + * auth_ip_addr - check whether the peer is authorized to use + * a given IP address. Returns 1 if authorized, 0 otherwise. + */ +int +auth_ip_addr(int unit, u32_t addr) +{ + return ip_addr_check(addr, addresses[unit]); +} + +static int /* @todo: integrate this funtion into auth_ip_addr()*/ +ip_addr_check(u32_t addr, struct wordlist *addrs) +{ + /* don't allow loopback or multicast address */ + if (bad_ip_adrs(addr)) { + return 0; + } + + if (addrs == NULL) { + return !ppp_settings.auth_required; /* no addresses authorized */ + } + + /* XXX All other addresses allowed. */ + return 1; +} + +/* + * bad_ip_adrs - return 1 if the IP address is one we don't want + * to use, such as an address in the loopback net or a multicast address. + * addr is in network byte order. + */ +int +bad_ip_adrs(u32_t addr) +{ + addr = ntohl(addr); + return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET + || IN_MULTICAST(addr) || IN_BADCLASS(addr); +} + +#if 0 /* UNUSED */ /* PAP_SUPPORT || CHAP_SUPPORT */ +/* + * some_ip_ok - check a wordlist to see if it authorizes any + * IP address(es). + */ +static int +some_ip_ok(struct wordlist *addrs) +{ + for (; addrs != 0; addrs = addrs->next) { + if (addrs->word[0] == '-') + break; + if (addrs->word[0] != '!') + return 1; /* some IP address is allowed */ + } + return 0; +} + +/* + * check_access - complain if a secret file has too-liberal permissions. + */ +static void +check_access(FILE *f, char *filename) +{ + struct stat sbuf; + + if (fstat(fileno(f), &sbuf) < 0) { + warn("cannot stat secret file %s: %m", filename); + } else if ((sbuf.st_mode & (S_IRWXG | S_IRWXO)) != 0) { + warn("Warning - secret file %s has world and/or group access", + filename); + } +} + + +/* + * scan_authfile - Scan an authorization file for a secret suitable + * for authenticating `client' on `server'. The return value is -1 + * if no secret is found, otherwise >= 0. The return value has + * NONWILD_CLIENT set if the secret didn't have "*" for the client, and + * NONWILD_SERVER set if the secret didn't have "*" for the server. + * Any following words on the line up to a "--" (i.e. address authorization + * info) are placed in a wordlist and returned in *addrs. Any + * following words (extra options) are placed in a wordlist and + * returned in *opts. + * We assume secret is NULL or points to MAXWORDLEN bytes of space. + */ +static int +scan_authfile(FILE *f, char *client, char *server, char *secret, struct wordlist **addrs, struct wordlist **opts, char *filename) +{ + /* We do not (currently) need this in lwip */ + return 0; /* dummy */ +} +/* + * free_wordlist - release memory allocated for a wordlist. + */ +static void +free_wordlist(struct wordlist *wp) +{ + struct wordlist *next; + + while (wp != NULL) { + next = wp->next; + free(wp); + wp = next; + } +} + +/* + * auth_script_done - called when the auth-up or auth-down script + * has finished. + */ +static void +auth_script_done(void *arg) +{ + auth_script_pid = 0; + switch (auth_script_state) { + case s_up: + if (auth_state == s_down) { + auth_script_state = s_down; + auth_script(_PATH_AUTHDOWN); + } + break; + case s_down: + if (auth_state == s_up) { + auth_script_state = s_up; + auth_script(_PATH_AUTHUP); + } + break; + } +} + +/* + * auth_script - execute a script with arguments + * interface-name peer-name real-user tty speed + */ +static void +auth_script(char *script) +{ + char strspeed[32]; + struct passwd *pw; + char struid[32]; + char *user_name; + char *argv[8]; + + if ((pw = getpwuid(getuid())) != NULL && pw->pw_name != NULL) + user_name = pw->pw_name; + else { + slprintf(struid, sizeof(struid), "%d", getuid()); + user_name = struid; + } + slprintf(strspeed, sizeof(strspeed), "%d", baud_rate); + + argv[0] = script; + argv[1] = ifname; + argv[2] = peer_authname; + argv[3] = user_name; + argv[4] = devnam; + argv[5] = strspeed; + argv[6] = NULL; + + auth_script_pid = run_program(script, argv, 0, auth_script_done, NULL); +} +#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */ +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.h new file mode 100644 index 0000000..a8069ec --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.h @@ -0,0 +1,111 @@ +/***************************************************************************** +* auth.h - PPP Authentication and phase control header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD pppd.h. +*****************************************************************************/ +/* + * pppd.h - PPP daemon global declarations. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef AUTH_H +#define AUTH_H + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +/* we are starting to use the link */ +void link_required (int); + +/* we are finished with the link */ +void link_terminated (int); + +/* the LCP layer has left the Opened state */ +void link_down (int); + +/* the link is up; authenticate now */ +void link_established (int); + +/* a network protocol has come up */ +void np_up (int, u16_t); + +/* a network protocol has gone down */ +void np_down (int, u16_t); + +/* a network protocol no longer needs link */ +void np_finished (int, u16_t); + +/* peer failed to authenticate itself */ +void auth_peer_fail (int, u16_t); + +/* peer successfully authenticated itself */ +void auth_peer_success (int, u16_t, char *, int); + +/* we failed to authenticate ourselves */ +void auth_withpeer_fail (int, u16_t); + +/* we successfully authenticated ourselves */ +void auth_withpeer_success (int, u16_t); + +/* check authentication options supplied */ +void auth_check_options (void); + +/* check what secrets we have */ +void auth_reset (int); + +/* Check peer-supplied username/password */ +u_char check_passwd (int, char *, int, char *, int, char **, int *); + +/* get "secret" for chap */ +int get_secret (int, char *, char *, char *, int *, int); + +/* check if IP address is authorized */ +int auth_ip_addr (int, u32_t); + +/* check if IP address is unreasonable */ +int bad_ip_adrs (u32_t); + +#endif /* AUTH_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.c new file mode 100644 index 0000000..3a49ff8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.c @@ -0,0 +1,908 @@ +/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/ +/***************************************************************************** +* chap.c - Network Challenge Handshake Authentication Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD chap.c. +*****************************************************************************/ +/* + * chap.c - Challenge Handshake Authentication Protocol. + * + * Copyright (c) 1993 The Australian National University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the Australian National University. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Copyright (c) 1991 Gregory M. Christy. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Gregory M. Christy. The name of the author may not be used to + * endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "ppp.h" +#include "pppdebug.h" + +#include "magic.h" +#include "randm.h" +#include "auth.h" +#include "md5.h" +#include "chap.h" +#include "chpms.h" + +#include + +#if 0 /* UNUSED */ +/* + * Command-line options. + */ +static option_t chap_option_list[] = { + { "chap-restart", o_int, &chap[0].timeouttime, + "Set timeout for CHAP" }, + { "chap-max-challenge", o_int, &chap[0].max_transmits, + "Set max #xmits for challenge" }, + { "chap-interval", o_int, &chap[0].chal_interval, + "Set interval for rechallenge" }, +#ifdef MSLANMAN + { "ms-lanman", o_bool, &ms_lanman, + "Use LanMan passwd when using MS-CHAP", 1 }, +#endif + { NULL } +}; +#endif /* UNUSED */ + +/* + * Protocol entry points. + */ +static void ChapInit (int); +static void ChapLowerUp (int); +static void ChapLowerDown (int); +static void ChapInput (int, u_char *, int); +static void ChapProtocolReject (int); +#if PPP_ADDITIONAL_CALLBACKS +static int ChapPrintPkt (u_char *, int, void (*) (void *, char *, ...), void *); +#endif + +struct protent chap_protent = { + PPP_CHAP, + ChapInit, + ChapInput, + ChapProtocolReject, + ChapLowerUp, + ChapLowerDown, + NULL, + NULL, +#if PPP_ADDITIONAL_CALLBACKS + ChapPrintPkt, + NULL, +#endif /* PPP_ADDITIONAL_CALLBACKS */ + 1, + "CHAP", +#if PPP_ADDITIONAL_CALLBACKS + NULL, + NULL, + NULL +#endif /* PPP_ADDITIONAL_CALLBACKS */ +}; + +chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */ + +static void ChapChallengeTimeout (void *); +static void ChapResponseTimeout (void *); +static void ChapReceiveChallenge (chap_state *, u_char *, u_char, int); +static void ChapRechallenge (void *); +static void ChapReceiveResponse (chap_state *, u_char *, int, int); +static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len); +static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len); +static void ChapSendStatus (chap_state *, int); +static void ChapSendChallenge (chap_state *); +static void ChapSendResponse (chap_state *); +static void ChapGenChallenge (chap_state *); + +/* + * ChapInit - Initialize a CHAP unit. + */ +static void +ChapInit(int unit) +{ + chap_state *cstate = &chap[unit]; + + BZERO(cstate, sizeof(*cstate)); + cstate->unit = unit; + cstate->clientstate = CHAPCS_INITIAL; + cstate->serverstate = CHAPSS_INITIAL; + cstate->timeouttime = CHAP_DEFTIMEOUT; + cstate->max_transmits = CHAP_DEFTRANSMITS; + /* random number generator is initialized in magic_init */ +} + + +/* + * ChapAuthWithPeer - Authenticate us with our peer (start client). + * + */ +void +ChapAuthWithPeer(int unit, char *our_name, u_char digest) +{ + chap_state *cstate = &chap[unit]; + + cstate->resp_name = our_name; + cstate->resp_type = digest; + + if (cstate->clientstate == CHAPCS_INITIAL || + cstate->clientstate == CHAPCS_PENDING) { + /* lower layer isn't up - wait until later */ + cstate->clientstate = CHAPCS_PENDING; + return; + } + + /* + * We get here as a result of LCP coming up. + * So even if CHAP was open before, we will + * have to re-authenticate ourselves. + */ + cstate->clientstate = CHAPCS_LISTEN; +} + + +/* + * ChapAuthPeer - Authenticate our peer (start server). + */ +void +ChapAuthPeer(int unit, char *our_name, u_char digest) +{ + chap_state *cstate = &chap[unit]; + + cstate->chal_name = our_name; + cstate->chal_type = digest; + + if (cstate->serverstate == CHAPSS_INITIAL || + cstate->serverstate == CHAPSS_PENDING) { + /* lower layer isn't up - wait until later */ + cstate->serverstate = CHAPSS_PENDING; + return; + } + + ChapGenChallenge(cstate); + ChapSendChallenge(cstate); /* crank it up dude! */ + cstate->serverstate = CHAPSS_INITIAL_CHAL; +} + + +/* + * ChapChallengeTimeout - Timeout expired on sending challenge. + */ +static void +ChapChallengeTimeout(void *arg) +{ + chap_state *cstate = (chap_state *) arg; + + /* if we aren't sending challenges, don't worry. then again we */ + /* probably shouldn't be here either */ + if (cstate->serverstate != CHAPSS_INITIAL_CHAL && + cstate->serverstate != CHAPSS_RECHALLENGE) { + return; + } + + if (cstate->chal_transmits >= cstate->max_transmits) { + /* give up on peer */ + CHAPDEBUG(LOG_ERR, ("Peer failed to respond to CHAP challenge\n")); + cstate->serverstate = CHAPSS_BADAUTH; + auth_peer_fail(cstate->unit, PPP_CHAP); + return; + } + + ChapSendChallenge(cstate); /* Re-send challenge */ +} + + +/* + * ChapResponseTimeout - Timeout expired on sending response. + */ +static void +ChapResponseTimeout(void *arg) +{ + chap_state *cstate = (chap_state *) arg; + + /* if we aren't sending a response, don't worry. */ + if (cstate->clientstate != CHAPCS_RESPONSE) { + return; + } + + ChapSendResponse(cstate); /* re-send response */ +} + + +/* + * ChapRechallenge - Time to challenge the peer again. + */ +static void +ChapRechallenge(void *arg) +{ + chap_state *cstate = (chap_state *) arg; + + /* if we aren't sending a response, don't worry. */ + if (cstate->serverstate != CHAPSS_OPEN) { + return; + } + + ChapGenChallenge(cstate); + ChapSendChallenge(cstate); + cstate->serverstate = CHAPSS_RECHALLENGE; +} + + +/* + * ChapLowerUp - The lower layer is up. + * + * Start up if we have pending requests. + */ +static void +ChapLowerUp(int unit) +{ + chap_state *cstate = &chap[unit]; + + if (cstate->clientstate == CHAPCS_INITIAL) { + cstate->clientstate = CHAPCS_CLOSED; + } else if (cstate->clientstate == CHAPCS_PENDING) { + cstate->clientstate = CHAPCS_LISTEN; + } + + if (cstate->serverstate == CHAPSS_INITIAL) { + cstate->serverstate = CHAPSS_CLOSED; + } else if (cstate->serverstate == CHAPSS_PENDING) { + ChapGenChallenge(cstate); + ChapSendChallenge(cstate); + cstate->serverstate = CHAPSS_INITIAL_CHAL; + } +} + + +/* + * ChapLowerDown - The lower layer is down. + * + * Cancel all timeouts. + */ +static void +ChapLowerDown(int unit) +{ + chap_state *cstate = &chap[unit]; + + /* Timeout(s) pending? Cancel if so. */ + if (cstate->serverstate == CHAPSS_INITIAL_CHAL || + cstate->serverstate == CHAPSS_RECHALLENGE) { + UNTIMEOUT(ChapChallengeTimeout, cstate); + } else if (cstate->serverstate == CHAPSS_OPEN + && cstate->chal_interval != 0) { + UNTIMEOUT(ChapRechallenge, cstate); + } + if (cstate->clientstate == CHAPCS_RESPONSE) { + UNTIMEOUT(ChapResponseTimeout, cstate); + } + cstate->clientstate = CHAPCS_INITIAL; + cstate->serverstate = CHAPSS_INITIAL; +} + + +/* + * ChapProtocolReject - Peer doesn't grok CHAP. + */ +static void +ChapProtocolReject(int unit) +{ + chap_state *cstate = &chap[unit]; + + if (cstate->serverstate != CHAPSS_INITIAL && + cstate->serverstate != CHAPSS_CLOSED) { + auth_peer_fail(unit, PPP_CHAP); + } + if (cstate->clientstate != CHAPCS_INITIAL && + cstate->clientstate != CHAPCS_CLOSED) { + auth_withpeer_fail(unit, PPP_CHAP); /* lwip: just sets the PPP error code on this unit to PPPERR_AUTHFAIL */ + } + ChapLowerDown(unit); /* shutdown chap */ +} + + +/* + * ChapInput - Input CHAP packet. + */ +static void +ChapInput(int unit, u_char *inpacket, int packet_len) +{ + chap_state *cstate = &chap[unit]; + u_char *inp; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + inp = inpacket; + if (packet_len < CHAP_HEADERLEN) { + CHAPDEBUG(LOG_INFO, ("ChapInput: rcvd short header.\n")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < CHAP_HEADERLEN) { + CHAPDEBUG(LOG_INFO, ("ChapInput: rcvd illegal length.\n")); + return; + } + if (len > packet_len) { + CHAPDEBUG(LOG_INFO, ("ChapInput: rcvd short packet.\n")); + return; + } + len -= CHAP_HEADERLEN; + + /* + * Action depends on code (as in fact it usually does :-). + */ + switch (code) { + case CHAP_CHALLENGE: + ChapReceiveChallenge(cstate, inp, id, len); + break; + + case CHAP_RESPONSE: + ChapReceiveResponse(cstate, inp, id, len); + break; + + case CHAP_FAILURE: + ChapReceiveFailure(cstate, inp, id, len); + break; + + case CHAP_SUCCESS: + ChapReceiveSuccess(cstate, inp, id, len); + break; + + default: /* Need code reject? */ + CHAPDEBUG(LOG_WARNING, ("Unknown CHAP code (%d) received.\n", code)); + break; + } +} + + +/* + * ChapReceiveChallenge - Receive Challenge and send Response. + */ +static void +ChapReceiveChallenge(chap_state *cstate, u_char *inp, u_char id, int len) +{ + int rchallenge_len; + u_char *rchallenge; + int secret_len; + char secret[MAXSECRETLEN]; + char rhostname[256]; + MD5_CTX mdContext; + u_char hash[MD5_SIGNATURE_SIZE]; + + CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: Rcvd id %d.\n", id)); + if (cstate->clientstate == CHAPCS_CLOSED || + cstate->clientstate == CHAPCS_PENDING) { + CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: in state %d\n", + cstate->clientstate)); + return; + } + + if (len < 2) { + CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: rcvd short packet.\n")); + return; + } + + GETCHAR(rchallenge_len, inp); + len -= sizeof (u_char) + rchallenge_len; /* now name field length */ + if (len < 0) { + CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: rcvd short packet.\n")); + return; + } + rchallenge = inp; + INCPTR(rchallenge_len, inp); + + if (len >= (int)sizeof(rhostname)) { + len = sizeof(rhostname) - 1; + } + BCOPY(inp, rhostname, len); + rhostname[len] = '\000'; + + CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: received name field '%s'\n", + rhostname)); + + /* Microsoft doesn't send their name back in the PPP packet */ + if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) { + strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname)); + rhostname[sizeof(rhostname) - 1] = 0; + CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: using '%s' as remote name\n", + rhostname)); + } + + /* get secret for authenticating ourselves with the specified host */ + if (!get_secret(cstate->unit, cstate->resp_name, rhostname, + secret, &secret_len, 0)) { + secret_len = 0; /* assume null secret if can't find one */ + CHAPDEBUG(LOG_WARNING, ("No CHAP secret found for authenticating us to %s\n", + rhostname)); + } + + /* cancel response send timeout if necessary */ + if (cstate->clientstate == CHAPCS_RESPONSE) { + UNTIMEOUT(ChapResponseTimeout, cstate); + } + + cstate->resp_id = id; + cstate->resp_transmits = 0; + + /* generate MD based on negotiated type */ + switch (cstate->resp_type) { + + case CHAP_DIGEST_MD5: + MD5Init(&mdContext); + MD5Update(&mdContext, &cstate->resp_id, 1); + MD5Update(&mdContext, (u_char*)secret, secret_len); + MD5Update(&mdContext, rchallenge, rchallenge_len); + MD5Final(hash, &mdContext); + BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE); + cstate->resp_length = MD5_SIGNATURE_SIZE; + break; + +#if MSCHAP_SUPPORT + case CHAP_MICROSOFT: + ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len); + break; +#endif + + default: + CHAPDEBUG(LOG_INFO, ("unknown digest type %d\n", cstate->resp_type)); + return; + } + + BZERO(secret, sizeof(secret)); + ChapSendResponse(cstate); +} + + +/* + * ChapReceiveResponse - Receive and process response. + */ +static void +ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len) +{ + u_char *remmd, remmd_len; + int secret_len, old_state; + int code; + char rhostname[256]; + MD5_CTX mdContext; + char secret[MAXSECRETLEN]; + u_char hash[MD5_SIGNATURE_SIZE]; + + CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: Rcvd id %d.\n", id)); + + if (cstate->serverstate == CHAPSS_CLOSED || + cstate->serverstate == CHAPSS_PENDING) { + CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: in state %d\n", + cstate->serverstate)); + return; + } + + if (id != cstate->chal_id) { + return; /* doesn't match ID of last challenge */ + } + + /* + * If we have received a duplicate or bogus Response, + * we have to send the same answer (Success/Failure) + * as we did for the first Response we saw. + */ + if (cstate->serverstate == CHAPSS_OPEN) { + ChapSendStatus(cstate, CHAP_SUCCESS); + return; + } + if (cstate->serverstate == CHAPSS_BADAUTH) { + ChapSendStatus(cstate, CHAP_FAILURE); + return; + } + + if (len < 2) { + CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: rcvd short packet.\n")); + return; + } + GETCHAR(remmd_len, inp); /* get length of MD */ + remmd = inp; /* get pointer to MD */ + INCPTR(remmd_len, inp); + + len -= sizeof (u_char) + remmd_len; + if (len < 0) { + CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: rcvd short packet.\n")); + return; + } + + UNTIMEOUT(ChapChallengeTimeout, cstate); + + if (len >= (int)sizeof(rhostname)) { + len = sizeof(rhostname) - 1; + } + BCOPY(inp, rhostname, len); + rhostname[len] = '\000'; + + CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: received name field: %s\n", + rhostname)); + + /* + * Get secret for authenticating them with us, + * do the hash ourselves, and compare the result. + */ + code = CHAP_FAILURE; + if (!get_secret(cstate->unit, rhostname, cstate->chal_name, + secret, &secret_len, 1)) { + CHAPDEBUG(LOG_WARNING, ("No CHAP secret found for authenticating %s\n", + rhostname)); + } else { + /* generate MD based on negotiated type */ + switch (cstate->chal_type) { + + case CHAP_DIGEST_MD5: /* only MD5 is defined for now */ + if (remmd_len != MD5_SIGNATURE_SIZE) { + break; /* it's not even the right length */ + } + MD5Init(&mdContext); + MD5Update(&mdContext, &cstate->chal_id, 1); + MD5Update(&mdContext, (u_char*)secret, secret_len); + MD5Update(&mdContext, cstate->challenge, cstate->chal_len); + MD5Final(hash, &mdContext); + + /* compare local and remote MDs and send the appropriate status */ + if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0) { + code = CHAP_SUCCESS; /* they are the same! */ + } + break; + + default: + CHAPDEBUG(LOG_INFO, ("unknown digest type %d\n", cstate->chal_type)); + } + } + + BZERO(secret, sizeof(secret)); + ChapSendStatus(cstate, code); + + if (code == CHAP_SUCCESS) { + old_state = cstate->serverstate; + cstate->serverstate = CHAPSS_OPEN; + if (old_state == CHAPSS_INITIAL_CHAL) { + auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len); + } + if (cstate->chal_interval != 0) { + TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval); + } + } else { + CHAPDEBUG(LOG_ERR, ("CHAP peer authentication failed\n")); + cstate->serverstate = CHAPSS_BADAUTH; + auth_peer_fail(cstate->unit, PPP_CHAP); + } +} + +/* + * ChapReceiveSuccess - Receive Success + */ +static void +ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len) +{ + LWIP_UNUSED_ARG(id); + LWIP_UNUSED_ARG(inp); + + CHAPDEBUG(LOG_INFO, ("ChapReceiveSuccess: Rcvd id %d.\n", id)); + + if (cstate->clientstate == CHAPCS_OPEN) { + /* presumably an answer to a duplicate response */ + return; + } + + if (cstate->clientstate != CHAPCS_RESPONSE) { + /* don't know what this is */ + CHAPDEBUG(LOG_INFO, ("ChapReceiveSuccess: in state %d\n", + cstate->clientstate)); + return; + } + + UNTIMEOUT(ChapResponseTimeout, cstate); + + /* + * Print message. + */ + if (len > 0) { + PRINTMSG(inp, len); + } + + cstate->clientstate = CHAPCS_OPEN; + + auth_withpeer_success(cstate->unit, PPP_CHAP); +} + + +/* + * ChapReceiveFailure - Receive failure. + */ +static void +ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len) +{ + LWIP_UNUSED_ARG(id); + LWIP_UNUSED_ARG(inp); + + CHAPDEBUG(LOG_INFO, ("ChapReceiveFailure: Rcvd id %d.\n", id)); + + if (cstate->clientstate != CHAPCS_RESPONSE) { + /* don't know what this is */ + CHAPDEBUG(LOG_INFO, ("ChapReceiveFailure: in state %d\n", + cstate->clientstate)); + return; + } + + UNTIMEOUT(ChapResponseTimeout, cstate); + + /* + * Print message. + */ + if (len > 0) { + PRINTMSG(inp, len); + } + + CHAPDEBUG(LOG_ERR, ("CHAP authentication failed\n")); + auth_withpeer_fail(cstate->unit, PPP_CHAP); /* lwip: just sets the PPP error code on this unit to PPPERR_AUTHFAIL */ +} + + +/* + * ChapSendChallenge - Send an Authenticate challenge. + */ +static void +ChapSendChallenge(chap_state *cstate) +{ + u_char *outp; + int chal_len, name_len; + int outlen; + + chal_len = cstate->chal_len; + name_len = (int)strlen(cstate->chal_name); + outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len; + outp = outpacket_buf[cstate->unit]; + + MAKEHEADER(outp, PPP_CHAP); /* paste in a CHAP header */ + + PUTCHAR(CHAP_CHALLENGE, outp); + PUTCHAR(cstate->chal_id, outp); + PUTSHORT(outlen, outp); + + PUTCHAR(chal_len, outp); /* put length of challenge */ + BCOPY(cstate->challenge, outp, chal_len); + INCPTR(chal_len, outp); + + BCOPY(cstate->chal_name, outp, name_len); /* append hostname */ + + pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); + + CHAPDEBUG(LOG_INFO, ("ChapSendChallenge: Sent id %d.\n", cstate->chal_id)); + + TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime); + ++cstate->chal_transmits; +} + + +/* + * ChapSendStatus - Send a status response (ack or nak). + */ +static void +ChapSendStatus(chap_state *cstate, int code) +{ + u_char *outp; + int outlen, msglen; + char msg[256]; /* @todo: this can be a char*, no strcpy needed */ + + if (code == CHAP_SUCCESS) { + strcpy(msg, "Welcome!"); + } else { + strcpy(msg, "I don't like you. Go 'way."); + } + msglen = (int)strlen(msg); + + outlen = CHAP_HEADERLEN + msglen; + outp = outpacket_buf[cstate->unit]; + + MAKEHEADER(outp, PPP_CHAP); /* paste in a header */ + + PUTCHAR(code, outp); + PUTCHAR(cstate->chal_id, outp); + PUTSHORT(outlen, outp); + BCOPY(msg, outp, msglen); + pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); + + CHAPDEBUG(LOG_INFO, ("ChapSendStatus: Sent code %d, id %d.\n", code, + cstate->chal_id)); +} + +/* + * ChapGenChallenge is used to generate a pseudo-random challenge string of + * a pseudo-random length between min_len and max_len. The challenge + * string and its length are stored in *cstate, and various other fields of + * *cstate are initialized. + */ + +static void +ChapGenChallenge(chap_state *cstate) +{ + int chal_len; + u_char *ptr = cstate->challenge; + int i; + + /* pick a random challenge length between MIN_CHALLENGE_LENGTH and + MAX_CHALLENGE_LENGTH */ + chal_len = (unsigned) + ((((magic() >> 16) * + (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16) + + MIN_CHALLENGE_LENGTH); + LWIP_ASSERT("chal_len <= 0xff", chal_len <= 0xffff); + cstate->chal_len = (u_char)chal_len; + cstate->chal_id = ++cstate->id; + cstate->chal_transmits = 0; + + /* generate a random string */ + for (i = 0; i < chal_len; i++ ) { + *ptr++ = (char) (magic() & 0xff); + } +} + +/* + * ChapSendResponse - send a response packet with values as specified + * in *cstate. + */ +/* ARGSUSED */ +static void +ChapSendResponse(chap_state *cstate) +{ + u_char *outp; + int outlen, md_len, name_len; + + md_len = cstate->resp_length; + name_len = (int)strlen(cstate->resp_name); + outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len; + outp = outpacket_buf[cstate->unit]; + + MAKEHEADER(outp, PPP_CHAP); + + PUTCHAR(CHAP_RESPONSE, outp); /* we are a response */ + PUTCHAR(cstate->resp_id, outp); /* copy id from challenge packet */ + PUTSHORT(outlen, outp); /* packet length */ + + PUTCHAR(md_len, outp); /* length of MD */ + BCOPY(cstate->response, outp, md_len); /* copy MD to buffer */ + INCPTR(md_len, outp); + + BCOPY(cstate->resp_name, outp, name_len); /* append our name */ + + /* send the packet */ + pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); + + cstate->clientstate = CHAPCS_RESPONSE; + TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime); + ++cstate->resp_transmits; +} + +#if PPP_ADDITIONAL_CALLBACKS +static char *ChapCodenames[] = { + "Challenge", "Response", "Success", "Failure" +}; +/* + * ChapPrintPkt - print the contents of a CHAP packet. + */ +static int +ChapPrintPkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg) +{ + int code, id, len; + int clen, nlen; + u_char x; + + if (plen < CHAP_HEADERLEN) { + return 0; + } + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < CHAP_HEADERLEN || len > plen) { + return 0; + } + + if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *)) { + printer(arg, " %s", ChapCodenames[code-1]); + } else { + printer(arg, " code=0x%x", code); + } + printer(arg, " id=0x%x", id); + len -= CHAP_HEADERLEN; + switch (code) { + case CHAP_CHALLENGE: + case CHAP_RESPONSE: + if (len < 1) { + break; + } + clen = p[0]; + if (len < clen + 1) { + break; + } + ++p; + nlen = len - clen - 1; + printer(arg, " <"); + for (; clen > 0; --clen) { + GETCHAR(x, p); + printer(arg, "%.2x", x); + } + printer(arg, ">, name = %.*Z", nlen, p); + break; + case CHAP_FAILURE: + case CHAP_SUCCESS: + printer(arg, " %.*Z", len, p); + break; + default: + for (clen = len; clen > 0; --clen) { + GETCHAR(x, p); + printer(arg, " %.2x", x); + } + } + + return len + CHAP_HEADERLEN; +} +#endif /* PPP_ADDITIONAL_CALLBACKS */ + +#endif /* CHAP_SUPPORT */ + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.h new file mode 100644 index 0000000..fedcab8 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.h @@ -0,0 +1,150 @@ +/***************************************************************************** +* chap.h - Network Challenge Handshake Authentication Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-03 Guy Lancaster , Global Election Systems Inc. +* Original built from BSD network code. +******************************************************************************/ +/* + * chap.h - Challenge Handshake Authentication Protocol definitions. + * + * Copyright (c) 1993 The Australian National University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the Australian National University. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Copyright (c) 1991 Gregory M. Christy + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the author. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: chap.h,v 1.6 2010/01/24 13:19:34 goldsimon Exp $ + */ + +#ifndef CHAP_H +#define CHAP_H + +/* Code + ID + length */ +#define CHAP_HEADERLEN 4 + +/* + * CHAP codes. + */ + +#define CHAP_DIGEST_MD5 5 /* use MD5 algorithm */ +#define MD5_SIGNATURE_SIZE 16 /* 16 bytes in a MD5 message digest */ +#define CHAP_MICROSOFT 0x80 /* use Microsoft-compatible alg. */ +#define MS_CHAP_RESPONSE_LEN 49 /* Response length for MS-CHAP */ + +#define CHAP_CHALLENGE 1 +#define CHAP_RESPONSE 2 +#define CHAP_SUCCESS 3 +#define CHAP_FAILURE 4 + +/* + * Challenge lengths (for challenges we send) and other limits. + */ +#define MIN_CHALLENGE_LENGTH 32 +#define MAX_CHALLENGE_LENGTH 64 +#define MAX_RESPONSE_LENGTH 64 /* sufficient for MD5 or MS-CHAP */ + +/* + * Each interface is described by a chap structure. + */ + +typedef struct chap_state { + int unit; /* Interface unit number */ + int clientstate; /* Client state */ + int serverstate; /* Server state */ + u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */ + u_char chal_len; /* challenge length */ + u_char chal_id; /* ID of last challenge */ + u_char chal_type; /* hash algorithm for challenges */ + u_char id; /* Current id */ + char *chal_name; /* Our name to use with challenge */ + int chal_interval; /* Time until we challenge peer again */ + int timeouttime; /* Timeout time in seconds */ + int max_transmits; /* Maximum # of challenge transmissions */ + int chal_transmits; /* Number of transmissions of challenge */ + int resp_transmits; /* Number of transmissions of response */ + u_char response[MAX_RESPONSE_LENGTH]; /* Response to send */ + u_char resp_length; /* length of response */ + u_char resp_id; /* ID for response messages */ + u_char resp_type; /* hash algorithm for responses */ + char *resp_name; /* Our name to send with response */ +} chap_state; + + +/* + * Client (peer) states. + */ +#define CHAPCS_INITIAL 0 /* Lower layer down, not opened */ +#define CHAPCS_CLOSED 1 /* Lower layer up, not opened */ +#define CHAPCS_PENDING 2 /* Auth us to peer when lower up */ +#define CHAPCS_LISTEN 3 /* Listening for a challenge */ +#define CHAPCS_RESPONSE 4 /* Sent response, waiting for status */ +#define CHAPCS_OPEN 5 /* We've received Success */ + +/* + * Server (authenticator) states. + */ +#define CHAPSS_INITIAL 0 /* Lower layer down, not opened */ +#define CHAPSS_CLOSED 1 /* Lower layer up, not opened */ +#define CHAPSS_PENDING 2 /* Auth peer when lower up */ +#define CHAPSS_INITIAL_CHAL 3 /* We've sent the first challenge */ +#define CHAPSS_OPEN 4 /* We've sent a Success msg */ +#define CHAPSS_RECHALLENGE 5 /* We've sent another challenge */ +#define CHAPSS_BADAUTH 6 /* We've sent a Failure msg */ + +extern chap_state chap[]; + +void ChapAuthWithPeer (int, char *, u_char); +void ChapAuthPeer (int, char *, u_char); + +extern struct protent chap_protent; + +#endif /* CHAP_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.c new file mode 100644 index 0000000..83acefc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.c @@ -0,0 +1,396 @@ +/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/ +/*** The original PPPD code is written in a way to require either the UNIX DES + encryption functions encrypt(3) and setkey(3) or the DES library libdes. + Since both is not included in lwIP, MSCHAP currently does not work! */ +/***************************************************************************** +* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-08 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD chap_ms.c. +*****************************************************************************/ +/* + * chap_ms.c - Microsoft MS-CHAP compatible implementation. + * + * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. + * http://www.strataware.com/ + * + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Eric Rosenquist. The name of the author may not be used to + * endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* + * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997 + * + * Implemented LANManager type password response to MS-CHAP challenges. + * Now pppd provides both NT style and LANMan style blocks, and the + * prefered is set by option "ms-lanman". Default is to use NT. + * The hash text (StdText) was taken from Win95 RASAPI32.DLL. + * + * You should also use DOMAIN\\USERNAME as described in README.MSCHAP80 + */ + +#define USE_CRYPT + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if MSCHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "ppp.h" +#include "pppdebug.h" + +#include "md4.h" +#ifndef USE_CRYPT +#include "des.h" +#endif +#include "chap.h" +#include "chpms.h" + +#include + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ +typedef struct { + u_char LANManResp[24]; + u_char NTResp[24]; + u_char UseNT; /* If 1, ignore the LANMan response field */ +} MS_ChapResponse; +/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse), + in case this struct gets padded. */ + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ + +/* XXX Don't know what to do with these. */ +extern void setkey(const char *); +extern void encrypt(char *, int); + +static void DesEncrypt (u_char *, u_char *, u_char *); +static void MakeKey (u_char *, u_char *); + +#ifdef USE_CRYPT +static void Expand (u_char *, u_char *); +static void Collapse (u_char *, u_char *); +#endif + +static void ChallengeResponse( + u_char *challenge, /* IN 8 octets */ + u_char *pwHash, /* IN 16 octets */ + u_char *response /* OUT 24 octets */ +); +static void ChapMS_NT( + char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len, + MS_ChapResponse *response +); +static u_char Get7Bits( + u_char *input, + int startBit +); + +static void +ChallengeResponse( u_char *challenge, /* IN 8 octets */ + u_char *pwHash, /* IN 16 octets */ + u_char *response /* OUT 24 octets */) +{ + u_char ZPasswordHash[21]; + + BZERO(ZPasswordHash, sizeof(ZPasswordHash)); + BCOPY(pwHash, ZPasswordHash, 16); + +#if 0 + log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG); +#endif + + DesEncrypt(challenge, ZPasswordHash + 0, response + 0); + DesEncrypt(challenge, ZPasswordHash + 7, response + 8); + DesEncrypt(challenge, ZPasswordHash + 14, response + 16); + +#if 0 + log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG); +#endif +} + + +#ifdef USE_CRYPT +static void +DesEncrypt( u_char *clear, /* IN 8 octets */ + u_char *key, /* IN 7 octets */ + u_char *cipher /* OUT 8 octets */) +{ + u_char des_key[8]; + u_char crypt_key[66]; + u_char des_input[66]; + + MakeKey(key, des_key); + + Expand(des_key, crypt_key); + setkey((char*)crypt_key); + +#if 0 + CHAPDEBUG(LOG_INFO, ("DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", + clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); +#endif + + Expand(clear, des_input); + encrypt((char*)des_input, 0); + Collapse(des_input, cipher); + +#if 0 + CHAPDEBUG(LOG_INFO, ("DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", + cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); +#endif +} + +#else /* USE_CRYPT */ + +static void +DesEncrypt( u_char *clear, /* IN 8 octets */ + u_char *key, /* IN 7 octets */ + u_char *cipher /* OUT 8 octets */) +{ + des_cblock des_key; + des_key_schedule key_schedule; + + MakeKey(key, des_key); + + des_set_key(&des_key, key_schedule); + +#if 0 + CHAPDEBUG(LOG_INFO, ("DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", + clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); +#endif + + des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1); + +#if 0 + CHAPDEBUG(LOG_INFO, ("DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", + cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); +#endif +} + +#endif /* USE_CRYPT */ + + +static u_char +Get7Bits( u_char *input, int startBit) +{ + register unsigned int word; + + word = (unsigned)input[startBit / 8] << 8; + word |= (unsigned)input[startBit / 8 + 1]; + + word >>= 15 - (startBit % 8 + 7); + + return word & 0xFE; +} + +#ifdef USE_CRYPT + +/* in == 8-byte string (expanded version of the 56-bit key) + * out == 64-byte string where each byte is either 1 or 0 + * Note that the low-order "bit" is always ignored by by setkey() + */ +static void +Expand(u_char *in, u_char *out) +{ + int j, c; + int i; + + for(i = 0; i < 64; in++){ + c = *in; + for(j = 7; j >= 0; j--) { + *out++ = (c >> j) & 01; + } + i += 8; + } +} + +/* The inverse of Expand + */ +static void +Collapse(u_char *in, u_char *out) +{ + int j; + int i; + unsigned int c; + + for (i = 0; i < 64; i += 8, out++) { + c = 0; + for (j = 7; j >= 0; j--, in++) { + c |= *in << j; + } + *out = c & 0xff; + } +} +#endif + +static void +MakeKey( u_char *key, /* IN 56 bit DES key missing parity bits */ + u_char *des_key /* OUT 64 bit DES key with parity bits added */) +{ + des_key[0] = Get7Bits(key, 0); + des_key[1] = Get7Bits(key, 7); + des_key[2] = Get7Bits(key, 14); + des_key[3] = Get7Bits(key, 21); + des_key[4] = Get7Bits(key, 28); + des_key[5] = Get7Bits(key, 35); + des_key[6] = Get7Bits(key, 42); + des_key[7] = Get7Bits(key, 49); + +#ifndef USE_CRYPT + des_set_odd_parity((des_cblock *)des_key); +#endif + +#if 0 + CHAPDEBUG(LOG_INFO, ("MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n", + key[0], key[1], key[2], key[3], key[4], key[5], key[6])); + CHAPDEBUG(LOG_INFO, ("MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n", + des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7])); +#endif +} + +static void +ChapMS_NT( char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len, + MS_ChapResponse *response) +{ + int i; + MDstruct md4Context; + u_char unicodePassword[MAX_NT_PASSWORD * 2]; + static int low_byte_first = -1; + + LWIP_UNUSED_ARG(rchallenge_len); + + /* Initialize the Unicode version of the secret (== password). */ + /* This implicitly supports 8-bit ISO8859/1 characters. */ + BZERO(unicodePassword, sizeof(unicodePassword)); + for (i = 0; i < secret_len; i++) { + unicodePassword[i * 2] = (u_char)secret[i]; + } + MDbegin(&md4Context); + MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8); /* Unicode is 2 bytes/char, *8 for bit count */ + + if (low_byte_first == -1) { + low_byte_first = (PP_HTONS((unsigned short int)1) != 1); + } + if (low_byte_first == 0) { + /* @todo: arg type - u_long* or u_int* ? */ + MDreverse((unsigned int*)&md4Context); /* sfb 961105 */ + } + + MDupdate(&md4Context, NULL, 0); /* Tell MD4 we're done */ + + ChallengeResponse((u_char*)rchallenge, (u_char*)md4Context.buffer, response->NTResp); +} + +#ifdef MSLANMAN +static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */ + +static void +ChapMS_LANMan( char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len, + MS_ChapResponse *response) +{ + int i; + u_char UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */ + u_char PasswordHash[16]; + + /* LANMan password is case insensitive */ + BZERO(UcasePassword, sizeof(UcasePassword)); + for (i = 0; i < secret_len; i++) { + UcasePassword[i] = (u_char)toupper(secret[i]); + } + DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 ); + DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 ); + ChallengeResponse(rchallenge, PasswordHash, response->LANManResp); +} +#endif + +void +ChapMS( chap_state *cstate, char *rchallenge, int rchallenge_len, char *secret, int secret_len) +{ + MS_ChapResponse response; +#ifdef MSLANMAN + extern int ms_lanman; +#endif + +#if 0 + CHAPDEBUG(LOG_INFO, ("ChapMS: secret is '%.*s'\n", secret_len, secret)); +#endif + BZERO(&response, sizeof(response)); + + /* Calculate both always */ + ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response); + +#ifdef MSLANMAN + ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response); + + /* prefered method is set by option */ + response.UseNT = !ms_lanman; +#else + response.UseNT = 1; +#endif + + BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN); + cstate->resp_length = MS_CHAP_RESPONSE_LEN; +} + +#endif /* MSCHAP_SUPPORT */ + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.h new file mode 100644 index 0000000..df070fb --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.h @@ -0,0 +1,64 @@ +/***************************************************************************** +* chpms.h - Network Microsoft Challenge Handshake Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-01-30 Guy Lancaster , Global Election Systems Inc. +* Original built from BSD network code. +******************************************************************************/ +/* + * chap.h - Challenge Handshake Authentication Protocol definitions. + * + * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. + * http://www.strataware.com/ + * + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Eric Rosenquist. The name of the author may not be used to + * endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: chpms.h,v 1.5 2007/12/19 20:47:23 fbernon Exp $ + */ + +#ifndef CHPMS_H +#define CHPMS_H + +#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */ + +void ChapMS (chap_state *, char *, int, char *, int); + +#endif /* CHPMS_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.c new file mode 100644 index 0000000..2e73c5a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.c @@ -0,0 +1,890 @@ +/***************************************************************************** +* fsm.c - Network Control Protocol Finite State Machine program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-01 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD fsm.c. +*****************************************************************************/ +/* + * fsm.c - {Link, IP} Control Protocol Finite State Machine. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* + * TODO: + * Randomize fsm id on link/init. + * Deal with variable outgoing MTU. + */ + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "ppp.h" +#include "pppdebug.h" + +#include "fsm.h" + +#include + +#if PPP_DEBUG +static const char *ppperr_strerr[] = { + "LS_INITIAL", /* LS_INITIAL 0 */ + "LS_STARTING", /* LS_STARTING 1 */ + "LS_CLOSED", /* LS_CLOSED 2 */ + "LS_STOPPED", /* LS_STOPPED 3 */ + "LS_CLOSING", /* LS_CLOSING 4 */ + "LS_STOPPING", /* LS_STOPPING 5 */ + "LS_REQSENT", /* LS_REQSENT 6 */ + "LS_ACKRCVD", /* LS_ACKRCVD 7 */ + "LS_ACKSENT", /* LS_ACKSENT 8 */ + "LS_OPENED" /* LS_OPENED 9 */ +}; +#endif /* PPP_DEBUG */ + +static void fsm_timeout (void *); +static void fsm_rconfreq (fsm *, u_char, u_char *, int); +static void fsm_rconfack (fsm *, int, u_char *, int); +static void fsm_rconfnakrej (fsm *, int, int, u_char *, int); +static void fsm_rtermreq (fsm *, int, u_char *, int); +static void fsm_rtermack (fsm *); +static void fsm_rcoderej (fsm *, u_char *, int); +static void fsm_sconfreq (fsm *, int); + +#define PROTO_NAME(f) ((f)->callbacks->proto_name) + +int peer_mru[NUM_PPP]; + + +/* + * fsm_init - Initialize fsm. + * + * Initialize fsm state. + */ +void +fsm_init(fsm *f) +{ + f->state = LS_INITIAL; + f->flags = 0; + f->id = 0; /* XXX Start with random id? */ + f->timeouttime = FSM_DEFTIMEOUT; + f->maxconfreqtransmits = FSM_DEFMAXCONFREQS; + f->maxtermtransmits = FSM_DEFMAXTERMREQS; + f->maxnakloops = FSM_DEFMAXNAKLOOPS; + f->term_reason_len = 0; +} + + +/* + * fsm_lowerup - The lower layer is up. + */ +void +fsm_lowerup(fsm *f) +{ + int oldState = f->state; + + LWIP_UNUSED_ARG(oldState); + + switch( f->state ) { + case LS_INITIAL: + f->state = LS_CLOSED; + break; + + case LS_STARTING: + if( f->flags & OPT_SILENT ) { + f->state = LS_STOPPED; + } else { + /* Send an initial configure-request */ + fsm_sconfreq(f, 0); + f->state = LS_REQSENT; + } + break; + + default: + FSMDEBUG(LOG_INFO, ("%s: Up event in state %d (%s)!\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + } + + FSMDEBUG(LOG_INFO, ("%s: lowerup state %d (%s) -> %d (%s)\n", + PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state])); +} + + +/* + * fsm_lowerdown - The lower layer is down. + * + * Cancel all timeouts and inform upper layers. + */ +void +fsm_lowerdown(fsm *f) +{ + int oldState = f->state; + + LWIP_UNUSED_ARG(oldState); + + switch( f->state ) { + case LS_CLOSED: + f->state = LS_INITIAL; + break; + + case LS_STOPPED: + f->state = LS_STARTING; + if( f->callbacks->starting ) { + (*f->callbacks->starting)(f); + } + break; + + case LS_CLOSING: + f->state = LS_INITIAL; + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + break; + + case LS_STOPPING: + case LS_REQSENT: + case LS_ACKRCVD: + case LS_ACKSENT: + f->state = LS_STARTING; + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + break; + + case LS_OPENED: + if( f->callbacks->down ) { + (*f->callbacks->down)(f); + } + f->state = LS_STARTING; + break; + + default: + FSMDEBUG(LOG_INFO, ("%s: Down event in state %d (%s)!\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + } + + FSMDEBUG(LOG_INFO, ("%s: lowerdown state %d (%s) -> %d (%s)\n", + PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state])); +} + + +/* + * fsm_open - Link is allowed to come up. + */ +void +fsm_open(fsm *f) +{ + int oldState = f->state; + + LWIP_UNUSED_ARG(oldState); + + switch( f->state ) { + case LS_INITIAL: + f->state = LS_STARTING; + if( f->callbacks->starting ) { + (*f->callbacks->starting)(f); + } + break; + + case LS_CLOSED: + if( f->flags & OPT_SILENT ) { + f->state = LS_STOPPED; + } else { + /* Send an initial configure-request */ + fsm_sconfreq(f, 0); + f->state = LS_REQSENT; + } + break; + + case LS_CLOSING: + f->state = LS_STOPPING; + /* fall through */ + case LS_STOPPED: + case LS_OPENED: + if( f->flags & OPT_RESTART ) { + fsm_lowerdown(f); + fsm_lowerup(f); + } + break; + } + + FSMDEBUG(LOG_INFO, ("%s: open state %d (%s) -> %d (%s)\n", + PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state])); +} + +#if 0 /* backport pppd 2.4.4b1; */ +/* + * terminate_layer - Start process of shutting down the FSM + * + * Cancel any timeout running, notify upper layers we're done, and + * send a terminate-request message as configured. + */ +static void +terminate_layer(fsm *f, int nextstate) +{ + /* @todo */ +} +#endif + +/* + * fsm_close - Start closing connection. + * + * Cancel timeouts and either initiate close or possibly go directly to + * the LS_CLOSED state. + */ +void +fsm_close(fsm *f, char *reason) +{ + int oldState = f->state; + + LWIP_UNUSED_ARG(oldState); + + f->term_reason = reason; + f->term_reason_len = (reason == NULL ? 0 : (int)strlen(reason)); + switch( f->state ) { + case LS_STARTING: + f->state = LS_INITIAL; + break; + case LS_STOPPED: + f->state = LS_CLOSED; + break; + case LS_STOPPING: + f->state = LS_CLOSING; + break; + + case LS_REQSENT: + case LS_ACKRCVD: + case LS_ACKSENT: + case LS_OPENED: + if( f->state != LS_OPENED ) { + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + } else if( f->callbacks->down ) { + (*f->callbacks->down)(f); /* Inform upper layers we're down */ + } + /* Init restart counter, send Terminate-Request */ + f->retransmits = f->maxtermtransmits; + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, f->timeouttime); + --f->retransmits; + + f->state = LS_CLOSING; + break; + } + + FSMDEBUG(LOG_INFO, ("%s: close reason=%s state %d (%s) -> %d (%s)\n", + PROTO_NAME(f), reason, oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state])); +} + + +/* + * fsm_timeout - Timeout expired. + */ +static void +fsm_timeout(void *arg) +{ + fsm *f = (fsm *) arg; + + switch (f->state) { + case LS_CLOSING: + case LS_STOPPING: + if( f->retransmits <= 0 ) { + FSMDEBUG(LOG_WARNING, ("%s: timeout sending Terminate-Request state=%d (%s)\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + /* + * We've waited for an ack long enough. Peer probably heard us. + */ + f->state = (f->state == LS_CLOSING)? LS_CLOSED: LS_STOPPED; + if( f->callbacks->finished ) { + (*f->callbacks->finished)(f); + } + } else { + FSMDEBUG(LOG_WARNING, ("%s: timeout resending Terminate-Requests state=%d (%s)\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + /* Send Terminate-Request */ + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, f->timeouttime); + --f->retransmits; + } + break; + + case LS_REQSENT: + case LS_ACKRCVD: + case LS_ACKSENT: + if (f->retransmits <= 0) { + FSMDEBUG(LOG_WARNING, ("%s: timeout sending Config-Requests state=%d (%s)\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + f->state = LS_STOPPED; + if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) { + (*f->callbacks->finished)(f); + } + } else { + FSMDEBUG(LOG_WARNING, ("%s: timeout resending Config-Request state=%d (%s)\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + /* Retransmit the configure-request */ + if (f->callbacks->retransmit) { + (*f->callbacks->retransmit)(f); + } + fsm_sconfreq(f, 1); /* Re-send Configure-Request */ + if( f->state == LS_ACKRCVD ) { + f->state = LS_REQSENT; + } + } + break; + + default: + FSMDEBUG(LOG_INFO, ("%s: UNHANDLED timeout event in state %d (%s)!\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + } +} + + +/* + * fsm_input - Input packet. + */ +void +fsm_input(fsm *f, u_char *inpacket, int l) +{ + u_char *inp = inpacket; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + if (l < HEADERLEN) { + FSMDEBUG(LOG_WARNING, ("fsm_input(%x): Rcvd short header.\n", + f->protocol)); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < HEADERLEN) { + FSMDEBUG(LOG_INFO, ("fsm_input(%x): Rcvd illegal length.\n", + f->protocol)); + return; + } + if (len > l) { + FSMDEBUG(LOG_INFO, ("fsm_input(%x): Rcvd short packet.\n", + f->protocol)); + return; + } + len -= HEADERLEN; /* subtract header length */ + + if( f->state == LS_INITIAL || f->state == LS_STARTING ) { + FSMDEBUG(LOG_INFO, ("fsm_input(%x): Rcvd packet in state %d (%s).\n", + f->protocol, f->state, ppperr_strerr[f->state])); + return; + } + FSMDEBUG(LOG_INFO, ("fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l)); + /* + * Action depends on code. + */ + switch (code) { + case CONFREQ: + fsm_rconfreq(f, id, inp, len); + break; + + case CONFACK: + fsm_rconfack(f, id, inp, len); + break; + + case CONFNAK: + case CONFREJ: + fsm_rconfnakrej(f, code, id, inp, len); + break; + + case TERMREQ: + fsm_rtermreq(f, id, inp, len); + break; + + case TERMACK: + fsm_rtermack(f); + break; + + case CODEREJ: + fsm_rcoderej(f, inp, len); + break; + + default: + FSMDEBUG(LOG_INFO, ("fsm_input(%s): default: \n", PROTO_NAME(f))); + if( !f->callbacks->extcode || + !(*f->callbacks->extcode)(f, code, id, inp, len) ) { + fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN); + } + break; + } +} + + +/* + * fsm_rconfreq - Receive Configure-Request. + */ +static void +fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len) +{ + int code, reject_if_disagree; + + FSMDEBUG(LOG_INFO, ("fsm_rconfreq(%s): Rcvd id %d state=%d (%s)\n", + PROTO_NAME(f), id, f->state, ppperr_strerr[f->state])); + switch( f->state ) { + case LS_CLOSED: + /* Go away, we're closed */ + fsm_sdata(f, TERMACK, id, NULL, 0); + return; + case LS_CLOSING: + case LS_STOPPING: + return; + + case LS_OPENED: + /* Go down and restart negotiation */ + if( f->callbacks->down ) { + (*f->callbacks->down)(f); /* Inform upper layers */ + } + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + break; + + case LS_STOPPED: + /* Negotiation started by our peer */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = LS_REQSENT; + break; + } + + /* + * Pass the requested configuration options + * to protocol-specific code for checking. + */ + if (f->callbacks->reqci) { /* Check CI */ + reject_if_disagree = (f->nakloops >= f->maxnakloops); + code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree); + } else if (len) { + code = CONFREJ; /* Reject all CI */ + } else { + code = CONFACK; + } + + /* send the Ack, Nak or Rej to the peer */ + fsm_sdata(f, (u_char)code, id, inp, len); + + if (code == CONFACK) { + if (f->state == LS_ACKRCVD) { + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + f->state = LS_OPENED; + if (f->callbacks->up) { + (*f->callbacks->up)(f); /* Inform upper layers */ + } + } else { + f->state = LS_ACKSENT; + } + f->nakloops = 0; + } else { + /* we sent CONFACK or CONFREJ */ + if (f->state != LS_ACKRCVD) { + f->state = LS_REQSENT; + } + if( code == CONFNAK ) { + ++f->nakloops; + } + } +} + + +/* + * fsm_rconfack - Receive Configure-Ack. + */ +static void +fsm_rconfack(fsm *f, int id, u_char *inp, int len) +{ + FSMDEBUG(LOG_INFO, ("fsm_rconfack(%s): Rcvd id %d state=%d (%s)\n", + PROTO_NAME(f), id, f->state, ppperr_strerr[f->state])); + + if (id != f->reqid || f->seen_ack) { /* Expected id? */ + return; /* Nope, toss... */ + } + if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): (len == 0)) ) { + /* Ack is bad - ignore it */ + FSMDEBUG(LOG_INFO, ("%s: received bad Ack (length %d)\n", + PROTO_NAME(f), len)); + return; + } + f->seen_ack = 1; + + switch (f->state) { + case LS_CLOSED: + case LS_STOPPED: + fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); + break; + + case LS_REQSENT: + f->state = LS_ACKRCVD; + f->retransmits = f->maxconfreqtransmits; + break; + + case LS_ACKRCVD: + /* Huh? an extra valid Ack? oh well... */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + fsm_sconfreq(f, 0); + f->state = LS_REQSENT; + break; + + case LS_ACKSENT: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + f->state = LS_OPENED; + f->retransmits = f->maxconfreqtransmits; + if (f->callbacks->up) { + (*f->callbacks->up)(f); /* Inform upper layers */ + } + break; + + case LS_OPENED: + /* Go down and restart negotiation */ + if (f->callbacks->down) { + (*f->callbacks->down)(f); /* Inform upper layers */ + } + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = LS_REQSENT; + break; + } +} + + +/* + * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject. + */ +static void +fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len) +{ + int (*proc) (fsm *, u_char *, int); + int ret; + + FSMDEBUG(LOG_INFO, ("fsm_rconfnakrej(%s): Rcvd id %d state=%d (%s)\n", + PROTO_NAME(f), id, f->state, ppperr_strerr[f->state])); + + if (id != f->reqid || f->seen_ack) { /* Expected id? */ + return; /* Nope, toss... */ + } + proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci; + if (!proc || !((ret = proc(f, inp, len)))) { + /* Nak/reject is bad - ignore it */ + FSMDEBUG(LOG_INFO, ("%s: received bad %s (length %d)\n", + PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len)); + return; + } + f->seen_ack = 1; + + switch (f->state) { + case LS_CLOSED: + case LS_STOPPED: + fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); + break; + + case LS_REQSENT: + case LS_ACKSENT: + /* They didn't agree to what we wanted - try another request */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + if (ret < 0) { + f->state = LS_STOPPED; /* kludge for stopping CCP */ + } else { + fsm_sconfreq(f, 0); /* Send Configure-Request */ + } + break; + + case LS_ACKRCVD: + /* Got a Nak/reject when we had already had an Ack?? oh well... */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + fsm_sconfreq(f, 0); + f->state = LS_REQSENT; + break; + + case LS_OPENED: + /* Go down and restart negotiation */ + if (f->callbacks->down) { + (*f->callbacks->down)(f); /* Inform upper layers */ + } + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = LS_REQSENT; + break; + } +} + + +/* + * fsm_rtermreq - Receive Terminate-Req. + */ +static void +fsm_rtermreq(fsm *f, int id, u_char *p, int len) +{ + LWIP_UNUSED_ARG(p); + + FSMDEBUG(LOG_INFO, ("fsm_rtermreq(%s): Rcvd id %d state=%d (%s)\n", + PROTO_NAME(f), id, f->state, ppperr_strerr[f->state])); + + switch (f->state) { + case LS_ACKRCVD: + case LS_ACKSENT: + f->state = LS_REQSENT; /* Start over but keep trying */ + break; + + case LS_OPENED: + if (len > 0) { + FSMDEBUG(LOG_INFO, ("%s terminated by peer (%p)\n", PROTO_NAME(f), p)); + } else { + FSMDEBUG(LOG_INFO, ("%s terminated by peer\n", PROTO_NAME(f))); + } + if (f->callbacks->down) { + (*f->callbacks->down)(f); /* Inform upper layers */ + } + f->retransmits = 0; + f->state = LS_STOPPING; + TIMEOUT(fsm_timeout, f, f->timeouttime); + break; + } + + fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); +} + + +/* + * fsm_rtermack - Receive Terminate-Ack. + */ +static void +fsm_rtermack(fsm *f) +{ + FSMDEBUG(LOG_INFO, ("fsm_rtermack(%s): state=%d (%s)\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + + switch (f->state) { + case LS_CLOSING: + UNTIMEOUT(fsm_timeout, f); + f->state = LS_CLOSED; + if( f->callbacks->finished ) { + (*f->callbacks->finished)(f); + } + break; + + case LS_STOPPING: + UNTIMEOUT(fsm_timeout, f); + f->state = LS_STOPPED; + if( f->callbacks->finished ) { + (*f->callbacks->finished)(f); + } + break; + + case LS_ACKRCVD: + f->state = LS_REQSENT; + break; + + case LS_OPENED: + if (f->callbacks->down) { + (*f->callbacks->down)(f); /* Inform upper layers */ + } + fsm_sconfreq(f, 0); + break; + default: + FSMDEBUG(LOG_INFO, ("fsm_rtermack(%s): UNHANDLED state=%d (%s)!!!\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + } +} + + +/* + * fsm_rcoderej - Receive an Code-Reject. + */ +static void +fsm_rcoderej(fsm *f, u_char *inp, int len) +{ + u_char code, id; + + FSMDEBUG(LOG_INFO, ("fsm_rcoderej(%s): state=%d (%s)\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + + if (len < HEADERLEN) { + FSMDEBUG(LOG_INFO, ("fsm_rcoderej: Rcvd short Code-Reject packet!\n")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + FSMDEBUG(LOG_WARNING, ("%s: Rcvd Code-Reject for code %d, id %d\n", + PROTO_NAME(f), code, id)); + + if( f->state == LS_ACKRCVD ) { + f->state = LS_REQSENT; + } +} + + +/* + * fsm_protreject - Peer doesn't speak this protocol. + * + * Treat this as a catastrophic error (RXJ-). + */ +void +fsm_protreject(fsm *f) +{ + switch( f->state ) { + case LS_CLOSING: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + /* fall through */ + case LS_CLOSED: + f->state = LS_CLOSED; + if( f->callbacks->finished ) { + (*f->callbacks->finished)(f); + } + break; + + case LS_STOPPING: + case LS_REQSENT: + case LS_ACKRCVD: + case LS_ACKSENT: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + /* fall through */ + case LS_STOPPED: + f->state = LS_STOPPED; + if( f->callbacks->finished ) { + (*f->callbacks->finished)(f); + } + break; + + case LS_OPENED: + if( f->callbacks->down ) { + (*f->callbacks->down)(f); + } + /* Init restart counter, send Terminate-Request */ + f->retransmits = f->maxtermtransmits; + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, f->timeouttime); + --f->retransmits; + + f->state = LS_STOPPING; + break; + + default: + FSMDEBUG(LOG_INFO, ("%s: Protocol-reject event in state %d (%s)!\n", + PROTO_NAME(f), f->state, ppperr_strerr[f->state])); + } +} + + +/* + * fsm_sconfreq - Send a Configure-Request. + */ +static void +fsm_sconfreq(fsm *f, int retransmit) +{ + u_char *outp; + int cilen; + + if( f->state != LS_REQSENT && f->state != LS_ACKRCVD && f->state != LS_ACKSENT ) { + /* Not currently negotiating - reset options */ + if( f->callbacks->resetci ) { + (*f->callbacks->resetci)(f); + } + f->nakloops = 0; + } + + if( !retransmit ) { + /* New request - reset retransmission counter, use new ID */ + f->retransmits = f->maxconfreqtransmits; + f->reqid = ++f->id; + } + + f->seen_ack = 0; + + /* + * Make up the request packet + */ + outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN; + if( f->callbacks->cilen && f->callbacks->addci ) { + cilen = (*f->callbacks->cilen)(f); + if( cilen > peer_mru[f->unit] - (int)HEADERLEN ) { + cilen = peer_mru[f->unit] - HEADERLEN; + } + if (f->callbacks->addci) { + (*f->callbacks->addci)(f, outp, &cilen); + } + } else { + cilen = 0; + } + + /* send the request to our peer */ + fsm_sdata(f, CONFREQ, f->reqid, outp, cilen); + + /* start the retransmit timer */ + --f->retransmits; + TIMEOUT(fsm_timeout, f, f->timeouttime); + + FSMDEBUG(LOG_INFO, ("%s: sending Configure-Request, id %d\n", + PROTO_NAME(f), f->reqid)); +} + + +/* + * fsm_sdata - Send some data. + * + * Used for all packets sent to our peer by this module. + */ +void +fsm_sdata( fsm *f, u_char code, u_char id, u_char *data, int datalen) +{ + u_char *outp; + int outlen; + + /* Adjust length to be smaller than MTU */ + outp = outpacket_buf[f->unit]; + if (datalen > peer_mru[f->unit] - (int)HEADERLEN) { + datalen = peer_mru[f->unit] - HEADERLEN; + } + if (datalen && data != outp + PPP_HDRLEN + HEADERLEN) { + BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen); + } + outlen = datalen + HEADERLEN; + MAKEHEADER(outp, f->protocol); + PUTCHAR(code, outp); + PUTCHAR(id, outp); + PUTSHORT(outlen, outp); + pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN); + FSMDEBUG(LOG_INFO, ("fsm_sdata(%s): Sent code %d,%d,%d.\n", + PROTO_NAME(f), code, id, outlen)); +} + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.h new file mode 100644 index 0000000..8d41b5f --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.h @@ -0,0 +1,157 @@ +/***************************************************************************** +* fsm.h - Network Control Protocol Finite State Machine header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD code. +*****************************************************************************/ +/* + * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: fsm.h,v 1.5 2009/12/31 17:08:08 goldsimon Exp $ + */ + +#ifndef FSM_H +#define FSM_H + +/* + * LCP Packet header = Code, id, length. + */ +#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) + + +/* + * CP (LCP, IPCP, etc.) codes. + */ +#define CONFREQ 1 /* Configuration Request */ +#define CONFACK 2 /* Configuration Ack */ +#define CONFNAK 3 /* Configuration Nak */ +#define CONFREJ 4 /* Configuration Reject */ +#define TERMREQ 5 /* Termination Request */ +#define TERMACK 6 /* Termination Ack */ +#define CODEREJ 7 /* Code Reject */ + + +/* + * Each FSM is described by an fsm structure and fsm callbacks. + */ +typedef struct fsm { + int unit; /* Interface unit number */ + u_short protocol; /* Data Link Layer Protocol field value */ + int state; /* State */ + int flags; /* Contains option bits */ + u_char id; /* Current id */ + u_char reqid; /* Current request id */ + u_char seen_ack; /* Have received valid Ack/Nak/Rej to Req */ + int timeouttime; /* Timeout time in milliseconds */ + int maxconfreqtransmits; /* Maximum Configure-Request transmissions */ + int retransmits; /* Number of retransmissions left */ + int maxtermtransmits; /* Maximum Terminate-Request transmissions */ + int nakloops; /* Number of nak loops since last ack */ + int maxnakloops; /* Maximum number of nak loops tolerated */ + struct fsm_callbacks* callbacks; /* Callback routines */ + char* term_reason; /* Reason for closing protocol */ + int term_reason_len; /* Length of term_reason */ +} fsm; + + +typedef struct fsm_callbacks { + void (*resetci)(fsm*); /* Reset our Configuration Information */ + int (*cilen)(fsm*); /* Length of our Configuration Information */ + void (*addci)(fsm*, u_char*, int*); /* Add our Configuration Information */ + int (*ackci)(fsm*, u_char*, int); /* ACK our Configuration Information */ + int (*nakci)(fsm*, u_char*, int); /* NAK our Configuration Information */ + int (*rejci)(fsm*, u_char*, int); /* Reject our Configuration Information */ + int (*reqci)(fsm*, u_char*, int*, int); /* Request peer's Configuration Information */ + void (*up)(fsm*); /* Called when fsm reaches LS_OPENED state */ + void (*down)(fsm*); /* Called when fsm leaves LS_OPENED state */ + void (*starting)(fsm*); /* Called when we want the lower layer */ + void (*finished)(fsm*); /* Called when we don't want the lower layer */ + void (*protreject)(int); /* Called when Protocol-Reject received */ + void (*retransmit)(fsm*); /* Retransmission is necessary */ + int (*extcode)(fsm*, int, u_char, u_char*, int); /* Called when unknown code received */ + char *proto_name; /* String name for protocol (for messages) */ +} fsm_callbacks; + + +/* + * Link states. + */ +#define LS_INITIAL 0 /* Down, hasn't been opened */ +#define LS_STARTING 1 /* Down, been opened */ +#define LS_CLOSED 2 /* Up, hasn't been opened */ +#define LS_STOPPED 3 /* Open, waiting for down event */ +#define LS_CLOSING 4 /* Terminating the connection, not open */ +#define LS_STOPPING 5 /* Terminating, but open */ +#define LS_REQSENT 6 /* We've sent a Config Request */ +#define LS_ACKRCVD 7 /* We've received a Config Ack */ +#define LS_ACKSENT 8 /* We've sent a Config Ack */ +#define LS_OPENED 9 /* Connection available */ + +/* + * Flags - indicate options controlling FSM operation + */ +#define OPT_PASSIVE 1 /* Don't die if we don't get a response */ +#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */ +#define OPT_SILENT 4 /* Wait for peer to speak first */ + + +/* + * Prototypes + */ +void fsm_init (fsm*); +void fsm_lowerup (fsm*); +void fsm_lowerdown (fsm*); +void fsm_open (fsm*); +void fsm_close (fsm*, char*); +void fsm_input (fsm*, u_char*, int); +void fsm_protreject (fsm*); +void fsm_sdata (fsm*, u_char, u_char, u_char*, int); + + +/* + * Variables + */ +extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */ + +#endif /* FSM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.c new file mode 100644 index 0000000..461a600 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.c @@ -0,0 +1,1411 @@ +/** In contrast to pppd 2.3.1, DNS support has been added, proxy-ARP and + dial-on-demand has been stripped. */ +/***************************************************************************** +* ipcp.c - Network PPP IP Control Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-08 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ +/* + * ipcp.c - PPP IP Control Protocol. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "ppp.h" +#include "pppdebug.h" + +#include "auth.h" +#include "fsm.h" +#include "vj.h" +#include "ipcp.h" + +#include "lwip/inet.h" + +#include + +/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */ + +/* global vars */ +ipcp_options ipcp_wantoptions[NUM_PPP]; /* Options that we want to request */ +ipcp_options ipcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ +ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ +ipcp_options ipcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ + +/* local vars */ +static int default_route_set[NUM_PPP]; /* Have set up a default route */ +static int cis_received[NUM_PPP]; /* # Conf-Reqs received */ + + +/* + * Callbacks for fsm code. (CI = Configuration Information) + */ +static void ipcp_resetci (fsm *); /* Reset our CI */ +static int ipcp_cilen (fsm *); /* Return length of our CI */ +static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */ +static int ipcp_ackci (fsm *, u_char *, int); /* Peer ack'd our CI */ +static int ipcp_nakci (fsm *, u_char *, int); /* Peer nak'd our CI */ +static int ipcp_rejci (fsm *, u_char *, int); /* Peer rej'd our CI */ +static int ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */ +static void ipcp_up (fsm *); /* We're UP */ +static void ipcp_down (fsm *); /* We're DOWN */ +#if PPP_ADDITIONAL_CALLBACKS +static void ipcp_script (fsm *, char *); /* Run an up/down script */ +#endif +static void ipcp_finished (fsm *); /* Don't need lower layer */ + + +fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */ + + +static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */ + ipcp_resetci, /* Reset our Configuration Information */ + ipcp_cilen, /* Length of our Configuration Information */ + ipcp_addci, /* Add our Configuration Information */ + ipcp_ackci, /* ACK our Configuration Information */ + ipcp_nakci, /* NAK our Configuration Information */ + ipcp_rejci, /* Reject our Configuration Information */ + ipcp_reqci, /* Request peer's Configuration Information */ + ipcp_up, /* Called when fsm reaches LS_OPENED state */ + ipcp_down, /* Called when fsm leaves LS_OPENED state */ + NULL, /* Called when we want the lower layer up */ + ipcp_finished, /* Called when we want the lower layer down */ + NULL, /* Called when Protocol-Reject received */ + NULL, /* Retransmission is necessary */ + NULL, /* Called to handle protocol-specific codes */ + "IPCP" /* String name of protocol */ +}; + +/* + * Protocol entry points from main code. + */ +static void ipcp_init (int); +static void ipcp_open (int); +static void ipcp_close (int, char *); +static void ipcp_lowerup (int); +static void ipcp_lowerdown (int); +static void ipcp_input (int, u_char *, int); +static void ipcp_protrej (int); + + +struct protent ipcp_protent = { + PPP_IPCP, + ipcp_init, + ipcp_input, + ipcp_protrej, + ipcp_lowerup, + ipcp_lowerdown, + ipcp_open, + ipcp_close, +#if PPP_ADDITIONAL_CALLBACKS + ipcp_printpkt, + NULL, +#endif /* PPP_ADDITIONAL_CALLBACKS */ + 1, + "IPCP", +#if PPP_ADDITIONAL_CALLBACKS + ip_check_options, + NULL, + ip_active_pkt +#endif /* PPP_ADDITIONAL_CALLBACKS */ +}; + +static void ipcp_clear_addrs (int); + +/* + * Lengths of configuration options. + */ +#define CILEN_VOID 2 +#define CILEN_COMPRESS 4 /* min length for compression protocol opt. */ +#define CILEN_VJ 6 /* length for RFC1332 Van-Jacobson opt. */ +#define CILEN_ADDR 6 /* new-style single address option */ +#define CILEN_ADDRS 10 /* old-style dual address option */ + + +#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ + (x) == CONFNAK ? "NAK" : "REJ") + + +/* + * ipcp_init - Initialize IPCP. + */ +static void +ipcp_init(int unit) +{ + fsm *f = &ipcp_fsm[unit]; + ipcp_options *wo = &ipcp_wantoptions[unit]; + ipcp_options *ao = &ipcp_allowoptions[unit]; + + f->unit = unit; + f->protocol = PPP_IPCP; + f->callbacks = &ipcp_callbacks; + fsm_init(&ipcp_fsm[unit]); + + memset(wo, 0, sizeof(*wo)); + memset(ao, 0, sizeof(*ao)); + + wo->neg_addr = 1; + wo->ouraddr = 0; +#if VJ_SUPPORT + wo->neg_vj = 1; +#else /* VJ_SUPPORT */ + wo->neg_vj = 0; +#endif /* VJ_SUPPORT */ + wo->vj_protocol = IPCP_VJ_COMP; + wo->maxslotindex = MAX_SLOTS - 1; + wo->cflag = 0; + wo->default_route = 1; + + ao->neg_addr = 1; +#if VJ_SUPPORT + ao->neg_vj = 1; +#else /* VJ_SUPPORT */ + ao->neg_vj = 0; +#endif /* VJ_SUPPORT */ + ao->maxslotindex = MAX_SLOTS - 1; + ao->cflag = 1; + ao->default_route = 1; +} + + +/* + * ipcp_open - IPCP is allowed to come up. + */ +static void +ipcp_open(int unit) +{ + fsm_open(&ipcp_fsm[unit]); +} + + +/* + * ipcp_close - Take IPCP down. + */ +static void +ipcp_close(int unit, char *reason) +{ + fsm_close(&ipcp_fsm[unit], reason); +} + + +/* + * ipcp_lowerup - The lower layer is up. + */ +static void +ipcp_lowerup(int unit) +{ + fsm_lowerup(&ipcp_fsm[unit]); +} + + +/* + * ipcp_lowerdown - The lower layer is down. + */ +static void +ipcp_lowerdown(int unit) +{ + fsm_lowerdown(&ipcp_fsm[unit]); +} + + +/* + * ipcp_input - Input IPCP packet. + */ +static void +ipcp_input(int unit, u_char *p, int len) +{ + fsm_input(&ipcp_fsm[unit], p, len); +} + + +/* + * ipcp_protrej - A Protocol-Reject was received for IPCP. + * + * Pretend the lower layer went down, so we shut up. + */ +static void +ipcp_protrej(int unit) +{ + fsm_lowerdown(&ipcp_fsm[unit]); +} + + +/* + * ipcp_resetci - Reset our CI. + */ +static void +ipcp_resetci(fsm *f) +{ + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + + wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr; + if (wo->ouraddr == 0) { + wo->accept_local = 1; + } + if (wo->hisaddr == 0) { + wo->accept_remote = 1; + } + /* Request DNS addresses from the peer */ + wo->req_dns1 = ppp_settings.usepeerdns; + wo->req_dns2 = ppp_settings.usepeerdns; + ipcp_gotoptions[f->unit] = *wo; + cis_received[f->unit] = 0; +} + + +/* + * ipcp_cilen - Return length of our CI. + */ +static int +ipcp_cilen(fsm *f) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + ipcp_options *ho = &ipcp_hisoptions[f->unit]; + +#define LENCIVJ(neg, old) (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0) +#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0) +#define LENCIDNS(neg) (neg ? (CILEN_ADDR) : 0) + + /* + * First see if we want to change our options to the old + * forms because we have received old forms from the peer. + */ + if (wo->neg_addr && !go->neg_addr && !go->old_addrs) { + /* use the old style of address negotiation */ + go->neg_addr = 1; + go->old_addrs = 1; + } + if (wo->neg_vj && !go->neg_vj && !go->old_vj) { + /* try an older style of VJ negotiation */ + if (cis_received[f->unit] == 0) { + /* keep trying the new style until we see some CI from the peer */ + go->neg_vj = 1; + } else { + /* use the old style only if the peer did */ + if (ho->neg_vj && ho->old_vj) { + go->neg_vj = 1; + go->old_vj = 1; + go->vj_protocol = ho->vj_protocol; + } + } + } + + return (LENCIADDR(go->neg_addr, go->old_addrs) + + LENCIVJ(go->neg_vj, go->old_vj) + + LENCIDNS(go->req_dns1) + + LENCIDNS(go->req_dns2)); +} + + +/* + * ipcp_addci - Add our desired CIs to a packet. + */ +static void +ipcp_addci(fsm *f, u_char *ucp, int *lenp) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + int len = *lenp; + +#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \ + if (neg) { \ + int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ + if (len >= vjlen) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(vjlen, ucp); \ + PUTSHORT(val, ucp); \ + if (!old) { \ + PUTCHAR(maxslotindex, ucp); \ + PUTCHAR(cflag, ucp); \ + } \ + len -= vjlen; \ + } else { \ + neg = 0; \ + } \ + } + +#define ADDCIADDR(opt, neg, old, val1, val2) \ + if (neg) { \ + int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ + if (len >= addrlen) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(addrlen, ucp); \ + l = ntohl(val1); \ + PUTLONG(l, ucp); \ + if (old) { \ + l = ntohl(val2); \ + PUTLONG(l, ucp); \ + } \ + len -= addrlen; \ + } else { \ + neg = 0; \ + } \ + } + +#define ADDCIDNS(opt, neg, addr) \ + if (neg) { \ + if (len >= CILEN_ADDR) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_ADDR, ucp); \ + l = ntohl(addr); \ + PUTLONG(l, ucp); \ + len -= CILEN_ADDR; \ + } else { \ + neg = 0; \ + } \ + } + + ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, + go->old_addrs, go->ouraddr, go->hisaddr); + + ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); + + ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); + + ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); + + *lenp -= len; +} + + +/* + * ipcp_ackci - Ack our CIs. + * + * Returns: + * 0 - Ack was bad. + * 1 - Ack was good. + */ +static int +ipcp_ackci(fsm *f, u_char *p, int len) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + u_short cilen, citype, cishort; + u32_t cilong; + u_char cimaxslotindex, cicflag; + + /* + * CIs must be in exactly the same order that we sent... + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ + +#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \ + if (neg) { \ + int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ + if ((len -= vjlen) < 0) { \ + goto bad; \ + } \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != vjlen || \ + citype != opt) { \ + goto bad; \ + } \ + GETSHORT(cishort, p); \ + if (cishort != val) { \ + goto bad; \ + } \ + if (!old) { \ + GETCHAR(cimaxslotindex, p); \ + if (cimaxslotindex != maxslotindex) { \ + goto bad; \ + } \ + GETCHAR(cicflag, p); \ + if (cicflag != cflag) { \ + goto bad; \ + } \ + } \ + } + +#define ACKCIADDR(opt, neg, old, val1, val2) \ + if (neg) { \ + int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ + u32_t l; \ + if ((len -= addrlen) < 0) { \ + goto bad; \ + } \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != addrlen || \ + citype != opt) { \ + goto bad; \ + } \ + GETLONG(l, p); \ + cilong = htonl(l); \ + if (val1 != cilong) { \ + goto bad; \ + } \ + if (old) { \ + GETLONG(l, p); \ + cilong = htonl(l); \ + if (val2 != cilong) { \ + goto bad; \ + } \ + } \ + } + +#define ACKCIDNS(opt, neg, addr) \ + if (neg) { \ + u32_t l; \ + if ((len -= CILEN_ADDR) < 0) { \ + goto bad; \ + } \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_ADDR || \ + citype != opt) { \ + goto bad; \ + } \ + GETLONG(l, p); \ + cilong = htonl(l); \ + if (addr != cilong) { \ + goto bad; \ + } \ + } + + ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, + go->old_addrs, go->ouraddr, go->hisaddr); + + ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); + + ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); + + ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) { + goto bad; + } + return (1); + +bad: + IPCPDEBUG(LOG_INFO, ("ipcp_ackci: received bad Ack!\n")); + return (0); +} + +/* + * ipcp_nakci - Peer has sent a NAK for some of our CIs. + * This should not modify any state if the Nak is bad + * or if IPCP is in the LS_OPENED state. + * + * Returns: + * 0 - Nak was bad. + * 1 - Nak was good. + */ +static int +ipcp_nakci(fsm *f, u_char *p, int len) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + u_char cimaxslotindex, cicflag; + u_char citype, cilen, *next; + u_short cishort; + u32_t ciaddr1, ciaddr2, l, cidnsaddr; + ipcp_options no; /* options we've seen Naks for */ + ipcp_options try; /* options to request next time */ + + BZERO(&no, sizeof(no)); + try = *go; + + /* + * Any Nak'd CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define NAKCIADDR(opt, neg, old, code) \ + if (go->neg && \ + len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \ + p[1] == cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + ciaddr1 = htonl(l); \ + if (old) { \ + GETLONG(l, p); \ + ciaddr2 = htonl(l); \ + no.old_addrs = 1; \ + } else { \ + ciaddr2 = 0; \ + } \ + no.neg = 1; \ + code \ + } + +#define NAKCIVJ(opt, neg, code) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + no.neg = 1; \ + code \ + } + +#define NAKCIDNS(opt, neg, code) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_ADDR) && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cidnsaddr = htonl(l); \ + no.neg = 1; \ + code \ + } + + /* + * Accept the peer's idea of {our,his} address, if different + * from our idea, only if the accept_{local,remote} flag is set. + */ + NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs, + if (go->accept_local && ciaddr1) { /* Do we know our address? */ + try.ouraddr = ciaddr1; + IPCPDEBUG(LOG_INFO, ("local IP address %s\n", + inet_ntoa(ciaddr1))); + } + if (go->accept_remote && ciaddr2) { /* Does he know his? */ + try.hisaddr = ciaddr2; + IPCPDEBUG(LOG_INFO, ("remote IP address %s\n", + inet_ntoa(ciaddr2))); + } + ); + + /* + * Accept the peer's value of maxslotindex provided that it + * is less than what we asked for. Turn off slot-ID compression + * if the peer wants. Send old-style compress-type option if + * the peer wants. + */ + NAKCIVJ(CI_COMPRESSTYPE, neg_vj, + if (cilen == CILEN_VJ) { + GETCHAR(cimaxslotindex, p); + GETCHAR(cicflag, p); + if (cishort == IPCP_VJ_COMP) { + try.old_vj = 0; + if (cimaxslotindex < go->maxslotindex) { + try.maxslotindex = cimaxslotindex; + } + if (!cicflag) { + try.cflag = 0; + } + } else { + try.neg_vj = 0; + } + } else { + if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) { + try.old_vj = 1; + try.vj_protocol = cishort; + } else { + try.neg_vj = 0; + } + } + ); + + NAKCIDNS(CI_MS_DNS1, req_dns1, + try.dnsaddr[0] = cidnsaddr; + IPCPDEBUG(LOG_INFO, ("primary DNS address %s\n", inet_ntoa(cidnsaddr))); + ); + + NAKCIDNS(CI_MS_DNS2, req_dns2, + try.dnsaddr[1] = cidnsaddr; + IPCPDEBUG(LOG_INFO, ("secondary DNS address %s\n", inet_ntoa(cidnsaddr))); + ); + + /* + * There may be remaining CIs, if the peer is requesting negotiation + * on an option that we didn't include in our request packet. + * If they want to negotiate about IP addresses, we comply. + * If they want us to ask for compression, we refuse. + */ + while (len > CILEN_VOID) { + GETCHAR(citype, p); + GETCHAR(cilen, p); + if( (len -= cilen) < 0 ) { + goto bad; + } + next = p + cilen - 2; + + switch (citype) { + case CI_COMPRESSTYPE: + if (go->neg_vj || no.neg_vj || + (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) { + goto bad; + } + no.neg_vj = 1; + break; + case CI_ADDRS: + if ((go->neg_addr && go->old_addrs) || no.old_addrs + || cilen != CILEN_ADDRS) { + goto bad; + } + try.neg_addr = 1; + try.old_addrs = 1; + GETLONG(l, p); + ciaddr1 = htonl(l); + if (ciaddr1 && go->accept_local) { + try.ouraddr = ciaddr1; + } + GETLONG(l, p); + ciaddr2 = htonl(l); + if (ciaddr2 && go->accept_remote) { + try.hisaddr = ciaddr2; + } + no.old_addrs = 1; + break; + case CI_ADDR: + if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) { + goto bad; + } + try.old_addrs = 0; + GETLONG(l, p); + ciaddr1 = htonl(l); + if (ciaddr1 && go->accept_local) { + try.ouraddr = ciaddr1; + } + if (try.ouraddr != 0) { + try.neg_addr = 1; + } + no.neg_addr = 1; + break; + } + p = next; + } + + /* If there is still anything left, this packet is bad. */ + if (len != 0) { + goto bad; + } + + /* + * OK, the Nak is good. Now we can update state. + */ + if (f->state != LS_OPENED) { + *go = try; + } + + return 1; + +bad: + IPCPDEBUG(LOG_INFO, ("ipcp_nakci: received bad Nak!\n")); + return 0; +} + + +/* + * ipcp_rejci - Reject some of our CIs. + */ +static int +ipcp_rejci(fsm *f, u_char *p, int len) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + u_char cimaxslotindex, ciflag, cilen; + u_short cishort; + u32_t cilong; + ipcp_options try; /* options to request next time */ + + try = *go; + /* + * Any Rejected CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define REJCIADDR(opt, neg, old, val1, val2) \ + if (go->neg && \ + len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \ + p[1] == cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = htonl(l); \ + /* Check rejected value. */ \ + if (cilong != val1) { \ + goto bad; \ + } \ + if (old) { \ + GETLONG(l, p); \ + cilong = htonl(l); \ + /* Check rejected value. */ \ + if (cilong != val2) { \ + goto bad; \ + } \ + } \ + try.neg = 0; \ + } + +#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \ + if (go->neg && \ + p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \ + len >= p[1] && \ + p[0] == opt) { \ + len -= p[1]; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + /* Check rejected value. */ \ + if (cishort != val) { \ + goto bad; \ + } \ + if (!old) { \ + GETCHAR(cimaxslotindex, p); \ + if (cimaxslotindex != maxslot) { \ + goto bad; \ + } \ + GETCHAR(ciflag, p); \ + if (ciflag != cflag) { \ + goto bad; \ + } \ + } \ + try.neg = 0; \ + } + +#define REJCIDNS(opt, neg, dnsaddr) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_ADDR) && \ + len >= cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = htonl(l); \ + /* Check rejected value. */ \ + if (cilong != dnsaddr) { \ + goto bad; \ + } \ + try.neg = 0; \ + } + + REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, + go->old_addrs, go->ouraddr, go->hisaddr); + + REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); + + REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]); + + REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) { + goto bad; + } + /* + * Now we can update state. + */ + if (f->state != LS_OPENED) { + *go = try; + } + return 1; + +bad: + IPCPDEBUG(LOG_INFO, ("ipcp_rejci: received bad Reject!\n")); + return 0; +} + + +/* + * ipcp_reqci - Check the peer's requested CIs and send appropriate response. + * + * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified + * appropriately. If reject_if_disagree is non-zero, doesn't return + * CONFNAK; returns CONFREJ if it can't return CONFACK. + */ +static int +ipcp_reqci(fsm *f, u_char *inp/* Requested CIs */,int *len/* Length of requested CIs */,int reject_if_disagree) +{ + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + ipcp_options *ho = &ipcp_hisoptions[f->unit]; + ipcp_options *ao = &ipcp_allowoptions[f->unit]; +#ifdef OLD_CI_ADDRS + ipcp_options *go = &ipcp_gotoptions[f->unit]; +#endif + u_char *cip, *next; /* Pointer to current and next CIs */ + u_short cilen, citype; /* Parsed len, type */ + u_short cishort; /* Parsed short value */ + u32_t tl, ciaddr1; /* Parsed address values */ +#ifdef OLD_CI_ADDRS + u32_t ciaddr2; /* Parsed address values */ +#endif + int rc = CONFACK; /* Final packet return code */ + int orc; /* Individual option return code */ + u_char *p; /* Pointer to next char to parse */ + u_char *ucp = inp; /* Pointer to current output char */ + int l = *len; /* Length left */ + u_char maxslotindex, cflag; + int d; + + cis_received[f->unit] = 1; + + /* + * Reset all his options. + */ + BZERO(ho, sizeof(*ho)); + + /* + * Process all his options. + */ + next = inp; + while (l) { + orc = CONFACK; /* Assume success */ + cip = p = next; /* Remember begining of CI */ + if (l < 2 || /* Not enough data for CI header or */ + p[1] < 2 || /* CI length too small or */ + p[1] > l) { /* CI length too big? */ + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: bad CI length!\n")); + orc = CONFREJ; /* Reject bad CI */ + cilen = (u_short)l;/* Reject till end of packet */ + l = 0; /* Don't loop again */ + goto endswitch; + } + GETCHAR(citype, p); /* Parse CI type */ + GETCHAR(cilen, p); /* Parse CI length */ + l -= cilen; /* Adjust remaining length */ + next += cilen; /* Step to next CI */ + + switch (citype) { /* Check CI type */ +#ifdef OLD_CI_ADDRS /* Need to save space... */ + case CI_ADDRS: + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: received ADDRS\n")); + if (!ao->neg_addr || + cilen != CILEN_ADDRS) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + + /* + * If he has no address, or if we both have his address but + * disagree about it, then NAK it with our idea. + * In particular, if we don't know his address, but he does, + * then accept it. + */ + GETLONG(tl, p); /* Parse source address (his) */ + ciaddr1 = htonl(tl); + IPCPDEBUG(LOG_INFO, ("his addr %s\n", inet_ntoa(ciaddr1))); + if (ciaddr1 != wo->hisaddr + && (ciaddr1 == 0 || !wo->accept_remote)) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(wo->hisaddr); + PUTLONG(tl, p); + } + } else if (ciaddr1 == 0 && wo->hisaddr == 0) { + /* + * If neither we nor he knows his address, reject the option. + */ + orc = CONFREJ; + wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ + break; + } + + /* + * If he doesn't know our address, or if we both have our address + * but disagree about it, then NAK it with our idea. + */ + GETLONG(tl, p); /* Parse desination address (ours) */ + ciaddr2 = htonl(tl); + IPCPDEBUG(LOG_INFO, ("our addr %s\n", inet_ntoa(ciaddr2))); + if (ciaddr2 != wo->ouraddr) { + if (ciaddr2 == 0 || !wo->accept_local) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(wo->ouraddr); + PUTLONG(tl, p); + } + } else { + go->ouraddr = ciaddr2; /* accept peer's idea */ + } + } + + ho->neg_addr = 1; + ho->old_addrs = 1; + ho->hisaddr = ciaddr1; + ho->ouraddr = ciaddr2; + break; +#endif + + case CI_ADDR: + if (!ao->neg_addr) { + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Reject ADDR not allowed\n")); + orc = CONFREJ; /* Reject CI */ + break; + } else if (cilen != CILEN_ADDR) { /* Check CI length */ + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Reject ADDR bad len\n")); + orc = CONFREJ; /* Reject CI */ + break; + } + + /* + * If he has no address, or if we both have his address but + * disagree about it, then NAK it with our idea. + * In particular, if we don't know his address, but he does, + * then accept it. + */ + GETLONG(tl, p); /* Parse source address (his) */ + ciaddr1 = htonl(tl); + if (ciaddr1 != wo->hisaddr + && (ciaddr1 == 0 || !wo->accept_remote)) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(wo->hisaddr); + PUTLONG(tl, p); + } + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1))); + } else if (ciaddr1 == 0 && wo->hisaddr == 0) { + /* + * Don't ACK an address of 0.0.0.0 - reject it instead. + */ + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1))); + orc = CONFREJ; + wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ + break; + } + + ho->neg_addr = 1; + ho->hisaddr = ciaddr1; + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1))); + break; + + case CI_MS_DNS1: + case CI_MS_DNS2: + /* Microsoft primary or secondary DNS request */ + d = citype == CI_MS_DNS2; + + /* If we do not have a DNS address then we cannot send it */ + if (ao->dnsaddr[d] == 0 || + cilen != CILEN_ADDR) { /* Check CI length */ + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting DNS%d Request\n", d+1)); + orc = CONFREJ; /* Reject CI */ + break; + } + GETLONG(tl, p); + if (htonl(tl) != ao->dnsaddr[d]) { + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Naking DNS%d Request %s\n", + d+1, inet_ntoa(tl))); + DECPTR(sizeof(u32_t), p); + tl = ntohl(ao->dnsaddr[d]); + PUTLONG(tl, p); + orc = CONFNAK; + } + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: received DNS%d Request\n", d+1)); + break; + + case CI_MS_WINS1: + case CI_MS_WINS2: + /* Microsoft primary or secondary WINS request */ + d = citype == CI_MS_WINS2; + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: received WINS%d Request\n", d+1)); + + /* If we do not have a DNS address then we cannot send it */ + if (ao->winsaddr[d] == 0 || + cilen != CILEN_ADDR) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + GETLONG(tl, p); + if (htonl(tl) != ao->winsaddr[d]) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(ao->winsaddr[d]); + PUTLONG(tl, p); + orc = CONFNAK; + } + break; + + case CI_COMPRESSTYPE: + if (!ao->neg_vj) { + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) { + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen)); + orc = CONFREJ; + break; + } + GETSHORT(cishort, p); + + if (!(cishort == IPCP_VJ_COMP || + (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) { + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort)); + orc = CONFREJ; + break; + } + + ho->neg_vj = 1; + ho->vj_protocol = cishort; + if (cilen == CILEN_VJ) { + GETCHAR(maxslotindex, p); + if (maxslotindex > ao->maxslotindex) { + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Naking VJ max slot %d\n", maxslotindex)); + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(1, p); + PUTCHAR(ao->maxslotindex, p); + } + } + GETCHAR(cflag, p); + if (cflag && !ao->cflag) { + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Naking VJ cflag %d\n", cflag)); + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(1, p); + PUTCHAR(wo->cflag, p); + } + } + ho->maxslotindex = maxslotindex; + ho->cflag = cflag; + } else { + ho->old_vj = 1; + ho->maxslotindex = MAX_SLOTS - 1; + ho->cflag = 1; + } + IPCPDEBUG(LOG_INFO, ( + "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n", + ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag)); + break; + + default: + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting unknown CI type %d\n", citype)); + orc = CONFREJ; + break; + } + +endswitch: + if (orc == CONFACK && /* Good CI */ + rc != CONFACK) { /* but prior CI wasnt? */ + continue; /* Don't send this one */ + } + + if (orc == CONFNAK) { /* Nak this CI? */ + if (reject_if_disagree) { /* Getting fed up with sending NAKs? */ + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting too many naks\n")); + orc = CONFREJ; /* Get tough if so */ + } else { + if (rc == CONFREJ) { /* Rejecting prior CI? */ + continue; /* Don't send this one */ + } + if (rc == CONFACK) { /* Ack'd all prior CIs? */ + rc = CONFNAK; /* Not anymore... */ + ucp = inp; /* Backup */ + } + } + } + + if (orc == CONFREJ && /* Reject this CI */ + rc != CONFREJ) { /* but no prior ones? */ + rc = CONFREJ; + ucp = inp; /* Backup */ + } + + /* Need to move CI? */ + if (ucp != cip) { + BCOPY(cip, ucp, cilen); /* Move it */ + } + + /* Update output pointer */ + INCPTR(cilen, ucp); + } + + /* + * If we aren't rejecting this packet, and we want to negotiate + * their address, and they didn't send their address, then we + * send a NAK with a CI_ADDR option appended. We assume the + * input buffer is long enough that we can append the extra + * option safely. + */ + if (rc != CONFREJ && !ho->neg_addr && + wo->req_addr && !reject_if_disagree) { + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Requesting peer address\n")); + if (rc == CONFACK) { + rc = CONFNAK; + ucp = inp; /* reset pointer */ + wo->req_addr = 0; /* don't ask again */ + } + PUTCHAR(CI_ADDR, ucp); + PUTCHAR(CILEN_ADDR, ucp); + tl = ntohl(wo->hisaddr); + PUTLONG(tl, ucp); + } + + *len = (int)(ucp - inp); /* Compute output length */ + IPCPDEBUG(LOG_INFO, ("ipcp_reqci: returning Configure-%s\n", CODENAME(rc))); + return (rc); /* Return final code */ +} + + +#if 0 +/* + * ip_check_options - check that any IP-related options are OK, + * and assign appropriate defaults. + */ +static void +ip_check_options(u_long localAddr) +{ + ipcp_options *wo = &ipcp_wantoptions[0]; + + /* + * Load our default IP address but allow the remote host to give us + * a new address. + */ + if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) { + wo->accept_local = 1; /* don't insist on this default value */ + wo->ouraddr = htonl(localAddr); + } +} +#endif + + +/* + * ipcp_up - IPCP has come UP. + * + * Configure the IP network interface appropriately and bring it up. + */ +static void +ipcp_up(fsm *f) +{ + u32_t mask; + ipcp_options *ho = &ipcp_hisoptions[f->unit]; + ipcp_options *go = &ipcp_gotoptions[f->unit]; + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + + np_up(f->unit, PPP_IP); + IPCPDEBUG(LOG_INFO, ("ipcp: up\n")); + + /* + * We must have a non-zero IP address for both ends of the link. + */ + if (!ho->neg_addr) { + ho->hisaddr = wo->hisaddr; + } + + if (ho->hisaddr == 0) { + IPCPDEBUG(LOG_ERR, ("Could not determine remote IP address\n")); + ipcp_close(f->unit, "Could not determine remote IP address"); + return; + } + if (go->ouraddr == 0) { + IPCPDEBUG(LOG_ERR, ("Could not determine local IP address\n")); + ipcp_close(f->unit, "Could not determine local IP address"); + return; + } + + if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) { + /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/ + } + + /* + * Check that the peer is allowed to use the IP address it wants. + */ + if (!auth_ip_addr(f->unit, ho->hisaddr)) { + IPCPDEBUG(LOG_ERR, ("Peer is not authorized to use remote address %s\n", + inet_ntoa(ho->hisaddr))); + ipcp_close(f->unit, "Unauthorized remote IP address"); + return; + } + + /* set tcp compression */ + sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex); + + /* + * Set IP addresses and (if specified) netmask. + */ + mask = GetMask(go->ouraddr); + + if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) { + IPCPDEBUG(LOG_WARNING, ("sifaddr failed\n")); + ipcp_close(f->unit, "Interface configuration failed"); + return; + } + + /* bring the interface up for IP */ + if (!sifup(f->unit)) { + IPCPDEBUG(LOG_WARNING, ("sifup failed\n")); + ipcp_close(f->unit, "Interface configuration failed"); + return; + } + + sifnpmode(f->unit, PPP_IP, NPMODE_PASS); + + /* assign a default route through the interface if required */ + if (ipcp_wantoptions[f->unit].default_route) { + if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) { + default_route_set[f->unit] = 1; + } + } + + IPCPDEBUG(LOG_NOTICE, ("local IP address %s\n", inet_ntoa(go->ouraddr))); + IPCPDEBUG(LOG_NOTICE, ("remote IP address %s\n", inet_ntoa(ho->hisaddr))); + if (go->dnsaddr[0]) { + IPCPDEBUG(LOG_NOTICE, ("primary DNS address %s\n", inet_ntoa(go->dnsaddr[0]))); + } + if (go->dnsaddr[1]) { + IPCPDEBUG(LOG_NOTICE, ("secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1]))); + } +} + + +/* + * ipcp_down - IPCP has gone DOWN. + * + * Take the IP network interface down, clear its addresses + * and delete routes through it. + */ +static void +ipcp_down(fsm *f) +{ + IPCPDEBUG(LOG_INFO, ("ipcp: down\n")); + np_down(f->unit, PPP_IP); + sifvjcomp(f->unit, 0, 0, 0); + + sifdown(f->unit); + ipcp_clear_addrs(f->unit); +} + + +/* + * ipcp_clear_addrs() - clear the interface addresses, routes, etc. + */ +static void +ipcp_clear_addrs(int unit) +{ + u32_t ouraddr, hisaddr; + + ouraddr = ipcp_gotoptions[unit].ouraddr; + hisaddr = ipcp_hisoptions[unit].hisaddr; + if (default_route_set[unit]) { + cifdefaultroute(unit, ouraddr, hisaddr); + default_route_set[unit] = 0; + } + cifaddr(unit, ouraddr, hisaddr); +} + + +/* + * ipcp_finished - possibly shut down the lower layers. + */ +static void +ipcp_finished(fsm *f) +{ + np_finished(f->unit, PPP_IP); +} + +#if PPP_ADDITIONAL_CALLBACKS +static int +ipcp_printpkt(u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg) +{ + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(plen); + LWIP_UNUSED_ARG(printer); + LWIP_UNUSED_ARG(arg); + return 0; +} + +/* + * ip_active_pkt - see if this IP packet is worth bringing the link up for. + * We don't bring the link up for IP fragments or for TCP FIN packets + * with no data. + */ +#define IP_HDRLEN 20 /* bytes */ +#define IP_OFFMASK 0x1fff +#define IPPROTO_TCP 6 +#define TCP_HDRLEN 20 +#define TH_FIN 0x01 + +/* + * We use these macros because the IP header may be at an odd address, + * and some compilers might use word loads to get th_off or ip_hl. + */ + +#define net_short(x) (((x)[0] << 8) + (x)[1]) +#define get_iphl(x) (((unsigned char *)(x))[0] & 0xF) +#define get_ipoff(x) net_short((unsigned char *)(x) + 6) +#define get_ipproto(x) (((unsigned char *)(x))[9]) +#define get_tcpoff(x) (((unsigned char *)(x))[12] >> 4) +#define get_tcpflags(x) (((unsigned char *)(x))[13]) + +static int +ip_active_pkt(u_char *pkt, int len) +{ + u_char *tcp; + int hlen; + + len -= PPP_HDRLEN; + pkt += PPP_HDRLEN; + if (len < IP_HDRLEN) { + return 0; + } + if ((get_ipoff(pkt) & IP_OFFMASK) != 0) { + return 0; + } + if (get_ipproto(pkt) != IPPROTO_TCP) { + return 1; + } + hlen = get_iphl(pkt) * 4; + if (len < hlen + TCP_HDRLEN) { + return 0; + } + tcp = pkt + hlen; + if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) { + return 0; + } + return 1; +} +#endif /* PPP_ADDITIONAL_CALLBACKS */ + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.h new file mode 100644 index 0000000..de03f46 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.h @@ -0,0 +1,106 @@ +/***************************************************************************** +* ipcp.h - PPP IP NCP: Internet Protocol Network Control Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * ipcp.h - IP Control Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: ipcp.h,v 1.4 2010/01/18 20:49:43 goldsimon Exp $ + */ + +#ifndef IPCP_H +#define IPCP_H + +/* + * Options. + */ +#define CI_ADDRS 1 /* IP Addresses */ +#define CI_COMPRESSTYPE 2 /* Compression Type */ +#define CI_ADDR 3 + +#define CI_MS_DNS1 129 /* Primary DNS value */ +#define CI_MS_WINS1 128 /* Primary WINS value */ +#define CI_MS_DNS2 131 /* Secondary DNS value */ +#define CI_MS_WINS2 130 /* Secondary WINS value */ + +#define IPCP_VJMODE_OLD 1 /* "old" mode (option # = 0x0037) */ +#define IPCP_VJMODE_RFC1172 2 /* "old-rfc"mode (option # = 0x002d) */ +#define IPCP_VJMODE_RFC1332 3 /* "new-rfc"mode (option # = 0x002d, */ + /* maxslot and slot number compression) */ + +#define IPCP_VJ_COMP 0x002d /* current value for VJ compression option */ +#define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */ + /* compression option */ + +typedef struct ipcp_options { + u_int neg_addr : 1; /* Negotiate IP Address? */ + u_int old_addrs : 1; /* Use old (IP-Addresses) option? */ + u_int req_addr : 1; /* Ask peer to send IP address? */ + u_int default_route : 1; /* Assign default route through interface? */ + u_int proxy_arp : 1; /* Make proxy ARP entry for peer? */ + u_int neg_vj : 1; /* Van Jacobson Compression? */ + u_int old_vj : 1; /* use old (short) form of VJ option? */ + u_int accept_local : 1; /* accept peer's value for ouraddr */ + u_int accept_remote : 1; /* accept peer's value for hisaddr */ + u_int req_dns1 : 1; /* Ask peer to send primary DNS address? */ + u_int req_dns2 : 1; /* Ask peer to send secondary DNS address? */ + u_short vj_protocol; /* protocol value to use in VJ option */ + u_char maxslotindex; /* VJ slots - 1. */ + u_char cflag; /* VJ slot compression flag. */ + u32_t ouraddr, hisaddr; /* Addresses in NETWORK BYTE ORDER */ + u32_t dnsaddr[2]; /* Primary and secondary MS DNS entries */ + u32_t winsaddr[2]; /* Primary and secondary MS WINS entries */ +} ipcp_options; + +extern fsm ipcp_fsm[]; +extern ipcp_options ipcp_wantoptions[]; +extern ipcp_options ipcp_gotoptions[]; +extern ipcp_options ipcp_allowoptions[]; +extern ipcp_options ipcp_hisoptions[]; + +extern struct protent ipcp_protent; + +#endif /* IPCP_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.c new file mode 100644 index 0000000..21c83ac --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.c @@ -0,0 +1,2066 @@ +/***************************************************************************** +* lcp.c - Network Link Control Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-01 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ + +/* + * lcp.c - PPP Link Control Protocol. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "ppp.h" +#include "pppdebug.h" + +#include "fsm.h" +#include "chap.h" +#include "magic.h" +#include "auth.h" +#include "lcp.h" + +#include + +#if PPPOE_SUPPORT +#include "netif/ppp_oe.h" +#else +#define PPPOE_MAXMTU PPP_MAXMRU +#endif + +#if 0 /* UNUSED */ +/* + * LCP-related command-line options. + */ +int lcp_echo_interval = 0; /* Interval between LCP echo-requests */ +int lcp_echo_fails = 0; /* Tolerance to unanswered echo-requests */ +bool lax_recv = 0; /* accept control chars in asyncmap */ + +static int setescape (char **); + +static option_t lcp_option_list[] = { + /* LCP options */ + /* list stripped for simplicity */ + {NULL} +}; +#endif /* UNUSED */ + +/* options */ +LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ +static u_int lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */ +static u_int lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */ + +/* global vars */ +static fsm lcp_fsm[NUM_PPP]; /* LCP fsm structure (global)*/ +lcp_options lcp_wantoptions[NUM_PPP]; /* Options that we want to request */ +lcp_options lcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ +lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ +lcp_options lcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ +ext_accm xmit_accm[NUM_PPP]; /* extended transmit ACCM */ + +static u32_t lcp_echos_pending = 0; /* Number of outstanding echo msgs */ +static u32_t lcp_echo_number = 0; /* ID number of next echo frame */ +static u32_t lcp_echo_timer_running = 0; /* TRUE if a timer is running */ + +/* @todo: do we really need such a large buffer? The typical 1500 bytes seem too much. */ +static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */ + +/* + * Callbacks for fsm code. (CI = Configuration Information) + */ +static void lcp_resetci (fsm*); /* Reset our CI */ +static int lcp_cilen (fsm*); /* Return length of our CI */ +static void lcp_addci (fsm*, u_char*, int*); /* Add our CI to pkt */ +static int lcp_ackci (fsm*, u_char*, int); /* Peer ack'd our CI */ +static int lcp_nakci (fsm*, u_char*, int); /* Peer nak'd our CI */ +static int lcp_rejci (fsm*, u_char*, int); /* Peer rej'd our CI */ +static int lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */ +static void lcp_up (fsm*); /* We're UP */ +static void lcp_down (fsm*); /* We're DOWN */ +static void lcp_starting (fsm*); /* We need lower layer up */ +static void lcp_finished (fsm*); /* We need lower layer down */ +static int lcp_extcode (fsm*, int, u_char, u_char*, int); +static void lcp_rprotrej (fsm*, u_char*, int); + +/* + * routines to send LCP echos to peer + */ + +static void lcp_echo_lowerup (int); +static void lcp_echo_lowerdown (int); +static void LcpEchoTimeout (void*); +static void lcp_received_echo_reply (fsm*, int, u_char*, int); +static void LcpSendEchoRequest (fsm*); +static void LcpLinkFailure (fsm*); +static void LcpEchoCheck (fsm*); + +static fsm_callbacks lcp_callbacks = { /* LCP callback routines */ + lcp_resetci, /* Reset our Configuration Information */ + lcp_cilen, /* Length of our Configuration Information */ + lcp_addci, /* Add our Configuration Information */ + lcp_ackci, /* ACK our Configuration Information */ + lcp_nakci, /* NAK our Configuration Information */ + lcp_rejci, /* Reject our Configuration Information */ + lcp_reqci, /* Request peer's Configuration Information */ + lcp_up, /* Called when fsm reaches LS_OPENED state */ + lcp_down, /* Called when fsm leaves LS_OPENED state */ + lcp_starting, /* Called when we want the lower layer up */ + lcp_finished, /* Called when we want the lower layer down */ + NULL, /* Called when Protocol-Reject received */ + NULL, /* Retransmission is necessary */ + lcp_extcode, /* Called to handle LCP-specific codes */ + "LCP" /* String name of protocol */ +}; + +/* + * Protocol entry points. + * Some of these are called directly. + */ + +static void lcp_input (int, u_char *, int); +static void lcp_protrej (int); + +struct protent lcp_protent = { + PPP_LCP, + lcp_init, + lcp_input, + lcp_protrej, + lcp_lowerup, + lcp_lowerdown, + lcp_open, + lcp_close, +#if PPP_ADDITIONAL_CALLBACKS + lcp_printpkt, + NULL, +#endif /* PPP_ADDITIONAL_CALLBACKS */ + 1, + "LCP", +#if PPP_ADDITIONAL_CALLBACKS + NULL, + NULL, + NULL +#endif /* PPP_ADDITIONAL_CALLBACKS */ +}; + +int lcp_loopbackfail = DEFLOOPBACKFAIL; + +/* + * Length of each type of configuration option (in octets) + */ +#define CILEN_VOID 2 +#define CILEN_CHAR 3 +#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */ +#define CILEN_CHAP 5 /* CILEN_VOID + sizeof(short) + 1 */ +#define CILEN_LONG 6 /* CILEN_VOID + sizeof(long) */ +#define CILEN_LQR 8 /* CILEN_VOID + sizeof(short) + sizeof(long) */ +#define CILEN_CBCP 3 + +#define CODENAME(x) ((x) == CONFACK ? "ACK" : (x) == CONFNAK ? "NAK" : "REJ") + +#if 0 /* UNUSED */ +/* + * setescape - add chars to the set we escape on transmission. + */ +static int +setescape(argv) + char **argv; +{ + int n, ret; + char *p, *endp; + + p = *argv; + ret = 1; + while (*p) { + n = strtol(p, &endp, 16); + if (p == endp) { + option_error("escape parameter contains invalid hex number '%s'", p); + return 0; + } + p = endp; + if (n < 0 || n == 0x5E || n > 0xFF) { + option_error("can't escape character 0x%x", n); + ret = 0; + } else + xmit_accm[0][n >> 5] |= 1 << (n & 0x1F); + while (*p == ',' || *p == ' ') + ++p; + } + return ret; +} +#endif /* UNUSED */ + +/* + * lcp_init - Initialize LCP. + */ +void +lcp_init(int unit) +{ + fsm *f = &lcp_fsm[unit]; + lcp_options *wo = &lcp_wantoptions[unit]; + lcp_options *ao = &lcp_allowoptions[unit]; + + f->unit = unit; + f->protocol = PPP_LCP; + f->callbacks = &lcp_callbacks; + + fsm_init(f); + + wo->passive = 0; + wo->silent = 0; + wo->restart = 0; /* Set to 1 in kernels or multi-line implementations */ + wo->neg_mru = 1; + wo->mru = PPP_DEFMRU; + wo->neg_asyncmap = 1; + wo->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ + wo->neg_chap = 0; /* Set to 1 on server */ + wo->neg_upap = 0; /* Set to 1 on server */ + wo->chap_mdtype = CHAP_DIGEST_MD5; + wo->neg_magicnumber = 1; + wo->neg_pcompression = 1; + wo->neg_accompression = 1; + wo->neg_lqr = 0; /* no LQR implementation yet */ + wo->neg_cbcp = 0; + + ao->neg_mru = 1; + ao->mru = PPP_MAXMRU; + ao->neg_asyncmap = 1; + ao->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ + ao->neg_chap = (CHAP_SUPPORT != 0); + ao->chap_mdtype = CHAP_DIGEST_MD5; + ao->neg_upap = (PAP_SUPPORT != 0); + ao->neg_magicnumber = 1; + ao->neg_pcompression = 1; + ao->neg_accompression = 1; + ao->neg_lqr = 0; /* no LQR implementation yet */ + ao->neg_cbcp = (CBCP_SUPPORT != 0); + + /* + * Set transmit escape for the flag and escape characters plus anything + * set for the allowable options. + */ + memset(xmit_accm[unit], 0, sizeof(xmit_accm[0])); + xmit_accm[unit][15] = 0x60; + xmit_accm[unit][0] = (u_char)((ao->asyncmap & 0xFF)); + xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF); + xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF); + xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF); + LCPDEBUG(LOG_INFO, ("lcp_init: xmit_accm=%X %X %X %X\n", + xmit_accm[unit][0], + xmit_accm[unit][1], + xmit_accm[unit][2], + xmit_accm[unit][3])); + + lcp_phase[unit] = PHASE_INITIALIZE; +} + + +/* + * lcp_open - LCP is allowed to come up. + */ +void +lcp_open(int unit) +{ + fsm *f = &lcp_fsm[unit]; + lcp_options *wo = &lcp_wantoptions[unit]; + + f->flags = 0; + if (wo->passive) { + f->flags |= OPT_PASSIVE; + } + if (wo->silent) { + f->flags |= OPT_SILENT; + } + fsm_open(f); + + lcp_phase[unit] = PHASE_ESTABLISH; +} + + +/* + * lcp_close - Take LCP down. + */ +void +lcp_close(int unit, char *reason) +{ + fsm *f = &lcp_fsm[unit]; + + if (lcp_phase[unit] != PHASE_DEAD) { + lcp_phase[unit] = PHASE_TERMINATE; + } + if (f->state == LS_STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) { + /* + * This action is not strictly according to the FSM in RFC1548, + * but it does mean that the program terminates if you do an + * lcp_close() in passive/silent mode when a connection hasn't + * been established. + */ + f->state = LS_CLOSED; + lcp_finished(f); + } else { + fsm_close(f, reason); + } +} + + +/* + * lcp_lowerup - The lower layer is up. + */ +void +lcp_lowerup(int unit) +{ + lcp_options *wo = &lcp_wantoptions[unit]; + + /* + * Don't use A/C or protocol compression on transmission, + * but accept A/C and protocol compressed packets + * if we are going to ask for A/C and protocol compression. + */ + ppp_set_xaccm(unit, &xmit_accm[unit]); + ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0); + ppp_recv_config(unit, PPP_MRU, 0x00000000l, + wo->neg_pcompression, wo->neg_accompression); + peer_mru[unit] = PPP_MRU; + lcp_allowoptions[unit].asyncmap = (u_long)xmit_accm[unit][0] + | ((u_long)xmit_accm[unit][1] << 8) + | ((u_long)xmit_accm[unit][2] << 16) + | ((u_long)xmit_accm[unit][3] << 24); + LCPDEBUG(LOG_INFO, ("lcp_lowerup: asyncmap=%X %X %X %X\n", + xmit_accm[unit][3], + xmit_accm[unit][2], + xmit_accm[unit][1], + xmit_accm[unit][0])); + + fsm_lowerup(&lcp_fsm[unit]); +} + + +/* + * lcp_lowerdown - The lower layer is down. + */ +void +lcp_lowerdown(int unit) +{ + fsm_lowerdown(&lcp_fsm[unit]); +} + + +/* + * lcp_input - Input LCP packet. + */ +static void +lcp_input(int unit, u_char *p, int len) +{ + fsm *f = &lcp_fsm[unit]; + + fsm_input(f, p, len); +} + + +/* + * lcp_extcode - Handle a LCP-specific code. + */ +static int +lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len) +{ + u_char *magp; + + switch( code ){ + case PROTREJ: + lcp_rprotrej(f, inp, len); + break; + + case ECHOREQ: + if (f->state != LS_OPENED) { + break; + } + LCPDEBUG(LOG_INFO, ("lcp: Echo-Request, Rcvd id %d\n", id)); + magp = inp; + PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp); + fsm_sdata(f, ECHOREP, id, inp, len); + break; + + case ECHOREP: + lcp_received_echo_reply(f, id, inp, len); + break; + + case DISCREQ: + break; + + default: + return 0; + } + return 1; +} + + +/* + * lcp_rprotrej - Receive an Protocol-Reject. + * + * Figure out which protocol is rejected and inform it. + */ +static void +lcp_rprotrej(fsm *f, u_char *inp, int len) +{ + int i; + struct protent *protp; + u_short prot; + + if (len < (int)sizeof (u_short)) { + LCPDEBUG(LOG_INFO, ("lcp_rprotrej: Rcvd short Protocol-Reject packet!\n")); + return; + } + + GETSHORT(prot, inp); + + LCPDEBUG(LOG_INFO, ("lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n", prot)); + + /* + * Protocol-Reject packets received in any state other than the LCP + * LS_OPENED state SHOULD be silently discarded. + */ + if( f->state != LS_OPENED ) { + LCPDEBUG(LOG_INFO, ("Protocol-Reject discarded: LCP in state %d\n", f->state)); + return; + } + + /* + * Upcall the proper Protocol-Reject routine. + */ + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { + if (protp->protocol == prot && protp->enabled_flag) { + (*protp->protrej)(f->unit); + return; + } + } + + LCPDEBUG(LOG_WARNING, ("Protocol-Reject for unsupported protocol 0x%x\n", prot)); +} + + +/* + * lcp_protrej - A Protocol-Reject was received. + */ +static void +lcp_protrej(int unit) +{ + LWIP_UNUSED_ARG(unit); + /* + * Can't reject LCP! + */ + LCPDEBUG(LOG_WARNING, ("lcp_protrej: Received Protocol-Reject for LCP!\n")); + fsm_protreject(&lcp_fsm[unit]); +} + + +/* + * lcp_sprotrej - Send a Protocol-Reject for some protocol. + */ +void +lcp_sprotrej(int unit, u_char *p, int len) +{ + /* + * Send back the protocol and the information field of the + * rejected packet. We only get here if LCP is in the LS_OPENED state. + */ + + fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id, p, len); +} + + +/* + * lcp_resetci - Reset our CI. + */ +static void +lcp_resetci(fsm *f) +{ + lcp_wantoptions[f->unit].magicnumber = magic(); + lcp_wantoptions[f->unit].numloops = 0; + lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit]; + peer_mru[f->unit] = PPP_MRU; + auth_reset(f->unit); +} + + +/* + * lcp_cilen - Return length of our CI. + */ +static int +lcp_cilen(fsm *f) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + +#define LENCIVOID(neg) ((neg) ? CILEN_VOID : 0) +#define LENCICHAP(neg) ((neg) ? CILEN_CHAP : 0) +#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0) +#define LENCILONG(neg) ((neg) ? CILEN_LONG : 0) +#define LENCILQR(neg) ((neg) ? CILEN_LQR: 0) +#define LENCICBCP(neg) ((neg) ? CILEN_CBCP: 0) + /* + * NB: we only ask for one of CHAP and UPAP, even if we will + * accept either. + */ + return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) + + LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) + + LENCICHAP(go->neg_chap) + + LENCISHORT(!go->neg_chap && go->neg_upap) + + LENCILQR(go->neg_lqr) + + LENCICBCP(go->neg_cbcp) + + LENCILONG(go->neg_magicnumber) + + LENCIVOID(go->neg_pcompression) + + LENCIVOID(go->neg_accompression)); +} + + +/* + * lcp_addci - Add our desired CIs to a packet. + */ +static void +lcp_addci(fsm *f, u_char *ucp, int *lenp) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + u_char *start_ucp = ucp; + +#define ADDCIVOID(opt, neg) \ + if (neg) { \ + LCPDEBUG(LOG_INFO, ("lcp_addci: opt=%d\n", opt)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_VOID, ucp); \ + } +#define ADDCISHORT(opt, neg, val) \ + if (neg) { \ + LCPDEBUG(LOG_INFO, ("lcp_addci: INT opt=%d %X\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_SHORT, ucp); \ + PUTSHORT(val, ucp); \ + } +#define ADDCICHAP(opt, neg, val, digest) \ + if (neg) { \ + LCPDEBUG(LOG_INFO, ("lcp_addci: CHAP opt=%d %X\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_CHAP, ucp); \ + PUTSHORT(val, ucp); \ + PUTCHAR(digest, ucp); \ + } +#define ADDCILONG(opt, neg, val) \ + if (neg) { \ + LCPDEBUG(LOG_INFO, ("lcp_addci: L opt=%d %lX\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_LONG, ucp); \ + PUTLONG(val, ucp); \ + } +#define ADDCILQR(opt, neg, val) \ + if (neg) { \ + LCPDEBUG(LOG_INFO, ("lcp_addci: LQR opt=%d %lX\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_LQR, ucp); \ + PUTSHORT(PPP_LQR, ucp); \ + PUTLONG(val, ucp); \ + } +#define ADDCICHAR(opt, neg, val) \ + if (neg) { \ + LCPDEBUG(LOG_INFO, ("lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_CHAR, ucp); \ + PUTCHAR(val, ucp); \ + } + + ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); + ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap); + ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); + ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); + ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); + ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); + ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); + ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression); + ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression); + + if (ucp - start_ucp != *lenp) { + /* this should never happen, because peer_mtu should be 1500 */ + LCPDEBUG(LOG_ERR, ("Bug in lcp_addci: wrong length\n")); + } +} + + +/* + * lcp_ackci - Ack our CIs. + * This should not modify any state if the Ack is bad. + * + * Returns: + * 0 - Ack was bad. + * 1 - Ack was good. + */ +static int +lcp_ackci(fsm *f, u_char *p, int len) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + u_char cilen, citype, cichar; + u_short cishort; + u32_t cilong; + + /* + * CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define ACKCIVOID(opt, neg) \ + if (neg) { \ + if ((len -= CILEN_VOID) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_VOID || citype != opt) \ + goto bad; \ + } +#define ACKCISHORT(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_SHORT) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_SHORT || citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + } +#define ACKCICHAR(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_CHAR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_CHAR || citype != opt) \ + goto bad; \ + GETCHAR(cichar, p); \ + if (cichar != val) \ + goto bad; \ + } +#define ACKCICHAP(opt, neg, val, digest) \ + if (neg) { \ + if ((len -= CILEN_CHAP) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_CHAP || citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + GETCHAR(cichar, p); \ + if (cichar != digest) \ + goto bad; \ + } +#define ACKCILONG(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_LONG) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_LONG || citype != opt) \ + goto bad; \ + GETLONG(cilong, p); \ + if (cilong != val) \ + goto bad; \ + } +#define ACKCILQR(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_LQR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_LQR || citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != PPP_LQR) \ + goto bad; \ + GETLONG(cilong, p); \ + if (cilong != val) \ + goto bad; \ + } + + ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); + ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap); + ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); + ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); + ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); + ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); + ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); + ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression); + ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) { + goto bad; + } + LCPDEBUG(LOG_INFO, ("lcp_acki: Ack\n")); + return (1); +bad: + LCPDEBUG(LOG_WARNING, ("lcp_acki: received bad Ack!\n")); + return (0); +} + + +/* + * lcp_nakci - Peer has sent a NAK for some of our CIs. + * This should not modify any state if the Nak is bad + * or if LCP is in the LS_OPENED state. + * + * Returns: + * 0 - Nak was bad. + * 1 - Nak was good. + */ +static int +lcp_nakci(fsm *f, u_char *p, int len) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + lcp_options *wo = &lcp_wantoptions[f->unit]; + u_char citype, cichar, *next; + u_short cishort; + u32_t cilong; + lcp_options no; /* options we've seen Naks for */ + lcp_options try; /* options to request next time */ + int looped_back = 0; + int cilen; + + BZERO(&no, sizeof(no)); + try = *go; + + /* + * Any Nak'd CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define NAKCIVOID(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_VOID && \ + p[1] == CILEN_VOID && \ + p[0] == opt) { \ + len -= CILEN_VOID; \ + INCPTR(CILEN_VOID, p); \ + no.neg = 1; \ + code \ + } +#define NAKCICHAP(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + no.neg = 1; \ + code \ + } +#define NAKCICHAR(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_CHAR && \ + p[1] == CILEN_CHAR && \ + p[0] == opt) { \ + len -= CILEN_CHAR; \ + INCPTR(2, p); \ + GETCHAR(cichar, p); \ + no.neg = 1; \ + code \ + } +#define NAKCISHORT(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_SHORT && \ + p[1] == CILEN_SHORT && \ + p[0] == opt) { \ + len -= CILEN_SHORT; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + no.neg = 1; \ + code \ + } +#define NAKCILONG(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_LONG && \ + p[1] == CILEN_LONG && \ + p[0] == opt) { \ + len -= CILEN_LONG; \ + INCPTR(2, p); \ + GETLONG(cilong, p); \ + no.neg = 1; \ + code \ + } +#define NAKCILQR(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_LQR && \ + p[1] == CILEN_LQR && \ + p[0] == opt) { \ + len -= CILEN_LQR; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETLONG(cilong, p); \ + no.neg = 1; \ + code \ + } + + /* + * We don't care if they want to send us smaller packets than + * we want. Therefore, accept any MRU less than what we asked for, + * but then ignore the new value when setting the MRU in the kernel. + * If they send us a bigger MRU than what we asked, accept it, up to + * the limit of the default MRU we'd get if we didn't negotiate. + */ + if (go->neg_mru && go->mru != PPP_DEFMRU) { + NAKCISHORT(CI_MRU, neg_mru, + if (cishort <= wo->mru || cishort < PPP_DEFMRU) { + try.mru = cishort; + } + ); + } + + /* + * Add any characters they want to our (receive-side) asyncmap. + */ + if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) { + NAKCILONG(CI_ASYNCMAP, neg_asyncmap, + try.asyncmap = go->asyncmap | cilong; + ); + } + + /* + * If they've nak'd our authentication-protocol, check whether + * they are proposing a different protocol, or a different + * hash algorithm for CHAP. + */ + if ((go->neg_chap || go->neg_upap) + && len >= CILEN_SHORT + && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) { + cilen = p[1]; + len -= cilen; + no.neg_chap = go->neg_chap; + no.neg_upap = go->neg_upap; + INCPTR(2, p); + GETSHORT(cishort, p); + if (cishort == PPP_PAP && cilen == CILEN_SHORT) { + /* + * If we were asking for CHAP, they obviously don't want to do it. + * If we weren't asking for CHAP, then we were asking for PAP, + * in which case this Nak is bad. + */ + if (!go->neg_chap) { + goto bad; + } + try.neg_chap = 0; + + } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) { + GETCHAR(cichar, p); + if (go->neg_chap) { + /* + * We were asking for CHAP/MD5; they must want a different + * algorithm. If they can't do MD5, we'll have to stop + * asking for CHAP. + */ + if (cichar != go->chap_mdtype) { + try.neg_chap = 0; + } + } else { + /* + * Stop asking for PAP if we were asking for it. + */ + try.neg_upap = 0; + } + + } else { + /* + * We don't recognize what they're suggesting. + * Stop asking for what we were asking for. + */ + if (go->neg_chap) { + try.neg_chap = 0; + } else { + try.neg_upap = 0; + } + p += cilen - CILEN_SHORT; + } + } + + /* + * If they can't cope with our link quality protocol, we'll have + * to stop asking for LQR. We haven't got any other protocol. + * If they Nak the reporting period, take their value XXX ? + */ + NAKCILQR(CI_QUALITY, neg_lqr, + if (cishort != PPP_LQR) { + try.neg_lqr = 0; + } else { + try.lqr_period = cilong; + } + ); + + /* + * Only implementing CBCP...not the rest of the callback options + */ + NAKCICHAR(CI_CALLBACK, neg_cbcp, + try.neg_cbcp = 0; + ); + + /* + * Check for a looped-back line. + */ + NAKCILONG(CI_MAGICNUMBER, neg_magicnumber, + try.magicnumber = magic(); + looped_back = 1; + ); + + /* + * Peer shouldn't send Nak for protocol compression or + * address/control compression requests; they should send + * a Reject instead. If they send a Nak, treat it as a Reject. + */ + NAKCIVOID(CI_PCOMPRESSION, neg_pcompression, + try.neg_pcompression = 0; + ); + NAKCIVOID(CI_ACCOMPRESSION, neg_accompression, + try.neg_accompression = 0; + ); + + /* + * There may be remaining CIs, if the peer is requesting negotiation + * on an option that we didn't include in our request packet. + * If we see an option that we requested, or one we've already seen + * in this packet, then this packet is bad. + * If we wanted to respond by starting to negotiate on the requested + * option(s), we could, but we don't, because except for the + * authentication type and quality protocol, if we are not negotiating + * an option, it is because we were told not to. + * For the authentication type, the Nak from the peer means + * `let me authenticate myself with you' which is a bit pointless. + * For the quality protocol, the Nak means `ask me to send you quality + * reports', but if we didn't ask for them, we don't want them. + * An option we don't recognize represents the peer asking to + * negotiate some option we don't support, so ignore it. + */ + while (len > CILEN_VOID) { + GETCHAR(citype, p); + GETCHAR(cilen, p); + if (cilen < CILEN_VOID || (len -= cilen) < 0) { + goto bad; + } + next = p + cilen - 2; + + switch (citype) { + case CI_MRU: + if ((go->neg_mru && go->mru != PPP_DEFMRU) + || no.neg_mru || cilen != CILEN_SHORT) { + goto bad; + } + GETSHORT(cishort, p); + if (cishort < PPP_DEFMRU) { + try.mru = cishort; + } + break; + case CI_ASYNCMAP: + if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) + || no.neg_asyncmap || cilen != CILEN_LONG) { + goto bad; + } + break; + case CI_AUTHTYPE: + if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap) { + goto bad; + } + break; + case CI_MAGICNUMBER: + if (go->neg_magicnumber || no.neg_magicnumber || + cilen != CILEN_LONG) { + goto bad; + } + break; + case CI_PCOMPRESSION: + if (go->neg_pcompression || no.neg_pcompression + || cilen != CILEN_VOID) { + goto bad; + } + break; + case CI_ACCOMPRESSION: + if (go->neg_accompression || no.neg_accompression + || cilen != CILEN_VOID) { + goto bad; + } + break; + case CI_QUALITY: + if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) { + goto bad; + } + break; + } + p = next; + } + + /* If there is still anything left, this packet is bad. */ + if (len != 0) { + goto bad; + } + + /* + * OK, the Nak is good. Now we can update state. + */ + if (f->state != LS_OPENED) { + if (looped_back) { + if (++try.numloops >= lcp_loopbackfail) { + LCPDEBUG(LOG_NOTICE, ("Serial line is looped back.\n")); + lcp_close(f->unit, "Loopback detected"); + } + } else { + try.numloops = 0; + } + *go = try; + } + + return 1; + +bad: + LCPDEBUG(LOG_WARNING, ("lcp_nakci: received bad Nak!\n")); + return 0; +} + + +/* + * lcp_rejci - Peer has Rejected some of our CIs. + * This should not modify any state if the Reject is bad + * or if LCP is in the LS_OPENED state. + * + * Returns: + * 0 - Reject was bad. + * 1 - Reject was good. + */ +static int +lcp_rejci(fsm *f, u_char *p, int len) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + u_char cichar; + u_short cishort; + u32_t cilong; + lcp_options try; /* options to request next time */ + + try = *go; + + /* + * Any Rejected CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define REJCIVOID(opt, neg) \ + if (go->neg && \ + len >= CILEN_VOID && \ + p[1] == CILEN_VOID && \ + p[0] == opt) { \ + len -= CILEN_VOID; \ + INCPTR(CILEN_VOID, p); \ + try.neg = 0; \ + LCPDEBUG(LOG_INFO, ("lcp_rejci: void opt %d rejected\n", opt)); \ + } +#define REJCISHORT(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_SHORT && \ + p[1] == CILEN_SHORT && \ + p[0] == opt) { \ + len -= CILEN_SHORT; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + /* Check rejected value. */ \ + if (cishort != val) { \ + goto bad; \ + } \ + try.neg = 0; \ + LCPDEBUG(LOG_INFO, ("lcp_rejci: short opt %d rejected\n", opt)); \ + } +#define REJCICHAP(opt, neg, val, digest) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if (cishort != val || cichar != digest) { \ + goto bad; \ + } \ + try.neg = 0; \ + try.neg_upap = 0; \ + LCPDEBUG(LOG_INFO, ("lcp_rejci: chap opt %d rejected\n", opt)); \ + } +#define REJCILONG(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_LONG && \ + p[1] == CILEN_LONG && \ + p[0] == opt) { \ + len -= CILEN_LONG; \ + INCPTR(2, p); \ + GETLONG(cilong, p); \ + /* Check rejected value. */ \ + if (cilong != val) { \ + goto bad; \ + } \ + try.neg = 0; \ + LCPDEBUG(LOG_INFO, ("lcp_rejci: long opt %d rejected\n", opt)); \ + } +#define REJCILQR(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_LQR && \ + p[1] == CILEN_LQR && \ + p[0] == opt) { \ + len -= CILEN_LQR; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETLONG(cilong, p); \ + /* Check rejected value. */ \ + if (cishort != PPP_LQR || cilong != val) { \ + goto bad; \ + } \ + try.neg = 0; \ + LCPDEBUG(LOG_INFO, ("lcp_rejci: LQR opt %d rejected\n", opt)); \ + } +#define REJCICBCP(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_CBCP && \ + p[1] == CILEN_CBCP && \ + p[0] == opt) { \ + len -= CILEN_CBCP; \ + INCPTR(2, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if (cichar != val) { \ + goto bad; \ + } \ + try.neg = 0; \ + LCPDEBUG(LOG_INFO, ("lcp_rejci: Callback opt %d rejected\n", opt)); \ + } + + REJCISHORT(CI_MRU, neg_mru, go->mru); + REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap); + REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype); + if (!go->neg_chap) { + REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP); + } + REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period); + REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT); + REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber); + REJCIVOID(CI_PCOMPRESSION, neg_pcompression); + REJCIVOID(CI_ACCOMPRESSION, neg_accompression); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) { + goto bad; + } + /* + * Now we can update state. + */ + if (f->state != LS_OPENED) { + *go = try; + } + return 1; + +bad: + LCPDEBUG(LOG_WARNING, ("lcp_rejci: received bad Reject!\n")); + return 0; +} + + +/* + * lcp_reqci - Check the peer's requested CIs and send appropriate response. + * + * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified + * appropriately. If reject_if_disagree is non-zero, doesn't return + * CONFNAK; returns CONFREJ if it can't return CONFACK. + */ +static int +lcp_reqci(fsm *f, + u_char *inp, /* Requested CIs */ + int *lenp, /* Length of requested CIs */ + int reject_if_disagree) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + lcp_options *ho = &lcp_hisoptions[f->unit]; + lcp_options *ao = &lcp_allowoptions[f->unit]; + u_char *cip, *next; /* Pointer to current and next CIs */ + int cilen, citype; /* Parsed len, type */ + u_char cichar; /* Parsed char value */ + u_short cishort; /* Parsed short value */ + u32_t cilong; /* Parse long value */ + int rc = CONFACK; /* Final packet return code */ + int orc; /* Individual option return code */ + u_char *p; /* Pointer to next char to parse */ + u_char *rejp; /* Pointer to next char in reject frame */ + u_char *nakp; /* Pointer to next char in Nak frame */ + int l = *lenp; /* Length left */ +#if TRACELCP > 0 + char traceBuf[80]; + size_t traceNdx = 0; +#endif + + /* + * Reset all his options. + */ + BZERO(ho, sizeof(*ho)); + + /* + * Process all his options. + */ + next = inp; + nakp = nak_buffer; + rejp = inp; + while (l) { + orc = CONFACK; /* Assume success */ + cip = p = next; /* Remember begining of CI */ + if (l < 2 || /* Not enough data for CI header or */ + p[1] < 2 || /* CI length too small or */ + p[1] > l) { /* CI length too big? */ + LCPDEBUG(LOG_WARNING, ("lcp_reqci: bad CI length!\n")); + orc = CONFREJ; /* Reject bad CI */ + cilen = l; /* Reject till end of packet */ + l = 0; /* Don't loop again */ + citype = 0; + goto endswitch; + } + GETCHAR(citype, p); /* Parse CI type */ + GETCHAR(cilen, p); /* Parse CI length */ + l -= cilen; /* Adjust remaining length */ + next += cilen; /* Step to next CI */ + + switch (citype) { /* Check CI type */ + case CI_MRU: + if (!ao->neg_mru) { /* Allow option? */ + LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject MRU - not allowed\n")); + orc = CONFREJ; /* Reject CI */ + break; + } else if (cilen != CILEN_SHORT) { /* Check CI length */ + LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject MRU - bad length\n")); + orc = CONFREJ; /* Reject CI */ + break; + } + GETSHORT(cishort, p); /* Parse MRU */ + + /* + * He must be able to receive at least our minimum. + * No need to check a maximum. If he sends a large number, + * we'll just ignore it. + */ + if (cishort < PPP_MINMRU) { + LCPDEBUG(LOG_INFO, ("lcp_reqci: Nak - MRU too small\n")); + orc = CONFNAK; /* Nak CI */ + PUTCHAR(CI_MRU, nakp); + PUTCHAR(CILEN_SHORT, nakp); + PUTSHORT(PPP_MINMRU, nakp); /* Give him a hint */ + break; + } + ho->neg_mru = 1; /* Remember he sent MRU */ + ho->mru = cishort; /* And remember value */ +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort); + traceNdx = strlen(traceBuf); +#endif + break; + + case CI_ASYNCMAP: + if (!ao->neg_asyncmap) { + LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject ASYNCMAP not allowed\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_LONG) { + LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject ASYNCMAP bad length\n")); + orc = CONFREJ; + break; + } + GETLONG(cilong, p); + + /* + * Asyncmap must have set at least the bits + * which are set in lcp_allowoptions[unit].asyncmap. + */ + if ((ao->asyncmap & ~cilong) != 0) { + LCPDEBUG(LOG_INFO, ("lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", + cilong, ao->asyncmap)); + orc = CONFNAK; + PUTCHAR(CI_ASYNCMAP, nakp); + PUTCHAR(CILEN_LONG, nakp); + PUTLONG(ao->asyncmap | cilong, nakp); + break; + } + ho->neg_asyncmap = 1; + ho->asyncmap = cilong; +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong); + traceNdx = strlen(traceBuf); +#endif + break; + + case CI_AUTHTYPE: + if (cilen < CILEN_SHORT) { + LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject AUTHTYPE missing arg\n")); + orc = CONFREJ; + break; + } else if (!(ao->neg_upap || ao->neg_chap)) { + /* + * Reject the option if we're not willing to authenticate. + */ + LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject AUTHTYPE not allowed\n")); + orc = CONFREJ; + break; + } + GETSHORT(cishort, p); + + /* + * Authtype must be UPAP or CHAP. + * + * Note: if both ao->neg_upap and ao->neg_chap are set, + * and the peer sends a Configure-Request with two + * authenticate-protocol requests, one for CHAP and one + * for UPAP, then we will reject the second request. + * Whether we end up doing CHAP or UPAP depends then on + * the ordering of the CIs in the peer's Configure-Request. + */ + + if (cishort == PPP_PAP) { + if (ho->neg_chap) { /* we've already accepted CHAP */ + LCPDEBUG(LOG_WARNING, ("lcp_reqci: Reject AUTHTYPE PAP already accepted\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_SHORT) { + LCPDEBUG(LOG_WARNING, ("lcp_reqci: Reject AUTHTYPE PAP bad len\n")); + orc = CONFREJ; + break; + } + if (!ao->neg_upap) { /* we don't want to do PAP */ + LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE PAP not allowed\n")); + orc = CONFNAK; /* NAK it and suggest CHAP */ + PUTCHAR(CI_AUTHTYPE, nakp); + PUTCHAR(CILEN_CHAP, nakp); + PUTSHORT(PPP_CHAP, nakp); + PUTCHAR(ao->chap_mdtype, nakp); + break; + } + ho->neg_upap = 1; +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort); + traceNdx = strlen(traceBuf); +#endif + break; + } + if (cishort == PPP_CHAP) { + if (ho->neg_upap) { /* we've already accepted PAP */ + LCPDEBUG(LOG_WARNING, ("lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_CHAP) { + LCPDEBUG(LOG_WARNING, ("lcp_reqci: Reject AUTHTYPE CHAP bad len\n")); + orc = CONFREJ; + break; + } + if (!ao->neg_chap) { /* we don't want to do CHAP */ + LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE CHAP not allowed\n")); + orc = CONFNAK; /* NAK it and suggest PAP */ + PUTCHAR(CI_AUTHTYPE, nakp); + PUTCHAR(CILEN_SHORT, nakp); + PUTSHORT(PPP_PAP, nakp); + break; + } + GETCHAR(cichar, p); /* get digest type*/ + if (cichar != CHAP_DIGEST_MD5 +#if MSCHAP_SUPPORT + && cichar != CHAP_MICROSOFT +#endif + ) { + LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", (int)cichar)); + orc = CONFNAK; + PUTCHAR(CI_AUTHTYPE, nakp); + PUTCHAR(CILEN_CHAP, nakp); + PUTSHORT(PPP_CHAP, nakp); + PUTCHAR(ao->chap_mdtype, nakp); + break; + } +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, (int)cichar); + traceNdx = strlen(traceBuf); +#endif + ho->chap_mdtype = cichar; /* save md type */ + ho->neg_chap = 1; + break; + } + + /* + * We don't recognize the protocol they're asking for. + * Nak it with something we're willing to do. + * (At this point we know ao->neg_upap || ao->neg_chap.) + */ + orc = CONFNAK; + PUTCHAR(CI_AUTHTYPE, nakp); + if (ao->neg_chap) { + LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort)); + PUTCHAR(CILEN_CHAP, nakp); + PUTSHORT(PPP_CHAP, nakp); + PUTCHAR(ao->chap_mdtype, nakp); + } else { + LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort)); + PUTCHAR(CILEN_SHORT, nakp); + PUTSHORT(PPP_PAP, nakp); + } + break; + + case CI_QUALITY: + GETSHORT(cishort, p); + GETLONG(cilong, p); +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong); + traceNdx = strlen(traceBuf); +#endif + + if (!ao->neg_lqr || + cilen != CILEN_LQR) { + orc = CONFREJ; + break; + } + + /* + * Check the protocol and the reporting period. + * XXX When should we Nak this, and what with? + */ + if (cishort != PPP_LQR) { + orc = CONFNAK; + PUTCHAR(CI_QUALITY, nakp); + PUTCHAR(CILEN_LQR, nakp); + PUTSHORT(PPP_LQR, nakp); + PUTLONG(ao->lqr_period, nakp); + break; + } + break; + + case CI_MAGICNUMBER: + if (!(ao->neg_magicnumber || go->neg_magicnumber) || + cilen != CILEN_LONG) { + orc = CONFREJ; + break; + } + GETLONG(cilong, p); +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong); + traceNdx = strlen(traceBuf); +#endif + + /* + * He must have a different magic number. + */ + if (go->neg_magicnumber && + cilong == go->magicnumber) { + cilong = magic(); /* Don't put magic() inside macro! */ + orc = CONFNAK; + PUTCHAR(CI_MAGICNUMBER, nakp); + PUTCHAR(CILEN_LONG, nakp); + PUTLONG(cilong, nakp); + break; + } + ho->neg_magicnumber = 1; + ho->magicnumber = cilong; + break; + + + case CI_PCOMPRESSION: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION"); + traceNdx = strlen(traceBuf); +#endif + if (!ao->neg_pcompression || + cilen != CILEN_VOID) { + orc = CONFREJ; + break; + } + ho->neg_pcompression = 1; + break; + + case CI_ACCOMPRESSION: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION"); + traceNdx = strlen(traceBuf); +#endif + if (!ao->neg_accompression || + cilen != CILEN_VOID) { + orc = CONFREJ; + break; + } + ho->neg_accompression = 1; + break; + + case CI_MRRU: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU"); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + + case CI_SSNHF: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF"); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + + case CI_EPDISC: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC"); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + + default: +#if TRACELCP + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + } + + endswitch: +#if TRACELCP + if (traceNdx >= 80 - 32) { + LCPDEBUG(LOG_INFO, ("lcp_reqci: rcvd%s\n", traceBuf)); + traceNdx = 0; + } +#endif + if (orc == CONFACK && /* Good CI */ + rc != CONFACK) { /* but prior CI wasnt? */ + continue; /* Don't send this one */ + } + + if (orc == CONFNAK) { /* Nak this CI? */ + if (reject_if_disagree /* Getting fed up with sending NAKs? */ + && citype != CI_MAGICNUMBER) { + orc = CONFREJ; /* Get tough if so */ + } else { + if (rc == CONFREJ) { /* Rejecting prior CI? */ + continue; /* Don't send this one */ + } + rc = CONFNAK; + } + } + if (orc == CONFREJ) { /* Reject this CI */ + rc = CONFREJ; + if (cip != rejp) { /* Need to move rejected CI? */ + BCOPY(cip, rejp, cilen); /* Move it */ + } + INCPTR(cilen, rejp); /* Update output pointer */ + } + } + + /* + * If we wanted to send additional NAKs (for unsent CIs), the + * code would go here. The extra NAKs would go at *nakp. + * At present there are no cases where we want to ask the + * peer to negotiate an option. + */ + + switch (rc) { + case CONFACK: + *lenp = (int)(next - inp); + break; + case CONFNAK: + /* + * Copy the Nak'd options from the nak_buffer to the caller's buffer. + */ + *lenp = (int)(nakp - nak_buffer); + BCOPY(nak_buffer, inp, *lenp); + break; + case CONFREJ: + *lenp = (int)(rejp - inp); + break; + } + +#if TRACELCP > 0 + if (traceNdx > 0) { + LCPDEBUG(LOG_INFO, ("lcp_reqci: %s\n", traceBuf)); + } +#endif + LCPDEBUG(LOG_INFO, ("lcp_reqci: returning CONF%s.\n", CODENAME(rc))); + return (rc); /* Return final code */ +} + + +/* + * lcp_up - LCP has come UP. + */ +static void +lcp_up(fsm *f) +{ + lcp_options *wo = &lcp_wantoptions[f->unit]; + lcp_options *ho = &lcp_hisoptions[f->unit]; + lcp_options *go = &lcp_gotoptions[f->unit]; + lcp_options *ao = &lcp_allowoptions[f->unit]; + + if (!go->neg_magicnumber) { + go->magicnumber = 0; + } + if (!ho->neg_magicnumber) { + ho->magicnumber = 0; + } + + /* + * Set our MTU to the smaller of the MTU we wanted and + * the MRU our peer wanted. If we negotiated an MRU, + * set our MRU to the larger of value we wanted and + * the value we got in the negotiation. + */ + ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)), + (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl), + ho->neg_pcompression, ho->neg_accompression); + /* + * If the asyncmap hasn't been negotiated, we really should + * set the receive asyncmap to ffffffff, but we set it to 0 + * for backwards contemptibility. + */ + ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU), + (go->neg_asyncmap? go->asyncmap: 0x00000000), + go->neg_pcompression, go->neg_accompression); + + if (ho->neg_mru) { + peer_mru[f->unit] = ho->mru; + } + + lcp_echo_lowerup(f->unit); /* Enable echo messages */ + + link_established(f->unit); /* The link is up; authenticate now */ +} + + +/* + * lcp_down - LCP has gone DOWN. + * + * Alert other protocols. + */ +static void +lcp_down(fsm *f) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + + lcp_echo_lowerdown(f->unit); + + link_down(f->unit); + + ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0); + ppp_recv_config(f->unit, PPP_MRU, + (go->neg_asyncmap? go->asyncmap: 0x00000000), + go->neg_pcompression, go->neg_accompression); + peer_mru[f->unit] = PPP_MRU; +} + + +/* + * lcp_starting - LCP needs the lower layer up. + */ +static void +lcp_starting(fsm *f) +{ + link_required(f->unit); /* lwip: currently does nothing */ +} + + +/* + * lcp_finished - LCP has finished with the lower layer. + */ +static void +lcp_finished(fsm *f) +{ + link_terminated(f->unit); /* we are finished with the link */ +} + + +#if PPP_ADDITIONAL_CALLBACKS +/* + * print_string - print a readable representation of a string using + * printer. + */ +static void +print_string( char *p, int len, void (*printer) (void *, char *, ...), void *arg) +{ + int c; + + printer(arg, "\""); + for (; len > 0; --len) { + c = *p++; + if (' ' <= c && c <= '~') { + if (c == '\\' || c == '"') { + printer(arg, "\\"); + } + printer(arg, "%c", c); + } else { + switch (c) { + case '\n': + printer(arg, "\\n"); + break; + case '\r': + printer(arg, "\\r"); + break; + case '\t': + printer(arg, "\\t"); + break; + default: + printer(arg, "\\%.3o", c); + } + } + } + printer(arg, "\""); +} + + +/* + * lcp_printpkt - print the contents of an LCP packet. + */ +static char *lcp_codenames[] = { + "ConfReq", "ConfAck", "ConfNak", "ConfRej", + "TermReq", "TermAck", "CodeRej", "ProtRej", + "EchoReq", "EchoRep", "DiscReq" +}; + +static int +lcp_printpkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg) +{ + int code, id, len, olen; + u_char *pstart, *optend; + u_short cishort; + u32_t cilong; + + if (plen < HEADERLEN) { + return 0; + } + pstart = p; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < HEADERLEN || len > plen) { + return 0; + } + + if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *)) { + printer(arg, " %s", lcp_codenames[code-1]); + } else { + printer(arg, " code=0x%x", code); + } + printer(arg, " id=0x%x", id); + len -= HEADERLEN; + switch (code) { + case CONFREQ: + case CONFACK: + case CONFNAK: + case CONFREJ: + /* print option list */ + while (len >= 2) { + GETCHAR(code, p); + GETCHAR(olen, p); + p -= 2; + if (olen < 2 || olen > len) { + break; + } + printer(arg, " <"); + len -= olen; + optend = p + olen; + switch (code) { + case CI_MRU: + if (olen == CILEN_SHORT) { + p += 2; + GETSHORT(cishort, p); + printer(arg, "mru %d", cishort); + } + break; + case CI_ASYNCMAP: + if (olen == CILEN_LONG) { + p += 2; + GETLONG(cilong, p); + printer(arg, "asyncmap 0x%lx", cilong); + } + break; + case CI_AUTHTYPE: + if (olen >= CILEN_SHORT) { + p += 2; + printer(arg, "auth "); + GETSHORT(cishort, p); + switch (cishort) { + case PPP_PAP: + printer(arg, "pap"); + break; + case PPP_CHAP: + printer(arg, "chap"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_QUALITY: + if (olen >= CILEN_SHORT) { + p += 2; + printer(arg, "quality "); + GETSHORT(cishort, p); + switch (cishort) { + case PPP_LQR: + printer(arg, "lqr"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_CALLBACK: + if (olen >= CILEN_CHAR) { + p += 2; + printer(arg, "callback "); + GETSHORT(cishort, p); + switch (cishort) { + case CBCP_OPT: + printer(arg, "CBCP"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_MAGICNUMBER: + if (olen == CILEN_LONG) { + p += 2; + GETLONG(cilong, p); + printer(arg, "magic 0x%x", cilong); + } + break; + case CI_PCOMPRESSION: + if (olen == CILEN_VOID) { + p += 2; + printer(arg, "pcomp"); + } + break; + case CI_ACCOMPRESSION: + if (olen == CILEN_VOID) { + p += 2; + printer(arg, "accomp"); + } + break; + } + while (p < optend) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + printer(arg, ">"); + } + break; + + case TERMACK: + case TERMREQ: + if (len > 0 && *p >= ' ' && *p < 0x7f) { + printer(arg, " "); + print_string((char*)p, len, printer, arg); + p += len; + len = 0; + } + break; + + case ECHOREQ: + case ECHOREP: + case DISCREQ: + if (len >= 4) { + GETLONG(cilong, p); + printer(arg, " magic=0x%x", cilong); + p += 4; + len -= 4; + } + break; + } + + /* print the rest of the bytes in the packet */ + for (; len > 0; --len) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + + return (int)(p - pstart); +} +#endif /* PPP_ADDITIONAL_CALLBACKS */ + +/* + * Time to shut down the link because there is nothing out there. + */ +static void +LcpLinkFailure (fsm *f) +{ + if (f->state == LS_OPENED) { + LCPDEBUG(LOG_INFO, ("No response to %d echo-requests\n", lcp_echos_pending)); + LCPDEBUG(LOG_NOTICE, ("Serial link appears to be disconnected.\n")); + lcp_close(f->unit, "Peer not responding"); + } +} + +/* + * Timer expired for the LCP echo requests from this process. + */ +static void +LcpEchoCheck (fsm *f) +{ + LcpSendEchoRequest (f); + + /* + * Start the timer for the next interval. + */ + LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0); + + TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval); + lcp_echo_timer_running = 1; +} + +/* + * LcpEchoTimeout - Timer expired on the LCP echo + */ +static void +LcpEchoTimeout (void *arg) +{ + if (lcp_echo_timer_running != 0) { + lcp_echo_timer_running = 0; + LcpEchoCheck ((fsm *) arg); + } +} + +/* + * LcpEchoReply - LCP has received a reply to the echo + */ +static void +lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len) +{ + u32_t magic; + + LWIP_UNUSED_ARG(id); + + /* Check the magic number - don't count replies from ourselves. */ + if (len < 4) { + LCPDEBUG(LOG_WARNING, ("lcp: received short Echo-Reply, length %d\n", len)); + return; + } + GETLONG(magic, inp); + if (lcp_gotoptions[f->unit].neg_magicnumber && magic == lcp_gotoptions[f->unit].magicnumber) { + LCPDEBUG(LOG_WARNING, ("appear to have received our own echo-reply!\n")); + return; + } + + /* Reset the number of outstanding echo frames */ + lcp_echos_pending = 0; +} + +/* + * LcpSendEchoRequest - Send an echo request frame to the peer + */ +static void +LcpSendEchoRequest (fsm *f) +{ + u32_t lcp_magic; + u_char pkt[4], *pktp; + + /* + * Detect the failure of the peer at this point. + */ + if (lcp_echo_fails != 0) { + if (lcp_echos_pending >= lcp_echo_fails) { + LcpLinkFailure(f); + lcp_echos_pending = 0; + } + } + + /* + * Make and send the echo request frame. + */ + if (f->state == LS_OPENED) { + lcp_magic = lcp_gotoptions[f->unit].magicnumber; + pktp = pkt; + PUTLONG(lcp_magic, pktp); + fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt)); + ++lcp_echos_pending; + } +} + +/* + * lcp_echo_lowerup - Start the timer for the LCP frame + */ + +static void +lcp_echo_lowerup (int unit) +{ + fsm *f = &lcp_fsm[unit]; + + /* Clear the parameters for generating echo frames */ + lcp_echos_pending = 0; + lcp_echo_number = 0; + lcp_echo_timer_running = 0; + + /* If a timeout interval is specified then start the timer */ + if (lcp_echo_interval != 0) { + LcpEchoCheck (f); + } +} + +/* + * lcp_echo_lowerdown - Stop the timer for the LCP frame + */ + +static void +lcp_echo_lowerdown (int unit) +{ + fsm *f = &lcp_fsm[unit]; + + if (lcp_echo_timer_running != 0) { + UNTIMEOUT (LcpEchoTimeout, f); + lcp_echo_timer_running = 0; + } +} + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.h new file mode 100644 index 0000000..b9201ee --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.h @@ -0,0 +1,151 @@ +/***************************************************************************** +* lcp.h - Network Link Control Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * lcp.h - Link Control Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: lcp.h,v 1.4 2010/01/18 20:49:43 goldsimon Exp $ + */ + +#ifndef LCP_H +#define LCP_H +/* + * Options. + */ +#define CI_MRU 1 /* Maximum Receive Unit */ +#define CI_ASYNCMAP 2 /* Async Control Character Map */ +#define CI_AUTHTYPE 3 /* Authentication Type */ +#define CI_QUALITY 4 /* Quality Protocol */ +#define CI_MAGICNUMBER 5 /* Magic Number */ +#define CI_PCOMPRESSION 7 /* Protocol Field Compression */ +#define CI_ACCOMPRESSION 8 /* Address/Control Field Compression */ +#define CI_CALLBACK 13 /* callback */ +#define CI_MRRU 17 /* max reconstructed receive unit; multilink */ +#define CI_SSNHF 18 /* short sequence numbers for multilink */ +#define CI_EPDISC 19 /* endpoint discriminator */ + +/* + * LCP-specific packet types (code numbers). + */ +#define PROTREJ 8 /* Protocol Reject */ +#define ECHOREQ 9 /* Echo Request */ +#define ECHOREP 10 /* Echo Reply */ +#define DISCREQ 11 /* Discard Request */ +#define CBCP_OPT 6 /* Use callback control protocol */ + +/* + * The state of options is described by an lcp_options structure. + */ +typedef struct lcp_options { + u_int passive : 1; /* Don't die if we don't get a response */ + u_int silent : 1; /* Wait for the other end to start first */ + u_int restart : 1; /* Restart vs. exit after close */ + u_int neg_mru : 1; /* Negotiate the MRU? */ + u_int neg_asyncmap : 1; /* Negotiate the async map? */ + u_int neg_upap : 1; /* Ask for UPAP authentication? */ + u_int neg_chap : 1; /* Ask for CHAP authentication? */ + u_int neg_magicnumber : 1; /* Ask for magic number? */ + u_int neg_pcompression : 1; /* HDLC Protocol Field Compression? */ + u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */ + u_int neg_lqr : 1; /* Negotiate use of Link Quality Reports */ + u_int neg_cbcp : 1; /* Negotiate use of CBCP */ +#ifdef PPP_MULTILINK + u_int neg_mrru : 1; /* Negotiate multilink MRRU */ + u_int neg_ssnhf : 1; /* Negotiate short sequence numbers */ + u_int neg_endpoint : 1; /* Negotiate endpoint discriminator */ +#endif + u_short mru; /* Value of MRU */ +#ifdef PPP_MULTILINK + u_short mrru; /* Value of MRRU, and multilink enable */ +#endif + u_char chap_mdtype; /* which MD type (hashing algorithm) */ + u32_t asyncmap; /* Value of async map */ + u32_t magicnumber; + int numloops; /* Number of loops during magic number neg. */ + u32_t lqr_period; /* Reporting period for LQR 1/100ths second */ +#ifdef PPP_MULTILINK + struct epdisc endpoint; /* endpoint discriminator */ +#endif +} lcp_options; + +/* + * Values for phase from BSD pppd.h based on RFC 1661. + */ +typedef enum { + PHASE_DEAD = 0, + PHASE_INITIALIZE, + PHASE_ESTABLISH, + PHASE_AUTHENTICATE, + PHASE_CALLBACK, + PHASE_NETWORK, + PHASE_TERMINATE +} LinkPhase; + + + +extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ +extern lcp_options lcp_wantoptions[]; +extern lcp_options lcp_gotoptions[]; +extern lcp_options lcp_allowoptions[]; +extern lcp_options lcp_hisoptions[]; +extern ext_accm xmit_accm[]; + + +void lcp_init (int); +void lcp_open (int); +void lcp_close (int, char *); +void lcp_lowerup (int); +void lcp_lowerdown(int); +void lcp_sprotrej (int, u_char *, int); /* send protocol reject */ + +extern struct protent lcp_protent; + +/* Default number of times we receive our magic number from the peer + before deciding the link is looped-back. */ +#define DEFLOOPBACKFAIL 10 + +#endif /* LCP_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.c new file mode 100644 index 0000000..3901330 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.c @@ -0,0 +1,80 @@ +/***************************************************************************** +* magic.c - Network Random Number Generator program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD magic.c. +*****************************************************************************/ +/* + * magic.c - PPP Magic Number routines. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "lwip/opt.h" + +#if PPP_SUPPORT + +#include "ppp.h" +#include "randm.h" +#include "magic.h" + + +/* + * magicInit - Initialize the magic number generator. + * + * Since we use another random number generator that has its own + * initialization, we do nothing here. + */ +void magicInit() +{ + return; +} + +/* + * magic - Returns the next magic number. + */ +u32_t magic() +{ + return avRandom(); +} + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.h new file mode 100644 index 0000000..eba70d2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.h @@ -0,0 +1,63 @@ +/***************************************************************************** +* magic.h - Network Random Number Generator header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * magic.h - PPP Magic Number definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: magic.h,v 1.3 2010/01/18 20:49:43 goldsimon Exp $ + */ + +#ifndef MAGIC_H +#define MAGIC_H + +/* Initialize the magic number generator */ +void magicInit(void); + +/* Returns the next magic number */ +u32_t magic(void); + +#endif /* MAGIC_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.c new file mode 100644 index 0000000..3cb69e2 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.c @@ -0,0 +1,320 @@ +/* + *********************************************************************** + ** md5.c -- the source code for MD5 routines ** + ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** + ** Created: 2/17/90 RLR ** + ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. ** + *********************************************************************** + */ + +/* + *********************************************************************** + ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** + ** ** + ** License to copy and use this software is granted provided that ** + ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** + ** Digest Algorithm" in all material mentioning or referencing this ** + ** software or this function. ** + ** ** + ** License is also granted to make and use derivative works ** + ** provided that such works are identified as "derived from the RSA ** + ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** + ** material mentioning or referencing the derived work. ** + ** ** + ** RSA Data Security, Inc. makes no representations concerning ** + ** either the merchantability of this software or the suitability ** + ** of this software for any particular purpose. It is provided "as ** + ** is" without express or implied warranty of any kind. ** + ** ** + ** These notices must be retained in any copies of any part of this ** + ** documentation and/or software. ** + *********************************************************************** + */ + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if CHAP_SUPPORT || MD5_SUPPORT + +#include "ppp.h" +#include "pppdebug.h" + +#include "md5.h" + +#include + +/* + *********************************************************************** + ** Message-digest routines: ** + ** To form the message digest for a message M ** + ** (1) Initialize a context buffer mdContext using MD5Init ** + ** (2) Call MD5Update on mdContext and M ** + ** (3) Call MD5Final on mdContext ** + ** The message digest is now in mdContext->digest[0...15] ** + *********************************************************************** + */ + +/* forward declaration */ +static void Transform (u32_t *buf, u32_t *in); + +static unsigned char PADDING[64] = { + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +/* F, G, H and I are basic MD5 functions */ +#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) +#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) +#define H(x, y, z) ((x) ^ (y) ^ (z)) +#define I(x, y, z) ((y) ^ ((x) | (~z))) + +/* ROTATE_LEFT rotates x left n bits */ +#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n)))) + +/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */ +/* Rotation is separate from addition to prevent recomputation */ +#define FF(a, b, c, d, x, s, ac) \ + {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define GG(a, b, c, d, x, s, ac) \ + {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define HH(a, b, c, d, x, s, ac) \ + {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define II(a, b, c, d, x, s, ac) \ + {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } + +#ifdef __STDC__ +#define UL(x) x##UL +#else +#ifdef WIN32 +#define UL(x) x##UL +#else +#define UL(x) x +#endif +#endif + +/* The routine MD5Init initializes the message-digest context + mdContext. All fields are set to zero. + */ +void +MD5Init (MD5_CTX *mdContext) +{ + mdContext->i[0] = mdContext->i[1] = (u32_t)0; + + /* Load magic initialization constants. */ + mdContext->buf[0] = (u32_t)0x67452301UL; + mdContext->buf[1] = (u32_t)0xefcdab89UL; + mdContext->buf[2] = (u32_t)0x98badcfeUL; + mdContext->buf[3] = (u32_t)0x10325476UL; +} + +/* The routine MD5Update updates the message-digest context to + account for the presence of each of the characters inBuf[0..inLen-1] + in the message whose digest is being computed. + */ +void +MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen) +{ + u32_t in[16]; + int mdi; + unsigned int i, ii; + +#if 0 + PPPDEBUG(LOG_INFO, ("MD5Update: %u:%.*H\n", inLen, LWIP_MIN(inLen, 20) * 2, inBuf)); + PPPDEBUG(LOG_INFO, ("MD5Update: %u:%s\n", inLen, inBuf)); +#endif + + /* compute number of bytes mod 64 */ + mdi = (int)((mdContext->i[0] >> 3) & 0x3F); + + /* update number of bits */ + if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0]) { + mdContext->i[1]++; + } + mdContext->i[0] += ((u32_t)inLen << 3); + mdContext->i[1] += ((u32_t)inLen >> 29); + + while (inLen--) { + /* add new character to buffer, increment mdi */ + mdContext->in[mdi++] = *inBuf++; + + /* transform if necessary */ + if (mdi == 0x40) { + for (i = 0, ii = 0; i < 16; i++, ii += 4) { + in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | + (((u32_t)mdContext->in[ii+2]) << 16) | + (((u32_t)mdContext->in[ii+1]) << 8) | + ((u32_t)mdContext->in[ii]); + } + Transform (mdContext->buf, in); + mdi = 0; + } + } +} + +/* The routine MD5Final terminates the message-digest computation and + ends with the desired message digest in mdContext->digest[0...15]. + */ +void +MD5Final (unsigned char hash[], MD5_CTX *mdContext) +{ + u32_t in[16]; + int mdi; + unsigned int i, ii; + unsigned int padLen; + + /* save number of bits */ + in[14] = mdContext->i[0]; + in[15] = mdContext->i[1]; + + /* compute number of bytes mod 64 */ + mdi = (int)((mdContext->i[0] >> 3) & 0x3F); + + /* pad out to 56 mod 64 */ + padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi); + MD5Update (mdContext, PADDING, padLen); + + /* append length in bits and transform */ + for (i = 0, ii = 0; i < 14; i++, ii += 4) { + in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | + (((u32_t)mdContext->in[ii+2]) << 16) | + (((u32_t)mdContext->in[ii+1]) << 8) | + ((u32_t)mdContext->in[ii]); + } + Transform (mdContext->buf, in); + + /* store buffer in digest */ + for (i = 0, ii = 0; i < 4; i++, ii += 4) { + mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF); + mdContext->digest[ii+1] = + (unsigned char)((mdContext->buf[i] >> 8) & 0xFF); + mdContext->digest[ii+2] = + (unsigned char)((mdContext->buf[i] >> 16) & 0xFF); + mdContext->digest[ii+3] = + (unsigned char)((mdContext->buf[i] >> 24) & 0xFF); + } + SMEMCPY(hash, mdContext->digest, 16); +} + +/* Basic MD5 step. Transforms buf based on in. + */ +static void +Transform (u32_t *buf, u32_t *in) +{ + u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3]; + + /* Round 1 */ +#define S11 7 +#define S12 12 +#define S13 17 +#define S14 22 + FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */ + FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */ + FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */ + FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */ + FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */ + FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */ + FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */ + FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */ + FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */ + FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */ + FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */ + FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */ + FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */ + FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */ + FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */ + FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */ + + /* Round 2 */ +#define S21 5 +#define S22 9 +#define S23 14 +#define S24 20 + GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */ + GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */ + GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */ + GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */ + GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */ + GG ( d, a, b, c, in[10], S22, UL( 38016083)); /* 22 */ + GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */ + GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */ + GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */ + GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */ + GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */ + GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */ + GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */ + GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */ + GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */ + GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */ + + /* Round 3 */ +#define S31 4 +#define S32 11 +#define S33 16 +#define S34 23 + HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */ + HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */ + HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */ + HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */ + HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */ + HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */ + HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */ + HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */ + HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */ + HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */ + HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */ + HH ( b, c, d, a, in[ 6], S34, UL( 76029189)); /* 44 */ + HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */ + HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */ + HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */ + HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */ + + /* Round 4 */ +#define S41 6 +#define S42 10 +#define S43 15 +#define S44 21 + II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */ + II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */ + II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */ + II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */ + II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */ + II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */ + II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */ + II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */ + II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */ + II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */ + II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */ + II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */ + II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */ + II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */ + II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */ + II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */ + + buf[0] += a; + buf[1] += b; + buf[2] += c; + buf[3] += d; +} + +#endif /* CHAP_SUPPORT || MD5_SUPPORT */ + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.h new file mode 100644 index 0000000..e129533 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.h @@ -0,0 +1,55 @@ +/* + *********************************************************************** + ** md5.h -- header file for implementation of MD5 ** + ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** + ** Created: 2/17/90 RLR ** + ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version ** + ** Revised (for MD5): RLR 4/27/91 ** + ** -- G modified to have y&~z instead of y&z ** + ** -- FF, GG, HH modified to add in last register done ** + ** -- Access pattern: round 2 works mod 5, round 3 works mod 3 ** + ** -- distinct additive constant for each step ** + ** -- round 4 added, working mod 7 ** + *********************************************************************** + */ + +/* + *********************************************************************** + ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** + ** ** + ** License to copy and use this software is granted provided that ** + ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** + ** Digest Algorithm" in all material mentioning or referencing this ** + ** software or this function. ** + ** ** + ** License is also granted to make and use derivative works ** + ** provided that such works are identified as "derived from the RSA ** + ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** + ** material mentioning or referencing the derived work. ** + ** ** + ** RSA Data Security, Inc. makes no representations concerning ** + ** either the merchantability of this software or the suitability ** + ** of this software for any particular purpose. It is provided "as ** + ** is" without express or implied warranty of any kind. ** + ** ** + ** These notices must be retained in any copies of any part of this ** + ** documentation and/or software. ** + *********************************************************************** + */ + +#ifndef MD5_H +#define MD5_H + +/* Data structure for MD5 (Message-Digest) computation */ +typedef struct { + u32_t i[2]; /* number of _bits_ handled mod 2^64 */ + u32_t buf[4]; /* scratch buffer */ + unsigned char in[64]; /* input buffer */ + unsigned char digest[16]; /* actual digest after MD5Final call */ +} MD5_CTX; + +void MD5Init ( MD5_CTX *mdContext); +void MD5Update( MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen); +void MD5Final ( unsigned char hash[], MD5_CTX *mdContext); + +#endif /* MD5_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.c new file mode 100644 index 0000000..ac44e64 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.c @@ -0,0 +1,628 @@ +/***************************************************************************** +* pap.c - Network Password Authentication Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-12 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ +/* + * upap.c - User/Password Authentication Protocol. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "ppp.h" +#include "pppdebug.h" + +#include "auth.h" +#include "pap.h" + +#include + +#if 0 /* UNUSED */ +static bool hide_password = 1; + +/* + * Command-line options. + */ +static option_t pap_option_list[] = { + { "hide-password", o_bool, &hide_password, + "Don't output passwords to log", 1 }, + { "show-password", o_bool, &hide_password, + "Show password string in debug log messages", 0 }, + { "pap-restart", o_int, &upap[0].us_timeouttime, + "Set retransmit timeout for PAP" }, + { "pap-max-authreq", o_int, &upap[0].us_maxtransmits, + "Set max number of transmissions for auth-reqs" }, + { "pap-timeout", o_int, &upap[0].us_reqtimeout, + "Set time limit for peer PAP authentication" }, + { NULL } +}; +#endif + +/* + * Protocol entry points. + */ +static void upap_init (int); +static void upap_lowerup (int); +static void upap_lowerdown (int); +static void upap_input (int, u_char *, int); +static void upap_protrej (int); +#if PPP_ADDITIONAL_CALLBACKS +static int upap_printpkt (u_char *, int, void (*)(void *, char *, ...), void *); +#endif /* PPP_ADDITIONAL_CALLBACKS */ + +struct protent pap_protent = { + PPP_PAP, + upap_init, + upap_input, + upap_protrej, + upap_lowerup, + upap_lowerdown, + NULL, + NULL, +#if PPP_ADDITIONAL_CALLBACKS + upap_printpkt, + NULL, +#endif /* PPP_ADDITIONAL_CALLBACKS */ + 1, + "PAP", +#if PPP_ADDITIONAL_CALLBACKS + NULL, + NULL, + NULL +#endif /* PPP_ADDITIONAL_CALLBACKS */ +}; + +upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */ + +static void upap_timeout (void *); +static void upap_reqtimeout(void *); +static void upap_rauthreq (upap_state *, u_char *, u_char, int); +static void upap_rauthack (upap_state *, u_char *, int, int); +static void upap_rauthnak (upap_state *, u_char *, int, int); +static void upap_sauthreq (upap_state *); +static void upap_sresp (upap_state *, u_char, u_char, char *, int); + + +/* + * upap_init - Initialize a UPAP unit. + */ +static void +upap_init(int unit) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG(LOG_INFO, ("upap_init: %d\n", unit)); + u->us_unit = unit; + u->us_user = NULL; + u->us_userlen = 0; + u->us_passwd = NULL; + u->us_passwdlen = 0; + u->us_clientstate = UPAPCS_INITIAL; + u->us_serverstate = UPAPSS_INITIAL; + u->us_id = 0; + u->us_timeouttime = UPAP_DEFTIMEOUT; + u->us_maxtransmits = 10; + u->us_reqtimeout = UPAP_DEFREQTIME; +} + +/* + * upap_authwithpeer - Authenticate us with our peer (start client). + * + * Set new state and send authenticate's. + */ +void +upap_authwithpeer(int unit, char *user, char *password) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG(LOG_INFO, ("upap_authwithpeer: %d user=%s password=%s s=%d\n", + unit, user, password, u->us_clientstate)); + + /* Save the username and password we're given */ + u->us_user = user; + u->us_userlen = (int)strlen(user); + u->us_passwd = password; + u->us_passwdlen = (int)strlen(password); + + u->us_transmits = 0; + + /* Lower layer up yet? */ + if (u->us_clientstate == UPAPCS_INITIAL || + u->us_clientstate == UPAPCS_PENDING) { + u->us_clientstate = UPAPCS_PENDING; + return; + } + + upap_sauthreq(u); /* Start protocol */ +} + + +/* + * upap_authpeer - Authenticate our peer (start server). + * + * Set new state. + */ +void +upap_authpeer(int unit) +{ + upap_state *u = &upap[unit]; + + /* Lower layer up yet? */ + if (u->us_serverstate == UPAPSS_INITIAL || + u->us_serverstate == UPAPSS_PENDING) { + u->us_serverstate = UPAPSS_PENDING; + return; + } + + u->us_serverstate = UPAPSS_LISTEN; + if (u->us_reqtimeout > 0) { + TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); + } +} + +/* + * upap_timeout - Retransmission timer for sending auth-reqs expired. + */ +static void +upap_timeout(void *arg) +{ + upap_state *u = (upap_state *) arg; + + UPAPDEBUG(LOG_INFO, ("upap_timeout: %d timeout %d expired s=%d\n", + u->us_unit, u->us_timeouttime, u->us_clientstate)); + + if (u->us_clientstate != UPAPCS_AUTHREQ) { + UPAPDEBUG(LOG_INFO, ("upap_timeout: not in AUTHREQ state!\n")); + return; + } + + if (u->us_transmits >= u->us_maxtransmits) { + /* give up in disgust */ + UPAPDEBUG(LOG_ERR, ("No response to PAP authenticate-requests\n")); + u->us_clientstate = UPAPCS_BADAUTH; + auth_withpeer_fail(u->us_unit, PPP_PAP); + return; + } + + upap_sauthreq(u); /* Send Authenticate-Request and set upap timeout*/ +} + + +/* + * upap_reqtimeout - Give up waiting for the peer to send an auth-req. + */ +static void +upap_reqtimeout(void *arg) +{ + upap_state *u = (upap_state *) arg; + + if (u->us_serverstate != UPAPSS_LISTEN) { + return; /* huh?? */ + } + + auth_peer_fail(u->us_unit, PPP_PAP); + u->us_serverstate = UPAPSS_BADAUTH; +} + + +/* + * upap_lowerup - The lower layer is up. + * + * Start authenticating if pending. + */ +static void +upap_lowerup(int unit) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG(LOG_INFO, ("upap_lowerup: init %d clientstate s=%d\n", unit, u->us_clientstate)); + + if (u->us_clientstate == UPAPCS_INITIAL) { + u->us_clientstate = UPAPCS_CLOSED; + } else if (u->us_clientstate == UPAPCS_PENDING) { + upap_sauthreq(u); /* send an auth-request */ + /* now client state is UPAPCS__AUTHREQ */ + } + + if (u->us_serverstate == UPAPSS_INITIAL) { + u->us_serverstate = UPAPSS_CLOSED; + } else if (u->us_serverstate == UPAPSS_PENDING) { + u->us_serverstate = UPAPSS_LISTEN; + if (u->us_reqtimeout > 0) { + TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); + } + } +} + + +/* + * upap_lowerdown - The lower layer is down. + * + * Cancel all timeouts. + */ +static void +upap_lowerdown(int unit) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG(LOG_INFO, ("upap_lowerdown: %d s=%d\n", unit, u->us_clientstate)); + + if (u->us_clientstate == UPAPCS_AUTHREQ) { /* Timeout pending? */ + UNTIMEOUT(upap_timeout, u); /* Cancel timeout */ + } + if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0) { + UNTIMEOUT(upap_reqtimeout, u); + } + + u->us_clientstate = UPAPCS_INITIAL; + u->us_serverstate = UPAPSS_INITIAL; +} + + +/* + * upap_protrej - Peer doesn't speak this protocol. + * + * This shouldn't happen. In any case, pretend lower layer went down. + */ +static void +upap_protrej(int unit) +{ + upap_state *u = &upap[unit]; + + if (u->us_clientstate == UPAPCS_AUTHREQ) { + UPAPDEBUG(LOG_ERR, ("PAP authentication failed due to protocol-reject\n")); + auth_withpeer_fail(unit, PPP_PAP); + } + if (u->us_serverstate == UPAPSS_LISTEN) { + UPAPDEBUG(LOG_ERR, ("PAP authentication of peer failed (protocol-reject)\n")); + auth_peer_fail(unit, PPP_PAP); + } + upap_lowerdown(unit); +} + + +/* + * upap_input - Input UPAP packet. + */ +static void +upap_input(int unit, u_char *inpacket, int l) +{ + upap_state *u = &upap[unit]; + u_char *inp; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + inp = inpacket; + if (l < (int)UPAP_HEADERLEN) { + UPAPDEBUG(LOG_INFO, ("pap_input: rcvd short header.\n")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < (int)UPAP_HEADERLEN) { + UPAPDEBUG(LOG_INFO, ("pap_input: rcvd illegal length.\n")); + return; + } + if (len > l) { + UPAPDEBUG(LOG_INFO, ("pap_input: rcvd short packet.\n")); + return; + } + len -= UPAP_HEADERLEN; + + /* + * Action depends on code. + */ + switch (code) { + case UPAP_AUTHREQ: + upap_rauthreq(u, inp, id, len); + break; + + case UPAP_AUTHACK: + upap_rauthack(u, inp, id, len); + break; + + case UPAP_AUTHNAK: + upap_rauthnak(u, inp, id, len); + break; + + default: /* XXX Need code reject */ + UPAPDEBUG(LOG_INFO, ("pap_input: UNHANDLED default: code: %d, id: %d, len: %d.\n", code, id, len)); + break; + } +} + + +/* + * upap_rauth - Receive Authenticate. + */ +static void +upap_rauthreq(upap_state *u, u_char *inp, u_char id, int len) +{ + u_char ruserlen, rpasswdlen; + char *ruser, *rpasswd; + u_char retcode; + char *msg; + int msglen; + + UPAPDEBUG(LOG_INFO, ("pap_rauth: Rcvd id %d.\n", id)); + + if (u->us_serverstate < UPAPSS_LISTEN) { + return; + } + + /* + * If we receive a duplicate authenticate-request, we are + * supposed to return the same status as for the first request. + */ + if (u->us_serverstate == UPAPSS_OPEN) { + upap_sresp(u, UPAP_AUTHACK, id, "", 0); /* return auth-ack */ + return; + } + if (u->us_serverstate == UPAPSS_BADAUTH) { + upap_sresp(u, UPAP_AUTHNAK, id, "", 0); /* return auth-nak */ + return; + } + + /* + * Parse user/passwd. + */ + if (len < (int)sizeof (u_char)) { + UPAPDEBUG(LOG_INFO, ("pap_rauth: rcvd short packet.\n")); + return; + } + GETCHAR(ruserlen, inp); + len -= sizeof (u_char) + ruserlen + sizeof (u_char); + if (len < 0) { + UPAPDEBUG(LOG_INFO, ("pap_rauth: rcvd short packet.\n")); + return; + } + ruser = (char *) inp; + INCPTR(ruserlen, inp); + GETCHAR(rpasswdlen, inp); + if (len < rpasswdlen) { + UPAPDEBUG(LOG_INFO, ("pap_rauth: rcvd short packet.\n")); + return; + } + rpasswd = (char *) inp; + + /* + * Check the username and password given. + */ + retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd, rpasswdlen, &msg, &msglen); + /* lwip: currently retcode is always UPAP_AUTHACK */ + BZERO(rpasswd, rpasswdlen); + + upap_sresp(u, retcode, id, msg, msglen); + + if (retcode == UPAP_AUTHACK) { + u->us_serverstate = UPAPSS_OPEN; + auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen); + } else { + u->us_serverstate = UPAPSS_BADAUTH; + auth_peer_fail(u->us_unit, PPP_PAP); + } + + if (u->us_reqtimeout > 0) { + UNTIMEOUT(upap_reqtimeout, u); + } +} + + +/* + * upap_rauthack - Receive Authenticate-Ack. + */ +static void +upap_rauthack(upap_state *u, u_char *inp, int id, int len) +{ + u_char msglen; + char *msg; + + LWIP_UNUSED_ARG(id); + + UPAPDEBUG(LOG_INFO, ("pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate)); + + if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */ + UPAPDEBUG(LOG_INFO, ("pap_rauthack: us_clientstate != UPAPCS_AUTHREQ\n")); + return; + } + + /* + * Parse message. + */ + if (len < (int)sizeof (u_char)) { + UPAPDEBUG(LOG_INFO, ("pap_rauthack: ignoring missing msg-length.\n")); + } else { + GETCHAR(msglen, inp); + if (msglen > 0) { + len -= sizeof (u_char); + if (len < msglen) { + UPAPDEBUG(LOG_INFO, ("pap_rauthack: rcvd short packet.\n")); + return; + } + msg = (char *) inp; + PRINTMSG(msg, msglen); + } + } + UNTIMEOUT(upap_timeout, u); /* Cancel timeout */ + u->us_clientstate = UPAPCS_OPEN; + + auth_withpeer_success(u->us_unit, PPP_PAP); +} + + +/* + * upap_rauthnak - Receive Authenticate-Nak. + */ +static void +upap_rauthnak(upap_state *u, u_char *inp, int id, int len) +{ + u_char msglen; + char *msg; + + LWIP_UNUSED_ARG(id); + + UPAPDEBUG(LOG_INFO, ("pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate)); + + if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */ + return; + } + + /* + * Parse message. + */ + if (len < sizeof (u_char)) { + UPAPDEBUG(LOG_INFO, ("pap_rauthnak: ignoring missing msg-length.\n")); + } else { + GETCHAR(msglen, inp); + if(msglen > 0) { + len -= sizeof (u_char); + if (len < msglen) { + UPAPDEBUG(LOG_INFO, ("pap_rauthnak: rcvd short packet.\n")); + return; + } + msg = (char *) inp; + PRINTMSG(msg, msglen); + } + } + + u->us_clientstate = UPAPCS_BADAUTH; + + UPAPDEBUG(LOG_ERR, ("PAP authentication failed\n")); + auth_withpeer_fail(u->us_unit, PPP_PAP); +} + + +/* + * upap_sauthreq - Send an Authenticate-Request. + */ +static void +upap_sauthreq(upap_state *u) +{ + u_char *outp; + int outlen; + + outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) + + u->us_userlen + u->us_passwdlen; + outp = outpacket_buf[u->us_unit]; + + MAKEHEADER(outp, PPP_PAP); + + PUTCHAR(UPAP_AUTHREQ, outp); + PUTCHAR(++u->us_id, outp); + PUTSHORT(outlen, outp); + PUTCHAR(u->us_userlen, outp); + BCOPY(u->us_user, outp, u->us_userlen); + INCPTR(u->us_userlen, outp); + PUTCHAR(u->us_passwdlen, outp); + BCOPY(u->us_passwd, outp, u->us_passwdlen); + + pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); + + UPAPDEBUG(LOG_INFO, ("pap_sauth: Sent id %d\n", u->us_id)); + + TIMEOUT(upap_timeout, u, u->us_timeouttime); + ++u->us_transmits; + u->us_clientstate = UPAPCS_AUTHREQ; +} + + +/* + * upap_sresp - Send a response (ack or nak). + */ +static void +upap_sresp(upap_state *u, u_char code, u_char id, char *msg, int msglen) +{ + u_char *outp; + int outlen; + + outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen; + outp = outpacket_buf[u->us_unit]; + MAKEHEADER(outp, PPP_PAP); + + PUTCHAR(code, outp); + PUTCHAR(id, outp); + PUTSHORT(outlen, outp); + PUTCHAR(msglen, outp); + BCOPY(msg, outp, msglen); + pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); + + UPAPDEBUG(LOG_INFO, ("pap_sresp: Sent code %d, id %d s=%d\n", code, id, u->us_clientstate)); +} + +#if PPP_ADDITIONAL_CALLBACKS +static char *upap_codenames[] = { + "AuthReq", "AuthAck", "AuthNak" +}; + +/* + * upap_printpkt - print the contents of a PAP packet. + */ +static int upap_printpkt( + u_char *p, + int plen, + void (*printer) (void *, char *, ...), + void *arg +) +{ + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(plen); + LWIP_UNUSED_ARG(printer); + LWIP_UNUSED_ARG(arg); + return 0; +} +#endif /* PPP_ADDITIONAL_CALLBACKS */ + +#endif /* PAP_SUPPORT */ + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.h new file mode 100644 index 0000000..c99a204 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.h @@ -0,0 +1,118 @@ +/***************************************************************************** +* pap.h - PPP Password Authentication Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * upap.h - User/Password Authentication Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef PAP_H +#define PAP_H + +#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +/* + * Packet header = Code, id, length. + */ +#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) + + +/* + * UPAP codes. + */ +#define UPAP_AUTHREQ 1 /* Authenticate-Request */ +#define UPAP_AUTHACK 2 /* Authenticate-Ack */ +#define UPAP_AUTHNAK 3 /* Authenticate-Nak */ + +/* + * Each interface is described by upap structure. + */ +typedef struct upap_state { + int us_unit; /* Interface unit number */ + const char *us_user; /* User */ + int us_userlen; /* User length */ + const char *us_passwd; /* Password */ + int us_passwdlen; /* Password length */ + int us_clientstate; /* Client state */ + int us_serverstate; /* Server state */ + u_char us_id; /* Current id */ + int us_timeouttime; /* Timeout (seconds) for auth-req retrans. */ + int us_transmits; /* Number of auth-reqs sent */ + int us_maxtransmits; /* Maximum number of auth-reqs to send */ + int us_reqtimeout; /* Time to wait for auth-req from peer */ +} upap_state; + +/* + * Client states. + */ +#define UPAPCS_INITIAL 0 /* Connection down */ +#define UPAPCS_CLOSED 1 /* Connection up, haven't requested auth */ +#define UPAPCS_PENDING 2 /* Connection down, have requested auth */ +#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */ +#define UPAPCS_OPEN 4 /* We've received an Ack */ +#define UPAPCS_BADAUTH 5 /* We've received a Nak */ + +/* + * Server states. + */ +#define UPAPSS_INITIAL 0 /* Connection down */ +#define UPAPSS_CLOSED 1 /* Connection up, haven't requested auth */ +#define UPAPSS_PENDING 2 /* Connection down, have requested auth */ +#define UPAPSS_LISTEN 3 /* Listening for an Authenticate */ +#define UPAPSS_OPEN 4 /* We've sent an Ack */ +#define UPAPSS_BADAUTH 5 /* We've sent a Nak */ + + +extern upap_state upap[]; + +void upap_authwithpeer (int, char *, char *); +void upap_authpeer (int); + +extern struct protent pap_protent; + +#endif /* PAP_SUPPORT */ + +#endif /* PAP_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.c new file mode 100644 index 0000000..e9b433b --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.c @@ -0,0 +1,2020 @@ +/***************************************************************************** +* ppp.c - Network Point to Point Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ + +/* + * ppp_defs.h - PPP definitions. + * + * if_pppvar.h - private structures and declarations for PPP. + * + * Copyright (c) 1994 The Australian National University. + * All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, provided that the above copyright + * notice appears in all copies. This software is provided without any + * warranty, express or implied. The Australian National University + * makes no representations about the suitability of this software for + * any purpose. + * + * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY + * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES + * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, + * OR MODIFICATIONS. + */ + +/* + * if_ppp.h - Point-to-Point Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/ip.h" /* for ip_input() */ + +#include "ppp.h" +#include "pppdebug.h" + +#include "randm.h" +#include "fsm.h" +#if PAP_SUPPORT +#include "pap.h" +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT +#include "chap.h" +#endif /* CHAP_SUPPORT */ +#include "ipcp.h" +#include "lcp.h" +#include "magic.h" +#include "auth.h" +#if VJ_SUPPORT +#include "vj.h" +#endif /* VJ_SUPPORT */ +#if PPPOE_SUPPORT +#include "netif/ppp_oe.h" +#endif /* PPPOE_SUPPORT */ + +#include "lwip/tcpip.h" +#include "lwip/api.h" +#include "lwip/snmp.h" + +#include + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + +/** PPP_INPROC_MULTITHREADED==1 call pppInput using tcpip_callback(). + * Set this to 0 if pppInProc is called inside tcpip_thread or with NO_SYS==1. + * Default is 1 for NO_SYS==0 (multithreaded) and 0 for NO_SYS==1 (single-threaded). + */ +#ifndef PPP_INPROC_MULTITHREADED +#define PPP_INPROC_MULTITHREADED (NO_SYS==0) +#endif + +/** PPP_INPROC_OWNTHREAD==1: start a dedicated RX thread per PPP session. + * Default is 0: call pppos_input() for received raw characters, charcater + * reception is up to the port */ +#ifndef PPP_INPROC_OWNTHREAD +#define PPP_INPROC_OWNTHREAD PPP_INPROC_MULTITHREADED +#endif + +#if PPP_INPROC_OWNTHREAD && !PPP_INPROC_MULTITHREADED + #error "PPP_INPROC_OWNTHREAD needs PPP_INPROC_MULTITHREADED==1" +#endif + +/* + * The basic PPP frame. + */ +#define PPP_ADDRESS(p) (((u_char *)(p))[0]) +#define PPP_CONTROL(p) (((u_char *)(p))[1]) +#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3]) + +/* PPP packet parser states. Current state indicates operation yet to be + * completed. */ +typedef enum { + PDIDLE = 0, /* Idle state - waiting. */ + PDSTART, /* Process start flag. */ + PDADDRESS, /* Process address field. */ + PDCONTROL, /* Process control field. */ + PDPROTOCOL1, /* Process protocol field 1. */ + PDPROTOCOL2, /* Process protocol field 2. */ + PDDATA /* Process data byte. */ +} PPPDevStates; + +#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07]) + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ + +/** RX buffer size: this may be configured smaller! */ +#ifndef PPPOS_RX_BUFSIZE +#define PPPOS_RX_BUFSIZE (PPP_MRU + PPP_HDRLEN) +#endif + +typedef struct PPPControlRx_s { + /** unit number / ppp descriptor */ + int pd; + /** the rx file descriptor */ + sio_fd_t fd; + /** receive buffer - encoded data is stored here */ + u_char rxbuf[PPPOS_RX_BUFSIZE]; + + /* The input packet. */ + struct pbuf *inHead, *inTail; + +#if PPPOS_SUPPORT + u16_t inProtocol; /* The input protocol code. */ + u16_t inFCS; /* Input Frame Check Sequence value. */ +#endif /* PPPOS_SUPPORT */ + PPPDevStates inState; /* The input process state. */ + char inEscaped; /* Escape next character. */ + ext_accm inACCM; /* Async-Ctl-Char-Map for input. */ +} PPPControlRx; + +/* + * PPP interface control block. + */ +typedef struct PPPControl_s { + PPPControlRx rx; + char openFlag; /* True when in use. */ +#if PPPOE_SUPPORT + struct netif *ethif; + struct pppoe_softc *pppoe_sc; +#endif /* PPPOE_SUPPORT */ + int if_up; /* True when the interface is up. */ + int errCode; /* Code indicating why interface is down. */ +#if PPPOS_SUPPORT + sio_fd_t fd; /* File device ID of port. */ +#endif /* PPPOS_SUPPORT */ + u16_t mtu; /* Peer's mru */ + int pcomp; /* Does peer accept protocol compression? */ + int accomp; /* Does peer accept addr/ctl compression? */ + u_long lastXMit; /* Time of last transmission. */ + ext_accm outACCM; /* Async-Ctl-Char-Map for output. */ +#if PPPOS_SUPPORT && VJ_SUPPORT + int vjEnabled; /* Flag indicating VJ compression enabled. */ + struct vjcompress vjComp; /* Van Jacobson compression header. */ +#endif /* PPPOS_SUPPORT && VJ_SUPPORT */ + + struct netif netif; + + struct ppp_addrs addrs; + + void (*linkStatusCB)(void *ctx, int errCode, void *arg); + void *linkStatusCtx; + +} PPPControl; + + +/* + * Ioctl definitions. + */ + +struct npioctl { + int protocol; /* PPP procotol, e.g. PPP_IP */ + enum NPmode mode; +}; + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +#if PPPOS_SUPPORT +#if PPP_INPROC_OWNTHREAD +static void pppInputThread(void *arg); +#endif /* PPP_INPROC_OWNTHREAD */ +static void pppDrop(PPPControlRx *pcrx); +static void pppInProc(PPPControlRx *pcrx, u_char *s, int l); +#endif /* PPPOS_SUPPORT */ + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +u_long subnetMask; + +static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */ + +/* + * PPP Data Link Layer "protocol" table. + * One entry per supported protocol. + * The last entry must be NULL. + */ +struct protent *ppp_protocols[] = { + &lcp_protent, +#if PAP_SUPPORT + &pap_protent, +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + &chap_protent, +#endif /* CHAP_SUPPORT */ +#if CBCP_SUPPORT + &cbcp_protent, +#endif /* CBCP_SUPPORT */ + &ipcp_protent, +#if CCP_SUPPORT + &ccp_protent, +#endif /* CCP_SUPPORT */ + NULL +}; + + +/* + * Buffers for outgoing packets. This must be accessed only from the appropriate + * PPP task so that it doesn't need to be protected to avoid collisions. + */ +u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ + +#if PPPOS_SUPPORT +/* + * FCS lookup table as calculated by genfcstab. + * @todo: smaller, slower implementation for lower memory footprint? + */ +static const u_short fcstab[256] = { + 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, + 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, + 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, + 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, + 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, + 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, + 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, + 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, + 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, + 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, + 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, + 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, + 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, + 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, + 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, + 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, + 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, + 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, + 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, + 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, + 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, + 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, + 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, + 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, + 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, + 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, + 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, + 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, + 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, + 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, + 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, + 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 +}; + +/* PPP's Asynchronous-Control-Character-Map. The mask array is used + * to select the specific bit for a character. */ +static u_char pppACCMMask[] = { + 0x01, + 0x02, + 0x04, + 0x08, + 0x10, + 0x20, + 0x40, + 0x80 +}; + +/** Wake up the task blocked in reading from serial line (if any) */ +static void +pppRecvWakeup(int pd) +{ + PPPDEBUG(LOG_DEBUG, ("pppRecvWakeup: unit %d\n", pd)); + if (pppControl[pd].openFlag != 0) { + sio_read_abort(pppControl[pd].fd); + } +} +#endif /* PPPOS_SUPPORT */ + +void +pppLinkTerminated(int pd) +{ + PPPDEBUG(LOG_DEBUG, ("pppLinkTerminated: unit %d\n", pd)); + +#if PPPOE_SUPPORT + if (pppControl[pd].ethif) { + pppoe_disconnect(pppControl[pd].pppoe_sc); + } else +#endif /* PPPOE_SUPPORT */ + { +#if PPPOS_SUPPORT + PPPControl* pc; + pppRecvWakeup(pd); + pc = &pppControl[pd]; + + PPPDEBUG(LOG_DEBUG, ("pppLinkTerminated: unit %d: linkStatusCB=%p errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); + if (pc->linkStatusCB) { + pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL); + } + + pc->openFlag = 0;/**/ +#endif /* PPPOS_SUPPORT */ + } + PPPDEBUG(LOG_DEBUG, ("pppLinkTerminated: finished.\n")); +} + +void +pppLinkDown(int pd) +{ + PPPDEBUG(LOG_DEBUG, ("pppLinkDown: unit %d\n", pd)); + +#if PPPOE_SUPPORT + if (pppControl[pd].ethif) { + pppoe_disconnect(pppControl[pd].pppoe_sc); + } else +#endif /* PPPOE_SUPPORT */ + { +#if PPPOS_SUPPORT + pppRecvWakeup(pd); +#endif /* PPPOS_SUPPORT */ + } +} + +/** Initiate LCP open request */ +static void +pppStart(int pd) +{ + PPPDEBUG(LOG_DEBUG, ("pppStart: unit %d\n", pd)); + lcp_lowerup(pd); + lcp_open(pd); /* Start protocol */ + PPPDEBUG(LOG_DEBUG, ("pppStart: finished\n")); +} + +/** LCP close request */ +static void +pppStop(int pd) +{ + PPPDEBUG(LOG_DEBUG, ("pppStop: unit %d\n", pd)); + lcp_close(pd, "User request"); +} + +/** Called when carrier/link is lost */ +static void +pppHup(int pd) +{ + PPPDEBUG(LOG_DEBUG, ("pppHupCB: unit %d\n", pd)); + lcp_lowerdown(pd); + link_terminated(pd); +} + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* Initialize the PPP subsystem. */ + +struct ppp_settings ppp_settings; + +void +pppInit(void) +{ + struct protent *protp; + int i, j; + + memset(&ppp_settings, 0, sizeof(ppp_settings)); + ppp_settings.usepeerdns = 1; + pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL); + + magicInit(); + + subnetMask = PP_HTONL(0xffffff00UL); + + for (i = 0; i < NUM_PPP; i++) { + /* Initialize each protocol to the standard option set. */ + for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j) { + (*protp->init)(i); + } + } +} + +void +pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd) +{ + switch(authType) { + case PPPAUTHTYPE_NONE: + default: +#ifdef LWIP_PPP_STRICT_PAP_REJECT + ppp_settings.refuse_pap = 1; +#else /* LWIP_PPP_STRICT_PAP_REJECT */ + /* some providers request pap and accept an empty login/pw */ + ppp_settings.refuse_pap = 0; +#endif /* LWIP_PPP_STRICT_PAP_REJECT */ + ppp_settings.refuse_chap = 1; + break; + + case PPPAUTHTYPE_ANY: + /* Warning: Using PPPAUTHTYPE_ANY might have security consequences. + * RFC 1994 says: + * + * In practice, within or associated with each PPP server, there is a + * database which associates "user" names with authentication + * information ("secrets"). It is not anticipated that a particular + * named user would be authenticated by multiple methods. This would + * make the user vulnerable to attacks which negotiate the least secure + * method from among a set (such as PAP rather than CHAP). If the same + * secret was used, PAP would reveal the secret to be used later with + * CHAP. + * + * Instead, for each user name there should be an indication of exactly + * one method used to authenticate that user name. If a user needs to + * make use of different authentication methods under different + * circumstances, then distinct user names SHOULD be employed, each of + * which identifies exactly one authentication method. + * + */ + ppp_settings.refuse_pap = 0; + ppp_settings.refuse_chap = 0; + break; + + case PPPAUTHTYPE_PAP: + ppp_settings.refuse_pap = 0; + ppp_settings.refuse_chap = 1; + break; + + case PPPAUTHTYPE_CHAP: + ppp_settings.refuse_pap = 1; + ppp_settings.refuse_chap = 0; + break; + } + + if(user) { + strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1); + ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0'; + } else { + ppp_settings.user[0] = '\0'; + } + + if(passwd) { + strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1); + ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0'; + } else { + ppp_settings.passwd[0] = '\0'; + } +} + +#if PPPOS_SUPPORT +/** Open a new PPP connection using the given I/O device. + * This initializes the PPP control block but does not + * attempt to negotiate the LCP session. If this port + * connects to a modem, the modem connection must be + * established before calling this. + * Return a new PPP connection descriptor on success or + * an error code (negative) on failure. + * + * pppOpen() is directly defined to this function. + */ +int +pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx) +{ + PPPControl *pc; + int pd; + + if (linkStatusCB == NULL) { + /* PPP is single-threaded: without a callback, + * there is no way to know when the link is up. */ + return PPPERR_PARAM; + } + + /* Find a free PPP session descriptor. */ + for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++); + + if (pd >= NUM_PPP) { + pd = PPPERR_OPEN; + } else { + pc = &pppControl[pd]; + /* @todo: is this correct or do I overwrite something? */ + memset(pc, 0, sizeof(PPPControl)); + pc->rx.pd = pd; + pc->rx.fd = fd; + + pc->openFlag = 1; + pc->fd = fd; + +#if VJ_SUPPORT + vj_compress_init(&pc->vjComp); +#endif /* VJ_SUPPORT */ + + /* + * Default the in and out accm so that escape and flag characters + * are always escaped. + */ + pc->rx.inACCM[15] = 0x60; /* no need to protect since RX is not running */ + pc->outACCM[15] = 0x60; + + pc->linkStatusCB = linkStatusCB; + pc->linkStatusCtx = linkStatusCtx; + + /* + * Start the connection and handle incoming events (packet or timeout). + */ + PPPDEBUG(LOG_INFO, ("pppOverSerialOpen: unit %d: Connecting\n", pd)); + pppStart(pd); +#if PPP_INPROC_OWNTHREAD + sys_thread_new(PPP_THREAD_NAME, pppInputThread, (void*)&pc->rx, PPP_THREAD_STACKSIZE, PPP_THREAD_PRIO); +#endif + } + + return pd; +} +#endif /* PPPOS_SUPPORT */ + +#if PPPOE_SUPPORT +static void pppOverEthernetLinkStatusCB(int pd, int up); + +void +pppOverEthernetClose(int pd) +{ + PPPControl* pc = &pppControl[pd]; + + /* *TJL* There's no lcp_deinit */ + lcp_close(pd, NULL); + + pppoe_destroy(&pc->netif); +} + +int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx) +{ + PPPControl *pc; + int pd; + + LWIP_UNUSED_ARG(service_name); + LWIP_UNUSED_ARG(concentrator_name); + + if (linkStatusCB == NULL) { + /* PPP is single-threaded: without a callback, + * there is no way to know when the link is up. */ + return PPPERR_PARAM; + } + + /* Find a free PPP session descriptor. Critical region? */ + for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++); + if (pd >= NUM_PPP) { + pd = PPPERR_OPEN; + } else { + pc = &pppControl[pd]; + memset(pc, 0, sizeof(PPPControl)); + pc->openFlag = 1; + pc->ethif = ethif; + + pc->linkStatusCB = linkStatusCB; + pc->linkStatusCtx = linkStatusCtx; + + lcp_wantoptions[pd].mru = PPPOE_MAXMTU; + lcp_wantoptions[pd].neg_asyncmap = 0; + lcp_wantoptions[pd].neg_pcompression = 0; + lcp_wantoptions[pd].neg_accompression = 0; + + lcp_allowoptions[pd].mru = PPPOE_MAXMTU; + lcp_allowoptions[pd].neg_asyncmap = 0; + lcp_allowoptions[pd].neg_pcompression = 0; + lcp_allowoptions[pd].neg_accompression = 0; + + if(pppoe_create(ethif, pd, pppOverEthernetLinkStatusCB, &pc->pppoe_sc) != ERR_OK) { + pc->openFlag = 0; + return PPPERR_OPEN; + } + + pppoe_connect(pc->pppoe_sc); + } + + return pd; +} +#endif /* PPPOE_SUPPORT */ + + +/* Close a PPP connection and release the descriptor. + * Any outstanding packets in the queues are dropped. + * Return 0 on success, an error code on failure. */ +int +pppClose(int pd) +{ + PPPControl *pc = &pppControl[pd]; + int st = 0; + + PPPDEBUG(LOG_DEBUG, ("pppClose() called\n")); + + /* Disconnect */ +#if PPPOE_SUPPORT + if(pc->ethif) { + PPPDEBUG(LOG_DEBUG, ("pppClose: unit %d kill_link -> pppStop\n", pd)); + pc->errCode = PPPERR_USER; + /* This will leave us at PHASE_DEAD. */ + pppStop(pd); + } else +#endif /* PPPOE_SUPPORT */ + { +#if PPPOS_SUPPORT + PPPDEBUG(LOG_DEBUG, ("pppClose: unit %d kill_link -> pppStop\n", pd)); + pc->errCode = PPPERR_USER; + /* This will leave us at PHASE_DEAD. */ + pppStop(pd); + pppRecvWakeup(pd); +#endif /* PPPOS_SUPPORT */ + } + + return st; +} + +/* This function is called when carrier is lost on the PPP channel. */ +void +pppSigHUP(int pd) +{ + PPPDEBUG(LOG_DEBUG, ("pppSigHUP: unit %d sig_hup -> pppHupCB\n", pd)); + pppHup(pd); +} + +#if PPPOS_SUPPORT +static void +nPut(PPPControl *pc, struct pbuf *nb) +{ + struct pbuf *b; + int c; + + for(b = nb; b != NULL; b = b->next) { + if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) { + PPPDEBUG(LOG_WARNING, + ("PPP nPut: incomplete sio_write(fd:%"SZT_F", len:%d, c: 0x%"X8_F") c = %d\n", (size_t)pc->fd, b->len, c, c)); + LINK_STATS_INC(link.err); + pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */ + snmp_inc_ifoutdiscards(&pc->netif); + pbuf_free(nb); + return; + } + } + + snmp_add_ifoutoctets(&pc->netif, nb->tot_len); + snmp_inc_ifoutucastpkts(&pc->netif); + pbuf_free(nb); + LINK_STATS_INC(link.xmit); +} + +/* + * pppAppend - append given character to end of given pbuf. If outACCM + * is not NULL and the character needs to be escaped, do so. + * If pbuf is full, append another. + * Return the current pbuf. + */ +static struct pbuf * +pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM) +{ + struct pbuf *tb = nb; + + /* Make sure there is room for the character and an escape code. + * Sure we don't quite fill the buffer if the character doesn't + * get escaped but is one character worth complicating this? */ + /* Note: We assume no packet header. */ + if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) { + tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (tb) { + nb->next = tb; + } else { + LINK_STATS_INC(link.memerr); + } + nb = tb; + } + + if (nb) { + if (outACCM && ESCAPE_P(*outACCM, c)) { + *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE; + *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS; + } else { + *((u_char*)nb->payload + nb->len++) = c; + } + } + + return tb; +} +#endif /* PPPOS_SUPPORT */ + +#if PPPOE_SUPPORT +static err_t +pppifOutputOverEthernet(int pd, struct pbuf *p) +{ + PPPControl *pc = &pppControl[pd]; + struct pbuf *pb; + u_short protocol = PPP_IP; + int i=0; + u16_t tot_len; + + /* @todo: try to use pbuf_header() here! */ + pb = pbuf_alloc(PBUF_LINK, PPPOE_HDRLEN + sizeof(protocol), PBUF_RAM); + if(!pb) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.proterr); + snmp_inc_ifoutdiscards(&pc->netif); + return ERR_MEM; + } + + pbuf_header(pb, -(s16_t)PPPOE_HDRLEN); + + pc->lastXMit = sys_jiffies(); + + if (!pc->pcomp || protocol > 0xFF) { + *((u_char*)pb->payload + i++) = (protocol >> 8) & 0xFF; + } + *((u_char*)pb->payload + i) = protocol & 0xFF; + + pbuf_chain(pb, p); + tot_len = pb->tot_len; + + if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) { + LINK_STATS_INC(link.err); + snmp_inc_ifoutdiscards(&pc->netif); + return PPPERR_DEVICE; + } + + snmp_add_ifoutoctets(&pc->netif, tot_len); + snmp_inc_ifoutucastpkts(&pc->netif); + LINK_STATS_INC(link.xmit); + return ERR_OK; +} +#endif /* PPPOE_SUPPORT */ + +/* Send a packet on the given connection. */ +static err_t +pppifOutput(struct netif *netif, struct pbuf *pb, ip_addr_t *ipaddr) +{ + int pd = (int)(size_t)netif->state; + PPPControl *pc = &pppControl[pd]; +#if PPPOS_SUPPORT + u_short protocol = PPP_IP; + u_int fcsOut = PPP_INITFCS; + struct pbuf *headMB = NULL, *tailMB = NULL, *p; + u_char c; +#endif /* PPPOS_SUPPORT */ + + LWIP_UNUSED_ARG(ipaddr); + + /* Validate parameters. */ + /* We let any protocol value go through - it can't hurt us + * and the peer will just drop it if it's not accepting it. */ + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) { + PPPDEBUG(LOG_WARNING, ("pppifOutput[%d]: bad parms prot=%d pb=%p\n", + pd, PPP_IP, pb)); + LINK_STATS_INC(link.opterr); + LINK_STATS_INC(link.drop); + snmp_inc_ifoutdiscards(netif); + return ERR_ARG; + } + + /* Check that the link is up. */ + if (lcp_phase[pd] == PHASE_DEAD) { + PPPDEBUG(LOG_ERR, ("pppifOutput[%d]: link not up\n", pd)); + LINK_STATS_INC(link.rterr); + LINK_STATS_INC(link.drop); + snmp_inc_ifoutdiscards(netif); + return ERR_RTE; + } + +#if PPPOE_SUPPORT + if(pc->ethif) { + return pppifOutputOverEthernet(pd, pb); + } +#endif /* PPPOE_SUPPORT */ + +#if PPPOS_SUPPORT + /* Grab an output buffer. */ + headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (headMB == NULL) { + PPPDEBUG(LOG_WARNING, ("pppifOutput[%d]: first alloc fail\n", pd)); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + snmp_inc_ifoutdiscards(netif); + return ERR_MEM; + } + +#if VJ_SUPPORT + /* + * Attempt Van Jacobson header compression if VJ is configured and + * this is an IP packet. + */ + if (protocol == PPP_IP && pc->vjEnabled) { + switch (vj_compress_tcp(&pc->vjComp, pb)) { + case TYPE_IP: + /* No change... + protocol = PPP_IP_PROTOCOL; */ + break; + case TYPE_COMPRESSED_TCP: + protocol = PPP_VJC_COMP; + break; + case TYPE_UNCOMPRESSED_TCP: + protocol = PPP_VJC_UNCOMP; + break; + default: + PPPDEBUG(LOG_WARNING, ("pppifOutput[%d]: bad IP packet\n", pd)); + LINK_STATS_INC(link.proterr); + LINK_STATS_INC(link.drop); + snmp_inc_ifoutdiscards(netif); + pbuf_free(headMB); + return ERR_VAL; + } + } +#endif /* VJ_SUPPORT */ + + tailMB = headMB; + + /* Build the PPP header. */ + if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) { + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + } + + pc->lastXMit = sys_jiffies(); + if (!pc->accomp) { + fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS); + tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM); + fcsOut = PPP_FCS(fcsOut, PPP_UI); + tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM); + } + if (!pc->pcomp || protocol > 0xFF) { + c = (protocol >> 8) & 0xFF; + fcsOut = PPP_FCS(fcsOut, c); + tailMB = pppAppend(c, tailMB, &pc->outACCM); + } + c = protocol & 0xFF; + fcsOut = PPP_FCS(fcsOut, c); + tailMB = pppAppend(c, tailMB, &pc->outACCM); + + /* Load packet. */ + for(p = pb; p; p = p->next) { + int n; + u_char *sPtr; + + sPtr = (u_char*)p->payload; + n = p->len; + while (n-- > 0) { + c = *sPtr++; + + /* Update FCS before checking for special characters. */ + fcsOut = PPP_FCS(fcsOut, c); + + /* Copy to output buffer escaping special characters. */ + tailMB = pppAppend(c, tailMB, &pc->outACCM); + } + } + + /* Add FCS and trailing flag. */ + c = ~fcsOut & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + c = (~fcsOut >> 8) & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + + /* If we failed to complete the packet, throw it away. */ + if (!tailMB) { + PPPDEBUG(LOG_WARNING, + ("pppifOutput[%d]: Alloc err - dropping proto=%d\n", + pd, protocol)); + pbuf_free(headMB); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + snmp_inc_ifoutdiscards(netif); + return ERR_MEM; + } + + /* Send it. */ + PPPDEBUG(LOG_INFO, ("pppifOutput[%d]: proto=0x%"X16_F"\n", pd, protocol)); + + nPut(pc, headMB); +#endif /* PPPOS_SUPPORT */ + + return ERR_OK; +} + +/* Get and set parameters for the given connection. + * Return 0 on success, an error code on failure. */ +int +pppIOCtl(int pd, int cmd, void *arg) +{ + PPPControl *pc = &pppControl[pd]; + int st = 0; + + if (pd < 0 || pd >= NUM_PPP) { + st = PPPERR_PARAM; + } else { + switch(cmd) { + case PPPCTLG_UPSTATUS: /* Get the PPP up status. */ + if (arg) { + *(int *)arg = (int)(pc->if_up); + } else { + st = PPPERR_PARAM; + } + break; + case PPPCTLS_ERRCODE: /* Set the PPP error code. */ + if (arg) { + pc->errCode = *(int *)arg; + } else { + st = PPPERR_PARAM; + } + break; + case PPPCTLG_ERRCODE: /* Get the PPP error code. */ + if (arg) { + *(int *)arg = (int)(pc->errCode); + } else { + st = PPPERR_PARAM; + } + break; +#if PPPOS_SUPPORT + case PPPCTLG_FD: /* Get the fd associated with the ppp */ + if (arg) { + *(sio_fd_t *)arg = pc->fd; + } else { + st = PPPERR_PARAM; + } + break; +#endif /* PPPOS_SUPPORT */ + default: + st = PPPERR_PARAM; + break; + } + } + + return st; +} + +/* + * Return the Maximum Transmission Unit for the given PPP connection. + */ +u_short +pppMTU(int pd) +{ + PPPControl *pc = &pppControl[pd]; + u_short st; + + /* Validate parameters. */ + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + } else { + st = pc->mtu; + } + + return st; +} + +#if PPPOE_SUPPORT +int +pppWriteOverEthernet(int pd, const u_char *s, int n) +{ + PPPControl *pc = &pppControl[pd]; + struct pbuf *pb; + + /* skip address & flags */ + s += 2; + n -= 2; + + LWIP_ASSERT("PPPOE_HDRLEN + n <= 0xffff", PPPOE_HDRLEN + n <= 0xffff); + pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HDRLEN + n), PBUF_RAM); + if(!pb) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.proterr); + snmp_inc_ifoutdiscards(&pc->netif); + return PPPERR_ALLOC; + } + + pbuf_header(pb, -(s16_t)PPPOE_HDRLEN); + + pc->lastXMit = sys_jiffies(); + + MEMCPY(pb->payload, s, n); + + if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) { + LINK_STATS_INC(link.err); + snmp_inc_ifoutdiscards(&pc->netif); + return PPPERR_DEVICE; + } + + snmp_add_ifoutoctets(&pc->netif, (u16_t)n); + snmp_inc_ifoutucastpkts(&pc->netif); + LINK_STATS_INC(link.xmit); + return PPPERR_NONE; +} +#endif /* PPPOE_SUPPORT */ + +/* + * Write n characters to a ppp link. + * RETURN: >= 0 Number of characters written + * -1 Failed to write to device + */ +int +pppWrite(int pd, const u_char *s, int n) +{ + PPPControl *pc = &pppControl[pd]; +#if PPPOS_SUPPORT + u_char c; + u_int fcsOut; + struct pbuf *headMB, *tailMB; +#endif /* PPPOS_SUPPORT */ + +#if PPPOE_SUPPORT + if(pc->ethif) { + return pppWriteOverEthernet(pd, s, n); + } +#endif /* PPPOE_SUPPORT */ + +#if PPPOS_SUPPORT + headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (headMB == NULL) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.proterr); + snmp_inc_ifoutdiscards(&pc->netif); + return PPPERR_ALLOC; + } + + tailMB = headMB; + + /* If the link has been idle, we'll send a fresh flag character to + * flush any noise. */ + if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) { + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + } + pc->lastXMit = sys_jiffies(); + + fcsOut = PPP_INITFCS; + /* Load output buffer. */ + while (n-- > 0) { + c = *s++; + + /* Update FCS before checking for special characters. */ + fcsOut = PPP_FCS(fcsOut, c); + + /* Copy to output buffer escaping special characters. */ + tailMB = pppAppend(c, tailMB, &pc->outACCM); + } + + /* Add FCS and trailing flag. */ + c = ~fcsOut & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + c = (~fcsOut >> 8) & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + + /* If we failed to complete the packet, throw it away. + * Otherwise send it. */ + if (!tailMB) { + PPPDEBUG(LOG_WARNING, + ("pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len)); + /*"pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ + pbuf_free(headMB); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.proterr); + snmp_inc_ifoutdiscards(&pc->netif); + return PPPERR_ALLOC; + } + + PPPDEBUG(LOG_INFO, ("pppWrite[%d]: len=%d\n", pd, headMB->len)); + /* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ + nPut(pc, headMB); +#endif /* PPPOS_SUPPORT */ + + return PPPERR_NONE; +} + +/* + * ppp_send_config - configure the transmit characteristics of + * the ppp interface. + */ +void +ppp_send_config( int unit, u16_t mtu, u32_t asyncmap, int pcomp, int accomp) +{ + PPPControl *pc = &pppControl[unit]; + int i; + + pc->mtu = mtu; + pc->pcomp = pcomp; + pc->accomp = accomp; + + /* Load the ACCM bits for the 32 control codes. */ + for (i = 0; i < 32/8; i++) { + pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF); + } + PPPDEBUG(LOG_INFO, ("ppp_send_config[%d]: outACCM=%X %X %X %X\n", + unit, + pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3])); +} + + +/* + * ppp_set_xaccm - set the extended transmit ACCM for the interface. + */ +void +ppp_set_xaccm(int unit, ext_accm *accm) +{ + SMEMCPY(pppControl[unit].outACCM, accm, sizeof(ext_accm)); + PPPDEBUG(LOG_INFO, ("ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n", + unit, + pppControl[unit].outACCM[0], + pppControl[unit].outACCM[1], + pppControl[unit].outACCM[2], + pppControl[unit].outACCM[3])); +} + + +/* + * ppp_recv_config - configure the receive-side characteristics of + * the ppp interface. + */ +void +ppp_recv_config( int unit, int mru, u32_t asyncmap, int pcomp, int accomp) +{ + PPPControl *pc = &pppControl[unit]; + int i; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_UNUSED_ARG(accomp); + LWIP_UNUSED_ARG(pcomp); + LWIP_UNUSED_ARG(mru); + + /* Load the ACCM bits for the 32 control codes. */ + SYS_ARCH_PROTECT(lev); + for (i = 0; i < 32 / 8; i++) { + /* @todo: does this work? ext_accm has been modified from pppd! */ + pc->rx.inACCM[i] = (u_char)(asyncmap >> (i * 8)); + } + SYS_ARCH_UNPROTECT(lev); + PPPDEBUG(LOG_INFO, ("ppp_recv_config[%d]: inACCM=%X %X %X %X\n", + unit, + pc->rx.inACCM[0], pc->rx.inACCM[1], pc->rx.inACCM[2], pc->rx.inACCM[3])); +} + +#if 0 +/* + * ccp_test - ask kernel whether a given compression method + * is acceptable for use. Returns 1 if the method and parameters + * are OK, 0 if the method is known but the parameters are not OK + * (e.g. code size should be reduced), or -1 if the method is unknown. + */ +int +ccp_test( int unit, int opt_len, int for_transmit, u_char *opt_ptr) +{ + return 0; /* XXX Currently no compression. */ +} + +/* + * ccp_flags_set - inform kernel about the current state of CCP. + */ +void +ccp_flags_set(int unit, int isopen, int isup) +{ + /* XXX */ +} + +/* + * ccp_fatal_error - returns 1 if decompression was disabled as a + * result of an error detected after decompression of a packet, + * 0 otherwise. This is necessary because of patent nonsense. + */ +int +ccp_fatal_error(int unit) +{ + /* XXX */ + return 0; +} +#endif + +/* + * get_idle_time - return how long the link has been idle. + */ +int +get_idle_time(int u, struct ppp_idle *ip) +{ + /* XXX */ + LWIP_UNUSED_ARG(u); + LWIP_UNUSED_ARG(ip); + + return 0; +} + + +/* + * Return user specified netmask, modified by any mask we might determine + * for address `addr' (in network byte order). + * Here we scan through the system's list of interfaces, looking for + * any non-point-to-point interfaces which might appear to be on the same + * network as `addr'. If we find any, we OR in their netmask to the + * user-specified netmask. + */ +u32_t +GetMask(u32_t addr) +{ + u32_t mask, nmask; + + htonl(addr); + if (IP_CLASSA(addr)) { /* determine network mask for address class */ + nmask = IP_CLASSA_NET; + } else if (IP_CLASSB(addr)) { + nmask = IP_CLASSB_NET; + } else { + nmask = IP_CLASSC_NET; + } + + /* class D nets are disallowed by bad_ip_adrs */ + mask = subnetMask | htonl(nmask); + + /* XXX + * Scan through the system's network interfaces. + * Get each netmask and OR them into our mask. + */ + + return mask; +} + +/* + * sifvjcomp - config tcp header compression + */ +int +sifvjcomp(int pd, int vjcomp, u8_t cidcomp, u8_t maxcid) +{ +#if PPPOS_SUPPORT && VJ_SUPPORT + PPPControl *pc = &pppControl[pd]; + + pc->vjEnabled = vjcomp; + pc->vjComp.compressSlot = cidcomp; + pc->vjComp.maxSlotIndex = maxcid; + PPPDEBUG(LOG_INFO, ("sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n", + vjcomp, cidcomp, maxcid)); +#else /* PPPOS_SUPPORT && VJ_SUPPORT */ + LWIP_UNUSED_ARG(pd); + LWIP_UNUSED_ARG(vjcomp); + LWIP_UNUSED_ARG(cidcomp); + LWIP_UNUSED_ARG(maxcid); +#endif /* PPPOS_SUPPORT && VJ_SUPPORT */ + + return 0; +} + +/* + * pppifNetifInit - netif init callback + */ +static err_t +pppifNetifInit(struct netif *netif) +{ + netif->name[0] = 'p'; + netif->name[1] = 'p'; + netif->output = pppifOutput; + netif->mtu = pppMTU((int)(size_t)netif->state); + netif->flags = NETIF_FLAG_POINTTOPOINT | NETIF_FLAG_LINK_UP; +#if LWIP_NETIF_HOSTNAME + /* @todo: Initialize interface hostname */ + /* netif_set_hostname(netif, "lwip"); */ +#endif /* LWIP_NETIF_HOSTNAME */ + return ERR_OK; +} + + +/* + * sifup - Config the interface up and enable IP packets to pass. + */ +int +sifup(int pd) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd)); + } else { + netif_remove(&pc->netif); + if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, + &pc->addrs.his_ipaddr, (void *)(size_t)pd, pppifNetifInit, ip_input)) { + netif_set_up(&pc->netif); + pc->if_up = 1; + pc->errCode = PPPERR_NONE; + + PPPDEBUG(LOG_DEBUG, ("sifup: unit %d: linkStatusCB=%p errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); + if (pc->linkStatusCB) { + pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs); + } + } else { + st = 0; + PPPDEBUG(LOG_ERR, ("sifup[%d]: netif_add failed\n", pd)); + } + } + + return st; +} + +/* + * sifnpmode - Set the mode for handling packets for a given NP. + */ +int +sifnpmode(int u, int proto, enum NPmode mode) +{ + LWIP_UNUSED_ARG(u); + LWIP_UNUSED_ARG(proto); + LWIP_UNUSED_ARG(mode); + return 0; +} + +/* + * sifdown - Config the interface down and disable IP. + */ +int +sifdown(int pd) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG(LOG_WARNING, ("sifdown[%d]: bad parms\n", pd)); + } else { + pc->if_up = 0; + /* make sure the netif status callback is called */ + netif_set_down(&pc->netif); + netif_remove(&pc->netif); + PPPDEBUG(LOG_DEBUG, ("sifdown: unit %d: linkStatusCB=%p errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); + if (pc->linkStatusCB) { + pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL); + } + } + return st; +} + +/** + * sifaddr - Config the interface IP addresses and netmask. + * @param pd Interface unit ??? + * @param o Our IP address ??? + * @param h His IP address ??? + * @param m IP subnet mask ??? + * @param ns1 Primary DNS + * @param ns2 Secondary DNS + */ +int +sifaddr( int pd, u32_t o, u32_t h, u32_t m, u32_t ns1, u32_t ns2) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd)); + } else { + SMEMCPY(&pc->addrs.our_ipaddr, &o, sizeof(o)); + SMEMCPY(&pc->addrs.his_ipaddr, &h, sizeof(h)); + SMEMCPY(&pc->addrs.netmask, &m, sizeof(m)); + SMEMCPY(&pc->addrs.dns1, &ns1, sizeof(ns1)); + SMEMCPY(&pc->addrs.dns2, &ns2, sizeof(ns2)); + } + return st; +} + +/** + * cifaddr - Clear the interface IP addresses, and delete routes + * through the interface if possible. + * @param pd Interface unit ??? + * @param o Our IP address ??? + * @param h IP broadcast address ??? + */ +int +cifaddr( int pd, u32_t o, u32_t h) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + LWIP_UNUSED_ARG(o); + LWIP_UNUSED_ARG(h); + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd)); + } else { + IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0); + IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0); + IP4_ADDR(&pc->addrs.netmask, 255,255,255,0); + IP4_ADDR(&pc->addrs.dns1, 0,0,0,0); + IP4_ADDR(&pc->addrs.dns2, 0,0,0,0); + } + return st; +} + +/* + * sifdefaultroute - assign a default route through the address given. + */ +int +sifdefaultroute(int pd, u32_t l, u32_t g) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + LWIP_UNUSED_ARG(l); + LWIP_UNUSED_ARG(g); + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd)); + } else { + netif_set_default(&pc->netif); + } + + /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */ + + return st; +} + +/* + * cifdefaultroute - delete a default route through the address given. + */ +int +cifdefaultroute(int pd, u32_t l, u32_t g) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + LWIP_UNUSED_ARG(l); + LWIP_UNUSED_ARG(g); + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd)); + } else { + netif_set_default(NULL); + } + + return st; +} + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ + +#if PPPOS_SUPPORT && PPP_INPROC_OWNTHREAD +/* The main PPP process function. This implements the state machine according + * to section 4 of RFC 1661: The Point-To-Point Protocol. */ +static void +pppInputThread(void *arg) +{ + int count; + PPPControlRx *pcrx = arg; + + while (lcp_phase[pcrx->pd] != PHASE_DEAD) { + count = sio_read(pcrx->fd, pcrx->rxbuf, PPPOS_RX_BUFSIZE); + if(count > 0) { + pppInProc(pcrx, pcrx->rxbuf, count); + } else { + /* nothing received, give other tasks a chance to run */ + sys_msleep(1); + } + } +} +#endif /* PPPOS_SUPPORT && PPP_INPROC_OWNTHREAD */ + +#if PPPOE_SUPPORT + +void +pppOverEthernetInitFailed(int pd) +{ + PPPControl* pc; + + pppHup(pd); + pppStop(pd); + + pc = &pppControl[pd]; + pppoe_destroy(&pc->netif); + pc->openFlag = 0; + + if(pc->linkStatusCB) { + pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL); + } +} + +static void +pppOverEthernetLinkStatusCB(int pd, int up) +{ + if(up) { + PPPDEBUG(LOG_INFO, ("pppOverEthernetLinkStatusCB: unit %d: Connecting\n", pd)); + pppStart(pd); + } else { + pppOverEthernetInitFailed(pd); + } +} +#endif /* PPPOE_SUPPORT */ + +struct pbuf * +pppSingleBuf(struct pbuf *p) +{ + struct pbuf *q, *b; + u_char *pl; + + if(p->tot_len == p->len) { + return p; + } + + q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if(!q) { + PPPDEBUG(LOG_ERR, + ("pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len)); + return p; /* live dangerously */ + } + + for(b = p, pl = q->payload; b != NULL; b = b->next) { + MEMCPY(pl, b->payload, b->len); + pl += b->len; + } + + pbuf_free(p); + + return q; +} + +struct pppInputHeader { + int unit; + u16_t proto; +}; + +/* + * Pass the processed input packet to the appropriate handler. + * This function and all handlers run in the context of the tcpip_thread + */ +static void +pppInput(void *arg) +{ + struct pbuf *nb = (struct pbuf *)arg; + u16_t protocol; + int pd; + + pd = ((struct pppInputHeader *)nb->payload)->unit; + protocol = ((struct pppInputHeader *)nb->payload)->proto; + + if(pbuf_header(nb, -(int)sizeof(struct pppInputHeader))) { + LWIP_ASSERT("pbuf_header failed\n", 0); + goto drop; + } + + LINK_STATS_INC(link.recv); + snmp_inc_ifinucastpkts(&pppControl[pd].netif); + snmp_add_ifinoctets(&pppControl[pd].netif, nb->tot_len); + + /* + * Toss all non-LCP packets unless LCP is OPEN. + * Until we get past the authentication phase, toss all packets + * except LCP, LQR and authentication packets. + */ + if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) { + if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) || + (lcp_phase[pd] != PHASE_AUTHENTICATE)) { + PPPDEBUG(LOG_INFO, ("pppInput: discarding proto 0x%"X16_F" in phase %d\n", protocol, lcp_phase[pd])); + goto drop; + } + } + + switch(protocol) { + case PPP_VJC_COMP: /* VJ compressed TCP */ +#if PPPOS_SUPPORT && VJ_SUPPORT + PPPDEBUG(LOG_INFO, ("pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len)); + /* + * Clip off the VJ header and prepend the rebuilt TCP/IP header and + * pass the result to IP. + */ + if ((vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) && (pppControl[pd].netif.input)) { + pppControl[pd].netif.input(nb, &pppControl[pd].netif); + return; + } + /* Something's wrong so drop it. */ + PPPDEBUG(LOG_WARNING, ("pppInput[%d]: Dropping VJ compressed\n", pd)); +#else /* PPPOS_SUPPORT && VJ_SUPPORT */ + /* No handler for this protocol so drop the packet. */ + PPPDEBUG(LOG_INFO, ("pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload)); +#endif /* PPPOS_SUPPORT && VJ_SUPPORT */ + break; + + case PPP_VJC_UNCOMP: /* VJ uncompressed TCP */ +#if PPPOS_SUPPORT && VJ_SUPPORT + PPPDEBUG(LOG_INFO, ("pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len)); + /* + * Process the TCP/IP header for VJ header compression and then pass + * the packet to IP. + */ + if ((vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) && pppControl[pd].netif.input) { + pppControl[pd].netif.input(nb, &pppControl[pd].netif); + return; + } + /* Something's wrong so drop it. */ + PPPDEBUG(LOG_WARNING, ("pppInput[%d]: Dropping VJ uncompressed\n", pd)); +#else /* PPPOS_SUPPORT && VJ_SUPPORT */ + /* No handler for this protocol so drop the packet. */ + PPPDEBUG(LOG_INFO, + ("pppInput[%d]: drop VJ UnComp in %d:.*H\n", + pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload)); +#endif /* PPPOS_SUPPORT && VJ_SUPPORT */ + break; + + case PPP_IP: /* Internet Protocol */ + PPPDEBUG(LOG_INFO, ("pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len)); + if (pppControl[pd].netif.input) { + pppControl[pd].netif.input(nb, &pppControl[pd].netif); + return; + } + break; + + default: { + struct protent *protp; + int i; + + /* + * Upcall the proper protocol input routine. + */ + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { + if (protp->protocol == protocol && protp->enabled_flag) { + PPPDEBUG(LOG_INFO, ("pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len)); + nb = pppSingleBuf(nb); + (*protp->input)(pd, nb->payload, nb->len); + PPPDEBUG(LOG_DETAIL, ("pppInput[%d]: packet processed\n", pd)); + goto out; + } + } + + /* No handler for this protocol so reject the packet. */ + PPPDEBUG(LOG_INFO, ("pppInput[%d]: rejecting unsupported proto 0x%"X16_F" len=%d\n", pd, protocol, nb->len)); + if (pbuf_header(nb, sizeof(protocol))) { + LWIP_ASSERT("pbuf_header failed\n", 0); + goto drop; + } +#if BYTE_ORDER == LITTLE_ENDIAN + protocol = htons(protocol); +#endif /* BYTE_ORDER == LITTLE_ENDIAN */ + SMEMCPY(nb->payload, &protocol, sizeof(protocol)); + lcp_sprotrej(pd, nb->payload, nb->len); + } + break; + } + +drop: + LINK_STATS_INC(link.drop); + snmp_inc_ifindiscards(&pppControl[pd].netif); + +out: + pbuf_free(nb); + return; +} + +#if PPPOS_SUPPORT +/* + * Drop the input packet. + */ +static void +pppDrop(PPPControlRx *pcrx) +{ + if (pcrx->inHead != NULL) { +#if 0 + PPPDEBUG(LOG_INFO, ("pppDrop: %d:%.*H\n", pcrx->inHead->len, min(60, pcrx->inHead->len * 2), pcrx->inHead->payload)); +#endif + PPPDEBUG(LOG_INFO, ("pppDrop: pbuf len=%d, addr %p\n", pcrx->inHead->len, (void*)pcrx->inHead)); + if (pcrx->inTail && (pcrx->inTail != pcrx->inHead)) { + pbuf_free(pcrx->inTail); + } + pbuf_free(pcrx->inHead); + pcrx->inHead = NULL; + pcrx->inTail = NULL; + } +#if VJ_SUPPORT + vj_uncompress_err(&pppControl[pcrx->pd].vjComp); +#endif /* VJ_SUPPORT */ + + LINK_STATS_INC(link.drop); + snmp_inc_ifindiscards(&pppControl[pcrx->pd].netif); +} + +/** Pass received raw characters to PPPoS to be decoded. This function is + * thread-safe and can be called from a dedicated RX-thread or from a main-loop. + * + * @param pd PPP descriptor index, returned by pppOpen() + * @param data received data + * @param len length of received data + */ +void +pppos_input(int pd, u_char* data, int len) +{ + pppInProc(&pppControl[pd].rx, data, len); +} + +/** + * Process a received octet string. + */ +static void +pppInProc(PPPControlRx *pcrx, u_char *s, int l) +{ + struct pbuf *nextNBuf; + u_char curChar; + u_char escaped; + SYS_ARCH_DECL_PROTECT(lev); + + PPPDEBUG(LOG_DEBUG, ("pppInProc[%d]: got %d bytes\n", pcrx->pd, l)); + while (l-- > 0) { + curChar = *s++; + + SYS_ARCH_PROTECT(lev); + escaped = ESCAPE_P(pcrx->inACCM, curChar); + SYS_ARCH_UNPROTECT(lev); + /* Handle special characters. */ + if (escaped) { + /* Check for escape sequences. */ + /* XXX Note that this does not handle an escaped 0x5d character which + * would appear as an escape character. Since this is an ASCII ']' + * and there is no reason that I know of to escape it, I won't complicate + * the code to handle this case. GLL */ + if (curChar == PPP_ESCAPE) { + pcrx->inEscaped = 1; + /* Check for the flag character. */ + } else if (curChar == PPP_FLAG) { + /* If this is just an extra flag character, ignore it. */ + if (pcrx->inState <= PDADDRESS) { + /* ignore it */; + /* If we haven't received the packet header, drop what has come in. */ + } else if (pcrx->inState < PDDATA) { + PPPDEBUG(LOG_WARNING, + ("pppInProc[%d]: Dropping incomplete packet %d\n", + pcrx->pd, pcrx->inState)); + LINK_STATS_INC(link.lenerr); + pppDrop(pcrx); + /* If the fcs is invalid, drop the packet. */ + } else if (pcrx->inFCS != PPP_GOODFCS) { + PPPDEBUG(LOG_INFO, + ("pppInProc[%d]: Dropping bad fcs 0x%"X16_F" proto=0x%"X16_F"\n", + pcrx->pd, pcrx->inFCS, pcrx->inProtocol)); + /* Note: If you get lots of these, check for UART frame errors or try different baud rate */ + LINK_STATS_INC(link.chkerr); + pppDrop(pcrx); + /* Otherwise it's a good packet so pass it on. */ + } else { + struct pbuf *inp; + /* Trim off the checksum. */ + if(pcrx->inTail->len >= 2) { + pcrx->inTail->len -= 2; + + pcrx->inTail->tot_len = pcrx->inTail->len; + if (pcrx->inTail != pcrx->inHead) { + pbuf_cat(pcrx->inHead, pcrx->inTail); + } + } else { + pcrx->inTail->tot_len = pcrx->inTail->len; + if (pcrx->inTail != pcrx->inHead) { + pbuf_cat(pcrx->inHead, pcrx->inTail); + } + + pbuf_realloc(pcrx->inHead, pcrx->inHead->tot_len - 2); + } + + /* Dispatch the packet thereby consuming it. */ + inp = pcrx->inHead; + /* Packet consumed, release our references. */ + pcrx->inHead = NULL; + pcrx->inTail = NULL; +#if PPP_INPROC_MULTITHREADED + if(tcpip_callback_with_block(pppInput, inp, 0) != ERR_OK) { + PPPDEBUG(LOG_ERR, ("pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pcrx->pd)); + pbuf_free(inp); + LINK_STATS_INC(link.drop); + snmp_inc_ifindiscards(&pppControl[pcrx->pd].netif); + } +#else /* PPP_INPROC_MULTITHREADED */ + pppInput(inp); +#endif /* PPP_INPROC_MULTITHREADED */ + } + + /* Prepare for a new packet. */ + pcrx->inFCS = PPP_INITFCS; + pcrx->inState = PDADDRESS; + pcrx->inEscaped = 0; + /* Other characters are usually control characters that may have + * been inserted by the physical layer so here we just drop them. */ + } else { + PPPDEBUG(LOG_WARNING, + ("pppInProc[%d]: Dropping ACCM char <%d>\n", pcrx->pd, curChar)); + } + /* Process other characters. */ + } else { + /* Unencode escaped characters. */ + if (pcrx->inEscaped) { + pcrx->inEscaped = 0; + curChar ^= PPP_TRANS; + } + + /* Process character relative to current state. */ + switch(pcrx->inState) { + case PDIDLE: /* Idle state - waiting. */ + /* Drop the character if it's not 0xff + * we would have processed a flag character above. */ + if (curChar != PPP_ALLSTATIONS) { + break; + } + + /* Fall through */ + case PDSTART: /* Process start flag. */ + /* Prepare for a new packet. */ + pcrx->inFCS = PPP_INITFCS; + + /* Fall through */ + case PDADDRESS: /* Process address field. */ + if (curChar == PPP_ALLSTATIONS) { + pcrx->inState = PDCONTROL; + break; + } + /* Else assume compressed address and control fields so + * fall through to get the protocol... */ + case PDCONTROL: /* Process control field. */ + /* If we don't get a valid control code, restart. */ + if (curChar == PPP_UI) { + pcrx->inState = PDPROTOCOL1; + break; + } +#if 0 + else { + PPPDEBUG(LOG_WARNING, + ("pppInProc[%d]: Invalid control <%d>\n", pcrx->pd, curChar)); + pcrx->inState = PDSTART; + } +#endif + case PDPROTOCOL1: /* Process protocol field 1. */ + /* If the lower bit is set, this is the end of the protocol + * field. */ + if (curChar & 1) { + pcrx->inProtocol = curChar; + pcrx->inState = PDDATA; + } else { + pcrx->inProtocol = (u_int)curChar << 8; + pcrx->inState = PDPROTOCOL2; + } + break; + case PDPROTOCOL2: /* Process protocol field 2. */ + pcrx->inProtocol |= curChar; + pcrx->inState = PDDATA; + break; + case PDDATA: /* Process data byte. */ + /* Make space to receive processed data. */ + if (pcrx->inTail == NULL || pcrx->inTail->len == PBUF_POOL_BUFSIZE) { + if (pcrx->inTail != NULL) { + pcrx->inTail->tot_len = pcrx->inTail->len; + if (pcrx->inTail != pcrx->inHead) { + pbuf_cat(pcrx->inHead, pcrx->inTail); + /* give up the inTail reference now */ + pcrx->inTail = NULL; + } + } + /* If we haven't started a packet, we need a packet header. */ + nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (nextNBuf == NULL) { + /* No free buffers. Drop the input packet and let the + * higher layers deal with it. Continue processing + * the received pbuf chain in case a new packet starts. */ + PPPDEBUG(LOG_ERR, ("pppInProc[%d]: NO FREE MBUFS!\n", pcrx->pd)); + LINK_STATS_INC(link.memerr); + pppDrop(pcrx); + pcrx->inState = PDSTART; /* Wait for flag sequence. */ + break; + } + if (pcrx->inHead == NULL) { + struct pppInputHeader *pih = nextNBuf->payload; + + pih->unit = pcrx->pd; + pih->proto = pcrx->inProtocol; + + nextNBuf->len += sizeof(*pih); + + pcrx->inHead = nextNBuf; + } + pcrx->inTail = nextNBuf; + } + /* Load character into buffer. */ + ((u_char*)pcrx->inTail->payload)[pcrx->inTail->len++] = curChar; + break; + } + + /* update the frame check sequence number. */ + pcrx->inFCS = PPP_FCS(pcrx->inFCS, curChar); + } + } /* while (l-- > 0), all bytes processed */ + + avRandomize(); +} +#endif /* PPPOS_SUPPORT */ + +#if PPPOE_SUPPORT +void +pppInProcOverEthernet(int pd, struct pbuf *pb) +{ + struct pppInputHeader *pih; + u16_t inProtocol; + + if(pb->len < sizeof(inProtocol)) { + PPPDEBUG(LOG_ERR, ("pppInProcOverEthernet: too small for protocol field\n")); + goto drop; + } + + inProtocol = (((u8_t *)pb->payload)[0] << 8) | ((u8_t*)pb->payload)[1]; + + /* make room for pppInputHeader - should not fail */ + if (pbuf_header(pb, sizeof(*pih) - sizeof(inProtocol)) != 0) { + PPPDEBUG(LOG_ERR, ("pppInProcOverEthernet: could not allocate room for header\n")); + goto drop; + } + + pih = pb->payload; + + pih->unit = pd; + pih->proto = inProtocol; + + /* Dispatch the packet thereby consuming it. */ + pppInput(pb); + return; + +drop: + LINK_STATS_INC(link.drop); + snmp_inc_ifindiscards(&pppControl[pd].netif); + pbuf_free(pb); + return; +} +#endif /* PPPOE_SUPPORT */ + +#if LWIP_NETIF_STATUS_CALLBACK +/** Set the status callback of a PPP's netif + * + * @param pd The PPP descriptor returned by pppOpen() + * @param status_callback pointer to the status callback function + * + * @see netif_set_status_callback + */ +void +ppp_set_netif_statuscallback(int pd, netif_status_callback_fn status_callback) +{ + netif_set_status_callback(&pppControl[pd].netif, status_callback); +} +#endif /* LWIP_NETIF_STATUS_CALLBACK */ + +#if LWIP_NETIF_LINK_CALLBACK +/** Set the link callback of a PPP's netif + * + * @param pd The PPP descriptor returned by pppOpen() + * @param link_callback pointer to the link callback function + * + * @see netif_set_link_callback + */ +void +ppp_set_netif_linkcallback(int pd, netif_status_callback_fn link_callback) +{ + netif_set_link_callback(&pppControl[pd].netif, link_callback); +} +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.h new file mode 100644 index 0000000..a72ac95 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.h @@ -0,0 +1,483 @@ +/***************************************************************************** +* ppp.h - Network Point to Point Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ + +#ifndef PPP_H +#define PPP_H + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/sio.h" +#include "lwip/stats.h" +#include "lwip/mem.h" +#include "lwip/netif.h" +#include "lwip/sys.h" +#include "lwip/timers.h" + +/** Some defines for code we skip compared to the original pppd. + * These are just here to minimise the use of the ugly "#if 0". */ +#define PPP_ADDITIONAL_CALLBACKS 0 + +/** Some error checks to test for unsupported code */ +#if CBCP_SUPPORT +#error "CBCP is not supported in lwIP PPP" +#endif +#if CCP_SUPPORT +#error "CCP is not supported in lwIP PPP" +#endif + +/* + * pppd.h - PPP daemon global declarations. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ +/* + * ppp_defs.h - PPP definitions. + * + * Copyright (c) 1994 The Australian National University. + * All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, provided that the above copyright + * notice appears in all copies. This software is provided without any + * warranty, express or implied. The Australian National University + * makes no representations about the suitability of this software for + * any purpose. + * + * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY + * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES + * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, + * OR MODIFICATIONS. + */ + +#define TIMEOUT(f, a, t) do { sys_untimeout((f), (a)); sys_timeout((t)*1000, (f), (a)); } while(0) +#define UNTIMEOUT(f, a) sys_untimeout((f), (a)) + + +#ifndef __u_char_defined + +/* Type definitions for BSD code. */ +typedef unsigned long u_long; +typedef unsigned int u_int; +typedef unsigned short u_short; +typedef unsigned char u_char; + +#endif + +/* + * Constants and structures defined by the internet system, + * Per RFC 790, September 1981, and numerous additions. + */ + +/* + * The basic PPP frame. + */ +#define PPP_HDRLEN 4 /* octets for standard ppp header */ +#define PPP_FCSLEN 2 /* octets for FCS */ + + +/* + * Significant octet values. + */ +#define PPP_ALLSTATIONS 0xff /* All-Stations broadcast address */ +#define PPP_UI 0x03 /* Unnumbered Information */ +#define PPP_FLAG 0x7e /* Flag Sequence */ +#define PPP_ESCAPE 0x7d /* Asynchronous Control Escape */ +#define PPP_TRANS 0x20 /* Asynchronous transparency modifier */ + +/* + * Protocol field values. + */ +#define PPP_IP 0x21 /* Internet Protocol */ +#define PPP_AT 0x29 /* AppleTalk Protocol */ +#define PPP_VJC_COMP 0x2d /* VJ compressed TCP */ +#define PPP_VJC_UNCOMP 0x2f /* VJ uncompressed TCP */ +#define PPP_COMP 0xfd /* compressed packet */ +#define PPP_IPCP 0x8021 /* IP Control Protocol */ +#define PPP_ATCP 0x8029 /* AppleTalk Control Protocol */ +#define PPP_CCP 0x80fd /* Compression Control Protocol */ +#define PPP_LCP 0xc021 /* Link Control Protocol */ +#define PPP_PAP 0xc023 /* Password Authentication Protocol */ +#define PPP_LQR 0xc025 /* Link Quality Report protocol */ +#define PPP_CHAP 0xc223 /* Cryptographic Handshake Auth. Protocol */ +#define PPP_CBCP 0xc029 /* Callback Control Protocol */ + +/* + * Values for FCS calculations. + */ +#define PPP_INITFCS 0xffff /* Initial FCS value */ +#define PPP_GOODFCS 0xf0b8 /* Good final FCS value */ +#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff]) + +/* + * Extended asyncmap - allows any character to be escaped. + */ +typedef u_char ext_accm[32]; + +/* + * What to do with network protocol (NP) packets. + */ +enum NPmode { + NPMODE_PASS, /* pass the packet through */ + NPMODE_DROP, /* silently drop the packet */ + NPMODE_ERROR, /* return an error */ + NPMODE_QUEUE /* save it up for later. */ +}; + +/* + * Inline versions of get/put char/short/long. + * Pointer is advanced; we assume that both arguments + * are lvalues and will already be in registers. + * cp MUST be u_char *. + */ +#define GETCHAR(c, cp) { \ + (c) = *(cp)++; \ +} +#define PUTCHAR(c, cp) { \ + *(cp)++ = (u_char) (c); \ +} + + +#define GETSHORT(s, cp) { \ + (s) = *(cp); (cp)++; (s) <<= 8; \ + (s) |= *(cp); (cp)++; \ +} +#define PUTSHORT(s, cp) { \ + *(cp)++ = (u_char) ((s) >> 8); \ + *(cp)++ = (u_char) (s & 0xff); \ +} + +#define GETLONG(l, cp) { \ + (l) = *(cp); (cp)++; (l) <<= 8; \ + (l) |= *(cp); (cp)++; (l) <<= 8; \ + (l) |= *(cp); (cp)++; (l) <<= 8; \ + (l) |= *(cp); (cp)++; \ +} +#define PUTLONG(l, cp) { \ + *(cp)++ = (u_char) ((l) >> 24); \ + *(cp)++ = (u_char) ((l) >> 16); \ + *(cp)++ = (u_char) ((l) >> 8); \ + *(cp)++ = (u_char) (l); \ +} + + +#define INCPTR(n, cp) ((cp) += (n)) +#define DECPTR(n, cp) ((cp) -= (n)) + +#define BCMP(s0, s1, l) memcmp((u_char *)(s0), (u_char *)(s1), (l)) +#define BCOPY(s, d, l) MEMCPY((d), (s), (l)) +#define BZERO(s, n) memset(s, 0, n) + +#if PPP_DEBUG +#define PRINTMSG(m, l) { m[l] = '\0'; LWIP_DEBUGF(LOG_INFO, ("Remote message: %s\n", m)); } +#else /* PPP_DEBUG */ +#define PRINTMSG(m, l) +#endif /* PPP_DEBUG */ + +/* + * MAKEHEADER - Add PPP Header fields to a packet. + */ +#define MAKEHEADER(p, t) { \ + PUTCHAR(PPP_ALLSTATIONS, p); \ + PUTCHAR(PPP_UI, p); \ + PUTSHORT(t, p); } + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ + +/* Error codes. */ +#define PPPERR_NONE 0 /* No error. */ +#define PPPERR_PARAM -1 /* Invalid parameter. */ +#define PPPERR_OPEN -2 /* Unable to open PPP session. */ +#define PPPERR_DEVICE -3 /* Invalid I/O device for PPP. */ +#define PPPERR_ALLOC -4 /* Unable to allocate resources. */ +#define PPPERR_USER -5 /* User interrupt. */ +#define PPPERR_CONNECT -6 /* Connection lost. */ +#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */ +#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */ + +/* + * PPP IOCTL commands. + */ +/* + * Get the up status - 0 for down, non-zero for up. The argument must + * point to an int. + */ +#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */ +#define PPPCTLS_ERRCODE 101 /* Set the error code */ +#define PPPCTLG_ERRCODE 102 /* Get the error code */ +#define PPPCTLG_FD 103 /* Get the fd associated with the ppp */ + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * The following struct gives the addresses of procedures to call + * for a particular protocol. + */ +struct protent { + u_short protocol; /* PPP protocol number */ + /* Initialization procedure */ + void (*init) (int unit); + /* Process a received packet */ + void (*input) (int unit, u_char *pkt, int len); + /* Process a received protocol-reject */ + void (*protrej) (int unit); + /* Lower layer has come up */ + void (*lowerup) (int unit); + /* Lower layer has gone down */ + void (*lowerdown) (int unit); + /* Open the protocol */ + void (*open) (int unit); + /* Close the protocol */ + void (*close) (int unit, char *reason); +#if PPP_ADDITIONAL_CALLBACKS + /* Print a packet in readable form */ + int (*printpkt) (u_char *pkt, int len, + void (*printer) (void *, char *, ...), + void *arg); + /* Process a received data packet */ + void (*datainput) (int unit, u_char *pkt, int len); +#endif /* PPP_ADDITIONAL_CALLBACKS */ + int enabled_flag; /* 0 if protocol is disabled */ + char *name; /* Text name of protocol */ +#if PPP_ADDITIONAL_CALLBACKS + /* Check requested options, assign defaults */ + void (*check_options) (u_long); + /* Configure interface for demand-dial */ + int (*demand_conf) (int unit); + /* Say whether to bring up link for this pkt */ + int (*active_pkt) (u_char *pkt, int len); +#endif /* PPP_ADDITIONAL_CALLBACKS */ +}; + +/* + * The following structure records the time in seconds since + * the last NP packet was sent or received. + */ +struct ppp_idle { + u_short xmit_idle; /* seconds since last NP packet sent */ + u_short recv_idle; /* seconds since last NP packet received */ +}; + +struct ppp_settings { + + u_int disable_defaultip : 1; /* Don't use hostname for default IP addrs */ + u_int auth_required : 1; /* Peer is required to authenticate */ + u_int explicit_remote : 1; /* remote_name specified with remotename opt */ + u_int refuse_pap : 1; /* Don't wanna auth. ourselves with PAP */ + u_int refuse_chap : 1; /* Don't wanna auth. ourselves with CHAP */ + u_int usehostname : 1; /* Use hostname for our_name */ + u_int usepeerdns : 1; /* Ask peer for DNS adds */ + + u_short idle_time_limit; /* Shut down link if idle for this long */ + int maxconnect; /* Maximum connect time (seconds) */ + + char user [MAXNAMELEN + 1]; /* Username for PAP */ + char passwd [MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */ + char our_name [MAXNAMELEN + 1]; /* Our name for authentication purposes */ + char remote_name[MAXNAMELEN + 1]; /* Peer's name for authentication */ +}; + +struct ppp_addrs { + ip_addr_t our_ipaddr, his_ipaddr, netmask, dns1, dns2; +}; + +/***************************** +*** PUBLIC DATA STRUCTURES *** +*****************************/ + +/* Buffers for outgoing packets. */ +extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; + +extern struct ppp_settings ppp_settings; + +extern struct protent *ppp_protocols[]; /* Table of pointers to supported protocols */ + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +/* Initialize the PPP subsystem. */ +void pppInit(void); + +/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. + * RFC 1994 says: + * + * In practice, within or associated with each PPP server, there is a + * database which associates "user" names with authentication + * information ("secrets"). It is not anticipated that a particular + * named user would be authenticated by multiple methods. This would + * make the user vulnerable to attacks which negotiate the least secure + * method from among a set (such as PAP rather than CHAP). If the same + * secret was used, PAP would reveal the secret to be used later with + * CHAP. + * + * Instead, for each user name there should be an indication of exactly + * one method used to authenticate that user name. If a user needs to + * make use of different authentication methods under different + * circumstances, then distinct user names SHOULD be employed, each of + * which identifies exactly one authentication method. + * + */ +enum pppAuthType { + PPPAUTHTYPE_NONE, + PPPAUTHTYPE_ANY, + PPPAUTHTYPE_PAP, + PPPAUTHTYPE_CHAP +}; + +void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd); + +/* + * Open a new PPP connection using the given serial I/O device. + * This initializes the PPP control block but does not + * attempt to negotiate the LCP session. + * Return a new PPP connection descriptor on success or + * an error code (negative) on failure. + */ +int pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx); + +/* + * Open a new PPP Over Ethernet (PPPOE) connection. + */ +int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx); + +/* for source code compatibility */ +#define pppOpen(fd,cb,ls) pppOverSerialOpen(fd,cb,ls) + +/* + * Close a PPP connection and release the descriptor. + * Any outstanding packets in the queues are dropped. + * Return 0 on success, an error code on failure. + */ +int pppClose(int pd); + +/* + * Indicate to the PPP process that the line has disconnected. + */ +void pppSigHUP(int pd); + +/* + * Get and set parameters for the given connection. + * Return 0 on success, an error code on failure. + */ +int pppIOCtl(int pd, int cmd, void *arg); + +/* + * Return the Maximum Transmission Unit for the given PPP connection. + */ +u_short pppMTU(int pd); + +/* + * Write n characters to a ppp link. + * RETURN: >= 0 Number of characters written, -1 Failed to write to device. + */ +int pppWrite(int pd, const u_char *s, int n); + +void pppInProcOverEthernet(int pd, struct pbuf *pb); + +struct pbuf *pppSingleBuf(struct pbuf *p); + +void pppLinkTerminated(int pd); + +void pppLinkDown(int pd); + +void pppos_input(int pd, u_char* data, int len); + +/* Configure i/f transmit parameters */ +void ppp_send_config (int, u16_t, u32_t, int, int); +/* Set extended transmit ACCM */ +void ppp_set_xaccm (int, ext_accm *); +/* Configure i/f receive parameters */ +void ppp_recv_config (int, int, u32_t, int, int); +/* Find out how long link has been idle */ +int get_idle_time (int, struct ppp_idle *); + +/* Configure VJ TCP header compression */ +int sifvjcomp (int, int, u8_t, u8_t); +/* Configure i/f down (for IP) */ +int sifup (int); +/* Set mode for handling packets for proto */ +int sifnpmode (int u, int proto, enum NPmode mode); +/* Configure i/f down (for IP) */ +int sifdown (int); +/* Configure IP addresses for i/f */ +int sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t); +/* Reset i/f IP addresses */ +int cifaddr (int, u32_t, u32_t); +/* Create default route through i/f */ +int sifdefaultroute (int, u32_t, u32_t); +/* Delete default route through i/f */ +int cifdefaultroute (int, u32_t, u32_t); + +/* Get appropriate netmask for address */ +u32_t GetMask (u32_t); + +#if LWIP_NETIF_STATUS_CALLBACK +void ppp_set_netif_statuscallback(int pd, netif_status_callback_fn status_callback); +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK +void ppp_set_netif_linkcallback(int pd, netif_status_callback_fn link_callback); +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#endif /* PPP_SUPPORT */ + +#endif /* PPP_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp_oe.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp_oe.c new file mode 100644 index 0000000..040a0bc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp_oe.c @@ -0,0 +1,1132 @@ +/***************************************************************************** +* ppp_oe.c - PPP Over Ethernet implementation for lwIP. +* +* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 06-01-01 Marc Boucher +* Ported to lwIP. +*****************************************************************************/ + + + +/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Martin Husemann . + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "lwip/opt.h" + +#if PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "netif/ppp_oe.h" + +#include "ppp.h" +#include "pppdebug.h" + +#include "lwip/timers.h" +#include "lwip/memp.h" + +#include +#include + + +/* Add a 16 bit unsigned value to a buffer pointed to by PTR */ +#define PPPOE_ADD_16(PTR, VAL) \ + *(PTR)++ = (u8_t)((VAL) / 256); \ + *(PTR)++ = (u8_t)((VAL) % 256) + +/* Add a complete PPPoE header to the buffer pointed to by PTR */ +#define PPPOE_ADD_HEADER(PTR, CODE, SESS, LEN) \ + *(PTR)++ = PPPOE_VERTYPE; \ + *(PTR)++ = (CODE); \ + PPPOE_ADD_16(PTR, SESS); \ + PPPOE_ADD_16(PTR, LEN) + +#define PPPOE_DISC_TIMEOUT (5*1000) /* base for quick timeout calculation */ +#define PPPOE_SLOW_RETRY (60*1000) /* persistent retry interval */ +#define PPPOE_DISC_MAXPADI 4 /* retry PADI four times (quickly) */ +#define PPPOE_DISC_MAXPADR 2 /* retry PADR twice */ + +#ifdef PPPOE_SERVER +#error "PPPOE_SERVER is not yet supported under lwIP!" +/* from if_spppsubr.c */ +#define IFF_PASSIVE IFF_LINK0 /* wait passively for connection */ +#endif + +#ifndef PPPOE_ERRORSTRING_LEN +#define PPPOE_ERRORSTRING_LEN 64 +#endif +static char pppoe_error_tmp[PPPOE_ERRORSTRING_LEN]; + + +/* input routines */ +static void pppoe_dispatch_disc_pkt(struct netif *, struct pbuf *); + +/* management routines */ +static int pppoe_do_disconnect(struct pppoe_softc *); +static void pppoe_abort_connect(struct pppoe_softc *); +static void pppoe_clear_softc(struct pppoe_softc *, const char *); + +/* internal timeout handling */ +static void pppoe_timeout(void *); + +/* sending actual protocol controll packets */ +static err_t pppoe_send_padi(struct pppoe_softc *); +static err_t pppoe_send_padr(struct pppoe_softc *); +#ifdef PPPOE_SERVER +static err_t pppoe_send_pado(struct pppoe_softc *); +static err_t pppoe_send_pads(struct pppoe_softc *); +#endif +static err_t pppoe_send_padt(struct netif *, u_int, const u8_t *); + +/* internal helper functions */ +static struct pppoe_softc * pppoe_find_softc_by_session(u_int, struct netif *); +static struct pppoe_softc * pppoe_find_softc_by_hunique(u8_t *, size_t, struct netif *); + +/** linked list of created pppoe interfaces */ +static struct pppoe_softc *pppoe_softc_list; + +err_t +pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr) +{ + struct pppoe_softc *sc; + + sc = (struct pppoe_softc *)memp_malloc(MEMP_PPPOE_IF); + if (sc == NULL) { + *scptr = NULL; + return ERR_MEM; + } + memset(sc, 0, sizeof(struct pppoe_softc)); + + /* changed to real address later */ + MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest)); + + sc->sc_pd = pd; + sc->sc_linkStatusCB = linkStatusCB; + sc->sc_ethif = ethif; + + /* put the new interface at the head of the list */ + sc->next = pppoe_softc_list; + pppoe_softc_list = sc; + + *scptr = sc; + + return ERR_OK; +} + +err_t +pppoe_destroy(struct netif *ifp) +{ + struct pppoe_softc *sc, *prev = NULL; + + for (sc = pppoe_softc_list; sc != NULL; prev = sc, sc = sc->next) { + if (sc->sc_ethif == ifp) { + break; + } + } + + if(!(sc && (sc->sc_ethif == ifp))) { + return ERR_IF; + } + + sys_untimeout(pppoe_timeout, sc); + if (prev == NULL) { + /* remove sc from the head of the list */ + pppoe_softc_list = sc->next; + } else { + /* remove sc from the list */ + prev->next = sc->next; + } + +#ifdef PPPOE_TODO + if (sc->sc_concentrator_name) { + mem_free(sc->sc_concentrator_name); + } + if (sc->sc_service_name) { + mem_free(sc->sc_service_name); + } +#endif /* PPPOE_TODO */ + memp_free(MEMP_PPPOE_IF, sc); + + return ERR_OK; +} + +/* + * Find the interface handling the specified session. + * Note: O(number of sessions open), this is a client-side only, mean + * and lean implementation, so number of open sessions typically should + * be 1. + */ +static struct pppoe_softc * +pppoe_find_softc_by_session(u_int session, struct netif *rcvif) +{ + struct pppoe_softc *sc; + + if (session == 0) { + return NULL; + } + + for (sc = pppoe_softc_list; sc != NULL; sc = sc->next) { + if (sc->sc_state == PPPOE_STATE_SESSION + && sc->sc_session == session) { + if (sc->sc_ethif == rcvif) { + return sc; + } else { + return NULL; + } + } + } + return NULL; +} + +/* Check host unique token passed and return appropriate softc pointer, + * or NULL if token is bogus. */ +static struct pppoe_softc * +pppoe_find_softc_by_hunique(u8_t *token, size_t len, struct netif *rcvif) +{ + struct pppoe_softc *sc, *t; + + if (pppoe_softc_list == NULL) { + return NULL; + } + + if (len != sizeof sc) { + return NULL; + } + MEMCPY(&t, token, len); + + for (sc = pppoe_softc_list; sc != NULL; sc = sc->next) { + if (sc == t) { + break; + } + } + + if (sc == NULL) { + PPPDEBUG(LOG_DEBUG, ("pppoe: alien host unique tag, no session found\n")); + return NULL; + } + + /* should be safe to access *sc now */ + if (sc->sc_state < PPPOE_STATE_PADI_SENT || sc->sc_state >= PPPOE_STATE_SESSION) { + printf("%c%c%"U16_F": host unique tag found, but it belongs to a connection in state %d\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_state); + return NULL; + } + if (sc->sc_ethif != rcvif) { + printf("%c%c%"U16_F": wrong interface, not accepting host unique\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num); + return NULL; + } + return sc; +} + +static void +pppoe_linkstatus_up(struct pppoe_softc *sc) +{ + sc->sc_linkStatusCB(sc->sc_pd, 1); +} + +/* analyze and handle a single received packet while not in session state */ +static void +pppoe_dispatch_disc_pkt(struct netif *netif, struct pbuf *pb) +{ + u16_t tag, len; + u16_t session, plen; + struct pppoe_softc *sc; + const char *err_msg; + char devname[6]; + u8_t *ac_cookie; + u16_t ac_cookie_len; +#ifdef PPPOE_SERVER + u8_t *hunique; + size_t hunique_len; +#endif + struct pppoehdr *ph; + struct pppoetag pt; + int off, err, errortag; + struct eth_hdr *ethhdr; + + pb = pppSingleBuf(pb); + + strcpy(devname, "pppoe"); /* as long as we don't know which instance */ + err_msg = NULL; + errortag = 0; + if (pb->len < sizeof(*ethhdr)) { + goto done; + } + ethhdr = (struct eth_hdr *)pb->payload; + off = sizeof(*ethhdr); + + ac_cookie = NULL; + ac_cookie_len = 0; +#ifdef PPPOE_SERVER + hunique = NULL; + hunique_len = 0; +#endif + session = 0; + if (pb->len - off < PPPOE_HEADERLEN) { + printf("pppoe: packet too short: %d\n", pb->len); + goto done; + } + + ph = (struct pppoehdr *) (ethhdr + 1); + if (ph->vertype != PPPOE_VERTYPE) { + printf("pppoe: unknown version/type packet: 0x%x\n", ph->vertype); + goto done; + } + session = ntohs(ph->session); + plen = ntohs(ph->plen); + off += sizeof(*ph); + + if (plen + off > pb->len) { + printf("pppoe: packet content does not fit: data available = %d, packet size = %u\n", + pb->len - off, plen); + goto done; + } + if(pb->tot_len == pb->len) { + pb->tot_len = pb->len = (u16_t)off + plen; /* ignore trailing garbage */ + } + tag = 0; + len = 0; + sc = NULL; + while (off + sizeof(pt) <= pb->len) { + MEMCPY(&pt, (u8_t*)pb->payload + off, sizeof(pt)); + tag = ntohs(pt.tag); + len = ntohs(pt.len); + if (off + sizeof(pt) + len > pb->len) { + printf("pppoe: tag 0x%x len 0x%x is too long\n", tag, len); + goto done; + } + switch (tag) { + case PPPOE_TAG_EOL: + goto breakbreak; + case PPPOE_TAG_SNAME: + break; /* ignored */ + case PPPOE_TAG_ACNAME: + break; /* ignored */ + case PPPOE_TAG_HUNIQUE: + if (sc != NULL) { + break; + } +#ifdef PPPOE_SERVER + hunique = (u8_t*)pb->payload + off + sizeof(pt); + hunique_len = len; +#endif + sc = pppoe_find_softc_by_hunique((u8_t*)pb->payload + off + sizeof(pt), len, netif); + if (sc != NULL) { + snprintf(devname, sizeof(devname), "%c%c%"U16_F, sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num); + } + break; + case PPPOE_TAG_ACCOOKIE: + if (ac_cookie == NULL) { + ac_cookie = (u8_t*)pb->payload + off + sizeof(pt); + ac_cookie_len = len; + } + break; + case PPPOE_TAG_SNAME_ERR: + err_msg = "SERVICE NAME ERROR"; + errortag = 1; + break; + case PPPOE_TAG_ACSYS_ERR: + err_msg = "AC SYSTEM ERROR"; + errortag = 1; + break; + case PPPOE_TAG_GENERIC_ERR: + err_msg = "GENERIC ERROR"; + errortag = 1; + break; + } + if (err_msg) { + if (errortag && len) { + u16_t error_len = LWIP_MIN(len, sizeof(pppoe_error_tmp)-1); + strncpy(pppoe_error_tmp, (char*)pb->payload + off + sizeof(pt), error_len); + pppoe_error_tmp[error_len-1] = '\0'; + printf("%s: %s: %s\n", devname, err_msg, pppoe_error_tmp); + } else { + printf("%s: %s\n", devname, err_msg); + } + if (errortag) { + goto done; + } + } + off += sizeof(pt) + len; + } + +breakbreak:; + switch (ph->code) { + case PPPOE_CODE_PADI: +#ifdef PPPOE_SERVER + /* + * got service name, concentrator name, and/or host unique. + * ignore if we have no interfaces with IFF_PASSIVE|IFF_UP. + */ + if (LIST_EMPTY(&pppoe_softc_list)) { + goto done; + } + LIST_FOREACH(sc, &pppoe_softc_list, sc_list) { + if (!(sc->sc_sppp.pp_if.if_flags & IFF_UP)) { + continue; + } + if (!(sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) { + continue; + } + if (sc->sc_state == PPPOE_STATE_INITIAL) { + break; + } + } + if (sc == NULL) { + /* printf("pppoe: free passive interface is not found\n"); */ + goto done; + } + if (hunique) { + if (sc->sc_hunique) { + mem_free(sc->sc_hunique); + } + sc->sc_hunique = mem_malloc(hunique_len); + if (sc->sc_hunique == NULL) { + goto done; + } + sc->sc_hunique_len = hunique_len; + MEMCPY(sc->sc_hunique, hunique, hunique_len); + } + MEMCPY(&sc->sc_dest, eh->ether_shost, sizeof sc->sc_dest); + sc->sc_state = PPPOE_STATE_PADO_SENT; + pppoe_send_pado(sc); + break; +#endif /* PPPOE_SERVER */ + case PPPOE_CODE_PADR: +#ifdef PPPOE_SERVER + /* + * get sc from ac_cookie if IFF_PASSIVE + */ + if (ac_cookie == NULL) { + /* be quiet if there is not a single pppoe instance */ + printf("pppoe: received PADR but not includes ac_cookie\n"); + goto done; + } + sc = pppoe_find_softc_by_hunique(ac_cookie, ac_cookie_len, netif); + if (sc == NULL) { + /* be quiet if there is not a single pppoe instance */ + if (!LIST_EMPTY(&pppoe_softc_list)) { + printf("pppoe: received PADR but could not find request for it\n"); + } + goto done; + } + if (sc->sc_state != PPPOE_STATE_PADO_SENT) { + printf("%c%c%"U16_F": received unexpected PADR\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num); + goto done; + } + if (hunique) { + if (sc->sc_hunique) { + mem_free(sc->sc_hunique); + } + sc->sc_hunique = mem_malloc(hunique_len); + if (sc->sc_hunique == NULL) { + goto done; + } + sc->sc_hunique_len = hunique_len; + MEMCPY(sc->sc_hunique, hunique, hunique_len); + } + pppoe_send_pads(sc); + sc->sc_state = PPPOE_STATE_SESSION; + pppoe_linkstatus_up(sc); /* notify upper layers */ + break; +#else + /* ignore, we are no access concentrator */ + goto done; +#endif /* PPPOE_SERVER */ + case PPPOE_CODE_PADO: + if (sc == NULL) { + /* be quiet if there is not a single pppoe instance */ + if (pppoe_softc_list != NULL) { + printf("pppoe: received PADO but could not find request for it\n"); + } + goto done; + } + if (sc->sc_state != PPPOE_STATE_PADI_SENT) { + printf("%c%c%"U16_F": received unexpected PADO\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num); + goto done; + } + if (ac_cookie) { + sc->sc_ac_cookie_len = ac_cookie_len; + MEMCPY(sc->sc_ac_cookie, ac_cookie, ac_cookie_len); + } + MEMCPY(&sc->sc_dest, ethhdr->src.addr, sizeof(sc->sc_dest.addr)); + sys_untimeout(pppoe_timeout, sc); + sc->sc_padr_retried = 0; + sc->sc_state = PPPOE_STATE_PADR_SENT; + if ((err = pppoe_send_padr(sc)) != 0) { + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + } + sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc); + break; + case PPPOE_CODE_PADS: + if (sc == NULL) { + goto done; + } + sc->sc_session = session; + sys_untimeout(pppoe_timeout, sc); + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": session 0x%x connected\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, session)); + sc->sc_state = PPPOE_STATE_SESSION; + pppoe_linkstatus_up(sc); /* notify upper layers */ + break; + case PPPOE_CODE_PADT: + if (sc == NULL) { + goto done; + } + pppoe_clear_softc(sc, "received PADT"); + break; + default: + if(sc) { + printf("%c%c%"U16_F": unknown code (0x%"X16_F") session = 0x%"X16_F"\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, + (u16_t)ph->code, session); + } else { + printf("pppoe: unknown code (0x%"X16_F") session = 0x%"X16_F"\n", (u16_t)ph->code, session); + } + break; + } + +done: + pbuf_free(pb); + return; +} + +void +pppoe_disc_input(struct netif *netif, struct pbuf *p) +{ + /* avoid error messages if there is not a single pppoe instance */ + if (pppoe_softc_list != NULL) { + pppoe_dispatch_disc_pkt(netif, p); + } else { + pbuf_free(p); + } +} + +void +pppoe_data_input(struct netif *netif, struct pbuf *pb) +{ + u16_t session, plen; + struct pppoe_softc *sc; + struct pppoehdr *ph; +#ifdef PPPOE_TERM_UNKNOWN_SESSIONS + u8_t shost[ETHER_ADDR_LEN]; +#endif + +#ifdef PPPOE_TERM_UNKNOWN_SESSIONS + MEMCPY(shost, ((struct eth_hdr *)pb->payload)->src.addr, sizeof(shost)); +#endif + if (pbuf_header(pb, -(int)sizeof(struct eth_hdr)) != 0) { + /* bail out */ + PPPDEBUG(LOG_ERR, ("pppoe_data_input: pbuf_header failed\n")); + LINK_STATS_INC(link.lenerr); + goto drop; + } + + pb = pppSingleBuf (pb); + + if (pb->len <= PPPOE_HEADERLEN) { + printf("pppoe (data): dropping too short packet: %d bytes\n", pb->len); + goto drop; + } + + if (pb->len < sizeof(*ph)) { + printf("pppoe_data_input: could not get PPPoE header\n"); + goto drop; + } + ph = (struct pppoehdr *)pb->payload; + + if (ph->vertype != PPPOE_VERTYPE) { + printf("pppoe (data): unknown version/type packet: 0x%x\n", ph->vertype); + goto drop; + } + if (ph->code != 0) { + goto drop; + } + + session = ntohs(ph->session); + sc = pppoe_find_softc_by_session(session, netif); + if (sc == NULL) { +#ifdef PPPOE_TERM_UNKNOWN_SESSIONS + printf("pppoe: input for unknown session 0x%x, sending PADT\n", session); + pppoe_send_padt(netif, session, shost); +#endif + goto drop; + } + + plen = ntohs(ph->plen); + + if (pbuf_header(pb, -(int)(PPPOE_HEADERLEN)) != 0) { + /* bail out */ + PPPDEBUG(LOG_ERR, ("pppoe_data_input: pbuf_header PPPOE_HEADERLEN failed\n")); + LINK_STATS_INC(link.lenerr); + goto drop; + } + + PPPDEBUG(LOG_DEBUG, ("pppoe_data_input: %c%c%"U16_F": pkthdr.len=%d, pppoe.len=%d\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, + pb->len, plen)); + + if (pb->len < plen) { + goto drop; + } + + pppInProcOverEthernet(sc->sc_pd, pb); + + return; + +drop: + pbuf_free(pb); +} + +static err_t +pppoe_output(struct pppoe_softc *sc, struct pbuf *pb) +{ + struct eth_hdr *ethhdr; + u16_t etype; + err_t res; + + if (!sc->sc_ethif) { + pbuf_free(pb); + return ERR_IF; + } + + ethhdr = (struct eth_hdr *)pb->payload; + etype = sc->sc_state == PPPOE_STATE_SESSION ? ETHTYPE_PPPOE : ETHTYPE_PPPOEDISC; + ethhdr->type = htons(etype); + MEMCPY(ethhdr->dest.addr, sc->sc_dest.addr, sizeof(ethhdr->dest.addr)); + MEMCPY(ethhdr->src.addr, ((struct eth_addr *)sc->sc_ethif->hwaddr)->addr, sizeof(ethhdr->src.addr)); + + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F" (%x) state=%d, session=0x%x output -> %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F", len=%d\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, etype, + sc->sc_state, sc->sc_session, + sc->sc_dest.addr[0], sc->sc_dest.addr[1], sc->sc_dest.addr[2], sc->sc_dest.addr[3], sc->sc_dest.addr[4], sc->sc_dest.addr[5], + pb->tot_len)); + + res = sc->sc_ethif->linkoutput(sc->sc_ethif, pb); + + pbuf_free(pb); + + return res; +} + +static err_t +pppoe_send_padi(struct pppoe_softc *sc) +{ + struct pbuf *pb; + u8_t *p; + int len; +#ifdef PPPOE_TODO + int l1 = 0, l2 = 0; /* XXX: gcc */ +#endif /* PPPOE_TODO */ + + if (sc->sc_state >PPPOE_STATE_PADI_SENT) { + PPPDEBUG(LOG_ERR, ("ERROR: pppoe_send_padi in state %d", sc->sc_state)); + } + + /* calculate length of frame (excluding ethernet header + pppoe header) */ + len = 2 + 2 + 2 + 2 + sizeof sc; /* service name tag is required, host unique is send too */ +#ifdef PPPOE_TODO + if (sc->sc_service_name != NULL) { + l1 = (int)strlen(sc->sc_service_name); + len += l1; + } + if (sc->sc_concentrator_name != NULL) { + l2 = (int)strlen(sc->sc_concentrator_name); + len += 2 + 2 + l2; + } +#endif /* PPPOE_TODO */ + LWIP_ASSERT("sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff", + sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff); + + /* allocate a buffer */ + pb = pbuf_alloc(PBUF_LINK, (u16_t)(sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len), PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + p = (u8_t*)pb->payload + sizeof (struct eth_hdr); + /* fill in pkt */ + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADI, 0, (u16_t)len); + PPPOE_ADD_16(p, PPPOE_TAG_SNAME); +#ifdef PPPOE_TODO + if (sc->sc_service_name != NULL) { + PPPOE_ADD_16(p, l1); + MEMCPY(p, sc->sc_service_name, l1); + p += l1; + } else +#endif /* PPPOE_TODO */ + { + PPPOE_ADD_16(p, 0); + } +#ifdef PPPOE_TODO + if (sc->sc_concentrator_name != NULL) { + PPPOE_ADD_16(p, PPPOE_TAG_ACNAME); + PPPOE_ADD_16(p, l2); + MEMCPY(p, sc->sc_concentrator_name, l2); + p += l2; + } +#endif /* PPPOE_TODO */ + PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE); + PPPOE_ADD_16(p, sizeof(sc)); + MEMCPY(p, &sc, sizeof sc); + + /* send pkt */ + return pppoe_output(sc, pb); +} + +static void +pppoe_timeout(void *arg) +{ + int retry_wait, err; + struct pppoe_softc *sc = (struct pppoe_softc*)arg; + + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": timeout\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + + switch (sc->sc_state) { + case PPPOE_STATE_PADI_SENT: + /* + * We have two basic ways of retrying: + * - Quick retry mode: try a few times in short sequence + * - Slow retry mode: we already had a connection successfully + * established and will try infinitely (without user + * intervention) + * We only enter slow retry mode if IFF_LINK1 (aka autodial) + * is not set. + */ + + /* initialize for quick retry mode */ + retry_wait = PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried); + + sc->sc_padi_retried++; + if (sc->sc_padi_retried >= PPPOE_DISC_MAXPADI) { +#if 0 + if ((sc->sc_sppp.pp_if.if_flags & IFF_LINK1) == 0) { + /* slow retry mode */ + retry_wait = PPPOE_SLOW_RETRY; + } else +#endif + { + pppoe_abort_connect(sc); + return; + } + } + if ((err = pppoe_send_padi(sc)) != 0) { + sc->sc_padi_retried--; + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to transmit PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + } + sys_timeout(retry_wait, pppoe_timeout, sc); + break; + + case PPPOE_STATE_PADR_SENT: + sc->sc_padr_retried++; + if (sc->sc_padr_retried >= PPPOE_DISC_MAXPADR) { + MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest)); + sc->sc_state = PPPOE_STATE_PADI_SENT; + sc->sc_padr_retried = 0; + if ((err = pppoe_send_padi(sc)) != 0) { + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + } + sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried), pppoe_timeout, sc); + return; + } + if ((err = pppoe_send_padr(sc)) != 0) { + sc->sc_padr_retried--; + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + } + sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc); + break; + case PPPOE_STATE_CLOSING: + pppoe_do_disconnect(sc); + break; + default: + return; /* all done, work in peace */ + } +} + +/* Start a connection (i.e. initiate discovery phase) */ +int +pppoe_connect(struct pppoe_softc *sc) +{ + int err; + + if (sc->sc_state != PPPOE_STATE_INITIAL) { + return EBUSY; + } + +#ifdef PPPOE_SERVER + /* wait PADI if IFF_PASSIVE */ + if ((sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) { + return 0; + } +#endif + /* save state, in case we fail to send PADI */ + sc->sc_state = PPPOE_STATE_PADI_SENT; + sc->sc_padr_retried = 0; + err = pppoe_send_padi(sc); + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + sys_timeout(PPPOE_DISC_TIMEOUT, pppoe_timeout, sc); + return err; +} + +/* disconnect */ +void +pppoe_disconnect(struct pppoe_softc *sc) +{ + if (sc->sc_state < PPPOE_STATE_SESSION) { + return; + } + /* + * Do not call pppoe_disconnect here, the upper layer state + * machine gets confused by this. We must return from this + * function and defer disconnecting to the timeout handler. + */ + sc->sc_state = PPPOE_STATE_CLOSING; + sys_timeout(20, pppoe_timeout, sc); +} + +static int +pppoe_do_disconnect(struct pppoe_softc *sc) +{ + int err; + + if (sc->sc_state < PPPOE_STATE_SESSION) { + err = EBUSY; + } else { + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": disconnecting\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + err = pppoe_send_padt(sc->sc_ethif, sc->sc_session, (const u8_t *)&sc->sc_dest); + } + + /* cleanup softc */ + sc->sc_state = PPPOE_STATE_INITIAL; + MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest)); + sc->sc_ac_cookie_len = 0; +#ifdef PPPOE_SERVER + if (sc->sc_hunique) { + mem_free(sc->sc_hunique); + sc->sc_hunique = NULL; + } + sc->sc_hunique_len = 0; +#endif + sc->sc_session = 0; + + sc->sc_linkStatusCB(sc->sc_pd, 0); /* notify upper layers */ + + return err; +} + +/* Connection attempt aborted */ +static void +pppoe_abort_connect(struct pppoe_softc *sc) +{ + printf("%c%c%"U16_F": could not establish connection\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num); + sc->sc_state = PPPOE_STATE_CLOSING; + + sc->sc_linkStatusCB(sc->sc_pd, 0); /* notify upper layers */ + + /* clear connection state */ + MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest)); + sc->sc_state = PPPOE_STATE_INITIAL; +} + +/* Send a PADR packet */ +static err_t +pppoe_send_padr(struct pppoe_softc *sc) +{ + struct pbuf *pb; + u8_t *p; + size_t len; +#ifdef PPPOE_TODO + size_t l1 = 0; /* XXX: gcc */ +#endif /* PPPOE_TODO */ + + if (sc->sc_state != PPPOE_STATE_PADR_SENT) { + return ERR_CONN; + } + + len = 2 + 2 + 2 + 2 + sizeof(sc); /* service name, host unique */ +#ifdef PPPOE_TODO + if (sc->sc_service_name != NULL) { /* service name tag maybe empty */ + l1 = strlen(sc->sc_service_name); + len += l1; + } +#endif /* PPPOE_TODO */ + if (sc->sc_ac_cookie_len > 0) { + len += 2 + 2 + sc->sc_ac_cookie_len; /* AC cookie */ + } + LWIP_ASSERT("sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff", + sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff); + pb = pbuf_alloc(PBUF_LINK, (u16_t)(sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len), PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + p = (u8_t*)pb->payload + sizeof (struct eth_hdr); + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADR, 0, len); + PPPOE_ADD_16(p, PPPOE_TAG_SNAME); +#ifdef PPPOE_TODO + if (sc->sc_service_name != NULL) { + PPPOE_ADD_16(p, l1); + MEMCPY(p, sc->sc_service_name, l1); + p += l1; + } else +#endif /* PPPOE_TODO */ + { + PPPOE_ADD_16(p, 0); + } + if (sc->sc_ac_cookie_len > 0) { + PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE); + PPPOE_ADD_16(p, sc->sc_ac_cookie_len); + MEMCPY(p, sc->sc_ac_cookie, sc->sc_ac_cookie_len); + p += sc->sc_ac_cookie_len; + } + PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE); + PPPOE_ADD_16(p, sizeof(sc)); + MEMCPY(p, &sc, sizeof sc); + + return pppoe_output(sc, pb); +} + +/* send a PADT packet */ +static err_t +pppoe_send_padt(struct netif *outgoing_if, u_int session, const u8_t *dest) +{ + struct pbuf *pb; + struct eth_hdr *ethhdr; + err_t res; + u8_t *p; + + pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN, PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + ethhdr = (struct eth_hdr *)pb->payload; + ethhdr->type = PP_HTONS(ETHTYPE_PPPOEDISC); + MEMCPY(ethhdr->dest.addr, dest, sizeof(ethhdr->dest.addr)); + MEMCPY(ethhdr->src.addr, ((struct eth_addr *)outgoing_if->hwaddr)->addr, sizeof(ethhdr->src.addr)); + + p = (u8_t*)(ethhdr + 1); + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADT, session, 0); + + res = outgoing_if->linkoutput(outgoing_if, pb); + + pbuf_free(pb); + + return res; +} + +#ifdef PPPOE_SERVER +static err_t +pppoe_send_pado(struct pppoe_softc *sc) +{ + struct pbuf *pb; + u8_t *p; + size_t len; + + if (sc->sc_state != PPPOE_STATE_PADO_SENT) { + return ERR_CONN; + } + + /* calc length */ + len = 0; + /* include ac_cookie */ + len += 2 + 2 + sizeof(sc); + /* include hunique */ + len += 2 + 2 + sc->sc_hunique_len; + pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + p = (u8_t*)pb->payload + sizeof (struct eth_hdr); + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADO, 0, len); + PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE); + PPPOE_ADD_16(p, sizeof(sc)); + MEMCPY(p, &sc, sizeof(sc)); + p += sizeof(sc); + PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE); + PPPOE_ADD_16(p, sc->sc_hunique_len); + MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len); + return pppoe_output(sc, pb); +} + +static err_t +pppoe_send_pads(struct pppoe_softc *sc) +{ + struct pbuf *pb; + u8_t *p; + size_t len, l1 = 0; /* XXX: gcc */ + + if (sc->sc_state != PPPOE_STATE_PADO_SENT) { + return ERR_CONN; + } + + sc->sc_session = mono_time.tv_sec % 0xff + 1; + /* calc length */ + len = 0; + /* include hunique */ + len += 2 + 2 + 2 + 2 + sc->sc_hunique_len; /* service name, host unique*/ + if (sc->sc_service_name != NULL) { /* service name tag maybe empty */ + l1 = strlen(sc->sc_service_name); + len += l1; + } + pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + p = (u8_t*)pb->payload + sizeof (struct eth_hdr); + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADS, sc->sc_session, len); + PPPOE_ADD_16(p, PPPOE_TAG_SNAME); + if (sc->sc_service_name != NULL) { + PPPOE_ADD_16(p, l1); + MEMCPY(p, sc->sc_service_name, l1); + p += l1; + } else { + PPPOE_ADD_16(p, 0); + } + PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE); + PPPOE_ADD_16(p, sc->sc_hunique_len); + MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len); + return pppoe_output(sc, pb); +} +#endif + +err_t +pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb) +{ + u8_t *p; + size_t len; + + /* are we ready to process data yet? */ + if (sc->sc_state < PPPOE_STATE_SESSION) { + /*sppp_flush(&sc->sc_sppp.pp_if);*/ + pbuf_free(pb); + return ERR_CONN; + } + + len = pb->tot_len; + + /* make room for Ethernet header - should not fail */ + if (pbuf_header(pb, sizeof(struct eth_hdr) + PPPOE_HEADERLEN) != 0) { + /* bail out */ + PPPDEBUG(LOG_ERR, ("pppoe: %c%c%"U16_F": pppoe_xmit: could not allocate room for header\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + LINK_STATS_INC(link.lenerr); + pbuf_free(pb); + return ERR_BUF; + } + + p = (u8_t*)pb->payload + sizeof(struct eth_hdr); + PPPOE_ADD_HEADER(p, 0, sc->sc_session, len); + + return pppoe_output(sc, pb); +} + +#if 0 /*def PFIL_HOOKS*/ +static int +pppoe_ifattach_hook(void *arg, struct pbuf **mp, struct netif *ifp, int dir) +{ + struct pppoe_softc *sc; + int s; + + if (mp != (struct pbuf **)PFIL_IFNET_DETACH) { + return 0; + } + + LIST_FOREACH(sc, &pppoe_softc_list, sc_list) { + if (sc->sc_ethif != ifp) { + continue; + } + if (sc->sc_sppp.pp_if.if_flags & IFF_UP) { + sc->sc_sppp.pp_if.if_flags &= ~(IFF_UP|IFF_RUNNING); + printf("%c%c%"U16_F": ethernet interface detached, going down\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num); + } + sc->sc_ethif = NULL; + pppoe_clear_softc(sc, "ethernet interface detached"); + } + + return 0; +} +#endif + +static void +pppoe_clear_softc(struct pppoe_softc *sc, const char *message) +{ + LWIP_UNUSED_ARG(message); + + /* stop timer */ + sys_untimeout(pppoe_timeout, sc); + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": session 0x%x terminated, %s\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_session, message)); + + /* fix our state */ + sc->sc_state = PPPOE_STATE_INITIAL; + + /* notify upper layers */ + sc->sc_linkStatusCB(sc->sc_pd, 0); + + /* clean up softc */ + MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest)); + sc->sc_ac_cookie_len = 0; + sc->sc_session = 0; +} + +#endif /* PPPOE_SUPPORT */ + diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/pppdebug.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/pppdebug.h new file mode 100644 index 0000000..8134997 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/pppdebug.h @@ -0,0 +1,73 @@ +/***************************************************************************** +* pppdebug.h - System debugging utilities. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* portions Copyright (c) 2001 by Cognizant Pty Ltd. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY (please don't use tabs!) +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-07-29 Guy Lancaster , Global Election Systems Inc. +* Original. +* +***************************************************************************** +*/ +#ifndef PPPDEBUG_H +#define PPPDEBUG_H + +/* Trace levels. */ +#define LOG_CRITICAL (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE) +#define LOG_ERR (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE) +#define LOG_NOTICE (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING) +#define LOG_WARNING (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING) +#define LOG_INFO (PPP_DEBUG) +#define LOG_DETAIL (PPP_DEBUG) +#define LOG_DEBUG (PPP_DEBUG) + + +#define TRACELCP PPP_DEBUG + +#if PPP_DEBUG + +#define AUTHDEBUG(a, b) LWIP_DEBUGF(a, b) +#define IPCPDEBUG(a, b) LWIP_DEBUGF(a, b) +#define UPAPDEBUG(a, b) LWIP_DEBUGF(a, b) +#define LCPDEBUG(a, b) LWIP_DEBUGF(a, b) +#define FSMDEBUG(a, b) LWIP_DEBUGF(a, b) +#define CHAPDEBUG(a, b) LWIP_DEBUGF(a, b) +#define PPPDEBUG(a, b) LWIP_DEBUGF(a, b) + +#else /* PPP_DEBUG */ + +#define AUTHDEBUG(a, b) +#define IPCPDEBUG(a, b) +#define UPAPDEBUG(a, b) +#define LCPDEBUG(a, b) +#define FSMDEBUG(a, b) +#define CHAPDEBUG(a, b) +#define PPPDEBUG(a, b) + +#endif /* PPP_DEBUG */ + +#endif /* PPPDEBUG_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.c new file mode 100644 index 0000000..2f35caf --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.c @@ -0,0 +1,249 @@ +/***************************************************************************** +* randm.c - Random number generator program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1998 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-06-03 Guy Lancaster , Global Election Systems Inc. +* Extracted from avos. +*****************************************************************************/ + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "md5.h" +#include "randm.h" + +#include "ppp.h" +#include "pppdebug.h" + +#include + +#if MD5_SUPPORT /* this module depends on MD5 */ +#define RANDPOOLSZ 16 /* Bytes stored in the pool of randomness. */ + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static char randPool[RANDPOOLSZ]; /* Pool of randomness. */ +static long randCount = 0; /* Pseudo-random incrementer */ + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * Initialize the random number generator. + * + * Since this is to be called on power up, we don't have much + * system randomess to work with. Here all we use is the + * real-time clock. We'll accumulate more randomness as soon + * as things start happening. + */ +void +avRandomInit() +{ + avChurnRand(NULL, 0); +} + +/* + * Churn the randomness pool on a random event. Call this early and often + * on random and semi-random system events to build randomness in time for + * usage. For randomly timed events, pass a null pointer and a zero length + * and this will use the system timer and other sources to add randomness. + * If new random data is available, pass a pointer to that and it will be + * included. + * + * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 + */ +void +avChurnRand(char *randData, u32_t randLen) +{ + MD5_CTX md5; + + /* LWIP_DEBUGF(LOG_INFO, ("churnRand: %u@%P\n", randLen, randData)); */ + MD5Init(&md5); + MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); + if (randData) { + MD5Update(&md5, (u_char *)randData, randLen); + } else { + struct { + /* INCLUDE fields for any system sources of randomness */ + char foobar; + } sysData; + + /* Load sysData fields here. */ + MD5Update(&md5, (u_char *)&sysData, sizeof(sysData)); + } + MD5Final((u_char *)randPool, &md5); +/* LWIP_DEBUGF(LOG_INFO, ("churnRand: -> 0\n")); */ +} + +/* + * Use the random pool to generate random data. This degrades to pseudo + * random when used faster than randomness is supplied using churnRand(). + * Note: It's important that there be sufficient randomness in randPool + * before this is called for otherwise the range of the result may be + * narrow enough to make a search feasible. + * + * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 + * + * XXX Why does he not just call churnRand() for each block? Probably + * so that you don't ever publish the seed which could possibly help + * predict future values. + * XXX Why don't we preserve md5 between blocks and just update it with + * randCount each time? Probably there is a weakness but I wish that + * it was documented. + */ +void +avGenRand(char *buf, u32_t bufLen) +{ + MD5_CTX md5; + u_char tmp[16]; + u32_t n; + + while (bufLen > 0) { + n = LWIP_MIN(bufLen, RANDPOOLSZ); + MD5Init(&md5); + MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); + MD5Update(&md5, (u_char *)&randCount, sizeof(randCount)); + MD5Final(tmp, &md5); + randCount++; + MEMCPY(buf, tmp, n); + buf += n; + bufLen -= n; + } +} + +/* + * Return a new random number. + */ +u32_t +avRandom() +{ + u32_t newRand; + + avGenRand((char *)&newRand, sizeof(newRand)); + + return newRand; +} + +#else /* MD5_SUPPORT */ + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static int avRandomized = 0; /* Set when truely randomized. */ +static u32_t avRandomSeed = 0; /* Seed used for random number generation. */ + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * Initialize the random number generator. + * + * Here we attempt to compute a random number seed but even if + * it isn't random, we'll randomize it later. + * + * The current method uses the fields from the real time clock, + * the idle process counter, the millisecond counter, and the + * hardware timer tick counter. When this is invoked + * in startup(), then the idle counter and timer values may + * repeat after each boot and the real time clock may not be + * operational. Thus we call it again on the first random + * event. + */ +void +avRandomInit() +{ +#if 0 + /* Get a pointer into the last 4 bytes of clockBuf. */ + u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]); + + /* + * Initialize our seed using the real-time clock, the idle + * counter, the millisecond timer, and the hardware timer + * tick counter. The real-time clock and the hardware + * tick counter are the best sources of randomness but + * since the tick counter is only 16 bit (and truncated + * at that), the idle counter and millisecond timer + * (which may be small values) are added to help + * randomize the lower 16 bits of the seed. + */ + readClk(); + avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr + + ppp_mtime() + ((u32_t)TM1 << 16) + TM1; +#else + avRandomSeed += sys_jiffies(); /* XXX */ +#endif + + /* Initialize the Borland random number generator. */ + srand((unsigned)avRandomSeed); +} + +/* + * Randomize our random seed value. Here we use the fact that + * this function is called at *truely random* times by the polling + * and network functions. Here we only get 16 bits of new random + * value but we use the previous value to randomize the other 16 + * bits. + */ +void +avRandomize(void) +{ + static u32_t last_jiffies; + + if (!avRandomized) { + avRandomized = !0; + avRandomInit(); + /* The initialization function also updates the seed. */ + } else { + /* avRandomSeed += (avRandomSeed << 16) + TM1; */ + avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */ + } + last_jiffies = sys_jiffies(); +} + +/* + * Return a new random number. + * Here we use the Borland rand() function to supply a pseudo random + * number which we make truely random by combining it with our own + * seed which is randomized by truely random events. + * Thus the numbers will be truely random unless there have been no + * operator or network events in which case it will be pseudo random + * seeded by the real time clock. + */ +u32_t +avRandom() +{ + return ((((u32_t)rand() << 16) + rand()) + avRandomSeed); +} + +#endif /* MD5_SUPPORT */ + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.h new file mode 100644 index 0000000..a0984b0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.h @@ -0,0 +1,81 @@ +/***************************************************************************** +* randm.h - Random number generator header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-05-29 Guy Lancaster , Global Election Systems Inc. +* Extracted from avos. +*****************************************************************************/ + +#ifndef RANDM_H +#define RANDM_H + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ +/* + * Initialize the random number generator. + */ +void avRandomInit(void); + +/* + * Churn the randomness pool on a random event. Call this early and often + * on random and semi-random system events to build randomness in time for + * usage. For randomly timed events, pass a null pointer and a zero length + * and this will use the system timer and other sources to add randomness. + * If new random data is available, pass a pointer to that and it will be + * included. + */ +void avChurnRand(char *randData, u32_t randLen); + +/* + * Randomize our random seed value. To be called for truely random events + * such as user operations and network traffic. + */ +#if MD5_SUPPORT +#define avRandomize() avChurnRand(NULL, 0) +#else /* MD5_SUPPORT */ +void avRandomize(void); +#endif /* MD5_SUPPORT */ + +/* + * Use the random pool to generate random data. This degrades to pseudo + * random when used faster than randomness is supplied using churnRand(). + * Thus it's important to make sure that the results of this are not + * published directly because one could predict the next result to at + * least some degree. Also, it's important to get a good seed before + * the first use. + */ +void avGenRand(char *buf, u32_t bufLen); + +/* + * Return a new random number. + */ +u32_t avRandom(void); + + +#endif /* RANDM_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.c new file mode 100644 index 0000000..b7f2d54 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.c @@ -0,0 +1,652 @@ +/* + * Routines to compress and uncompess tcp packets (for transmission + * over low speed serial lines. + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: + * Initial distribution. + * + * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au, + * so that the entire packet being decompressed doesn't have + * to be in contiguous memory (just the compressed header). + * + * Modified March 1998 by Guy Lancaster, glanca@gesn.com, + * for a 16 bit processor. + */ + +#include "lwip/opt.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "ppp.h" +#include "pppdebug.h" + +#include "vj.h" + +#include + +#if VJ_SUPPORT + +#if LINK_STATS +#define INCR(counter) ++comp->stats.counter +#else +#define INCR(counter) +#endif + +void +vj_compress_init(struct vjcompress *comp) +{ + register u_char i; + register struct cstate *tstate = comp->tstate; + +#if MAX_SLOTS == 0 + memset((char *)comp, 0, sizeof(*comp)); +#endif + comp->maxSlotIndex = MAX_SLOTS - 1; + comp->compressSlot = 0; /* Disable slot ID compression by default. */ + for (i = MAX_SLOTS - 1; i > 0; --i) { + tstate[i].cs_id = i; + tstate[i].cs_next = &tstate[i - 1]; + } + tstate[0].cs_next = &tstate[MAX_SLOTS - 1]; + tstate[0].cs_id = 0; + comp->last_cs = &tstate[0]; + comp->last_recv = 255; + comp->last_xmit = 255; + comp->flags = VJF_TOSS; +} + + +/* ENCODE encodes a number that is known to be non-zero. ENCODEZ + * checks for zero (since zero has to be encoded in the long, 3 byte + * form). + */ +#define ENCODE(n) { \ + if ((u_short)(n) >= 256) { \ + *cp++ = 0; \ + cp[1] = (u_char)(n); \ + cp[0] = (u_char)((n) >> 8); \ + cp += 2; \ + } else { \ + *cp++ = (u_char)(n); \ + } \ +} +#define ENCODEZ(n) { \ + if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \ + *cp++ = 0; \ + cp[1] = (u_char)(n); \ + cp[0] = (u_char)((n) >> 8); \ + cp += 2; \ + } else { \ + *cp++ = (u_char)(n); \ + } \ +} + +#define DECODEL(f) { \ + if (*cp == 0) {\ + u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \ + (f) = htonl(tmp); \ + cp += 3; \ + } else { \ + u32_t tmp = ntohl(f) + (u32_t)*cp++; \ + (f) = htonl(tmp); \ + } \ +} + +#define DECODES(f) { \ + if (*cp == 0) {\ + u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \ + (f) = htons(tmp); \ + cp += 3; \ + } else { \ + u_short tmp = ntohs(f) + (u_short)*cp++; \ + (f) = htons(tmp); \ + } \ +} + +#define DECODEU(f) { \ + if (*cp == 0) {\ + (f) = htons(((u_short)cp[1] << 8) | cp[2]); \ + cp += 3; \ + } else { \ + (f) = htons((u_short)*cp++); \ + } \ +} + +/* + * vj_compress_tcp - Attempt to do Van Jacobson header compression on a + * packet. This assumes that nb and comp are not null and that the first + * buffer of the chain contains a valid IP header. + * Return the VJ type code indicating whether or not the packet was + * compressed. + */ +u_int +vj_compress_tcp(struct vjcompress *comp, struct pbuf *pb) +{ + register struct ip_hdr *ip = (struct ip_hdr *)pb->payload; + register struct cstate *cs = comp->last_cs->cs_next; + register u_short hlen = IPH_HL(ip); + register struct tcp_hdr *oth; + register struct tcp_hdr *th; + register u_short deltaS, deltaA; + register u_long deltaL; + register u_int changes = 0; + u_char new_seq[16]; + register u_char *cp = new_seq; + + /* + * Check that the packet is IP proto TCP. + */ + if (IPH_PROTO(ip) != IP_PROTO_TCP) { + return (TYPE_IP); + } + + /* + * Bail if this is an IP fragment or if the TCP packet isn't + * `compressible' (i.e., ACK isn't set or some other control bit is + * set). + */ + if ((IPH_OFFSET(ip) & PP_HTONS(0x3fff)) || pb->tot_len < 40) { + return (TYPE_IP); + } + th = (struct tcp_hdr *)&((long *)ip)[hlen]; + if ((TCPH_FLAGS(th) & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) { + return (TYPE_IP); + } + /* + * Packet is compressible -- we're going to send either a + * COMPRESSED_TCP or UNCOMPRESSED_TCP packet. Either way we need + * to locate (or create) the connection state. Special case the + * most recently used connection since it's most likely to be used + * again & we don't have to do any reordering if it's used. + */ + INCR(vjs_packets); + if (!ip_addr_cmp(&ip->src, &cs->cs_ip.src) + || !ip_addr_cmp(&ip->dest, &cs->cs_ip.dest) + || *(long *)th != ((long *)&cs->cs_ip)[IPH_HL(&cs->cs_ip)]) { + /* + * Wasn't the first -- search for it. + * + * States are kept in a circularly linked list with + * last_cs pointing to the end of the list. The + * list is kept in lru order by moving a state to the + * head of the list whenever it is referenced. Since + * the list is short and, empirically, the connection + * we want is almost always near the front, we locate + * states via linear search. If we don't find a state + * for the datagram, the oldest state is (re-)used. + */ + register struct cstate *lcs; + register struct cstate *lastcs = comp->last_cs; + + do { + lcs = cs; cs = cs->cs_next; + INCR(vjs_searches); + if (ip_addr_cmp(&ip->src, &cs->cs_ip.src) + && ip_addr_cmp(&ip->dest, &cs->cs_ip.dest) + && *(long *)th == ((long *)&cs->cs_ip)[IPH_HL(&cs->cs_ip)]) { + goto found; + } + } while (cs != lastcs); + + /* + * Didn't find it -- re-use oldest cstate. Send an + * uncompressed packet that tells the other side what + * connection number we're using for this conversation. + * Note that since the state list is circular, the oldest + * state points to the newest and we only need to set + * last_cs to update the lru linkage. + */ + INCR(vjs_misses); + comp->last_cs = lcs; + hlen += TCPH_OFFSET(th); + hlen <<= 2; + /* Check that the IP/TCP headers are contained in the first buffer. */ + if (hlen > pb->len) { + return (TYPE_IP); + } + goto uncompressed; + + found: + /* + * Found it -- move to the front on the connection list. + */ + if (cs == lastcs) { + comp->last_cs = lcs; + } else { + lcs->cs_next = cs->cs_next; + cs->cs_next = lastcs->cs_next; + lastcs->cs_next = cs; + } + } + + oth = (struct tcp_hdr *)&((long *)&cs->cs_ip)[hlen]; + deltaS = hlen; + hlen += TCPH_OFFSET(th); + hlen <<= 2; + /* Check that the IP/TCP headers are contained in the first buffer. */ + if (hlen > pb->len) { + PPPDEBUG(LOG_INFO, ("vj_compress_tcp: header len %d spans buffers\n", hlen)); + return (TYPE_IP); + } + + /* + * Make sure that only what we expect to change changed. The first + * line of the `if' checks the IP protocol version, header length & + * type of service. The 2nd line checks the "Don't fragment" bit. + * The 3rd line checks the time-to-live and protocol (the protocol + * check is unnecessary but costless). The 4th line checks the TCP + * header length. The 5th line checks IP options, if any. The 6th + * line checks TCP options, if any. If any of these things are + * different between the previous & current datagram, we send the + * current datagram `uncompressed'. + */ + if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] + || ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] + || ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] + || TCPH_OFFSET(th) != TCPH_OFFSET(oth) + || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) + || (TCPH_OFFSET(th) > 5 && BCMP(th + 1, oth + 1, (TCPH_OFFSET(th) - 5) << 2))) { + goto uncompressed; + } + + /* + * Figure out which of the changing fields changed. The + * receiver expects changes in the order: urgent, window, + * ack, seq (the order minimizes the number of temporaries + * needed in this section of code). + */ + if (TCPH_FLAGS(th) & TCP_URG) { + deltaS = ntohs(th->urgp); + ENCODEZ(deltaS); + changes |= NEW_U; + } else if (th->urgp != oth->urgp) { + /* argh! URG not set but urp changed -- a sensible + * implementation should never do this but RFC793 + * doesn't prohibit the change so we have to deal + * with it. */ + goto uncompressed; + } + + if ((deltaS = (u_short)(ntohs(th->wnd) - ntohs(oth->wnd))) != 0) { + ENCODE(deltaS); + changes |= NEW_W; + } + + if ((deltaL = ntohl(th->ackno) - ntohl(oth->ackno)) != 0) { + if (deltaL > 0xffff) { + goto uncompressed; + } + deltaA = (u_short)deltaL; + ENCODE(deltaA); + changes |= NEW_A; + } + + if ((deltaL = ntohl(th->seqno) - ntohl(oth->seqno)) != 0) { + if (deltaL > 0xffff) { + goto uncompressed; + } + deltaS = (u_short)deltaL; + ENCODE(deltaS); + changes |= NEW_S; + } + + switch(changes) { + case 0: + /* + * Nothing changed. If this packet contains data and the + * last one didn't, this is probably a data packet following + * an ack (normal on an interactive connection) and we send + * it compressed. Otherwise it's probably a retransmit, + * retransmitted ack or window probe. Send it uncompressed + * in case the other side missed the compressed version. + */ + if (IPH_LEN(ip) != IPH_LEN(&cs->cs_ip) && + ntohs(IPH_LEN(&cs->cs_ip)) == hlen) { + break; + } + + /* (fall through) */ + + case SPECIAL_I: + case SPECIAL_D: + /* + * actual changes match one of our special case encodings -- + * send packet uncompressed. + */ + goto uncompressed; + + case NEW_S|NEW_A: + if (deltaS == deltaA && deltaS == ntohs(IPH_LEN(&cs->cs_ip)) - hlen) { + /* special case for echoed terminal traffic */ + changes = SPECIAL_I; + cp = new_seq; + } + break; + + case NEW_S: + if (deltaS == ntohs(IPH_LEN(&cs->cs_ip)) - hlen) { + /* special case for data xfer */ + changes = SPECIAL_D; + cp = new_seq; + } + break; + } + + deltaS = (u_short)(ntohs(IPH_ID(ip)) - ntohs(IPH_ID(&cs->cs_ip))); + if (deltaS != 1) { + ENCODEZ(deltaS); + changes |= NEW_I; + } + if (TCPH_FLAGS(th) & TCP_PSH) { + changes |= TCP_PUSH_BIT; + } + /* + * Grab the cksum before we overwrite it below. Then update our + * state with this packet's header. + */ + deltaA = ntohs(th->chksum); + BCOPY(ip, &cs->cs_ip, hlen); + + /* + * We want to use the original packet as our compressed packet. + * (cp - new_seq) is the number of bytes we need for compressed + * sequence numbers. In addition we need one byte for the change + * mask, one for the connection id and two for the tcp checksum. + * So, (cp - new_seq) + 4 bytes of header are needed. hlen is how + * many bytes of the original packet to toss so subtract the two to + * get the new packet size. + */ + deltaS = (u_short)(cp - new_seq); + if (!comp->compressSlot || comp->last_xmit != cs->cs_id) { + comp->last_xmit = cs->cs_id; + hlen -= deltaS + 4; + if(pbuf_header(pb, -hlen)){ + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_header failed\n", 0); + } + cp = (u_char *)pb->payload; + *cp++ = (u_char)(changes | NEW_C); + *cp++ = cs->cs_id; + } else { + hlen -= deltaS + 3; + if(pbuf_header(pb, -hlen)) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_header failed\n", 0); + } + cp = (u_char *)pb->payload; + *cp++ = (u_char)changes; + } + *cp++ = (u_char)(deltaA >> 8); + *cp++ = (u_char)deltaA; + BCOPY(new_seq, cp, deltaS); + INCR(vjs_compressed); + return (TYPE_COMPRESSED_TCP); + + /* + * Update connection state cs & send uncompressed packet (that is, + * a regular ip/tcp packet but with the 'conversation id' we hope + * to use on future compressed packets in the protocol field). + */ +uncompressed: + BCOPY(ip, &cs->cs_ip, hlen); + IPH_PROTO_SET(ip, cs->cs_id); + comp->last_xmit = cs->cs_id; + return (TYPE_UNCOMPRESSED_TCP); +} + +/* + * Called when we may have missed a packet. + */ +void +vj_uncompress_err(struct vjcompress *comp) +{ + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); +} + +/* + * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP. + * Return 0 on success, -1 on failure. + */ +int +vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp) +{ + register u_int hlen; + register struct cstate *cs; + register struct ip_hdr *ip; + + ip = (struct ip_hdr *)nb->payload; + hlen = IPH_HL(ip) << 2; + if (IPH_PROTO(ip) >= MAX_SLOTS + || hlen + sizeof(struct tcp_hdr) > nb->len + || (hlen += TCPH_OFFSET(((struct tcp_hdr *)&((char *)ip)[hlen])) << 2) + > nb->len + || hlen > MAX_HDR) { + PPPDEBUG(LOG_INFO, ("vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", + IPH_PROTO(ip), hlen, nb->len)); + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); + return -1; + } + cs = &comp->rstate[comp->last_recv = IPH_PROTO(ip)]; + comp->flags &=~ VJF_TOSS; + IPH_PROTO_SET(ip, IP_PROTO_TCP); + BCOPY(ip, &cs->cs_ip, hlen); + cs->cs_hlen = (u_short)hlen; + INCR(vjs_uncompressedin); + return 0; +} + +/* + * Uncompress a packet of type TYPE_COMPRESSED_TCP. + * The packet is composed of a buffer chain and the first buffer + * must contain an accurate chain length. + * The first buffer must include the entire compressed TCP/IP header. + * This procedure replaces the compressed header with the uncompressed + * header and returns the length of the VJ header. + */ +int +vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp) +{ + u_char *cp; + struct tcp_hdr *th; + struct cstate *cs; + u_short *bp; + struct pbuf *n0 = *nb; + u32_t tmp; + u_int vjlen, hlen, changes; + + INCR(vjs_compressedin); + cp = (u_char *)n0->payload; + changes = *cp++; + if (changes & NEW_C) { + /* + * Make sure the state index is in range, then grab the state. + * If we have a good state index, clear the 'discard' flag. + */ + if (*cp >= MAX_SLOTS) { + PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: bad cid=%d\n", *cp)); + goto bad; + } + + comp->flags &=~ VJF_TOSS; + comp->last_recv = *cp++; + } else { + /* + * this packet has an implicit state index. If we've + * had a line error since the last time we got an + * explicit state index, we have to toss the packet. + */ + if (comp->flags & VJF_TOSS) { + PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: tossing\n")); + INCR(vjs_tossed); + return (-1); + } + } + cs = &comp->rstate[comp->last_recv]; + hlen = IPH_HL(&cs->cs_ip) << 2; + th = (struct tcp_hdr *)&((u_char *)&cs->cs_ip)[hlen]; + th->chksum = htons((*cp << 8) | cp[1]); + cp += 2; + if (changes & TCP_PUSH_BIT) { + TCPH_SET_FLAG(th, TCP_PSH); + } else { + TCPH_UNSET_FLAG(th, TCP_PSH); + } + + switch (changes & SPECIALS_MASK) { + case SPECIAL_I: + { + register u32_t i = ntohs(IPH_LEN(&cs->cs_ip)) - cs->cs_hlen; + /* some compilers can't nest inline assembler.. */ + tmp = ntohl(th->ackno) + i; + th->ackno = htonl(tmp); + tmp = ntohl(th->seqno) + i; + th->seqno = htonl(tmp); + } + break; + + case SPECIAL_D: + /* some compilers can't nest inline assembler.. */ + tmp = ntohl(th->seqno) + ntohs(IPH_LEN(&cs->cs_ip)) - cs->cs_hlen; + th->seqno = htonl(tmp); + break; + + default: + if (changes & NEW_U) { + TCPH_SET_FLAG(th, TCP_URG); + DECODEU(th->urgp); + } else { + TCPH_UNSET_FLAG(th, TCP_URG); + } + if (changes & NEW_W) { + DECODES(th->wnd); + } + if (changes & NEW_A) { + DECODEL(th->ackno); + } + if (changes & NEW_S) { + DECODEL(th->seqno); + } + break; + } + if (changes & NEW_I) { + DECODES(cs->cs_ip._id); + } else { + IPH_ID_SET(&cs->cs_ip, ntohs(IPH_ID(&cs->cs_ip)) + 1); + IPH_ID_SET(&cs->cs_ip, htons(IPH_ID(&cs->cs_ip))); + } + + /* + * At this point, cp points to the first byte of data in the + * packet. Fill in the IP total length and update the IP + * header checksum. + */ + vjlen = (u_short)(cp - (u_char*)n0->payload); + if (n0->len < vjlen) { + /* + * We must have dropped some characters (crc should detect + * this but the old slip framing won't) + */ + PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: head buffer %d too short %d\n", + n0->len, vjlen)); + goto bad; + } + +#if BYTE_ORDER == LITTLE_ENDIAN + tmp = n0->tot_len - vjlen + cs->cs_hlen; + IPH_LEN_SET(&cs->cs_ip, htons((u_short)tmp)); +#else + IPH_LEN_SET(&cs->cs_ip, htons(n0->tot_len - vjlen + cs->cs_hlen)); +#endif + + /* recompute the ip header checksum */ + bp = (u_short *) &cs->cs_ip; + IPH_CHKSUM_SET(&cs->cs_ip, 0); + for (tmp = 0; hlen > 0; hlen -= 2) { + tmp += *bp++; + } + tmp = (tmp & 0xffff) + (tmp >> 16); + tmp = (tmp & 0xffff) + (tmp >> 16); + IPH_CHKSUM_SET(&cs->cs_ip, (u_short)(~tmp)); + + /* Remove the compressed header and prepend the uncompressed header. */ + if(pbuf_header(n0, -((s16_t)(vjlen)))) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_header failed\n", 0); + goto bad; + } + + if(LWIP_MEM_ALIGN(n0->payload) != n0->payload) { + struct pbuf *np, *q; + u8_t *bufptr; + + np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL); + if(!np) { + PPPDEBUG(LOG_WARNING, ("vj_uncompress_tcp: realign failed\n")); + goto bad; + } + + if(pbuf_header(np, -cs->cs_hlen)) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_header failed\n", 0); + goto bad; + } + + bufptr = n0->payload; + for(q = np; q != NULL; q = q->next) { + MEMCPY(q->payload, bufptr, q->len); + bufptr += q->len; + } + + if(n0->next) { + pbuf_chain(np, n0->next); + pbuf_dechain(n0); + } + pbuf_free(n0); + n0 = np; + } + + if(pbuf_header(n0, cs->cs_hlen)) { + struct pbuf *np; + + LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE); + np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL); + if(!np) { + PPPDEBUG(LOG_WARNING, ("vj_uncompress_tcp: prepend failed\n")); + goto bad; + } + pbuf_cat(np, n0); + n0 = np; + } + LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen); + MEMCPY(n0->payload, &cs->cs_ip, cs->cs_hlen); + + *nb = n0; + + return vjlen; + +bad: + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); + return (-1); +} + +#endif /* VJ_SUPPORT */ + +#endif /* PPP_SUPPORT */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.h b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.h new file mode 100644 index 0000000..fad1213 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.h @@ -0,0 +1,156 @@ +/* + * Definitions for tcp compression routines. + * + * $Id: vj.h,v 1.7 2010/02/22 17:52:09 goldsimon Exp $ + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: + * - Initial distribution. + */ + +#ifndef VJ_H +#define VJ_H + +#include "lwip/ip.h" +#include "lwip/tcp_impl.h" + +#define MAX_SLOTS 16 /* must be > 2 and < 256 */ +#define MAX_HDR 128 + +/* + * Compressed packet format: + * + * The first octet contains the packet type (top 3 bits), TCP + * 'push' bit, and flags that indicate which of the 4 TCP sequence + * numbers have changed (bottom 5 bits). The next octet is a + * conversation number that associates a saved IP/TCP header with + * the compressed packet. The next two octets are the TCP checksum + * from the original datagram. The next 0 to 15 octets are + * sequence number changes, one change per bit set in the header + * (there may be no changes and there are two special cases where + * the receiver implicitly knows what changed -- see below). + * + * There are 5 numbers which can change (they are always inserted + * in the following order): TCP urgent pointer, window, + * acknowlegement, sequence number and IP ID. (The urgent pointer + * is different from the others in that its value is sent, not the + * change in value.) Since typical use of SLIP links is biased + * toward small packets (see comments on MTU/MSS below), changes + * use a variable length coding with one octet for numbers in the + * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the + * range 256 - 65535 or 0. (If the change in sequence number or + * ack is more than 65535, an uncompressed packet is sent.) + */ + +/* + * Packet types (must not conflict with IP protocol version) + * + * The top nibble of the first octet is the packet type. There are + * three possible types: IP (not proto TCP or tcp with one of the + * control flags set); uncompressed TCP (a normal IP/TCP packet but + * with the 8-bit protocol field replaced by an 8-bit connection id -- + * this type of packet syncs the sender & receiver); and compressed + * TCP (described above). + * + * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and + * is logically part of the 4-bit "changes" field that follows. Top + * three bits are actual packet type. For backward compatibility + * and in the interest of conserving bits, numbers are chosen so the + * IP protocol version number (4) which normally appears in this nibble + * means "IP packet". + */ + +/* packet types */ +#define TYPE_IP 0x40 +#define TYPE_UNCOMPRESSED_TCP 0x70 +#define TYPE_COMPRESSED_TCP 0x80 +#define TYPE_ERROR 0x00 + +/* Bits in first octet of compressed packet */ +#define NEW_C 0x40 /* flag bits for what changed in a packet */ +#define NEW_I 0x20 +#define NEW_S 0x08 +#define NEW_A 0x04 +#define NEW_W 0x02 +#define NEW_U 0x01 + +/* reserved, special-case values of above */ +#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */ +#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */ +#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U) + +#define TCP_PUSH_BIT 0x10 + + +/* + * "state" data for each active tcp conversation on the wire. This is + * basically a copy of the entire IP/TCP header from the last packet + * we saw from the conversation together with a small identifier + * the transmit & receive ends of the line use to locate saved header. + */ +struct cstate { + struct cstate *cs_next; /* next most recently used state (xmit only) */ + u_short cs_hlen; /* size of hdr (receive only) */ + u_char cs_id; /* connection # associated with this state */ + u_char cs_filler; + union { + char csu_hdr[MAX_HDR]; + struct ip_hdr csu_ip; /* ip/tcp hdr from most recent packet */ + } vjcs_u; +}; +#define cs_ip vjcs_u.csu_ip +#define cs_hdr vjcs_u.csu_hdr + + +struct vjstat { + unsigned long vjs_packets; /* outbound packets */ + unsigned long vjs_compressed; /* outbound compressed packets */ + unsigned long vjs_searches; /* searches for connection state */ + unsigned long vjs_misses; /* times couldn't find conn. state */ + unsigned long vjs_uncompressedin; /* inbound uncompressed packets */ + unsigned long vjs_compressedin; /* inbound compressed packets */ + unsigned long vjs_errorin; /* inbound unknown type packets */ + unsigned long vjs_tossed; /* inbound packets tossed because of error */ +}; + +/* + * all the state data for one serial line (we need one of these per line). + */ +struct vjcompress { + struct cstate *last_cs; /* most recently used tstate */ + u_char last_recv; /* last rcvd conn. id */ + u_char last_xmit; /* last sent conn. id */ + u_short flags; + u_char maxSlotIndex; + u_char compressSlot; /* Flag indicating OK to compress slot ID. */ +#if LINK_STATS + struct vjstat stats; +#endif + struct cstate tstate[MAX_SLOTS]; /* xmit connection states */ + struct cstate rstate[MAX_SLOTS]; /* receive connection states */ +}; + +/* flag values */ +#define VJF_TOSS 1U /* tossing rcvd frames because of input err */ + +extern void vj_compress_init (struct vjcompress *comp); +extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb); +extern void vj_uncompress_err (struct vjcompress *comp); +extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp); +extern int vj_uncompress_tcp (struct pbuf **nb, struct vjcompress *comp); + +#endif /* VJ_H */ diff --git a/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/slipif.c b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/slipif.c new file mode 100644 index 0000000..c19333d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/ethernet/lwip-1.4.0/src/netif/slipif.c @@ -0,0 +1,367 @@ +/** + * @file + * SLIP Interface + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is built upon the file: src/arch/rtxc/netif/sioslip.c + * + * Author: Magnus Ivarsson + */ + +/* + * This is an arch independent SLIP netif. The specific serial hooks must be + * provided by another file. They are sio_open, sio_read/sio_tryread and sio_send + */ + +#include "netif/slipif.h" +#include "lwip/opt.h" + +#if LWIP_HAVE_SLIPIF + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/sio.h" + +#define SLIP_BLOCK 1 +#define SLIP_DONTBLOCK 0 + +#define SLIP_END 0300 /* 0xC0 */ +#define SLIP_ESC 0333 /* 0xDB */ +#define SLIP_ESC_END 0334 /* 0xDC */ +#define SLIP_ESC_ESC 0335 /* 0xDD */ + +#define SLIP_MAX_SIZE 1500 + +enum slipif_recv_state { + SLIP_RECV_NORMAL, + SLIP_RECV_ESCAPE, +}; + +struct slipif_priv { + sio_fd_t sd; + /* q is the whole pbuf chain for a packet, p is the current pbuf in the chain */ + struct pbuf *p, *q; + enum slipif_recv_state state; + u16_t i, recved; +}; + +/** + * Send a pbuf doing the necessary SLIP encapsulation + * + * Uses the serial layer's sio_send() + * + * @param netif the lwip network interface structure for this slipif + * @param p the pbuf chaing packet to send + * @param ipaddr the ip address to send the packet to (not used for slipif) + * @return always returns ERR_OK since the serial layer does not provide return values + */ +err_t +slipif_output(struct netif *netif, struct pbuf *p, ip_addr_t *ipaddr) +{ + struct slipif_priv *priv; + struct pbuf *q; + u16_t i; + u8_t c; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); + LWIP_ASSERT("p != NULL", (p != NULL)); + + LWIP_UNUSED_ARG(ipaddr); + + priv = netif->state; + + /* Send pbuf out on the serial I/O device. */ + sio_send(SLIP_END, priv->sd); + + for (q = p; q != NULL; q = q->next) { + for (i = 0; i < q->len; i++) { + c = ((u8_t *)q->payload)[i]; + switch (c) { + case SLIP_END: + sio_send(SLIP_ESC, priv->sd); + sio_send(SLIP_ESC_END, priv->sd); + break; + case SLIP_ESC: + sio_send(SLIP_ESC, priv->sd); + sio_send(SLIP_ESC_ESC, priv->sd); + break; + default: + sio_send(c, priv->sd); + break; + } + } + } + sio_send(SLIP_END, priv->sd); + return ERR_OK; +} + +/** + * Static function for easy use of blockig or non-blocking + * sio_read + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @param block if 1, call sio_read; if 0, call sio_tryread + * @return return value of sio_read of sio_tryread + */ +static u32_t +slip_sio_read(sio_fd_t fd, u8_t* data, u32_t len, u8_t block) +{ + if (block) { + return sio_read(fd, data, len); + } else { + return sio_tryread(fd, data, len); + } +} + +/** + * Handle the incoming SLIP stream character by character + * + * Poll the serial layer by calling sio_read() or sio_tryread(). + * + * @param netif the lwip network interface structure for this slipif + * @param block if 1, block until data is received; if 0, return when all data + * from the buffer is received (multiple calls to this function will + * return a complete packet, NULL is returned before - used for polling) + * @return The IP packet when SLIP_END is received + */ +static struct pbuf * +slipif_input(struct netif *netif, u8_t block) +{ + struct slipif_priv *priv; + u8_t c; + struct pbuf *t; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); + + priv = netif->state; + + while (slip_sio_read(priv->sd, &c, 1, block) > 0) { + switch (priv->state) { + case SLIP_RECV_NORMAL: + switch (c) { + case SLIP_END: + if (priv->recved > 0) { + /* Received whole packet. */ + /* Trim the pbuf to the size of the received packet. */ + pbuf_realloc(priv->q, priv->recved); + + LINK_STATS_INC(link.recv); + + LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n")); + t = priv->q; + priv->p = priv->q = NULL; + priv->i = priv->recved = 0; + return t; + } + continue; + case SLIP_ESC: + priv->state = SLIP_RECV_ESCAPE; + continue; + } + break; + case SLIP_RECV_ESCAPE: + switch (c) { + case SLIP_ESC_END: + c = SLIP_END; + break; + case SLIP_ESC_ESC: + c = SLIP_ESC; + break; + } + priv->state = SLIP_RECV_NORMAL; + /* FALLTHROUGH */ + } + + /* byte received, packet not yet completely received */ + if (priv->p == NULL) { + /* allocate a new pbuf */ + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n")); + priv->p = pbuf_alloc(PBUF_LINK, (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN), PBUF_POOL); + + if (priv->p == NULL) { + LINK_STATS_INC(link.drop); + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n")); + /* don't process any further since we got no pbuf to receive to */ + break; + } + + if (priv->q != NULL) { + /* 'chain' the pbuf to the existing chain */ + pbuf_cat(priv->q, priv->p); + } else { + /* p is the first pbuf in the chain */ + priv->q = priv->p; + } + } + + /* this automatically drops bytes if > SLIP_MAX_SIZE */ + if ((priv->p != NULL) && (priv->recved <= SLIP_MAX_SIZE)) { + ((u8_t *)priv->p->payload)[priv->i] = c; + priv->recved++; + priv->i++; + if (priv->i >= priv->p->len) { + /* on to the next pbuf */ + priv->i = 0; + if (priv->p->next != NULL && priv->p->next->len > 0) { + /* p is a chain, on to the next in the chain */ + priv->p = priv->p->next; + } else { + /* p is a single pbuf, set it to NULL so next time a new + * pbuf is allocated */ + priv->p = NULL; + } + } + } + } + + return NULL; +} + +#if !NO_SYS +/** + * The SLIP input thread. + * + * Feed the IP layer with incoming packets + * + * @param nf the lwip network interface structure for this slipif + */ +static void +slipif_loop_thread(void *nf) +{ + struct pbuf *p; + struct netif *netif = (struct netif *)nf; + + while (1) { + p = slipif_input(netif, SLIP_BLOCK); + if (p != NULL) { + if (netif->input(p, netif) != ERR_OK) { + pbuf_free(p); + p = NULL; + } + } + } +} +#endif /* !NO_SYS */ + +/** + * SLIP netif initialization + * + * Call the arch specific sio_open and remember + * the opened device in the state field of the netif. + * + * @param netif the lwip network interface structure for this slipif + * @return ERR_OK if serial line could be opened, + * ERR_MEM if no memory could be allocated, + * ERR_IF is serial line couldn't be opened + * + * @note netif->num must contain the number of the serial port to open + * (0 by default) + */ +err_t +slipif_init(struct netif *netif) +{ + struct slipif_priv *priv; + + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num)); + + /* Allocate private data */ + priv = mem_malloc(sizeof(struct slipif_priv)); + if (!priv) { + return ERR_MEM; + } + + netif->name[0] = 's'; + netif->name[1] = 'l'; + netif->output = slipif_output; + netif->mtu = SLIP_MAX_SIZE; + netif->flags |= NETIF_FLAG_POINTTOPOINT; + + /* Try to open the serial port (netif->num contains the port number). */ + priv->sd = sio_open(netif->num); + if (!priv->sd) { + /* Opening the serial port failed. */ + mem_free(priv); + return ERR_IF; + } + + /* Initialize private data */ + priv->p = NULL; + priv->q = NULL; + priv->state = SLIP_RECV_NORMAL; + priv->i = 0; + priv->recved = 0; + + netif->state = priv; + + /* initialize the snmp variables and counters inside the struct netif + * ifSpeed: no assumption can be made without knowing more about the + * serial line! + */ + NETIF_INIT_SNMP(netif, snmp_ifType_slip, 0); + + /* Create a thread to poll the serial line. */ + sys_thread_new(SLIPIF_THREAD_NAME, slipif_loop_thread, netif, + SLIPIF_THREAD_STACKSIZE, SLIPIF_THREAD_PRIO); + return ERR_OK; +} + +/** + * Polls the serial device and feeds the IP layer with incoming packets. + * + * @param netif The lwip network interface structure for this slipif + */ +void +slipif_poll(struct netif *netif) +{ + struct pbuf *p; + struct slipif_priv *priv; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); + + priv = netif->state; + + while ((p = slipif_input(netif, SLIP_DONTBLOCK)) != NULL) { + if (netif->input(p, netif) != ERR_OK) { + pbuf_free(p); + } + } +} + +#endif /* LWIP_HAVE_SLIPIF */ diff --git a/SOFTWARE-FreeRTOS/Common/include/AbortDelay.h b/SOFTWARE-FreeRTOS/Common/include/AbortDelay.h new file mode 100644 index 0000000..7e6fa76 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/AbortDelay.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef ABORT_DELAY_H +#define ABORT_DELAY_H + +void vCreateAbortDelayTasks( void ); +BaseType_t xAreAbortDelayTestTasksStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/BlockQ.h b/SOFTWARE-FreeRTOS/Common/include/BlockQ.h new file mode 100644 index 0000000..aea4273 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/BlockQ.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef BLOCK_Q_H +#define BLOCK_Q_H + +void vStartBlockingQueueTasks( UBaseType_t uxPriority ); +BaseType_t xAreBlockingQueuesStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/EventGroupsDemo.h b/SOFTWARE-FreeRTOS/Common/include/EventGroupsDemo.h new file mode 100644 index 0000000..5f06d25 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/EventGroupsDemo.h @@ -0,0 +1,42 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + +/* + * This file contains fairly comprehensive checks on the behaviour of event + * groups. It is not intended to be a user friendly demonstration of the event + * groups API. + */ + +#ifndef EVENT_GROUPS_DEMO_H +#define EVENT_GROUPS_DEMO_H + +void vStartEventGroupTasks( void ); +BaseType_t xAreEventGroupTasksStillRunning( void ); +void vPeriodicEventGroupsProcessing( void ); + +#endif /* EVENT_GROUPS_DEMO_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/GenQTest.h b/SOFTWARE-FreeRTOS/Common/include/GenQTest.h new file mode 100644 index 0000000..e5923a5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/GenQTest.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef GEN_Q_TEST_H +#define GEN_Q_TEST_H + +void vStartGenericQueueTasks( UBaseType_t uxPriority ); +BaseType_t xAreGenericQueueTasksStillRunning( void ); +void vMutexISRInteractionTest( void ); + +#endif /* GEN_Q_TEST_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/IntQueue.h b/SOFTWARE-FreeRTOS/Common/include/IntQueue.h new file mode 100644 index 0000000..249962a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/IntQueue.h @@ -0,0 +1,35 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef QUEUE_ACCESS_TEST +#define QUEUE_ACCESS_TEST + +void vStartInterruptQueueTasks( void ); +BaseType_t xAreIntQueueTasksStillRunning( void ); +BaseType_t xFirstTimerHandler( void ); +BaseType_t xSecondTimerHandler( void ); + +#endif /* QUEUE_ACCESS_TEST */ diff --git a/SOFTWARE-FreeRTOS/Common/include/IntSemTest.h b/SOFTWARE-FreeRTOS/Common/include/IntSemTest.h new file mode 100644 index 0000000..0242906 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/IntSemTest.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef INT_SEM_TEST_H +#define INT_SEM_TEST_H + +void vStartInterruptSemaphoreTasks( void ); +BaseType_t xAreInterruptSemaphoreTasksStillRunning( void ); +void vInterruptSemaphorePeriodicTest( void ); + +#endif /* INT_SEM_TEST_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/MessageBufferAMP.h b/SOFTWARE-FreeRTOS/Common/include/MessageBufferAMP.h new file mode 100644 index 0000000..932ad93 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/MessageBufferAMP.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef MESSAGE_BUFFER_AMP_H +#define MESSAGE_BUFFER_AMP_H + +void vStartMessageBufferAMPTasks( configSTACK_DEPTH_TYPE xStackSize ); +BaseType_t xAreMessageBufferAMPTasksStillRunning( void ); +void vGenerateCoreBInterrupt( void * xUpdatedMessageBuffer ); + +#endif /* MESSAGE_BUFFER_AMP_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/MessageBufferDemo.h b/SOFTWARE-FreeRTOS/Common/include/MessageBufferDemo.h new file mode 100644 index 0000000..cf4c825 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/MessageBufferDemo.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef MESSAGE_BUFFER_TEST_H +#define MESSAGE_BUFFER_TEST_H + +void vStartMessageBufferTasks( configSTACK_DEPTH_TYPE xStackSize ); +BaseType_t xAreMessageBufferTasksStillRunning( void ); + +#endif /* MESSAGE_BUFFER_TEST_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/PollQ.h b/SOFTWARE-FreeRTOS/Common/include/PollQ.h new file mode 100644 index 0000000..8585dbf --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/PollQ.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef POLLED_Q_H +#define POLLED_Q_H + +void vStartPolledQueueTasks( UBaseType_t uxPriority ); +BaseType_t xArePollingQueuesStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/QPeek.h b/SOFTWARE-FreeRTOS/Common/include/QPeek.h new file mode 100644 index 0000000..f5d8e81 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/QPeek.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef Q_PEEK_TEST_H +#define Q_PEEK_TEST_H + +void vStartQueuePeekTasks( void ); +BaseType_t xAreQueuePeekTasksStillRunning( void ); + +#endif /* Q_PEEK_TEST_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/QueueOverwrite.h b/SOFTWARE-FreeRTOS/Common/include/QueueOverwrite.h new file mode 100644 index 0000000..a66c660 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/QueueOverwrite.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef QUEUE_OVERWRITE_H +#define QUEUE_OVERWRITE_H + +void vStartQueueOverwriteTask( UBaseType_t uxPriority ); +BaseType_t xIsQueueOverwriteTaskStillRunning( void ); +void vQueueOverwritePeriodicISRDemo( void ); + +#endif /* QUEUE_OVERWRITE_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/QueueSet.h b/SOFTWARE-FreeRTOS/Common/include/QueueSet.h new file mode 100644 index 0000000..4e66d06 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/QueueSet.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef QUEUE_WAIT_MULTIPLE_H +#define QUEUE_WAIT_MULTIPLE_H + +void vStartQueueSetTasks( void ); +BaseType_t xAreQueueSetTasksStillRunning( void ); +void vQueueSetAccessQueueSetFromISR( void ); + +#endif /* QUEUE_WAIT_MULTIPLE_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/QueueSetPolling.h b/SOFTWARE-FreeRTOS/Common/include/QueueSetPolling.h new file mode 100644 index 0000000..c83cc47 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/QueueSetPolling.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef QUEUE_SET_POLLING_H +#define QUEUE_SET_POLLING_H + +void vStartQueueSetPollingTask( void ); +BaseType_t xAreQueueSetPollTasksStillRunning( void ); +void vQueueSetPollingInterruptAccess( void ); + +#endif /* QUEUE_SET_POLLING_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/StaticAllocation.h b/SOFTWARE-FreeRTOS/Common/include/StaticAllocation.h new file mode 100644 index 0000000..e729b41 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/StaticAllocation.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef STATIC_ALLOCATION_H +#define STATIC_ALLOCATION_H + +void vStartStaticallyAllocatedTasks( void ); +BaseType_t xAreStaticAllocationTasksStillRunning( void ); + +#endif /* STATIC_ALLOCATION_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/StreamBufferDemo.h b/SOFTWARE-FreeRTOS/Common/include/StreamBufferDemo.h new file mode 100644 index 0000000..ace38ac --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/StreamBufferDemo.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef STREAM_BUFFER_TEST_H +#define STREAM_BUFFER_TEST_H + +void vStartStreamBufferTasks( void ); +BaseType_t xAreStreamBufferTasksStillRunning( void ); +void vPeriodicStreamBufferProcessing( void ); + +#endif /* STREAM_BUFFER_TEST_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/StreamBufferInterrupt.h b/SOFTWARE-FreeRTOS/Common/include/StreamBufferInterrupt.h new file mode 100644 index 0000000..885afa6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/StreamBufferInterrupt.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef STREAM_BUFFER_INTERRUPT_H +#define STREAM_BUFFER_INTERRUPT_H + +void vStartStreamBufferInterruptDemo( void ); +void vBasicStreamBufferSendFromISR( void ); +BaseType_t xIsInterruptStreamBufferDemoStillRunning( void ); + +#endif /* STREAM_BUFFER_INTERRUPT_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/TaskNotify.h b/SOFTWARE-FreeRTOS/Common/include/TaskNotify.h new file mode 100644 index 0000000..4e53148 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/TaskNotify.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef TASK_NOTIFY_H +#define TASK_NOTIFY_H + +void vStartTaskNotifyTask( void ); +BaseType_t xAreTaskNotificationTasksStillRunning( void ); +void xNotifyTaskFromISR( void ); + +#endif /* TASK_NOTIFY_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/TaskNotifyArray.h b/SOFTWARE-FreeRTOS/Common/include/TaskNotifyArray.h new file mode 100644 index 0000000..d933cff --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/TaskNotifyArray.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef TASK_NOTIFY_ARRAY_H +#define TASK_NOTIFY_ARRAY_H + +void vStartTaskNotifyArrayTask( void ); +BaseType_t xAreTaskNotificationArrayTasksStillRunning( void ); +void xNotifyArrayTaskFromISR( void ); + +#endif /* TASK_NOTIFY_ARRAY_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/TimerDemo.h b/SOFTWARE-FreeRTOS/Common/include/TimerDemo.h new file mode 100644 index 0000000..ba48fac --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/TimerDemo.h @@ -0,0 +1,43 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef TIMER_DEMO_H +#define TIMER_DEMO_H + +void vStartTimerDemoTask( TickType_t xBaseFrequencyIn ); +BaseType_t xAreTimerDemoTasksStillRunning( TickType_t xCycleFrequency ); +void vTimerPeriodicISRTests( void ); + +/* + * Test the behavior of backlogged timers. The backlog tests should not be + * included while other demos are running concurrently with the timer demo. The + * backlog tests utilize xTaskCatchUpTicks(), which is logically equivalent to + * starving all tasks for some number of ticks. Under these conditions, other + * demos may errantly detect test failures. + */ +void vTimerDemoIncludeBacklogTests( BaseType_t includeBacklogTests ); + +#endif /* TIMER_DEMO_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/blocktim.h b/SOFTWARE-FreeRTOS/Common/include/blocktim.h new file mode 100644 index 0000000..9bd17db --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/blocktim.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef BLOCK_TIME_TEST_H +#define BLOCK_TIME_TEST_H + +void vCreateBlockTimeTasks( void ); +BaseType_t xAreBlockTimeTestTasksStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/comtest.h b/SOFTWARE-FreeRTOS/Common/include/comtest.h new file mode 100644 index 0000000..4b3acda --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/comtest.h @@ -0,0 +1,39 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef COMTEST_H +#define COMTEST_H + +void vAltStartComTestTasks( UBaseType_t uxPriority, + uint32_t ulBaudRate, + UBaseType_t uxLED ); +void vStartComTestTasks( UBaseType_t uxPriority, + eCOMPort ePort, + eBaud eBaudRate ); +BaseType_t xAreComTestTasksStillRunning( void ); +void vComTestUnsuspendTask( void ); + +#endif /* ifndef COMTEST_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/comtest2.h b/SOFTWARE-FreeRTOS/Common/include/comtest2.h new file mode 100644 index 0000000..c4d0da1 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/comtest2.h @@ -0,0 +1,35 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef COMTEST_H +#define COMTEST_H + +void vAltStartComTestTasks( UBaseType_t uxPriority, + uint32_t ulBaudRate, + UBaseType_t uxLED ); +BaseType_t xAreComTestTasksStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/comtest_strings.h b/SOFTWARE-FreeRTOS/Common/include/comtest_strings.h new file mode 100644 index 0000000..7d38157 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/comtest_strings.h @@ -0,0 +1,35 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef COMTEST_STRINGS_H +#define COMTEST_STRINGS_H + +void vStartComTestStringsTasks( UBaseType_t uxPriority, + uint32_t ulBaudRate, + UBaseType_t uxLED ); +BaseType_t xAreComTestTasksStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/countsem.h b/SOFTWARE-FreeRTOS/Common/include/countsem.h new file mode 100644 index 0000000..6951ffd --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/countsem.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef COUNT_SEMAPHORE_TEST_H +#define COUNT_SEMAPHORE_TEST_H + +void vStartCountingSemaphoreTasks( void ); +BaseType_t xAreCountingSemaphoreTasksStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/crflash.h b/SOFTWARE-FreeRTOS/Common/include/crflash.h new file mode 100644 index 0000000..a6c8064 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/crflash.h @@ -0,0 +1,45 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef CRFLASH_LED_H +#define CRFLASH_LED_H + +/* + * Create the co-routines used to flash the LED's at different rates. + * + * @param uxPriority The number of 'fixed delay' co-routines to create. This + * also effects the number of LED's that will be utilised. For example, + * passing in 3 will cause LED's 0 to 2 to be utilised. + */ +void vStartFlashCoRoutines( UBaseType_t uxPriority ); + +/* + * Return pdPASS or pdFAIL depending on whether an error has been detected + * or not. + */ +BaseType_t xAreFlashCoRoutinesStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/crhook.h b/SOFTWARE-FreeRTOS/Common/include/crhook.h new file mode 100644 index 0000000..aaed971 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/crhook.h @@ -0,0 +1,41 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef CRHOOK_H +#define CRHOOK_H + +/* + * Create the co-routines used to communicate wit the tick hook. + */ +void vStartHookCoRoutines( void ); + +/* + * Return pdPASS or pdFAIL depending on whether an error has been detected + * or not. + */ +BaseType_t xAreHookCoRoutinesStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/death.h b/SOFTWARE-FreeRTOS/Common/include/death.h new file mode 100644 index 0000000..c4fe160 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/death.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SUICIDE_TASK_H +#define SUICIDE_TASK_H + +void vCreateSuicidalTasks( UBaseType_t uxPriority ); +BaseType_t xIsCreateTaskStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/dynamic.h b/SOFTWARE-FreeRTOS/Common/include/dynamic.h new file mode 100644 index 0000000..f3a3c16 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/dynamic.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DYNAMIC_MANIPULATION_H +#define DYNAMIC_MANIPULATION_H + +void vStartDynamicPriorityTasks( void ); +BaseType_t xAreDynamicPriorityTasksStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/fileIO.h b/SOFTWARE-FreeRTOS/Common/include/fileIO.h new file mode 100644 index 0000000..0039a87 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/fileIO.h @@ -0,0 +1,35 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FILE_IO_H +#define FILE_IO_H + +void vDisplayMessage( const char * const pcMessageToPrint ); +void vWriteMessageToDisk( const char * const pcMessage ); +void vWriteBufferToDisk( const char * const pcBuffer, + uint32_t ulBufferLength ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/flash.h b/SOFTWARE-FreeRTOS/Common/include/flash.h new file mode 100644 index 0000000..d301837 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/flash.h @@ -0,0 +1,32 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FLASH_LED_H +#define FLASH_LED_H + +void vStartLEDFlashTasks( UBaseType_t uxPriority ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/flash_timer.h b/SOFTWARE-FreeRTOS/Common/include/flash_timer.h new file mode 100644 index 0000000..b82e88d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/flash_timer.h @@ -0,0 +1,40 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FLASH_TIMER_H +#define FLASH_TIMER_H + +/* + * Creates the LED flashing timers. xNumberOfLEDs specifies how many timers to + * create, with each timer toggling a different LED. The first LED to be + * toggled is LED 0, with subsequent LEDs following on in numerical order. Each + * timer uses the exact same callback function, with the timer ID being used + * within the callback function to determine which timer has actually expired + * (and therefore which LED to toggle). + */ +void vStartLEDFlashTimers( UBaseType_t uxNumberOfLEDs ); + +#endif /* FLASH_TIMER_H */ diff --git a/SOFTWARE-FreeRTOS/Common/include/flop.h b/SOFTWARE-FreeRTOS/Common/include/flop.h new file mode 100644 index 0000000..3fb2d8a --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/flop.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FLOP_TASKS_H +#define FLOP_TASKS_H + +void vStartMathTasks( UBaseType_t uxPriority ); +BaseType_t xAreMathsTaskStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/integer.h b/SOFTWARE-FreeRTOS/Common/include/integer.h new file mode 100644 index 0000000..ff7dd17 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/integer.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef INTEGER_TASKS_H +#define INTEGER_TASKS_H + +void vStartIntegerMathTasks( UBaseType_t uxPriority ); +BaseType_t xAreIntegerMathsTaskStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/mevents.h b/SOFTWARE-FreeRTOS/Common/include/mevents.h new file mode 100644 index 0000000..7a4db7c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/mevents.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef EVENTS_TEST_H +#define EVENTS_TEST_H + +void vStartMultiEventTasks( void ); +BaseType_t xAreMultiEventTasksStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/partest.h b/SOFTWARE-FreeRTOS/Common/include/partest.h new file mode 100644 index 0000000..920f058 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/partest.h @@ -0,0 +1,37 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PARTEST_H +#define PARTEST_H + +#define partstDEFAULT_PORT_ADDRESS ( ( uint16_t ) 0x378 ) + +void vParTestInitialise( void ); +void vParTestSetLED( UBaseType_t uxLED, + BaseType_t xValue ); +void vParTestToggleLED( UBaseType_t uxLED ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/print.h b/SOFTWARE-FreeRTOS/Common/include/print.h new file mode 100644 index 0000000..57d6182 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/print.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PRINT_H +#define PRINT_H + +void vPrintInitialise( void ); +void vPrintDisplayMessage( const char * const * pcMessageToSend ); +const char * pcPrintGetNextMessage( TickType_t xPrintRate ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/recmutex.h b/SOFTWARE-FreeRTOS/Common/include/recmutex.h new file mode 100644 index 0000000..61c2024 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/recmutex.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef RECURSIVE_MUTEX_TEST_H +#define RECURSIVE_MUTEX_TEST_H + +void vStartRecursiveMutexTasks( void ); +BaseType_t xAreRecursiveMutexTasksStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/semtest.h b/SOFTWARE-FreeRTOS/Common/include/semtest.h new file mode 100644 index 0000000..74f447c --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/semtest.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SEMAPHORE_TEST_H +#define SEMAPHORE_TEST_H + +void vStartSemaphoreTasks( UBaseType_t uxPriority ); +BaseType_t xAreSemaphoreTasksStillRunning( void ); + +#endif diff --git a/SOFTWARE-FreeRTOS/Common/include/serial.h b/SOFTWARE-FreeRTOS/Common/include/serial.h new file mode 100644 index 0000000..add5790 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Common/include/serial.h @@ -0,0 +1,108 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SERIAL_COMMS_H +#define SERIAL_COMMS_H + +typedef void * xComPortHandle; + +typedef enum +{ + serCOM1, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, + unsigned portBASE_TYPE uxQueueLength ); +xComPortHandle xSerialPortInit( eCOMPort ePort, + eBaud eWantedBaud, + eParity eWantedParity, + eDataBits eWantedDataBits, + eStopBits eWantedStopBits, + unsigned portBASE_TYPE uxBufferLength ); +void vSerialPutString( xComPortHandle pxPort, + const signed char * const pcString, + unsigned short usStringLength ); +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, + signed char * pcRxedChar, + TickType_t xBlockTime ); +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, + signed char cOutChar, + TickType_t xBlockTime ); +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); +void vSerialClose( xComPortHandle xPort ); + +#endif /* ifndef SERIAL_COMMS_H */ diff --git a/SOFTWARE-FreeRTOS/FreeRTOS_Kernel_import.cmake b/SOFTWARE-FreeRTOS/FreeRTOS_Kernel_import.cmake new file mode 100644 index 0000000..dc68ed0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/FreeRTOS_Kernel_import.cmake @@ -0,0 +1,62 @@ +# This is a copy of /portable/ThirdParty/GCC/RP2040/FREERTOS_KERNEL_import.cmake + +# This can be dropped into an external project to help locate the FreeRTOS kernel +# It should be include()ed prior to project(). Alternatively this file may +# or the CMakeLists.txt in this directory may be included or added via add_subdirectory +# respectively. + +if (DEFINED ENV{FREERTOS_KERNEL_PATH} AND (NOT FREERTOS_KERNEL_PATH)) + set(FREERTOS_KERNEL_PATH $ENV{FREERTOS_KERNEL_PATH}) + message("Using FREERTOS_KERNEL_PATH from environment ('${FREERTOS_KERNEL_PATH}')") +endif () + +set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/GCC/RP2040") +# undo the above +set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../..") + +if (NOT FREERTOS_KERNEL_PATH) + # check if we are inside the FreeRTOS kernel tree (i.e. this file has been included directly) + get_filename_component(_ACTUAL_PATH ${CMAKE_CURRENT_LIST_DIR} REALPATH) + get_filename_component(_POSSIBLE_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} REALPATH) + if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH) + get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH) + endif() + if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH) + get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH) + message("Setting FREERTOS_KERNEL_PATH to ${FREERTOS_KERNEL_PATH} based on location of FreeRTOS-Kernel-import.cmake") + elseif (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../FreeRTOS-Kernel") + set(FREERTOS_KERNEL_PATH ${PICO_SDK_PATH}/../FreeRTOS-Kernel) + message("Defaulting FREERTOS_KERNEL_PATH as sibling of PICO_SDK_PATH: ${FREERTOS_KERNEL_PATH}") + endif() +endif () + +if (NOT FREERTOS_KERNEL_PATH) + foreach(POSSIBLE_SUFFIX Source FreeRTOS-Kernel FreeRTOS/Source) + # check if FreeRTOS-Kernel exists under directory that included us + set(SEARCH_ROOT ${CMAKE_CURRENT_SOURCE_DIR}}) + set(SEARCH_ROOT ../../../..) + get_filename_component(_POSSIBLE_PATH ${SEARCH_ROOT}/${POSSIBLE_SUFFIX} REALPATH) + if (EXISTS ${_POSSIBLE_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt) + get_filename_component(FREERTOS_KERNEL_PATH ${_POSSIBLE_PATH} REALPATH) + message("Setting FREERTOS_KERNEL_PATH to '${FREERTOS_KERNEL_PATH}' found relative to enclosing project") + break() + endif() + endforeach() +endif() + +if (NOT FREERTOS_KERNEL_PATH) + message(FATAL_ERROR "FreeRTOS location was not specified. Please set FREERTOS_KERNEL_PATH.") +endif() + +set(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" CACHE PATH "Path to the FreeRTOS Kernel") + +get_filename_component(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${FREERTOS_KERNEL_PATH}) + message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' not found") +endif() +if (NOT EXISTS ${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt) + message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' does not contain an RP2040 port here: ${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}") +endif() +set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} CACHE PATH "Path to the FreeRTOS_KERNEL" FORCE) + +add_subdirectory(${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} FREERTOS_KERNEL) \ No newline at end of file diff --git a/SOFTWARE-FreeRTOS/Source/DTH11.cpp b/SOFTWARE-FreeRTOS/Source/DTH11.cpp new file mode 100644 index 0000000..3446bcc --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/DTH11.cpp @@ -0,0 +1,70 @@ +#include "DTH11.hpp" + +typedef struct { + float humidity; + float temp_celsius; +} dht_reading; + +void read_from_dht(dht_reading * result, int DHT_PIN) +{ + int data[5] = { 0, 0, 0, 0, 0 }; + uint last = 1; + uint j = 0; + + gpio_set_dir(DHT_PIN, GPIO_OUT); + gpio_put(DHT_PIN, 0); + sleep_ms(20); + gpio_set_dir(DHT_PIN, GPIO_IN); + + for (uint i = 0; i < MAX_TIMINGS; i++) { + uint count = 0; + while (gpio_get(DHT_PIN) == last) { + count++; + sleep_us(1); + if (count == 255) + break; + } + + last = gpio_get(DHT_PIN); + if (count == 255) + break; + + if ((i >= 4) && (i % 2 == 0)) { + data[j / 8] <<= 1; + if (count > 16) + data[j / 8] |= 1; + j++; + } + } + + if ((j >= 40) && (data[4] == ((data[0] + data[1] + data[2] + data[3]) & 0xFF))) { + result->humidity = (float)((data[0] << 8) + data[1]) / 10; + if (result->humidity > 100) { + result->humidity = data[0]; + } + result->temp_celsius = (float)(((data[2] & 0x7F) << 8) + data[3]) / 10; + if (result->temp_celsius > 125) { + result->temp_celsius = data[2]; + } + if (data[2] & 0x80) { + result->temp_celsius = -result->temp_celsius; + } + } else { + printf("Bad data\n"); + } +} + +int DTH11_(int DHT_PIN) +{ + stdio_init_all(); + gpio_init(DHT_PIN); + + dht_reading reading; + read_from_dht(&reading, DHT_PIN); + float fahrenheit = (reading.temp_celsius * 9 / 5) + 32; + printf("Humidity = %.1f%%, Temperature = %.1fC (%.1fF)\n", reading.humidity, reading.temp_celsius, fahrenheit); + + sleep_ms(2000); + + return 0; +} diff --git a/SOFTWARE-FreeRTOS/Source/DTH11.hpp b/SOFTWARE-FreeRTOS/Source/DTH11.hpp new file mode 100644 index 0000000..8453386 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/DTH11.hpp @@ -0,0 +1,11 @@ +#ifndef DTH11_H +#define DTH11_H + +#include +#include +#include "pico/stdlib.h" +#include "hardware/gpio.h" + +const uint MAX_TIMINGS = 85; + +#endif diff --git a/SOFTWARE-FreeRTOS/Source/FreeRTOSConfig.h b/SOFTWARE-FreeRTOS/Source/FreeRTOSConfig.h new file mode 100644 index 0000000..01e777d --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/FreeRTOSConfig.h @@ -0,0 +1,137 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* Scheduler Related */ +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMAX_PRIORITIES 32 +#define configMINIMAL_STACK_SIZE ( configSTACK_DEPTH_TYPE ) 256 +#define configUSE_16_BIT_TICKS 0 + +#define configIDLE_SHOULD_YIELD 1 + +/* Synchronization Related */ +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 1 +#define configUSE_TIME_SLICING 1 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* System */ +#define configSTACK_DEPTH_TYPE uint32_t +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE (128*1024) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 1 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH 1024 + +/* Interrupt nesting behaviour configuration. */ +/* +#define configKERNEL_INTERRUPT_PRIORITY [dependent of processor] +#define configMAX_SYSCALL_INTERRUPT_PRIORITY [dependent on processor and application] +#define configMAX_API_CALL_INTERRUPT_PRIORITY [dependent on processor and application] +*/ + +/* SMP port only */ +#define configNUMBER_OF_CORES 1 +#define configTICK_CORE 0 +#define configRUN_MULTIPLE_PRIORITIES 0 + +/* RP2040 specific */ +#define configSUPPORT_PICO_SYNC_INTEROP 1 +#define configSUPPORT_PICO_TIME_INTEROP 1 + +#include +/* Define to trap errors during development. */ +#define configASSERT(x) assert(x) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xTaskResumeFromISR 1 +#define INCLUDE_xQueueGetMutexHolder 1 + +/* A header file that defines trace macro can be included here. */ + +#endif /* FREERTOS_CONFIG_H */ diff --git a/SOFTWARE-FreeRTOS/Source/HC-12.cpp b/SOFTWARE-FreeRTOS/Source/HC-12.cpp new file mode 100644 index 0000000..c7e0050 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/HC-12.cpp @@ -0,0 +1,20 @@ +#include "HC-12.hpp" + +void _HC_12_INIT() +{ + uint tx_offset = pio_add_program(pio1, &uart_tx_program); + uart_tx_program_init(HC_12_PIO, HC_12_PIO_SM_TX, tx_offset, HC_12_PIO_TX_PIN, HC_12_PIO_SERIAL_BAUD); + + uint rx_offset = pio_add_program(pio1, &uart_rx_program); + uart_rx_program_init(HC_12_PIO, HC_12_PIO_SM_RX, rx_offset, HC_12_PIO_RX_PIN, HC_12_PIO_SERIAL_BAUD); + + return; +} + +void _HC_12(const char *string) +{ + uart_tx_program_puts(HC_12_PIO, HC_12_PIO_SM_TX, string); + sleep_ms(100); + + return; +} diff --git a/SOFTWARE-FreeRTOS/Source/HC-12.hpp b/SOFTWARE-FreeRTOS/Source/HC-12.hpp new file mode 100644 index 0000000..506fff6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/HC-12.hpp @@ -0,0 +1,19 @@ +#ifndef HC_12_H +#define HC_12_H + +#include "pico/stdlib.h" +#include "hardware/pio.h" +#include "uart_tx.pio.h" +#include "uart_rx.pio.h" + +#define HC_12_PIO pio1 +#define HC_12_PIO_TX_PIN 16 // 接 HC-12 RX +#define HC_12_PIO_RX_PIN 15 // 接 HC-12 TX +#define HC_12_PIO_SM_TX 0 +#define HC_12_PIO_SM_RX 1 +#define HC_12_PIO_SERIAL_BAUD 9600 + +extern void _HC_12_INIT(); +extern void _HC_12(const char *string); + +#endif diff --git a/SOFTWARE-FreeRTOS/Source/ZC13.cpp b/SOFTWARE-FreeRTOS/Source/ZC13.cpp new file mode 100644 index 0000000..b80755e --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/ZC13.cpp @@ -0,0 +1,171 @@ +#include "ZC13.hpp" +#include "common.h" + +int ZC13_INIT() +{ + uint tx_offset = pio_add_program(ZC13_PIO, &uart_tx_program); + uart_tx_program_init(ZC13_PIO, ZC13_PIO_SM_TX, tx_offset, ZC13_PIO_TX_PIN, ZC13_PIO_SERIAL_BAUD); + + uint rx_offset = pio_add_program(ZC13_PIO, &uart_rx_program); + uart_rx_program_init(ZC13_PIO, ZC13_PIO_SM_RX, rx_offset, ZC13_PIO_RX_PIN, ZC13_PIO_SERIAL_BAUD); + + return 0; +} + +int ZC13_PIO_UART_TX_DATA(PIO pio, uint sm, uint8_t *DATA, int DATA_LEN) { + + for (int i = 0; i < DATA_LEN; i++) { + uart_tx_program_putc(pio, sm, DATA[i]); + sleep_ms(3); + } + + return 0; +} + +int ZC13_PIO_UART_RX_DATA(PIO pio, uint sm, uint8_t *DATA, int DATA_LEN) { + char c = '\0'; + int received_count = 0; + int timeout_ms = 100; // 设置较长的超时时间 + + while (received_count < DATA_LEN && timeout_ms > 0) { + if (uart_rx_program_available(pio, sm)) { + c = uart_rx_program_getc(pio, sm); + DATA[received_count++] = c; + printf("0x%X ", c); + if (c == '\n') { + // 接收到换行符，停止接收数据 + break; + } + } else { + // 没有接收到数据，继续等待 + sleep_ms(1); + timeout_ms--; + } + } + + if (received_count == 0) { + // 没有接收到有效数据，可以进行相应的处理 + return -1; + } + + return received_count; +} + +int ZC13(const char *model) +{ + uint8_t CH4_DATA[270] = { 0 }; + int CH4_DATA_LEN = 0; + + // 发送指令 + uint8_t CH4_CMD[9] = { 0xFF, 0x01, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79 }; + ZC13_PIO_UART_TX_DATA(ZC13_PIO, ZC13_PIO_SM_TX, CH4_CMD, sizeof(CH4_CMD)); + sleep_ms(200); + + // 接收指令 + CH4_DATA_LEN = ZC13_PIO_UART_RX_DATA(ZC13_PIO, ZC13_PIO_SM_RX, CH4_DATA, 9); + + + printf("\n"); + printf("%d\n", CH4_DATA_LEN); + + uint8_t highByte = CH4_DATA[2]; // 假设这是气体浓度高位字节 + uint8_t lowByte = CH4_DATA[3]; // 假设这是气体浓度高位字节 + + // 判断最高位是否为 1 + if (highByte & 0x80) { + // 最高位是 1，表示传感器故障 + printf("CH4 sensor malfunction!\n"); + } else { + if (CH4_DATA[1] == 0X86) { + if ( 0 == strcasecmp(model, "ZC05")) { + // 计算气体浓度值 + uint16_t gasConcentration = (highByte & 0x3F) * 256 + lowByte; + // 输出气体浓度值 + printf("CH4 Concentration: %uppm\n", gasConcentration); + + return gasConcentration; + } + + if ( 0 == strcasecmp(model, "ZC13")) { + // 计算气体浓度值 + uint16_t gasConcentration = (highByte & 0x1F) * 256 + lowByte; + // 输出气体浓度值 + printf("CH4 Concentration: %uppm\n", gasConcentration); + + return gasConcentration; + } + } + } + + return -1; +} + +/* +int ZC13(const char *model) +{ + char CH4_DATA[9] = { 0 }; + int CH4_DATA_index = 0; + + // 发送指令 + char CH4_CMD[9] = { 0xFF, 0x01, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79 }; + for (int i = 0; i < 9; i++) { + uart_tx_program_putc(ZC13_PIO, ZC13_PIO_SM_TX, CH4_CMD[i]); + sleep_ms(1); + } + sleep_ms(200); + + // 接收数据，直到收到换行符或达到缓冲区大小限制 + char c = '\0'; + int timeout_ms = 100; // 设置超时时间为100ms + int received_count = 0; + + while (received_count < 9 && timeout_ms > 0) { + if (uart_rx_program_available(ZC13_PIO, ZC13_PIO_SM_RX)) { + c = uart_rx_program_getc(ZC13_PIO, ZC13_PIO_SM_RX); + CH4_DATA[CH4_DATA_index++] = c; + received_count++; + timeout_ms = 100; // 重置超时时间 + } else { + sleep_ms(1); + timeout_ms--; // 减少超时时间 + } + } + + // 处理接收到的数据 + for (int i = 0; i < 9; i++) { + printf("0x%X ", CH4_DATA[i]); + } + printf("\n"); + + uint8_t highByte = CH4_DATA[2]; // 假设这是气体浓度高位字节 + uint8_t lowByte = CH4_DATA[3]; // 假设这是气体浓度高位字节 + + // 判断最高位是否为 1 + if (highByte & 0x80) { + // 最高位是 1，表示传感器故障 + printf("CH4 sensor malfunction!\n"); + } else { + if (CH4_DATA[1] == 0X86) { + if ( 0 == strcasecmp(model, "ZC05")) { + // 计算气体浓度值 + uint16_t gasConcentration = (highByte & 0x3F) * 256 + lowByte; + // 输出气体浓度值 + printf("CH4 Concentration: %uppm\n", gasConcentration); + + return gasConcentration; + } + + if ( 0 == strcasecmp(model, "ZC13")) { + // 计算气体浓度值 + uint16_t gasConcentration = (highByte & 0x1F) * 256 + lowByte; + // 输出气体浓度值 + printf("CH4 Concentration: %uppm\n", gasConcentration); + + return gasConcentration; + } + } + } + + return -1; +} +*/ \ No newline at end of file diff --git a/SOFTWARE-FreeRTOS/Source/ZC13.hpp b/SOFTWARE-FreeRTOS/Source/ZC13.hpp new file mode 100644 index 0000000..f703d71 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/ZC13.hpp @@ -0,0 +1,21 @@ +#ifndef ZC13_HPP +#define ZC13_HPP + +#include +#include +#include "pico/stdlib.h" +#include "hardware/pio.h" +#include "uart_tx.pio.h" +#include "uart_rx.pio.h" + +#define ZC13_PIO pio0 +#define ZC13_PIO_TX_PIN 19 // 接ZC13 4 TX PIN +#define ZC13_PIO_RX_PIN 20 // 接ZC13 5 RX PIN +#define ZC13_PIO_SM_TX 0 +#define ZC13_PIO_SM_RX 1 +#define ZC13_PIO_SERIAL_BAUD 9600 + +extern int ZC13_INIT(); +extern int ZC13(const char *model); + +#endif diff --git a/SOFTWARE-FreeRTOS/Source/common.c b/SOFTWARE-FreeRTOS/Source/common.c new file mode 100644 index 0000000..a7536d9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/common.c @@ -0,0 +1,81 @@ +#include "common.h" + +void vApplicationMallocFailedHook(void) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT((volatile void *)NULL); +} + +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName) +{ + (void)pcTaskName; + (void)pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT((volatile void *)NULL); +} + +void vApplicationTickHook(void) +{ +#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + /*完整的演示包括软件定时器演示/测试，需要 + 从滴答声中断中周期性地发出提示*/ +#if (mainENABLE_TIMER_DEMO == 1) + vTimerPeriodicISRTests(); +#endif + + /* Call the periodic queue overwrite from ISR demo. */ + /*调用ISR演示中的周期性队列覆盖*/ +#if (mainENABLE_QUEUE_OVERWRITE == 1) + vQueueOverwritePeriodicISRDemo(); +#endif + + /* Call the periodic event group from ISR demo. */ + /*从ISR演示中调用定期事件组*/ +#if (mainENABLE_EVENT_GROUP == 1) + vPeriodicEventGroupsProcessing(); +#endif + + /* Call the code that uses a mutex from an ISR. */ + /*从ISR调用使用互斥的代码*/ +#if (mainENABLE_INTERRUPT_SEMAPHORE == 1) + vInterruptSemaphorePeriodicTest(); +#endif + + /* Call the code that 'gives' a task notification from an ISR. */ + /*调用从ISR“发出”任务通知的代码*/ +#if (mainENABLE_TASK_NOTIFY == 1) + xNotifyTaskFromISR(); +#endif + } +#endif +} + + +void _printTaskStackHighWaterMark(void) +{ + TaskHandle_t currentTask = xTaskGetCurrentTaskHandle(); + if (currentTask != NULL) + { + printf("TASK STACK HIGH WATER MARK: %ld\n", uxTaskGetStackHighWaterMark(currentTask)); + } + else + { + printf("FAILED TO GET CURRENT TASK HANDLE.\n"); + } +} diff --git a/SOFTWARE-FreeRTOS/Source/common.h b/SOFTWARE-FreeRTOS/Source/common.h new file mode 100644 index 0000000..2c6ac72 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/common.h @@ -0,0 +1,22 @@ +#ifndef COMMOM_H +#define COMMOM_H + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +#include +#include "hardware/pio.h" + + +#define BUILD(fmt...) do { fprintf(stderr,"%s %s ",__DATE__,__TIME__); fprintf(stderr, ##fmt); } while(0) + +static inline bool uart_rx_program_available(PIO pio, uint sm) +{ + return !pio_sm_is_rx_fifo_empty(pio, sm); +} + +extern void _printTaskStackHighWaterMark(void); + +#endif diff --git a/SOFTWARE-FreeRTOS/Source/lwipopts.h b/SOFTWARE-FreeRTOS/Source/lwipopts.h new file mode 100644 index 0000000..8571ed5 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/lwipopts.h @@ -0,0 +1,10 @@ +#ifndef _LWIPOPTS_H +#define _LWIPOPTS_H + +// Generally you would define your own explicit list of lwIP options +// (see https://www.nongnu.org/lwip/2_1_x/group__lwip__opts.html) +// +// This example uses a common include to avoid repetition +#include "lwipopts_examples_common.h" + +#endif diff --git a/SOFTWARE-FreeRTOS/Source/lwipopts_examples_common.h b/SOFTWARE-FreeRTOS/Source/lwipopts_examples_common.h new file mode 100644 index 0000000..cb0ac56 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/lwipopts_examples_common.h @@ -0,0 +1,89 @@ +#ifndef _LWIPOPTS_EXAMPLE_COMMONH_H +#define _LWIPOPTS_EXAMPLE_COMMONH_H + +// Common settings used in most of the pico_w examples +// (see https://www.nongnu.org/lwip/2_1_x/group__lwip__opts.html for details) + +// allow override in some examples +#ifndef NO_SYS +#define NO_SYS 1 +#endif +// allow override in some examples +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 0 +#endif +#if PICO_CYW43_ARCH_POLL +#define MEM_LIBC_MALLOC 1 +#else +// MEM_LIBC_MALLOC is incompatible with non polling versions +#define MEM_LIBC_MALLOC 0 +#endif +#define MEM_ALIGNMENT 4 +#define MEM_SIZE 4000 +#define MEMP_NUM_TCP_SEG 32 +#define MEMP_NUM_ARP_QUEUE 10 +#define PBUF_POOL_SIZE 24 +#define LWIP_ARP 1 +#define LWIP_ETHERNET 1 +#define LWIP_ICMP 1 +#define LWIP_RAW 1 +#define TCP_WND (8 * TCP_MSS) +#define TCP_MSS 1460 +#define TCP_SND_BUF (8 * TCP_MSS) +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1)) / (TCP_MSS)) +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define LWIP_NETIF_HOSTNAME 1 +#define LWIP_NETCONN 0 +#define MEM_STATS 0 +#define SYS_STATS 0 +#define MEMP_STATS 0 +#define LINK_STATS 0 +// #define ETH_PAD_SIZE 2 +#define LWIP_CHKSUM_ALGORITHM 3 +#define LWIP_DHCP 1 +#define LWIP_IPV4 1 +#define LWIP_TCP 1 +#define LWIP_UDP 1 +#define LWIP_DNS 1 +#define LWIP_TCP_KEEPALIVE 1 +#define LWIP_NETIF_TX_SINGLE_PBUF 1 +#define DHCP_DOES_ARP_CHECK 0 +#define LWIP_DHCP_DOES_ACD_CHECK 0 + +#ifndef NDEBUG +#define LWIP_DEBUG 1 +#define LWIP_STATS 1 +#define LWIP_STATS_DISPLAY 1 +#endif + +#define ETHARP_DEBUG LWIP_DBG_OFF +#define NETIF_DEBUG LWIP_DBG_OFF +#define PBUF_DEBUG LWIP_DBG_OFF +#define API_LIB_DEBUG LWIP_DBG_OFF +#define API_MSG_DEBUG LWIP_DBG_OFF +#define SOCKETS_DEBUG LWIP_DBG_OFF +#define ICMP_DEBUG LWIP_DBG_OFF +#define INET_DEBUG LWIP_DBG_OFF +#define IP_DEBUG LWIP_DBG_OFF +#define IP_REASS_DEBUG LWIP_DBG_OFF +#define RAW_DEBUG LWIP_DBG_OFF +#define MEM_DEBUG LWIP_DBG_OFF +#define MEMP_DEBUG LWIP_DBG_OFF +#define SYS_DEBUG LWIP_DBG_OFF +#define TCP_DEBUG LWIP_DBG_OFF +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#define TCP_WND_DEBUG LWIP_DBG_OFF +#define TCP_FR_DEBUG LWIP_DBG_OFF +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#define TCP_RST_DEBUG LWIP_DBG_OFF +#define UDP_DEBUG LWIP_DBG_OFF +#define TCPIP_DEBUG LWIP_DBG_OFF +#define PPP_DEBUG LWIP_DBG_OFF +#define SLIP_DEBUG LWIP_DBG_OFF +#define DHCP_DEBUG LWIP_DBG_OFF + +#endif /* __LWIPOPTS_H__ */ diff --git a/SOFTWARE-FreeRTOS/Source/main.c b/SOFTWARE-FreeRTOS/Source/main.c new file mode 100644 index 0000000..24d0ad9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/main.c @@ -0,0 +1,86 @@ +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "EventGroupsDemo.h" +#include "IntSemTest.h" +#include "TaskNotify.h" + +#include "MAIN.h" +#include "lwipopts.h" +#include "common.h" + +#ifndef PICO_DEFAULT_LED_PIN + #warning pio/hello_pio example requires a board with a regular LED + #define PICO_DEFAULT_LED_PIN 25 +#endif + +void Led_Blinky(void *pvParameters) +{ + (void)pvParameters; + + const uint LED_PIN = PICO_DEFAULT_LED_PIN; + gpio_init(LED_PIN); + gpio_set_dir(LED_PIN, GPIO_OUT); + + _printTaskStackHighWaterMark(); + + while (1) { + vTaskDelay(pdMS_TO_TICKS(500)); + gpio_put(LED_PIN, 1); + + vTaskDelay(pdMS_TO_TICKS(500)); + gpio_put(LED_PIN, 0); + + _printTaskStackHighWaterMark(); + } +} + +void Read_Onboard_Temperature(void *pvParameters) +{ + (void)pvParameters; + + adc_init(); + adc_set_temp_sensor_enabled(true); + adc_select_input(4); // Input 4 is the onboard temperature sensor. + + //_printTaskStackHighWaterMark(); + + while (1) { + const float conversionFactor = 3.3f / (1 << 12); + + float adc = (float)adc_read() * conversionFactor; + float tempC = 27.0f - (adc - 0.706f) / 0.001721f; + + printf("Onboard temperature %.02f°C %.02f°F\n", tempC, (tempC * 9 / 5 + 32)); + + //_printTaskStackHighWaterMark(); + + vTaskDelay(pdMS_TO_TICKS(3000)); // 非阻塞延时 + } +} + +int main(void) +{ + stdio_init_all(); + sleep_ms(1000); + //set_sys_clock_khz(250000, true); + + BaseType_t xReturned; + TaskHandle_t Led_Blinky_xHandle = NULL; + + // 板载LED闪烁 + xReturned = xTaskCreate(Led_Blinky, "Blinky task", 512, NULL, tskIDLE_PRIORITY, &Led_Blinky_xHandle); + if (xReturned == errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY) + { + printf("Blinky Task Error!"); + } + + vTaskStartScheduler(); + + return 0; +} diff --git a/SOFTWARE-FreeRTOS/Source/main.h b/SOFTWARE-FreeRTOS/Source/main.h new file mode 100644 index 0000000..7371ea9 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/main.h @@ -0,0 +1,17 @@ +#ifndef MAIN_H +#define MAIN_H + +#include +#include +#include "pico/stdlib.h" +#include "hardware/gpio.h" +#include "hardware/clocks.h" +#include "hardware/watchdog.h" +#include "pico/multicore.h" +#include "hardware/i2c.h" +#include "pico/binary_info.h" +#include "hardware/uart.h" +#include "hardware/pwm.h" +#include "hardware/adc.h" + +#endif diff --git a/SOFTWARE-FreeRTOS/Source/uart_rx.pio b/SOFTWARE-FreeRTOS/Source/uart_rx.pio new file mode 100644 index 0000000..54a6577 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/uart_rx.pio @@ -0,0 +1,94 @@ +; +; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +; +; SPDX-License-Identifier: BSD-3-Clause +; + +.program uart_rx_mini + +; Minimum viable 8n1 UART receiver. Wait for the start bit, then sample 8 bits +; with the correct timing. +; IN pin 0 is mapped to the GPIO used as UART RX. +; Autopush must be enabled, with a threshold of 8. + + wait 0 pin 0 ; Wait for start bit + set x, 7 [10] ; Preload bit counter, delay until eye of first data bit +bitloop: ; Loop 8 times + in pins, 1 ; Sample data + jmp x-- bitloop [6] ; Each iteration is 8 cycles + +% c-sdk { +#include "hardware/clocks.h" +#include "hardware/gpio.h" + +static inline void uart_rx_mini_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) { + pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false); + pio_gpio_init(pio, pin); + gpio_pull_up(pin); + + pio_sm_config c = uart_rx_mini_program_get_default_config(offset); + sm_config_set_in_pins(&c, pin); // for WAIT, IN + // Shift to right, autopush enabled + sm_config_set_in_shift(&c, true, true, 8); + sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX); + // SM transmits 1 bit per 8 execution cycles. + float div = (float)clock_get_hz(clk_sys) / (8 * baud); + sm_config_set_clkdiv(&c, div); + + pio_sm_init(pio, sm, offset, &c); + pio_sm_set_enabled(pio, sm, true); +} +%} + +.program uart_rx + +; Slightly more fleshed-out 8n1 UART receiver which handles framing errors and +; break conditions more gracefully. +; IN pin 0 and JMP pin are both mapped to the GPIO used as UART RX. + +start: + wait 0 pin 0 ; Stall until start bit is asserted + set x, 7 [10] ; Preload bit counter, then delay until halfway through +bitloop: ; the first data bit (12 cycles incl wait, set). + in pins, 1 ; Shift data bit into ISR + jmp x-- bitloop [6] ; Loop 8 times, each loop iteration is 8 cycles + jmp pin good_stop ; Check stop bit (should be high) + + irq 4 rel ; Either a framing error or a break. Set a sticky flag, + wait 1 pin 0 ; and wait for line to return to idle state. + jmp start ; Don't push data if we didn't see good framing. + +good_stop: ; No delay before returning to start; a little slack is + push ; important in case the TX clock is slightly too fast. + + +% c-sdk { +static inline void uart_rx_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) { + pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false); + pio_gpio_init(pio, pin); + gpio_pull_up(pin); + + pio_sm_config c = uart_rx_program_get_default_config(offset); + sm_config_set_in_pins(&c, pin); // for WAIT, IN + sm_config_set_jmp_pin(&c, pin); // for JMP + // Shift to right, autopush disabled + sm_config_set_in_shift(&c, true, false, 32); + // Deeper FIFO as we're not doing any TX + sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX); + // SM transmits 1 bit per 8 execution cycles. + float div = (float)clock_get_hz(clk_sys) / (8 * baud); + sm_config_set_clkdiv(&c, div); + + pio_sm_init(pio, sm, offset, &c); + pio_sm_set_enabled(pio, sm, true); +} + +static inline char uart_rx_program_getc(PIO pio, uint sm) { + // 8-bit read from the uppermost byte of the FIFO, as data is left-justified + io_rw_8 *rxfifo_shift = (io_rw_8*)&pio->rxf[sm] + 3; + while (pio_sm_is_rx_fifo_empty(pio, sm)) + tight_loop_contents(); + return (char)*rxfifo_shift; +} + +%} diff --git a/SOFTWARE-FreeRTOS/Source/uart_tx.pio b/SOFTWARE-FreeRTOS/Source/uart_tx.pio new file mode 100644 index 0000000..b1320f6 --- /dev/null +++ b/SOFTWARE-FreeRTOS/Source/uart_tx.pio @@ -0,0 +1,61 @@ +; +; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +; +; SPDX-License-Identifier: BSD-3-Clause +; + +.program uart_tx +.side_set 1 opt + +; An 8n1 UART transmit program. +; OUT pin 0 and side-set pin 0 are both mapped to UART TX pin. + + pull side 1 [7] ; Assert stop bit, or stall with line in idle state + set x, 7 side 0 [7] ; Preload bit counter, assert start bit for 8 clocks +bitloop: ; This loop will run 8 times (8n1 UART) + out pins, 1 ; Shift 1 bit from OSR to the first OUT pin + jmp x-- bitloop [6] ; Each loop iteration is 8 cycles. + + +% c-sdk { +#include "hardware/clocks.h" + +static inline void uart_tx_program_init(PIO pio, uint sm, uint offset, uint pin_tx, uint baud) { + // Tell PIO to initially drive output-high on the selected pin, then map PIO + // onto that pin with the IO muxes. + pio_sm_set_pins_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx); + pio_sm_set_pindirs_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx); + pio_gpio_init(pio, pin_tx); + + pio_sm_config c = uart_tx_program_get_default_config(offset); + + // OUT shifts to right, no autopull + sm_config_set_out_shift(&c, true, false, 32); + + // We are mapping both OUT and side-set to the same pin, because sometimes + // we need to assert user data onto the pin (with OUT) and sometimes + // assert constant values (start/stop bit) + sm_config_set_out_pins(&c, pin_tx, 1); + sm_config_set_sideset_pins(&c, pin_tx); + + // We only need TX, so get an 8-deep FIFO! + sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); + + // SM transmits 1 bit per 8 execution cycles. + float div = (float)clock_get_hz(clk_sys) / (8 * baud); + sm_config_set_clkdiv(&c, div); + + pio_sm_init(pio, sm, offset, &c); + pio_sm_set_enabled(pio, sm, true); +} + +static inline void uart_tx_program_putc(PIO pio, uint sm, char c) { + pio_sm_put_blocking(pio, sm, (uint32_t)c); +} + +static inline void uart_tx_program_puts(PIO pio, uint sm, const char *s) { + while (*s) + uart_tx_program_putc(pio, sm, *s++); +} + +%} diff --git a/SOFTWARE-FreeRTOS/pico_extras_import.cmake b/SOFTWARE-FreeRTOS/pico_extras_import.cmake new file mode 100644 index 0000000..706add0 --- /dev/null +++ b/SOFTWARE-FreeRTOS/pico_extras_import.cmake @@ -0,0 +1,62 @@ +# This is a copy of /external/pico_extras_import.cmake + +# This can be dropped into an external project to help locate pico-extras +# It should be include()ed prior to project() + +if (DEFINED ENV{PICO_EXTRAS_PATH} AND (NOT PICO_EXTRAS_PATH)) + set(PICO_EXTRAS_PATH $ENV{PICO_EXTRAS_PATH}) + message("Using PICO_EXTRAS_PATH from environment ('${PICO_EXTRAS_PATH}')") +endif () + +if (DEFINED ENV{PICO_EXTRAS_FETCH_FROM_GIT} AND (NOT PICO_EXTRAS_FETCH_FROM_GIT)) + set(PICO_EXTRAS_FETCH_FROM_GIT $ENV{PICO_EXTRAS_FETCH_FROM_GIT}) + message("Using PICO_EXTRAS_FETCH_FROM_GIT from environment ('${PICO_EXTRAS_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_EXTRAS_FETCH_FROM_GIT_PATH} AND (NOT PICO_EXTRAS_FETCH_FROM_GIT_PATH)) + set(PICO_EXTRAS_FETCH_FROM_GIT_PATH $ENV{PICO_EXTRAS_FETCH_FROM_GIT_PATH}) + message("Using PICO_EXTRAS_FETCH_FROM_GIT_PATH from environment ('${PICO_EXTRAS_FETCH_FROM_GIT_PATH}')") +endif () + +if (NOT PICO_EXTRAS_PATH) + if (PICO_EXTRAS_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_EXTRAS_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_EXTRAS_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + PICO_EXTRAS + GIT_REPOSITORY https://github.com/raspberrypi/pico-extras + GIT_TAG master + ) + if (NOT PICO_EXTRAS) + message("Downloading PICO EXTRAS") + FetchContent_Populate(PICO_EXTRAS) + set(PICO_EXTRAS_PATH ${PICO_EXTRAS_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + if (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../pico-extras") + set(PICO_EXTRAS_PATH ${PICO_SDK_PATH}/../pico-extras) + message("Defaulting PICO_EXTRAS_PATH as sibling of PICO_SDK_PATH: ${PICO_EXTRAS_PATH}") + else() + message(FATAL_ERROR + "PICO EXTRAS location was not specified. Please set PICO_EXTRAS_PATH or set PICO_EXTRAS_FETCH_FROM_GIT to on to fetch from git." + ) + endif() + endif () +endif () + +set(PICO_EXTRAS_PATH "${PICO_EXTRAS_PATH}" CACHE PATH "Path to the PICO EXTRAS") +set(PICO_EXTRAS_FETCH_FROM_GIT "${PICO_EXTRAS_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of PICO EXTRAS from git if not otherwise locatable") +set(PICO_EXTRAS_FETCH_FROM_GIT_PATH "${PICO_EXTRAS_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download EXTRAS") + +get_filename_component(PICO_EXTRAS_PATH "${PICO_EXTRAS_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_EXTRAS_PATH}) + message(FATAL_ERROR "Directory '${PICO_EXTRAS_PATH}' not found") +endif () + +set(PICO_EXTRAS_PATH ${PICO_EXTRAS_PATH} CACHE PATH "Path to the PICO EXTRAS" FORCE) + +add_subdirectory(${PICO_EXTRAS_PATH} pico_extras) \ No newline at end of file diff --git a/SOFTWARE-FreeRTOS/pico_sdk_import.cmake b/SOFTWARE-FreeRTOS/pico_sdk_import.cmake new file mode 100644 index 0000000..e02a33e --- /dev/null +++ b/SOFTWARE-FreeRTOS/pico_sdk_import.cmake @@ -0,0 +1,62 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the PICO SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of PICO SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG master + ) + if (NOT pico_sdk) + message("Downloading PICO SDK") + FetchContent_Populate(pico_sdk) + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "PICO SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the PICO SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the PICO SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/SOFTWARE/CMakeLists.txt b/SOFTWARE/CMakeLists.txt new file mode 100644 index 0000000..529cb28 --- /dev/null +++ b/SOFTWARE/CMakeLists.txt @@ -0,0 +1,54 @@ +cmake_minimum_required(VERSION 3.25.1) +include(pico_sdk_import.cmake) +include(pico_extras_import.cmake) +project(Danger-alarm CXX C ASM) +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +pico_sdk_init() + + +add_subdirectory(Lib/pico-onewire) + +add_executable( + Danger-alarm +) + +pico_generate_pio_header(Danger-alarm ${CMAKE_CURRENT_LIST_DIR}/Source/uart_tx.pio) +pico_generate_pio_header(Danger-alarm ${CMAKE_CURRENT_LIST_DIR}/Source/uart_rx.pio) + +target_sources(Danger-alarm PRIVATE + lib/radio-switch.cc + ${CMAKE_CURRENT_LIST_DIR}/Source/common.c + ${CMAKE_CURRENT_LIST_DIR}/Source/MAIN.cpp + ${CMAKE_CURRENT_LIST_DIR}/Source/DTH11.cpp + ${CMAKE_CURRENT_LIST_DIR}/Source/HC-12.cpp + ${CMAKE_CURRENT_LIST_DIR}/Source/ZC13.cpp +) + +pico_enable_stdio_uart(Danger-alarm 1) +pico_enable_stdio_usb(Danger-alarm 1) +pico_add_extra_outputs(Danger-alarm) + +target_include_directories(Danger-alarm PRIVATE + ${CMAKE_CURRENT_LIST_DIR} + ${CMAKE_CURRENT_LIST_DIR}/Source + ${CMAKE_CURRENT_LIST_DIR}/lib + ) + +target_link_libraries( + Danger-alarm + pico_stdlib + pico_runtime + pico_multicore + pico_one_wire + hardware_sleep + hardware_rtc + hardware_i2c + hardware_uart + hardware_pwm + hardware_adc + hardware_pio + pico_lwip + pico_cyw43_arch + pico_cyw43_arch_lwip_poll +) diff --git a/SOFTWARE/Lib/radio-switch.cc b/SOFTWARE/Lib/radio-switch.cc new file mode 100644 index 0000000..01f9875 --- /dev/null +++ b/SOFTWARE/Lib/radio-switch.cc @@ -0,0 +1,728 @@ +/* + RCSwitch - Arduino libary for remote control outlet switches + Copyright (c) 2011 Suat Özgür. All right reserved. + + Contributors: + - Andre Koehler / info(at)tomate-online(dot)de + - Gordeev Andrey Vladimirovich / gordeev(at)openpyro(dot)com + - Skineffect / http://forum.ardumote.com/viewtopic.php?f=2&t=46 + - Dominik Fischer / dom_fischer(at)web(dot)de + - Frank Oltmanns / .(at)gmail(dot)com + - Andreas Steinel / A.(at)gmail(dot)com + - Max Horn / max(at)quendi(dot)de + - Robert ter Vehn / .(at)gmail(dot)com + - Johann Richard / .(at)gmail(dot)com + - Vlad Gheorghe / .(at)gmail(dot)com https://github.com/vgheo + - Matias Cuenca-Acuna + + Project home: https://github.com/sui77/rc-switch/ + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "radio-switch.h" +#include "pico/stdlib.h" +#include "hardware/gpio.h" +#include "hardware/uart.h" + +#ifdef _PICO_STDLIB_H +#define HIGH 1 +#define LOW 0 +#endif + + +#define PROGMEM +#define memcpy_P(dest, src, num) memcpy((dest), (src), (num)) + + +#if defined(ESP8266) + // interrupt handler and related code must be in RAM on ESP8266, + // according to issue #46. + #define RECEIVE_ATTR ICACHE_RAM_ATTR + #define VAR_ISR_ATTR +#elif defined(ESP32) + #define RECEIVE_ATTR IRAM_ATTR + #define VAR_ISR_ATTR DRAM_ATTR +#else + #define RECEIVE_ATTR + #define VAR_ISR_ATTR +#endif + +/* Format for protocol definitions: + * {pulselength, Sync bit, "0" bit, "1" bit, invertedSignal} + * + * pulselength: pulse length in microseconds, e.g. 350 + * Sync bit: {1, 31} means 1 high pulse and 31 low pulses + * (perceived as a 31*pulselength long pulse, total length of sync bit is + * 32*pulselength microseconds), i.e: + * _ + * | |_______________________________ (don't count the vertical bars) + * "0" bit: waveform for a data bit of value "0", {1, 3} means 1 high pulse + * and 3 low pulses, total length (1+3)*pulselength, i.e: + * _ + * | |___ + * "1" bit: waveform for a data bit of value "1", e.g. {3,1}: + * ___ + * | |_ + * + * These are combined to form Tri-State bits when sending or receiving codes. + */ +#if defined(ESP8266) || defined(ESP32) +static const VAR_ISR_ATTR RCSwitch::Protocol proto[] = { +#else +static const RCSwitch::Protocol PROGMEM proto[] = { +#endif + { 350, { 1, 31 }, { 1, 3 }, { 3, 1 }, false }, // protocol 1 + { 650, { 1, 10 }, { 1, 2 }, { 2, 1 }, false }, // protocol 2 + { 100, { 30, 71 }, { 4, 11 }, { 9, 6 }, false }, // protocol 3 + { 380, { 1, 6 }, { 1, 3 }, { 3, 1 }, false }, // protocol 4 + { 500, { 6, 14 }, { 1, 2 }, { 2, 1 }, false }, // protocol 5 + { 450, { 23, 1 }, { 1, 2 }, { 2, 1 }, true }, // protocol 6 (HT6P20B) + { 150, { 2, 62 }, { 1, 6 }, { 6, 1 }, false }, // protocol 7 (HS2303-PT, i. e. used in AUKEY Remote) + { 200, { 3, 130}, { 7, 16 }, { 3, 16}, false}, // protocol 8 Conrad RS-200 RX + { 200, { 130, 7 }, { 16, 7 }, { 16, 3 }, true}, // protocol 9 Conrad RS-200 TX + { 365, { 18, 1 }, { 3, 1 }, { 1, 3 }, true }, // protocol 10 (1ByOne Doorbell) + { 270, { 36, 1 }, { 1, 2 }, { 2, 1 }, true }, // protocol 11 (HT12E) + { 320, { 36, 1 }, { 1, 2 }, { 2, 1 }, true } // protocol 12 (SM5212) +}; + +void RCSwitch::gpio_callback(unsigned int gpio, uint32_t events) { + RCSwitch::handleInterrupt(); +} + +enum { + numProto = sizeof(proto) / sizeof(proto[0]) +}; + +#if not defined( RCSwitchDisableReceiving ) +volatile unsigned long RCSwitch::nReceivedValue = 0; +volatile unsigned int RCSwitch::nReceivedBitlength = 0; +volatile unsigned int RCSwitch::nReceivedDelay = 0; +volatile unsigned int RCSwitch::nReceivedProtocol = 0; +int RCSwitch::nReceiveTolerance = 60; +const unsigned int VAR_ISR_ATTR RCSwitch::nSeparationLimit = 4300; +// separationLimit: minimum microseconds between received codes, closer codes are ignored. +// according to discussion on issue #14 it might be more suitable to set the separation +// limit to the same time as the 'low' part of the sync signal for the current protocol. +unsigned int RCSwitch::timings[RCSWITCH_MAX_CHANGES]; +#endif + +RCSwitch::RCSwitch() { + this->nTransmitterPin = -1; + this->setRepeatTransmit(10); + this->setProtocol(1); + #if not defined( RCSwitchDisableReceiving ) + this->nReceiverInterrupt = -1; + this->setReceiveTolerance(60); + RCSwitch::nReceivedValue = 0; + #endif +} + +/** + * Sets the protocol to send. + */ +void RCSwitch::setProtocol(Protocol protocol) { + this->protocol = protocol; +} + +/** + * Sets the protocol to send, from a list of predefined protocols + */ +void RCSwitch::setProtocol(int nProtocol) { + if (nProtocol < 1 || nProtocol > numProto) { + nProtocol = 1; // TODO: trigger an error, e.g. "bad protocol" ??? + } +#if defined(ESP8266) || defined(ESP32) + this->protocol = proto[nProtocol-1]; +#else + memcpy_P(&this->protocol, &proto[nProtocol-1], sizeof(Protocol)); +#endif +} + +/** + * Sets the protocol to send with pulse length in microseconds. + */ +void RCSwitch::setProtocol(int nProtocol, int nPulseLength) { + setProtocol(nProtocol); + this->setPulseLength(nPulseLength); +} + + +/** + * Sets pulse length in microseconds + */ +void RCSwitch::setPulseLength(int nPulseLength) { + this->protocol.pulseLength = nPulseLength; +} + +/** + * Sets Repeat Transmits + */ +void RCSwitch::setRepeatTransmit(int nRepeatTransmit) { + this->nRepeatTransmit = nRepeatTransmit; +} + +/** + * Set Receiving Tolerance + */ +#if not defined( RCSwitchDisableReceiving ) +void RCSwitch::setReceiveTolerance(int nPercent) { + RCSwitch::nReceiveTolerance = nPercent; +} +#endif + + +/** + * Enable transmissions + * + * @param nTransmitterPin Arduino Pin to which the sender is connected to + */ +void RCSwitch::enableTransmit(int nTransmitterPin) { + this->nTransmitterPin = nTransmitterPin; + // pinMode(this->nTransmitterPin, OUTPUT); + gpio_set_dir(this->nTransmitterPin,GPIO_OUT); +} + +/** + * Disable transmissions + */ +void RCSwitch::disableTransmit() { + this->nTransmitterPin = -1; +} + +/** + * Switch a remote switch on (Type D REV) + * + * @param sGroup Code of the switch group (A,B,C,D) + * @param nDevice Number of the switch itself (1..3) + */ +void RCSwitch::switchOn(char sGroup, int nDevice) { + this->sendTriState( this->getCodeWordD(sGroup, nDevice, true) ); +} + +/** + * Switch a remote switch off (Type D REV) + * + * @param sGroup Code of the switch group (A,B,C,D) + * @param nDevice Number of the switch itself (1..3) + */ +void RCSwitch::switchOff(char sGroup, int nDevice) { + this->sendTriState( this->getCodeWordD(sGroup, nDevice, false) ); +} + +/** + * Switch a remote switch on (Type C Intertechno) + * + * @param sFamily Familycode (a..f) + * @param nGroup Number of group (1..4) + * @param nDevice Number of device (1..4) + */ +void RCSwitch::switchOn(char sFamily, int nGroup, int nDevice) { + this->sendTriState( this->getCodeWordC(sFamily, nGroup, nDevice, true) ); +} + +/** + * Switch a remote switch off (Type C Intertechno) + * + * @param sFamily Familycode (a..f) + * @param nGroup Number of group (1..4) + * @param nDevice Number of device (1..4) + */ +void RCSwitch::switchOff(char sFamily, int nGroup, int nDevice) { + this->sendTriState( this->getCodeWordC(sFamily, nGroup, nDevice, false) ); +} + +/** + * Switch a remote switch on (Type B with two rotary/sliding switches) + * + * @param nAddressCode Number of the switch group (1..4) + * @param nChannelCode Number of the switch itself (1..4) + */ +void RCSwitch::switchOn(int nAddressCode, int nChannelCode) { + this->sendTriState( this->getCodeWordB(nAddressCode, nChannelCode, true) ); +} + +/** + * Switch a remote switch off (Type B with two rotary/sliding switches) + * + * @param nAddressCode Number of the switch group (1..4) + * @param nChannelCode Number of the switch itself (1..4) + */ +void RCSwitch::switchOff(int nAddressCode, int nChannelCode) { + this->sendTriState( this->getCodeWordB(nAddressCode, nChannelCode, false) ); +} + +/** + * Deprecated, use switchOn(const char* sGroup, const char* sDevice) instead! + * Switch a remote switch on (Type A with 10 pole DIP switches) + * + * @param sGroup Code of the switch group (refers to DIP switches 1..5 where "1" = on and "0" = off, if all DIP switches are on it's "11111") + * @param nChannelCode Number of the switch itself (1..5) + */ +void RCSwitch::switchOn(const char* sGroup, int nChannel) { + const char* code[6] = { "00000", "10000", "01000", "00100", "00010", "00001" }; + this->switchOn(sGroup, code[nChannel]); +} + +/** + * Deprecated, use switchOff(const char* sGroup, const char* sDevice) instead! + * Switch a remote switch off (Type A with 10 pole DIP switches) + * + * @param sGroup Code of the switch group (refers to DIP switches 1..5 where "1" = on and "0" = off, if all DIP switches are on it's "11111") + * @param nChannelCode Number of the switch itself (1..5) + */ +void RCSwitch::switchOff(const char* sGroup, int nChannel) { + const char* code[6] = { "00000", "10000", "01000", "00100", "00010", "00001" }; + this->switchOff(sGroup, code[nChannel]); +} + +/** + * Switch a remote switch on (Type A with 10 pole DIP switches) + * + * @param sGroup Code of the switch group (refers to DIP switches 1..5 where "1" = on and "0" = off, if all DIP switches are on it's "11111") + * @param sDevice Code of the switch device (refers to DIP switches 6..10 (A..E) where "1" = on and "0" = off, if all DIP switches are on it's "11111") + */ +void RCSwitch::switchOn(const char* sGroup, const char* sDevice) { + this->sendTriState( this->getCodeWordA(sGroup, sDevice, true) ); +} + +/** + * Switch a remote switch off (Type A with 10 pole DIP switches) + * + * @param sGroup Code of the switch group (refers to DIP switches 1..5 where "1" = on and "0" = off, if all DIP switches are on it's "11111") + * @param sDevice Code of the switch device (refers to DIP switches 6..10 (A..E) where "1" = on and "0" = off, if all DIP switches are on it's "11111") + */ +void RCSwitch::switchOff(const char* sGroup, const char* sDevice) { + this->sendTriState( this->getCodeWordA(sGroup, sDevice, false) ); +} + + +/** + * Returns a char[13], representing the code word to be send. + * + */ +char* RCSwitch::getCodeWordA(const char* sGroup, const char* sDevice, bool bStatus) { + static char sReturn[13]; + int nReturnPos = 0; + + for (int i = 0; i < 5; i++) { + sReturn[nReturnPos++] = (sGroup[i] == '0') ? 'F' : '0'; + } + + for (int i = 0; i < 5; i++) { + sReturn[nReturnPos++] = (sDevice[i] == '0') ? 'F' : '0'; + } + + sReturn[nReturnPos++] = bStatus ? '0' : 'F'; + sReturn[nReturnPos++] = bStatus ? 'F' : '0'; + + sReturn[nReturnPos] = '\0'; + return sReturn; +} + +/** + * Encoding for type B switches with two rotary/sliding switches. + * + * The code word is a tristate word and with following bit pattern: + * + * +-----------------------------+-----------------------------+----------+------------+ + * | 4 bits address | 4 bits address | 3 bits | 1 bit | + * | switch group | switch number | not used | on / off | + * | 1=0FFF 2=F0FF 3=FF0F 4=FFF0 | 1=0FFF 2=F0FF 3=FF0F 4=FFF0 | FFF | on=F off=0 | + * +-----------------------------+-----------------------------+----------+------------+ + * + * @param nAddressCode Number of the switch group (1..4) + * @param nChannelCode Number of the switch itself (1..4) + * @param bStatus Whether to switch on (true) or off (false) + * + * @return char[13], representing a tristate code word of length 12 + */ +char* RCSwitch::getCodeWordB(int nAddressCode, int nChannelCode, bool bStatus) { + static char sReturn[13]; + int nReturnPos = 0; + + if (nAddressCode < 1 || nAddressCode > 4 || nChannelCode < 1 || nChannelCode > 4) { + return 0; + } + + for (int i = 1; i <= 4; i++) { + sReturn[nReturnPos++] = (nAddressCode == i) ? '0' : 'F'; + } + + for (int i = 1; i <= 4; i++) { + sReturn[nReturnPos++] = (nChannelCode == i) ? '0' : 'F'; + } + + sReturn[nReturnPos++] = 'F'; + sReturn[nReturnPos++] = 'F'; + sReturn[nReturnPos++] = 'F'; + + sReturn[nReturnPos++] = bStatus ? 'F' : '0'; + + sReturn[nReturnPos] = '\0'; + return sReturn; +} + +/** + * Like getCodeWord (Type C = Intertechno) + */ +char* RCSwitch::getCodeWordC(char sFamily, int nGroup, int nDevice, bool bStatus) { + static char sReturn[13]; + int nReturnPos = 0; + + int nFamily = (int)sFamily - 'a'; + if ( nFamily < 0 || nFamily > 15 || nGroup < 1 || nGroup > 4 || nDevice < 1 || nDevice > 4) { + return 0; + } + + // encode the family into four bits + sReturn[nReturnPos++] = (nFamily & 1) ? 'F' : '0'; + sReturn[nReturnPos++] = (nFamily & 2) ? 'F' : '0'; + sReturn[nReturnPos++] = (nFamily & 4) ? 'F' : '0'; + sReturn[nReturnPos++] = (nFamily & 8) ? 'F' : '0'; + + // encode the device and group + sReturn[nReturnPos++] = ((nDevice-1) & 1) ? 'F' : '0'; + sReturn[nReturnPos++] = ((nDevice-1) & 2) ? 'F' : '0'; + sReturn[nReturnPos++] = ((nGroup-1) & 1) ? 'F' : '0'; + sReturn[nReturnPos++] = ((nGroup-1) & 2) ? 'F' : '0'; + + // encode the status code + sReturn[nReturnPos++] = '0'; + sReturn[nReturnPos++] = 'F'; + sReturn[nReturnPos++] = 'F'; + sReturn[nReturnPos++] = bStatus ? 'F' : '0'; + + sReturn[nReturnPos] = '\0'; + return sReturn; +} + +/** + * Encoding for the REV Switch Type + * + * The code word is a tristate word and with following bit pattern: + * + * +-----------------------------+-------------------+----------+--------------+ + * | 4 bits address | 3 bits address | 3 bits | 2 bits | + * | switch group | device number | not used | on / off | + * | A=1FFF B=F1FF C=FF1F D=FFF1 | 1=0FF 2=F0F 3=FF0 | 000 | on=10 off=01 | + * +-----------------------------+-------------------+----------+--------------+ + * + * Source: http://www.the-intruder.net/funksteckdosen-von-rev-uber-arduino-ansteuern/ + * + * @param sGroup Name of the switch group (A..D, resp. a..d) + * @param nDevice Number of the switch itself (1..3) + * @param bStatus Whether to switch on (true) or off (false) + * + * @return char[13], representing a tristate code word of length 12 + */ +char* RCSwitch::getCodeWordD(char sGroup, int nDevice, bool bStatus) { + static char sReturn[13]; + int nReturnPos = 0; + + // sGroup must be one of the letters in "abcdABCD" + int nGroup = (sGroup >= 'a') ? (int)sGroup - 'a' : (int)sGroup - 'A'; + if ( nGroup < 0 || nGroup > 3 || nDevice < 1 || nDevice > 3) { + return 0; + } + + for (int i = 0; i < 4; i++) { + sReturn[nReturnPos++] = (nGroup == i) ? '1' : 'F'; + } + + for (int i = 1; i <= 3; i++) { + sReturn[nReturnPos++] = (nDevice == i) ? '1' : 'F'; + } + + sReturn[nReturnPos++] = '0'; + sReturn[nReturnPos++] = '0'; + sReturn[nReturnPos++] = '0'; + + sReturn[nReturnPos++] = bStatus ? '1' : '0'; + sReturn[nReturnPos++] = bStatus ? '0' : '1'; + + sReturn[nReturnPos] = '\0'; + return sReturn; +} + +/** + * @param sCodeWord a tristate code word consisting of the letter 0, 1, F + */ +void RCSwitch::sendTriState(const char* sCodeWord) { + // turn the tristate code word into the corresponding bit pattern, then send it + unsigned long code = 0; + unsigned int length = 0; + for (const char* p = sCodeWord; *p; p++) { + code <<= 2L; + switch (*p) { + case '0': + // bit pattern 00 + break; + case 'F': + // bit pattern 01 + code |= 1L; + break; + case '1': + // bit pattern 11 + code |= 3L; + break; + } + length += 2; + } + this->send(code, length); +} + +/** + * @param sCodeWord a binary code word consisting of the letter 0, 1 + */ +void RCSwitch::send(const char* sCodeWord) { + // turn the tristate code word into the corresponding bit pattern, then send it + unsigned long code = 0; + unsigned int length = 0; + for (const char* p = sCodeWord; *p; p++) { + code <<= 1L; + if (*p != '0') + code |= 1L; + length++; + } + this->send(code, length); +} + +/** + * Transmit the first 'length' bits of the integer 'code'. The + * bits are sent from MSB to LSB, i.e., first the bit at position length-1, + * then the bit at position length-2, and so on, till finally the bit at position 0. + */ +void RCSwitch::send(unsigned long code, unsigned int length) { + if (this->nTransmitterPin == -1) + return; + +#if not defined( RCSwitchDisableReceiving ) + // make sure the receiver is disabled while we transmit + int nReceiverInterrupt_backup = nReceiverInterrupt; + if (nReceiverInterrupt_backup != -1) { + this->disableReceive(); + } +#endif + + for (int nRepeat = 0; nRepeat < nRepeatTransmit; nRepeat++) { + for (int i = length-1; i >= 0; i--) { + if (code & (1L << i)) + this->transmit(protocol.one); + else + this->transmit(protocol.zero); + } + this->transmit(protocol.syncFactor); + } + + // Disable transmit after sending (i.e., for inverted protocols) + // digitalWrite(this->nTransmitterPin, LOW); + gpio_put(this->nTransmitterPin, LOW); + +#if not defined( RCSwitchDisableReceiving ) + // enable receiver again if we just disabled it + if (nReceiverInterrupt_backup != -1) { + this->enableReceive(nReceiverInterrupt_backup); + } +#endif +} + +/** + * Transmit a single high-low pulse. + */ +void RCSwitch::transmit(HighLow pulses) { + uint8_t firstLogicLevel = (this->protocol.invertedSignal) ? LOW : HIGH; + uint8_t secondLogicLevel = (this->protocol.invertedSignal) ? HIGH : LOW; + + // digitalWrite(this->nTransmitterPin, firstLogicLevel); + // delayMicroseconds( this->protocol.pulseLength * pulses.high); + // digitalWrite(this->nTransmitterPin, secondLogicLevel); + // delayMicroseconds( this->protocol.pulseLength * pulses.low); + gpio_put(this->nTransmitterPin, firstLogicLevel); + sleep_us(this->protocol.pulseLength * pulses.high); + gpio_put(this->nTransmitterPin, secondLogicLevel); + sleep_us(this->protocol.pulseLength * pulses.low); +} + + +#if not defined( RCSwitchDisableReceiving ) +/** + * Enable receiving data + */ +void RCSwitch::enableReceive(int interrupt) { + this->nReceiverInterrupt = interrupt; + this->enableReceive(); +} + +void RCSwitch::enableReceive() { + if (this->nReceiverInterrupt != -1) { + RCSwitch::nReceivedValue = 0; + RCSwitch::nReceivedBitlength = 0; + gpio_set_irq_enabled_with_callback(this->nReceiverInterrupt, GPIO_IRQ_EDGE_RISE | GPIO_IRQ_EDGE_FALL, true, &gpio_callback); + // attachInterrupt(this->nReceiverInterrupt, handleInterrupt, CHANGE); + + + } +} + +/** + * Disable receiving data + */ +void RCSwitch::disableReceive() { +#if not defined(RaspberryPi) // Arduino + // detachInterrupt(this->nReceiverInterrupt); +#endif // For Raspberry Pi (wiringPi) you can't unregister the ISR + this->nReceiverInterrupt = -1; +} + +bool RCSwitch::available() { + return RCSwitch::nReceivedValue != 0; +} + +void RCSwitch::resetAvailable() { + RCSwitch::nReceivedValue = 0; +} + +unsigned long RCSwitch::getReceivedValue() { + return RCSwitch::nReceivedValue; +} + +unsigned int RCSwitch::getReceivedBitlength() { + return RCSwitch::nReceivedBitlength; +} + +unsigned int RCSwitch::getReceivedDelay() { + return RCSwitch::nReceivedDelay; +} + +unsigned int RCSwitch::getReceivedProtocol() { + return RCSwitch::nReceivedProtocol; +} + +unsigned int* RCSwitch::getReceivedRawdata() { + return RCSwitch::timings; +} + +/* helper function for the receiveProtocol method */ +static inline unsigned int diff(int A, int B) { + return abs(A - B); +} + +/** + * + */ +bool RECEIVE_ATTR RCSwitch::receiveProtocol(const int p, unsigned int changeCount) { +#if defined(ESP8266) || defined(ESP32) + const Protocol &pro = proto[p-1]; +#else + Protocol pro; + memcpy_P(&pro, &proto[p-1], sizeof(Protocol)); +#endif + + unsigned long code = 0; + //Assuming the longer pulse length is the pulse captured in timings[0] + const unsigned int syncLengthInPulses = ((pro.syncFactor.low) > (pro.syncFactor.high)) ? (pro.syncFactor.low) : (pro.syncFactor.high); + const unsigned int delay = RCSwitch::timings[0] / syncLengthInPulses; + const unsigned int delayTolerance = delay * RCSwitch::nReceiveTolerance / 100; + + /* For protocols that start low, the sync period looks like + * _________ + * _____________| |XXXXXXXXXXXX| + * + * |--1st dur--|-2nd dur-|-Start data-| + * + * The 3rd saved duration starts the data. + * + * For protocols that start high, the sync period looks like + * + * ______________ + * | |____________|XXXXXXXXXXXXX| + * + * |-filtered out-|--1st dur--|--Start data--| + * + * The 2nd saved duration starts the data + */ + const unsigned int firstDataTiming = (pro.invertedSignal) ? (2) : (1); + + for (unsigned int i = firstDataTiming; i < changeCount - 1; i += 2) { + code <<= 1; + if (diff(RCSwitch::timings[i], delay * pro.zero.high) < delayTolerance && + diff(RCSwitch::timings[i + 1], delay * pro.zero.low) < delayTolerance) { + // zero + } else if (diff(RCSwitch::timings[i], delay * pro.one.high) < delayTolerance && + diff(RCSwitch::timings[i + 1], delay * pro.one.low) < delayTolerance) { + // one + code |= 1; + } else { + // Failed + return false; + } + } + + if (changeCount > 7) { // ignore very short transmissions: no device sends them, so this must be noise + RCSwitch::nReceivedValue = code; + RCSwitch::nReceivedBitlength = (changeCount - 1) / 2; + RCSwitch::nReceivedDelay = delay; + RCSwitch::nReceivedProtocol = p; + return true; + } + + return false; +} + + + +void RECEIVE_ATTR RCSwitch::handleInterrupt() { + + static unsigned int changeCount = 0; + static unsigned long lastTime = 0; + static unsigned int repeatCount = 0; + + // const long time = micros(); + const long time = to_us_since_boot(get_absolute_time()); + const unsigned int duration = time - lastTime; + + if (duration > RCSwitch::nSeparationLimit) { + + // A long stretch without signal level change occurred. This could + // be the gap between two transmission. + if ((repeatCount==0) || (diff(duration, RCSwitch::timings[0]) < 200)) { + + // This long signal is close in length to the long signal which + // started the previously recorded timings; this suggests that + // it may indeed by a a gap between two transmissions (we assume + // here that a sender will send the signal multiple times, + // with roughly the same gap between them). + repeatCount++; + if (repeatCount == 2) { + for(unsigned int i = 1; i <= numProto; i++) { + if (receiveProtocol(i, changeCount)) { + // receive succeeded for protocol i + break; + } + } + repeatCount = 0; + } + } + changeCount = 0; + } + + // detect overflow + if (changeCount >= RCSWITCH_MAX_CHANGES) { + changeCount = 0; + repeatCount = 0; + } + + RCSwitch::timings[changeCount++] = duration; + lastTime = time; +} +#endif diff --git a/SOFTWARE/Lib/radio-switch.h b/SOFTWARE/Lib/radio-switch.h new file mode 100644 index 0000000..24d72a1 --- /dev/null +++ b/SOFTWARE/Lib/radio-switch.h @@ -0,0 +1,170 @@ +/* + RCSwitch - Arduino libary for remote control outlet switches + Copyright (c) 2011 Suat Özgür. All right reserved. + + Contributors: + - Andre Koehler / info(at)tomate-online(dot)de + - Gordeev Andrey Vladimirovich / gordeev(at)openpyro(dot)com + - Skineffect / http://forum.ardumote.com/viewtopic.php?f=2&t=46 + - Dominik Fischer / dom_fischer(at)web(dot)de + - Frank Oltmanns / .(at)gmail(dot)com + - Max Horn / max(at)quendi(dot)de + - Robert ter Vehn / .(at)gmail(dot)com + + Project home: https://github.com/sui77/rc-switch/ + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#ifndef _RCSwitch_h +#define _RCSwitch_h + + +// #define RaspberryPi + +// Include libraries for RPi: +#include /* memcpy */ +#include /* abs */ + + + +#include + +// Number of maximum high/Low changes per packet. +// We can handle up to (unsigned long) => 32 bit * 2 H/L changes per bit + 2 for sync +#define RCSWITCH_MAX_CHANGES 67 + +class RCSwitch { + + public: + RCSwitch(); + + void switchOn(int nGroupNumber, int nSwitchNumber); + void switchOff(int nGroupNumber, int nSwitchNumber); + void switchOn(const char* sGroup, int nSwitchNumber); + void switchOff(const char* sGroup, int nSwitchNumber); + void switchOn(char sFamily, int nGroup, int nDevice); + void switchOff(char sFamily, int nGroup, int nDevice); + void switchOn(const char* sGroup, const char* sDevice); + void switchOff(const char* sGroup, const char* sDevice); + void switchOn(char sGroup, int nDevice); + void switchOff(char sGroup, int nDevice); + + void sendTriState(const char* sCodeWord); + void send(unsigned long code, unsigned int length); + void send(const char* sCodeWord); + + #if not defined( RCSwitchDisableReceiving ) + void enableReceive(int interrupt); + void enableReceive(); + void disableReceive(); + bool available(); + void resetAvailable(); + + unsigned long getReceivedValue(); + unsigned int getReceivedBitlength(); + unsigned int getReceivedDelay(); + unsigned int getReceivedProtocol(); + unsigned int* getReceivedRawdata(); + #endif + + void enableTransmit(int nTransmitterPin); + void disableTransmit(); + void setPulseLength(int nPulseLength); + void setRepeatTransmit(int nRepeatTransmit); + #if not defined( RCSwitchDisableReceiving ) + void setReceiveTolerance(int nPercent); + #endif + + /** + * Description of a single pule, which consists of a high signal + * whose duration is "high" times the base pulse length, followed + * by a low signal lasting "low" times the base pulse length. + * Thus, the pulse overall lasts (high+low)*pulseLength + */ + struct HighLow { + uint8_t high; + uint8_t low; + }; + + /** + * A "protocol" describes how zero and one bits are encoded into high/low + * pulses. + */ + struct Protocol { + /** base pulse length in microseconds, e.g. 350 */ + uint16_t pulseLength; + + HighLow syncFactor; + HighLow zero; + HighLow one; + + /** + * If true, interchange high and low logic levels in all transmissions. + * + * By default, RCSwitch assumes that any signals it sends or receives + * can be broken down into pulses which start with a high signal level, + * followed by a a low signal level. This is e.g. the case for the + * popular PT 2260 encoder chip, and thus many switches out there. + * + * But some devices do it the other way around, and start with a low + * signal level, followed by a high signal level, e.g. the HT6P20B. To + * accommodate this, one can set invertedSignal to true, which causes + * RCSwitch to change how it interprets any HighLow struct FOO: It will + * then assume transmissions start with a low signal lasting + * FOO.high*pulseLength microseconds, followed by a high signal lasting + * FOO.low*pulseLength microseconds. + */ + bool invertedSignal; + }; + + void setProtocol(Protocol protocol); + void setProtocol(int nProtocol); + void setProtocol(int nProtocol, int nPulseLength); + + private: + static void gpio_callback(unsigned int gpio, uint32_t events); + char* getCodeWordA(const char* sGroup, const char* sDevice, bool bStatus); + char* getCodeWordB(int nGroupNumber, int nSwitchNumber, bool bStatus); + char* getCodeWordC(char sFamily, int nGroup, int nDevice, bool bStatus); + char* getCodeWordD(char group, int nDevice, bool bStatus); + void transmit(HighLow pulses); + + #if not defined( RCSwitchDisableReceiving ) + static void handleInterrupt(); + static bool receiveProtocol(const int p, unsigned int changeCount); + int nReceiverInterrupt; + #endif + int nTransmitterPin; + int nRepeatTransmit; + + Protocol protocol; + + #if not defined( RCSwitchDisableReceiving ) + static int nReceiveTolerance; + volatile static unsigned long nReceivedValue; + volatile static unsigned int nReceivedBitlength; + volatile static unsigned int nReceivedDelay; + volatile static unsigned int nReceivedProtocol; + const static unsigned int nSeparationLimit; + /* + * timings[0] contains sync timing, followed by a number of bits + */ + static unsigned int timings[RCSWITCH_MAX_CHANGES]; + #endif + + +}; + +#endif diff --git a/SOFTWARE/Server/hc-12/Makefile b/SOFTWARE/Server/hc-12/Makefile new file mode 100644 index 0000000..315fe5f --- /dev/null +++ b/SOFTWARE/Server/hc-12/Makefile @@ -0,0 +1,21 @@ +CROSS_COMPILE ?= +CC = $(CROSS_COMPILE)gcc +STRIP := $(CROSS_COMPILE)strip +AR := $(CROSS_COMPILE)ar +CFLAGS += -g -Wall -Os +LDFLAGS += -lwiringPi + +MYSQL_LIB := $(shell mysql_config --libs) +MYSQL_CFLAGS := $(shell mysql_config --cflags) +OBJ = hc-12 + +all: hc-12 + +hc-12: hc-12.o ../libconf/libconf.o mysql.o + $(CC) $(CFLAGS) $(MYSQL_CFLAGS) -o $(OBJ) $^ $(MYSQL_LIB) $(LDFLAGS) +.c.o: + $(CC) $(CFLAGS) $(MYSQL_CFLAGS) -c $< $@ + +clean: + rm hc-12 hc-12.o ../libconf/libconf.o mysql.o + diff --git a/SOFTWARE/Server/hc-12/hc-12 b/SOFTWARE/Server/hc-12/hc-12 new file mode 100644 index 0000000..16034d0 Binary files /dev/null and b/SOFTWARE/Server/hc-12/hc-12 differ diff --git a/SOFTWARE/Server/hc-12/hc-12.c b/SOFTWARE/Server/hc-12/hc-12.c new file mode 100644 index 0000000..7098a8b --- /dev/null +++ b/SOFTWARE/Server/hc-12/hc-12.c @@ -0,0 +1,385 @@ +#include "hc-12.h" +#include "mysql.h" + +pthread_mutex_t mutex; + +void *pull_data_mysql(void *p) +{ + char sql_insert[1024] = { 0 }; + time_t current_time; + struct tm *time_info; + char timeString[20]; + static int r = 0; + + Thread *args = (Thread *) p; + + if (args->data->co >= 0 && args->data->co2 >= 0 && args->data->ch4_ >= 0) { + time(¤t_time); // 获取当前时间 + time_info = localtime(¤t_time); // 将时间转换为本地时间 + strftime(timeString, sizeof(timeString), "%Y-%m-%d %H:%M:%S", time_info); // 格式化时间字符串 + + sprintf(sql_insert, "INSERT INTO %s (TIME, CO, CO2, CH4, TEMPERATURE, RP2040_TEMPERATURE) VALUES ('%s', '%.0fppm', '%.0fppm', '%.0fppm', '%.3f°C', '%.02f°C');", + args->conf->MYSQL_TABLES, timeString, args->data->co, args->data->co2, args->data->ch4_, args->data->ds18b20, args->data->rp2040); + printf("%s\n", sql_insert); + + r = _mysql(sql_insert, args->conf->MYSQL_HOST, args->conf->MYSQL_PORT_, args->conf->MYSQL_USRT, args->conf->MYSQL_PASSWORD, args->conf->MYSQL_DB, args->conf->MYSQL_TABLES); + if (r == -1) { + perror("_mysql"); + } + } + + return NULL; +} + +int send_mail(char *mail, const char *string, CONF *conf, DATA *data) +{ + static char *buff; + const char *subject = "厨房危险(火灾)报警!!!"; + + buff = (char *)alloca(BUFFER * 10); + if (buff == NULL) + perror("out of memory."); + + sprintf(buff, MAIL, mail, subject, string); + printf("%s\n", buff); + system(buff); + + return 0; +} + +void *createSharedMemory(int key, size_t size) +{ + static int shm_id; + static void *shared_memory; + + shm_id = shmget(key, size, IPC_CREAT | 0666); + if (shm_id == -1) { + perror("shmget"); + exit(1); + } + + shared_memory = shmat(shm_id, NULL, 0); + if (shared_memory == (void *)-1) { + perror("shmat"); + exit(1); + } + + return shared_memory; +} + +void detachAndDeleteSharedMemory(int key, void *shared_memory) +{ + static int shm_id; + + if (shmdt(shared_memory) == -1) { + perror("shmdt"); + exit(1); + } + + shm_id = shmget(key, 0, 0); + if (shmctl(shm_id, IPC_RMID, NULL) == -1) { + perror("shmctl"); + exit(1); + } +} + +int loop(int fd, CONF *conf, DATA *DATA) +{ + static char receivedString[BUFFER]; + static int index = 0; + static int timing = 0; + + DATA->ds18b20_shm = (int *)createSharedMemory(1, sizeof(int)); + DATA->co_shm = (int *)createSharedMemory(2, sizeof(int)); + DATA->co2_shm = (int *)createSharedMemory(3, sizeof(int)); + *DATA->ds18b20_shm = 0; + *DATA->co_shm = 0; + *DATA->co2_shm = 0; + + pid_t pid = fork(); + if (pid < 0) { + perror("fork"); + exit(1); + } + + if (pid == 0) // 子进程 + { + int conut = 0; + + while (1) { + + pthread_mutex_lock(&mutex); // 加锁 + if (conut >= DATA->_time) { + *DATA->ds18b20_shm = 1; + *DATA->co_shm = 1; + *DATA->co2_shm = 1; + + conut = 0; + } + pthread_mutex_unlock(&mutex); // 解锁 + + conut++; + sleep(1); + } + + } else // 父进程 + { + while (1) { + if (serialDataAvail(fd)) { + // 串口有数据可读 + char data = serialGetchar(fd); + if (data != '\n') { + // 如果接收到的不是回车符，则添加到接收字符串中 + receivedString[index] = data; + index++; + // 检查是否超出数组长度，如果超出则重置索引 + if (index >= BUFFER) { + index = 0; + } + } else { + // 如果接收到回车符，则打印接收到的字符串，并清空接收字符串和索引 + receivedString[index] = '\0'; // 添加字符串结束符 + if (index > 0) { + + // RP2040 + if (strstr(receivedString, "Onboard")) { + + if (2 == (sscanf(receivedString, "Onboard temperature %f°C %f°F\n", &(DATA->rp2040), &(DATA->rp2040_f)))) { + DATA->rp2040_num++; + printf("Onboard temperature %.02f°C %.02f°F\n", DATA->rp2040, DATA->rp2040_f); + } + + } + // DS18B20 + if (strstr(receivedString, "Temperature")) { + + if (1 == (sscanf(receivedString, "Temperature: %f°C\n", &DATA->ds18b20))) { + printf("Temperature: %.3f°C\n", DATA->ds18b20); + + if (DATA->ds18b20 >= atoi(conf->temperature)) { + DATA->ds18b20_num++; + printf("请注意室内温度%.3f°C超过%d次!\n", DATA->ds18b20, DATA->ds18b20_num); + + if (DATA->ds18b20_num >= 3) { + // 第一次发送 + if (DATA->ds18b20_1st == 1) { + DATA->ds18b20_1st = 0; + send_mail(conf->mail, receivedString, conf, DATA); + } + // 如果浓度持续一段时间, (降低发送频率, 若干秒后再次发送) + pthread_mutex_lock(&mutex); // 加锁 + if (*DATA->ds18b20_shm == 1) { + send_mail(conf->mail, receivedString, conf, DATA); + *DATA->ds18b20_shm = 0; + } + pthread_mutex_unlock(&mutex); // 解锁 + + DATA->ds18b20_num = 0; + } + + } + + } + + } + // CH4 + if (strstr(receivedString, "CH4 Concentration")) { + if (1 == (sscanf(receivedString, "CH4 Concentration: %f\n", &DATA->ch4_))) { + printf("CH4 Concentration: %.0F ppm\n", DATA->ch4_); + } + + } + // CO + if (strstr(receivedString, "CO")) { + + if (1 == (sscanf(receivedString, "CO Concentration: %f ppm", &DATA->co))) { + printf("CO Concentration: %.2f ppm\n", DATA->co); + + if (DATA->co >= atoi(conf->co)) { + DATA->co_num++; + printf("请注意室内CO浓度%.3f°C超过%d次!\n", DATA->co, DATA->co_num); + + if (DATA->co_num >= 3) { + if (DATA->co_1st == 1) { + DATA->co_1st = 0; + send_mail(conf->mail, receivedString, conf, DATA); + } + pthread_mutex_lock(&mutex); + if (*DATA->co_shm == 1) { + send_mail(conf->mail, receivedString, conf, DATA); + *DATA->co_shm = 0; + } + pthread_mutex_unlock(&mutex); + + DATA->co_num = 0; + } + + } + } + } + // CO2 + if (strstr(receivedString, "CO2")) { + + if (1 == (sscanf(receivedString, "CO2 Concentration: %f ppm", &DATA->co2))) { + printf("CO2 Concentration: %.2f ppm\n", DATA->co2); + + if (DATA->co2 >= atoi(conf->co2)) { + DATA->co2_num++; + printf("请注意室内CO2浓度%.3f°C超过%d次!\n", DATA->co2, DATA->co2_num); + + if (DATA->co2_num >= 3) { + if (DATA->co2_1st == 1) { + DATA->co2_1st = 0; + send_mail(conf->mail, receivedString, conf, DATA); + } + pthread_mutex_lock(&mutex); + if (*DATA->co2_shm == 1) { + send_mail(conf->mail, receivedString, conf, DATA); + *DATA->co2_shm = 0; + } + pthread_mutex_unlock(&mutex); + + DATA->co2_num = 0; + } + } + } + + printf("\n"); + } + } + + receivedString[0] = '\0'; + index = 0; + } + + } + + // 上传传感器数据到Mysql数据库 + timing++; + if (0 == strcasecmp(conf->MYSQL_ON, "on")) { + if (timing >= (atoi(conf->PUSH_MYSQL_DATA_TIME) * 100)) { + + Thread args = { conf, DATA }; + pthread_t tid; + // 创建线程，并传递包含两个结构体的参数 + if (pthread_create(&tid, NULL, pull_data_mysql, &args) != 0) { + perror("pthread_create"); + return 1; + } + // 等待线程结束 + pthread_join(tid, NULL); + + timing = 0; + } + } + + delay(10); + } + + } + + waitpid(pid, NULL, 0); + // 断开共享内存连接 + detachAndDeleteSharedMemory(1, DATA->ds18b20_shm); + detachAndDeleteSharedMemory(2, DATA->co_shm); + detachAndDeleteSharedMemory(3, DATA->co2_shm); + + return 0; +} + +int redirect_stdout_to_file(int fd, const char *filename) +{ + fd = open(filename, O_WRONLY | O_CREAT | O_APPEND, 0644); + if (fd == -1) { + perror("open"); + return 1; + } + + if (dup2(fd, STDOUT_FILENO) == -1) { + perror("dup2"); + return 1; + } + + return 0; +} + +int main() +{ + int logfd = -1; + int fd = -1; + + if (nice(-20) == -1) { + perror("nice"); + return 1; + } + + if (0 != daemon(1, 1)) { + perror("daemon"); + } + + if ((fd = serialOpen("/dev/serial0", 9600)) < 0) { + printf("Unable to open device\n"); + return 1; + } else { + printf("Serial port opened\n"); + } + + CONF *conf = (struct CONF *)malloc(sizeof(struct CONF)); + memset(conf, 0, sizeof(struct CONF)); + conf->mail = strdup(read_conf("hc-12.conf", "global", "MAIL")); + conf->temperature = strdup(read_conf("hc-12.conf", "global", "TEMPERATURE")); + conf->co = strdup(read_conf("hc-12.conf", "global", "CO")); + conf->co2 = strdup(read_conf("hc-12.conf", "global", "CO2")); + + conf->MYSQL_ON = strdup(read_conf("hc-12.conf", "global", "MYSQL")); + if (0 == strcasecmp(conf->MYSQL_ON, "on")) { + conf->PUSH_MYSQL_DATA_TIME = strdup(read_conf("hc-12.conf", "global", "PUSH_MYSQL_DATA_TIME")); + conf->MYSQL_HOST = strdup(read_conf("hc-12.conf", "global", "MYSQL_HOST")); + conf->MYSQL_PORT_ = strdup(read_conf("hc-12.conf", "global", "MYSQL_PORT")); + conf->MYSQL_USRT = strdup(read_conf("hc-12.conf", "global", "MYSQL_USRT")); + conf->MYSQL_PASSWORD = strdup(read_conf("hc-12.conf", "global", "MYSQL_PASSWORD")); + conf->MYSQL_DB = strdup(read_conf("hc-12.conf", "global", "MYSQL_DB")); + conf->MYSQL_TABLES = strdup(read_conf("hc-12.conf", "global", "MYSQL_TABLES")); + } + + DATA *data = (struct DATA *)malloc(sizeof(struct DATA)); + memset(data, 0, sizeof(struct DATA)); + data->ds18b20 = 0; + data->ch4 = 0; + data->rp2040 = 0; + data->rp2040_f = 0; + data->co = 0; + data->co2 = 0; + data->rp2040_num = 0; + data->ch4_num = 0; + data->ds18b20_num = 0; + data->co_num = 0; + data->co2_num = 0; + data->ds18b20_1st = 1; + data->ch4_1st = 1; + data->co_1st = 1; + data->co2_1st = 1; + data->_time = 180; + + redirect_stdout_to_file(logfd, "hc-12.log"); + pthread_mutex_init(&mutex, NULL); // 初始化互斥锁 + loop(fd, conf, data); + pthread_mutex_destroy(&mutex); // 销毁互斥锁 + + free(conf->mail); + free(conf->temperature); + free(conf->co); + free(conf->co2); + free(conf->PUSH_MYSQL_DATA_TIME); + free(conf->MYSQL_HOST); + free(conf->MYSQL_PORT_); + free(conf->MYSQL_USRT); + free(conf->MYSQL_PASSWORD); + free(conf->MYSQL_DB); + free(conf->MYSQL_TABLES); + free(conf); + free(data); + close(fd); + close(logfd); + return 0; +} diff --git a/SOFTWARE/Server/hc-12/hc-12.conf b/SOFTWARE/Server/hc-12/hc-12.conf new file mode 100644 index 0000000..aa9d614 --- /dev/null +++ b/SOFTWARE/Server/hc-12/hc-12.conf @@ -0,0 +1,16 @@ +global { + + MAIL="1605227279@qq.com"; // 发送邮箱 + TEMPERATURE=60; // 温度上限(单位摄氏度) + CO=200; // CO 上限(单位ppm) + CO2=1500; // CO2 上限(单位ppm) + + MYSQL="on"; // 传感器上传到数据库(非on 不上传) + PUSH_MYSQL_DATA_TIME=60; // 上传数据频率（单位秒大于等于1） + MYSQL_HOST="git.aixiao.me"; // 数据库地址 + MYSQL_PORT="3306"; // 数据库端口 + MYSQL_USRT="root"; // 数据库账号 + MYSQL_PASSWORD="198"; // 数据库密码 + MYSQL_DB="raspberrypi"; // 数据库名 + MYSQL_TABLES="gas"; // 数据库表 +} diff --git a/SOFTWARE/Server/hc-12/hc-12.h b/SOFTWARE/Server/hc-12/hc-12.h new file mode 100644 index 0000000..7c4c829 --- /dev/null +++ b/SOFTWARE/Server/hc-12/hc-12.h @@ -0,0 +1,79 @@ +#ifndef HC_12_H +#define HC_12_H + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "../libconf/libconf.h" + +#define BUFFER 1024 +#define MAIL "gomail -r \"%s\" -s \"%s\" -t \"%s\"" + +typedef struct CONF { + char *mail; + char *temperature; + char *co; + char *co2; + char *MYSQL_ON; + char *PUSH_MYSQL_DATA_TIME; + char *MYSQL_HOST; + char *MYSQL_PORT_; + char *MYSQL_USRT; + char *MYSQL_PASSWORD; + char *MYSQL_DB; + char *MYSQL_TABLES; + +} CONF; + +typedef struct DATA { + // 存储实际传感器数据 + float ds18b20; + float ch4; + float rp2040; + float rp2040_f; + float co; + float co2; + float ch4_; + + // 超过阈值次数 + int ds18b20_num; + int ch4_num; + int rp2040_num; + int co_num; + int co2_num; + + // 共享内存 + int *ds18b20_shm; + int *co_shm; + int *co2_shm; + + // 第一次发送Mail标志 + int ds18b20_1st; + int ch4_1st; + int co_1st; + int co2_1st; + + // 持续浓度时候,等待时间再发送Mail + int _time; +} DATA; + +// 定义包含两个结构体的参数结构体 +typedef struct { + CONF *conf; + DATA *data; +} Thread; + +#endif diff --git a/SOFTWARE/Server/hc-12/mysql.c b/SOFTWARE/Server/hc-12/mysql.c new file mode 100644 index 0000000..8942a41 --- /dev/null +++ b/SOFTWARE/Server/hc-12/mysql.c @@ -0,0 +1,38 @@ +#include "mysql.h" + +int _mysql(char *sql, char *MYSQL_HOST, char *MYSQL_PORT_, char *MYSQL_USRT, char *MYSQL_PASSWORD, char *MYSQL_DB, char *MYSQL_TABLES) +{ + static MYSQL mysql; // 静态变量，仅初始化一次 + static char MYSQL_DB_[270] = { 0 }; + + if (!mysql_init(&mysql)) { + perror("mysql_init"); + return -1; + } + + int result = 0; + + if (mysql_real_connect(&mysql, MYSQL_HOST, MYSQL_USRT, MYSQL_PASSWORD, "mysql", atoi(MYSQL_PORT_), NULL, 0)) { + if (0 != mysql_set_character_set(&mysql, "utf8")) { + perror("mysql_set_character_set"); + result = -1; + goto shutdown; + } + + sprintf(MYSQL_DB_, "use %s;", MYSQL_DB); + if (mysql_query(&mysql, MYSQL_DB_) || mysql_query(&mysql, sql)) { + fprintf(stderr, "Query execution failed: %s\n", mysql_error(&mysql)); + result = -1; + } else { + // 执行成功的操作 + } + } else { + fprintf(stderr, "Connect failed: %s\n", mysql_error(&mysql)); + result = -1; + } + +shutdown: + mysql_close(&mysql); + + return result; +} diff --git a/SOFTWARE/Server/hc-12/mysql.h b/SOFTWARE/Server/hc-12/mysql.h new file mode 100644 index 0000000..80eeca6 --- /dev/null +++ b/SOFTWARE/Server/hc-12/mysql.h @@ -0,0 +1,13 @@ +#ifndef MYSQL_H +#define MYSQL_H + +#include +#include +#include +#include +#include +#include + +extern int _mysql(char *sql, char *MYSQL_HOST, char *MYSQL_PORT_, char *MYSQL_USRT, char *MYSQL_PASSWORD, char *MYSQL_DB, char *MYSQL_TABLES); + +#endif diff --git a/SOFTWARE/Server/hc-12/tables/gas.sql b/SOFTWARE/Server/hc-12/tables/gas.sql new file mode 100644 index 0000000..2cd6150 --- /dev/null +++ b/SOFTWARE/Server/hc-12/tables/gas.sql @@ -0,0 +1,35 @@ +/* + Navicat Premium Data Transfer + + Source Server : git.aixiao.me_3306 + Source Server Type : MySQL + Source Server Version : 50740 + Source Host : git.aixiao.me:3306 + Source Schema : raspberrypi + + Target Server Type : MySQL + Target Server Version : 50740 + File Encoding : 65001 + + Date: 21/03/2024 10:57:51 +*/ + +SET NAMES utf8mb4; +SET FOREIGN_KEY_CHECKS = 0; + +-- ---------------------------- +-- Table structure for gas +-- ---------------------------- +DROP TABLE IF EXISTS `gas`; +CREATE TABLE `gas` ( + `ID` int(11) NOT NULL AUTO_INCREMENT, + `TIME` datetime NULL DEFAULT NULL, + `CO` varchar(255) CHARACTER SET utf8 COLLATE utf8_croatian_ci NULL DEFAULT NULL, + `CO2` varchar(255) CHARACTER SET utf8 COLLATE utf8_croatian_ci NULL DEFAULT NULL, + `CH4` varchar(255) CHARACTER SET utf8 COLLATE utf8_croatian_ci NULL DEFAULT NULL, + `TEMPERATURE` varchar(255) CHARACTER SET utf8 COLLATE utf8_croatian_ci NULL DEFAULT NULL, + `RP2040_TEMPERATURE` varchar(255) CHARACTER SET utf8 COLLATE utf8_croatian_ci NULL DEFAULT NULL, + PRIMARY KEY (`ID`) USING BTREE +) ENGINE = InnoDB AUTO_INCREMENT = 1 CHARACTER SET = utf8 COLLATE = utf8_croatian_ci ROW_FORMAT = Dynamic; + +SET FOREIGN_KEY_CHECKS = 1; diff --git a/SOFTWARE/Source/DTH11.cpp b/SOFTWARE/Source/DTH11.cpp new file mode 100644 index 0000000..3446bcc --- /dev/null +++ b/SOFTWARE/Source/DTH11.cpp @@ -0,0 +1,70 @@ +#include "DTH11.hpp" + +typedef struct { + float humidity; + float temp_celsius; +} dht_reading; + +void read_from_dht(dht_reading * result, int DHT_PIN) +{ + int data[5] = { 0, 0, 0, 0, 0 }; + uint last = 1; + uint j = 0; + + gpio_set_dir(DHT_PIN, GPIO_OUT); + gpio_put(DHT_PIN, 0); + sleep_ms(20); + gpio_set_dir(DHT_PIN, GPIO_IN); + + for (uint i = 0; i < MAX_TIMINGS; i++) { + uint count = 0; + while (gpio_get(DHT_PIN) == last) { + count++; + sleep_us(1); + if (count == 255) + break; + } + + last = gpio_get(DHT_PIN); + if (count == 255) + break; + + if ((i >= 4) && (i % 2 == 0)) { + data[j / 8] <<= 1; + if (count > 16) + data[j / 8] |= 1; + j++; + } + } + + if ((j >= 40) && (data[4] == ((data[0] + data[1] + data[2] + data[3]) & 0xFF))) { + result->humidity = (float)((data[0] << 8) + data[1]) / 10; + if (result->humidity > 100) { + result->humidity = data[0]; + } + result->temp_celsius = (float)(((data[2] & 0x7F) << 8) + data[3]) / 10; + if (result->temp_celsius > 125) { + result->temp_celsius = data[2]; + } + if (data[2] & 0x80) { + result->temp_celsius = -result->temp_celsius; + } + } else { + printf("Bad data\n"); + } +} + +int DTH11_(int DHT_PIN) +{ + stdio_init_all(); + gpio_init(DHT_PIN); + + dht_reading reading; + read_from_dht(&reading, DHT_PIN); + float fahrenheit = (reading.temp_celsius * 9 / 5) + 32; + printf("Humidity = %.1f%%, Temperature = %.1fC (%.1fF)\n", reading.humidity, reading.temp_celsius, fahrenheit); + + sleep_ms(2000); + + return 0; +} diff --git a/SOFTWARE/Source/DTH11.hpp b/SOFTWARE/Source/DTH11.hpp new file mode 100644 index 0000000..8453386 --- /dev/null +++ b/SOFTWARE/Source/DTH11.hpp @@ -0,0 +1,11 @@ +#ifndef DTH11_H +#define DTH11_H + +#include +#include +#include "pico/stdlib.h" +#include "hardware/gpio.h" + +const uint MAX_TIMINGS = 85; + +#endif diff --git a/SOFTWARE/Source/HC-12.cpp b/SOFTWARE/Source/HC-12.cpp new file mode 100644 index 0000000..c7e0050 --- /dev/null +++ b/SOFTWARE/Source/HC-12.cpp @@ -0,0 +1,20 @@ +#include "HC-12.hpp" + +void _HC_12_INIT() +{ + uint tx_offset = pio_add_program(pio1, &uart_tx_program); + uart_tx_program_init(HC_12_PIO, HC_12_PIO_SM_TX, tx_offset, HC_12_PIO_TX_PIN, HC_12_PIO_SERIAL_BAUD); + + uint rx_offset = pio_add_program(pio1, &uart_rx_program); + uart_rx_program_init(HC_12_PIO, HC_12_PIO_SM_RX, rx_offset, HC_12_PIO_RX_PIN, HC_12_PIO_SERIAL_BAUD); + + return; +} + +void _HC_12(const char *string) +{ + uart_tx_program_puts(HC_12_PIO, HC_12_PIO_SM_TX, string); + sleep_ms(100); + + return; +} diff --git a/SOFTWARE/Source/HC-12.hpp b/SOFTWARE/Source/HC-12.hpp new file mode 100644 index 0000000..506fff6 --- /dev/null +++ b/SOFTWARE/Source/HC-12.hpp @@ -0,0 +1,19 @@ +#ifndef HC_12_H +#define HC_12_H + +#include "pico/stdlib.h" +#include "hardware/pio.h" +#include "uart_tx.pio.h" +#include "uart_rx.pio.h" + +#define HC_12_PIO pio1 +#define HC_12_PIO_TX_PIN 16 // 接 HC-12 RX +#define HC_12_PIO_RX_PIN 15 // 接 HC-12 TX +#define HC_12_PIO_SM_TX 0 +#define HC_12_PIO_SM_RX 1 +#define HC_12_PIO_SERIAL_BAUD 9600 + +extern void _HC_12_INIT(); +extern void _HC_12(const char *string); + +#endif diff --git a/SOFTWARE/Source/MAIN.cpp b/SOFTWARE/Source/MAIN.cpp new file mode 100644 index 0000000..955610c --- /dev/null +++ b/SOFTWARE/Source/MAIN.cpp @@ -0,0 +1,380 @@ +/* + * + * 基于 Raspberry Pico 的厨房危险(火灾)报警 + * 使用 DS18B20温度传感器 + * 使用 CH4 N55A甲烷气体传感器(进口) + * 使用 PASCO2V01 CO2二氧化碳传感器模块(进口模块暂时买不到！) + * 使用 MH-Z14B CO2二氧化碳传感器模块(国产)(0 - 5000ppm) + * 使用 ME2_CO CO一氧化碳传感器模块(国产) + * + * Date: 20240103 + * + */ + +#include "MAIN.hpp" +#include "DTH11.hpp" +#include "HC-12.hpp" +#include "ZC13.hpp" + +#ifndef PICO_DEFAULT_LED_PIN +#warning pio/hello_pio example requires a board with a regular LED +#define PICO_DEFAULT_LED_PIN 25 + +#endif + +static inline bool uart_rx_program_available(PIO pio, uint sm) +{ + return !pio_sm_is_rx_fifo_empty(pio, sm); +} + +// 闪烁LED +static void light_flashing() +{ + gpio_init(PICO_DEFAULT_LED_PIN); + gpio_set_dir(PICO_DEFAULT_LED_PIN, GPIO_OUT); + gpio_put(PICO_DEFAULT_LED_PIN, 1); + sleep_ms(100); + gpio_put(PICO_DEFAULT_LED_PIN, 0); + sleep_ms(100); + + return; +} + +int wifi() +{ + if (cyw43_arch_init()) { + printf("failed to initialise\n"); + return 1; + } + + cyw43_arch_enable_sta_mode(); + + printf("Connecting to Wi-Fi...\n"); + if (cyw43_arch_wifi_connect_timeout_ms(WIFI_SSID, WIFI_PASSWORD, CYW43_AUTH_WPA2_AES_PSK, 30000)) { + printf("failed to connect.\n"); + return 1; + } else { + printf("Connected.\n"); + } + + cyw43_arch_deinit(); + + return 0; +} + +// 获取主板温度 +float read_onboard_temperature() +{ + adc_init(); + adc_set_temp_sensor_enabled(true); + adc_select_input(4); // Input 4 is the onboard temperature sensor. + + /* 12-bit conversion, assume max value == ADC_VREF == 3.3 V */ + const float conversionFactor = 3.3f / (1 << 12); + + float adc = (float)adc_read() * conversionFactor; + float tempC = 27.0f - (adc - 0.706f) / 0.001721f; + + //printf("Onboard temperature %.02f°C %.02f°F\n", tempC, (tempC * 9 / 5 + 32)); + return tempC; +} + +// 温度传感器 +float DS18B20() +{ + float TEMPERATURE = -1; + + One_wire one_wire(DS18B20_PIN); + one_wire.init(); + rom_address_t address { + }; + + one_wire.single_device_read_rom(address); + /* + printf("Device Address: %02x%02x%02x%02x%02x%02x%02x%02x\n", + address.rom[0], address.rom[1], address.rom[2], address.rom[3], + address.rom[4], address.rom[5], address.rom[6], address.rom[7]); + */ + one_wire.convert_temperature(address, true, false); + TEMPERATURE = one_wire.temperature(address); + //printf("Temperature: %3.1f°C\n", one_wire.temperature(address)); + + return TEMPERATURE; +} + +// 甲烷气体传感器 +int CH4() +{ + int CH4_TRUE = 0; + + gpio_init(PICO_DEFAULT_LED_PIN); + gpio_set_dir(PICO_DEFAULT_LED_PIN, GPIO_OUT); + + gpio_init(CH4_PIN); // 设置 GP14 引脚作为输入引脚 + gpio_set_dir(CH4_PIN, GPIO_IN); + + if (gpio_get(CH4_PIN) == 1) { + CH4_TRUE = 1; + + } + sleep_ms(100); + return CH4_TRUE; +} + +// CO2 +static uint16_t MH_Z14B(int *MH_Z14B_DATA_IS_OK) +{ + // 初始化UART + uart_init(UART1, BAUD_RATE); + gpio_set_function(UART1_TX_PIN, GPIO_FUNC_UART); + gpio_set_function(UART1_RX_PIN, GPIO_FUNC_UART); + uart_set_hw_flow(UART1, false, false); + uart_set_format(UART1, DATA_BITS, STOP_BITS, PARITY); + + // 0x86 读气体浓度值 + uint8_t CMD[9] = { 0xFF, 0x01, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79 }; + uart_write_blocking(UART1, CMD, 9); + sleep_ms(200); + + // 读取 + uint8_t CO2_DATA[9] = { 0 }; + uart_read_blocking(UART1, CO2_DATA, 9); + + // CO2 浓度 + uint16_t CO2_CONC = (256 * CO2_DATA[2]) + CO2_DATA[3]; + + // 校验 + uint8_t CHECKSUM = (0xFF - (CO2_DATA[1] + CO2_DATA[2] + CO2_DATA[3] + CO2_DATA[4] + CO2_DATA[5] + CO2_DATA[6] + CO2_DATA[7])) + 1; + + if (CO2_DATA[8] == CHECKSUM && CO2_DATA[1] == 0x86) { + //printf("CHECKSUM: %X = %X\n", CO2_DATA[8], CHECKSUM); + //printf("CO2 Concentration: %d ppm\n", CO2_CONC); + *MH_Z14B_DATA_IS_OK = 1; + } else { + // 校准传感器 零点 （ZERO） + uint8_t ZERO[] = { 0XFF, 0X01, 0X87, 0X00, 0X00, 0X00, 0X00, 0X00, 0X78 }; + uart_write_blocking(UART1, ZERO, 9); + sleep_ms(200); + + // 校准传感器 跨度点 （SPAN） + uint8_t SPAN[] = { 0XFF, 0X01, 0X88, 0X07, 0XD0, 0X00, 0X00, 0X00, 0XA0 }; + uart_write_blocking(UART1, SPAN, 9); + sleep_ms(200); + + *MH_Z14B_DATA_IS_OK = 0; + printf("CO2 concentration reading failed!\n"); + } + + return CO2_CONC; +} + +// CO +static uint16_t ME2_CO(int IS_ANSWER, int *ME2_CO_DATA_IS_OK) +{ + // 初始化UART + uart_init(UART0, BAUD_RATE); + gpio_set_function(UART0_TX_PIN, GPIO_FUNC_UART); + gpio_set_function(UART0_RX_PIN, GPIO_FUNC_UART); + uart_set_hw_flow(UART0, false, false); + uart_set_format(UART0, DATA_BITS, STOP_BITS, PARITY); + + if (IS_ANSWER == 1) { + // 应答模式 + uint8_t _ANSWER[9] = { 0xFF, 0x01, 0x78, 0x41, 0x00, 0x00, 0x00, 0x00, 0x46 }; + uart_write_blocking(UART0, _ANSWER, 9); + sleep_ms(100); + } + // 读取 + uint8_t CO_DATA[9] = { 0 }; + uart_read_blocking(UART0, CO_DATA, 9); + + // CO 浓度 + uint16_t CO_CONC = (256 * CO_DATA[4]) + CO_DATA[5]; + + // 校验 + uint8_t CHECKSUM = (0xFF - (CO_DATA[1] + CO_DATA[2] + CO_DATA[3] + CO_DATA[4] + CO_DATA[5] + CO_DATA[6] + CO_DATA[7])) + 1; + + if (CO_DATA[8] == CHECKSUM && CO_DATA[1] == 0x04) { + //printf("CHECKSUM: %X = %X\n", CO_DATA[8], CHECKSUM); + //printf("CO Concentration: %d ppm\n", CO_CONC); + *ME2_CO_DATA_IS_OK = 1; + } else { + *ME2_CO_DATA_IS_OK = 0; + } + + return CO_CONC; +} + +// 433MHZ 无线电发送数据到服务器端（Raspberry pico W WiFi 暂时不实现） +int _433_MHZ(unsigned long val) +{ + const uint RADIO_TRANSMIT_PIN = _433_MHZ_PIN; // 433发射模块引脚 + const uint PULSE_LENGTH = 169; // set this to PULSELENGTH RECIEVED + const uint REPEAT_TRANSMIT = 4; // set this to whatever works best for you. // 重复发送 + const uint PROTOCOL = 1; // set this to PROTOCOL RECIEVED + const uint BIT_LENGTH = 24; // set this to BIT LENGTH RECIEVED + + gpio_init(RADIO_TRANSMIT_PIN); + RCSwitch mySwitch = RCSwitch(); + mySwitch.enableTransmit(RADIO_TRANSMIT_PIN); + mySwitch.setProtocol(PROTOCOL); + mySwitch.setPulseLength(PULSE_LENGTH); + mySwitch.setRepeatTransmit(REPEAT_TRANSMIT); + + mySwitch.send(val, BIT_LENGTH); + sleep_ms(10); + + return 0; +} + +// 简单编码通过433MHZ发送 +int addDigit(int number, int digit) +{ + char TEMP[BUFER] = { 0 }; + + snprintf(TEMP, sizeof(TEMP), "%d%d%d", digit, number, digit); + + return atoi(TEMP); +} + +// 核心0发送数据到核心1, 核心1判断是否有数据到来. +static void core1_main() +{ + + while (1) { + multicore_fifo_push_blocking(CH4()); + watchdog_update(); + + sleep_ms(1000); + } + + return; +} + +int main() +{ + stdio_init_all(); + sleep_ms(1000); + + set_sys_clock_khz(250000, true); + + int FIFO_ = -1; + float TEMPERATURE = -1; + float ONBOARD_TEMPERATURE = -1; + uint16_t CO2_DATA = -1; + uint16_t CO_DATA = -1; + int MH_Z14B_DATA_IS_OK = 0; + int ME2_CO_DATA_IS_OK = 0; + + // core1 + multicore_reset_core1(); + multicore_launch_core1(core1_main); + + if (watchdog_caused_reboot()) { // 判断是否从看门狗启动或者正常启动 + printf("Rebooted by Watchdog!\n"); + } else { + printf("Clean boot\n"); + } + watchdog_enable(8300, 1); // 8秒检测是否重新加载看门狗计数器. (不更新计数器则重启硬件, 最高8秒) + watchdog_start_tick(12); + + _HC_12_INIT(); + ZC13_INIT(); + + while (1) { + + watchdog_update(); // 喂狗 + + // RP2040温度 + ONBOARD_TEMPERATURE = read_onboard_temperature(); + if (ONBOARD_TEMPERATURE != -1) { + printf("Onboard temperature %.02f°C %.02f°F\n", ONBOARD_TEMPERATURE, (ONBOARD_TEMPERATURE * 9 / 5 + 32)); + //_433_MHZ(addDigit(ONBOARD_TEMPERATURE, SIGN_RP2040)); + + char ONBOARD_TEMPERATURE_TEMP[BUFER] = { 0 }; + sprintf(ONBOARD_TEMPERATURE_TEMP, "Onboard temperature %.02f°C %.02f°F\n", ONBOARD_TEMPERATURE, (ONBOARD_TEMPERATURE * 9 / 5 + 32)); + _HC_12(ONBOARD_TEMPERATURE_TEMP); + } + watchdog_update(); // 喂狗 + + + + // CH4 + FIFO_ = multicore_fifo_pop_blocking(); + if (FIFO_ == 1) { + printf("Kitchen danger (fire) alarm detects CH4!!!\n"); + light_flashing(); + FIFO_ = -1; + //_433_MHZ(addDigit(4, SIGN_CH4)); + } + watchdog_update(); // 喂狗 + + /* + if (1 == CH4()) { + printf("Kitchen danger (fire) alarm detects CH4!!!\n"); + light_flashing(); + _HC_12("Kitchen danger (fire) alarm detects CH4!!!\n"); + } + watchdog_update(); // 喂狗 + */ + + // DS18B20 + TEMPERATURE = DS18B20(); + if (TEMPERATURE != -1) { + if (TEMPERATURE >= 10) { + printf("Temperature: %.3f°C\n", TEMPERATURE); + } + //_433_MHZ(addDigit(TEMPERATURE, SIGN_DS18B20)); + + if (TEMPERATURE != 85) { + char TEMPERATURE_TEMP[BUFER] = { 0 }; + sprintf(TEMPERATURE_TEMP, "Temperature: %.3f°C\n", TEMPERATURE); + _HC_12(TEMPERATURE_TEMP); + + TEMPERATURE = -1; + } + + } + watchdog_update(); // 喂狗 + + // ZC13 CH4 传感器 + char CH4_DATA[BUFER] = { 0 }; + sprintf(CH4_DATA, "CH4 Concentration: %d\n", ZC13("ZC05")); + _HC_12(CH4_DATA); + watchdog_update(); // 喂狗 + + // ME2_CO CO + // 50 ppm（百万分之一）：长时间暴露可能会导致头痛、恶心、疲劳等不适症状。 + // 200 ppm：短时间暴露可能会导致轻微的头痛、疲劳和呼吸困难。 + // 800 ppm：短时间暴露可能会导致头晕、恶心和死亡。 + // 1600 ppm：短时间暴露可能会导致昏迷、危及生命。 + CO_DATA = ME2_CO(0, &ME2_CO_DATA_IS_OK); + if (CO_DATA != -1 && ME2_CO_DATA_IS_OK == 1) { + printf("CO Concentration: %d ppm\n", CO_DATA); + //_433_MHZ(addDigit(CO_DATA, SIGN_CO)); + + char CO_DATA_TEMP[BUFER] = { 0 }; + sprintf(CO_DATA_TEMP, "CO Concentration: %d ppm\n", CO_DATA); + _HC_12(CO_DATA_TEMP); + } + watchdog_update(); // 喂狗 + + // MH_Z14B CO2 + CO2_DATA = MH_Z14B(&MH_Z14B_DATA_IS_OK); + if (CO2_DATA != -1 && MH_Z14B_DATA_IS_OK == 1) { + printf("CO2 Concentration: %d ppm\n", CO2_DATA); + //_433_MHZ(addDigit(CO2_DATA, SIGN_CO2)); + + char CO2_DATA_TEMP[BUFER] = { 0 }; + sprintf(CO2_DATA_TEMP, "CO2 Concentration: %d ppm\n", CO2_DATA); + _HC_12(CO2_DATA_TEMP); + } + printf("\r\n"); + + watchdog_update(); // 喂狗 + sleep_ms(3000); + watchdog_update(); // 喂狗 + } + + return 0; +} diff --git a/SOFTWARE/Source/MAIN.hpp b/SOFTWARE/Source/MAIN.hpp new file mode 100644 index 0000000..d28c571 --- /dev/null +++ b/SOFTWARE/Source/MAIN.hpp @@ -0,0 +1,49 @@ +#ifndef MAIN_H +#define MAIN_H + +#include +#include "pico/stdlib.h" +#include "hardware/gpio.h" +#include "lib/pico-onewire/api/one_wire.h" +#include "lib/radio-switch.h" + +#include "hardware/clocks.h" +#include "hardware/watchdog.h" +#include "pico/multicore.h" +#include "hardware/i2c.h" +#include "pico/binary_info.h" +#include "hardware/uart.h" +#include "hardware/pwm.h" +#include "hardware/adc.h" + +#include "pico/cyw43_arch.h" +#include "lwip/pbuf.h" +#include "lwip/tcp.h" + +#define BUFER 1024 +#define DS18B20_PIN 15 // DS18B20 引脚 +#define CH4_PIN 14 // CH4 引脚 +#define _433_MHZ_PIN 13 + +#define SIGN_CH4 1 +#define SIGN_DS18B20 2 +#define SIGN_CO 3 +#define SIGN_CO2 4 +#define SIGN_RP2040 5 + +#define WIFI_SSID "your_wifi_ssid" +#define WIFI_PASSWORD "your_wifi_password" + +#define UART1 uart1 +#define BAUD_RATE 9600 +#define DATA_BITS 8 +#define STOP_BITS 1 +#define PARITY UART_PARITY_NONE +#define UART1_TX_PIN 5 // MH-Z14B T +#define UART1_RX_PIN 4 // MH-Z14B R + +#define UART0 uart0 +#define UART0_TX_PIN 1 // +#define UART0_RX_PIN 0 // + +#endif diff --git a/SOFTWARE/Source/ZC13.cpp b/SOFTWARE/Source/ZC13.cpp new file mode 100644 index 0000000..b80755e --- /dev/null +++ b/SOFTWARE/Source/ZC13.cpp @@ -0,0 +1,171 @@ +#include "ZC13.hpp" +#include "common.h" + +int ZC13_INIT() +{ + uint tx_offset = pio_add_program(ZC13_PIO, &uart_tx_program); + uart_tx_program_init(ZC13_PIO, ZC13_PIO_SM_TX, tx_offset, ZC13_PIO_TX_PIN, ZC13_PIO_SERIAL_BAUD); + + uint rx_offset = pio_add_program(ZC13_PIO, &uart_rx_program); + uart_rx_program_init(ZC13_PIO, ZC13_PIO_SM_RX, rx_offset, ZC13_PIO_RX_PIN, ZC13_PIO_SERIAL_BAUD); + + return 0; +} + +int ZC13_PIO_UART_TX_DATA(PIO pio, uint sm, uint8_t *DATA, int DATA_LEN) { + + for (int i = 0; i < DATA_LEN; i++) { + uart_tx_program_putc(pio, sm, DATA[i]); + sleep_ms(3); + } + + return 0; +} + +int ZC13_PIO_UART_RX_DATA(PIO pio, uint sm, uint8_t *DATA, int DATA_LEN) { + char c = '\0'; + int received_count = 0; + int timeout_ms = 100; // 设置较长的超时时间 + + while (received_count < DATA_LEN && timeout_ms > 0) { + if (uart_rx_program_available(pio, sm)) { + c = uart_rx_program_getc(pio, sm); + DATA[received_count++] = c; + printf("0x%X ", c); + if (c == '\n') { + // 接收到换行符，停止接收数据 + break; + } + } else { + // 没有接收到数据，继续等待 + sleep_ms(1); + timeout_ms--; + } + } + + if (received_count == 0) { + // 没有接收到有效数据，可以进行相应的处理 + return -1; + } + + return received_count; +} + +int ZC13(const char *model) +{ + uint8_t CH4_DATA[270] = { 0 }; + int CH4_DATA_LEN = 0; + + // 发送指令 + uint8_t CH4_CMD[9] = { 0xFF, 0x01, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79 }; + ZC13_PIO_UART_TX_DATA(ZC13_PIO, ZC13_PIO_SM_TX, CH4_CMD, sizeof(CH4_CMD)); + sleep_ms(200); + + // 接收指令 + CH4_DATA_LEN = ZC13_PIO_UART_RX_DATA(ZC13_PIO, ZC13_PIO_SM_RX, CH4_DATA, 9); + + + printf("\n"); + printf("%d\n", CH4_DATA_LEN); + + uint8_t highByte = CH4_DATA[2]; // 假设这是气体浓度高位字节 + uint8_t lowByte = CH4_DATA[3]; // 假设这是气体浓度高位字节 + + // 判断最高位是否为 1 + if (highByte & 0x80) { + // 最高位是 1，表示传感器故障 + printf("CH4 sensor malfunction!\n"); + } else { + if (CH4_DATA[1] == 0X86) { + if ( 0 == strcasecmp(model, "ZC05")) { + // 计算气体浓度值 + uint16_t gasConcentration = (highByte & 0x3F) * 256 + lowByte; + // 输出气体浓度值 + printf("CH4 Concentration: %uppm\n", gasConcentration); + + return gasConcentration; + } + + if ( 0 == strcasecmp(model, "ZC13")) { + // 计算气体浓度值 + uint16_t gasConcentration = (highByte & 0x1F) * 256 + lowByte; + // 输出气体浓度值 + printf("CH4 Concentration: %uppm\n", gasConcentration); + + return gasConcentration; + } + } + } + + return -1; +} + +/* +int ZC13(const char *model) +{ + char CH4_DATA[9] = { 0 }; + int CH4_DATA_index = 0; + + // 发送指令 + char CH4_CMD[9] = { 0xFF, 0x01, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79 }; + for (int i = 0; i < 9; i++) { + uart_tx_program_putc(ZC13_PIO, ZC13_PIO_SM_TX, CH4_CMD[i]); + sleep_ms(1); + } + sleep_ms(200); + + // 接收数据，直到收到换行符或达到缓冲区大小限制 + char c = '\0'; + int timeout_ms = 100; // 设置超时时间为100ms + int received_count = 0; + + while (received_count < 9 && timeout_ms > 0) { + if (uart_rx_program_available(ZC13_PIO, ZC13_PIO_SM_RX)) { + c = uart_rx_program_getc(ZC13_PIO, ZC13_PIO_SM_RX); + CH4_DATA[CH4_DATA_index++] = c; + received_count++; + timeout_ms = 100; // 重置超时时间 + } else { + sleep_ms(1); + timeout_ms--; // 减少超时时间 + } + } + + // 处理接收到的数据 + for (int i = 0; i < 9; i++) { + printf("0x%X ", CH4_DATA[i]); + } + printf("\n"); + + uint8_t highByte = CH4_DATA[2]; // 假设这是气体浓度高位字节 + uint8_t lowByte = CH4_DATA[3]; // 假设这是气体浓度高位字节 + + // 判断最高位是否为 1 + if (highByte & 0x80) { + // 最高位是 1，表示传感器故障 + printf("CH4 sensor malfunction!\n"); + } else { + if (CH4_DATA[1] == 0X86) { + if ( 0 == strcasecmp(model, "ZC05")) { + // 计算气体浓度值 + uint16_t gasConcentration = (highByte & 0x3F) * 256 + lowByte; + // 输出气体浓度值 + printf("CH4 Concentration: %uppm\n", gasConcentration); + + return gasConcentration; + } + + if ( 0 == strcasecmp(model, "ZC13")) { + // 计算气体浓度值 + uint16_t gasConcentration = (highByte & 0x1F) * 256 + lowByte; + // 输出气体浓度值 + printf("CH4 Concentration: %uppm\n", gasConcentration); + + return gasConcentration; + } + } + } + + return -1; +} +*/ \ No newline at end of file diff --git a/SOFTWARE/Source/ZC13.hpp b/SOFTWARE/Source/ZC13.hpp new file mode 100644 index 0000000..f703d71 --- /dev/null +++ b/SOFTWARE/Source/ZC13.hpp @@ -0,0 +1,21 @@ +#ifndef ZC13_HPP +#define ZC13_HPP + +#include +#include +#include "pico/stdlib.h" +#include "hardware/pio.h" +#include "uart_tx.pio.h" +#include "uart_rx.pio.h" + +#define ZC13_PIO pio0 +#define ZC13_PIO_TX_PIN 19 // 接ZC13 4 TX PIN +#define ZC13_PIO_RX_PIN 20 // 接ZC13 5 RX PIN +#define ZC13_PIO_SM_TX 0 +#define ZC13_PIO_SM_RX 1 +#define ZC13_PIO_SERIAL_BAUD 9600 + +extern int ZC13_INIT(); +extern int ZC13(const char *model); + +#endif diff --git a/SOFTWARE/Source/common.c b/SOFTWARE/Source/common.c new file mode 100644 index 0000000..fca1675 --- /dev/null +++ b/SOFTWARE/Source/common.c @@ -0,0 +1,4 @@ +#include "common.h" + + + diff --git a/SOFTWARE/Source/common.h b/SOFTWARE/Source/common.h new file mode 100644 index 0000000..c98eb26 --- /dev/null +++ b/SOFTWARE/Source/common.h @@ -0,0 +1,12 @@ +#ifndef COMMOM_H +#define COMMOM_H + + +#include "hardware/pio.h" + +static inline bool uart_rx_program_available(PIO pio, uint sm) +{ + return !pio_sm_is_rx_fifo_empty(pio, sm); +} + +#endif diff --git a/SOFTWARE/Source/lwipopts.h b/SOFTWARE/Source/lwipopts.h new file mode 100644 index 0000000..8571ed5 --- /dev/null +++ b/SOFTWARE/Source/lwipopts.h @@ -0,0 +1,10 @@ +#ifndef _LWIPOPTS_H +#define _LWIPOPTS_H + +// Generally you would define your own explicit list of lwIP options +// (see https://www.nongnu.org/lwip/2_1_x/group__lwip__opts.html) +// +// This example uses a common include to avoid repetition +#include "lwipopts_examples_common.h" + +#endif diff --git a/SOFTWARE/Source/lwipopts_examples_common.h b/SOFTWARE/Source/lwipopts_examples_common.h new file mode 100644 index 0000000..cb0ac56 --- /dev/null +++ b/SOFTWARE/Source/lwipopts_examples_common.h @@ -0,0 +1,89 @@ +#ifndef _LWIPOPTS_EXAMPLE_COMMONH_H +#define _LWIPOPTS_EXAMPLE_COMMONH_H + +// Common settings used in most of the pico_w examples +// (see https://www.nongnu.org/lwip/2_1_x/group__lwip__opts.html for details) + +// allow override in some examples +#ifndef NO_SYS +#define NO_SYS 1 +#endif +// allow override in some examples +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 0 +#endif +#if PICO_CYW43_ARCH_POLL +#define MEM_LIBC_MALLOC 1 +#else +// MEM_LIBC_MALLOC is incompatible with non polling versions +#define MEM_LIBC_MALLOC 0 +#endif +#define MEM_ALIGNMENT 4 +#define MEM_SIZE 4000 +#define MEMP_NUM_TCP_SEG 32 +#define MEMP_NUM_ARP_QUEUE 10 +#define PBUF_POOL_SIZE 24 +#define LWIP_ARP 1 +#define LWIP_ETHERNET 1 +#define LWIP_ICMP 1 +#define LWIP_RAW 1 +#define TCP_WND (8 * TCP_MSS) +#define TCP_MSS 1460 +#define TCP_SND_BUF (8 * TCP_MSS) +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1)) / (TCP_MSS)) +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define LWIP_NETIF_HOSTNAME 1 +#define LWIP_NETCONN 0 +#define MEM_STATS 0 +#define SYS_STATS 0 +#define MEMP_STATS 0 +#define LINK_STATS 0 +// #define ETH_PAD_SIZE 2 +#define LWIP_CHKSUM_ALGORITHM 3 +#define LWIP_DHCP 1 +#define LWIP_IPV4 1 +#define LWIP_TCP 1 +#define LWIP_UDP 1 +#define LWIP_DNS 1 +#define LWIP_TCP_KEEPALIVE 1 +#define LWIP_NETIF_TX_SINGLE_PBUF 1 +#define DHCP_DOES_ARP_CHECK 0 +#define LWIP_DHCP_DOES_ACD_CHECK 0 + +#ifndef NDEBUG +#define LWIP_DEBUG 1 +#define LWIP_STATS 1 +#define LWIP_STATS_DISPLAY 1 +#endif + +#define ETHARP_DEBUG LWIP_DBG_OFF +#define NETIF_DEBUG LWIP_DBG_OFF +#define PBUF_DEBUG LWIP_DBG_OFF +#define API_LIB_DEBUG LWIP_DBG_OFF +#define API_MSG_DEBUG LWIP_DBG_OFF +#define SOCKETS_DEBUG LWIP_DBG_OFF +#define ICMP_DEBUG LWIP_DBG_OFF +#define INET_DEBUG LWIP_DBG_OFF +#define IP_DEBUG LWIP_DBG_OFF +#define IP_REASS_DEBUG LWIP_DBG_OFF +#define RAW_DEBUG LWIP_DBG_OFF +#define MEM_DEBUG LWIP_DBG_OFF +#define MEMP_DEBUG LWIP_DBG_OFF +#define SYS_DEBUG LWIP_DBG_OFF +#define TCP_DEBUG LWIP_DBG_OFF +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#define TCP_WND_DEBUG LWIP_DBG_OFF +#define TCP_FR_DEBUG LWIP_DBG_OFF +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#define TCP_RST_DEBUG LWIP_DBG_OFF +#define UDP_DEBUG LWIP_DBG_OFF +#define TCPIP_DEBUG LWIP_DBG_OFF +#define PPP_DEBUG LWIP_DBG_OFF +#define SLIP_DEBUG LWIP_DBG_OFF +#define DHCP_DEBUG LWIP_DBG_OFF + +#endif /* __LWIPOPTS_H__ */ diff --git a/SOFTWARE/Source/uart_rx.pio b/SOFTWARE/Source/uart_rx.pio new file mode 100644 index 0000000..54a6577 --- /dev/null +++ b/SOFTWARE/Source/uart_rx.pio @@ -0,0 +1,94 @@ +; +; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +; +; SPDX-License-Identifier: BSD-3-Clause +; + +.program uart_rx_mini + +; Minimum viable 8n1 UART receiver. Wait for the start bit, then sample 8 bits +; with the correct timing. +; IN pin 0 is mapped to the GPIO used as UART RX. +; Autopush must be enabled, with a threshold of 8. + + wait 0 pin 0 ; Wait for start bit + set x, 7 [10] ; Preload bit counter, delay until eye of first data bit +bitloop: ; Loop 8 times + in pins, 1 ; Sample data + jmp x-- bitloop [6] ; Each iteration is 8 cycles + +% c-sdk { +#include "hardware/clocks.h" +#include "hardware/gpio.h" + +static inline void uart_rx_mini_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) { + pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false); + pio_gpio_init(pio, pin); + gpio_pull_up(pin); + + pio_sm_config c = uart_rx_mini_program_get_default_config(offset); + sm_config_set_in_pins(&c, pin); // for WAIT, IN + // Shift to right, autopush enabled + sm_config_set_in_shift(&c, true, true, 8); + sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX); + // SM transmits 1 bit per 8 execution cycles. + float div = (float)clock_get_hz(clk_sys) / (8 * baud); + sm_config_set_clkdiv(&c, div); + + pio_sm_init(pio, sm, offset, &c); + pio_sm_set_enabled(pio, sm, true); +} +%} + +.program uart_rx + +; Slightly more fleshed-out 8n1 UART receiver which handles framing errors and +; break conditions more gracefully. +; IN pin 0 and JMP pin are both mapped to the GPIO used as UART RX. + +start: + wait 0 pin 0 ; Stall until start bit is asserted + set x, 7 [10] ; Preload bit counter, then delay until halfway through +bitloop: ; the first data bit (12 cycles incl wait, set). + in pins, 1 ; Shift data bit into ISR + jmp x-- bitloop [6] ; Loop 8 times, each loop iteration is 8 cycles + jmp pin good_stop ; Check stop bit (should be high) + + irq 4 rel ; Either a framing error or a break. Set a sticky flag, + wait 1 pin 0 ; and wait for line to return to idle state. + jmp start ; Don't push data if we didn't see good framing. + +good_stop: ; No delay before returning to start; a little slack is + push ; important in case the TX clock is slightly too fast. + + +% c-sdk { +static inline void uart_rx_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) { + pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false); + pio_gpio_init(pio, pin); + gpio_pull_up(pin); + + pio_sm_config c = uart_rx_program_get_default_config(offset); + sm_config_set_in_pins(&c, pin); // for WAIT, IN + sm_config_set_jmp_pin(&c, pin); // for JMP + // Shift to right, autopush disabled + sm_config_set_in_shift(&c, true, false, 32); + // Deeper FIFO as we're not doing any TX + sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX); + // SM transmits 1 bit per 8 execution cycles. + float div = (float)clock_get_hz(clk_sys) / (8 * baud); + sm_config_set_clkdiv(&c, div); + + pio_sm_init(pio, sm, offset, &c); + pio_sm_set_enabled(pio, sm, true); +} + +static inline char uart_rx_program_getc(PIO pio, uint sm) { + // 8-bit read from the uppermost byte of the FIFO, as data is left-justified + io_rw_8 *rxfifo_shift = (io_rw_8*)&pio->rxf[sm] + 3; + while (pio_sm_is_rx_fifo_empty(pio, sm)) + tight_loop_contents(); + return (char)*rxfifo_shift; +} + +%} diff --git a/SOFTWARE/Source/uart_tx.pio b/SOFTWARE/Source/uart_tx.pio new file mode 100644 index 0000000..b1320f6 --- /dev/null +++ b/SOFTWARE/Source/uart_tx.pio @@ -0,0 +1,61 @@ +; +; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +; +; SPDX-License-Identifier: BSD-3-Clause +; + +.program uart_tx +.side_set 1 opt + +; An 8n1 UART transmit program. +; OUT pin 0 and side-set pin 0 are both mapped to UART TX pin. + + pull side 1 [7] ; Assert stop bit, or stall with line in idle state + set x, 7 side 0 [7] ; Preload bit counter, assert start bit for 8 clocks +bitloop: ; This loop will run 8 times (8n1 UART) + out pins, 1 ; Shift 1 bit from OSR to the first OUT pin + jmp x-- bitloop [6] ; Each loop iteration is 8 cycles. + + +% c-sdk { +#include "hardware/clocks.h" + +static inline void uart_tx_program_init(PIO pio, uint sm, uint offset, uint pin_tx, uint baud) { + // Tell PIO to initially drive output-high on the selected pin, then map PIO + // onto that pin with the IO muxes. + pio_sm_set_pins_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx); + pio_sm_set_pindirs_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx); + pio_gpio_init(pio, pin_tx); + + pio_sm_config c = uart_tx_program_get_default_config(offset); + + // OUT shifts to right, no autopull + sm_config_set_out_shift(&c, true, false, 32); + + // We are mapping both OUT and side-set to the same pin, because sometimes + // we need to assert user data onto the pin (with OUT) and sometimes + // assert constant values (start/stop bit) + sm_config_set_out_pins(&c, pin_tx, 1); + sm_config_set_sideset_pins(&c, pin_tx); + + // We only need TX, so get an 8-deep FIFO! + sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); + + // SM transmits 1 bit per 8 execution cycles. + float div = (float)clock_get_hz(clk_sys) / (8 * baud); + sm_config_set_clkdiv(&c, div); + + pio_sm_init(pio, sm, offset, &c); + pio_sm_set_enabled(pio, sm, true); +} + +static inline void uart_tx_program_putc(PIO pio, uint sm, char c) { + pio_sm_put_blocking(pio, sm, (uint32_t)c); +} + +static inline void uart_tx_program_puts(PIO pio, uint sm, const char *s) { + while (*s) + uart_tx_program_putc(pio, sm, *s++); +} + +%} diff --git a/SOFTWARE/pico_extras_import.cmake b/SOFTWARE/pico_extras_import.cmake new file mode 100644 index 0000000..706add0 --- /dev/null +++ b/SOFTWARE/pico_extras_import.cmake @@ -0,0 +1,62 @@ +# This is a copy of /external/pico_extras_import.cmake + +# This can be dropped into an external project to help locate pico-extras +# It should be include()ed prior to project() + +if (DEFINED ENV{PICO_EXTRAS_PATH} AND (NOT PICO_EXTRAS_PATH)) + set(PICO_EXTRAS_PATH $ENV{PICO_EXTRAS_PATH}) + message("Using PICO_EXTRAS_PATH from environment ('${PICO_EXTRAS_PATH}')") +endif () + +if (DEFINED ENV{PICO_EXTRAS_FETCH_FROM_GIT} AND (NOT PICO_EXTRAS_FETCH_FROM_GIT)) + set(PICO_EXTRAS_FETCH_FROM_GIT $ENV{PICO_EXTRAS_FETCH_FROM_GIT}) + message("Using PICO_EXTRAS_FETCH_FROM_GIT from environment ('${PICO_EXTRAS_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_EXTRAS_FETCH_FROM_GIT_PATH} AND (NOT PICO_EXTRAS_FETCH_FROM_GIT_PATH)) + set(PICO_EXTRAS_FETCH_FROM_GIT_PATH $ENV{PICO_EXTRAS_FETCH_FROM_GIT_PATH}) + message("Using PICO_EXTRAS_FETCH_FROM_GIT_PATH from environment ('${PICO_EXTRAS_FETCH_FROM_GIT_PATH}')") +endif () + +if (NOT PICO_EXTRAS_PATH) + if (PICO_EXTRAS_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_EXTRAS_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_EXTRAS_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + PICO_EXTRAS + GIT_REPOSITORY https://github.com/raspberrypi/pico-extras + GIT_TAG master + ) + if (NOT PICO_EXTRAS) + message("Downloading PICO EXTRAS") + FetchContent_Populate(PICO_EXTRAS) + set(PICO_EXTRAS_PATH ${PICO_EXTRAS_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + if (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../pico-extras") + set(PICO_EXTRAS_PATH ${PICO_SDK_PATH}/../pico-extras) + message("Defaulting PICO_EXTRAS_PATH as sibling of PICO_SDK_PATH: ${PICO_EXTRAS_PATH}") + else() + message(FATAL_ERROR + "PICO EXTRAS location was not specified. Please set PICO_EXTRAS_PATH or set PICO_EXTRAS_FETCH_FROM_GIT to on to fetch from git." + ) + endif() + endif () +endif () + +set(PICO_EXTRAS_PATH "${PICO_EXTRAS_PATH}" CACHE PATH "Path to the PICO EXTRAS") +set(PICO_EXTRAS_FETCH_FROM_GIT "${PICO_EXTRAS_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of PICO EXTRAS from git if not otherwise locatable") +set(PICO_EXTRAS_FETCH_FROM_GIT_PATH "${PICO_EXTRAS_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download EXTRAS") + +get_filename_component(PICO_EXTRAS_PATH "${PICO_EXTRAS_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_EXTRAS_PATH}) + message(FATAL_ERROR "Directory '${PICO_EXTRAS_PATH}' not found") +endif () + +set(PICO_EXTRAS_PATH ${PICO_EXTRAS_PATH} CACHE PATH "Path to the PICO EXTRAS" FORCE) + +add_subdirectory(${PICO_EXTRAS_PATH} pico_extras) \ No newline at end of file diff --git a/SOFTWARE/pico_sdk_import.cmake b/SOFTWARE/pico_sdk_import.cmake new file mode 100644 index 0000000..e02a33e --- /dev/null +++ b/SOFTWARE/pico_sdk_import.cmake @@ -0,0 +1,62 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the PICO SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of PICO SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG master + ) + if (NOT pico_sdk) + message("Downloading PICO SDK") + FetchContent_Populate(pico_sdk) + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "PICO SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the PICO SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the PICO SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE})