305 lines
13 KiB
C
305 lines
13 KiB
C
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/* ----------------------------------------------------------------------------
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* ATMEL Microcontroller Software Support
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* ----------------------------------------------------------------------------
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* Copyright (c) 2008, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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//------------------------------------------------------------------------------
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// Headers
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//------------------------------------------------------------------------------
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#include <board.h>
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#include <pio/pio.h>
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//------------------------------------------------------------------------------
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// Local macros
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//------------------------------------------------------------------------------
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/// Reads a register value. Useful to add trace information to read accesses.
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#define READ(peripheral, register) (peripheral->register)
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/// Writes data in a register. Useful to add trace information to write accesses.
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#define WRITE(peripheral, register, value) (peripheral->register = value)
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//------------------------------------------------------------------------------
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// Global functions
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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/// Changes the mapping of the chip so that the remap area mirrors the
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/// internal ROM or the EBI CS0 (depending on the BMS input).
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//------------------------------------------------------------------------------
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void BOARD_RemapRom(void)
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{
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WRITE(AT91C_BASE_MATRIX, MATRIX_MRCR, 0);
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}
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//------------------------------------------------------------------------------
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/// Changes the mapping of the chip so that the remap area mirrors the
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/// internal RAM.
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//------------------------------------------------------------------------------
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void BOARD_RemapRam(void)
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{
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WRITE(AT91C_BASE_MATRIX,
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MATRIX_MRCR,
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(AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D));
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}
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//------------------------------------------------------------------------------
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/// Initialize and configure the external SDRAM.
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//------------------------------------------------------------------------------
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void BOARD_ConfigureSdram(void)
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{
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volatile unsigned int i;
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static const Pin pinsSdram = PINS_SDRAM;
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volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
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// Enable corresponding PIOs
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PIO_Configure(&pinsSdram, 1);
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// Enable EBI chip select for the SDRAM
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WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
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// CFG Control Register
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
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| AT91C_SDRAMC_NR_13
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| AT91C_SDRAMC_CAS_2
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| AT91C_SDRAMC_NB_4_BANKS
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| AT91C_SDRAMC_DBW_32_BITS
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| AT91C_SDRAMC_TWR_2
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| AT91C_SDRAMC_TRC_7
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| AT91C_SDRAMC_TRP_2
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| AT91C_SDRAMC_TRCD_2
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| AT91C_SDRAMC_TRAS_5
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| AT91C_SDRAMC_TXSR_8);
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for (i = 0; i < 1000; i++);
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
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pSdram[0] = 0x00000000;
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
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pSdram[0] = 0x00000000; // Perform PRCHG
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for (i = 0; i < 10000; i++);
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
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pSdram[1] = 0x00000001; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
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pSdram[2] = 0x00000002; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
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pSdram[3] = 0x00000003; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
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pSdram[4] = 0x00000004; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
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pSdram[5] = 0x00000005; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
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pSdram[6] = 0x00000006; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
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pSdram[7] = 0x00000007; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
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pSdram[8] = 0x00000008; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
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pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000); // Set Refresh Timer
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
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pSdram[0] = 0x00000000; // Perform Normal mode
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}
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//------------------------------------------------------------------------------
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/// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings).
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//------------------------------------------------------------------------------
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void BOARD_ConfigureSdram48MHz(void)
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{
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volatile unsigned int i;
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static const Pin pinsSdram = PINS_SDRAM;
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volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
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// Enable corresponding PIOs
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PIO_Configure(&pinsSdram, 1);
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// Enable EBI chip select for the SDRAM
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WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
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// CFG Control Register
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
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| AT91C_SDRAMC_NR_13
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| AT91C_SDRAMC_CAS_2
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| AT91C_SDRAMC_NB_4_BANKS
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| AT91C_SDRAMC_DBW_32_BITS
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| AT91C_SDRAMC_TWR_1
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| AT91C_SDRAMC_TRC_4
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| AT91C_SDRAMC_TRP_1
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| AT91C_SDRAMC_TRCD_1
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| AT91C_SDRAMC_TRAS_2
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| AT91C_SDRAMC_TXSR_3);
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for (i = 0; i < 1000; i++);
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
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pSdram[0] = 0x00000000;
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
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pSdram[0] = 0x00000000; // Perform PRCHG
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for (i = 0; i < 10000; i++);
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
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pSdram[1] = 0x00000001; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
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pSdram[2] = 0x00000002; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
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pSdram[3] = 0x00000003; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
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pSdram[4] = 0x00000004; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
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pSdram[5] = 0x00000005; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
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pSdram[6] = 0x00000006; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
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pSdram[7] = 0x00000007; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
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pSdram[8] = 0x00000008; // Perform CBR
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
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pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000); // Set Refresh Timer
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WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
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pSdram[0] = 0x00000000; // Perform Normal mode
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}
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//------------------------------------------------------------------------------
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/// Configures the EBI for NandFlash access. Pins must be configured after or
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/// before calling this function.
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//------------------------------------------------------------------------------
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void BOARD_ConfigureNandFlash(unsigned char busWidth)
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{
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// Configure EBI
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AT91C_BASE_MATRIX->MATRIX_EBI |= AT91C_MATRIX_CS3A_SM;
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// Configure SMC
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AT91C_BASE_SMC->SMC_SETUP3 = 0x00000000;
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AT91C_BASE_SMC->SMC_PULSE3 = 0x00030003;
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AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005;
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AT91C_BASE_SMC->SMC_CTRL3 = 0x00002003;
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if (busWidth == 8) {
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AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
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}
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else if (busWidth == 16) {
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AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
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}
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}
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//------------------------------------------------------------------------------
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/// Configures the EBI for NandFlash access at 48MHz. Pins must be configured
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/// after or before calling this function.
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//------------------------------------------------------------------------------
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void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth)
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{
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// Configure EBI
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AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM;
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// Configure SMC
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AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001;
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AT91C_BASE_SMC->SMC_PULSE3 = 0x04030302;
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AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070004;
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AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE
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| AT91C_SMC_WRITEMODE
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| AT91C_SMC_NWAITM_NWAIT_DISABLE
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| ((0x1 << 16) & AT91C_SMC_TDF));
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if (busWidth == 8) {
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AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
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}
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else if (busWidth == 16) {
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AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
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}
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}
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//------------------------------------------------------------------------------
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/// Configures the EBI for NorFlash access at 48MHz.
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/// \Param busWidth Bus width
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//------------------------------------------------------------------------------
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void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth)
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{
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// Configure SMC
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AT91C_BASE_SMC->SMC_SETUP0 = 0x00000001;
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AT91C_BASE_SMC->SMC_PULSE0 = 0x07070703;
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AT91C_BASE_SMC->SMC_CYCLE0 = 0x00070007;
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AT91C_BASE_SMC->SMC_CTRL0 = (AT91C_SMC_READMODE
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| AT91C_SMC_WRITEMODE
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| AT91C_SMC_NWAITM_NWAIT_DISABLE
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| ((0x1 << 16) & AT91C_SMC_TDF));
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if (busWidth == 8) {
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AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
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}
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else if (busWidth == 16) {
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AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
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}
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else if (busWidth == 32) {
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AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS;
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}
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}
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//------------------------------------------------------------------------------
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/// Set flash wait states in the EFC for 48MHz
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//------------------------------------------------------------------------------
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void BOARD_ConfigureFlash48MHz(void)
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{
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// Set flash wait states
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//----------------------
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AT91C_BASE_EFC->EFC_FMR = 6 << 8;
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}
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