init
This commit is contained in:
312
Common/ARMv8M/reg_tests/GCC/ARM_CM23/non_secure/reg_test_asm.c
Normal file
312
Common/ARMv8M/reg_tests/GCC/ARM_CM23/non_secure/reg_test_asm.c
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/*
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* FreeRTOS V202212.00
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* "Reg tests" - These tests fill the registers with known values, then check
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* that each register maintains its expected value for the lifetime of the
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* task. Each task uses a different set of values. The reg test tasks execute
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* with a very low priority, so get preempted very frequently. A register
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* containing an unexpected value is indicative of an error in the context
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* switching mechanism.
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*/
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#include "reg_test_asm.h"
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/*-----------------------------------------------------------*/
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void vRegTest1Asm_NonSecure( void ) /* __attribute__(( naked )) */
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{
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__asm volatile
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(
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".extern ulRegTest1LoopCounter \n"
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".syntax unified \n"
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" \n"
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" /* Fill the core registers with known values. */ \n"
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" movs r1, #101 \n"
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" movs r2, #102 \n"
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" movs r3, #103 \n"
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" movs r4, #104 \n"
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" movs r5, #105 \n"
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" movs r6, #106 \n"
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" movs r7, #107 \n"
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" movs r0, #108 \n"
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" mov r8, r0 \n"
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" movs r0, #109 \n"
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" mov r9, r0 \n"
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" movs r0, #110 \n"
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" mov r10, r0 \n"
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" movs r0, #111 \n"
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" mov r11, r0 \n"
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" movs r0, #112 \n"
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" mov r12, r0 \n"
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" movs r0, #100 \n"
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" \n"
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"reg1_loop: \n"
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" \n"
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" /* Verify that core registers contain correct values. */ \n"
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" cmp r0, #100 \n"
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" bne reg1_error_loop \n"
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" cmp r1, #101 \n"
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" bne reg1_error_loop \n"
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" cmp r2, #102 \n"
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" bne reg1_error_loop \n"
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" cmp r3, #103 \n"
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" bne reg1_error_loop \n"
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" cmp r4, #104 \n"
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" bne reg1_error_loop \n"
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" cmp r5, #105 \n"
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" bne reg1_error_loop \n"
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" cmp r6, #106 \n"
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" bne reg1_error_loop \n"
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" cmp r7, #107 \n"
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" bne reg1_error_loop \n"
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" movs r0, #108 \n"
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" cmp r8, r0 \n"
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" bne reg1_error_loop \n"
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" movs r0, #109 \n"
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" cmp r9, r0 \n"
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" bne reg1_error_loop \n"
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" movs r0, #110 \n"
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" cmp r10, r0 \n"
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" bne reg1_error_loop \n"
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" movs r0, #111 \n"
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" cmp r11, r0 \n"
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" bne reg1_error_loop \n"
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" movs r0, #112 \n"
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" cmp r12, r0 \n"
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" bne reg1_error_loop \n"
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" \n"
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" /* Everything passed, inc the loop counter. */ \n"
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" push { r1 } \n"
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" ldr r0, =ulRegTest1LoopCounter \n"
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" ldr r1, [r0] \n"
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" adds r1, r1, #1 \n"
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" str r1, [r0] \n"
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" \n"
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" /* Yield to increase test coverage. */ \n"
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" movs r0, #0x01 \n"
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" ldr r1, =0xe000ed04 \n" /* NVIC_ICSR. */
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" lsls r0, #28 \n" /* Shift to PendSV bit. */
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" str r0, [r1] \n"
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" dsb \n"
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" pop { r1 } \n"
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" \n"
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" /* Start again. */ \n"
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" movs r0, #100 \n"
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" b reg1_loop \n"
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" \n"
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"reg1_error_loop: \n"
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" /* If this line is hit then there was an error in \n"
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" * a core register value. The loop ensures the \n"
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" * loop counter stops incrementing. */ \n"
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" b reg1_error_loop \n"
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" nop \n"
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);
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}
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/*-----------------------------------------------------------*/
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void vRegTest2Asm_NonSecure( void ) /* __attribute__(( naked )) */
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{
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__asm volatile
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(
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".extern ulRegTest2LoopCounter \n"
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".syntax unified \n"
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" \n"
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" /* Fill the core registers with known values. */ \n"
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" movs r1, #1 \n"
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" movs r2, #2 \n"
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" movs r3, #3 \n"
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" movs r4, #4 \n"
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" movs r5, #5 \n"
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" movs r6, #6 \n"
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" movs r7, #7 \n"
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" movs r0, #8 \n"
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" mov r8, r0 \n"
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" movs r0, #9 \n"
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" mov r9, r0 \n"
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" movs r0, #10 \n"
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" mov r10, r0 \n"
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" movs r0, #11 \n"
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" mov r11, r0 \n"
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" movs r0, #12 \n"
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" mov r12, r0 \n"
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" movs r0, #10 \n"
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" \n"
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"reg2_loop: \n"
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" \n"
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" /* Verify that core registers contain correct values. */ \n"
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" cmp r0, #10 \n"
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" bne reg2_error_loop \n"
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" cmp r1, #1 \n"
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" bne reg2_error_loop \n"
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" cmp r2, #2 \n"
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" bne reg2_error_loop \n"
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" cmp r3, #3 \n"
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" bne reg2_error_loop \n"
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" cmp r4, #4 \n"
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" bne reg2_error_loop \n"
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" cmp r5, #5 \n"
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" bne reg2_error_loop \n"
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" cmp r6, #6 \n"
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" bne reg2_error_loop \n"
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" cmp r7, #7 \n"
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" bne reg2_error_loop \n"
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" movs r0, #8 \n"
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" cmp r8, r0 \n"
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" bne reg2_error_loop \n"
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" movs r0, #9 \n"
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" cmp r9, r0 \n"
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" bne reg2_error_loop \n"
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" movs r0, #10 \n"
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" cmp r10, r0 \n"
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" bne reg2_error_loop \n"
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" movs r0, #11 \n"
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" cmp r11, r0 \n"
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" bne reg2_error_loop \n"
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" movs r0, #12 \n"
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" cmp r12, r0 \n"
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" bne reg2_error_loop \n"
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" \n"
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" /* Everything passed, inc the loop counter. */ \n"
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" push { r1 } \n"
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" ldr r0, =ulRegTest2LoopCounter \n"
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" ldr r1, [r0] \n"
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" adds r1, r1, #1 \n"
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" str r1, [r0] \n"
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" pop { r1 } \n"
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" \n"
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" /* Start again. */ \n"
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" movs r0, #10 \n"
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" b reg2_loop \n"
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" \n"
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"reg2_error_loop: \n"
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" /* If this line is hit then there was an error in \n"
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" * a core register value. The loop ensures the \n"
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" * loop counter stops incrementing. */ \n"
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" b reg2_error_loop \n"
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" nop \n"
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);
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}
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/*-----------------------------------------------------------*/
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void vRegTestAsm_NonSecureCallback( void )
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{
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__asm volatile
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(
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".syntax unified \n"
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" \n"
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" /* Store callee saved registers. */ \n"
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" push { r4-r7 } \n"
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" mov r0, r8 \n"
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" mov r1, r9 \n"
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" mov r2, r10 \n"
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" mov r3, r11 \n"
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" mov r4, r12 \n"
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" push { r0-r4 } \n"
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" \n"
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" /* Fill the core registers with known values. */ \n"
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" movs r1, #151 \n"
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" movs r2, #152 \n"
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" movs r3, #153 \n"
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" movs r4, #154 \n"
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" movs r5, #155 \n"
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" movs r6, #156 \n"
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" movs r7, #157 \n"
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" movs r0, #158 \n"
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" mov r8, r0 \n"
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" movs r0, #159 \n"
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" mov r9, r0 \n"
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" movs r0, #160 \n"
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" mov r10, r0 \n"
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" movs r0, #161 \n"
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" mov r11, r0 \n"
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" movs r0, #162 \n"
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" mov r12, r0 \n"
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" movs r0, #150 \n"
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" \n"
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" /* Force a context switch by pending non-secure sv. */ \n"
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" push { r0, r1 } \n"
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" movs r0, #0x01 \n"
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" ldr r1, =0xe000ed04 \n" /* NVIC_ICSR. */
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" lsls r0, #28 \n" /* Shift to PendSV bit. */
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" str r0, [r1] \n"
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" dsb \n"
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" pop { r0, r1 } \n"
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" \n"
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" /* Verify that core registers contain correct values. */ \n"
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" cmp r0, #150 \n"
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" bne reg_nscb_error_loop \n"
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" cmp r1, #151 \n"
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" bne reg_nscb_error_loop \n"
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" cmp r2, #152 \n"
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" bne reg_nscb_error_loop \n"
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" cmp r3, #153 \n"
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" bne reg_nscb_error_loop \n"
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" cmp r4, #154 \n"
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" bne reg_nscb_error_loop \n"
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" cmp r5, #155 \n"
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" bne reg_nscb_error_loop \n"
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" cmp r6, #156 \n"
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" bne reg_nscb_error_loop \n"
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" cmp r7, #157 \n"
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" bne reg_nscb_error_loop \n"
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" movs r0, #158 \n"
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" cmp r8, r0 \n"
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" bne reg_nscb_error_loop \n"
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" movs r0, #159 \n"
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" cmp r9, r0 \n"
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" bne reg_nscb_error_loop \n"
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" movs r0, #160 \n"
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" cmp r10, r0 \n"
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" bne reg_nscb_error_loop \n"
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" movs r0, #161 \n"
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" cmp r11, r0 \n"
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" bne reg_nscb_error_loop \n"
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" movs r0, #162 \n"
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" cmp r12, r0 \n"
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" bne reg_nscb_error_loop \n"
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" \n"
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" /* Everything passed, finish. */ \n"
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" b reg_nscb_success \n"
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" \n"
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"reg_nscb_error_loop : \n"
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" /* If this line is hit then there was an error in \n"
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" * a core register value. The loop ensures the \n"
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" * loop counter stops incrementing. */ \n"
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" b reg_nscb_error_loop \n"
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" nop \n"
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" \n"
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"reg_nscb_success: \n"
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" /* Restore callee saved registers. */ \n"
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" pop { r0-r4 } \n"
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" mov r8, r0 \n"
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" mov r9, r1 \n"
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" mov r10, r2 \n"
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" mov r11, r3 \n"
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" mov r12, r4 \n"
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" pop { r4-r7 } \n"
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);
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}
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/*-----------------------------------------------------------*/
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@@ -0,0 +1,46 @@
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/*
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* FreeRTOS V202212.00
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||||
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
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||||
*
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*/
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#ifndef REG_TEST_ASM_H
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#define REG_TEST_ASM_H
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/**
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* @brief Functions that implement reg tests in assembly.
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*
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* These are called from the FreeRTOS tasks on the non-secure side.
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*/
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void vRegTest1Asm_NonSecure( void ) __attribute__( ( naked ) );
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void vRegTest2Asm_NonSecure( void ) __attribute__( ( naked ) );
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/**
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* @brief Function that implements reg tests in assembly.
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*
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* This is passed as function pointer to the secure side and called
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* from the secure side.
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*/
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void vRegTestAsm_NonSecureCallback( void );
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#endif /* REG_TEST_ASM_H */
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Reference in New Issue
Block a user