594 lines
37 KiB
C
594 lines
37 KiB
C
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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* File Name : stm32fxxx_eth_map.h
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* Author : MCD Application Team
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* Version : VX.Y.Z
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* Date : mm/dd/2008
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* Description : This file contains all ETHERNET peripheral register's
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* definitions and memory mapping.
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********************************************************************************
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32FXXX_ETH_MAP_H
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#define __STM32FXXX_ETH_MAP_H
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#ifndef EXT
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#define EXT extern
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#endif /* EXT */
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/* Includes ------------------------------------------------------------------*/
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#include "stm32fxxx_eth_conf.h"
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#include "stm32f10x_type.h"
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/* Exported types ------------------------------------------------------------*/
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/******************************************************************************/
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/* Ethernet Peripheral registers structures */
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/******************************************************************************/
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typedef struct
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{
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vu32 MACCR;
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vu32 MACFFR;
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vu32 MACHTHR;
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vu32 MACHTLR;
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vu32 MACMIIAR;
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vu32 MACMIIDR;
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vu32 MACFCR;
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vu32 MACVLANTR;
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vu32 RESERVED0[2];
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vu32 MACRWUFFR;
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vu32 MACPMTCSR;
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vu32 RESERVED1[2];
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vu32 MACSR;
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vu32 MACIMR;
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vu32 MACA0HR;
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vu32 MACA0LR;
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vu32 MACA1HR;
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vu32 MACA1LR;
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vu32 MACA2HR;
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vu32 MACA2LR;
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vu32 MACA3HR;
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vu32 MACA3LR;
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} ETH_MAC_TypeDef;
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typedef struct
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{
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vu32 MMCCR;
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vu32 MMCRIR;
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vu32 MMCTIR;
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vu32 MMCRIMR;
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vu32 MMCTIMR;
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vu32 RESERVED0[14];
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vu32 MMCTGFSCCR;
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vu32 MMCTGFMSCCR;
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vu32 RESERVED1[5];
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vu32 MMCTGFCR;
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vu32 RESERVED2[10];
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vu32 MMCRFCECR;
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vu32 MMCRFAER;
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vu32 RESERVED3[10];
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vu32 MMCRGUFCR;
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} ETH_MMC_TypeDef;
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typedef struct
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{
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vu32 PTPTSCR;
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vu32 PTPSSIR;
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vu32 PTPTSHR;
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vu32 PTPTSLR;
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vu32 PTPTSHUR;
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vu32 PTPTSLUR;
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vu32 PTPTSAR;
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vu32 PTPTTHR;
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vu32 PTPTTLR;
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} ETH_PTP_TypeDef;
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typedef struct
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{
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vu32 DMABMR;
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vu32 DMATPDR;
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vu32 DMARPDR;
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vu32 DMARDLAR;
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vu32 DMATDLAR;
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vu32 DMASR;
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vu32 DMAOMR;
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vu32 DMAIER;
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vu32 DMAMFBOCR;
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vu32 RESERVED0[9];
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vu32 DMACHTDR;
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vu32 DMACHRDR;
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vu32 DMACHTBAR;
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vu32 DMACHRBAR;
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} ETH_DMA_TypeDef;
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/******************************************************************************/
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/* Ethernet MAC Registers bits definitions */
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/******************************************************************************/
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//#define IPNAME_REGNAME_BITNAME /* BIT MASK */
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/* Bit definition for Ethernet MAC Control Register register */
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#define ETH_MACCR_WD ((u32)0x00800000) /* Watchdog disable */
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#define ETH_MACCR_JD ((u32)0x00400000) /* Jabber disable */
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#define ETH_MACCR_JFE ((u32)0x00100000) /* Jumbo frame enable */
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#define ETH_MACCR_IFG ((u32)0x000E0000) /* Inter-frame gap */
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#define ETH_MACCR_IFG_96Bit ((u32)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
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#define ETH_MACCR_IFG_88Bit ((u32)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
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#define ETH_MACCR_IFG_80Bit ((u32)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
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#define ETH_MACCR_IFG_72Bit ((u32)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
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#define ETH_MACCR_IFG_64Bit ((u32)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
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#define ETH_MACCR_IFG_56Bit ((u32)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
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#define ETH_MACCR_IFG_48Bit ((u32)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
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#define ETH_MACCR_IFG_40Bit ((u32)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
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#define ETH_MACCR_CSD ((u32)0x00010000) /* Carrier sense disable (during transmission) */
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#define ETH_MACCR_FES ((u32)0x00004000) /* Fast ethernet speed */
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#define ETH_MACCR_ROD ((u32)0x00002000) /* Receive own disable */
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#define ETH_MACCR_LM ((u32)0x00001000) /* loopback mode */
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#define ETH_MACCR_DM ((u32)0x00000800) /* Duplex mode */
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#define ETH_MACCR_IPCO ((u32)0x00000400) /* IP Checksum offload */
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#define ETH_MACCR_RD ((u32)0x00000200) /* Retry disable */
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#define ETH_MACCR_APCS ((u32)0x00000080) /* Automatic Pad/CRC stripping */
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#define ETH_MACCR_BL ((u32)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
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a transmission attempt during retries after a collision: 0 =< r <2^k */
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#define ETH_MACCR_BL_10 ((u32)0x00000000) /* k = min (n, 10) */
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#define ETH_MACCR_BL_8 ((u32)0x00000020) /* k = min (n, 8) */
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#define ETH_MACCR_BL_4 ((u32)0x00000040) /* k = min (n, 4) */
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#define ETH_MACCR_BL_1 ((u32)0x00000060) /* k = min (n, 1) */
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#define ETH_MACCR_DC ((u32)0x00000010) /* Defferal check */
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#define ETH_MACCR_TE ((u32)0x00000008) /* Transmitter enable */
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#define ETH_MACCR_RE ((u32)0x00000004) /* Receiver enable */
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/* Bit definition for Ethernet MAC Frame Filter Register */
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#define ETH_MACFFR_RA ((u32)0x80000000) /* Receive all */
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#define ETH_MACFFR_HPF ((u32)0x00000400) /* Hash or perfect filter */
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#define ETH_MACFFR_SAF ((u32)0x00000200) /* Source address filter enable */
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#define ETH_MACFFR_SAIF ((u32)0x00000100) /* SA inverse filtering */
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#define ETH_MACFFR_PCF ((u32)0x000000C0) /* Pass control frames: 3 cases */
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#define ETH_MACFFR_PCF_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */
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#define ETH_MACFFR_PCF_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
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#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
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#define ETH_MACFFR_BFD ((u32)0x00000020) /* Broadcast frame disable */
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#define ETH_MACFFR_PAM ((u32)0x00000010) /* Pass all mutlicast */
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#define ETH_MACFFR_DAIF ((u32)0x00000008) /* DA Inverse filtering */
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#define ETH_MACFFR_HM ((u32)0x00000004) /* Hash multicast */
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#define ETH_MACFFR_HU ((u32)0x00000002) /* Hash unicast */
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#define ETH_MACFFR_PM ((u32)0x00000001) /* Promiscuous mode */
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/* Bit definition for Ethernet MAC Hash Table High Register */
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#define ETH_MACHTHR_HTH ((u32)0xFFFFFFFF) /* Hash table high */
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/* Bit definition for Ethernet MAC Hash Table Low Register */
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#define ETH_MACHTLR_HTL ((u32)0xFFFFFFFF) /* Hash table low */
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/* Bit definition for Ethernet MAC MII Address Register */
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#define ETH_MACMIIAR_PA ((u32)0x0000F800) /* Physical layer address */
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#define ETH_MACMIIAR_MR ((u32)0x000007C0) /* MII register in the selected PHY */
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#define ETH_MACMIIAR_CR ((u32)0x0000001C) /* CR clock range: 6 cases */
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#define ETH_MACMIIAR_CR_Div42 ((u32)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
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#define ETH_MACMIIAR_CR_Div16 ((u32)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
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#define ETH_MACMIIAR_CR_Div26 ((u32)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
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#define ETH_MACMIIAR_MW ((u32)0x00000002) /* MII write */
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#define ETH_MACMIIAR_MB ((u32)0x00000001) /* MII busy */
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/* Bit definition for Ethernet MAC MII Data Register */
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#define ETH_MACMIIDR_MD ((u32)0x0000FFFF) /* MII data: read/write data from/to PHY */
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/* Bit definition for Ethernet MAC Flow Control Register */
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#define ETH_MACFCR_PT ((u32)0xFFFF0000) /* Pause time */
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#define ETH_MACFCR_ZQPD ((u32)0x00000080) /* Zero-quanta pause disable */
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#define ETH_MACFCR_PLT ((u32)0x00000030) /* Pause low threshold: 4 cases */
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#define ETH_MACFCR_PLT_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */
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#define ETH_MACFCR_PLT_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */
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#define ETH_MACFCR_PLT_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */
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#define ETH_MACFCR_PLT_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */
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#define ETH_MACFCR_UPFD ((u32)0x00000008) /* Unicast pause frame detect */
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#define ETH_MACFCR_RFCE ((u32)0x00000004) /* Receive flow control enable */
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#define ETH_MACFCR_TFCE ((u32)0x00000002) /* Transmit flow control enable */
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#define ETH_MACFCR_FCBBPA ((u32)0x00000001) /* Flow control busy/backpressure activate */
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/* Bit definition for Ethernet MAC VLAN Tag Register */
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#define ETH_MACVLANTR_VLANTC ((u32)0x00010000) /* 12-bit VLAN tag comparison */
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#define ETH_MACVLANTR_VLANTI ((u32)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
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/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
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#define ETH_MACRWUFFR_D ((u32)0xFFFFFFFF) /* Wake-up frame filter register data */
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/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
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Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
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/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
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Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
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Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
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Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
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Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
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RSVD - Filter1 Command - RSVD - Filter0 Command
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Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
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Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
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Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
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/* Bit definition for Ethernet MAC PMT Control and Status Register */
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#define ETH_MACPMTCSR_WFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
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#define ETH_MACPMTCSR_GU ((u32)0x00000200) /* Global Unicast */
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#define ETH_MACPMTCSR_WFR ((u32)0x00000040) /* Wake-Up Frame Received */
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#define ETH_MACPMTCSR_MPR ((u32)0x00000020) /* Magic Packet Received */
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#define ETH_MACPMTCSR_WFE ((u32)0x00000004) /* Wake-Up Frame Enable */
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#define ETH_MACPMTCSR_MPE ((u32)0x00000002) /* Magic Packet Enable */
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#define ETH_MACPMTCSR_PD ((u32)0x00000001) /* Power Down */
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/* Bit definition for Ethernet MAC Status Register */
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#define ETH_MACSR_TSTS ((u32)0x00000200) /* Time stamp trigger status */
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#define ETH_MACSR_MMCTS ((u32)0x00000040) /* MMC transmit status */
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#define ETH_MACSR_MMMCRS ((u32)0x00000020) /* MMC receive status */
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#define ETH_MACSR_MMCS ((u32)0x00000010) /* MMC status */
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#define ETH_MACSR_PMTS ((u32)0x00000008) /* PMT status */
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/* Bit definition for Ethernet MAC Interrupt Mask Register */
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#define ETH_MACIMR_TSTIM ((u32)0x00000200) /* Time stamp trigger interrupt mask */
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#define ETH_MACIMR_PMTIM ((u32)0x00000008) /* PMT interrupt mask */
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/* Bit definition for Ethernet MAC Address0 High Register */
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#define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) /* MAC address0 high */
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/* Bit definition for Ethernet MAC Address0 Low Register */
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#define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) /* MAC address0 low */
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/* Bit definition for Ethernet MAC Address1 High Register */
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#define ETH_MACA1HR_AE ((u32)0x80000000) /* Address enable */
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#define ETH_MACA1HR_SA ((u32)0x40000000) /* Source address */
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#define ETH_MACA1HR_MBC ((u32)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
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#define ETH_MACA1HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
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#define ETH_MACA1HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
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#define ETH_MACA1HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
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#define ETH_MACA1HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
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#define ETH_MACA1HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
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#define ETH_MACA1HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [7:0] */
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#define ETH_MACA1HR_MACA1H ((u32)0x0000FFFF) /* MAC address1 high */
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/* Bit definition for Ethernet MAC Address1 Low Register */
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#define ETH_MACA1LR_MACA1L ((u32)0xFFFFFFFF) /* MAC address1 low */
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/* Bit definition for Ethernet MAC Address2 High Register */
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#define ETH_MACA2HR_AE ((u32)0x80000000) /* Address enable */
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#define ETH_MACA2HR_SA ((u32)0x40000000) /* Source address */
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#define ETH_MACA2HR_MBC ((u32)0x3F000000) /* Mask byte control */
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#define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
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#define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
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#define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
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#define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
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#define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
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#define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */
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#define ETH_MACA2HR_MACA2H ((u32)0x0000FFFF) /* MAC address1 high */
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/* Bit definition for Ethernet MAC Address2 Low Register */
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#define ETH_MACA2LR_MACA2L ((u32)0xFFFFFFFF) /* MAC address2 low */
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/* Bit definition for Ethernet MAC Address3 High Register */
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#define ETH_MACA3HR_AE ((u32)0x80000000) /* Address enable */
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#define ETH_MACA3HR_SA ((u32)0x40000000) /* Source address */
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#define ETH_MACA3HR_MBC ((u32)0x3F000000) /* Mask byte control */
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#define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
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#define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
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#define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
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#define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
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#define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
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#define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */
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#define ETH_MACA3HR_MACA3H ((u32)0x0000FFFF) /* MAC address3 high */
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/* Bit definition for Ethernet MAC Address3 Low Register */
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#define ETH_MACA3LR_MACA3L ((u32)0xFFFFFFFF) /* MAC address3 low */
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/******************************************************************************/
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/* Ethernet MMC Registers bits definition */
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/******************************************************************************/
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/* Bit definition for Ethernet MMC Contol Register */
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#define ETH_MMCCR_MCF ((u32)0x00000008) /* MMC Counter Freeze */
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#define ETH_MMCCR_ROR ((u32)0x00000004) /* Reset on Read */
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#define ETH_MMCCR_CSR ((u32)0x00000002) /* Counter Stop Rollover */
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#define ETH_MMCCR_CR ((u32)0x00000001) /* Counters Reset */
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/* Bit definition for Ethernet MMC Receive Interrupt Register */
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#define ETH_MMCRIR_RGUFS ((u32)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
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#define ETH_MMCRIR_RFAES ((u32)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
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#define ETH_MMCRIR_RFCES ((u32)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
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/* Bit definition for Ethernet MMC Transmit Interrupt Register */
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#define ETH_MMCTIR_TGFS ((u32)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
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#define ETH_MMCTIR_TGFMSCS ((u32)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
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#define ETH_MMCTIR_TGFSCS ((u32)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
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/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
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#define ETH_MMCRIMR_RGUFM ((u32)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
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#define ETH_MMCRIMR_RFAEM ((u32)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
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#define ETH_MMCRIMR_RFCEM ((u32)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
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/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
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#define ETH_MMCTIMR_TGFM ((u32)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
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#define ETH_MMCTIMR_TGFMSCM ((u32)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
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#define ETH_MMCTIMR_TGFSCM ((u32)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
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/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
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#define ETH_MMCTGFSCCR_TGFSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
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/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
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#define ETH_MMCTGFMSCCR_TGFMSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
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/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
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#define ETH_MMCTGFCR_TGFC ((u32)0xFFFFFFFF) /* Number of good frames transmitted. */
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/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
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#define ETH_MMCRFCECR_RFCEC ((u32)0xFFFFFFFF) /* Number of frames received with CRC error. */
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/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
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#define ETH_MMCRFAECR_RFAEC ((u32)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
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/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
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#define ETH_MMCRGUFCR_RGUFC ((u32)0xFFFFFFFF) /* Number of good unicast frames received. */
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/******************************************************************************/
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/* Ethernet PTP Registers bits definition */
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/******************************************************************************/
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/* Bit definition for Ethernet PTP Time Stamp Contol Register */
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#define ETH_PTPTSCR_TSARU ((u32)0x00000020) /* Addend register update */
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#define ETH_PTPTSCR_TSITE ((u32)0x00000010) /* Time stamp interrupt trigger enable */
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#define ETH_PTPTSCR_TSSTU ((u32)0x00000008) /* Time stamp update */
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#define ETH_PTPTSCR_TSSTI ((u32)0x00000004) /* Time stamp initialize */
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#define ETH_PTPTSCR_TSFCU ((u32)0x00000002) /* Time stamp fine or coarse update */
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#define ETH_PTPTSCR_TSE ((u32)0x00000001) /* Time stamp enable */
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/* Bit definition for Ethernet PTP Sub-Second Increment Register */
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#define ETH_PTPSSIR_STSSI ((u32)0x000000FF) /* System time Sub-second increment value */
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/* Bit definition for Ethernet PTP Time Stamp High Register */
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#define ETH_PTPTSHR_STS ((u32)0xFFFFFFFF) /* System Time second */
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/* Bit definition for Ethernet PTP Time Stamp Low Register */
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#define ETH_PTPTSLR_STPNS ((u32)0x80000000) /* System Time Positive or negative time */
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#define ETH_PTPTSLR_STSS ((u32)0x7FFFFFFF) /* System Time sub-seconds */
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/* Bit definition for Ethernet PTP Time Stamp High Update Register */
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#define ETH_PTPTSHUR_TSUS ((u32)0xFFFFFFFF) /* Time stamp update seconds */
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/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
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#define ETH_PTPTSLUR_TSUPNS ((u32)0x80000000) /* Time stamp update Positive or negative time */
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#define ETH_PTPTSLUR_TSUSS ((u32)0x7FFFFFFF) /* Time stamp update sub-seconds */
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/* Bit definition for Ethernet PTP Time Stamp Addend Register */
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#define ETH_PTPTSAR_TSA ((u32)0xFFFFFFFF) /* Time stamp addend */
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/* Bit definition for Ethernet PTP Target Time High Register */
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#define ETH_PTPTTHR_TTSH ((u32)0xFFFFFFFF) /* Target time stamp high */
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/* Bit definition for Ethernet PTP Target Time Low Register */
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#define ETH_PTPTTLR_TTSL ((u32)0xFFFFFFFF) /* Target time stamp low */
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/******************************************************************************/
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/* Ethernet DMA Registers bits definition */
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/******************************************************************************/
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/* Bit definition for Ethernet DMA Bus Mode Register */
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#define ETH_DMABMR_AAB ((u32)0x02000000) /* Address-Aligned beats */
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#define ETH_DMABMR_FPM ((u32)0x01000000) /* 4xPBL mode */
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#define ETH_DMABMR_USP ((u32)0x00800000) /* Use separate PBL */
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#define ETH_DMABMR_RDP ((u32)0x007E0000) /* RxDMA PBL */
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/* Values to be confirmed: maybe they are inversed */
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#define ETH_DMABMR_RDP_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
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#define ETH_DMABMR_RDP_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
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#define ETH_DMABMR_RDP_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
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#define ETH_DMABMR_RDP_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
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#define ETH_DMABMR_RDP_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
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#define ETH_DMABMR_RDP_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
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#define ETH_DMABMR_RDP_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
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#define ETH_DMABMR_RDP_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
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#define ETH_DMABMR_RDP_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
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#define ETH_DMABMR_RDP_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
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#define ETH_DMABMR_RDP_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
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#define ETH_DMABMR_RDP_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
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#define ETH_DMABMR_FB ((u32)0x00010000) /* Fixed Burst */
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#define ETH_DMABMR_RTPR ((u32)0x0000C000) /* Rx Tx priority ratio */
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#define ETH_DMABMR_RTPR_1_1 ((u32)0x00000000) /* Rx Tx priority ratio */
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#define ETH_DMABMR_RTPR_2_1 ((u32)0x00004000) /* Rx Tx priority ratio */
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#define ETH_DMABMR_RTPR_3_1 ((u32)0x00008000) /* Rx Tx priority ratio */
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#define ETH_DMABMR_RTPR_4_1 ((u32)0x0000C000) /* Rx Tx priority ratio */
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#define ETH_DMABMR_PBL ((u32)0x00003F00) /* Programmable burst length */
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/* Values to be confirmed: maybe they are inversed */
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#define ETH_DMABMR_PBL_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
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#define ETH_DMABMR_PBL_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
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#define ETH_DMABMR_PBL_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
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#define ETH_DMABMR_PBL_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
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#define ETH_DMABMR_PBL_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
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#define ETH_DMABMR_PBL_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
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#define ETH_DMABMR_PBL_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
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#define ETH_DMABMR_PBL_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
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#define ETH_DMABMR_PBL_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
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#define ETH_DMABMR_PBL_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
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#define ETH_DMABMR_PBL_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
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#define ETH_DMABMR_PBL_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
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#define ETH_DMABMR_DSL ((u32)0x0000007C) /* Descriptor Skip Length */
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#define ETH_DMABMR_DA ((u32)0x00000002) /* DMA arbitration scheme */
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#define ETH_DMABMR_SR ((u32)0x00000001) /* Software reset */
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/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
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#define ETH_DMATPDR_TPD ((u32)0xFFFFFFFF) /* Transmit poll demand */
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/* Bit definition for Ethernet DMA Receive Poll Demand Register */
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#define ETH_DMARPDR_RPD ((u32)0xFFFFFFFF) /* Receive poll demand */
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/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
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#define ETH_DMARDLAR_SRL ((u32)0xFFFFFFFF) /* Start of receive list */
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/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
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#define ETH_DMATDLAR_STL ((u32)0xFFFFFFFF) /* Start of transmit list */
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/* Bit definition for Ethernet DMA Status Register */
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#define ETH_DMASR_TSTS ((u32)0x20000000) /* Time-stamp trigger status */
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#define ETH_DMASR_PMTS ((u32)0x10000000) /* PMT status */
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#define ETH_DMASR_MMCS ((u32)0x08000000) /* MMC status */
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#define ETH_DMASR_EBS ((u32)0x03800000) /* Error bits status */
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/* combination with EBS[2:0] for GetFlagStatus function */
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#define ETH_DMASR_EBS_DescAccess ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
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#define ETH_DMASR_EBS_ReadTransf ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
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#define ETH_DMASR_EBS_DataTransfTx ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
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#define ETH_DMASR_TPS ((u32)0x00700000) /* Transmit process state */
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#define ETH_DMASR_TPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
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#define ETH_DMASR_TPS_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */
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#define ETH_DMASR_TPS_Waiting ((u32)0x00200000) /* Running - waiting for status */
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#define ETH_DMASR_TPS_Reading ((u32)0x00300000) /* Running - reading the data from host memory */
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#define ETH_DMASR_TPS_Suspended ((u32)0x00600000) /* Suspended - Tx Descriptor unavailabe */
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#define ETH_DMASR_TPS_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */
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#define ETH_DMASR_RPS ((u32)0x000E0000) /* Receive process state */
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#define ETH_DMASR_RPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
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#define ETH_DMASR_RPS_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */
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#define ETH_DMASR_RPS_Waiting ((u32)0x00060000) /* Running - waiting for packet */
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#define ETH_DMASR_RPS_Suspended ((u32)0x00080000) /* Suspended - Rx Descriptor unavailable */
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#define ETH_DMASR_RPS_Closing ((u32)0x000A0000) /* Running - closing descriptor */
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#define ETH_DMASR_RPS_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */
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#define ETH_DMASR_NIS ((u32)0x00010000) /* Normal interrupt summary */
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#define ETH_DMASR_AIS ((u32)0x00008000) /* Abnormal interrupt summary */
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#define ETH_DMASR_ERS ((u32)0x00004000) /* Early receive status */
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#define ETH_DMASR_FBES ((u32)0x00002000) /* Fatal bus error status */
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#define ETH_DMASR_ETS ((u32)0x00000400) /* Early transmit status */
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#define ETH_DMASR_RWTS ((u32)0x00000200) /* Receive watchdog timeout status */
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#define ETH_DMASR_RPSS ((u32)0x00000100) /* Receive process stopped status */
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#define ETH_DMASR_RBUS ((u32)0x00000080) /* Receive buffer unavailable status */
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#define ETH_DMASR_RS ((u32)0x00000040) /* Receive status */
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#define ETH_DMASR_TUS ((u32)0x00000020) /* Transmit underflow status */
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#define ETH_DMASR_ROS ((u32)0x00000010) /* Receive overflow status */
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#define ETH_DMASR_TJTS ((u32)0x00000008) /* Transmit jabber timeout status */
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#define ETH_DMASR_TBUS ((u32)0x00000004) /* Transmit buffer unavailable status */
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#define ETH_DMASR_TPSS ((u32)0x00000002) /* Transmit process stopped status */
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#define ETH_DMASR_TS ((u32)0x00000001) /* Transmit status */
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/* Bit definition for Ethernet DMA Operation Mode Register */
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#define ETH_DMAOMR_DTCEFD ((u32)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
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#define ETH_DMAOMR_RSF ((u32)0x02000000) /* Receive store and forward */
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#define ETH_DMAOMR_DFRF ((u32)0x01000000) /* Disable flushing of received frames */
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#define ETH_DMAOMR_TSF ((u32)0x00200000) /* Transmit store and forward */
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#define ETH_DMAOMR_FTF ((u32)0x00100000) /* Flush transmit FIFO */
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#define ETH_DMAOMR_TTC ((u32)0x0001C000) /* Transmit threshold control */
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#define ETH_DMAOMR_TTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
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#define ETH_DMAOMR_TTC_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
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#define ETH_DMAOMR_TTC_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
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#define ETH_DMAOMR_TTC_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
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#define ETH_DMAOMR_TTC_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
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#define ETH_DMAOMR_TTC_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
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#define ETH_DMAOMR_TTC_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
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#define ETH_DMAOMR_TTC_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
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#define ETH_DMAOMR_ST ((u32)0x00002000) /* Start/stop transmission command */
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#define ETH_DMAOMR_FEF ((u32)0x00000080) /* Forward error frames */
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#define ETH_DMAOMR_FUGF ((u32)0x00000040) /* Forward undersized good frames */
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#define ETH_DMAOMR_RTC ((u32)0x00000018) /* receive threshold control */
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#define ETH_DMAOMR_RTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
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#define ETH_DMAOMR_RTC_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
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#define ETH_DMAOMR_RTC_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
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#define ETH_DMAOMR_RTC_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
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#define ETH_DMAOMR_OSF ((u32)0x00000004) /* operate on second frame */
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#define ETH_DMAOMR_SR ((u32)0x00000002) /* Start/stop receive */
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/* Bit definition for Ethernet DMA Interrupt Enable Register */
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#define ETH_DMAIER_NISE ((u32)0x00010000) /* Normal interrupt summary enable */
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#define ETH_DMAIER_AISE ((u32)0x00008000) /* Abnormal interrupt summary enable */
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#define ETH_DMAIER_ERIE ((u32)0x00004000) /* Early receive interrupt enable */
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#define ETH_DMAIER_FBEIE ((u32)0x00002000) /* Fatal bus error interrupt enable */
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#define ETH_DMAIER_ETIE ((u32)0x00000400) /* Early transmit interrupt enable */
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#define ETH_DMAIER_RWTIE ((u32)0x00000200) /* Receive watchdog timeout interrupt enable */
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#define ETH_DMAIER_RPSIE ((u32)0x00000100) /* Receive process stopped interrupt enable */
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#define ETH_DMAIER_RBUIE ((u32)0x00000080) /* Receive buffer unavailable interrupt enable */
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#define ETH_DMAIER_RIE ((u32)0x00000040) /* Receive interrupt enable */
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#define ETH_DMAIER_TUIE ((u32)0x00000020) /* Transmit Underflow interrupt enable */
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#define ETH_DMAIER_ROIE ((u32)0x00000010) /* Receive Overflow interrupt enable */
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#define ETH_DMAIER_TJTIE ((u32)0x00000008) /* Transmit jabber timeout interrupt enable */
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#define ETH_DMAIER_TBUIE ((u32)0x00000004) /* Transmit buffer unavailable interrupt enable */
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#define ETH_DMAIER_TPSIE ((u32)0x00000002) /* Transmit process stopped interrupt enable */
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#define ETH_DMAIER_TIE ((u32)0x00000001) /* Transmit interrupt enable */
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/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
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#define ETH_DMAMFBOCR_OFOC ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */
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#define ETH_DMAMFBOCR_MFA ((u32)0x0FFE0000) /* Number of frames missed by the application */
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#define ETH_DMAMFBOCR_OMFC ((u32)0x00010000) /* Overflow bit for missed frame counter */
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#define ETH_DMAMFBOCR_MFC ((u32)0x0000FFFF) /* Number of frames missed by the controller */
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/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
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#define ETH_DMACHTDR_HTDAP ((u32)0xFFFFFFFF) /* Host transmit descriptor address pointer */
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/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
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#define ETH_DMACHRDR_HRDAP ((u32)0xFFFFFFFF) /* Host receive descriptor address pointer */
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/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
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#define ETH_DMACHTBAR_HTBAP ((u32)0xFFFFFFFF) /* Host transmit buffer address pointer */
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/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
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#define ETH_DMACHRBAR_HRBAP ((u32)0xFFFFFFFF) /* Host receive buffer address pointer */
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/******************************************************************************/
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/* Macros */
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/******************************************************************************/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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/******************************************************************************/
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/* Peripheral memory map */
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/******************************************************************************/
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/* ETHERNET registers base address */
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#define ETH_BASE ((u32)0x40028000)
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#define ETH_MAC_BASE (ETH_BASE)
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#define ETH_MMC_BASE (ETH_BASE + 0x0100)
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#define ETH_PTP_BASE (ETH_BASE + 0x0700)
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#define ETH_DMA_BASE (ETH_BASE + 0x1000)
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/******************************************************************************/
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/* Peripheral declaration */
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/******************************************************************************/
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/*------------------------ Non Debug Mode ------------------------------------*/
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#ifndef ETH_DEBUG
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#ifdef _ETH_MAC
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#define ETH_MAC ((ETH_MAC_TypeDef *) ETH_MAC_BASE)
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#endif /*_ETH_MAC */
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#ifdef _ETH_MMC
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#define ETH_MMC ((ETH_MMC_TypeDef *) ETH_MMC_BASE)
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#endif /*_ETH_MMC */
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#ifdef _ETH_PTP
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#define ETH_PTP ((ETH_PTP_TypeDef *) ETH_PTP_BASE)
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#endif /*_ETH_PTP */
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#ifdef _ETH_DMA
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#define ETH_DMA ((ETH_DMA_TypeDef *) ETH_DMA_BASE)
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#endif /*_ETH_DMA */
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/*------------------------ Debug Mode ----------------------------------------*/
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#else /* ETH_DEBUG */
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#ifdef _ETH_MAC
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EXT ETH_MAC_TypeDef *ETH_MAC;
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#endif /*_ETH_MAC */
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#ifdef _ETH_MMC
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EXT ETH_MMC_TypeDef *ETH_MMC;
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#endif /*_ETH_MMC */
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#ifdef _ETH_PTP
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EXT ETH_PTP_TypeDef *ETH_PTP;
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#endif /*_ETH_PTP */
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#ifdef _ETH_DMA
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EXT ETH_DMA_TypeDef *ETH_DMA;
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#endif /*_ETH_DMA */
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#endif /* ETH_DEBUG */
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/* Exported constants --------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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#endif /* __STM32FXXX_ETH_MAP_H */
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/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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