225 lines
12 KiB
C
225 lines
12 KiB
C
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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* File Name : stm32f10x_dma.h
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* Author : MCD Application Team
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* Date First Issued : 09/29/2006
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* Description : This file contains all the functions prototypes for the
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* DMA firmware library.
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********************************************************************************
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* History:
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* 04/02/2007: V0.2
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* 02/05/2007: V0.1
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* 09/29/2006: V0.01
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F10x_DMA_H
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#define __STM32F10x_DMA_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_map.h"
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/* Exported types ------------------------------------------------------------*/
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/* DMA Init structure definition */
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typedef struct
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{
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u32 DMA_PeripheralBaseAddr;
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u32 DMA_MemoryBaseAddr;
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u32 DMA_DIR;
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u32 DMA_BufferSize;
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u32 DMA_PeripheralInc;
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u32 DMA_MemoryInc;
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u32 DMA_PeripheralDataSize;
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u32 DMA_MemoryDataSize;
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u32 DMA_Mode;
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u32 DMA_Priority;
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u32 DMA_M2M;
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}DMA_InitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/* DMA data transfer direction -----------------------------------------------*/
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#define DMA_DIR_PeripheralDST ((u32)0x00000010)
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#define DMA_DIR_PeripheralSRC ((u32)0x00000000)
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#define IS_DMA_DIR(DIR) ((DIR == DMA_DIR_PeripheralDST) || \
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(DIR == DMA_DIR_PeripheralSRC))
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/* DMA peripheral incremented mode -------------------------------------------*/
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#define DMA_PeripheralInc_Enable ((u32)0x00000040)
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#define DMA_PeripheralInc_Disable ((u32)0x00000000)
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#define IS_DMA_PERIPHERAL_INC_STATE(STATE) ((STATE == DMA_PeripheralInc_Enable) || \
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(STATE == DMA_PeripheralInc_Disable))
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/* DMA memory incremented mode -----------------------------------------------*/
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#define DMA_MemoryInc_Enable ((u32)0x00000080)
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#define DMA_MemoryInc_Disable ((u32)0x00000000)
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#define IS_DMA_MEMORY_INC_STATE(STATE) ((STATE == DMA_MemoryInc_Enable) || \
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(STATE == DMA_MemoryInc_Disable))
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/* DMA peripheral data size --------------------------------------------------*/
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#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
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#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
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#define DMA_PeripheralDataSize_Word ((u32)0x00000200)
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#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) ((SIZE == DMA_PeripheralDataSize_Byte) || \
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(SIZE == DMA_PeripheralDataSize_HalfWord) || \
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(SIZE == DMA_PeripheralDataSize_Word))
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/* DMA memory data size ------------------------------------------------------*/
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#define DMA_MemoryDataSize_Byte ((u32)0x00000000)
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#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
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#define DMA_MemoryDataSize_Word ((u32)0x00000800)
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#define IS_DMA_MEMORY_DATA_SIZE(SIZE) ((SIZE == DMA_MemoryDataSize_Byte) || \
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(SIZE == DMA_MemoryDataSize_HalfWord) || \
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(SIZE == DMA_MemoryDataSize_Word))
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/* DMA circular/normal mode --------------------------------------------------*/
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#define DMA_Mode_Circular ((u32)0x00000020)
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#define DMA_Mode_Normal ((u32)0x00000000)
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#define IS_DMA_MODE(MODE) ((MODE == DMA_Mode_Circular) || (MODE == DMA_Mode_Normal))
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/* DMA priority level --------------------------------------------------------*/
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#define DMA_Priority_VeryHigh ((u32)0x00003000)
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#define DMA_Priority_High ((u32)0x00002000)
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#define DMA_Priority_Medium ((u32)0x00001000)
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#define DMA_Priority_Low ((u32)0x00000000)
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#define IS_DMA_PRIORITY(PRIORITY) ((PRIORITY == DMA_Priority_VeryHigh) || \
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(PRIORITY == DMA_Priority_High) || \
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(PRIORITY == DMA_Priority_Medium) || \
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(PRIORITY == DMA_Priority_Low))
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/* DMA memory to memory ------------------------------------------------------*/
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#define DMA_M2M_Enable ((u32)0x00004000)
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#define DMA_M2M_Disable ((u32)0x00000000)
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#define IS_DMA_M2M_STATE(STATE) ((STATE == DMA_M2M_Enable) || (STATE == DMA_M2M_Disable))
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/* DMA interrupts definition -------------------------------------------------*/
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#define DMA_IT_TC ((u32)0x00000002)
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#define DMA_IT_HT ((u32)0x00000004)
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#define DMA_IT_TE ((u32)0x00000008)
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#define IS_DMA_CONFIG_IT(IT) (((IT & 0xFFFFFFF1) == 0x00) && (IT != 0x00))
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#define DMA_IT_GL1 ((u32)0x00000001)
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#define DMA_IT_TC1 ((u32)0x00000002)
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#define DMA_IT_HT1 ((u32)0x00000004)
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#define DMA_IT_TE1 ((u32)0x00000008)
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#define DMA_IT_GL2 ((u32)0x00000010)
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#define DMA_IT_TC2 ((u32)0x00000020)
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#define DMA_IT_HT2 ((u32)0x00000040)
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#define DMA_IT_TE2 ((u32)0x00000080)
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#define DMA_IT_GL3 ((u32)0x00000100)
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#define DMA_IT_TC3 ((u32)0x00000200)
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#define DMA_IT_HT3 ((u32)0x00000400)
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#define DMA_IT_TE3 ((u32)0x00000800)
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#define DMA_IT_GL4 ((u32)0x00001000)
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#define DMA_IT_TC4 ((u32)0x00002000)
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#define DMA_IT_HT4 ((u32)0x00004000)
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#define DMA_IT_TE4 ((u32)0x00008000)
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#define DMA_IT_GL5 ((u32)0x00010000)
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#define DMA_IT_TC5 ((u32)0x00020000)
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#define DMA_IT_HT5 ((u32)0x00040000)
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#define DMA_IT_TE5 ((u32)0x00080000)
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#define DMA_IT_GL6 ((u32)0x00100000)
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#define DMA_IT_TC6 ((u32)0x00200000)
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#define DMA_IT_HT6 ((u32)0x00400000)
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#define DMA_IT_TE6 ((u32)0x00800000)
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#define DMA_IT_GL7 ((u32)0x01000000)
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#define DMA_IT_TC7 ((u32)0x02000000)
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#define DMA_IT_HT7 ((u32)0x04000000)
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#define DMA_IT_TE7 ((u32)0x08000000)
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#define IS_DMA_CLEAR_IT(IT) (((IT & 0xF0000000) == 0x00) && (IT != 0x00))
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#define IS_DMA_GET_IT(IT) ((IT == DMA_IT_GL1) || (IT == DMA_IT_TC1) || \
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(IT == DMA_IT_HT1) || (IT == DMA_IT_TE1) || \
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(IT == DMA_IT_GL2) || (IT == DMA_IT_TC2) || \
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(IT == DMA_IT_HT2) || (IT == DMA_IT_TE2) || \
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(IT == DMA_IT_GL3) || (IT == DMA_IT_TC3) || \
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(IT == DMA_IT_HT3) || (IT == DMA_IT_TE3) || \
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(IT == DMA_IT_GL4) || (IT == DMA_IT_TC4) || \
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(IT == DMA_IT_HT4) || (IT == DMA_IT_TE4) || \
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(IT == DMA_IT_GL5) || (IT == DMA_IT_TC5) || \
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(IT == DMA_IT_HT5) || (IT == DMA_IT_TE5) || \
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(IT == DMA_IT_GL6) || (IT == DMA_IT_TC6) || \
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(IT == DMA_IT_HT6) || (IT == DMA_IT_TE6) || \
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(IT == DMA_IT_GL7) || (IT == DMA_IT_TC7) || \
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(IT == DMA_IT_HT7) || (IT == DMA_IT_TE7))
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/* DMA flags definition ------------------------------------------------------*/
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#define DMA_FLAG_GL1 ((u32)0x00000001)
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#define DMA_FLAG_TC1 ((u32)0x00000002)
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#define DMA_FLAG_HT1 ((u32)0x00000004)
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#define DMA_FLAG_TE1 ((u32)0x00000008)
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#define DMA_FLAG_GL2 ((u32)0x00000010)
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#define DMA_FLAG_TC2 ((u32)0x00000020)
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#define DMA_FLAG_HT2 ((u32)0x00000040)
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#define DMA_FLAG_TE2 ((u32)0x00000080)
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#define DMA_FLAG_GL3 ((u32)0x00000100)
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#define DMA_FLAG_TC3 ((u32)0x00000200)
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#define DMA_FLAG_HT3 ((u32)0x00000400)
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#define DMA_FLAG_TE3 ((u32)0x00000800)
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#define DMA_FLAG_GL4 ((u32)0x00001000)
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#define DMA_FLAG_TC4 ((u32)0x00002000)
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#define DMA_FLAG_HT4 ((u32)0x00004000)
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#define DMA_FLAG_TE4 ((u32)0x00008000)
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#define DMA_FLAG_GL5 ((u32)0x00010000)
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#define DMA_FLAG_TC5 ((u32)0x00020000)
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#define DMA_FLAG_HT5 ((u32)0x00040000)
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#define DMA_FLAG_TE5 ((u32)0x00080000)
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#define DMA_FLAG_GL6 ((u32)0x00100000)
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#define DMA_FLAG_TC6 ((u32)0x00200000)
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#define DMA_FLAG_HT6 ((u32)0x00400000)
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#define DMA_FLAG_TE6 ((u32)0x00800000)
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#define DMA_FLAG_GL7 ((u32)0x01000000)
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#define DMA_FLAG_TC7 ((u32)0x02000000)
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#define DMA_FLAG_HT7 ((u32)0x04000000)
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#define DMA_FLAG_TE7 ((u32)0x08000000)
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#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG & 0xF0000000) == 0x00) && (FLAG != 0x00))
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#define IS_DMA_GET_FLAG(FLAG) ((FLAG == DMA_FLAG_GL1) || (FLAG == DMA_FLAG_TC1) || \
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(FLAG == DMA_FLAG_HT1) || (FLAG == DMA_FLAG_TE1) || \
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(FLAG == DMA_FLAG_GL2) || (FLAG == DMA_FLAG_TC2) || \
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(FLAG == DMA_FLAG_HT2) || (FLAG == DMA_FLAG_TE2) || \
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(FLAG == DMA_FLAG_GL3) || (FLAG == DMA_FLAG_TC3) || \
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(FLAG == DMA_FLAG_HT3) || (FLAG == DMA_FLAG_TE3) || \
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(FLAG == DMA_FLAG_GL4) || (FLAG == DMA_FLAG_TC4) || \
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(FLAG == DMA_FLAG_HT4) || (FLAG == DMA_FLAG_TE4) || \
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(FLAG == DMA_FLAG_GL5) || (FLAG == DMA_FLAG_TC5) || \
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(FLAG == DMA_FLAG_HT5) || (FLAG == DMA_FLAG_TE5) || \
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(FLAG == DMA_FLAG_GL6) || (FLAG == DMA_FLAG_TC6) || \
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(FLAG == DMA_FLAG_HT6) || (FLAG == DMA_FLAG_TE6) || \
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(FLAG == DMA_FLAG_GL7) || (FLAG == DMA_FLAG_TC7) || \
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(FLAG == DMA_FLAG_HT7) || (FLAG == DMA_FLAG_TE7))
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/* DMA Buffer Size -----------------------------------------------------------*/
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#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE >= 0x1) && (SIZE < 0x10000))
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx);
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void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct);
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void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
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void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState);
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void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState);
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u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx);
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FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
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void DMA_ClearFlag(u32 DMA_FLAG);
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ITStatus DMA_GetITStatus(u32 DMA_IT);
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void DMA_ClearITPendingBit(u32 DMA_IT);
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#endif /*__STM32F10x_DMA_H */
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/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
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