109 lines
3.4 KiB
Diff
109 lines
3.4 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Vyacheslav Bocharov <adeep@lexina.in>
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Date: Mon, 7 Nov 2022 14:19:08 +0100
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Subject: arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase
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clock settings from devicetree data
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The mmc driver has the same phase values for all meson platforms. However,
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some platforms (and even some boards) require different values. This patch
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transfers the values from the set in the code to the variables in the
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device-tree file.
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Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
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---
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drivers/mmc/host/meson-gx-mmc.c | 19 +++--
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include/dt-bindings/mmc/meson-gx-mmc.h | 35 ++++++++++
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2 files changed, 48 insertions(+), 6 deletions(-)
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diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
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index 64a1520321b0..fa9ec777e4a2 100644
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--- a/drivers/mmc/host/meson-gx-mmc.c
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+++ b/drivers/mmc/host/meson-gx-mmc.c
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@@ -27,6 +27,7 @@
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#include <linux/interrupt.h>
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#include <linux/bitfield.h>
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#include <linux/pinctrl/consumer.h>
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+#include <dt-bindings/mmc/meson-gx-mmc.h>
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#define DRIVER_NAME "meson-gx-mmc"
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@@ -36,8 +37,6 @@
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#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
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#define CLK_TX_PHASE_MASK GENMASK(11, 10)
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#define CLK_RX_PHASE_MASK GENMASK(13, 12)
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-#define CLK_PHASE_0 0
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-#define CLK_PHASE_180 2
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#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
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#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
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#define CLK_V2_ALWAYS_ON BIT(24)
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@@ -428,13 +427,21 @@ static int meson_mmc_clk_init(struct meson_host *host)
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const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
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const char *clk_parent[1];
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u32 clk_reg;
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-
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+ u32 phase[3]; // <core_phase, tx_phase, rx_phase>
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+
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+ if (!(host->dev && host->dev->of_node) || (device_property_read_u32_array(host->dev,
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+ "amlogic,mmc-phase", phase, 3) < 0)) {
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+ dev_dbg(host->dev, "get amlogic,mmc-phase failed, use default phase settings\n");
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+ phase[0] = CLK_PHASE_180;
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+ phase[1] = CLK_PHASE_0;
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+ phase[2] = CLK_PHASE_0;
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+ }
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/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
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clk_reg = CLK_ALWAYS_ON(host);
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clk_reg |= CLK_DIV_MASK;
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- clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
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- clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
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- clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
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+ clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, phase[0]);
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+ clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, phase[1]);
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+ clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, phase[2]);
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if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
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clk_reg |= CLK_IRQ_SDIO_SLEEP(host);
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writel(clk_reg, host->regs + SD_EMMC_CLOCK);
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diff --git a/include/dt-bindings/mmc/meson-gx-mmc.h b/include/dt-bindings/mmc/meson-gx-mmc.h
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new file mode 100644
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index 000000000000..cfc4a9d75b2b
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--- /dev/null
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+++ b/include/dt-bindings/mmc/meson-gx-mmc.h
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@@ -0,0 +1,35 @@
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+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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+/*
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+ * Copyright (c) 2022 Vyacheslav Bocharov
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+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
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+ */
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+
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+#ifndef _DT_BINDINGS_MESON_GX_MMC_H
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+#define _DT_BINDINGS_MESON_GX_MMC_H
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+
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+/*
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+ * Cfg_rx_phase: RX clock phase
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+ * bits: 9:8 R/W
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+ * default: 0
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+ * Recommended value: 0
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+ *
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+ * Cfg_tx_phase: TX clock phase
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+ * bits: 9:8 R/W
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+ * default: 0
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+ * Recommended value: 2
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+ *
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+ * Cfg_co_phase: Core clock phase
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+ * bits: 9:8 R/W
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+ * default: 0
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+ * Recommended value: 2
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+ *
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+ * values: 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
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+ */
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+
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+#define CLK_PHASE_0 0
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+#define CLK_PHASE_90 1
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+#define CLK_PHASE_180 2
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+#define CLK_PHASE_270 3
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+
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+
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+#endif
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--
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Armbian
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