220 lines
9.4 KiB
Diff
220 lines
9.4 KiB
Diff
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Subject: [PATCH v3] PCI: Disallow retraining link for Atheros chips on non-Gen1 PCIe bridges
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Atheros AR9xxx and QCA9xxx chips have behaviour issues not only after a
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bus reset, but also after doing retrain link, if PCIe bridge is not in
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GEN1 mode (at 2.5 GT/s speed):
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- QCA9880 and QCA9890 chips throw a Link Down event and completely
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disappear from the bus and their config space is not accessible
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afterwards.
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- QCA9377 chip throws a Link Down event followed by Link Up event, the
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config space is accessible and PCI device ID is correct. But trying to
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access chip's I/O space causes Uncorrected (Non-Fatal) AER error,
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followed by Synchronous external abort 96000210 and Segmentation fault
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of insmod while loading ath10k_pci.ko module.
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- AR9390 chip throws a Link Down event followed by Link Up event, config
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space is accessible, but contains nonsense values. PCI device ID is
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0xABCD which indicates HW bug that chip itself was not able to read
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values from internal EEPROM/OTP.
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- AR9287 chip throws also Link Down and Link Up events, also has
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accessible config space containing correct values. But ath9k driver
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fails to initialize card from this state as it is unable to access HW
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registers. This also indicates that the chip iself is not able to read
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values from internal EEPROM/OTP.
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These issues related to PCI device ID 0xABCD and to reading internal
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EEPROM/OTP were previously discussed at ath9k-devel mailing list in
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following thread:
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https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html
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After experiments we've come up with a solution: it seems that Retrain
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link can be called only when using GEN1 PCIe bridge or when PCIe bridge
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link speed is forced to 2.5 GT/s. Applying this workaround fixes all
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mentioned cards.
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This issue was reproduced with more cards:
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- Compex WLE900VX (QCA9880 based / device ID 0x003c)
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- QCNFA435 (QCA9377 based / device ID 0x0042)
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- Compex WLE200NX (AR9287 based / device ID 0x002e)
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- "noname" card (QCA9890 based / device ID 0x003c)
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- Wistron NKR-DNXAH1 (AR9390 based / device ID 0x0030)
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on Armada 385 with pci-mvebu.c driver and also on Armada 3720 with
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pci-aardvark.c driver.
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To workaround this issue, this change introduces a new PCI quirk called
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PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1, which is enabled for all
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Atheros chips with PCI_DEV_FLAGS_NO_BUS_RESET quirk, and also for Atheros
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chip AR9287.
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When this quirk is set, kernel disallows triggering PCI_EXP_LNKCTL_RL
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bit in config space of PCIe Bridge in the case when PCIe Bridge is
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capable of higher speed than 2.5 GT/s and this higher speed is already
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allowed. When PCIe Bridge has accessible LNKCTL2 register, we try to
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force target link speed to 2.5 GT/s. After this change it is possible
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to trigger PCI_EXP_LNKCTL_RL bit without issues.
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Currently only PCIe ASPM kernel code triggers this PCI_EXP_LNKCTL_RL bit,
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so quirk check is added only into pcie/aspm.c file.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Reported-by: Toke Høiland-Jørgensen <toke@redhat.com>
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Tested-by: Toke Høiland-Jørgensen <toke@redhat.com>
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Tested-by: Marek Behún <kabel@kernel.org>
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BugLink: https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
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BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=84821
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BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=192441
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BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=209833
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Cc: stable@vger.kernel.org # c80851f6ce63a ("PCI: Add PCI_EXP_LNKCTL2_TLS* macros")
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---
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Changes since v1:
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* Move whole quirk code into pcie_downgrade_link_to_gen1() function
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* Reformat to 80 chars per line where possible
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* Add quirk also for cards with AR9287 chip (PCI ID 0x002e)
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* Extend commit message description and add information about 0xABCD
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Changes since v2:
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* Add quirk also for Atheros QCA9377 chip
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---
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drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++
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drivers/pci/quirks.c | 39 ++++++++++++++++++++++++++++--------
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include/linux/pci.h | 2 ++
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3 files changed, 77 insertions(+), 8 deletions(-)
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diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
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index ac0557a305af..729b0389562b 100644
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--- a/drivers/pci/pcie/aspm.c
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+++ b/drivers/pci/pcie/aspm.c
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@@ -192,12 +192,56 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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link->clkpm_disable = blacklist ? 1 : 0;
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}
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+static int pcie_downgrade_link_to_gen1(struct pci_dev *parent)
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+{
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+ u16 reg16;
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+ u32 reg32;
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+ int ret;
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+
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+ /* Check if link is capable of higher speed than 2.5 GT/s */
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+ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, ®32);
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+ if ((reg32 & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
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+ return 0;
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+
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+ /* Check if link speed can be downgraded to 2.5 GT/s */
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+ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP2, ®32);
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+ if (!(reg32 & PCI_EXP_LNKCAP2_SLS_2_5GB)) {
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+ pci_err(parent, "ASPM: Bridge does not support changing Link Speed to 2.5 GT/s\n");
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+ return -EOPNOTSUPP;
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+ }
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+
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+ /* Force link speed to 2.5 GT/s */
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+ ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2,
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+ PCI_EXP_LNKCTL2_TLS,
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+ PCI_EXP_LNKCTL2_TLS_2_5GT);
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+ if (!ret) {
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+ /* Verify that new value was really set */
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+ pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, ®16);
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+ if ((reg16 & PCI_EXP_LNKCTL2_TLS) != PCI_EXP_LNKCTL2_TLS_2_5GT)
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+ ret = -EINVAL;
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+ }
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+
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+ if (ret) {
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+ pci_err(parent, "ASPM: Changing Target Link Speed to 2.5 GT/s failed: %d\n", ret);
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+ return ret;
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+ }
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+
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+ pci_info(parent, "ASPM: Target Link Speed changed to 2.5 GT/s due to quirk\n");
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+ return 0;
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+}
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+
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static bool pcie_retrain_link(struct pcie_link_state *link)
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{
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struct pci_dev *parent = link->pdev;
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unsigned long end_jiffies;
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u16 reg16;
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+ if ((link->downstream->dev_flags & PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1) &&
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+ pcie_downgrade_link_to_gen1(parent)) {
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+ pci_err(parent, "ASPM: Retrain Link at higher speed is disallowed by quirk\n");
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+ return false;
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+ }
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+
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pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
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reg16 |= PCI_EXP_LNKCTL_RL;
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
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index 5d2acebc3..91d675e0d 100644
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--- a/drivers/pci/quirks.c
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+++ b/drivers/pci/quirks.c
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@@ -3572,19 +3572,46 @@ static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
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quirk_nvidia_no_bus_reset);
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+
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+static void quirk_no_bus_reset_and_no_retrain_link(struct pci_dev *dev)
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+{
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+ dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET |
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+ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1;
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+}
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+
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/*
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* Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
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+ * Atheros AR9xxx and QCA9xxx chips do not behave after a bus reset and also
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+ * after retrain link when PCIe bridge is not in GEN1 mode at 2.5 GT/s speed.
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* The device will throw a Link Down error on AER-capable systems and
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* regardless of AER, config space of the device is never accessible again
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* and typically causes the system to hang or reset when access is attempted.
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+ * Or if config space is accessible again then it contains only dummy values
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+ * like fixed PCI device ID 0xABCD or values not initialized at all.
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+ * Retrain link can be called only when using GEN1 PCIe bridge or when
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+ * PCIe bridge has forced link speed to 2.5 GT/s via PCI_EXP_LNKCTL2 register.
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+ * To reset these cards it is required to do PCIe Warm Reset via PERST# pin.
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* https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
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+ * https://lore.kernel.org/r/87h7l8axqp.fsf@toke.dk/
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+ * https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html
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*/
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-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
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-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
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-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
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-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
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-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
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-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x002e,
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+ quirk_no_bus_reset_and_no_retrain_link);
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030,
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+ quirk_no_bus_reset_and_no_retrain_link);
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032,
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+ quirk_no_bus_reset_and_no_retrain_link);
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033,
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+ quirk_no_bus_reset_and_no_retrain_link);
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034,
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+ quirk_no_bus_reset_and_no_retrain_link);
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e,
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+ quirk_no_bus_reset_and_no_retrain_link);
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c,
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+ quirk_no_bus_reset_and_no_retrain_link);
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0042,
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+ quirk_no_bus_reset_and_no_retrain_link);
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+
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/*
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* Root port on some Cavium CN8xxx chips do not successfully complete a bus
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diff --git a/include/linux/pci.h b/include/linux/pci.h
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index 86c799c97b77..fdbf7254e4ab 100644
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--- a/include/linux/pci.h
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+++ b/include/linux/pci.h
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@@ -227,6 +227,8 @@ enum pci_dev_flags {
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PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
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/* Device does honor MSI masking despite saying otherwise */
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PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
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+ /* Don't Retrain Link for device when bridge is not in GEN1 mode */
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+ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1 = (__force pci_dev_flags_t) (1 << 12),
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};
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enum pci_irq_reroute_variant {
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--
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2.20.1
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