56 lines
2.3 KiB
Diff
56 lines
2.3 KiB
Diff
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From f1149effc7fd438ac5925a8e58ee2da294033ec5 Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@armlinux.org.uk>
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Date: Tue, 2 Feb 2021 13:45:28 +0000
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Subject: PCI: pci-bridge-emul: re-arrange register tests
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Re-arrange the tests for which sets of registers are being accessed
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so that it is easier to add further regions later. No functional
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change.
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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---
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drivers/pci/pci-bridge-emul.c | 15 ++++++++++-----
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1 file changed, 10 insertions(+), 5 deletions(-)
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diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
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index 9334b2dd4764..d746116104c6 100644
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--- a/drivers/pci/pci-bridge-emul.c
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+++ b/drivers/pci/pci-bridge-emul.c
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@@ -477,8 +477,11 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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read_op = pci_bridge_emul_read_ssid;
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cfgspace = NULL;
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behavior = NULL;
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- } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF &&
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- bridge->has_pcie) {
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+ } else if (!bridge->has_pcie) {
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+ /* PCIe space is not implemented, and no PCI capabilities */
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+ *value = 0;
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+ return PCIBIOS_SUCCESSFUL;
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+ } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF) {
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/* Our emulated PCIe capability */
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reg -= bridge->pcie_start;
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read_op = bridge->ops->read_pcie;
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@@ -551,14 +554,16 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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write_op = bridge->ops->write_base;
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cfgspace = (__le32 *) &bridge->conf;
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behavior = bridge->pci_regs_behavior;
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- } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF &&
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- bridge->has_pcie) {
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+ } else if (!bridge->has_pcie) {
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+ /* PCIe space is not implemented, and no PCI capabilities */
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+ return PCIBIOS_SUCCESSFUL;
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+ } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF) {
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/* Our emulated PCIe capability */
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reg -= bridge->pcie_start;
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write_op = bridge->ops->write_pcie;
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cfgspace = (__le32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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- } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
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+ } else if (reg >= PCI_CFG_SPACE_SIZE) {
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/* PCIe extended capability space */
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reg -= PCI_CFG_SPACE_SIZE;
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write_op = bridge->ops->write_ext;
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--
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cgit
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