51 lines
1.7 KiB
Diff
51 lines
1.7 KiB
Diff
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From f83d188f49bd11d085c3f4160b208cb8194daff4 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Wed, 8 Jan 2020 21:07:52 +0000
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Subject: [PATCH] drm/rockchip: dw-hdmi: limit tmds to 340mhz
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RK3228/RK3328 does not provide a stable hdmi signal at TMDS rates
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above 371.25MHz (340MHz pixel clock).
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Limit the pixel clock rate to 340MHz to provide a stable signal.
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Also limit the pixel clock to the display reported max tmds clock.
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This also enables use of pixel clocks up to 340MHz on RK3288/RK3399.
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And limit resolution to 3840x2160
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++------------
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1 file changed, 4 insertions(+), 12 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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index b5d2cdaa24fa..5f7ab8e6bb72 100644
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -221,19 +221,11 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *info,
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const struct drm_display_mode *mode)
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{
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- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
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- int pclk = mode->clock * 1000;
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- bool valid = false;
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- int i;
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+ if (mode->clock > 340000 ||
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+ (info->max_tmds_clock && mode->clock > info->max_tmds_clock))
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+ return MODE_CLOCK_HIGH;
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- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
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- if (pclk == mpll_cfg[i].mpixelclock) {
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- valid = true;
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- break;
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- }
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- }
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-
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- return (valid) ? MODE_OK : MODE_BAD;
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+ return drm_mode_validate_size(mode, 3840, 2160);
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}
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static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
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--
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2.26.2
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