51 lines
2.2 KiB
Diff
51 lines
2.2 KiB
Diff
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From f12f665a30838e00faef29dcab92dcd799cb5275 Mon Sep 17 00:00:00 2001
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From: Nickey Yang <nickey.yang@rock-chips.com>
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Date: Mon, 17 Jul 2017 16:35:34 +0800
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Subject: [PATCH 12/14] MINIARM: set npll be used for hdmi only
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Change-Id: I8bebfb2cfb68e3dad172e5547d3886526ad5e912
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Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
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---
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arch/arm/boot/dts/rk3288.dtsi | 2 ++
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drivers/clk/rockchip/clk-rk3288.c | 4 ++--
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2 files changed, 4 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index 9beb66216..42e3075b5 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -1031,6 +1031,8 @@ vopb: vop@ff930000 {
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resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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iommus = <&vopb_mmu>;
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+ assigned-clocks = <&cru DCLK_VOP0>;
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+ assigned-clock-parents = <&cru PLL_NPLL>;
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status = "disabled";
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vopb_out: port {
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index cc2a177bb..799207a2b 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -226,7 +226,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
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[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
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RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
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[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
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- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
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+ RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
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};
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static struct clk_div_table div_hclk_cpu_t[] = {
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@@ -438,7 +438,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK3288_CLKGATE_CON(3), 4, GFLAGS),
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- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
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+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
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RK3288_CLKGATE_CON(3), 1, GFLAGS),
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COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
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--
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2.26.2
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