1543 lines
38 KiB
Diff
1543 lines
38 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sun, 31 Oct 2021 17:15:58 +0100
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Subject: riscv: dts: Add full JH7100, Starlight and VisionFive support
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Based on the device tree in https://github.com/starfive-tech/u-boot/
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with contributions from:
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yanhong.wang <yanhong.wang@starfivetech.com>
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Huan.Feng <huan.feng@starfivetech.com>
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ke.zhu <ke.zhu@starfivetech.com>
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yiming.li <yiming.li@starfivetech.com>
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jack.zhu <jack.zhu@starfivetech.com>
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Samin Guo <samin.guo@starfivetech.com>
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Chenjieqin <Jessica.Chen@starfivetech.com>
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bo.li <bo.li@starfivetech.com>
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Rearranged, cleanups, fixes, pins and resets added by Emil.
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Cleanups, fixes, clocks added by Geert.
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Cleanups and GPIO fixes from Drew.
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Thermal zone added by Stephen.
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PWM pins added by Jianlong.
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cpu-map added by Jonas.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org>
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Signed-off-by: Drew Fustini <drew@beagleboard.org>
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Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Signed-off-by: Jonas Hahnfeld <hahnjo@hahnjo.de>
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---
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arch/riscv/boot/dts/starfive/Makefile | 2 +-
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arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts | 24 +
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arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts | 154 +--
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arch/riscv/boot/dts/starfive/jh7100-common.dtsi | 587 ++++++++++
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arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts | 32 +
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arch/riscv/boot/dts/starfive/jh7100.dtsi | 568 +++++++++
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6 files changed, 1218 insertions(+), 149 deletions(-)
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diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
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index 0ea1bc15ab30..058ea584aae4 100644
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--- a/arch/riscv/boot/dts/starfive/Makefile
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+++ b/arch/riscv/boot/dts/starfive/Makefile
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@@ -1,2 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
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+dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight-a1.dtb jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
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diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
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new file mode 100644
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index 000000000000..d307e44590f3
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--- /dev/null
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+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
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@@ -0,0 +1,24 @@
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+// SPDX-License-Identifier: GPL-2.0 OR MIT
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+/*
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+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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+ */
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+
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+/dts-v1/;
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+#include "jh7100-common.dtsi"
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ model = "BeagleV Starlight Beta A1";
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+ compatible = "beagle,beaglev-starlight-jh7100-a1", "starfive,jh7100";
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+
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+ gpio-restart {
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+ compatible = "gpio-restart";
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+ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
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+ priority = <224>;
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+ };
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+};
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+
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+&gpio {
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+ /* don't reset gpio mux for serial console and reset gpio */
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+ starfive,keep-gpiomux = <13 14 63>;
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+};
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diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
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index f7a230110512..ec42effa7a0e 100644
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--- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
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+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
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@@ -1,164 +1,22 @@
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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- * Copyright (C) 2021 StarFive Technology Co., Ltd.
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* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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*/
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/dts-v1/;
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-#include "jh7100.dtsi"
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+#include "jh7100-common.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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-#include <dt-bindings/leds/common.h>
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-#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
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/ {
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model = "BeagleV Starlight Beta";
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compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
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-
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- aliases {
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- serial0 = &uart3;
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- };
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-
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- chosen {
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- stdout-path = "serial0:115200n8";
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- };
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-
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- cpus {
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- timebase-frequency = <6250000>;
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- };
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-
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- memory@80000000 {
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- device_type = "memory";
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- reg = <0x0 0x80000000 0x2 0x0>;
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- };
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-
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- leds {
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- compatible = "gpio-leds";
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-
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- led-ack {
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- gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
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- color = <LED_COLOR_ID_GREEN>;
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- function = LED_FUNCTION_HEARTBEAT;
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- linux,default-trigger = "heartbeat";
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- label = "ack";
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- };
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- };
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};
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-&gpio {
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- i2c0_pins: i2c0-0 {
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- i2c-pins {
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- pinmux = <GPIOMUX(62, GPO_LOW,
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- GPO_I2C0_PAD_SCK_OEN,
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- GPI_I2C0_PAD_SCK_IN)>,
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- <GPIOMUX(61, GPO_LOW,
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- GPO_I2C0_PAD_SDA_OEN,
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- GPI_I2C0_PAD_SDA_IN)>;
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- bias-disable; /* external pull-up */
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- input-enable;
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- input-schmitt-enable;
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- };
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- };
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-
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- i2c1_pins: i2c1-0 {
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- i2c-pins {
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- pinmux = <GPIOMUX(47, GPO_LOW,
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- GPO_I2C1_PAD_SCK_OEN,
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- GPI_I2C1_PAD_SCK_IN)>,
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- <GPIOMUX(48, GPO_LOW,
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- GPO_I2C1_PAD_SDA_OEN,
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- GPI_I2C1_PAD_SDA_IN)>;
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- bias-pull-up;
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- input-enable;
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- input-schmitt-enable;
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- };
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- };
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-
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- i2c2_pins: i2c2-0 {
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- i2c-pins {
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- pinmux = <GPIOMUX(60, GPO_LOW,
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- GPO_I2C2_PAD_SCK_OEN,
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- GPI_I2C2_PAD_SCK_IN)>,
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- <GPIOMUX(59, GPO_LOW,
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- GPO_I2C2_PAD_SDA_OEN,
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- GPI_I2C2_PAD_SDA_IN)>;
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- bias-disable; /* external pull-up */
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- input-enable;
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- input-schmitt-enable;
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- };
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- };
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-
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- uart3_pins: uart3-0 {
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- rx-pins {
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- pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
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- GPI_UART3_PAD_SIN)>;
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- bias-pull-up;
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- drive-strength = <14>;
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- input-enable;
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- input-schmitt-enable;
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- slew-rate = <0>;
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- };
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- tx-pins {
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- pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
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- GPO_ENABLE, GPI_NONE)>;
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- bias-disable;
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- drive-strength = <35>;
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- input-disable;
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- input-schmitt-disable;
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- slew-rate = <0>;
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- };
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- };
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+&gmac {
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+ snps,reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
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};
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-&i2c0 {
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- clock-frequency = <100000>;
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- i2c-sda-hold-time-ns = <300>;
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- i2c-sda-falling-time-ns = <500>;
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- i2c-scl-falling-time-ns = <500>;
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- pinctrl-names = "default";
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- pinctrl-0 = <&i2c0_pins>;
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- status = "okay";
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-
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- pmic@5e {
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- compatible = "ti,tps65086";
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- reg = <0x5e>;
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- gpio-controller;
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- #gpio-cells = <2>;
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-
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- regulators {
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- };
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- };
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-};
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-
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-&i2c1 {
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- clock-frequency = <400000>;
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- i2c-sda-hold-time-ns = <300>;
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- i2c-sda-falling-time-ns = <100>;
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- i2c-scl-falling-time-ns = <100>;
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- pinctrl-names = "default";
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- pinctrl-0 = <&i2c1_pins>;
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- status = "okay";
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-};
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-
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-&i2c2 {
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- clock-frequency = <100000>;
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- i2c-sda-hold-time-ns = <300>;
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- i2c-sda-falling-time-ns = <500>;
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- i2c-scl-falling-time-ns = <500>;
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- pinctrl-names = "default";
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- pinctrl-0 = <&i2c2_pins>;
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- status = "okay";
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-};
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-
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-&osc_sys {
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- clock-frequency = <25000000>;
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-};
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-
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-&osc_aud {
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- clock-frequency = <27000000>;
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-};
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-
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-&uart3 {
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- pinctrl-names = "default";
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- pinctrl-0 = <&uart3_pins>;
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- status = "okay";
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+&gpio {
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+ /* don't reset gpio mux for serial console on uart3 */
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+ starfive,keep-gpiomux = <13 14>;
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};
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diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
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|
new file mode 100644
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index 000000000000..1a36da546137
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--- /dev/null
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+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
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@@ -0,0 +1,587 @@
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+// SPDX-License-Identifier: GPL-2.0 OR MIT
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+/*
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+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
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+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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+ */
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+
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+/dts-v1/;
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+#include "jh7100.dtsi"
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/leds/common.h>
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+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
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+
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+/ {
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+ aliases {
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+ mmc0 = &sdio0;
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+ mmc1 = &sdio1;
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+ serial0 = &uart3;
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+ serial1 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ cpus {
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+ timebase-frequency = <6250000>;
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|
+ };
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+
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+ memory@80000000 {
|
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+ device_type = "memory";
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+ reg = <0x0 0x80000000 0x2 0x0>;
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ led-ack {
|
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+ gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
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+ color = <LED_COLOR_ID_GREEN>;
|
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+ function = LED_FUNCTION_HEARTBEAT;
|
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|
+ linux,default-trigger = "heartbeat";
|
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|
+ label = "ack";
|
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|
+ };
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|
+ };
|
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|
+
|
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+ reserved-memory {
|
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|
+ #address-cells = <2>;
|
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|
+ #size-cells = <2>;
|
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|
+ ranges;
|
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|
+
|
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|
+ linux,cma {
|
||
|
+ compatible = "shared-dma-pool";
|
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|
+ reusable;
|
||
|
+ size = <0x0 0x28000000>;
|
||
|
+ alignment = <0x0 0x1000>;
|
||
|
+ alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
|
||
|
+ linux,cma-default;
|
||
|
+ };
|
||
|
+
|
||
|
+ jpu_reserved: framebuffer@c9000000 {
|
||
|
+ reg = <0x0 0xc9000000 0x0 0x4000000>;
|
||
|
+ };
|
||
|
+
|
||
|
+ nvdla_reserved: framebuffer@d0000000 {
|
||
|
+ no-map;
|
||
|
+ reg = <0x0 0xd0000000 0x0 0x28000000>;
|
||
|
+ };
|
||
|
+
|
||
|
+ vin_reserved: framebuffer@f9000000 {
|
||
|
+ compatible = "shared-dma-pool";
|
||
|
+ no-map;
|
||
|
+ reg = <0x0 0xf9000000 0x0 0x1000000>;
|
||
|
+ };
|
||
|
+
|
||
|
+ sffb_reserved: framebuffer@fb000000 {
|
||
|
+ compatible = "shared-dma-pool";
|
||
|
+ no-map;
|
||
|
+ reg = <0x0 0xfb000000 0x0 0x2000000>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ wifi_pwrseq: wifi-pwrseq {
|
||
|
+ compatible = "mmc-pwrseq-simple";
|
||
|
+ reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
|
||
|
+ };
|
||
|
+};
|
||
|
+
|
||
|
+&display {
|
||
|
+ memory-region = <&sffb_reserved>;
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
+
|
||
|
+&crtc {
|
||
|
+ ddr-format = <4>; //<WIN_FMT_RGB565>;
|
||
|
+ status = "okay";
|
||
|
+
|
||
|
+ port: port@0 {
|
||
|
+ reg = <0>;
|
||
|
+
|
||
|
+ crtc_0_out: endpoint {
|
||
|
+ remote-endpoint = <&hdmi_input0>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+};
|
||
|
+
|
||
|
+&encoder {
|
||
|
+ encoder-type = <2>; // 2-TMDS, 3-LVDS, 6-DSI, 8-DPI
|
||
|
+ status = "okay";
|
||
|
+
|
||
|
+ ports {
|
||
|
+ port@0 {
|
||
|
+ hdmi_out: endpoint {
|
||
|
+ remote-endpoint = <&tda998x_0_input>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ port@1 {
|
||
|
+ hdmi_input0: endpoint {
|
||
|
+ remote-endpoint = <&crtc_0_out>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ };
|
||
|
+};
|
||
|
+
|
||
|
+&gmac {
|
||
|
+ starfive,gtxclk-dlychain = <4>;
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&gmac_pins>;
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
+
|
||
|
+&gpio {
|
||
|
+ gmac_pins: gmac-0 {
|
||
|
+ gtxclk-pins {
|
||
|
+ pins = <PAD_FUNC_SHARE(115)>;
|
||
|
+ bias-pull-up;
|
||
|
+ drive-strength = <35>;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ slew-rate = <0>;
|
||
|
+ };
|
||
|
+ miitxclk-pins {
|
||
|
+ pins = <PAD_FUNC_SHARE(116)>;
|
||
|
+ bias-pull-up;
|
||
|
+ drive-strength = <14>;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ slew-rate = <0>;
|
||
|
+ };
|
||
|
+ tx-pins {
|
||
|
+ pins = <PAD_FUNC_SHARE(117)>,
|
||
|
+ <PAD_FUNC_SHARE(119)>,
|
||
|
+ <PAD_FUNC_SHARE(120)>,
|
||
|
+ <PAD_FUNC_SHARE(121)>,
|
||
|
+ <PAD_FUNC_SHARE(122)>,
|
||
|
+ <PAD_FUNC_SHARE(123)>,
|
||
|
+ <PAD_FUNC_SHARE(124)>,
|
||
|
+ <PAD_FUNC_SHARE(125)>,
|
||
|
+ <PAD_FUNC_SHARE(126)>;
|
||
|
+ bias-pull-up;
|
||
|
+ drive-strength = <35>;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ slew-rate = <0>;
|
||
|
+ };
|
||
|
+ rxclk-pins {
|
||
|
+ pins = <PAD_FUNC_SHARE(127)>;
|
||
|
+ bias-pull-up;
|
||
|
+ drive-strength = <14>;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ slew-rate = <6>;
|
||
|
+ };
|
||
|
+ rxer-pins {
|
||
|
+ pins = <PAD_FUNC_SHARE(129)>;
|
||
|
+ bias-pull-up;
|
||
|
+ drive-strength = <14>;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ slew-rate = <0>;
|
||
|
+ };
|
||
|
+ rx-pins {
|
||
|
+ pins = <PAD_FUNC_SHARE(128)>,
|
||
|
+ <PAD_FUNC_SHARE(130)>,
|
||
|
+ <PAD_FUNC_SHARE(131)>,
|
||
|
+ <PAD_FUNC_SHARE(132)>,
|
||
|
+ <PAD_FUNC_SHARE(133)>,
|
||
|
+ <PAD_FUNC_SHARE(134)>,
|
||
|
+ <PAD_FUNC_SHARE(135)>,
|
||
|
+ <PAD_FUNC_SHARE(136)>,
|
||
|
+ <PAD_FUNC_SHARE(137)>,
|
||
|
+ <PAD_FUNC_SHARE(138)>,
|
||
|
+ <PAD_FUNC_SHARE(139)>,
|
||
|
+ <PAD_FUNC_SHARE(140)>,
|
||
|
+ <PAD_FUNC_SHARE(141)>;
|
||
|
+ bias-pull-up;
|
||
|
+ drive-strength = <14>;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ slew-rate = <0>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ i2c0_pins: i2c0-0 {
|
||
|
+ i2c-pins {
|
||
|
+ pinmux = <GPIOMUX(62, GPO_LOW,
|
||
|
+ GPO_I2C0_PAD_SCK_OEN,
|
||
|
+ GPI_I2C0_PAD_SCK_IN)>,
|
||
|
+ <GPIOMUX(61, GPO_LOW,
|
||
|
+ GPO_I2C0_PAD_SDA_OEN,
|
||
|
+ GPI_I2C0_PAD_SDA_IN)>;
|
||
|
+ bias-disable; /* external pull-up */
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ i2c1_pins: i2c1-0 {
|
||
|
+ i2c-pins {
|
||
|
+ pinmux = <GPIOMUX(47, GPO_LOW,
|
||
|
+ GPO_I2C1_PAD_SCK_OEN,
|
||
|
+ GPI_I2C1_PAD_SCK_IN)>,
|
||
|
+ <GPIOMUX(48, GPO_LOW,
|
||
|
+ GPO_I2C1_PAD_SDA_OEN,
|
||
|
+ GPI_I2C1_PAD_SDA_IN)>;
|
||
|
+ bias-pull-up;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ i2c2_pins: i2c2-0 {
|
||
|
+ i2c-pins {
|
||
|
+ pinmux = <GPIOMUX(60, GPO_LOW,
|
||
|
+ GPO_I2C2_PAD_SCK_OEN,
|
||
|
+ GPI_I2C2_PAD_SCK_IN)>,
|
||
|
+ <GPIOMUX(59, GPO_LOW,
|
||
|
+ GPO_I2C2_PAD_SDA_OEN,
|
||
|
+ GPI_I2C2_PAD_SDA_IN)>;
|
||
|
+ bias-disable; /* external pull-up */
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ pwmdac_pins: pwmdac-0 {
|
||
|
+ pwmdac-pins {
|
||
|
+ pinmux = <GPIOMUX(23, GPO_PWMDAC_LEFT_OUT,
|
||
|
+ GPO_ENABLE, GPI_NONE)>,
|
||
|
+ <GPIOMUX(24, GPO_PWMDAC_RIGHT_OUT,
|
||
|
+ GPO_ENABLE, GPI_NONE)>;
|
||
|
+ bias-disable;
|
||
|
+ drive-strength = <35>;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ slew-rate = <0>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ pwm_pins: pwm-0 {
|
||
|
+ pwm-pins {
|
||
|
+ pinmux = <GPIOMUX(7,
|
||
|
+ GPO_PWM_PAD_OUT_BIT0,
|
||
|
+ GPO_PWM_PAD_OE_N_BIT0,
|
||
|
+ GPI_NONE)>,
|
||
|
+ <GPIOMUX(5,
|
||
|
+ GPO_PWM_PAD_OUT_BIT1,
|
||
|
+ GPO_PWM_PAD_OE_N_BIT1,
|
||
|
+ GPI_NONE)>;
|
||
|
+ bias-disable;
|
||
|
+ drive-strength = <35>;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ slew-rate = <0>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ sdio0_pins: sdio0-0 {
|
||
|
+ clk-pins {
|
||
|
+ pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
|
||
|
+ GPO_ENABLE, GPI_NONE)>;
|
||
|
+ bias-disable;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ };
|
||
|
+ sdio-pins {
|
||
|
+ pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
|
||
|
+ GPI_SDIO0_PAD_CARD_DETECT_N)>,
|
||
|
+ <GPIOMUX(53,
|
||
|
+ GPO_SDIO0_PAD_CCMD_OUT,
|
||
|
+ GPO_SDIO0_PAD_CCMD_OEN,
|
||
|
+ GPI_SDIO0_PAD_CCMD_IN)>,
|
||
|
+ <GPIOMUX(49,
|
||
|
+ GPO_SDIO0_PAD_CDATA_OUT_BIT0,
|
||
|
+ GPO_SDIO0_PAD_CDATA_OEN_BIT0,
|
||
|
+ GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
|
||
|
+ <GPIOMUX(50,
|
||
|
+ GPO_SDIO0_PAD_CDATA_OUT_BIT1,
|
||
|
+ GPO_SDIO0_PAD_CDATA_OEN_BIT1,
|
||
|
+ GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
|
||
|
+ <GPIOMUX(51,
|
||
|
+ GPO_SDIO0_PAD_CDATA_OUT_BIT2,
|
||
|
+ GPO_SDIO0_PAD_CDATA_OEN_BIT2,
|
||
|
+ GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
|
||
|
+ <GPIOMUX(52,
|
||
|
+ GPO_SDIO0_PAD_CDATA_OUT_BIT3,
|
||
|
+ GPO_SDIO0_PAD_CDATA_OEN_BIT3,
|
||
|
+ GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
|
||
|
+ bias-pull-up;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ sdio1_pins: sdio1-0 {
|
||
|
+ clk-pins {
|
||
|
+ pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
|
||
|
+ GPO_ENABLE, GPI_NONE)>;
|
||
|
+ bias-disable;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ };
|
||
|
+ sdio-pins {
|
||
|
+ pinmux = <GPIOMUX(29,
|
||
|
+ GPO_SDIO1_PAD_CCMD_OUT,
|
||
|
+ GPO_SDIO1_PAD_CCMD_OEN,
|
||
|
+ GPI_SDIO1_PAD_CCMD_IN)>,
|
||
|
+ <GPIOMUX(36,
|
||
|
+ GPO_SDIO1_PAD_CDATA_OUT_BIT0,
|
||
|
+ GPO_SDIO1_PAD_CDATA_OEN_BIT0,
|
||
|
+ GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
|
||
|
+ <GPIOMUX(30,
|
||
|
+ GPO_SDIO1_PAD_CDATA_OUT_BIT1,
|
||
|
+ GPO_SDIO1_PAD_CDATA_OEN_BIT1,
|
||
|
+ GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
|
||
|
+ <GPIOMUX(34,
|
||
|
+ GPO_SDIO1_PAD_CDATA_OUT_BIT2,
|
||
|
+ GPO_SDIO1_PAD_CDATA_OEN_BIT2,
|
||
|
+ GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
|
||
|
+ <GPIOMUX(31,
|
||
|
+ GPO_SDIO1_PAD_CDATA_OUT_BIT3,
|
||
|
+ GPO_SDIO1_PAD_CDATA_OEN_BIT3,
|
||
|
+ GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
|
||
|
+ bias-pull-up;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ spi2_pins: spi2-0 {
|
||
|
+ mosi-pins {
|
||
|
+ pinmux = <GPIOMUX(18, GPO_SPI2_PAD_TXD,
|
||
|
+ GPO_ENABLE, GPI_NONE)>;
|
||
|
+ bias-disable;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ };
|
||
|
+ miso-pins {
|
||
|
+ pinmux = <GPIOMUX(16, GPO_LOW, GPO_DISABLE,
|
||
|
+ GPI_SPI2_PAD_RXD)>;
|
||
|
+ bias-pull-up;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ };
|
||
|
+ sck-pins {
|
||
|
+ pinmux = <GPIOMUX(12, GPO_SPI2_PAD_SCK_OUT,
|
||
|
+ GPO_ENABLE, GPI_NONE)>;
|
||
|
+ bias-disable;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ };
|
||
|
+ ss-pins {
|
||
|
+ pinmux = <GPIOMUX(15, GPO_SPI2_PAD_SS_0_N,
|
||
|
+ GPO_ENABLE, GPI_NONE)>,
|
||
|
+ <GPIOMUX(11, GPO_SPI2_PAD_SS_1_N,
|
||
|
+ GPO_ENABLE, GPI_NONE)>;
|
||
|
+ bias-disable;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ uart0_pins: uart0-0 {
|
||
|
+ rx-pins {
|
||
|
+ pinmux = <GPIOMUX(40, GPO_LOW, GPO_DISABLE,
|
||
|
+ GPI_UART0_PAD_SIN)>,
|
||
|
+ <GPIOMUX(39, GPO_LOW, GPO_DISABLE,
|
||
|
+ GPI_UART0_PAD_CTSN)>;
|
||
|
+ bias-pull-up;
|
||
|
+ drive-strength = <14>;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ };
|
||
|
+ tx-pins {
|
||
|
+ pinmux = <GPIOMUX(41, GPO_UART0_PAD_SOUT,
|
||
|
+ GPO_ENABLE, GPI_NONE)>,
|
||
|
+ <GPIOMUX(42, GPO_UART0_PAD_RTSN,
|
||
|
+ GPO_ENABLE, GPI_NONE)>;
|
||
|
+ bias-disable;
|
||
|
+ drive-strength = <35>;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ uart3_pins: uart3-0 {
|
||
|
+ rx-pins {
|
||
|
+ pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
|
||
|
+ GPI_UART3_PAD_SIN)>;
|
||
|
+ bias-pull-up;
|
||
|
+ drive-strength = <14>;
|
||
|
+ input-enable;
|
||
|
+ input-schmitt-enable;
|
||
|
+ slew-rate = <0>;
|
||
|
+ };
|
||
|
+ tx-pins {
|
||
|
+ pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
|
||
|
+ GPO_ENABLE, GPI_NONE)>;
|
||
|
+ bias-disable;
|
||
|
+ drive-strength = <35>;
|
||
|
+ input-disable;
|
||
|
+ input-schmitt-disable;
|
||
|
+ slew-rate = <0>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+};
|
||
|
+
|
||
|
+&i2c0 {
|
||
|
+ clock-frequency = <100000>;
|
||
|
+ i2c-sda-hold-time-ns = <300>;
|
||
|
+ i2c-sda-falling-time-ns = <500>;
|
||
|
+ i2c-scl-falling-time-ns = <500>;
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&i2c0_pins>;
|
||
|
+ status = "okay";
|
||
|
+
|
||
|
+ pmic@5e {
|
||
|
+ compatible = "ti,tps65086";
|
||
|
+ reg = <0x5e>;
|
||
|
+ gpio-controller;
|
||
|
+ #gpio-cells = <2>;
|
||
|
+
|
||
|
+ regulators {
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ tda998x@70 {
|
||
|
+ compatible = "nxp,tda998x";
|
||
|
+ reg = <0x70>;
|
||
|
+
|
||
|
+ port {
|
||
|
+ tda998x_0_input: endpoint {
|
||
|
+ remote-endpoint = <&hdmi_out>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+ };
|
||
|
+};
|
||
|
+
|
||
|
+&i2c1 {
|
||
|
+ clock-frequency = <400000>;
|
||
|
+ i2c-sda-hold-time-ns = <300>;
|
||
|
+ i2c-sda-falling-time-ns = <100>;
|
||
|
+ i2c-scl-falling-time-ns = <100>;
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&i2c1_pins>;
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
+
|
||
|
+&i2c2 {
|
||
|
+ clock-frequency = <100000>;
|
||
|
+ i2c-sda-hold-time-ns = <300>;
|
||
|
+ i2c-sda-falling-time-ns = <500>;
|
||
|
+ i2c-scl-falling-time-ns = <500>;
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&i2c2_pins>;
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
+
|
||
|
+&osc_sys {
|
||
|
+ clock-frequency = <25000000>;
|
||
|
+};
|
||
|
+
|
||
|
+&osc_aud {
|
||
|
+ clock-frequency = <27000000>;
|
||
|
+};
|
||
|
+
|
||
|
+&ptc {
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&pwm_pins>;
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
+
|
||
|
+&pwmdac {
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&pwmdac_pins>;
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
+
|
||
|
+&qspi {
|
||
|
+ nor_flash: nor-flash@0 {
|
||
|
+ compatible = "spi-flash";
|
||
|
+ reg = <0>;
|
||
|
+ spi-max-frequency = <31250000>;
|
||
|
+ page-size = <256>;
|
||
|
+ block-size = <16>;
|
||
|
+ cdns,read-delay = <4>;
|
||
|
+ cdns,tshsl-ns = <1>;
|
||
|
+ cdns,tsd2d-ns = <1>;
|
||
|
+ cdns,tchsh-ns = <1>;
|
||
|
+ cdns,tslch-ns = <1>;
|
||
|
+ spi-tx-bus-width = <1>;
|
||
|
+ spi-rx-bus-width = <1>;
|
||
|
+ };
|
||
|
+
|
||
|
+ nand_flash: nand-flash@1 {
|
||
|
+ compatible = "spi-flash-nand";
|
||
|
+ reg = <1>;
|
||
|
+ spi-max-frequency = <31250000>;
|
||
|
+ page-size = <2048>;
|
||
|
+ block-size = <17>;
|
||
|
+ cdns,read-delay = <4>;
|
||
|
+ cdns,tshsl-ns = <1>;
|
||
|
+ cdns,tsd2d-ns = <1>;
|
||
|
+ cdns,tchsh-ns = <1>;
|
||
|
+ cdns,tslch-ns = <1>;
|
||
|
+ spi-tx-bus-width = <1>;
|
||
|
+ spi-rx-bus-width = <1>;
|
||
|
+ };
|
||
|
+};
|
||
|
+
|
||
|
+&sdio0 {
|
||
|
+ broken-cd;
|
||
|
+ bus-width = <4>;
|
||
|
+ cap-sd-highspeed;
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&sdio0_pins>;
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
+
|
||
|
+&sdio1 {
|
||
|
+ #address-cells = <1>;
|
||
|
+ #size-cells = <0>;
|
||
|
+ bus-width = <4>;
|
||
|
+ cap-sd-highspeed;
|
||
|
+ cap-sdio-irq;
|
||
|
+ cap-power-off-card;
|
||
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
||
|
+ non-removable;
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&sdio1_pins>;
|
||
|
+ status = "okay";
|
||
|
+
|
||
|
+ wifi@1 {
|
||
|
+ compatible = "brcm,bcm4329-fmac";
|
||
|
+ reg = <1>;
|
||
|
+ };
|
||
|
+};
|
||
|
+
|
||
|
+&spi2 {
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&spi2_pins>;
|
||
|
+ status = "okay";
|
||
|
+
|
||
|
+ spi_dev0: spi@0 {
|
||
|
+ compatible = "rohm,dh2228fv";
|
||
|
+ spi-max-frequency = <10000000>;
|
||
|
+ reg = <0>;
|
||
|
+ };
|
||
|
+};
|
||
|
+
|
||
|
+&uart0 {
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&uart0_pins>;
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
+
|
||
|
+&uart3 {
|
||
|
+ pinctrl-names = "default";
|
||
|
+ pinctrl-0 = <&uart3_pins>;
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
+
|
||
|
+&usb3 {
|
||
|
+ dr_mode = "host";
|
||
|
+ status = "okay";
|
||
|
+};
|
||
|
diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
|
||
|
new file mode 100644
|
||
|
index 000000000000..68616a1c9cf6
|
||
|
--- /dev/null
|
||
|
+++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
|
||
|
@@ -0,0 +1,32 @@
|
||
|
+// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||
|
+/*
|
||
|
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
|
||
|
+ */
|
||
|
+
|
||
|
+/dts-v1/;
|
||
|
+#include "jh7100-common.dtsi"
|
||
|
+#include <dt-bindings/gpio/gpio.h>
|
||
|
+
|
||
|
+/ {
|
||
|
+ model = "StarFive VisionFive V1";
|
||
|
+ compatible = "starfive,visionfive-v1", "starfive,jh7100";
|
||
|
+
|
||
|
+ gpio-restart {
|
||
|
+ compatible = "gpio-restart";
|
||
|
+ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
|
||
|
+ priority = <224>;
|
||
|
+ };
|
||
|
+};
|
||
|
+
|
||
|
+&gpio {
|
||
|
+ /* don't reset gpio mux for serial console and reset gpio */
|
||
|
+ starfive,keep-gpiomux = <13 14 63>;
|
||
|
+};
|
||
|
+
|
||
|
+&i2c0 {
|
||
|
+ eeprom@50 {
|
||
|
+ compatible = "atmel,24c04";
|
||
|
+ reg = <0x50>;
|
||
|
+ pagesize = <16>;
|
||
|
+ };
|
||
|
+};
|
||
|
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
||
|
index 9f387fdf4afc..94b3519f5849 100644
|
||
|
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
||
|
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
||
|
@@ -6,7 +6,9 @@
|
||
|
|
||
|
/dts-v1/;
|
||
|
#include <dt-bindings/clock/starfive-jh7100.h>
|
||
|
+#include <dt-bindings/clock/starfive-jh7100-audio.h>
|
||
|
#include <dt-bindings/reset/starfive-jh7100.h>
|
||
|
+#include <dt-bindings/reset/starfive-jh7100-audio.h>
|
||
|
|
||
|
/ {
|
||
|
compatible = "starfive,jh7100";
|
||
|
@@ -32,7 +34,9 @@ U74_0: cpu@0 {
|
||
|
i-tlb-sets = <1>;
|
||
|
i-tlb-size = <32>;
|
||
|
mmu-type = "riscv,sv39";
|
||
|
+ next-level-cache = <&ccache>;
|
||
|
riscv,isa = "rv64imafdc";
|
||
|
+ starfive,itim = <&itim0>;
|
||
|
tlb-split;
|
||
|
|
||
|
cpu0_intc: interrupt-controller {
|
||
|
@@ -57,7 +61,9 @@ U74_1: cpu@1 {
|
||
|
i-tlb-sets = <1>;
|
||
|
i-tlb-size = <32>;
|
||
|
mmu-type = "riscv,sv39";
|
||
|
+ next-level-cache = <&ccache>;
|
||
|
riscv,isa = "rv64imafdc";
|
||
|
+ starfive,itim = <&itim1>;
|
||
|
tlb-split;
|
||
|
|
||
|
cpu1_intc: interrupt-controller {
|
||
|
@@ -116,6 +122,24 @@ soc {
|
||
|
#size-cells = <2>;
|
||
|
ranges;
|
||
|
|
||
|
+ dtim: dtim@1000000 {
|
||
|
+ compatible = "starfive,dtim0";
|
||
|
+ reg = <0x0 0x1000000 0x0 0x2000>;
|
||
|
+ reg-names = "mem";
|
||
|
+ };
|
||
|
+
|
||
|
+ itim0: itim@1808000 {
|
||
|
+ compatible = "starfive,itim0";
|
||
|
+ reg = <0x0 0x1808000 0x0 0x8000>;
|
||
|
+ reg-names = "mem";
|
||
|
+ };
|
||
|
+
|
||
|
+ itim1: itim@1820000 {
|
||
|
+ compatible = "starfive,itim0";
|
||
|
+ reg = <0x0 0x1820000 0x0 0x8000>;
|
||
|
+ reg-names = "mem";
|
||
|
+ };
|
||
|
+
|
||
|
clint: clint@2000000 {
|
||
|
compatible = "starfive,jh7100-clint", "sifive,clint0";
|
||
|
reg = <0x0 0x2000000 0x0 0x10000>;
|
||
|
@@ -123,6 +147,21 @@ clint: clint@2000000 {
|
||
|
<&cpu1_intc 3>, <&cpu1_intc 7>;
|
||
|
};
|
||
|
|
||
|
+ ccache: cache-controller@2010000 {
|
||
|
+ compatible = "starfive,jh7100-ccache", "cache";
|
||
|
+ reg = <0x0 0x2010000 0x0 0x1000>,
|
||
|
+ <0x0 0x8000000 0x0 0x2000000>;
|
||
|
+ reg-names = "control", "sideband";
|
||
|
+ interrupts = <128>, <130>, <131>, <129>;
|
||
|
+ cache-block-size = <64>;
|
||
|
+ cache-level = <2>;
|
||
|
+ cache-sets = <2048>;
|
||
|
+ cache-size = <2097152>;
|
||
|
+ cache-unified;
|
||
|
+ /*next-level-cache = <&L40 &L36>;*/
|
||
|
+ uncached-offset = <0xf 0x80000000>;
|
||
|
+ };
|
||
|
+
|
||
|
plic: interrupt-controller@c000000 {
|
||
|
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
|
||
|
reg = <0x0 0xc000000 0x0 0x4000000>;
|
||
|
@@ -134,6 +173,182 @@ plic: interrupt-controller@c000000 {
|
||
|
riscv,ndev = <133>;
|
||
|
};
|
||
|
|
||
|
+ sdio0: mmc@10000000 {
|
||
|
+ compatible = "snps,dw-mshc";
|
||
|
+ reg = <0x0 0x10000000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
|
||
|
+ <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
|
||
|
+ clock-names = "biu", "ciu";
|
||
|
+ interrupts = <4>;
|
||
|
+ data-addr = <0>;
|
||
|
+ fifo-depth = <32>;
|
||
|
+ fifo-watermark-aligned;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ sdio1: mmc@10010000 {
|
||
|
+ compatible = "snps,dw-mshc";
|
||
|
+ reg = <0x0 0x10010000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
|
||
|
+ <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
|
||
|
+ clock-names = "biu", "ciu";
|
||
|
+ interrupts = <5>;
|
||
|
+ data-addr = <0>;
|
||
|
+ fifo-depth = <32>;
|
||
|
+ fifo-watermark-aligned;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ /* gmac device configuration */
|
||
|
+ stmmac_axi_setup: stmmac-axi-config {
|
||
|
+ snps,wr_osr_lmt = <0xf>;
|
||
|
+ snps,rd_osr_lmt = <0xf>;
|
||
|
+ snps,blen = <256 128 64 32 0 0 0>;
|
||
|
+ };
|
||
|
+
|
||
|
+ gmac: ethernet@10020000 {
|
||
|
+ compatible = "starfive,jh7100-gmac", "snps,dwmac";
|
||
|
+ reg = <0x0 0x10020000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
|
||
|
+ <&clkgen JH7100_CLK_GMAC_AHB>,
|
||
|
+ <&clkgen JH7100_CLK_GMAC_PTP_REF>,
|
||
|
+ <&clkgen JH7100_CLK_GMAC_GTX>,
|
||
|
+ <&clkgen JH7100_CLK_GMAC_TX_INV>;
|
||
|
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "gtxc", "tx";
|
||
|
+ resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
|
||
|
+ reset-names = "ahb";
|
||
|
+ interrupts = <6>, <7>;
|
||
|
+ interrupt-names = "macirq", "eth_wake_irq";
|
||
|
+ max-frame-size = <9000>;
|
||
|
+ phy-mode = "rgmii-txid";
|
||
|
+ snps,multicast-filter-bins = <32>;
|
||
|
+ snps,perfect-filter-entries = <128>;
|
||
|
+ starfive,syscon = <&sysmain>;
|
||
|
+ rx-fifo-depth = <32768>;
|
||
|
+ tx-fifo-depth = <16384>;
|
||
|
+ snps,axi-config = <&stmmac_axi_setup>;
|
||
|
+ snps,fixed-burst;
|
||
|
+ /*snps,force_sf_dma_mode;*/
|
||
|
+ snps,force_thresh_dma_mode;
|
||
|
+ snps,no-pbl-x8;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ dma2p: dma-controller@100b0000 {
|
||
|
+ compatible = "snps,axi-dma-1.01a";
|
||
|
+ reg = <0x0 0x100b0000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
|
||
|
+ <&clkgen JH7100_CLK_SGDMA2P_AHB>;
|
||
|
+ clock-names = "core-clk", "cfgr-clk";
|
||
|
+ interrupts = <2>;
|
||
|
+ #dma-cells = <1>;
|
||
|
+ dma-channels = <4>;
|
||
|
+ snps,dma-masters = <1>;
|
||
|
+ snps,data-width = <4>;
|
||
|
+ snps,block-size = <4096 4096 4096 4096>;
|
||
|
+ snps,priority = <0 1 2 3>;
|
||
|
+ snps,axi-max-burst-len = <128>;
|
||
|
+ dma-coherent;
|
||
|
+ };
|
||
|
+
|
||
|
+ crypto: crypto@100d0000 {
|
||
|
+ compatible = "starfive,vic-sec";
|
||
|
+ reg = <0x0 0x100d0000 0x0 0x20000>,
|
||
|
+ <0x0 0x11800234 0x0 0xc>;
|
||
|
+ reg-names = "secmem", "secclk";
|
||
|
+ clocks = <&clkgen JH7100_CLK_SEC_AHB>;
|
||
|
+ interrupts = <31>;
|
||
|
+ };
|
||
|
+
|
||
|
+ i2sadc0: i2sadc0@10400000 {
|
||
|
+ compatible = "snps,designware-i2sadc0";
|
||
|
+ reg = <0x0 0x10400000 0x0 0x1000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_APB1_BUS>;
|
||
|
+ clock-names = "i2sclk";
|
||
|
+ interrupt-parent = <&plic>;
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ dmas = <&dma2p 28>;
|
||
|
+ dma-names = "rx";
|
||
|
+ };
|
||
|
+
|
||
|
+ i2svad: i2svad@10420000 {
|
||
|
+ compatible = "starfive,sf-i2svad";
|
||
|
+ reg = <0x0 0x10420000 0x0 0x1000> ;
|
||
|
+ clocks = <&audclk JH7100_AUDCLK_I2SVAD_APB>;
|
||
|
+ clock-names = "i2svad_apb";
|
||
|
+ resets = <&audrst JH7100_AUDRSTN_I2SVAD_APB>,
|
||
|
+ <&audrst JH7100_AUDRSTN_I2SVAD_SRST>;
|
||
|
+ reset-names = "apb_i2svad", "i2svad_srst";
|
||
|
+ interrupts = <60>, <61>;
|
||
|
+ interrupt-names = "spintr", "slintr";
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ };
|
||
|
+
|
||
|
+ pwmdac: pwmdac@10440000 {
|
||
|
+ compatible = "starfive,pwmdac";
|
||
|
+ reg = <0x0 0x10440000 0x0 0x1000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_AUDIO_ROOT>,
|
||
|
+ <&clkgen JH7100_CLK_AUDIO_SRC>,
|
||
|
+ <&clkgen JH7100_CLK_AUDIO_12288>,
|
||
|
+ <&audclk JH7100_AUDCLK_DMA1P_AHB>,
|
||
|
+ <&audclk JH7100_AUDCLK_PWMDAC_APB>,
|
||
|
+ <&audclk JH7100_AUDCLK_DAC_MCLK>;
|
||
|
+ clock-names = "audio_root",
|
||
|
+ "audio_src",
|
||
|
+ "audio_12288",
|
||
|
+ "dma1p_ahb",
|
||
|
+ "pwmdac_apb",
|
||
|
+ "dac_mclk";
|
||
|
+ resets = <&audrst JH7100_AUDRSTN_APB_BUS>,
|
||
|
+ <&audrst JH7100_AUDRSTN_DMA1P_AHB>,
|
||
|
+ <&audrst JH7100_AUDRSTN_PWMDAC_APB>;
|
||
|
+ reset-names = "apb_bus", "dma1p_ahb", "apb_pwmdac";
|
||
|
+ dmas = <&dma2p 23>;
|
||
|
+ dma-names = "tx";
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ };
|
||
|
+
|
||
|
+ i2sdac0: i2sdac0@10450000 {
|
||
|
+ compatible = "snps,designware-i2sdac0";
|
||
|
+ reg = <0x0 0x10450000 0x0 0x1000>;
|
||
|
+ clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
|
||
|
+ <&audclk JH7100_AUDCLK_I2SDAC_BCLK>,
|
||
|
+ <&audclk JH7100_AUDCLK_I2SDAC_LRCLK>,
|
||
|
+ <&audclk JH7100_AUDCLK_I2SDAC_APB>;
|
||
|
+ clock-names = "dac_mclk", "i2sdac0_bclk", "i2sdac0_lrclk", "i2sdac_apb";
|
||
|
+ resets = <&audrst JH7100_AUDRSTN_I2SDAC_APB>,
|
||
|
+ <&audrst JH7100_AUDRSTN_I2SDAC_SRST>;
|
||
|
+ reset-names = "apb_i2sdac", "i2sdac_srst";
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ dmas = <&dma2p 30>;
|
||
|
+ dma-names = "tx";
|
||
|
+ };
|
||
|
+
|
||
|
+ i2sdac1: i2sdac1@10460000 {
|
||
|
+ compatible = "snps,designware-i2sdac1";
|
||
|
+ reg = <0x0 0x10460000 0x0 0x1000>;
|
||
|
+ clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
|
||
|
+ <&audclk JH7100_AUDCLK_I2S1_BCLK>,
|
||
|
+ <&audclk JH7100_AUDCLK_I2S1_LRCLK>,
|
||
|
+ <&audclk JH7100_AUDCLK_I2S1_APB>;
|
||
|
+ clock-names = "dac_mclk", "i2sdac1_bclk", "i2sdac1_lrclk", "i2s1_apb";
|
||
|
+ resets = <&audrst JH7100_AUDRSTN_I2S1_APB>,
|
||
|
+ <&audrst JH7100_AUDRSTN_I2S1_SRST>;
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ dmas = <&dma2p 31>;
|
||
|
+ dma-names = "tx";
|
||
|
+ };
|
||
|
+
|
||
|
+ i2sdac16k: i2sdac16k@10470000 {
|
||
|
+ compatible = "snps,designware-i2sdac16k";
|
||
|
+ reg = <0x0 0x10470000 0x0 0x1000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_APB1_BUS>;
|
||
|
+ clock-names = "i2sclk";
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ dmas = <&dma2p 29>;
|
||
|
+ dma-names = "tx";
|
||
|
+ };
|
||
|
+
|
||
|
audclk: clock-controller@10480000 {
|
||
|
compatible = "starfive,jh7100-audclk";
|
||
|
reg = <0x0 0x10480000 0x0 0x10000>;
|
||
|
@@ -150,6 +365,79 @@ audrst: reset-controller@10490000 {
|
||
|
#reset-cells = <1>;
|
||
|
};
|
||
|
|
||
|
+ spdif_transmitter: spdif-transmitter {
|
||
|
+ compatible = "linux,spdif-dit";
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ };
|
||
|
+
|
||
|
+ spdif_receiver: spdif-receiver {
|
||
|
+ compatible = "linux,spdif-dir";
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ };
|
||
|
+
|
||
|
+ pwmdac_codec: pwmdac-transmitter {
|
||
|
+ compatible = "linux,pwmdac-dit";
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ };
|
||
|
+
|
||
|
+ dmic_codec: dmic {
|
||
|
+ compatible = "dmic-codec";
|
||
|
+ #sound-dai-cells = <0>;
|
||
|
+ };
|
||
|
+
|
||
|
+ sound: snd-card {
|
||
|
+ compatible = "simple-audio-card";
|
||
|
+ simple-audio-card,name = "Starfive-Multi-Sound-Card";
|
||
|
+ #address-cells = <1>;
|
||
|
+ #size-cells = <0>;
|
||
|
+
|
||
|
+ /* pwmdac */
|
||
|
+ simple-audio-card,dai-link@0 {
|
||
|
+ reg = <0>;
|
||
|
+ status = "okay";
|
||
|
+ format = "left_j";
|
||
|
+ bitclock-master = <&sndcpu0>;
|
||
|
+ frame-master = <&sndcpu0>;
|
||
|
+
|
||
|
+ sndcpu0: cpu {
|
||
|
+ sound-dai = <&pwmdac>;
|
||
|
+ };
|
||
|
+
|
||
|
+ codec {
|
||
|
+ sound-dai = <&pwmdac_codec>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ usb3: usb@104c0000 {
|
||
|
+ compatible = "cdns,usb3";
|
||
|
+ reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
|
||
|
+ <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
|
||
|
+ <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
|
||
|
+ reg-names = "otg", "xhci", "dev";
|
||
|
+ interrupts = <44>, <52>, <43>;
|
||
|
+ interrupt-names = "host", "peripheral", "otg";
|
||
|
+ phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
|
||
|
+ maximum-speed = "super-speed";
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ dma1p: dma-controller@10500000 {
|
||
|
+ compatible = "snps,axi-dma-1.01a";
|
||
|
+ reg = <0x0 0x10500000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
|
||
|
+ <&clkgen JH7100_CLK_SGDMA1P_BUS>;
|
||
|
+ clock-names = "core-clk", "cfgr-clk";
|
||
|
+ interrupts = <1>;
|
||
|
+ #dma-cells = <1>;
|
||
|
+ dma-channels = <16>;
|
||
|
+ snps,dma-masters = <1>;
|
||
|
+ snps,data-width = <3>;
|
||
|
+ snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
|
||
|
+ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||
|
+ snps,axi-max-burst-len = <64>;
|
||
|
+ };
|
||
|
+
|
||
|
clkgen: clock-controller@11800000 {
|
||
|
compatible = "starfive,jh7100-clkgen";
|
||
|
reg = <0x0 0x11800000 0x0 0x10000>;
|
||
|
@@ -158,12 +446,93 @@ clkgen: clock-controller@11800000 {
|
||
|
#clock-cells = <1>;
|
||
|
};
|
||
|
|
||
|
+ otp: otp@11810000 {
|
||
|
+ compatible = "starfive,fu740-otp";
|
||
|
+ reg = <0x0 0x11810000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_OTP_APB>;
|
||
|
+ fuse-count = <0x200>;
|
||
|
+ };
|
||
|
+
|
||
|
rstgen: reset-controller@11840000 {
|
||
|
compatible = "starfive,jh7100-reset";
|
||
|
reg = <0x0 0x11840000 0x0 0x10000>;
|
||
|
#reset-cells = <1>;
|
||
|
};
|
||
|
|
||
|
+ sysmain: syscon@11850000 {
|
||
|
+ compatible = "starfive,jh7100-sysmain", "syscon";
|
||
|
+ reg = <0x0 0x11850000 0x0 0x10000>;
|
||
|
+ };
|
||
|
+
|
||
|
+ qspi: spi@11860000 {
|
||
|
+ compatible = "cdns,qspi-nor";
|
||
|
+ reg = <0x0 0x11860000 0x0 0x10000>,
|
||
|
+ <0x0 0x20000000 0x0 0x20000000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
|
||
|
+ interrupts = <3>;
|
||
|
+ #address-cells = <1>;
|
||
|
+ #size-cells = <0>;
|
||
|
+ cdns,fifo-depth = <256>;
|
||
|
+ cdns,fifo-width = <4>;
|
||
|
+ cdns,trigger-address = <0x0>;
|
||
|
+ spi-max-frequency = <250000000>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ uart0: serial@11870000 {
|
||
|
+ compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
|
||
|
+ reg = <0x0 0x11870000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_UART0_CORE>,
|
||
|
+ <&clkgen JH7100_CLK_UART0_APB>;
|
||
|
+ clock-names = "baudclk", "apb_pclk";
|
||
|
+ resets = <&rstgen JH7100_RSTN_UART0_APB>;
|
||
|
+ interrupts = <92>;
|
||
|
+ reg-io-width = <4>;
|
||
|
+ reg-shift = <2>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ uart1: serial@11880000 {
|
||
|
+ compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
|
||
|
+ reg = <0x0 0x11880000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_UART1_CORE>,
|
||
|
+ <&clkgen JH7100_CLK_UART1_APB>;
|
||
|
+ clock-names = "baudclk", "apb_pclk";
|
||
|
+ resets = <&rstgen JH7100_RSTN_UART1_APB>;
|
||
|
+ interrupts = <93>;
|
||
|
+ reg-io-width = <4>;
|
||
|
+ reg-shift = <2>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ spi0: spi@11890000 {
|
||
|
+ compatible = "snps,dw-apb-ssi";
|
||
|
+ reg = <0x0 0x11890000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
|
||
|
+ <&clkgen JH7100_CLK_SPI0_APB>;
|
||
|
+ clock-names = "ssi_clk", "pclk";
|
||
|
+ resets = <&rstgen JH7100_RSTN_SPI0_APB>;
|
||
|
+ reset-names = "spi";
|
||
|
+ interrupts = <94>;
|
||
|
+ #address-cells = <1>;
|
||
|
+ #size-cells = <0>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ spi1: spi@118a0000 {
|
||
|
+ compatible = "snps,dw-apb-ssi";
|
||
|
+ reg = <0x0 0x118a0000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
|
||
|
+ <&clkgen JH7100_CLK_SPI1_APB>;
|
||
|
+ clock-names = "ssi_clk", "pclk";
|
||
|
+ resets = <&rstgen JH7100_RSTN_SPI1_APB>;
|
||
|
+ reset-names = "spi";
|
||
|
+ interrupts = <95>;
|
||
|
+ #address-cells = <1>;
|
||
|
+ #size-cells = <0>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
i2c0: i2c@118b0000 {
|
||
|
compatible = "snps,designware-i2c";
|
||
|
reg = <0x0 0x118b0000 0x0 0x10000>;
|
||
|
@@ -190,6 +559,41 @@ i2c1: i2c@118c0000 {
|
||
|
status = "disabled";
|
||
|
};
|
||
|
|
||
|
+ trng: trng@118d0000 {
|
||
|
+ compatible = "starfive,vic-rng";
|
||
|
+ reg = <0x0 0x118d0000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_TRNG_APB>;
|
||
|
+ interrupts = <98>;
|
||
|
+ };
|
||
|
+
|
||
|
+ vpu_enc: vpu_enc@118e0000 {
|
||
|
+ compatible = "cm,cm521-vpu";
|
||
|
+ reg = <0x0 0x118e0000 0x0 0x4000>;
|
||
|
+ reg-names = "control";
|
||
|
+ clocks = <&clkgen JH7100_CLK_VP6_CORE>;
|
||
|
+ clock-names = "vcodec";
|
||
|
+ interrupts = <26>;
|
||
|
+ };
|
||
|
+
|
||
|
+ vpu_dec: vpu_dec@118f0000 {
|
||
|
+ compatible = "c&m,cm511-vpu";
|
||
|
+ reg = <0 0x118f0000 0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_VP6_CORE>;
|
||
|
+ clock-names = "vcodec";
|
||
|
+ interrupts = <23>;
|
||
|
+ //memory-region = <&vpu_reserved>;
|
||
|
+ };
|
||
|
+
|
||
|
+ jpu: coadj12@11900000 {
|
||
|
+ compatible = "cm,codaj12-jpu-1";
|
||
|
+ reg = <0x0 0x11900000 0x0 0x300>;
|
||
|
+ reg-names = "control";
|
||
|
+ clocks = <&clkgen JH7100_CLK_JPEG_APB>;
|
||
|
+ clock-names = "jpege";
|
||
|
+ interrupts = <24>;
|
||
|
+ memory-region = <&jpu_reserved>;
|
||
|
+ };
|
||
|
+
|
||
|
gpio: pinctrl@11910000 {
|
||
|
compatible = "starfive,jh7100-pinctrl";
|
||
|
reg = <0x0 0x11910000 0x0 0x10000>,
|
||
|
@@ -204,6 +608,86 @@ gpio: pinctrl@11910000 {
|
||
|
#interrupt-cells = <2>;
|
||
|
};
|
||
|
|
||
|
+ nvdla@11940000 {
|
||
|
+ compatible = "nvidia,nvdla_os_initial";
|
||
|
+ interrupts = <22>;
|
||
|
+ memory-region = <&nvdla_reserved>;
|
||
|
+ reg = <0x0 0x11940000 0x0 0x40000>;
|
||
|
+ status = "okay";
|
||
|
+ };
|
||
|
+
|
||
|
+ display: display-subsystem {
|
||
|
+ compatible = "starfive,display-subsystem";
|
||
|
+ dma-coherent;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ encoder: display-encoder {
|
||
|
+ compatible = "starfive,display-encoder";
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ crtc: crtc@12000000 {
|
||
|
+ compatible = "starfive,jh7100-crtc";
|
||
|
+ reg = <0x0 0x12000000 0x0 0x10000>,
|
||
|
+ <0x0 0x12040000 0x0 0x10000>,
|
||
|
+ <0x0 0x12080000 0x0 0x10000>,
|
||
|
+ <0x0 0x120c0000 0x0 0x10000>,
|
||
|
+ <0x0 0x12240000 0x0 0x10000>,
|
||
|
+ <0x0 0x12250000 0x0 0x10000>,
|
||
|
+ <0x0 0x12260000 0x0 0x10000>;
|
||
|
+ reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
|
||
|
+ clocks = <&clkgen JH7100_CLK_DISP_AXI>, <&clkgen JH7100_CLK_VOUT_SRC>;
|
||
|
+ clock-names = "disp_axi", "vout_src";
|
||
|
+ resets = <&rstgen JH7100_RSTN_DISP_AXI>, <&rstgen JH7100_RSTN_VOUT_SRC>;
|
||
|
+ reset-names = "disp_axi", "vout_src";
|
||
|
+ interrupts = <101>, <103>;
|
||
|
+ interrupt-names = "lcdc_irq", "vpp1_irq";
|
||
|
+ #address-cells = <1>;
|
||
|
+ #size-cells = <0>;
|
||
|
+ status = "disabled";
|
||
|
+
|
||
|
+ pp1 {
|
||
|
+ pp-id = <1>;
|
||
|
+ fifo-out;
|
||
|
+ //sys-bus-out;
|
||
|
+ src-format = <11>; //<COLOR_RGB565>;
|
||
|
+ src-width = <1920>;
|
||
|
+ src-height = <1080>;
|
||
|
+ dst-format = <7>; //<COLOR_RGB888_ARGB>;
|
||
|
+ dst-width = <1920>;
|
||
|
+ dst-height = <1080>;
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ spi2: spi@12410000 {
|
||
|
+ compatible = "snps,dw-apb-ssi";
|
||
|
+ reg = <0x0 0x12410000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
|
||
|
+ <&clkgen JH7100_CLK_SPI2_APB>;
|
||
|
+ clock-names = "ssi_clk", "pclk";
|
||
|
+ resets = <&rstgen JH7100_RSTN_SPI2_APB>;
|
||
|
+ reset-names = "spi";
|
||
|
+ interrupts = <70>;
|
||
|
+ #address-cells = <1>;
|
||
|
+ #size-cells = <0>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ spi3: spi@12420000 {
|
||
|
+ compatible = "snps,dw-apb-ssi";
|
||
|
+ reg = <0x0 0x12420000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
|
||
|
+ <&clkgen JH7100_CLK_SPI3_APB>;
|
||
|
+ clock-names = "ssi_clk", "pclk";
|
||
|
+ resets = <&rstgen JH7100_RSTN_SPI3_APB>;
|
||
|
+ reset-names = "spi";
|
||
|
+ interrupts = <71>;
|
||
|
+ #address-cells = <1>;
|
||
|
+ #size-cells = <0>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
uart2: serial@12430000 {
|
||
|
compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
|
||
|
reg = <0x0 0x12430000 0x0 0x10000>;
|
||
|
@@ -255,5 +739,89 @@ i2c3: i2c@12460000 {
|
||
|
#size-cells = <0>;
|
||
|
status = "disabled";
|
||
|
};
|
||
|
+
|
||
|
+ watchdog@12480000 {
|
||
|
+ compatible = "starfive,si5-wdt";
|
||
|
+ reg = <0x0 0x12480000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_WDT_CORE>,
|
||
|
+ <&clkgen JH7100_CLK_WDTIMER_APB>;
|
||
|
+ clock-names = "wdt_coreclk", "wdtimer_apb";
|
||
|
+ resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
|
||
|
+ <&rstgen JH7100_RSTN_WDT>;
|
||
|
+ reset-names = "wdtimer_apb", "wdt";
|
||
|
+ interrupts = <80>;
|
||
|
+ };
|
||
|
+
|
||
|
+ ptc: pwm@12490000 {
|
||
|
+ compatible = "starfive,pwm0";
|
||
|
+ reg = <0x0 0x12490000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_PWM_APB>;
|
||
|
+ resets = <&rstgen JH7100_RSTN_PWM_APB>;
|
||
|
+ #pwm-cells = <3>;
|
||
|
+ sifive,npwm = <8>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ sfctemp: tmon@124a0000 {
|
||
|
+ compatible = "starfive,jh7100-temp";
|
||
|
+ reg = <0x0 0x124a0000 0x0 0x10000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
|
||
|
+ <&clkgen JH7100_CLK_TEMP_APB>;
|
||
|
+ clock-names = "sense", "bus";
|
||
|
+ resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
|
||
|
+ <&rstgen JH7100_RSTN_TEMP_APB>;
|
||
|
+ reset-names = "sense", "bus";
|
||
|
+ interrupts = <122>;
|
||
|
+ #thermal-sensor-cells = <0>;
|
||
|
+ };
|
||
|
+
|
||
|
+ thermal-zones {
|
||
|
+ cpu-thermal {
|
||
|
+ polling-delay-passive = <250>;
|
||
|
+ polling-delay = <15000>;
|
||
|
+
|
||
|
+ thermal-sensors = <&sfctemp>;
|
||
|
+
|
||
|
+ cooling-maps {
|
||
|
+ };
|
||
|
+
|
||
|
+ trips {
|
||
|
+ cpu_alert0: cpu_alert0 {
|
||
|
+ /* milliCelsius */
|
||
|
+ temperature = <75000>;
|
||
|
+ hysteresis = <2000>;
|
||
|
+ type = "passive";
|
||
|
+ };
|
||
|
+
|
||
|
+ cpu_crit: cpu_crit {
|
||
|
+ /* milliCelsius */
|
||
|
+ temperature = <90000>;
|
||
|
+ hysteresis = <2000>;
|
||
|
+ type = "critical";
|
||
|
+ };
|
||
|
+ };
|
||
|
+ };
|
||
|
+ };
|
||
|
+
|
||
|
+ xrp@f0000000 {
|
||
|
+ compatible = "cdns,xrp";
|
||
|
+ reg = <0x0 0xf0000000 0x0 0x01ffffff>,
|
||
|
+ <0x10 0x72000000 0x0 0x00001000>,
|
||
|
+ <0x10 0x72001000 0x0 0x00fff000>,
|
||
|
+ <0x0 0x124b0000 0x0 0x00010000>;
|
||
|
+ clocks = <&clkgen JH7100_CLK_VP6_CORE>;
|
||
|
+ interrupts = <27>, <28>;
|
||
|
+ firmware-name = "vp6_elf";
|
||
|
+ dsp-irq = <19 20>;
|
||
|
+ dsp-irq-src = <0x20 0x21>;
|
||
|
+ intc-irq-mode = <1>;
|
||
|
+ intc-irq = <0 1>;
|
||
|
+ #address-cells = <1>;
|
||
|
+ #size-cells = <1>;
|
||
|
+ ranges = <0x40000000 0x0 0x40000000 0x01000000>,
|
||
|
+ <0xb0000000 0x10 0x70000000 0x3000000>;
|
||
|
+ dsp@0 {
|
||
|
+ };
|
||
|
+ };
|
||
|
};
|
||
|
};
|
||
|
--
|
||
|
Armbian
|
||
|
|