85 lines
2.7 KiB
Diff
85 lines
2.7 KiB
Diff
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From 74e4a7637084f25c046c2e1d99cdeffe772f82fd Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Thu, 22 Jul 2021 14:35:27 -0400
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Subject: [PATCH 093/478] arm64: dts: rockchip: add rk356x sata controller
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nodes
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Add the sata controller nodes to the rk356x device tree.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 15 ++++++++++++
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 30 ++++++++++++++++++++++++
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2 files changed, 45 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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index 305d49c587f2..591ebea8527b 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -8,6 +8,21 @@
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/ {
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compatible = "rockchip,rk3568";
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+ sata0: sata@fc000000 {
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+ compatible = "snps,dwc-ahci";
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+ reg = <0 0xfc000000 0 0x1000>;
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+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
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+ <&cru CLK_SATA0_RXOOB>;
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+ clock-names = "sata", "pmalive", "rxoob";
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+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hostc";
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+ phys = <&combphy0_us PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ ports-implemented = <0x1>;
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ status = "disabled";
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+ };
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+
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qos_pcie3x1: qos@fe190080 {
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compatible = "rockchip,rk3568-qos", "syscon";
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reg = <0x0 0xfe190080 0x0 0x20>;
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 72e388212040..2d9f46d36d37 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -192,6 +192,36 @@ scmi_shmem: sram@0 {
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};
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};
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+ sata1: sata@fc400000 {
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+ compatible = "snps,dwc-ahci";
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+ reg = <0 0xfc400000 0 0x1000>;
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+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
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+ <&cru CLK_SATA1_RXOOB>;
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+ clock-names = "sata", "pmalive", "rxoob";
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+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hostc";
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+ phys = <&combphy1_usq PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ ports-implemented = <0x1>;
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ status = "disabled";
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+ };
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+
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+ sata2: sata@fc800000 {
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+ compatible = "snps,dwc-ahci";
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+ reg = <0 0xfc800000 0 0x1000>;
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+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
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+ <&cru CLK_SATA2_RXOOB>;
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+ clock-names = "sata", "pmalive", "rxoob";
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hostc";
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+ phys = <&combphy2_psq PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ ports-implemented = <0x1>;
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ status = "disabled";
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+ };
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+
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gic: interrupt-controller@fd400000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
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--
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2.35.3
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