51 lines
1.8 KiB
Diff
51 lines
1.8 KiB
Diff
|
From e13a455d7e5e5fbd8b8646a64cf05db38ce807a5 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Bin Yang <yangbin@rock-chips.com>
|
||
|
|
Date: Wed, 11 Nov 2020 11:06:37 +0800
|
||
|
|
Subject: [PATCH] usb: dwc3: core: do not use 3.0 clock when operating in 2.0
|
||
|
|
mode
|
||
|
|
|
||
|
|
In the 3.0 device core, if the core is programmed to operate in
|
||
|
|
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
|
||
|
|
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
|
||
|
|
clock. Enabling this feature allows the pipe3 clock to be not-running
|
||
|
|
when forcibly operating in 2.0 device mode.
|
||
|
|
|
||
|
|
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
|
||
|
|
Change-Id: I217a380815c21903c1090bd003c1d8ba2fadbe7c
|
||
|
|
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||
|
|
---
|
||
|
|
drivers/usb/dwc3/core.c | 4 ++++
|
||
|
|
drivers/usb/dwc3/core.h | 1 +
|
||
|
|
2 files changed, 5 insertions(+)
|
||
|
|
|
||
|
|
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
|
||
|
|
index 9dbea2148..94cd112ea 100644
|
||
|
|
--- a/drivers/usb/dwc3/core.c
|
||
|
|
+++ b/drivers/usb/dwc3/core.c
|
||
|
|
@@ -1090,6 +1090,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
|
||
|
|
if (dwc->parkmode_disable_ss_quirk)
|
||
|
|
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
|
||
|
|
|
||
|
|
+ if (dwc->maximum_speed == USB_SPEED_HIGH ||
|
||
|
|
+ dwc->maximum_speed == USB_SPEED_FULL)
|
||
|
|
+ reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
|
||
|
|
+
|
||
|
|
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
|
||
|
|
index 725653711..e6815acdd 100644
|
||
|
|
--- a/drivers/usb/dwc3/core.h
|
||
|
|
+++ b/drivers/usb/dwc3/core.h
|
||
|
|
@@ -258,6 +258,7 @@
|
||
|
|
/* Global User Control 1 Register */
|
||
|
|
#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
|
||
|
|
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
|
||
|
|
+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
|
||
|
|
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
|
||
|
|
#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
|
||
|
|
#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
|
||
|
|
--
|
||
|
|
2.35.3
|
||
|
|
|