88 lines
4.0 KiB
Diff
88 lines
4.0 KiB
Diff
|
From 2a325998acbe215d4fd5aba68df2d8511dcfff36 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Samuel Holland <samuel@sholland.org>
|
||
|
|
Date: Sun, 19 Jul 2020 17:10:15 -0500
|
||
|
|
Subject: [PATCH 257/391] clk: sunxi-ng: a64: Increase PLL_AUDIO base frequency
|
||
|
|
|
||
|
|
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||
|
|
---
|
||
|
|
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 41 +++++++++++++++++++++------
|
||
|
|
1 file changed, 32 insertions(+), 9 deletions(-)
|
||
|
|
|
||
|
|
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
|
||
|
|
index 6fbfe9b3b..761d50597 100644
|
||
|
|
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
|
||
|
|
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
|
||
|
|
@@ -47,15 +47,35 @@ static struct ccu_nkmp pll_cpux_clk = {
|
||
|
|
* With sigma-delta modulation for fractional-N on the audio PLL,
|
||
|
|
* we have to use specific dividers. This means the variable divider
|
||
|
|
* can no longer be used, as the audio codec requests the exact clock
|
||
|
|
- * rates we support through this mechanism. So we now hard code the
|
||
|
|
- * variable divider to 1. This means the clock rates will no longer
|
||
|
|
- * match the clock names.
|
||
|
|
+ * rates we support through this mechanism.
|
||
|
|
+ *
|
||
|
|
+ * For the audio codec to work correctly, pll-audio must be exactly
|
||
|
|
+ * 22579200 Hz or 24576000 Hz, and pll-audio-4x (1x the base) must be
|
||
|
|
+ * between 3x and 8x that frequency. For the SRC to work at 96 kHz,
|
||
|
|
+ * pll-audio-4x must be at least 6x pll-audio.
|
||
|
|
+ *
|
||
|
|
+ * For now, hard code the variable divider to 3.
|
||
|
|
*/
|
||
|
|
#define SUN50I_A64_PLL_AUDIO_REG 0x008
|
||
|
|
+#define SUN50I_A64_PLL_AUDIO_BIAS_REG 0x224
|
||
|
|
|
||
|
|
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
|
||
|
|
- { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
|
||
|
|
- { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
|
||
|
|
+ /* 24000000 * ( 7 + 0x10d84 / 131072 ) / 8 / 1 - 22579200 == -6.9Hz */
|
||
|
|
+ { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
|
||
|
|
+ /* 24000000 * ( 14 + 0x0ac02 / 131072 ) / 14 / 1 - 24576000 == -2.5Hz */
|
||
|
|
+ { .rate = 24576000, .pattern = 0xc000ac08, .m = 14, .n = 14 },
|
||
|
|
+ /* 24000000 * ( 8 + 0x0ef35 / 131072 ) / 3 / 3 - 22579200 == 3.3Hz */
|
||
|
|
+ { .rate = 67737600, .pattern = 0xc000ef35, .m = 3, .n = 8 },
|
||
|
|
+ /* 24000000 * ( 15 + 0x0b852 / 131072 ) / 5 / 3 - 24576000 == 1.0Hz */
|
||
|
|
+ { .rate = 73728000, .pattern = 0xc000b852, .m = 5, .n = 15 },
|
||
|
|
+ /* 24000000 * ( 7 + 0x10d84 / 131072 ) / 2 / 4 - 22579200 == -6.9Hz */
|
||
|
|
+ { .rate = 90316800, .pattern = 0xc0010d84, .m = 2, .n = 7 },
|
||
|
|
+ /* 24000000 * ( 16 + 0x0c49c / 131072 ) / 4 / 4 - 24576000 == 4.0Hz */
|
||
|
|
+ { .rate = 98304000, .pattern = 0xc000c49c, .m = 4, .n = 16 },
|
||
|
|
+ /* 24000000 * ( 5 + 0x14a23 / 131072 ) / 1 / 6 - 22579200 == -6.9Hz */
|
||
|
|
+ { .rate = 135475200, .pattern = 0xc0014a23, .m = 1, .n = 5 },
|
||
|
|
+ /* 24000000 * ( 12 + 0x09375 / 131072 ) / 2 / 6 - 24576000 == 4.0Hz */
|
||
|
|
+ { .rate = 147456000, .pattern = 0xc0009375, .m = 2, .n = 12 },
|
||
|
|
};
|
||
|
|
|
||
|
|
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
||
|
|
@@ -614,10 +634,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
|
||
|
|
&pll_audio_base_clk.common.hw
|
||
|
|
};
|
||
|
|
|
||
|
|
-/* We hardcode the divider to 1 for now */
|
||
|
|
+/* We hardcode the divider to 3 for now */
|
||
|
|
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
|
||
|
|
clk_parent_pll_audio,
|
||
|
|
- 1, 1, CLK_SET_RATE_PARENT);
|
||
|
|
+ 3, 1, CLK_SET_RATE_PARENT);
|
||
|
|
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
|
||
|
|
clk_parent_pll_audio,
|
||
|
|
2, 1, CLK_SET_RATE_PARENT);
|
||
|
|
@@ -962,10 +982,13 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
|
||
|
|
if (IS_ERR(reg))
|
||
|
|
return PTR_ERR(reg);
|
||
|
|
|
||
|
|
- /* Force the PLL-Audio-1x divider to 1 */
|
||
|
|
+ /* Force the pll-audio variable divider to 3 */
|
||
|
|
val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
|
||
|
|
val &= ~GENMASK(19, 16);
|
||
|
|
- writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
|
||
|
|
+ writel(val | (2 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
|
||
|
|
+
|
||
|
|
+ /* Decrease the PLL AUDIO bias current to reduce noise. */
|
||
|
|
+ writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
|
||
|
|
|
||
|
|
ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
|
||
|
|
if (ret) {
|
||
|
|
--
|
||
|
|
2.35.3
|
||
|
|
|