86 lines
3.3 KiB
Diff
86 lines
3.3 KiB
Diff
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From 64d433e2d43ffc5d3e2d96b1f266c3b3864600db Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Wed, 17 Jun 2020 08:42:52 +0800
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Subject: [PATCH 200/391] clk: sunxi-ng: a64: try to keep TCON0 clock in CCU
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As part of the clock tree of LCD and HDMI pipelines on A64 are
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conflicted, usual way to keep LCD clock cannot work on A64.
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However, there's a PLL dedicated to TCON0, PLL-MIPI, which can be
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utilized to get a clock tree that can satisfy both clock rates on LCD
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and HDMI pipelines.
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This patch forbids the PLL-Video0-2X parent of TCON0 clock, and let TCON0
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clock (and then PLL-MIPI by CLK_SET_RATE_PARENT) gets resetted when
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PLL-Video0 changes (because of HDMI PHY clk which is a child of
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PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we can get
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clock tree to satisfy both pipelines.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 27 +++++++++++++++++++++++++--
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1 file changed, 25 insertions(+), 2 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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index 415191856..f03aaf4f3 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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@@ -528,8 +528,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
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0x104, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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-static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
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-static const u8 tcon0_table[] = { 0, 2, };
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+#define SUN50I_A64_TCON0_REG 0x118
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+
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+/*
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+ * When using PLL-Video0 as the parent of tcon0 clock, tcon0 clock will
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+ * conflict with HDMI PHY clock (also a child of PLL-Video0) which is on
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+ * another display pipeline. Force tcon0 to use PLL-MIPI as parent here
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+ * to prevent this. As the parent of PLL-MIPI is still PLL-Video0, a notifier
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+ * is required to restore the rate of TCON0 when the rate of PLL-Video0
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+ * changed.
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+ */
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+static const char * const tcon0_parents[] = { "pll-mipi", /* "pll-video0-2x" */ };
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+static const u8 tcon0_table[] = { 0, /* 2, */ };
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static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
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tcon0_table, 0x118, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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@@ -936,6 +946,10 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
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.bypass_index = 1, /* index of 24 MHz oscillator */
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};
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+static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb = {
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+ .common = &pll_video0_clk.common,
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+};
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+
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static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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{
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void __iomem *reg;
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@@ -953,6 +967,11 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
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+ /* Force the parent of TCON0 to PLL-MIPI */
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+ val = readl(reg + SUN50I_A64_TCON0_REG);
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+ val &= ~GENMASK(26, 24);
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+ writel(val | (0 << 24), reg + SUN50I_A64_TCON0_REG);
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+
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ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
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if (ret)
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return ret;
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@@ -964,6 +983,10 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
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&sun50i_a64_cpu_nb);
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+ /* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed */
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+ sun50i_a64_pll_video0_reset_tcon0_nb.target_clk = tcon0_clk.common.hw.clk;
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+ ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset_tcon0_nb);
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+
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return 0;
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}
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--
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2.35.3
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