267 lines
13 KiB
Diff
267 lines
13 KiB
Diff
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From a2459b3c2ffcb590115ddcad54fa56a3b0263996 Mon Sep 17 00:00:00 2001
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From: Boris Brezillon <boris.brezillon@collabora.com>
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Date: Tue, 12 Jul 2022 09:20:43 +0200
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Subject: [PATCH 404/469] soc: rockchip: power-domain: add rk3588 mem module
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support
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On RK3588 it's also possible to power down the memory used by the
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particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds
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support for this feature.
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Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
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Co-Developed-by: Finley Xiao <finley.xiao@rock-chips.com>
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++-------
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1 file changed, 125 insertions(+), 35 deletions(-)
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diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
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index 84bc022f9e5b..e3de49e671dc 100644
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--- a/drivers/soc/rockchip/pm_domains.c
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+++ b/drivers/soc/rockchip/pm_domains.c
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@@ -43,8 +43,10 @@ struct rockchip_domain_info {
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bool active_wakeup;
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int pwr_w_mask;
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int req_w_mask;
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+ int mem_status_mask;
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int repair_status_mask;
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u32 pwr_offset;
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+ u32 mem_offset;
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u32 req_offset;
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};
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@@ -54,6 +56,9 @@ struct rockchip_pmu_info {
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u32 req_offset;
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u32 idle_offset;
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u32 ack_offset;
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+ u32 mem_pwr_offset;
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+ u32 chain_status_offset;
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+ u32 mem_status_offset;
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u32 repair_status_offset;
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u32 core_pwrcnt_offset;
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@@ -119,13 +124,15 @@ struct rockchip_pmu {
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.active_wakeup = wakeup, \
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}
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-#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \
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+#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \
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{ \
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.name = _name, \
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.pwr_offset = p_offset, \
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.pwr_w_mask = (pwr) << 16, \
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.pwr_mask = (pwr), \
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.status_mask = (status), \
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+ .mem_offset = m_offset, \
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+ .mem_status_mask = (m_status), \
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.repair_status_mask = (r_status), \
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.req_offset = r_offset, \
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.req_w_mask = (req) << 16, \
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@@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void)
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}
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EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
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-#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
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- DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)
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+#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
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+ DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup)
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static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
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{
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@@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
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return !(val & pd->info->status_mask);
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}
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+static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
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+{
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+ struct rockchip_pmu *pmu = pd->pmu;
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+ unsigned int val;
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+
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+ regmap_read(pmu->regmap,
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+ pmu->info->mem_status_offset + pd->info->mem_offset, &val);
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+
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+ /* 1'b0: power on, 1'b1: power off */
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+ return !(val & pd->info->mem_status_mask);
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+}
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+
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+static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
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+{
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+ struct rockchip_pmu *pmu = pd->pmu;
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+ unsigned int val;
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+
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+ regmap_read(pmu->regmap,
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+ pmu->info->chain_status_offset + pd->info->mem_offset, &val);
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+
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+ /* 1'b1: power on, 1'b0: power off */
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+ return val & pd->info->mem_status_mask;
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+}
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+
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+static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
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+{
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+ struct rockchip_pmu *pmu = pd->pmu;
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+ struct generic_pm_domain *genpd = &pd->genpd;
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+ bool is_on;
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+ int ret = 0;
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+
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+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
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+ is_on == true, 0, 10000);
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+ if (ret) {
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+ dev_err(pmu->dev,
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+ "failed to get chain status '%s', target_on=1, val=%d\n",
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+ genpd->name, is_on);
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+ goto error;
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+ }
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+
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+ udelay(20);
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+
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+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
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+ (pd->info->pwr_mask | pd->info->pwr_w_mask));
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+ wmb();
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+
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+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
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+ is_on == false, 0, 10000);
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+ if (ret) {
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+ dev_err(pmu->dev,
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+ "failed to get mem status '%s', target_on=0, val=%d\n",
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+ genpd->name, is_on);
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+ goto error;
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+ }
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+
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+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
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+ pd->info->pwr_w_mask);
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+ wmb();
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+
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+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
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+ is_on == true, 0, 10000);
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+ if (ret) {
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+ dev_err(pmu->dev,
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+ "failed to get mem status '%s', target_on=1, val=%d\n",
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+ genpd->name, is_on);
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+ }
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+
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+error:
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+ return ret;
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+}
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+
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static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
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bool on)
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{
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struct rockchip_pmu *pmu = pd->pmu;
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struct generic_pm_domain *genpd = &pd->genpd;
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u32 pd_pwr_offset = pd->info->pwr_offset;
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- bool is_on;
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+ bool is_on, is_mem_on = false;
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if (pd->info->pwr_mask == 0)
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return;
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- else if (pd->info->pwr_w_mask)
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+
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+ if (on && pd->info->mem_status_mask)
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+ is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
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+
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+ if (pd->info->pwr_w_mask)
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regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
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on ? pd->info->pwr_w_mask :
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(pd->info->pwr_mask | pd->info->pwr_w_mask));
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@@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
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wmb();
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+ if (is_mem_on && rockchip_pmu_domain_mem_reset(pd))
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+ return;
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+
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if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
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is_on == on, 0, 10000)) {
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dev_err(pmu->dev,
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@@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
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pd->genpd.flags = GENPD_FLAG_PM_CLK;
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if (pd_info->active_wakeup)
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pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
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- pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
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+ pm_genpd_init(&pd->genpd, NULL,
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+ !rockchip_pmu_domain_is_on(pd) ||
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+ (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
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pmu->genpd_data.domains[id] = &pd->genpd;
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return 0;
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@@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
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};
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static const struct rockchip_domain_info rk3588_pm_domains[] = {
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- [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false),
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- [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false),
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- [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false),
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- [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false),
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- [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false),
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- [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false),
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- [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false),
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- [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false),
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- [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false),
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- [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false),
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- [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false),
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- [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false),
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- [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false),
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- [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false),
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- [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false),
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- [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false),
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- [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false),
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- [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
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- [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false),
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- [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false),
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- [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false),
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- [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false),
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- [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false),
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- [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true),
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- [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false),
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- [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false),
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- [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false),
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- [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true),
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- [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false),
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+ [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
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+ [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
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+ [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
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+ [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
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+ [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
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+ [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
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+ [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),
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+ [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false),
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+ [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false),
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+ [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false),
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+ [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false),
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+ [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false),
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+ [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false),
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+ [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
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+ [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false),
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+ [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
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+ [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
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+ [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
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||
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+ [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
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||
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+ [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false),
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||
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+ [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false),
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||
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+ [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false),
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||
|
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+ [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false),
|
||
|
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+ [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true),
|
||
|
|
+ [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false),
|
||
|
|
+ [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false),
|
||
|
|
+ [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false),
|
||
|
|
+ [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true),
|
||
|
|
+ [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct rockchip_pmu_info px30_pmu = {
|
||
|
|
@@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk3588_pmu = {
|
||
|
|
.req_offset = 0x10c,
|
||
|
|
.idle_offset = 0x120,
|
||
|
|
.ack_offset = 0x118,
|
||
|
|
+ .mem_pwr_offset = 0x1a0,
|
||
|
|
+ .chain_status_offset = 0x1f0,
|
||
|
|
+ .mem_status_offset = 0x1f8,
|
||
|
|
.repair_status_offset = 0x290,
|
||
|
|
|
||
|
|
.num_domains = ARRAY_SIZE(rk3588_pm_domains),
|
||
|
|
--
|
||
|
|
2.34.1
|
||
|
|
|