85 lines
4.2 KiB
Diff
85 lines
4.2 KiB
Diff
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diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
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index 606ae6cd918b..ee8924ac0093 100644
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--- a/drivers/clk/rockchip/clk-rk3568.c
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+++ b/drivers/clk/rockchip/clk-rk3568.c
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@@ -13,6 +13,8 @@
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#include <dt-bindings/clock/rk3568-cru.h>
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#include "clk.h"
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+#define RK3568_GRF_SOC_CON1 0x504
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+#define RK3568_GRF_SOC_CON2 0x508
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#define RK3568_GRF_SOC_STATUS0 0x580
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enum rk3568_pmu_plls {
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@@ -247,13 +249,13 @@ PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
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PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" };
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PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
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PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" };
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-PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" };
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-PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" };
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-PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" };
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-PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" };
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-PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" };
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-PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" };
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-PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" };
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+PNAME(i2s0_mclkout_tx_p) = { "mclk_i2s0_8ch_tx", "xin_osc0_half" };
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+PNAME(i2s0_mclkout_rx_p) = { "mclk_i2s0_8ch_rx", "xin_osc0_half" };
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+PNAME(i2s1_mclkout_tx_p) = { "mclk_i2s1_8ch_tx", "xin_osc0_half" };
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+PNAME(i2s1_mclkout_rx_p) = { "mclk_i2s1_8ch_rx", "xin_osc0_half" };
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+PNAME(i2s2_mclkout_p) = { "mclk_i2s2_2ch", "xin_osc0_half" };
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+PNAME(i2s3_mclkout_tx_p) = { "mclk_i2s3_2ch_tx", "xin_osc0_half" };
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+PNAME(i2s3_mclkout_rx_p) = { "mclk_i2s3_2ch_rx", "xin_osc0_half" };
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PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
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PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
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PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" };
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@@ -307,6 +309,12 @@ PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
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PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" };
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PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" };
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PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
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+PNAME(i2s1_mclkout_p) = { "i2s1_mclkout_rx", "i2s1_mclkout_tx" };
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+PNAME(i2s3_mclkout_p) = { "i2s3_mclkout_rx", "i2s3_mclkout_tx" };
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+PNAME(i2s1_mclk_rx_ioe_p) = { "i2s1_mclkin_rx", "i2s1_mclkout_rx" };
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+PNAME(i2s1_mclk_tx_ioe_p) = { "i2s1_mclkin_tx", "i2s1_mclkout_tx" };
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+PNAME(i2s2_mclk_ioe_p) = { "i2s2_mclkin", "i2s2_mclkout" };
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+PNAME(i2s3_mclk_ioe_p) = { "i2s3_mclkin", "i2s3_mclkout" };
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static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
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[ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
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@@ -704,6 +712,19 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
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RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
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RK3568_CLKGATE_CON(7), 11, GFLAGS),
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+ MUXGRF(I2S1_MCLKOUT, "i2s1_mclkout", i2s1_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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+ RK3568_GRF_SOC_CON1, 5, 1, MFLAGS),
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+ MUXGRF(I2S3_MCLKOUT, "i2s3_mclkout", i2s3_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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+ RK3568_GRF_SOC_CON2, 15, 1, MFLAGS),
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+ MUXGRF(I2S1_MCLK_RX_IOE, "i2s1_mclk_rx_ioe", i2s1_mclk_rx_ioe_p, 0,
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+ RK3568_GRF_SOC_CON2, 0, 1, MFLAGS),
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+ MUXGRF(I2S1_MCLK_TX_IOE, "i2s1_mclk_tx_ioe", i2s1_mclk_tx_ioe_p, 0,
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+ RK3568_GRF_SOC_CON2, 1, 1, MFLAGS),
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+ MUXGRF(I2S2_MCLK_IOE, "i2s2_mclk_ioe", i2s2_mclk_ioe_p, 0,
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+ RK3568_GRF_SOC_CON2, 2, 1, MFLAGS),
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+ MUXGRF(I2S3_MCLK_IOE, "i2s3_mclk_ioe", i2s3_mclk_ioe_p, 0,
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+ RK3568_GRF_SOC_CON2, 3, 1, MFLAGS),
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+
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GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
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RK3568_CLKGATE_CON(5), 14, GFLAGS),
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COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
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diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h
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index d29890865150..251445cf7632 100644
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--- a/include/dt-bindings/clock/rk3568-cru.h
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+++ b/include/dt-bindings/clock/rk3568-cru.h
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@@ -479,6 +479,12 @@
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#define CPLL_25M 416
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#define CPLL_100M 417
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#define SCLK_DDRCLK 418
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+#define I2S1_MCLKOUT 419
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+#define I2S3_MCLKOUT 420
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+#define I2S1_MCLK_RX_IOE 421
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+#define I2S1_MCLK_TX_IOE 422
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+#define I2S2_MCLK_IOE 423
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+#define I2S3_MCLK_IOE 424
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#define PCLK_CORE_PVTM 450
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