34 lines
903 B
Diff
34 lines
903 B
Diff
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From 2bd59104066b4daf9157c573e2ac747accd1ebd6 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Tue, 20 Dec 2016 11:25:12 +0100
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Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers
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Kernel would lower the divider on first CLK change and cause the
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lock up.
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---
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arch/arm/mach-sunxi/clock_sun6i.c | 7 +++----
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1 file changed, 3 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
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index 6bd75a15f6..86f08ab717 100644
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--- a/arch/arm/mach-sunxi/clock_sun6i.c
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+++ b/arch/arm/mach-sunxi/clock_sun6i.c
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@@ -134,11 +134,10 @@ void clock_set_pll1(unsigned int clk)
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int k = 1;
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int m = 1;
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- if (clk > 1152000000) {
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- k = 2;
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- } else if (clk > 768000000) {
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+ if (clk >= 1368000000) {
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k = 4;
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- m = 2;
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+ } else if (clk >= 768000000) {
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+ k = 2;
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}
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/* Switch to 24MHz clock while changing PLL1 */
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--
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2.34.1
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