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build/patch/u-boot/v2022.04/board_rk322x-box/zzz-usbphy-clk-ehci-support.patch

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添加构建Allwinner H616四核2GB RAM SoC WiFi（蓝莓）
2023-09-19 11:24:52 +08:00
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 4a8be5da..8ae54a04 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -168,6 +168,60 @@
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3228-grf", "syscon";
reg = <0x11000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy0: usb2-phy@760 {
+ compatible = "rockchip,rk3228-usb2phy", "rockchip,rk3288-usb-phy";
+ reg = <0x0760 0x0c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy0";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy0_host: host-port {
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ u2phy1: usb2-phy@800 {
+ compatible = "rockchip,rk3228-usb2phy", "rockchip,rk3288-usb-phy";
+ reg = <0x0800 0x0c>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy1_host: host-port {
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
};
uart0: serial@11010000 {
@@ -435,8 +489,75 @@
"snps,dwc2";
reg = <0x30040000 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- hnp-srp-disable;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ hnp-srp-disable;
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host0_ehci: usb@30080000 {
+ compatible = "generic-ehci";
+ reg = <0x30080000 0x20000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy0>;
+ phys = <&u2phy0_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@300a0000 {
+ compatible = "generic-ohci";
+ reg = <0x300a0000 0x20000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST0>, <&u2phy0>;
+ phys = <&u2phy0_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host1_ehci: usb@300c0000 {
+ compatible = "generic-ehci";
+ reg = <0x300c0000 0x20000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST1>, <&u2phy1>;
+ phys = <&u2phy1_otg>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host1_ohci: usb@300e0000 {
+ compatible = "generic-ohci";
+ reg = <0x300e0000 0x20000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST1>, <&u2phy1>;
+ phys = <&u2phy1_otg>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host2_ehci: usb@30100000 {
+ compatible = "generic-ehci";
+ reg = <0x30100000 0x20000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host2_ohci: usb@30120000 {
+ compatible = "generic-ohci";
+ reg = <0x30120000 0x20000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
status = "disabled";
};
diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
index 0d9dca81..37c04095 100644
--- a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
+++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
@@ -17,5 +17,8 @@ static const struct udevice_id rk322x_syscon_ids[] = {
U_BOOT_DRIVER(syscon_rk322x) = {
.name = "rk322x_syscon",
.id = UCLASS_SYSCON,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
.of_match = rk322x_syscon_ids,
};
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index 054b2fd3..21ee1775 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -469,10 +469,131 @@ static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
return -ENOENT;
}
+static int rk322x_clk_enable(struct clk *clk)
+{
+
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk322x_cru *cru = priv->cru;
+
+ switch (clk->id) {
+ case SCLK_OTGPHY0:
+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(5));
+ break;
+ case SCLK_OTGPHY1:
+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(6));
+ break;
+ case HCLK_OTG:
+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(12));
+ break;
+ case HCLK_HOST0:
+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(6));
+ break;
+ case HCLK_HOST1:
+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(8));
+ break;
+ case HCLK_HOST2:
+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(10));
+ break;
+ case SCLK_MAC:
+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(6));
+ break;
+ case SCLK_MAC_SRC:
+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(7));
+ break;
+ case SCLK_MAC_RX:
+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(5));
+ break;
+ case SCLK_MAC_TX:
+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(6));
+ break;
+ case SCLK_MAC_REF:
+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(3));
+ break;
+ case SCLK_MAC_REFOUT:
+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(4));
+ break;
+ case SCLK_MAC_PHY:
+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(7));
+ break;
+ case ACLK_GMAC:
+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(4));
+ break;
+ case PCLK_GMAC:
+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(5));
+ break;
+ default:
+ log_debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+ }
+
+ return 0;
+
+}
+
+static int rk322x_clk_disable(struct clk *clk)
+{
+
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk322x_cru *cru = priv->cru;
+
+ switch (clk->id) {
+ case SCLK_OTGPHY0:
+ rk_setreg(&cru->cru_clkgate_con[1], BIT(5));
+ break;
+ case SCLK_OTGPHY1:
+ rk_setreg(&cru->cru_clkgate_con[1], BIT(6));
+ break;
+ case HCLK_OTG:
+ rk_setreg(&cru->cru_clkgate_con[11], BIT(12));
+ break;
+ case HCLK_HOST0:
+ rk_setreg(&cru->cru_clkgate_con[11], BIT(6));
+ break;
+ case HCLK_HOST1:
+ rk_setreg(&cru->cru_clkgate_con[11], BIT(8));
+ break;
+ case HCLK_HOST2:
+ rk_setreg(&cru->cru_clkgate_con[11], BIT(10));
+ break;
+ case SCLK_MAC_SRC:
+ rk_setreg(&cru->cru_clkgate_con[1], BIT(7));
+ break;
+ case SCLK_MAC_RX:
+ rk_setreg(&cru->cru_clkgate_con[5], BIT(5));
+ break;
+ case SCLK_MAC_TX:
+ rk_setreg(&cru->cru_clkgate_con[5], BIT(6));
+ break;
+ case SCLK_MAC_REF:
+ rk_setreg(&cru->cru_clkgate_con[5], BIT(3));
+ break;
+ case SCLK_MAC_REFOUT:
+ rk_setreg(&cru->cru_clkgate_con[5], BIT(4));
+ break;
+ case SCLK_MAC_PHY:
+ rk_setreg(&cru->cru_clkgate_con[5], BIT(7));
+ break;
+ case ACLK_GMAC:
+ rk_setreg(&cru->cru_clkgate_con[11], BIT(4));
+ break;
+ case PCLK_GMAC:
+ rk_setreg(&cru->cru_clkgate_con[11], BIT(5));
+ break;
+ default:
+ log_debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+ }
+
+ return 0;
+
+}
+
static struct clk_ops rk322x_clk_ops = {
.get_rate = rk322x_clk_get_rate,
.set_rate = rk322x_clk_set_rate,
.set_parent = rk322x_clk_set_parent,
+ .enable = rk322x_clk_enable,
+ .disable = rk322x_clk_disable
};
static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index c5ea6ca3..04caf292 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -242,6 +242,67 @@ static int rockchip_usb2phy_bind(struct udevice *dev)
return ret;
}
+static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
+ {
+ .reg = 0x760,
+ //.num_ports = 2,
+ //.clkout_ctl = { 0x0768, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
+ .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
+ .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
+ .ls_det_en = { 0x0680, 2, 2, 0, 1 },
+ .ls_det_st = { 0x0690, 2, 2, 0, 1 },
+ .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
+ .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
+ .utmi_ls = { 0x0480, 3, 2, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 },
+ .ls_det_en = { 0x0680, 4, 4, 0, 1 },
+ .ls_det_st = { 0x0690, 4, 4, 0, 1 },
+ .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
+ }
+ },
+ /*
+ .chg_det = {
+ .opmode = { 0x0760, 3, 0, 5, 1 },
+ .cp_det = { 0x0884, 4, 4, 0, 1 },
+ .dcp_det = { 0x0884, 3, 3, 0, 1 },
+ .dp_det = { 0x0884, 5, 5, 0, 1 },
+ .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
+ .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
+ .idp_src_en = { 0x0768, 9, 9, 0, 1 },
+ .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
+ .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
+ .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
+ },
+ */
+ },
+ {
+ .reg = 0x800,
+ //.num_ports = 2,
+ //.clkout_ctl = { 0x0808, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x800, 15, 0, 0, 0x1d1 },
+ .ls_det_en = { 0x0684, 0, 0, 0, 1 },
+ .ls_det_st = { 0x0694, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x804, 15, 0, 0, 0x1d1 },
+ .ls_det_en = { 0x0684, 1, 1, 0, 1 },
+ .ls_det_st = { 0x0694, 1, 1, 0, 1 },
+ .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
{
.reg = 0xe450,
@@ -293,6 +354,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
.compatible = "rockchip,rk3399-usb2phy",
.data = (ulong)&rk3399_usb2phy_cfgs,
},
+ {
+ .compatible = "rockchip,rk3228-usb2phy",
+ .data = (ulong)&rk3228_phy_cfgs,
+ },
{ /* sentinel */ }
};
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index 1217d523..b6a25397 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -51,6 +51,8 @@
#define SCLK_MAC_TX 130
#define SCLK_MAC_PHY 131
#define SCLK_MAC_OUT 132
+#define SCLK_OTGPHY0 142
+#define SCLK_OTGPHY1 143
/* dclk gates */
#define DCLK_VOP 190
@@ -94,6 +96,10 @@
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
+#define HCLK_HOST0 471
+#define HCLK_HOST1 472
+#define HCLK_HOST2 473
+#define HCLK_OTG 474
#define HCLK_PERI 478
#define CLK_NR_CLKS (HCLK_PERI + 1)
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