75 lines
2.3 KiB
Diff
75 lines
2.3 KiB
Diff
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From b23c8fb3421984a72578a4235746653dcd2e82b7 Mon Sep 17 00:00:00 2001
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From: Artem Lapkin <art@khadas.com>
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Date: Tue, 13 Jul 2021 10:46:41 +0800
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Subject: [PATCH v2] PCI: DWC: meson: add 256 bytes MRRS quirk
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256 bytes maximum read request size. They can't handle
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anything larger than this. So force this limit on
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any devices attached under these ports.
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Come-from: https://lkml.org/lkml/2021/6/18/160
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Come-from: https://lkml.org/lkml/2021/6/19/19
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It only affects PCIe in P2P, in non-P2P is will certainly affect
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transfers on the internal SoC/Processor/Chip internal bus/fabric.
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These quirks are currently implemented in the
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controller driver and only applies when the controller has been probed
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and to each endpoint detected on this particular controller.
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Continue having separate quirks for each controller if the core
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isn't the right place to handle MPS/MRRS.
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>> Neil
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Signed-off-by: Artem Lapkin <art@khadas.com>
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---
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drivers/pci/controller/dwc/pci-meson.c | 31 ++++++++++++++++++++++++++
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1 file changed, 31 insertions(+)
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diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
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index 686ded034..1498950de 100644
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--- a/drivers/pci/controller/dwc/pci-meson.c
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+++ b/drivers/pci/controller/dwc/pci-meson.c
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@@ -466,6 +466,37 @@ static int meson_pcie_probe(struct platform_device *pdev)
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return ret;
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}
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+static void meson_mrrs_limit_quirk(struct pci_dev *dev)
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+{
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+ struct pci_bus *bus = dev->bus;
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+ int mrrs, mrrs_limit = 256;
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+ static const struct pci_device_id bridge_devids[] = {
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+ { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3) },
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+ { 0, },
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+ };
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+
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+ /* look for the matching bridge */
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+ while (!pci_is_root_bus(bus)) {
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+ /*
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+ * 256 bytes maximum read request size. They can't handle
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+ * anything larger than this. So force this limit on
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+ * any devices attached under these ports.
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+ */
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+ if (!pci_match_id(bridge_devids, bus->self)) {
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+ bus = bus->parent;
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+ continue;
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+ }
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+
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+ mrrs = pcie_get_readrq(dev);
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+ if (mrrs > mrrs_limit) {
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+ pci_info(dev, "limiting MRRS %d to %d\n", mrrs, mrrs_limit);
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+ pcie_set_readrq(dev, mrrs_limit);
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+ }
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+ break;
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+ }
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+}
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+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, meson_mrrs_limit_quirk);
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+
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static const struct of_device_id meson_pcie_of_match[] = {
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{
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.compatible = "amlogic,axg-pcie",
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--
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2.25.1
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