46 lines
1.7 KiB
Diff
46 lines
1.7 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Vyacheslav Bocharov <adeep@lexina.in>
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Date: Thu, 10 Nov 2022 14:52:47 +0300
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Subject: arm64: dts: docs: Update mmc meson-gx documentation for new config
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option amlogic,mmc-phase
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- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx
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clock with values:
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0: CLK_PHASE_0 - 0 phase
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1: CLK_PHASE_90 - 90 phase
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2: CLK_PHASE_180 - 180 phase
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3: CLK_PHASE_270 - 270 phase
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By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
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Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
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---
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Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 7 +++++++
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1 file changed, 7 insertions(+)
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diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
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index ccc5358db131..98c89c5b3455 100644
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--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
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+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
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@@ -25,6 +25,12 @@ Required properties:
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Optional properties:
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- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
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DRAM memory, like on the G12A dedicated SDIO controller.
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+- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values:
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+ 0: CLK_PHASE_0 - 0 phase
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+ 1: CLK_PHASE_90 - 90 phase
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+ 2: CLK_PHASE_180 - 180 phase
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+ 3: CLK_PHASE_270 - 270 phase
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+ By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
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Example:
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@@ -36,4 +42,5 @@ Example:
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clock-names = "core", "clkin0", "clkin1";
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pinctrl-0 = <&emmc_pins>;
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resets = <&reset RESET_SD_EMMC_A>;
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+ amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
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};
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--
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Armbian
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