233 lines
8.2 KiB
Diff
233 lines
8.2 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Date: Sun, 3 Oct 2021 05:35:48 +0000
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Subject: ASoC: meson: aiu: Fix HDMI codec control selection
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The HDMI controllers on Amlogic Meson SoCs which use the AIU
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audio-controller have two different audio format inputs:
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- I2S which is also the only configuration supported on GXBB, GXL and
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GXM SoCs since there's no SPDIF support in the DesignWare HDMI
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controller driver (at the time of writing this)
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- SPDIF can be used optionally, including pass-through formats
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Switching between these requires us to set different registers:
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AIU_HDMI_CLK_DATA_CTRL[1:0] "HDMI_DATA_CLK_SEL":
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- 0x0 disables the HDMI output clock
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- 0x1 selects the PCM clock
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- 0x2 selects the AIU clock
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- 0x3 is reserved
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AIU_HDMI_CLK_DATA_CTRL[5:4] "HDMI_DATA_SEL":
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- 0x0 outputs constant zero, disables HDMI data
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- 0x1 selects PCM data
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- 0x2 selects AIU I2S data
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- 0x3 is reserved
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AIU_CLK_CTRL_MORE[6] "HDMITX_SEL_AOCLKX2":
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- 0x0 selects cts_i958 as AIU clk to hdmi_tx_audio_master_clk
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- 0x1 selects cts_aoclkx2_int as AIU clk to hdmi_tx_audio_master_clk
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The Meson8/8b/8m2 vendor driver uses the following settings:
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SPDIF output to the HDMI controller:
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- 0x2 (AIU clock) in AIU_HDMI_CLK_DATA_CTRL[1:0]
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- 0x0 (no HDMI data) in AIU_HDMI_CLK_DATA_CTRL[5:4]
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- 0x0 (using cts_i958 as AIU clk) in AIU_CLK_CTRL_MORE[6]
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I2S output to the HDMI controller:
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- 0x2 (AIU clock) in AIU_HDMI_CLK_DATA_CTRL[1:0]
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- 0x2 (I2S data) in AIU_HDMI_CLK_DATA_CTRL[5:4]
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- 0x0 (using cts_aoclkx2_int as AIU clk) in AIU_CLK_CTRL_MORE[6]
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The GXBB/GXL/GXM vendor driver uses the following settings:
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SPDIF output to the HDMI controller:
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- not setting AIU_HDMI_CLK_DATA_CTRL at all
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- 0x0 (using cts_i958 as AIU clk) in AIU_CLK_CTRL_MORE[6]
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I2S output to the HDMI controller:
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- 0x2 (AIU clock) in AIU_HDMI_CLK_DATA_CTRL[1:0]
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- 0x2 (I2S data) in AIU_HDMI_CLK_DATA_CTRL[5:4]
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- 0x0 (using cts_aoclkx2_int as AIU clk) in AIU_CLK_CTRL_MORE[6]
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Set the three registers at the same time following what the vendor
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driver does on Meson8/8b/8m2 SoCs. This makes the SPDIF output to the
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HDMI controller work. The entries and order of the entries in the enum
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is not changed on purpose to not break old configurations.
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Fixes: b82b734c0e9a7 ("ASoC: meson: aiu: add hdmi codec control support")
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Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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---
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sound/soc/meson/aiu-codec-ctrl.c | 108 +++++++---
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sound/soc/meson/aiu-encoder-i2s.c | 6 -
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2 files changed, 80 insertions(+), 34 deletions(-)
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diff --git a/sound/soc/meson/aiu-codec-ctrl.c b/sound/soc/meson/aiu-codec-ctrl.c
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index 84c10956c241..c1aa13f4d65b 100644
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--- a/sound/soc/meson/aiu-codec-ctrl.c
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+++ b/sound/soc/meson/aiu-codec-ctrl.c
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@@ -12,14 +12,60 @@
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#include "aiu.h"
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#include "meson-codec-glue.h"
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-#define CTRL_CLK_SEL GENMASK(1, 0)
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-#define CTRL_DATA_SEL_SHIFT 4
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-#define CTRL_DATA_SEL (0x3 << CTRL_DATA_SEL_SHIFT)
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-
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-static const char * const aiu_codec_ctrl_mux_texts[] = {
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- "DISABLED", "PCM", "I2S",
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+#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL GENMASK(1, 0)
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+#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_DISABLE 0x0
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+#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_PCM 0x1
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+#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_AIU 0x2
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+#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL GENMASK(5, 4)
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+#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_OUTPUT_ZERO 0x0
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+#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_PCM_DATA 0x1
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+#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_I2S_DATA 0x2
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+
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+#define AIU_CLK_CTRL_MORE_AMCLK BIT(6)
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+
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+#define AIU_HDMI_CTRL_MUX_DISABLED 0
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+#define AIU_HDMI_CTRL_MUX_PCM 1
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+#define AIU_HDMI_CTRL_MUX_I2S 2
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+
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+static const char * const aiu_codec_hdmi_ctrl_mux_texts[] = {
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+ [AIU_HDMI_CTRL_MUX_DISABLED] = "DISABLED",
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+ [AIU_HDMI_CTRL_MUX_PCM] = "PCM",
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+ [AIU_HDMI_CTRL_MUX_I2S] = "I2S",
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};
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+static int aiu_codec_ctrl_mux_get_enum(struct snd_kcontrol *kcontrol,
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+ struct snd_ctl_elem_value *ucontrol)
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+{
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+ struct snd_soc_component *component =
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+ snd_soc_dapm_kcontrol_component(kcontrol);
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+ unsigned int ctrl, more, mux = AIU_HDMI_CTRL_MUX_DISABLED;
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+
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+ ctrl = snd_soc_component_read(component, AIU_HDMI_CLK_DATA_CTRL);
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+ if (FIELD_GET(AIU_HDMI_CLK_DATA_CTRL_CLK_SEL, ctrl) !=
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+ AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_AIU) {
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+ goto out;
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+ }
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+
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+ more = snd_soc_component_read(component, AIU_CLK_CTRL_MORE);
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+ if (FIELD_GET(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL, ctrl) ==
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+ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_I2S_DATA &&
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+ !!(more & AIU_CLK_CTRL_MORE_AMCLK)) {
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+ mux = AIU_HDMI_CTRL_MUX_I2S;
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+ goto out;
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+ }
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+
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+ if (FIELD_GET(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL, ctrl) ==
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+ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_OUTPUT_ZERO &&
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+ !(more & AIU_CLK_CTRL_MORE_AMCLK)) {
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+ mux = AIU_HDMI_CTRL_MUX_PCM;
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+ goto out;
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+ }
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+
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+out:
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+ ucontrol->value.enumerated.item[0] = mux;
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+ return 0;
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+}
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+
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static int aiu_codec_ctrl_mux_put_enum(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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@@ -28,45 +74,51 @@ static int aiu_codec_ctrl_mux_put_enum(struct snd_kcontrol *kcontrol,
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struct snd_soc_dapm_context *dapm =
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snd_soc_dapm_kcontrol_dapm(kcontrol);
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struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
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- unsigned int mux, changed;
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+ unsigned int mux, ctrl, more;
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mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
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- changed = snd_soc_component_test_bits(component, e->reg,
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- CTRL_DATA_SEL,
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- FIELD_PREP(CTRL_DATA_SEL, mux));
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- if (!changed)
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- return 0;
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+ if (mux == AIU_HDMI_CTRL_MUX_I2S) {
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+ ctrl = FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL,
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+ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_I2S_DATA);
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+ more = AIU_CLK_CTRL_MORE_AMCLK;
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+ } else {
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+ ctrl = FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL,
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+ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_OUTPUT_ZERO);
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+ more = 0;
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+ }
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+
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+ if (mux == AIU_HDMI_CTRL_MUX_DISABLED) {
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+ ctrl |= FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_CLK_SEL,
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+ AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_DISABLE);
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+ } else {
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+ ctrl |= FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_CLK_SEL,
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+ AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_AIU);
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+ }
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/* Force disconnect of the mux while updating */
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snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
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- /* Reset the source first */
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- snd_soc_component_update_bits(component, e->reg,
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- CTRL_CLK_SEL |
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- CTRL_DATA_SEL,
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- FIELD_PREP(CTRL_CLK_SEL, 0) |
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- FIELD_PREP(CTRL_DATA_SEL, 0));
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+ snd_soc_component_update_bits(component, AIU_HDMI_CLK_DATA_CTRL,
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+ AIU_HDMI_CLK_DATA_CTRL_CLK_SEL |
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+ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL,
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+ ctrl);
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- /* Set the appropriate source */
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- snd_soc_component_update_bits(component, e->reg,
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- CTRL_CLK_SEL |
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- CTRL_DATA_SEL,
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- FIELD_PREP(CTRL_CLK_SEL, mux) |
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- FIELD_PREP(CTRL_DATA_SEL, mux));
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+ snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
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+ AIU_CLK_CTRL_MORE_AMCLK,
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+ more);
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snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
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return 1;
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}
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-static SOC_ENUM_SINGLE_DECL(aiu_hdmi_ctrl_mux_enum, AIU_HDMI_CLK_DATA_CTRL,
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- CTRL_DATA_SEL_SHIFT,
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- aiu_codec_ctrl_mux_texts);
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+static SOC_ENUM_SINGLE_VIRT_DECL(aiu_hdmi_ctrl_mux_enum,
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+ aiu_codec_hdmi_ctrl_mux_texts);
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static const struct snd_kcontrol_new aiu_hdmi_ctrl_mux =
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SOC_DAPM_ENUM_EXT("HDMI Source", aiu_hdmi_ctrl_mux_enum,
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- snd_soc_dapm_get_enum_double,
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+ aiu_codec_ctrl_mux_get_enum,
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aiu_codec_ctrl_mux_put_enum);
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static const struct snd_soc_dapm_widget aiu_hdmi_ctrl_widgets[] = {
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diff --git a/sound/soc/meson/aiu-encoder-i2s.c b/sound/soc/meson/aiu-encoder-i2s.c
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index a0dd914c8ed1..21916034a46d 100644
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--- a/sound/soc/meson/aiu-encoder-i2s.c
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+++ b/sound/soc/meson/aiu-encoder-i2s.c
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@@ -23,7 +23,6 @@
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#define AIU_CLK_CTRL_AOCLK_INVERT BIT(6)
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#define AIU_CLK_CTRL_LRCLK_INVERT BIT(7)
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#define AIU_CLK_CTRL_LRCLK_SKEW GENMASK(9, 8)
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-#define AIU_CLK_CTRL_MORE_HDMI_AMCLK BIT(6)
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#define AIU_CLK_CTRL_MORE_I2S_DIV GENMASK(5, 0)
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#define AIU_CODEC_DAC_LRCLK_CTRL_DIV GENMASK(11, 0)
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@@ -176,11 +175,6 @@ static int aiu_encoder_i2s_set_clocks(struct snd_soc_component *component,
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if (ret)
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return ret;
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- /* Make sure amclk is used for HDMI i2s as well */
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- snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
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- AIU_CLK_CTRL_MORE_HDMI_AMCLK,
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- AIU_CLK_CTRL_MORE_HDMI_AMCLK);
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-
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return 0;
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}
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--
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Armbian
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