245 lines
8.4 KiB
Diff
245 lines
8.4 KiB
Diff
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From 9d274182feb7642db60ac4b713ac6572b5dbd04b Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@arm.linux.org.uk>
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Date: Tue, 29 Nov 2016 10:13:46 +0000
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Subject: mvebu/clearfog pcie updates
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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---
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drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++++++++++-
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drivers/pci/pci-bridge-emul.c | 2 +
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drivers/pci/pcie/aspm.c | 6 ++
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drivers/pci/pcie/portdrv_core.c | 2 +
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4 files changed, 121 insertions(+), 1 deletion(-)
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diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
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index ed13e81cd691..2dc9f457bc76 100644
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--- a/drivers/pci/controller/pci-mvebu.c
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+++ b/drivers/pci/controller/pci-mvebu.c
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@@ -52,7 +52,14 @@
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PCIE_CONF_ADDR_EN)
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#define PCIE_CONF_DATA_OFF 0x18fc
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#define PCIE_MASK_OFF 0x1910
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+#define PCIE_MASK_PM_PME BIT(28)
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#define PCIE_MASK_ENABLE_INTS 0x0f000000
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+#define PCIE_MASK_ERR_COR BIT(18)
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+#define PCIE_MASK_ERR_NONFATAL BIT(17)
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+#define PCIE_MASK_ERR_FATAL BIT(16)
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+#define PCIE_MASK_FERR_DET BIT(10)
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+#define PCIE_MASK_NFERR_DET BIT(9)
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+#define PCIE_MASK_CORERR_DET BIT(8)
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE 0x0001
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#define PCIE_STAT_OFF 0x1a04
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@@ -430,6 +437,54 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
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&port->memwin);
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}
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+static void mvebu_pcie_handle_irq_change(struct mvebu_pcie_port *port)
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+{
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+ u32 reg, old;
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+ u16 devctl, rtctl;
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+
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+ /*
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+ * Errors from downstream devices:
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+ * bridge control register SERR: enables reception of errors
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+ * Errors from this device, or received errors:
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+ * command SERR: enables ERR_NONFATAL and ERR_FATAL messages
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+ * => when enabled, these conditions also flag SERR in status register
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+ * devctl CERE: enables ERR_CORR messages
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+ * devctl NFERE: enables ERR_NONFATAL messages
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+ * devctl FERE: enables ERR_FATAL messages
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+ * Enabled messages then have three paths:
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+ * 1. rtctl: enables system error indication
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+ * 2. root error status register updated
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+ * 3. root error command register: forwarding via MSI
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+ */
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+ old = mvebu_readl(port, PCIE_MASK_OFF);
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+ reg = old & ~(PCIE_MASK_PM_PME | PCIE_MASK_FERR_DET |
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+ PCIE_MASK_NFERR_DET | PCIE_MASK_CORERR_DET |
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+ PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
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+ PCIE_MASK_ERR_FATAL);
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+
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+ devctl = port->bridge.pcie_conf.devctl;
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+ if (devctl & PCI_EXP_DEVCTL_FERE)
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+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_ERR_FATAL;
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+ if (devctl & PCI_EXP_DEVCTL_NFERE)
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+ reg |= PCIE_MASK_NFERR_DET | PCIE_MASK_ERR_NONFATAL;
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+ if (devctl & PCI_EXP_DEVCTL_CERE)
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+ reg |= PCIE_MASK_CORERR_DET | PCIE_MASK_ERR_COR;
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+ if (port->bridge.conf.command & PCI_COMMAND_SERR)
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+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_NFERR_DET |
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+ PCIE_MASK_ERR_FATAL | PCIE_MASK_ERR_NONFATAL;
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+
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+ if (!(port->bridge.conf.bridgectrl & PCI_BRIDGE_CTL_SERR))
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+ reg &= ~(PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
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+ PCIE_MASK_ERR_FATAL);
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+
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+ rtctl = port->bridge.pcie_conf.rootctl;
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+ if (rtctl & PCI_EXP_RTCTL_PMEIE)
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+ reg |= PCIE_MASK_PM_PME;
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+
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+ if (old != reg)
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+ mvebu_writel(port, reg, PCIE_MASK_OFF);
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+}
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+
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static pci_bridge_emul_read_status_t
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mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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int reg, u32 *value)
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@@ -475,6 +530,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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return PCI_BRIDGE_EMUL_HANDLED;
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}
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+static pci_bridge_emul_read_status_t
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+mvebu_pci_bridge_emul_pcie_ext_read(struct pci_bridge_emul *bridge,
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+ int reg, u32 *value)
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+{
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+ struct mvebu_pcie_port *port = bridge->data;
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+
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+ switch (reg) {
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+ case 0x00 ... 0x28:
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+ *value = mvebu_readl(port, 0x100 + (reg & ~3));
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+ break;
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+
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+ case PCI_ERR_ROOT_COMMAND:
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+ case PCI_ERR_ROOT_STATUS:
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+ case PCI_ERR_ROOT_ERR_SRC:
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+ *value = 0;
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+ break;
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+
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+ default:
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+ return PCI_BRIDGE_EMUL_NOT_HANDLED;
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+ }
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+
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+ return PCI_BRIDGE_EMUL_HANDLED;
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+}
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+
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static void
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mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
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int reg, u32 old, u32 new, u32 mask)
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@@ -656,6 +656,8 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
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case PCI_IO_BASE:
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mvebu_pcie_handle_iobase_change(port);
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+ if ((old ^ new) & PCI_COMMAND_SERR)
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+ mvebu_pcie_handle_irq_change(port);
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break;
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case PCI_MEMORY_BASE:
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@@ -672,6 +674,9 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
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break;
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case PCI_INTERRUPT_LINE:
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+ if (((old ^ new) >> 16) & PCI_BRIDGE_CTL_SERR)
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+ mvebu_pcie_handle_irq_change(port);
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+
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if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {
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u32 ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
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if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))
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@@ -532,6 +617,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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switch (reg) {
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case PCI_EXP_DEVCTL:
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+ if ((new ^ old) & (PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_NFERE |
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+ PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_URRE))
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+ mvebu_pcie_handle_irq_change(port);
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+
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mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
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break;
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@@ -557,6 +646,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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case PCI_EXP_RTSTA:
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mvebu_writel(port, new, PCIE_RC_RTSTA);
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break;
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+
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+ case PCI_EXP_RTCTL:
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+ if ((new ^ old) & (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
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+ PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE))
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+ mvebu_pcie_handle_irq_change(port);
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+ break;
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+ }
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+}
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+
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+static void
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+mvebu_pci_bridge_emul_pcie_ext_write(struct pci_bridge_emul *bridge,
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+ int reg, u32 old, u32 new, u32 mask)
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+{
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+ struct mvebu_pcie_port *port = bridge->data;
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+
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+ switch (reg) {
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+ case 0x00 ... 0x28:
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+ mvebu_writel(port, new, 0x100 + (reg & ~3));
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+ break;
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}
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}
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@@ -564,6 +672,8 @@ static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
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.write_base = mvebu_pci_bridge_emul_base_conf_write,
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.read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
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.write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
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+ .read_ext = mvebu_pci_bridge_emul_pcie_ext_read,
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+ .write_ext = mvebu_pci_bridge_emul_pcie_ext_write,
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};
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/*
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diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
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index c5e21f1f210b..b2a32af1e073 100644
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--- a/drivers/pci/pci-bridge-emul.c
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+++ b/drivers/pci/pci-bridge-emul.c
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@@ -153,6 +153,7 @@ struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
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.rw = (GENMASK(7, 0) |
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((PCI_BRIDGE_CTL_PARITY |
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PCI_BRIDGE_CTL_SERR |
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+ /* NOTE: PCIe does not allow ISA, VGA, MASTER_ABORT */
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PCI_BRIDGE_CTL_ISA |
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PCI_BRIDGE_CTL_VGA |
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PCI_BRIDGE_CTL_MASTER_ABORT |
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@@ -269,6 +270,7 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
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bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
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bridge->conf.cache_line_size = 0x10;
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bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
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+ bridge->conf.bridgectrl = cpu_to_le16(PCI_BRIDGE_CTL_SERR);
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bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
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sizeof(pci_regs_behavior),
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GFP_KERNEL);
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diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
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index 52c74682601a..84c1448e1543 100644
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--- a/drivers/pci/pcie/aspm.c
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+++ b/drivers/pci/pcie/aspm.c
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@@ -578,6 +578,12 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
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pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
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pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
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+dev_info(&parent->dev, "up support %x enabled %x\n",
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+ (parent_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10,
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+ !!(parent_lnkctl & PCI_EXP_LNKCTL_ASPMC));
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+dev_info(&parent->dev, "dn support %x enabled %x\n",
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+ (child_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10,
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+ !!(child_lnkctl & PCI_EXP_LNKCTL_ASPMC));
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/*
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* Setup L0s state
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diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
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index bda630889f95..a9be5002a56c 100644
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--- a/drivers/pci/pcie/portdrv_core.c
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+++ b/drivers/pci/pcie/portdrv_core.c
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@@ -326,6 +326,7 @@ int pcie_port_device_register(struct pci_dev *dev)
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/* Get and check PCI Express port services */
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capabilities = get_port_device_capability(dev);
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+ dev_info(&dev->dev, "PCIe capabilities: 0x%x\n", capabilities);
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if (!capabilities)
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return 0;
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@@ -340,6 +340,7 @@ int pcie_port_device_register(struct pci_dev *dev)
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* if that is to be used.
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*/
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status = pcie_init_service_irqs(dev, irqs, capabilities);
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+ dev_info(&dev->dev, "init_service_irqs: %d\n", status);
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if (status) {
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capabilities &= PCIE_PORT_SERVICE_HP;
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if (!capabilities)
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--
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cgit v1.2.3
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