235 lines
10 KiB
Diff
235 lines
10 KiB
Diff
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diff --git a/include/linux/rockchip/iomap.h b/include/linux/rockchip/iomap.h
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new file mode 100644
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index 0000000..e6ffe50
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--- /dev/null
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+++ b/include/linux/rockchip/iomap.h
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@@ -0,0 +1,228 @@
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+#ifndef __MACH_ROCKCHIP_IOMAP_H
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+#define __MACH_ROCKCHIP_IOMAP_H
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+
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+#ifndef __ASSEMBLY__
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+#include <asm/io.h>
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+#endif
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+
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+#ifdef IOMEM
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+#define RK_IO_ADDRESS(x) IOMEM(0xFED00000 + x)
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+#else
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+#define RK_IO_ADDRESS(x) ((void __force __iomem *)(0xFED00000 + x))
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+#endif
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+
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+#define RK_CRU_VIRT RK_IO_ADDRESS(0x00000000)
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+#define RK_GRF_VIRT RK_IO_ADDRESS(0x00010000)
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+#define RK_SGRF_VIRT (RK_GRF_VIRT + 0x1000)
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+#define RK_PMU_VIRT RK_IO_ADDRESS(0x00020000)
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+#define RK_ROM_VIRT RK_IO_ADDRESS(0x00030000)
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+#define RK_EFUSE_VIRT RK_IO_ADDRESS(0x00040000)
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+#define RK_GPIO_VIRT(n) RK_IO_ADDRESS(0x00050000 + (n) * 0x1000)
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+#define RK_DEBUG_UART_VIRT RK_IO_ADDRESS(0x00060000)
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+#define RK_CPU_AXI_BUS_VIRT RK_IO_ADDRESS(0x00070000)
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+#define RK_TIMER_VIRT RK_IO_ADDRESS(0x00080000)
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+#define RK_PWM_VIRT RK_IO_ADDRESS(0x00088000)
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+#define RK_GIC_VIRT RK_IO_ADDRESS(0x00090000)
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+#define RK_BOOTRAM_VIRT RK_IO_ADDRESS(0x000a0000)
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+#define RK_DDR_VIRT RK_IO_ADDRESS(0x000d0000)
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+
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+#define RK3188_CRU_PHYS 0x20000000
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+#define RK3188_CRU_SIZE SZ_4K
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+#define RK3188_GRF_PHYS 0x20008000
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+#define RK3188_GRF_SIZE SZ_4K
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+#define RK3188_PMU_PHYS 0x20004000
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+#define RK3188_PMU_SIZE SZ_4K
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+#define RK3188_ROM_PHYS 0x10120000
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+#define RK3188_ROM_SIZE SZ_16K
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+#define RK3188_EFUSE_PHYS 0x20010000
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+#define RK3188_EFUSE_SIZE SZ_4K
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+#define RK3188_GPIO0_PHYS 0x2000a000
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+#define RK3188_GPIO1_PHYS 0x2003c000
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+#define RK3188_GPIO2_PHYS 0x2003e000
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+#define RK3188_GPIO3_PHYS 0x20080000
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+#define RK3188_GPIO_SIZE SZ_4K
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+#define RK3188_CPU_AXI_BUS_PHYS 0x10128000
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+#define RK3188_CPU_AXI_BUS_SIZE SZ_32K
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+#define RK3188_TIMER0_PHYS 0x20038000
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+#define RK3188_TIMER3_PHYS 0x2000e000
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+#define RK3188_TIMER_SIZE SZ_4K
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+#define RK3188_DDR_PCTL_PHYS 0x20020000
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+#define RK3188_DDR_PCTL_SIZE SZ_4K
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+#define RK3188_DDR_PUBL_PHYS 0x20040000
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+#define RK3188_DDR_PUBL_SIZE SZ_4K
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+#define RK3188_UART0_PHYS 0x10124000
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+#define RK3188_UART1_PHYS 0x10126000
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+#define RK3188_UART2_PHYS 0x20064000
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+#define RK3188_UART3_PHYS 0x20068000
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+#define RK3188_UART_SIZE SZ_4K
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+
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+#define RK3288_CRU_PHYS 0xFF760000
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+#define RK3288_CRU_SIZE SZ_4K
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+#define RK3288_GRF_PHYS 0xFF770000
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+#define RK3288_GRF_SIZE SZ_4K
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+#define RK3288_SGRF_PHYS 0xFF740000
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+#define RK3288_SGRF_SIZE SZ_4K
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+#define RK3288_PMU_PHYS 0xFF730000
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+#define RK3288_PMU_SIZE SZ_4K
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+#define RK3288_ROM_PHYS 0xFFFD0000
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+#define RK3288_ROM_SIZE (SZ_16K + SZ_4K)
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+#define RK3288_EFUSE_PHYS 0xFFB40000
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+#define RK3288_EFUSE_SIZE SZ_4K
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+#define RK3288_GPIO0_PHYS 0xFF750000
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+#define RK3288_GPIO1_PHYS 0xFF780000
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+#define RK3288_GPIO2_PHYS 0xFF790000
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+#define RK3288_GPIO3_PHYS 0xFF7A0000
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+#define RK3288_GPIO4_PHYS 0xFF7B0000
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+#define RK3288_GPIO5_PHYS 0xFF7C0000
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+#define RK3288_GPIO6_PHYS 0xFF7D0000
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+#define RK3288_GPIO7_PHYS 0xFF7E0000
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+#define RK3288_GPIO8_PHYS 0xFF7F0000
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+#define RK3288_GPIO_SIZE SZ_4K
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+#define RK3288_SERVICE_CORE_PHYS 0XFFA80000
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+#define RK3288_SERVICE_CORE_SIZE SZ_4K
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+#define RK3288_SERVICE_DMAC_PHYS 0XFFA90000
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+#define RK3288_SERVICE_DMAC_SIZE SZ_4K
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+#define RK3288_SERVICE_GPU_PHYS 0XFFAA0000
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+#define RK3288_SERVICE_GPU_SIZE SZ_4K
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+#define RK3288_SERVICE_PERI_PHYS 0XFFAB0000
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+#define RK3288_SERVICE_PERI_SIZE SZ_4K
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+#define RK3288_SERVICE_BUS_PHYS 0XFFAC0000
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+#define RK3288_SERVICE_BUS_SIZE SZ_16K
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+#define RK3288_SERVICE_VIO_PHYS 0XFFAD0000
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+#define RK3288_SERVICE_VIO_SIZE SZ_4K
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+#define RK3288_SERVICE_VIDEO_PHYS 0XFFAE0000
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+#define RK3288_SERVICE_VIDEO_SIZE SZ_4K
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+#define RK3288_SERVICE_HEVC_PHYS 0XFFAF0000
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+#define RK3288_SERVICE_HEVC_SIZE SZ_4K
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+#define RK3288_TIMER0_PHYS 0xFF6B0000
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+#define RK3288_TIMER6_PHYS 0xFF810000
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+#define RK3288_TIMER_SIZE SZ_4K
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+#define RK3288_DDR_PCTL0_PHYS 0xFF610000
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+#define RK3288_DDR_PCTL1_PHYS 0xFF630000
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+#define RK3288_DDR_PCTL_SIZE SZ_4K
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+#define RK3288_DDR_PUBL0_PHYS 0xFF620000
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+#define RK3288_DDR_PUBL1_PHYS 0xFF640000
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+#define RK3288_DDR_PUBL_SIZE SZ_4K
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+#define RK3288_UART_BT_PHYS 0xFF180000
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+#define RK3288_UART_BB_PHYS 0xFF190000
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+#define RK3288_UART_DBG_PHYS 0xFF690000
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+#define RK3288_UART_GPS_PHYS 0xFF1B0000
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+#define RK3288_UART_EXP_PHYS 0xFF1C0000
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+#define RK3288_UART_SIZE SZ_4K
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+#define RK3288_GIC_DIST_PHYS 0xFFC01000
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+#define RK3288_GIC_DIST_SIZE SZ_4K
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+#define RK3288_GIC_CPU_PHYS 0xFFC02000
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+#define RK3288_GIC_CPU_SIZE SZ_4K
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+#define RK3288_BOOTRAM_PHYS 0xFF720000
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+#define RK3288_BOOTRAM_SIZE SZ_4K
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+#define RK3288_IMEM_PHYS 0xFF700000
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+#define RK3288_IMEM_SZIE 0x00018000
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+
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+#define RK3036_IMEM_PHYS 0x10080000
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+#define RK3036_IMEM_SIZE SZ_8K
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+#define RK3036_ROM_PHYS 0x10100000
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+#define RK3036_ROM_SIZE SZ_16K
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+#define RK3036_CPU_AXI_BUS_PHYS 0x10128000
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+#define RK3036_CPU_AXI_BUS_SIZE SZ_32K
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+#define RK3036_GIC_DIST_PHYS 0x10139000
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+#define RK3036_GIC_DIST_SIZE SZ_4K
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+#define RK3036_GIC_CPU_PHYS 0x1013a000
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+#define RK3036_GIC_CPU_SIZE SZ_4K
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+#define RK3036_CRU_PHYS 0x20000000
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+#define RK3036_CRU_SIZE SZ_4K
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+#define RK3036_DDR_PCTL_PHYS 0x20004000
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+#define RK3036_DDR_PCTL_SIZE SZ_4K
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+#define RK3036_GRF_PHYS 0x20008000
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+#define RK3036_GRF_SIZE SZ_4K
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+#define RK3036_DDR_PHY_PHYS 0x2000a000
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+#define RK3036_DDR_PHY_SIZE SZ_4K
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+#define RK3036_TIMER_PHYS 0x20044000
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+#define RK3036_TIMER_SIZE SZ_4K
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+#define RK3036_UART0_PHYS 0x20060000
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+#define RK3036_UART1_PHYS 0x20064000
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+#define RK3036_UART2_PHYS 0x20068000
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+#define RK3036_UART_SIZE SZ_4K
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+#define RK3036_GPIO0_PHYS 0x2007c000
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+#define RK3036_GPIO1_PHYS 0x20080000
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+#define RK3036_GPIO2_PHYS 0x20084000
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+#define RK3036_GPIO_SIZE SZ_4K
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+#define RK3036_EFUSE_PHYS 0x20090000
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+#define RK3036_EFUSE_SIZE SZ_4K
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+#define RK3036_PWM_PHYS 0x20050000
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+#define RK3036_PWM_SIZE SZ_16K
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+
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+#define RK312X_IMEM_PHYS RK3036_IMEM_PHYS
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+#define RK312X_IMEM_SIZE RK3036_IMEM_SIZE
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+#define RK312X_ROM_PHYS RK3036_ROM_PHYS
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+#define RK312X_ROM_SIZE RK3036_ROM_SIZE
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+#define RK312X_CPU_AXI_BUS_PHYS RK3036_CPU_AXI_BUS_PHYS
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+#define RK312X_CPU_AXI_BUS_SIZE RK3036_CPU_AXI_BUS_SIZE
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+#define RK312X_GIC_DIST_PHYS RK3036_GIC_DIST_PHYS
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+#define RK312X_GIC_DIST_SIZE RK3036_GIC_DIST_SIZE
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+#define RK312X_GIC_CPU_PHYS RK3036_GIC_CPU_PHYS
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+#define RK312X_GIC_CPU_SIZE RK3036_GIC_CPU_SIZE
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+#define RK312X_CRU_PHYS RK3036_CRU_PHYS
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+#define RK312X_CRU_SIZE RK3036_CRU_SIZE
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+#define RK312X_DDR_PCTL_PHYS RK3036_DDR_PCTL_PHYS
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+#define RK312X_DDR_PCTL_SIZE RK3036_DDR_PCTL_SIZE
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+#define RK312X_GRF_PHYS RK3036_GRF_PHYS
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+#define RK312X_GRF_SIZE RK3036_GRF_SIZE
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+#define RK312X_DDR_PHY_PHYS RK3036_DDR_PHY_PHYS
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+#define RK312X_DDR_PHY_SIZE RK3036_DDR_PHY_SIZE
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+#define RK312X_TIMER_PHYS RK3036_TIMER_PHYS
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+#define RK312X_TIMER_SIZE RK3036_TIMER_SIZE
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+#define RK312X_UART0_PHYS RK3036_UART0_PHYS
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+#define RK312X_UART1_PHYS RK3036_UART1_PHYS
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+#define RK312X_UART2_PHYS RK3036_UART2_PHYS
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+#define RK312X_UART_SIZE RK3036_UART_SIZE
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+#define RK312X_GPIO0_PHYS RK3036_GPIO0_PHYS
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+#define RK312X_GPIO1_PHYS RK3036_GPIO1_PHYS
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+#define RK312X_GPIO2_PHYS RK3036_GPIO2_PHYS
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+#define RK312X_GPIO3_PHYS 0x20088000
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+#define RK312X_GPIO_SIZE RK3036_GPIO_SIZE
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+#define RK312X_EFUSE_PHYS RK3036_EFUSE_PHYS
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+#define RK312X_EFUSE_SIZE RK3036_EFUSE_SIZE
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+#define RK312X_PMU_PHYS 0x100a0000
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+#define RK312X_PMU_SIZE SZ_64K
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+#define RK312X_PWM_PHYS 0x20050000
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+#define RK312X_PWM_SIZE SZ_16K
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+
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+#define RK3228_IMEM_PHYS RK3036_IMEM_PHYS
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+#define RK3228_IMEM_SIZE SZ_32K
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+#define RK3228_ROM_PHYS RK3036_ROM_PHYS
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+#define RK3228_ROM_SIZE RK3036_ROM_SIZE
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+#define RK3228_CPU_AXI_BUS_PHYS 0x31000000
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+#define RK3228_CPU_AXI_BUS_SIZE SZ_32K
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+#define RK3228_GIC_DIST_PHYS 0x32011000
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+#define RK3228_GIC_DIST_SIZE SZ_4K
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+#define RK3228_GIC_CPU_PHYS 0x32012000
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+#define RK3228_GIC_CPU_SIZE SZ_4K
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+#define RK3228_CRU_PHYS 0x110e0000
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+#define RK3228_CRU_SIZE SZ_4K
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+#define RK3228_DDR_PCTL_PHYS 0x11200000
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+#define RK3228_DDR_PCTL_SIZE SZ_4K
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+#define RK3228_GRF_PHYS 0x11000000
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+#define RK3228_GRF_SIZE SZ_4K
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+#define RK3228_SGRF_PHYS 0x10140000
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+#define RK3228_SGRF_SIZE SZ_4K
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+#define RK3228_DDR_PHY_PHYS 0x12000000
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+#define RK3228_DDR_PHY_SIZE SZ_4K
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+#define RK3228_TIMER_PHYS 0x110c0000
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+#define RK3228_TIMER_SIZE SZ_4K
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+#define RK3228_STIMER_PHYS 0x110d0000
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+#define RK3228_STIMER_SIZE SZ_4K
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+#define RK3228_UART0_PHYS 0x11010000
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+#define RK3228_UART1_PHYS 0x11020000
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+#define RK3228_UART2_PHYS 0x11030000
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+#define RK3228_UART_SIZE SZ_4K
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+#define RK3228_GPIO0_PHYS 0x11110000
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+#define RK3228_GPIO1_PHYS 0x11120000
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+#define RK3228_GPIO2_PHYS 0x11130000
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+#define RK3228_GPIO3_PHYS 0x11140000
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+#define RK3228_GPIO_SIZE SZ_4K
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+#define RK3228_EFUSE_PHYS 0x11040000
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+#define RK3228_EFUSE_SIZE SZ_4K
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+#define RK3228_PWM_PHYS 0x110b0000
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+#define RK3228_PWM_SIZE SZ_16K
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+
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+#endif
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