76 lines
2.8 KiB
Diff
76 lines
2.8 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Wed, 19 Aug 2020 21:12:54 +0200
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Subject: [PATCH] arm64: dts: rockchip: add rkvdec node for RK3328
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Signed-off-by: Alex Bee <knaerzche@gmail.com>
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---
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.../bindings/media/rockchip,vdec.yaml | 3 +++
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arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 ++++++++++++++++++-
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2 files changed, 27 insertions(+), 1 deletion(-)
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diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
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index 3f4772c8d095..21a78372dae6 100644
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--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
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+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
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@@ -20,6 +20,9 @@ properties:
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- items:
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- const: rockchip,rk3228-vdec
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- const: rockchip,rk3399-vdec
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+ - items:
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+ - const: rockchip,rk3328-vdec
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+ - const: rockchip,rk3399-vdec
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reg:
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maxItems: 1
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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index 9c10b6e3b9bc..23021373e15b 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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@@ -306,6 +306,10 @@ power-domain@RK3328_PD_HEVC {
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};
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power-domain@RK3328_PD_VIDEO {
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reg = <RK3328_PD_VIDEO>;
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+ clocks = <&cru ACLK_RKVDEC>,
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+ <&cru HCLK_RKVDEC>,
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+ <&cru SCLK_VDEC_CABAC>,
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+ <&cru SCLK_VDEC_CORE>;
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#power-domain-cells = <0>;
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};
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power-domain@RK3328_PD_VPU {
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@@ -660,6 +664,25 @@ vpu_mmu: iommu@ff350800 {
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power-domains = <&power RK3328_PD_VPU>;
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};
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+ rkvdec: video-codec@ff360000 {
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+ compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
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+ reg = <0x0 0xff360000 0x0 0x480>;
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+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
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+ <&cru SCLK_VDEC_CORE>;
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+ assigned-clock-rates = <400000000>, <400000000>, <300000000>;
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+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
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+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
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+ clock-names = "axi", "ahb", "cabac", "core";
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+ iommus = <&rkvdec_mmu>;
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+ power-domains = <&power RK3328_PD_VIDEO>;
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+ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>,
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+ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>,
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+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>;
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+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
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+ "niu_a", "niu_h";
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+ };
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+
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rkvdec_mmu: iommu@ff360480 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
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@@ -667,7 +690,7 @@ rkvdec_mmu: iommu@ff360480 {
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clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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- status = "disabled";
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+ power-domains = <&power RK3328_PD_VIDEO>;
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};
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vop: vop@ff370000 {
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