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build/patch/kernel/archive/rockchip64-5.18/add-board-tvbox-rk3318.patch

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添加构建Allwinner H616四核2GB RAM SoC WiFi（蓝莓）
2023-09-19 11:24:52 +08:00
diff --git a/arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi
new file mode 100644
index 000000000..31a28d829
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/memory/rk3328-dram.h>
+
+/ {
+ ddr_timing: ddr_timing {
+ compatible = "rockchip,ddr-timing";
+ ddr3_speed_bin = <DDR3_DEFAULT>;
+ ddr4_speed_bin = <DDR4_DEFAULT>;
+ pd_idle = <0>;
+ sr_idle = <0>;
+ sr_mc_gate_idle = <0>;
+ srpd_lite_idle = <0>;
+ standby_idle = <0>;
+
+ auto_pd_dis_freq = <1066>;
+ auto_sr_dis_freq = <800>;
+ ddr3_dll_dis_freq = <300>;
+ ddr4_dll_dis_freq = <625>;
+ phy_dll_dis_freq = <400>;
+
+ ddr3_odt_dis_freq = <100>;
+ phy_ddr3_odt_dis_freq = <100>;
+ ddr3_drv = <DDR3_DS_40ohm>;
+ ddr3_odt = <DDR3_ODT_120ohm>;
+ phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_23ohm>;
+ phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_34ohm>;
+ phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
+ phy_ddr3_odt = <PHY_DDR3_RON_RTT_150ohm>;
+
+ lpddr3_odt_dis_freq = <666>;
+ phy_lpddr3_odt_dis_freq = <666>;
+ lpddr3_drv = <LP3_DS_40ohm>;
+ lpddr3_odt = <LP3_ODT_240ohm>;
+ phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
+ phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
+
+ lpddr4_odt_dis_freq = <800>;
+ phy_lpddr4_odt_dis_freq = <800>;
+ lpddr4_drv = <LP4_PDDS_60ohm>;
+ lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
+ lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
+ phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
+ phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+ phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
+ phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
+
+ ddr4_odt_dis_freq = <666>;
+ phy_ddr4_odt_dis_freq = <666>;
+ ddr4_drv = <DDR4_DS_34ohm>;
+ ddr4_odt = <DDR4_RTT_NOM_240ohm>;
+ phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
+ phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
+ phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
+
+ /* CA de-skew, one step is 47.8ps, range 0-15 */
+ ddr3a1_ddr4a9_de-skew = <2>;
+ ddr3a0_ddr4a10_de-skew = <3>;
+ ddr3a3_ddr4a6_de-skew = <3>;
+ ddr3a2_ddr4a4_de-skew = <2>;
+ ddr3a5_ddr4a8_de-skew = <3>;
+ ddr3a4_ddr4a5_de-skew = <2>;
+ ddr3a7_ddr4a11_de-skew = <3>;
+ ddr3a6_ddr4a7_de-skew = <2>;
+ ddr3a9_ddr4a0_de-skew = <2>;
+ ddr3a8_ddr4a13_de-skew = <1>;
+ ddr3a11_ddr4a3_de-skew = <2>;
+ ddr3a10_ddr4cs0_de-skew = <2>;
+ ddr3a13_ddr4a2_de-skew = <1>;
+ ddr3a12_ddr4ba1_de-skew = <2>;
+ ddr3a15_ddr4odt0_de-skew = <3>;
+ ddr3a14_ddr4a1_de-skew = <2>;
+ ddr3ba1_ddr4a15_de-skew = <2>;
+ ddr3ba0_ddr4bg0_de-skew = <4>;
+ ddr3ras_ddr4cke_de-skew = <4>;
+ ddr3ba2_ddr4ba0_de-skew = <3>;
+ ddr3we_ddr4bg1_de-skew = <2>;
+ ddr3cas_ddr4a12_de-skew = <2>;
+ ddr3ckn_ddr4ckn_de-skew = <11>;
+ ddr3ckp_ddr4ckp_de-skew = <11>;
+ ddr3cke_ddr4a16_de-skew = <2>;
+ ddr3odt0_ddr4a14_de-skew = <4>;
+ ddr3cs0_ddr4act_de-skew = <4>;
+ ddr3reset_ddr4reset_de-skew = <7>;
+ ddr3cs1_ddr4cs1_de-skew = <7>;
+ ddr3odt1_ddr4odt1_de-skew = <7>;
+
+ /* DATA de-skew
+ * RX one step is 25.1ps, range 0-15
+ * TX one step is 47.8ps, range 0-15
+ */
+ cs0_dm0_rx_de-skew = <12>;
+ cs0_dm0_tx_de-skew = <10>;
+ cs0_dq0_rx_de-skew = <12>;
+ cs0_dq0_tx_de-skew = <10>;
+ cs0_dq1_rx_de-skew = <12>;
+ cs0_dq1_tx_de-skew = <10>;
+ cs0_dq2_rx_de-skew = <12>;
+ cs0_dq2_tx_de-skew = <10>;
+ cs0_dq3_rx_de-skew = <12>;
+ cs0_dq3_tx_de-skew = <10>;
+ cs0_dq4_rx_de-skew = <12>;
+ cs0_dq4_tx_de-skew = <10>;
+ cs0_dq5_rx_de-skew = <12>;
+ cs0_dq5_tx_de-skew = <10>;
+ cs0_dq6_rx_de-skew = <12>;
+ cs0_dq6_tx_de-skew = <10>;
+ cs0_dq7_rx_de-skew = <12>;
+ cs0_dq7_tx_de-skew = <10>;
+ cs0_dqs0_rx_de-skew = <10>;
+ cs0_dqs0p_tx_de-skew = <12>;
+ cs0_dqs0n_tx_de-skew = <12>;
+
+ cs0_dm1_rx_de-skew = <10>;
+ cs0_dm1_tx_de-skew = <8>;
+ cs0_dq8_rx_de-skew = <10>;
+ cs0_dq8_tx_de-skew = <8>;
+ cs0_dq9_rx_de-skew = <10>;
+ cs0_dq9_tx_de-skew = <8>;
+ cs0_dq10_rx_de-skew = <10>;
+ cs0_dq10_tx_de-skew = <8>;
+ cs0_dq11_rx_de-skew = <10>;
+ cs0_dq11_tx_de-skew = <8>;
+ cs0_dq12_rx_de-skew = <10>;
+ cs0_dq12_tx_de-skew = <8>;
+ cs0_dq13_rx_de-skew = <10>;
+ cs0_dq13_tx_de-skew = <8>;
+ cs0_dq14_rx_de-skew = <10>;
+ cs0_dq14_tx_de-skew = <8>;
+ cs0_dq15_rx_de-skew = <10>;
+ cs0_dq15_tx_de-skew = <8>;
+ cs0_dqs1_rx_de-skew = <9>;
+ cs0_dqs1p_tx_de-skew = <10>;
+ cs0_dqs1n_tx_de-skew = <10>;
+
+ cs0_dm2_rx_de-skew = <10>;
+ cs0_dm2_tx_de-skew = <9>;
+ cs0_dq16_rx_de-skew = <10>;
+ cs0_dq16_tx_de-skew = <9>;
+ cs0_dq17_rx_de-skew = <10>;
+ cs0_dq17_tx_de-skew = <9>;
+ cs0_dq18_rx_de-skew = <10>;
+ cs0_dq18_tx_de-skew = <9>;
+ cs0_dq19_rx_de-skew = <10>;
+ cs0_dq19_tx_de-skew = <9>;
+ cs0_dq20_rx_de-skew = <10>;
+ cs0_dq20_tx_de-skew = <9>;
+ cs0_dq21_rx_de-skew = <10>;
+ cs0_dq21_tx_de-skew = <9>;
+ cs0_dq22_rx_de-skew = <10>;
+ cs0_dq22_tx_de-skew = <9>;
+ cs0_dq23_rx_de-skew = <10>;
+ cs0_dq23_tx_de-skew = <9>;
+ cs0_dqs2_rx_de-skew = <9>;
+ cs0_dqs2p_tx_de-skew = <11>;
+ cs0_dqs2n_tx_de-skew = <11>;
+
+ cs0_dm3_rx_de-skew = <7>;
+ cs0_dm3_tx_de-skew = <7>;
+ cs0_dq24_rx_de-skew = <7>;
+ cs0_dq24_tx_de-skew = <7>;
+ cs0_dq25_rx_de-skew = <7>;
+ cs0_dq25_tx_de-skew = <7>;
+ cs0_dq26_rx_de-skew = <7>;
+ cs0_dq26_tx_de-skew = <7>;
+ cs0_dq27_rx_de-skew = <7>;
+ cs0_dq27_tx_de-skew = <7>;
+ cs0_dq28_rx_de-skew = <7>;
+ cs0_dq28_tx_de-skew = <7>;
+ cs0_dq29_rx_de-skew = <7>;
+ cs0_dq29_tx_de-skew = <7>;
+ cs0_dq30_rx_de-skew = <7>;
+ cs0_dq30_tx_de-skew = <7>;
+ cs0_dq31_rx_de-skew = <7>;
+ cs0_dq31_tx_de-skew = <7>;
+ cs0_dqs3_rx_de-skew = <7>;
+ cs0_dqs3p_tx_de-skew = <10>;
+ cs0_dqs3n_tx_de-skew = <10>;
+
+ cs1_dm0_rx_de-skew = <7>;
+ cs1_dm0_tx_de-skew = <8>;
+ cs1_dq0_rx_de-skew = <7>;
+ cs1_dq0_tx_de-skew = <8>;
+ cs1_dq1_rx_de-skew = <7>;
+ cs1_dq1_tx_de-skew = <8>;
+ cs1_dq2_rx_de-skew = <7>;
+ cs1_dq2_tx_de-skew = <8>;
+ cs1_dq3_rx_de-skew = <7>;
+ cs1_dq3_tx_de-skew = <8>;
+ cs1_dq4_rx_de-skew = <7>;
+ cs1_dq4_tx_de-skew = <8>;
+ cs1_dq5_rx_de-skew = <7>;
+ cs1_dq5_tx_de-skew = <8>;
+ cs1_dq6_rx_de-skew = <7>;
+ cs1_dq6_tx_de-skew = <8>;
+ cs1_dq7_rx_de-skew = <7>;
+ cs1_dq7_tx_de-skew = <8>;
+ cs1_dqs0_rx_de-skew = <6>;
+ cs1_dqs0p_tx_de-skew = <9>;
+ cs1_dqs0n_tx_de-skew = <9>;
+
+ cs1_dm1_rx_de-skew = <7>;
+ cs1_dm1_tx_de-skew = <7>;
+ cs1_dq8_rx_de-skew = <7>;
+ cs1_dq8_tx_de-skew = <8>;
+ cs1_dq9_rx_de-skew = <7>;
+ cs1_dq9_tx_de-skew = <7>;
+ cs1_dq10_rx_de-skew = <7>;
+ cs1_dq10_tx_de-skew = <8>;
+ cs1_dq11_rx_de-skew = <7>;
+ cs1_dq11_tx_de-skew = <7>;
+ cs1_dq12_rx_de-skew = <7>;
+ cs1_dq12_tx_de-skew = <8>;
+ cs1_dq13_rx_de-skew = <7>;
+ cs1_dq13_tx_de-skew = <7>;
+ cs1_dq14_rx_de-skew = <7>;
+ cs1_dq14_tx_de-skew = <8>;
+ cs1_dq15_rx_de-skew = <7>;
+ cs1_dq15_tx_de-skew = <7>;
+ cs1_dqs1_rx_de-skew = <7>;
+ cs1_dqs1p_tx_de-skew = <9>;
+ cs1_dqs1n_tx_de-skew = <9>;
+
+ cs1_dm2_rx_de-skew = <7>;
+ cs1_dm2_tx_de-skew = <8>;
+ cs1_dq16_rx_de-skew = <7>;
+ cs1_dq16_tx_de-skew = <8>;
+ cs1_dq17_rx_de-skew = <7>;
+ cs1_dq17_tx_de-skew = <8>;
+ cs1_dq18_rx_de-skew = <7>;
+ cs1_dq18_tx_de-skew = <8>;
+ cs1_dq19_rx_de-skew = <7>;
+ cs1_dq19_tx_de-skew = <8>;
+ cs1_dq20_rx_de-skew = <7>;
+ cs1_dq20_tx_de-skew = <8>;
+ cs1_dq21_rx_de-skew = <7>;
+ cs1_dq21_tx_de-skew = <8>;
+ cs1_dq22_rx_de-skew = <7>;
+ cs1_dq22_tx_de-skew = <8>;
+ cs1_dq23_rx_de-skew = <7>;
+ cs1_dq23_tx_de-skew = <8>;
+ cs1_dqs2_rx_de-skew = <6>;
+ cs1_dqs2p_tx_de-skew = <9>;
+ cs1_dqs2n_tx_de-skew = <9>;
+
+ cs1_dm3_rx_de-skew = <7>;
+ cs1_dm3_tx_de-skew = <7>;
+ cs1_dq24_rx_de-skew = <7>;
+ cs1_dq24_tx_de-skew = <8>;
+ cs1_dq25_rx_de-skew = <7>;
+ cs1_dq25_tx_de-skew = <7>;
+ cs1_dq26_rx_de-skew = <7>;
+ cs1_dq26_tx_de-skew = <7>;
+ cs1_dq27_rx_de-skew = <7>;
+ cs1_dq27_tx_de-skew = <7>;
+ cs1_dq28_rx_de-skew = <7>;
+ cs1_dq28_tx_de-skew = <7>;
+ cs1_dq29_rx_de-skew = <7>;
+ cs1_dq29_tx_de-skew = <7>;
+ cs1_dq30_rx_de-skew = <7>;
+ cs1_dq30_tx_de-skew = <7>;
+ cs1_dq31_rx_de-skew = <7>;
+ cs1_dq31_tx_de-skew = <7>;
+ cs1_dqs3_rx_de-skew = <7>;
+ cs1_dqs3p_tx_de-skew = <9>;
+ cs1_dqs3n_tx_de-skew = <9>;
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3318-box.dts b/arch/arm64/boot/dts/rockchip/rk3318-box.dts
new file mode 100644
index 00000000000..28acf1fe127
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3318-box.dts
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Paolo Sabatino
+ */
+
+/dts-v1/;
+#include "dt-bindings/pwm/pwm.h"
+#include "dt-bindings/input/input.h"
+#include "rk3328.dtsi"
+#include "rk3318-dram-default-timing.dtsi"
+
+/ {
+ model = "Rockchip RK3318 BOX";
+ compatible = "rockchip,rk3318-box", "rockchip,rk3328-box", "rockchip,rk3328";
+
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &sdio;
+ mmc2 = &emmc;
+ mmc3 = &sdmmc_ext;
+ mmc4 = &sdio_ext;
+ };
+
+ /delete-node/ opp-table-0;
+ /delete-node/ gpu-opp-table;
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1200000>;
+ clock-latency-ns = <40000>;
+ status = "disabled";
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1275000>;
+ clock-latency-ns = <40000>;
+ status = "disabled";
+ };
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1000000 950000 1200000>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1050000 950000 1200000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000 950000 1200000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1100000 950000 1200000>;
+ };
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc_keys: adc-keys {
+
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <17000>;
+ };
+
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+
+ gmac_clkin: gmac-clkin {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0x00>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ vcc_18: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcc_io: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_pin>;
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ /*
+ * USB3 vbus
+ */
+ vcc_host_vbus: vcc-host-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_host_drv>;
+ regulator-name = "vcc_host_vbus";
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ /*
+ * USB2 OTG vbus
+ */
+ vcc_otg_vbus: vcc-otg-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb20_host_drv>;
+ regulator-name = "vcc_otg_vbus";
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vdd_arm: vdd-arm {
+ compatible = "pwm-regulator";
+ pwms = <&pwm0 0 5000 PWM_POLARITY_INVERTED>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <12500>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_logic: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ gpio_led: gpio-leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&working_led>;
+
+ working {
+ gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "timer";
+ default-state = "on";
+ };
+
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ pinctrl-names = "default";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+
+ /*
+ wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "rts_gpio";
+ pinctrl-0 = <&uart0_rts>;
+ pinctrl-1 = <&uart0_rts_gpio>;
+ BT,power_gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "ap6330";
+ sdio_vref = <1800>;
+ WIFI,host_wake_irq = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+ };
+ */
+
+ fd628_dev {
+ compatible = "fd628_dev";
+ fd628_gpio_clk = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ fd628_gpio_dat = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ analog-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "ANALOG";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
+ hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "HDMI";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
+ /*
+ * This node is a duplicate of sdmmc_ext: most common board do not use sdmmc_ext
+ * controller, so it is left unused. Some other boards use it as sdio controller
+ * for wifi and some others use it as sdcard controller.
+ * To handle the most critical situation, the controller will be configured as
+ * sdcard controller by default. An overlay can be set to disable the sdmmc_ext
+ * node and enable this sdio_ext in case wifi chips are attached to this.
+ */
+ sdio_ext: mmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMCEXT>;
+ reset-names = "reset";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-0 = <&sdmmc0ext_cmd &sdmmc0ext_clk &sdmmc0ext_bus4>;
+ pinctrl-names = "default";
+ supports-sdio;
+ status = "disabled";
+ };
+
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ center-supply = <&vdd_logic>;
+ ddr_timing = <&ddr_timing>;
+ status = "disabled";
+};
+
+&codec {
+ status = "okay";
+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&emmc {
+
+ supports-emmc;
+ no-sdio;
+ no-sd;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ bus-width = <8>;
+ num-slots = <0x01>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_18>;
+
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <500>;
+ cd-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ no-sdio;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ supports-sd;
+ status = "okay";
+ vmmc-supply = <&vcc_sd>;
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ supports-sdio;
+ status = "okay";
+};
+
+/*
+ * sdmmc_ext is configured as sdcard controller and enabled by default.
+ * In this way boards which have the sdcard attached to sdmmc_ext will work
+ * by default. In case the controller is not attached to anything, the
+ * kernel will just autodetect and give up.
+ */
+&sdmmc_ext {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <500>;
+ cd-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ no-sdio;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_dectn &sdmmc0ext_bus4>;
+ supports-sd;
+ status = "okay";
+ vmmc-supply = <&vcc_sd>;
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+
+ phy-mode = "rmii";
+
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-rate = <50000000>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+
+ status = "okay";
+
+};
+
+&gpu {
+ status = "okay";
+ mali-supply = <&vdd_logic>;
+};
+
+/*
+&h265e {
+ status = "okay";
+};
+*/
+
+&h265e_mmu {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&spdif {
+ pinctrl-0 = <&spdifm0_tx>;
+ status = "okay";
+};
+
+&spdif_out {
+ status = "okay";
+};
+
+&spdif_sound {
+ status = "okay";
+};
+
+&hdmiphy {
+ status = "okay";
+};
+
+&i2s0 {
+ status = "okay";
+};
+
+&i2s1 {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc_18>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_32k_out>;
+
+ clk_32k {
+ clk_32k_out: clk-32k-out {
+ rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ working_led: working-led {
+ rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none_2ma>;
+ };
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_4ma>;/*,
+ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none_4ma>;*/
+ };
+ };
+
+ usb2 {
+ usb20_host_drv: usb20-host-drv {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb3 {
+ usb30_host_drv: usb30-host-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-wlan {
+
+ /*
+ * SDIO host wake interrupt on YX_RK3328 board (sdio is attached to
+ * regular mmc controller mmc@ff510000)
+ */
+ sdio_host_wake: sdio-host-wake {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /*
+ * SDIO host wake interrupt on X88_PRO_B board (sdio is attached to
+ * alternative mmc controller mmc@ff5f0000)
+ */
+ sdio_host_wake_ext: sdio-host-wake-ext {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ };
+
+};
+
+/*
+&rkvdec {
+ status = "okay";
+ vcodec-supply = <&vdd_logic>;
+};
+*/
+
+&rkvdec_mmu {
+ status = "okay";
+};
+
+&threshold {
+ temperature = <80000>; /* millicelsius */
+};
+
+&target {
+ temperature = <95000>; /* millicelsius */
+};
+
+&soc_crit {
+ temperature = <100000>; /* millicelsius */
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart0 {
+
+ status = "okay";
+
+};
+
+&uart2 {
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
+&usb20_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vpu {
+ status = "okay";
+ vcodec-supply = <&vdd_logic>;
+};
+
+&vpu_mmu {
+ status = "okay";
+};
+
+/*
+&vepu {
+ status = "okay";
+};
+*/
+
+&vepu_mmu {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+ status = "okay";
+};
+
+/*
+&rga {
+ status = "okay";
+};
+*/
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&analog_sound {
+ status = "okay";
+};
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