331 lines
11 KiB
Diff
331 lines
11 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: tonymac32 <tonymckahan@gmail.com>
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Date: Wed, 7 Oct 2020 23:39:54 -0400
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Subject: board-rk3328-roc-cc-adjust-DMC-opps
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Signed-off-by: tonymac32 <tonymckahan@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi | 311 ++++++++++
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1 file changed, 311 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi
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new file mode 100644
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index 000000000000..303428153094
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi
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@@ -0,0 +1,311 @@
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+/*
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+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPL or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This library is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This library is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+#include <dt-bindings/clock/rockchip-ddr.h>
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+#include <dt-bindings/memory/rk3328-dram.h>
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+
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+/ {
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+ ddr_timing: ddr_timing {
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+ compatible = "rockchip,ddr-timing";
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+ ddr3_speed_bin = <DDR3_DEFAULT>;
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+ ddr4_speed_bin = <DDR4_DEFAULT>;
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+ pd_idle = <0>;
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+ sr_idle = <0>;
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+ sr_mc_gate_idle = <0>;
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+ srpd_lite_idle = <0>;
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+ standby_idle = <0>;
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+
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+ auto_pd_dis_freq = <1066>;
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+ auto_sr_dis_freq = <800>;
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+ ddr3_dll_dis_freq = <300>;
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+ ddr4_dll_dis_freq = <625>;
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+ phy_dll_dis_freq = <400>;
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+
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+ ddr3_odt_dis_freq = <100>;
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+ phy_ddr3_odt_dis_freq = <100>;
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+ ddr3_drv = <DDR3_DS_40ohm>;
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+ ddr3_odt = <DDR3_ODT_120ohm>;
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+ phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
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+ phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
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+ phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
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+ phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
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+
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+ lpddr3_odt_dis_freq = <666>;
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+ phy_lpddr3_odt_dis_freq = <666>;
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+ lpddr3_drv = <LP3_DS_40ohm>;
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+ lpddr3_odt = <LP3_ODT_240ohm>;
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+ phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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+ phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
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+ phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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+ phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
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+
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+ lpddr4_odt_dis_freq = <800>;
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+ phy_lpddr4_odt_dis_freq = <800>;
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+ lpddr4_drv = <LP4_PDDS_60ohm>;
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+ lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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+ lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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+ phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
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+ phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
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+ phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
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+ phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
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+
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+ ddr4_odt_dis_freq = <666>;
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+ phy_ddr4_odt_dis_freq = <666>;
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+ ddr4_drv = <DDR4_DS_34ohm>;
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+ ddr4_odt = <DDR4_RTT_NOM_240ohm>;
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+ phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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+ phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
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+ phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
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+ phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
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+
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+ /* CA de-skew, one step is 47.8ps, range 0-15 */
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+ ddr3a1_ddr4a9_de-skew = <0>;
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+ ddr3a0_ddr4a10_de-skew = <0>;
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+ ddr3a3_ddr4a6_de-skew = <1>;
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+ ddr3a2_ddr4a4_de-skew = <1>;
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+ ddr3a5_ddr4a8_de-skew = <0>;
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+ ddr3a4_ddr4a5_de-skew = <2>;
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+ ddr3a7_ddr4a11_de-skew = <0>;
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+ ddr3a6_ddr4a7_de-skew = <2>;
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+ ddr3a9_ddr4a0_de-skew = <1>;
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+ ddr3a8_ddr4a13_de-skew = <0>;
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+ ddr3a11_ddr4a3_de-skew = <2>;
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+ ddr3a10_ddr4cs0_de-skew = <0>;
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+ ddr3a13_ddr4a2_de-skew = <1>;
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+ ddr3a12_ddr4ba1_de-skew = <0>;
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+ ddr3a15_ddr4odt0_de-skew = <0>;
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+ ddr3a14_ddr4a1_de-skew = <1>;
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+ ddr3ba1_ddr4a15_de-skew = <0>;
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+ ddr3ba0_ddr4bg0_de-skew = <0>;
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+ ddr3ras_ddr4cke_de-skew = <0>;
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+ ddr3ba2_ddr4ba0_de-skew = <1>;
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+ ddr3we_ddr4bg1_de-skew = <1>;
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+ ddr3cas_ddr4a12_de-skew = <0>;
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+ ddr3ckn_ddr4ckn_de-skew = <5>;
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+ ddr3ckp_ddr4ckp_de-skew = <5>;
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+ ddr3cke_ddr4a16_de-skew = <1>;
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+ ddr3odt0_ddr4a14_de-skew = <0>;
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+ ddr3cs0_ddr4act_de-skew = <1>;
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+ ddr3reset_ddr4reset_de-skew = <0>;
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+ ddr3cs1_ddr4cs1_de-skew = <0>;
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+ ddr3odt1_ddr4odt1_de-skew = <0>;
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+
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+ /* DATA de-skew
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+ * RX one step is 25.1ps, range 0-15
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+ * TX one step is 47.8ps, range 0-15
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+ */
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+ cs0_dm0_rx_de-skew = <7>;
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+ cs0_dm0_tx_de-skew = <8>;
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+ cs0_dq0_rx_de-skew = <7>;
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+ cs0_dq0_tx_de-skew = <8>;
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+ cs0_dq1_rx_de-skew = <7>;
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+ cs0_dq1_tx_de-skew = <8>;
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+ cs0_dq2_rx_de-skew = <7>;
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+ cs0_dq2_tx_de-skew = <8>;
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+ cs0_dq3_rx_de-skew = <7>;
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+ cs0_dq3_tx_de-skew = <8>;
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+ cs0_dq4_rx_de-skew = <7>;
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+ cs0_dq4_tx_de-skew = <8>;
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+ cs0_dq5_rx_de-skew = <7>;
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+ cs0_dq5_tx_de-skew = <8>;
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+ cs0_dq6_rx_de-skew = <7>;
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+ cs0_dq6_tx_de-skew = <8>;
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+ cs0_dq7_rx_de-skew = <7>;
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+ cs0_dq7_tx_de-skew = <8>;
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+ cs0_dqs0_rx_de-skew = <6>;
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+ cs0_dqs0p_tx_de-skew = <9>;
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+ cs0_dqs0n_tx_de-skew = <9>;
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+
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+ cs0_dm1_rx_de-skew = <7>;
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+ cs0_dm1_tx_de-skew = <7>;
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+ cs0_dq8_rx_de-skew = <7>;
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+ cs0_dq8_tx_de-skew = <8>;
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+ cs0_dq9_rx_de-skew = <7>;
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+ cs0_dq9_tx_de-skew = <7>;
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+ cs0_dq10_rx_de-skew = <7>;
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+ cs0_dq10_tx_de-skew = <8>;
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+ cs0_dq11_rx_de-skew = <7>;
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+ cs0_dq11_tx_de-skew = <7>;
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+ cs0_dq12_rx_de-skew = <7>;
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+ cs0_dq12_tx_de-skew = <8>;
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+ cs0_dq13_rx_de-skew = <7>;
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+ cs0_dq13_tx_de-skew = <7>;
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+ cs0_dq14_rx_de-skew = <7>;
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+ cs0_dq14_tx_de-skew = <8>;
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+ cs0_dq15_rx_de-skew = <7>;
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+ cs0_dq15_tx_de-skew = <7>;
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+ cs0_dqs1_rx_de-skew = <7>;
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+ cs0_dqs1p_tx_de-skew = <9>;
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+ cs0_dqs1n_tx_de-skew = <9>;
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+
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+ cs0_dm2_rx_de-skew = <7>;
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+ cs0_dm2_tx_de-skew = <8>;
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+ cs0_dq16_rx_de-skew = <7>;
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+ cs0_dq16_tx_de-skew = <8>;
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+ cs0_dq17_rx_de-skew = <7>;
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+ cs0_dq17_tx_de-skew = <8>;
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+ cs0_dq18_rx_de-skew = <7>;
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+ cs0_dq18_tx_de-skew = <8>;
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+ cs0_dq19_rx_de-skew = <7>;
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+ cs0_dq19_tx_de-skew = <8>;
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+ cs0_dq20_rx_de-skew = <7>;
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+ cs0_dq20_tx_de-skew = <8>;
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+ cs0_dq21_rx_de-skew = <7>;
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+ cs0_dq21_tx_de-skew = <8>;
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+ cs0_dq22_rx_de-skew = <7>;
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+ cs0_dq22_tx_de-skew = <8>;
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+ cs0_dq23_rx_de-skew = <7>;
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+ cs0_dq23_tx_de-skew = <8>;
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+ cs0_dqs2_rx_de-skew = <6>;
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+ cs0_dqs2p_tx_de-skew = <9>;
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+ cs0_dqs2n_tx_de-skew = <9>;
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+
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+ cs0_dm3_rx_de-skew = <7>;
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+ cs0_dm3_tx_de-skew = <7>;
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+ cs0_dq24_rx_de-skew = <7>;
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+ cs0_dq24_tx_de-skew = <8>;
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+ cs0_dq25_rx_de-skew = <7>;
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+ cs0_dq25_tx_de-skew = <7>;
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+ cs0_dq26_rx_de-skew = <7>;
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+ cs0_dq26_tx_de-skew = <7>;
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+ cs0_dq27_rx_de-skew = <7>;
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+ cs0_dq27_tx_de-skew = <7>;
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+ cs0_dq28_rx_de-skew = <7>;
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+ cs0_dq28_tx_de-skew = <7>;
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+ cs0_dq29_rx_de-skew = <7>;
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+ cs0_dq29_tx_de-skew = <7>;
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+ cs0_dq30_rx_de-skew = <7>;
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+ cs0_dq30_tx_de-skew = <7>;
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+ cs0_dq31_rx_de-skew = <7>;
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+ cs0_dq31_tx_de-skew = <7>;
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+ cs0_dqs3_rx_de-skew = <7>;
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+ cs0_dqs3p_tx_de-skew = <9>;
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+ cs0_dqs3n_tx_de-skew = <9>;
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+
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+ cs1_dm0_rx_de-skew = <7>;
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+ cs1_dm0_tx_de-skew = <8>;
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+ cs1_dq0_rx_de-skew = <7>;
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+ cs1_dq0_tx_de-skew = <8>;
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+ cs1_dq1_rx_de-skew = <7>;
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+ cs1_dq1_tx_de-skew = <8>;
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+ cs1_dq2_rx_de-skew = <7>;
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+ cs1_dq2_tx_de-skew = <8>;
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+ cs1_dq3_rx_de-skew = <7>;
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+ cs1_dq3_tx_de-skew = <8>;
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+ cs1_dq4_rx_de-skew = <7>;
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+ cs1_dq4_tx_de-skew = <8>;
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+ cs1_dq5_rx_de-skew = <7>;
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+ cs1_dq5_tx_de-skew = <8>;
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+ cs1_dq6_rx_de-skew = <7>;
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+ cs1_dq6_tx_de-skew = <8>;
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+ cs1_dq7_rx_de-skew = <7>;
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+ cs1_dq7_tx_de-skew = <8>;
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+ cs1_dqs0_rx_de-skew = <6>;
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+ cs1_dqs0p_tx_de-skew = <9>;
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+ cs1_dqs0n_tx_de-skew = <9>;
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+
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+ cs1_dm1_rx_de-skew = <7>;
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+ cs1_dm1_tx_de-skew = <7>;
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+ cs1_dq8_rx_de-skew = <7>;
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+ cs1_dq8_tx_de-skew = <8>;
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+ cs1_dq9_rx_de-skew = <7>;
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+ cs1_dq9_tx_de-skew = <7>;
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+ cs1_dq10_rx_de-skew = <7>;
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+ cs1_dq10_tx_de-skew = <8>;
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+ cs1_dq11_rx_de-skew = <7>;
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+ cs1_dq11_tx_de-skew = <7>;
|
||
|
|
+ cs1_dq12_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq12_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq13_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq13_tx_de-skew = <7>;
|
||
|
|
+ cs1_dq14_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq14_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq15_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq15_tx_de-skew = <7>;
|
||
|
|
+ cs1_dqs1_rx_de-skew = <7>;
|
||
|
|
+ cs1_dqs1p_tx_de-skew = <9>;
|
||
|
|
+ cs1_dqs1n_tx_de-skew = <9>;
|
||
|
|
+
|
||
|
|
+ cs1_dm2_rx_de-skew = <7>;
|
||
|
|
+ cs1_dm2_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq16_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq16_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq17_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq17_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq18_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq18_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq19_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq19_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq20_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq20_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq21_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq21_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq22_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq22_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq23_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq23_tx_de-skew = <8>;
|
||
|
|
+ cs1_dqs2_rx_de-skew = <6>;
|
||
|
|
+ cs1_dqs2p_tx_de-skew = <9>;
|
||
|
|
+ cs1_dqs2n_tx_de-skew = <9>;
|
||
|
|
+
|
||
|
|
+ cs1_dm3_rx_de-skew = <7>;
|
||
|
|
+ cs1_dm3_tx_de-skew = <7>;
|
||
|
|
+ cs1_dq24_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq24_tx_de-skew = <8>;
|
||
|
|
+ cs1_dq25_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq25_tx_de-skew = <7>;
|
||
|
|
+ cs1_dq26_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq26_tx_de-skew = <7>;
|
||
|
|
+ cs1_dq27_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq27_tx_de-skew = <7>;
|
||
|
|
+ cs1_dq28_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq28_tx_de-skew = <7>;
|
||
|
|
+ cs1_dq29_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq29_tx_de-skew = <7>;
|
||
|
|
+ cs1_dq30_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq30_tx_de-skew = <7>;
|
||
|
|
+ cs1_dq31_rx_de-skew = <7>;
|
||
|
|
+ cs1_dq31_tx_de-skew = <7>;
|
||
|
|
+ cs1_dqs3_rx_de-skew = <7>;
|
||
|
|
+ cs1_dqs3p_tx_de-skew = <9>;
|
||
|
|
+ cs1_dqs3n_tx_de-skew = <9>;
|
||
|
|
+ };
|
||
|
|
+};
|
||
|
|
--
|
||
|
|
Armbian
|
||
|
|
|