39 lines
1.1 KiB
Diff
39 lines
1.1 KiB
Diff
|
From 5e433dd63332d469940582ec16ad2e28a565b6dc Mon Sep 17 00:00:00 2001
|
||
|
|
From: Samuel Holland <samuel@sholland.org>
|
||
|
|
Date: Sun, 12 Jan 2020 20:27:08 -0600
|
||
|
|
Subject: [PATCH 167/351] ARM: dts: sunxi: h3/h5: Add r_intc node
|
||
|
|
|
||
|
|
The H3 and H5 SoCs have an additional interrupt controller in the RTC
|
||
|
|
power domain that can be used to enable wakeup for certain IRQs.
|
||
|
|
|
||
|
|
Add a node for it.
|
||
|
|
|
||
|
|
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||
|
|
---
|
||
|
|
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++
|
||
|
|
1 file changed, 9 insertions(+)
|
||
|
|
|
||
|
|
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
|
||
|
|
index 99fee08780f8..e4a9db619920 100644
|
||
|
|
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
|
||
|
|
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
|
||
|
|
@@ -854,6 +854,15 @@ rtc: rtc@1f00000 {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
+ r_intc: interrupt-controller@1f00c00 {
|
||
|
|
+ compatible = "allwinner,sun8i-h3-r-intc",
|
||
|
|
+ "allwinner,sun6i-a31-r-intc";
|
||
|
|
+ interrupt-controller;
|
||
|
|
+ #interrupt-cells = <2>;
|
||
|
|
+ reg = <0x01f00c00 0x400>;
|
||
|
|
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
+ };
|
||
|
|
+
|
||
|
|
r_ccu: clock@1f01400 {
|
||
|
|
compatible = "allwinner,sun8i-h3-r-ccu";
|
||
|
|
reg = <0x01f01400 0x100>;
|
||
|
|
--
|
||
|
|
2.34.0
|
||
|
|
|