75 lines
2.7 KiB
Diff
75 lines
2.7 KiB
Diff
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From 4a45831e4fc5204f7d72c5628a1b0167f78a94ce Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Mon, 30 Dec 2019 22:58:21 -0600
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Subject: [PATCH 157/351] bus: sunxi-rsb: Make interrupt handling more robust
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The RSB controller has two registers for controlling interrupt inputs:
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RSB_INTE, which has bits for each possible interrupt, and the global
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interrupt enable bit in RSB_CTRL.
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Currently, we enable the bits in RSB_INTE before each transfer, but this
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is unnecessary because we never disable them. Move the initialization of
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RSB_INTE so it is done only once.
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We also set the global interrupt enable bit before each transfer. Unlike
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other bits in RSB_CTRL, this bit is cleared by writing a zero. Thus, we
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clear the bit in the post-timeout cleanup code, but that is not
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documented, so note that in the comment. However, in the success/error
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path (when an IRQ is received), we do not disable further interrupts.
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Add a register write to do just that.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/bus/sunxi-rsb.c | 14 ++++++++++----
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1 file changed, 10 insertions(+), 4 deletions(-)
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diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c
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index cbfbee32e15e..edb5f338f494 100644
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--- a/drivers/bus/sunxi-rsb.c
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+++ b/drivers/bus/sunxi-rsb.c
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@@ -276,8 +276,6 @@ static int _sunxi_rsb_run_xfer(struct sunxi_rsb *rsb)
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reinit_completion(&rsb->complete);
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- writel(RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | RSB_INTS_TRANS_OVER,
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- rsb->regs + RSB_INTE);
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writel(RSB_CTRL_START_TRANS | RSB_CTRL_GLOBAL_INT_ENB,
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rsb->regs + RSB_CTRL);
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@@ -285,7 +283,7 @@ static int _sunxi_rsb_run_xfer(struct sunxi_rsb *rsb)
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msecs_to_jiffies(100))) {
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dev_dbg(rsb->dev, "RSB timeout\n");
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- /* abort the transfer */
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+ /* abort the transfer and disable interrupts */
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writel(RSB_CTRL_ABORT_TRANS, rsb->regs + RSB_CTRL);
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/* clear any interrupt flags */
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@@ -460,7 +458,8 @@ static irqreturn_t sunxi_rsb_irq(int irq, void *dev_id)
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status = readl(rsb->regs + RSB_INTS);
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rsb->status = status;
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- /* Clear interrupts */
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+ /* Disable and clear interrupts */
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+ writel(0, rsb->regs + RSB_CTRL);
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status &= (RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR |
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RSB_INTS_TRANS_OVER);
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writel(status, rsb->regs + RSB_INTS);
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@@ -640,6 +639,13 @@ static int sunxi_rsb_init_controller(struct sunxi_rsb *rsb)
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writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1),
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rsb->regs + RSB_CCR);
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+ /*
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+ * Select the interrupts we care about. They will not actually fire
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+ * until the RSB_CTRL_GLOBAL_INT_ENB bit is set.
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+ */
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+ writel(RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | RSB_INTS_TRANS_OVER,
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+ rsb->regs + RSB_INTE);
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+
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return 0;
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err_clk_disable:
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--
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2.34.0
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