106 lines
3.3 KiB
Diff
106 lines
3.3 KiB
Diff
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From f081b3349bc32b852fcfedb9fbb0e7529f9b0af1 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Tue, 21 Jul 2020 21:53:27 +0200
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Subject: [PATCH 053/101] drv:media: cedrus: check for H264, HEVC limitations
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/staging/media/sunxi/cedrus/cedrus.c | 47 +++++++++++++++++++++
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drivers/staging/media/sunxi/cedrus/cedrus.h | 1 +
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2 files changed, 48 insertions(+)
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
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index b86bef8d4..314afde91 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
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@@ -28,6 +28,50 @@
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#include "cedrus_dec.h"
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#include "cedrus_hw.h"
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+static int cedrus_try_ctrl(struct v4l2_ctrl *ctrl)
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+{
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+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
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+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
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+
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+ if (sps->chroma_format_idc != 1)
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+ /* Only 4:2:0 is supported */
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+ return -EINVAL;
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+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
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+ /* Luma and chroma bit depth mismatch */
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+ return -EINVAL;
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+ if (sps->bit_depth_luma_minus8 != 0)
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+ /* Only 8-bit is supported */
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+ return -EINVAL;
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+ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) {
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+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
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+ struct cedrus_ctx *ctx = container_of(ctrl->handler, struct cedrus_ctx, hdl);
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+
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+ if (sps->chroma_format_idc != 1)
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+ /* Only 4:2:0 is supported */
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+ return -EINVAL;
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+
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+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
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+ /* Luma and chroma bit depth mismatch */
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+ return -EINVAL;
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+
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+ if (ctx->dev->capabilities & CEDRUS_CAPABILITY_H265_10_DEC) {
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+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
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+ /* Only 8-bit and 10-bit are supported */
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+ return -EINVAL;
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+ } else {
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+ if (sps->bit_depth_luma_minus8 != 0)
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+ /* Only 8-bit is supported */
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+ return -EINVAL;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct v4l2_ctrl_ops cedrus_ctrl_ops = {
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+ .try_ctrl = cedrus_try_ctrl,
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+};
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+
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static const struct cedrus_control cedrus_controls[] = {
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{
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.cfg = {
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@@ -62,6 +106,7 @@ static const struct cedrus_control cedrus_controls[] = {
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{
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.cfg = {
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.id = V4L2_CID_STATELESS_H264_SPS,
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+ .ops = &cedrus_ctrl_ops,
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},
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.codec = CEDRUS_CODEC_H264,
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},
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@@ -120,6 +165,7 @@ static const struct cedrus_control cedrus_controls[] = {
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{
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.cfg = {
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.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
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+ .ops = &cedrus_ctrl_ops,
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},
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.codec = CEDRUS_CODEC_H265,
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},
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@@ -560,6 +606,7 @@ static const struct cedrus_variant sun50i_h6_cedrus_variant = {
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CEDRUS_CAPABILITY_MPEG2_DEC |
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CEDRUS_CAPABILITY_H264_DEC |
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CEDRUS_CAPABILITY_H265_DEC |
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+ CEDRUS_CAPABILITY_H265_10_DEC |
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CEDRUS_CAPABILITY_VP8_DEC,
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.mod_rate = 600000000,
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};
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
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index f280e81d0..25079901a 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
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@@ -32,6 +32,7 @@
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#define CEDRUS_CAPABILITY_H264_DEC BIT(2)
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#define CEDRUS_CAPABILITY_MPEG2_DEC BIT(3)
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#define CEDRUS_CAPABILITY_VP8_DEC BIT(4)
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+#define CEDRUS_CAPABILITY_H265_10_DEC BIT(5)
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enum cedrus_codec {
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CEDRUS_CODEC_MPEG2,
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--
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2.31.1
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