59 lines
2.6 KiB
Diff
59 lines
2.6 KiB
Diff
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From 50887c0016bcb1495c9a9c13f90584f8bbed0736 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megi@xff.cz>
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Date: Thu, 25 Aug 2022 00:29:15 +0200
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Subject: [PATCH 316/469] clk: rk3399: Allow to set rate of clk_i2s0_frac's
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parent
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Otherwise when when clk_i2s0 muxes to clk_i2s0_div which requires
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setting high divider value on clk_i2s0_div, and then muxes back to
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clk_i2s0_frac, clk_i2s0_frac would have no way to change the
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clk_i2s0_div's divider ratio back to 1 so that it can satisfy the
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condition for m/n > 20 for fractional division to work correctly.
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Bug is reproducible by playing 44.1k audio, then 48k audio, and then
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44.1k audio again. This results in clk_i2s0_div being set to 49 and
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clk_i2s0_frac not being able to cope with such a low input clock rate
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and audio playing extremely slowly.
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The identical issue is on i2s1 and i2s2 clocks, too.
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Signed-off-by: Ondrej Jirman <megi@xff.cz>
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---
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drivers/clk/rockchip/clk-rk3399.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
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index aa3cb0ddca35..89df64ad989b 100644
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--- a/drivers/clk/rockchip/clk-rk3399.c
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+++ b/drivers/clk/rockchip/clk-rk3399.c
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@@ -597,7 +597,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(8), 3, GFLAGS),
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- COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
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+ COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(96), 0,
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RK3399_CLKGATE_CON(8), 4, GFLAGS,
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&rk3399_i2s0_fracmux),
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@@ -607,7 +607,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(8), 6, GFLAGS),
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- COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
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+ COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(97), 0,
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RK3399_CLKGATE_CON(8), 7, GFLAGS,
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&rk3399_i2s1_fracmux),
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@@ -617,7 +617,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(8), 9, GFLAGS),
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- COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
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+ COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(98), 0,
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RK3399_CLKGATE_CON(8), 10, GFLAGS,
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&rk3399_i2s2_fracmux),
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--
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2.34.1
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