88 lines
3.9 KiB
Diff
88 lines
3.9 KiB
Diff
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From 207f1833a05f8964b606e869a46e13d21fef5b50 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 19 Jul 2020 17:10:15 -0500
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Subject: [PATCH 260/469] clk: sunxi-ng: a64: Increase PLL_AUDIO base frequency
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 41 +++++++++++++++++++++------
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1 file changed, 32 insertions(+), 9 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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index 41519185600a..5d92cf8e2eab 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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@@ -47,15 +47,35 @@ static struct ccu_nkmp pll_cpux_clk = {
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* With sigma-delta modulation for fractional-N on the audio PLL,
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* we have to use specific dividers. This means the variable divider
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* can no longer be used, as the audio codec requests the exact clock
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- * rates we support through this mechanism. So we now hard code the
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- * variable divider to 1. This means the clock rates will no longer
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- * match the clock names.
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+ * rates we support through this mechanism.
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+ *
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+ * For the audio codec to work correctly, pll-audio must be exactly
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+ * 22579200 Hz or 24576000 Hz, and pll-audio-4x (1x the base) must be
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+ * between 3x and 8x that frequency. For the SRC to work at 96 kHz,
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+ * pll-audio-4x must be at least 6x pll-audio.
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+ *
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+ * For now, hard code the variable divider to 3.
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*/
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#define SUN50I_A64_PLL_AUDIO_REG 0x008
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+#define SUN50I_A64_PLL_AUDIO_BIAS_REG 0x224
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static struct ccu_sdm_setting pll_audio_sdm_table[] = {
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- { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
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- { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
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+ /* 24000000 * ( 7 + 0x10d84 / 131072 ) / 8 / 1 - 22579200 == -6.9Hz */
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+ { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
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+ /* 24000000 * ( 14 + 0x0ac02 / 131072 ) / 14 / 1 - 24576000 == -2.5Hz */
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+ { .rate = 24576000, .pattern = 0xc000ac08, .m = 14, .n = 14 },
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+ /* 24000000 * ( 8 + 0x0ef35 / 131072 ) / 3 / 3 - 22579200 == 3.3Hz */
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+ { .rate = 67737600, .pattern = 0xc000ef35, .m = 3, .n = 8 },
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+ /* 24000000 * ( 15 + 0x0b852 / 131072 ) / 5 / 3 - 24576000 == 1.0Hz */
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+ { .rate = 73728000, .pattern = 0xc000b852, .m = 5, .n = 15 },
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+ /* 24000000 * ( 7 + 0x10d84 / 131072 ) / 2 / 4 - 22579200 == -6.9Hz */
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+ { .rate = 90316800, .pattern = 0xc0010d84, .m = 2, .n = 7 },
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+ /* 24000000 * ( 16 + 0x0c49c / 131072 ) / 4 / 4 - 24576000 == 4.0Hz */
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+ { .rate = 98304000, .pattern = 0xc000c49c, .m = 4, .n = 16 },
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+ /* 24000000 * ( 5 + 0x14a23 / 131072 ) / 1 / 6 - 22579200 == -6.9Hz */
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+ { .rate = 135475200, .pattern = 0xc0014a23, .m = 1, .n = 5 },
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+ /* 24000000 * ( 12 + 0x09375 / 131072 ) / 2 / 6 - 24576000 == 4.0Hz */
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+ { .rate = 147456000, .pattern = 0xc0009375, .m = 2, .n = 12 },
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};
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static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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@@ -604,10 +624,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
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&pll_audio_base_clk.common.hw
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};
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-/* We hardcode the divider to 1 for now */
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+/* We hardcode the divider to 3 for now */
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static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
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clk_parent_pll_audio,
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- 1, 1, CLK_SET_RATE_PARENT);
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+ 3, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
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clk_parent_pll_audio,
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2, 1, CLK_SET_RATE_PARENT);
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@@ -946,10 +966,13 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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- /* Force the PLL-Audio-1x divider to 1 */
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+ /* Force the pll-audio variable divider to 3 */
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val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
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val &= ~GENMASK(19, 16);
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- writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
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+ writel(val | (2 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
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+
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+ /* Decrease the PLL AUDIO bias current to reduce noise. */
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+ writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
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writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
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--
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2.34.1
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