106 lines
3.1 KiB
Diff
106 lines
3.1 KiB
Diff
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From 6c06a690a82eeaa6616d41ab1a93f1817e89360a Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
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Date: Tue, 20 Aug 2019 14:54:48 +0200
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Subject: [PATCH 059/464] arm64: dts: allwinner: orange-pi-3: Enable ethernet
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Orange Pi 3 has two regulators that power the Realtek RTL8211E
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PHY. According to the datasheet, both regulators need to be enabled
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at the same time, or that "phy-io" should be enabled slightly earlier
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than "phy" regulator.
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RTL8211E/RTL8211EG datasheet says:
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Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously
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or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power
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later than 3.3V power may lead to errors.
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The driver ensures the regulator enable ordering. The timing is set
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in DT via startup-delay-us.
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We also need to wait at least 30ms after power-up/reset, before
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accessing the PHY registers.
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All values of RX/TX delay were tested exhaustively and a middle one
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of the range of working values was chosen.
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Signed-off-by: Ondrej Jirman <megi@xff.cz>
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---
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.../dts/allwinner/sun50i-h6-orangepi-3.dts | 40 +++++++++++++++++++
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1 file changed, 40 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
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index 6fc65e8db220..c2ea73d43122 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
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@@ -15,6 +15,7 @@ / {
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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+ ethernet0 = &emac;
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};
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chosen {
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@@ -64,6 +65,15 @@ reg_vcc5v: vcc5v {
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regulator-always-on;
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};
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+ reg_gmac_2v5: gmac-2v5 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "gmac-2v5";
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+ regulator-min-microvolt = <2500000>;
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+ regulator-max-microvolt = <2500000>;
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+ enable-active-high;
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+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
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+ };
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+
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reg_vcc33_wifi: vcc33-wifi {
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/* Always on 3.3V regulator for WiFi and BT */
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compatible = "regulator-fixed";
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@@ -128,6 +138,35 @@ hdmi_out_con: endpoint {
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};
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};
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&ext_rgmii_pins>;
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+ phy-mode = "rgmii-id";
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+ phy-handle = <&ext_rgmii_phy>;
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+ /*
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+ * The board uses 2.5V RGMII signalling. Power sequence to enable
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+ * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
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+ * at the same time and to wait 100ms. The driver enables phy-io
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+ * first. Delay is achieved with enable-ramp-delay on reg_aldo2.
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+ */
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+ phy-supply = <®_aldo2>;
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+ phy-io-supply = <®_gmac_2v5>;
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+ allwinner,rx-delay-ps = <200>;
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+ allwinner,tx-delay-ps = <200>;
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+ status = "okay";
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+};
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+
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+&mdio {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+
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+ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
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+ reset-assert-us = <15000>;
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+ reset-deassert-us = <40000>;
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+ };
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+};
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+
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&mmc0 {
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vmmc-supply = <®_cldo1>;
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cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
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@@ -211,6 +250,7 @@ reg_aldo2: aldo2 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc33-audio-tv-ephy-mac";
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+ regulator-enable-ramp-delay = <100000>;
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};
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/* ALDO3 is shorted to CLDO1 */
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--
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2.34.1
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