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build/patch/u-boot/u-boot-media/board_nanopi-r4s/0002-rockchip-rk3399-split-nanopi-r4s-out-of-evb_rk3399.patch

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添加构建Allwinner H616四核2GB RAM SoC WiFi（蓝莓）
2023-09-19 11:24:52 +08:00
From 244492a7a5451eca042d3ec7ccff8de6e23dd288 Mon Sep 17 00:00:00 2001
From: hmz007 <hmz007@gmail.com>
Date: Fri, 18 Dec 2020 17:10:35 +0800
Subject: [PATCH 2/4] rockchip: rk3399: split nanopi-r4s out of evb_rk3399
Signed-off-by: hmz007 <hmz007@gmail.com>
---
arch/arm/mach-rockchip/rk3399/Kconfig | 6 +
board/friendlyarm/nanopi4/Kconfig | 15 +++
board/friendlyarm/nanopi4/MAINTAINERS | 6 +
board/friendlyarm/nanopi4/Makefile | 8 ++
board/friendlyarm/nanopi4/README | 122 +++++++++++++++++++
board/friendlyarm/nanopi4/hwrev.c | 149 ++++++++++++++++++++++++
board/friendlyarm/nanopi4/hwrev.h | 27 +++++
board/friendlyarm/nanopi4/nanopi4.c | 148 +++++++++++++++++++++++
configs/nanopi-r4s-4gb-rk3399_defconfig | 4 +-
configs/nanopi-r4s-rk3399_defconfig | 4 +-
drivers/clk/rockchip/clk_rk3399.c | 2 +
include/configs/nanopi4.h | 24 ++++
12 files changed, 511 insertions(+), 4 deletions(-)
create mode 100644 board/friendlyarm/nanopi4/Kconfig
create mode 100644 board/friendlyarm/nanopi4/MAINTAINERS
create mode 100644 board/friendlyarm/nanopi4/Makefile
create mode 100644 board/friendlyarm/nanopi4/README
create mode 100644 board/friendlyarm/nanopi4/hwrev.c
create mode 100644 board/friendlyarm/nanopi4/hwrev.h
create mode 100644 board/friendlyarm/nanopi4/nanopi4.c
create mode 100644 include/configs/nanopi4.h
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 17628f9171..2a44aae43c 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -109,6 +109,11 @@ config TARGET_ROC_PC_RK3399
* wide voltage input(5V-15V), dual cell battery
* Wifi/BT accessible via expansion board M.2
+config TARGET_NANOPI4
+ bool "FriendlyElec NanoPi 4 Series"
+ help
+ Support for FriendlyElec boards based on RK3399.
+
endchoice
config ROCKCHIP_BOOT_MODE_REG
@@ -152,6 +157,7 @@ config SYS_BOOTCOUNT_ADDR
endif # BOOTCOUNT_LIMIT
source "board/firefly/roc-pc-rk3399/Kconfig"
+source "board/friendlyarm/nanopi4/Kconfig"
source "board/google/gru/Kconfig"
source "board/pine64/pinebook-pro-rk3399/Kconfig"
source "board/pine64/rockpro64_rk3399/Kconfig"
diff --git a/board/friendlyarm/nanopi4/Kconfig b/board/friendlyarm/nanopi4/Kconfig
new file mode 100644
index 0000000000..f3f9dd7b56
--- /dev/null
+++ b/board/friendlyarm/nanopi4/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_NANOPI4
+
+config SYS_BOARD
+ default "nanopi4"
+
+config SYS_VENDOR
+ default "friendlyarm"
+
+config SYS_CONFIG_NAME
+ default "nanopi4"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+
+endif
diff --git a/board/friendlyarm/nanopi4/MAINTAINERS b/board/friendlyarm/nanopi4/MAINTAINERS
new file mode 100644
index 0000000000..b4c35701d6
--- /dev/null
+++ b/board/friendlyarm/nanopi4/MAINTAINERS
@@ -0,0 +1,6 @@
+NanoPi 4 Series
+M: <support@friendlyarm.com>
+S: Maintained
+F: board/friendlyarm/nanopi4/
+F: include/configs/nanopi4.h
+F: configs/nanopi4_defconfig
diff --git a/board/friendlyarm/nanopi4/Makefile b/board/friendlyarm/nanopi4/Makefile
new file mode 100644
index 0000000000..33a1466567
--- /dev/null
+++ b/board/friendlyarm/nanopi4/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd.
+# (http://www.friendlyarm.com)
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += nanopi4.o hwrev.o
diff --git a/board/friendlyarm/nanopi4/README b/board/friendlyarm/nanopi4/README
new file mode 100644
index 0000000000..c6f58203eb
--- /dev/null
+++ b/board/friendlyarm/nanopi4/README
@@ -0,0 +1,122 @@
+Introduction
+============
+
+RK3399 key features we might use in U-Boot:
+* CPU: ARMv8 64bit Big-Little architecture,
+* Big: dual-core Cortex-A72
+* Little: quad-core Cortex-A53
+* IRAM: 200KB
+* DRAM: 4GB-128MB dual-channel
+* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
+* SD/MMC: support SD 3.0, MMC 4.51
+* USB: USB3.0 type-C port *2 with dwc3 controller
+* USB2.0 EHCI host port *2
+* Display: RGB/HDMI/DP/MIPI/EDP
+
+evb key features:
+* regulator: pwm regulator for CPU B/L
+* PMIC: rk808
+* debug console: UART2
+
+In order to support Arm Trust Firmware(ATF), we can use either SPL or
+miniloader from rockchip to do:
+* do DRAM init
+* load and verify ATF image
+* load and verify U-Boot image
+
+Here is the step-by-step to boot to U-Boot on rk3399.
+
+Get the Source and prebuild binary
+==================================
+
+ > mkdir ~/evb_rk3399
+ > cd ~/evb_rk3399
+ > git clone https://github.com/ARM-software/arm-trusted-firmware.git
+ > git clone https://github.com/rockchip-linux/rkbin.git
+ > git clone https://github.com/rockchip-linux/rkdeveloptool.git
+
+
+Compile ATF
+===========
+
+ > cd arm-trusted-firmware
+ > make realclean
+ > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+
+ Get bl31.elf in this step, copy it to U-Boot root dir:
+ > cp build/rk3399/release/bl31/bl31.elf ../u-boot/
+
+ Or you can get the bl31.elf directly from Rockchip:
+ > cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf
+
+
+Compile U-Boot
+==============
+
+ > cd ../u-boot
+ > export CROSS_COMPILE=aarch64-linux-gnu-
+ > make evb-rk3399_defconfig
+ for firefly-rk3399, use below instead:
+ > make firefly-rk3399_defconfig
+ > make
+ > make u-boot.itb
+
+ Get spl/u-boot-spl.bin and u-boot.itb in this step.
+
+Compile rkdeveloptool
+=====================
+
+Get rkdeveloptool installed on your Host in this step.
+
+Follow instructions in latest README, example:
+ > cd ../rkdeveloptool
+ > autoreconf -i
+ > ./configure
+ > make
+ > sudo make install
+
+Both origin binaries and Tool are ready now, choose either option 1 or
+option 2 to deploy U-Boot.
+
+Package the image
+=================
+
+Package the image for U-Boot SPL(option 1)
+--------------------------------
+ > cd ..
+ > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin idbspl.img
+
+ Get idbspl.img in this step.
+
+Package the image for Rockchip miniloader(option 2)
+------------------------------------------
+ > cd ..
+ > cp arm-trusted-firmware/build/rk3399/release/bl31.elf rkbin/rk33
+ > ./rkbin/tools/trust_merger rkbin/tools/RK3399TRUST.ini
+ > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
+
+ Get trust.img and uboot.img in this step.
+
+Flash the image to eMMC
+=======================
+
+Flash the image with U-Boot SPL(option 1)
+-------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > rkdeveloptool wl 64 u-boot/idbspl.img
+ > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
+ > rkdeveloptool rd
+
+Flash the image with Rockchip miniloader(option 2)
+----------------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > rkdeveloptool ul rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > rkdeveloptool wl 0x4000 u-boot/uboot.img
+ > rkdeveloptool wl 0x6000 u-boot/trust.img
+ > rkdeveloptool rd
+
+You should be able to get U-Boot log in console/UART2(baurdrate 1500000)
+For more detail, please reference to:
+http://opensource.rock-chips.com/wiki_Boot_option
diff --git a/board/friendlyarm/nanopi4/hwrev.c b/board/friendlyarm/nanopi4/hwrev.c
new file mode 100644
index 0000000000..9199a927ee
--- /dev/null
+++ b/board/friendlyarm/nanopi4/hwrev.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch-rockchip/gpio.h>
+
+/*
+ * ID info:
+ * ID : Volts : ADC value : Bucket
+ * == ===== ========= ===========
+ * 0 : 0.102V: 58 : 0 - 81
+ * 1 : 0.211V: 120 : 82 - 150
+ * 2 : 0.319V: 181 : 151 - 211
+ * 3 : 0.427V: 242 : 212 - 274
+ * 4 : 0.542V: 307 : 275 - 342
+ * 5 : 0.666V: 378 : 343 - 411
+ * 6 : 0.781V: 444 : 412 - 477
+ * 7 : 0.900V: 511 : 478 - 545
+ * 8 : 1.023V: 581 : 546 - 613
+ * 9 : 1.137V: 646 : 614 - 675
+ * 10 : 1.240V: 704 : 676 - 733
+ * 11 : 1.343V: 763 : 734 - 795
+ * 12 : 1.457V: 828 : 796 - 861
+ * 13 : 1.576V: 895 : 862 - 925
+ * 14 : 1.684V: 956 : 926 - 989
+ * 15 : 1.800V: 1023 : 990 - 1023
+ */
+static const int id_readings[] = {
+ 81, 150, 211, 274, 342, 411, 477, 545,
+ 613, 675, 733, 795, 861, 925, 989, 1023
+};
+
+static int cached_board_id = -1;
+
+#define SARADC_BASE 0xFF100000
+#define SARADC_DATA (SARADC_BASE + 0)
+#define SARADC_CTRL (SARADC_BASE + 8)
+
+static u32 get_saradc_value(int chn)
+{
+ int timeout = 0;
+ u32 adc_value = 0;
+
+ writel(0, SARADC_CTRL);
+ udelay(2);
+
+ writel(0x28 | chn, SARADC_CTRL);
+ udelay(50);
+
+ timeout = 0;
+ do {
+ if (readl(SARADC_CTRL) & 0x40) {
+ adc_value = readl(SARADC_DATA) & 0x3FF;
+ goto stop_adc;
+ }
+
+ udelay(10);
+ } while (timeout++ < 100);
+
+stop_adc:
+ writel(0, SARADC_CTRL);
+
+ return adc_value;
+}
+
+static uint32_t get_adc_index(int chn)
+{
+ int i;
+ int adc_reading;
+
+ if (cached_board_id != -1)
+ return cached_board_id;
+
+ adc_reading = get_saradc_value(chn);
+ for (i = 0; i < ARRAY_SIZE(id_readings); i++) {
+ if (adc_reading <= id_readings[i]) {
+ debug("ADC reading %d, ID %d\n", adc_reading, i);
+ cached_board_id = i;
+ return i;
+ }
+ }
+
+ /* should die for impossible value */
+ return 0;
+}
+
+/*
+ * Board revision list: <GPIO4_D1 | GPIO4_D0>
+ * 0b00 - NanoPC-T4
+ * 0b01 - NanoPi M4
+ *
+ * Extended by ADC_IN4
+ * Group A:
+ * 0x04 - NanoPi NEO4
+ * 0x06 - SOC-RK3399
+ *
+ * Group B:
+ * 0x21 - NanoPi M4 Ver2.0
+ */
+static int pcb_rev = -1;
+
+void bd_hwrev_init(void)
+{
+#define GPIO4_BASE 0xff790000
+ struct rockchip_gpio_regs *regs = (void *)GPIO4_BASE;
+
+#ifdef CONFIG_SPL_BUILD
+ struct udevice *dev;
+
+ if (uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(clk_rk3399), &dev))
+ return;
+#endif
+
+ if (pcb_rev >= 0)
+ return;
+
+ /* D1, D0: input mode */
+ clrbits_le32(&regs->swport_ddr, (0x3 << 24));
+ pcb_rev = (readl(&regs->ext_port) >> 24) & 0x3;
+
+ if (pcb_rev == 0x3) {
+ /* Revision group A: 0x04 ~ 0x13 */
+ pcb_rev = 0x4 + get_adc_index(4);
+
+ } else if (pcb_rev == 0x1) {
+ int idx = get_adc_index(4);
+
+ /* Revision group B: 0x21 ~ 0x2f */
+ if (idx > 0) {
+ pcb_rev = 0x20 + idx;
+ }
+ }
+}
+
+/* To override __weak symbols */
+u32 get_board_rev(void)
+{
+ return pcb_rev;
+}
+
diff --git a/board/friendlyarm/nanopi4/hwrev.h b/board/friendlyarm/nanopi4/hwrev.h
new file mode 100644
index 0000000000..23b3c7a557
--- /dev/null
+++ b/board/friendlyarm/nanopi4/hwrev.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can access it online at
+ * http://www.gnu.org/licenses/gpl-2.0.html.
+ */
+
+#ifndef __BD_HW_REV_H__
+#define __BD_HW_REV_H__
+
+extern void bd_hwrev_config_gpio(void);
+extern void bd_hwrev_init(void);
+extern u32 get_board_rev(void);
+
+#endif /* __BD_HW_REV_H__ */
diff --git a/board/friendlyarm/nanopi4/nanopi4.c b/board/friendlyarm/nanopi4/nanopi4.c
new file mode 100644
index 0000000000..a140370ca2
--- /dev/null
+++ b/board/friendlyarm/nanopi4/nanopi4.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <hash.h>
+#include <linux/bitops.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <u-boot/sha256.h>
+
+#ifdef CONFIG_MISC_INIT_R
+static void setup_iodomain(void)
+{
+ struct rk3399_grf_regs *grf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /* BT565 and AUDIO is in 1.8v domain */
+ rk_setreg(&grf->io_vsel, BIT(0) | BIT(1));
+}
+
+static int __maybe_unused mac_read_from_generic_eeprom(u8 *addr)
+{
+ struct udevice *i2c_dev;
+ int ret;
+
+ /* Microchip 24AA02xxx EEPROMs with EUI-48 Node Identity */
+ ret = i2c_get_chip_for_busnum(2, 0x51, 1, &i2c_dev);
+ if (!ret)
+ ret = dm_i2c_read(i2c_dev, 0xfa, addr, 6);
+
+ return ret;
+}
+
+static void setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(CMD_NET)
+ int ret;
+ const char *cpuid = env_get("cpuid#");
+ u8 hash[SHA256_SUM_LEN];
+ int size = sizeof(hash);
+ u8 mac_addr[6];
+ int from_eeprom = 0;
+ int lockdown = 0;
+
+#ifndef CONFIG_ENV_IS_NOWHERE
+ lockdown = env_get_yesno("lockdown") == 1;
+#endif
+ if (lockdown && env_get("ethaddr"))
+ return;
+
+ ret = mac_read_from_generic_eeprom(mac_addr);
+ if (!ret && is_valid_ethaddr(mac_addr)) {
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ from_eeprom = 1;
+ }
+
+ if (!cpuid) {
+ debug("%s: could not retrieve 'cpuid#'\n", __func__);
+ return;
+ }
+
+ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
+ if (ret) {
+ debug("%s: failed to calculate SHA256\n", __func__);
+ return;
+ }
+
+ /* Copy 6 bytes of the hash to base the MAC address on */
+ memcpy(mac_addr, hash, 6);
+
+ /* Make this a valid MAC address and set it */
+ mac_addr[0] &= 0xfe; /* clear multicast bit */
+ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+
+ if (from_eeprom) {
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+ } else {
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+
+ if (lockdown && env_get("eth1addr"))
+ return;
+
+ /* Ugly, copy another 4 bytes to generate a similar address */
+ memcpy(mac_addr + 2, hash + 8, 4);
+ if (!memcmp(hash + 2, hash + 8, 4))
+ mac_addr[5] ^= 0xff;
+
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+ }
+#endif
+
+ return;
+}
+
+int misc_init_r(void)
+{
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
+
+ setup_iodomain();
+
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
+
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
+
+ setup_macaddr();
+ bd_hwrev_init();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial_string;
+ u64 serial = 0;
+
+ serial_string = env_get("serial#");
+
+ if (serial_string)
+ serial = simple_strtoull(serial_string, NULL, 16);
+
+ serialnr->high = (u32)(serial >> 32);
+ serialnr->low = (u32)(serial & 0xffffffff);
+}
+#endif
diff --git a/configs/nanopi-r4s-4gb-rk3399_defconfig b/configs/nanopi-r4s-4gb-rk3399_defconfig
index dcac8d426f..147bffad9d 100644
--- a/configs/nanopi-r4s-4gb-rk3399_defconfig
+++ b/configs/nanopi-r4s-4gb-rk3399_defconfig
@@ -4,13 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_TARGET_EVB_RK3399=y
+CONFIG_TARGET_NANOPI4=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s-4gb"
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s-4gb.dtb"
-CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig
index 034241f209..b67f7c0dc9 100644
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -4,13 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_TARGET_EVB_RK3399=y
+CONFIG_TARGET_NANOPI4=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
-CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 22c373a623..38975c0c65 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1351,6 +1351,8 @@ static void rkclk_init(struct rockchip_cru *cru)
pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
+
+ rk3399_saradc_set_clk(cru, 1000000);
}
#endif
diff --git a/include/configs/nanopi4.h b/include/configs/nanopi4.h
new file mode 100644
index 0000000000..a86d38976a
--- /dev/null
+++ b/include/configs/nanopi4.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_NANOPI4_H__
+#define __CONFIG_NANOPI4_H__
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3399_common.h>
+
+#define SDRAM_BANK_SIZE (2UL << 30)
+
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+
+#endif
--
2.25.1
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