38 lines
1.4 KiB
Diff
38 lines
1.4 KiB
Diff
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diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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index 7fcf340db6..723113b10b 100644
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--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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@@ -208,6 +208,7 @@ struct sunxi_ccm_reg {
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#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
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#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16)
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#define CCM_PLL1_CTRL_EN (0x1 << 31)
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+#define CCM_PLL1_CTRL_LOCK (0x1 << 28)
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#define CCM_PLL3_CTRL_M_SHIFT 0
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#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT)
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diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
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index 86f08ab717..0c403204c5 100644
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--- a/arch/arm/mach-sunxi/clock_sun6i.c
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+++ b/arch/arm/mach-sunxi/clock_sun6i.c
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@@ -158,15 +158,17 @@ void clock_set_pll1(unsigned int clk)
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writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
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CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
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CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
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- sdelay(200);
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+
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+ while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK))
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+ ;
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/* Switch CPU to PLL1 */
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if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
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writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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} else {
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- writel(AXI_DIV_3 << AXI_DIV_SHIFT |
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- ATB_DIV_2 << ATB_DIV_SHIFT |
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+ writel(AXI_DIV_4 << AXI_DIV_SHIFT |
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+ ATB_DIV_4 << ATB_DIV_SHIFT |
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CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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}
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