45 lines
1.6 KiB
Diff
45 lines
1.6 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Geert Uytterhoeven <geert@linux-m68k.org>
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Date: Thu, 25 Nov 2021 14:21:18 +0100
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Subject: riscv: dts: starfive: Group tuples in interrupt properties
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To improve human readability and enable automatic validation, the tuples
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in the various properties containing interrupt specifiers should be
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grouped.
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Fix this by grouping the tuples of "interrupts-extended" properties
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using angle brackets.
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Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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---
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arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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index 000447482aca..08eca47b5f29 100644
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--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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@@ -118,15 +118,15 @@ soc {
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clint: clint@2000000 {
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compatible = "starfive,jh7100-clint", "sifive,clint0";
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reg = <0x0 0x2000000 0x0 0x10000>;
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- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
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- &cpu1_intc 3 &cpu1_intc 7>;
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+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
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+ <&cpu1_intc 3>, <&cpu1_intc 7>;
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};
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plic: interrupt-controller@c000000 {
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compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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- interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
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- &cpu1_intc 11 &cpu1_intc 9>;
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+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
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+ <&cpu1_intc 11>, <&cpu1_intc 9>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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--
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Armbian
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