66 lines
2.4 KiB
Diff
66 lines
2.4 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sun, 24 Jul 2022 20:35:41 +0200
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Subject: dt-bindings: clock: Add StarFive JH7110 always-on definitions
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Add all clock outputs for the StarFive JH7110 always-on clock generator.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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include/dt-bindings/clock/starfive-jh7110-aon.h | 44 ++++++++++
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1 file changed, 44 insertions(+)
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diff --git a/include/dt-bindings/clock/starfive-jh7110-aon.h b/include/dt-bindings/clock/starfive-jh7110-aon.h
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new file mode 100755
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index 000000000000..ab5003d006c8
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--- /dev/null
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+++ b/include/dt-bindings/clock/starfive-jh7110-aon.h
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@@ -0,0 +1,44 @@
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+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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+/*
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+ * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
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+ */
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+
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+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_AON_H__
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+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_AON_H__
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+
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+#define JH7110_AONCLK_OSC_DIV4 0 /* clk_osc_div4 */
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+#define JH7110_AONCLK_APB_FUNC 1 /* clk_aon_apb_func */
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+#define JH7110_AONCLK_GMAC0_AHB 2 /* clk_u0_dw_gmac5_axi64_clk_ahb */
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+#define JH7110_AONCLK_GMAC0_AXI 3 /* clk_u0_dw_gmac5_axi64_clk_axi */
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+#define JH7110_AONCLK_GMAC0_RMII_RTX 4 /* clk_gmac0_rmii_rtx */
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+#define JH7110_AONCLK_GMAC0_TX 5 /* clk_u0_dw_gmac5_axi64_clk_tx */
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+#define JH7110_AONCLK_GMAC0_TX_INV 6 /* clk_u0_dw_gmac5_axi64_clk_tx_inv */
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+#define JH7110_AONCLK_GMAC0_RX 7 /* clk_u0_dw_gmac5_axi64_clk_rx */
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+#define JH7110_AONCLK_GMAC0_RX_INV 8 /* clk_u0_dw_gmac5_axi64_clk_rx_inv */
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+#define JH7110_AONCLK_OTPC_APB 9 /* clk_u0_otpc_clk_apb */
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+#define JH7110_AONCLK_RTC_APB 10 /* clk_u0_rtc_hms_clk_apb */
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+#define JH7110_AONCLK_RTC_INTERNAL 11 /* clk_rtc_internal */
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+#define JH7110_AONCLK_RTC_32K 12 /* clk_u0_rtc_hms_clk_osc32k */
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+#define JH7110_AONCLK_RTC_CAL 13 /* clk_u0_rtc_hms_clk_cal */
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+
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+#define JH7110_AONCLK_END 14
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+
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+#if 0
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+/* aon other */
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+#define JH7110_U0_GMAC5_CLK_PTP 15
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+#define JH7110_U0_GMAC5_CLK_RMII 16
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+#define JH7110_AON_SYSCON_PCLK 17
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+#define JH7110_AON_IOMUX_PCLK 18
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+#define JH7110_AON_CRG_PCLK 19
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+#define JH7110_PMU_CLK_APB 20
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+#define JH7110_PMU_CLK_WKUP 21
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+#define JH7110_RTC_HMS_CLK_OSC32K_G 22
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+#define JH7110_32K_OUT 23
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+#define JH7110_RESET0_CTRL_CLK_SRC 24
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+/* aon other and source */
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+#define JH7110_PCLK_MUX_FUNC_PCLK 25
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+#define JH7110_PCLK_MUX_BIST_PCLK 26
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+
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+#endif
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+
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+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
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--
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Armbian
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