86 lines
2.7 KiB
Diff
86 lines
2.7 KiB
Diff
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From 4d3f1f419bc3e5e4946c39bf2c2c882ff3a4a94f Mon Sep 17 00:00:00 2001
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From: Philipp Rossak <embed3d@gmail.com>
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Date: Wed, 24 Jan 2018 17:28:02 +0100
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Subject: [PATCH 050/101] drv:iio:adc:sun4i-gpadc-iio: add A80 thermal sensor
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This patch adds support for the A80 ths sensor.
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The A80 has 4 sensors and supports interrupts. The interrupt is configured to update
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the sensor values every second. The A80 shares some registers with the
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integrated GPADC. ACQ0 must be set in the GPADC register with the offset
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0x00. In fact the GPADC and the THS use the same register base and also
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the same clocks and resets.
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Signed-off-by: Philipp Rossak <embed3d@gmail.com>
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---
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drivers/iio/adc/sun4i-gpadc-iio.c | 46 +++++++++++++++++++++++++++++++
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1 file changed, 46 insertions(+)
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diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
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index 7450a914d..696561cb4 100644
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--- a/drivers/iio/adc/sun4i-gpadc-iio.c
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+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
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@@ -201,6 +201,48 @@ static const struct gpadc_data sun8i_a83t_ths_data = {
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SUNXI_THS_TEMP_PERIOD(0x257),
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};
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+static const struct gpadc_data sun9i_a80_ths_data = {
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+ .temp_offset = -2794,
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+ .temp_scale = -67,
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+ .temp_data = {SUNXI_THS_TDATA0,
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+ SUNXI_THS_TDATA1,
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+ SUNXI_THS_TDATA2,
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+ SUNXI_THS_TDATA3},
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+ .sample_start = sunxi_ths_sample_start,
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+ .sample_end = sunxi_ths_sample_end,
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+ .has_bus_clk = true,
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+ .has_bus_rst = true,
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+ .has_mod_clk = true,
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+ .sensor_count = 4,
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+ .supports_nvmem = false,
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+ .support_irq = true,
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+ .ctrl0_map = SUNXI_THS_ACQ0(0x1f3),
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+ .ctrl2_map = SUNXI_THS_TEMP_SENSE_EN0 |
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+ SUNXI_THS_TEMP_SENSE_EN1 |
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+ SUNXI_THS_TEMP_SENSE_EN2 |
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+ SUNXI_THS_TEMP_SENSE_EN3 |
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+ SUNXI_THS_ACQ1(0x1f3),
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+ .filter_map = SUNXI_THS_FILTER_EN |
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+ SUNXI_THS_FILTER_TYPE(0x2),
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+ .irq_clear_map = SUNXI_THS_INTS_ALARM_INT_0 |
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+ SUNXI_THS_INTS_ALARM_INT_1 |
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+ SUNXI_THS_INTS_ALARM_INT_2 |
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+ SUNXI_THS_INTS_ALARM_INT_3 |
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+ SUNXI_THS_INTS_SHUT_INT_0 |
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+ SUNXI_THS_INTS_SHUT_INT_1 |
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+ SUNXI_THS_INTS_SHUT_INT_2 |
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+ SUNXI_THS_INTS_SHUT_INT_3 |
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+ SUNXI_THS_INTS_TDATA_IRQ_0 |
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+ SUNXI_THS_INTS_TDATA_IRQ_1 |
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+ SUNXI_THS_INTS_TDATA_IRQ_2 |
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+ SUNXI_THS_INTS_TDATA_IRQ_3,
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+ .irq_control_map = SUNXI_THS_INTC_TDATA_IRQ_EN0 |
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+ SUNXI_THS_INTC_TDATA_IRQ_EN1 |
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+ SUNXI_THS_INTC_TDATA_IRQ_EN2 |
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+ SUNXI_THS_INTC_TDATA_IRQ_EN3 |
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+ SUNXI_THS_TEMP_PERIOD(0x3a),
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+};
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+
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struct sun4i_gpadc_iio {
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struct iio_dev *indio_dev;
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struct completion completion;
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@@ -705,6 +747,10 @@ static const struct of_device_id sun4i_gpadc_of_id[] = {
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.compatible = "allwinner,sun8i-a83t-ths",
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.data = &sun8i_a83t_ths_data,
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},
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+ {
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+ .compatible = "allwinner,sun9i-a80-ths",
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+ .data = &sun9i_a80_ths_data,
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+ },
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{ /* sentinel */ }
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};
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--
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2.31.1
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