106 lines
3.3 KiB
Diff
106 lines
3.3 KiB
Diff
|
From f081b3349bc32b852fcfedb9fbb0e7529f9b0af1 Mon Sep 17 00:00:00 2001
|
||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||
|
Date: Tue, 21 Jul 2020 21:53:27 +0200
|
||
|
Subject: [PATCH 053/101] drv:media: cedrus: check for H264, HEVC limitations
|
||
|
|
||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||
|
---
|
||
|
drivers/staging/media/sunxi/cedrus/cedrus.c | 47 +++++++++++++++++++++
|
||
|
drivers/staging/media/sunxi/cedrus/cedrus.h | 1 +
|
||
|
2 files changed, 48 insertions(+)
|
||
|
|
||
|
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
|
||
|
index b86bef8d4..314afde91 100644
|
||
|
--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
|
||
|
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
|
||
|
@@ -28,6 +28,50 @@
|
||
|
#include "cedrus_dec.h"
|
||
|
#include "cedrus_hw.h"
|
||
|
|
||
|
+static int cedrus_try_ctrl(struct v4l2_ctrl *ctrl)
|
||
|
+{
|
||
|
+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
|
||
|
+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
|
||
|
+
|
||
|
+ if (sps->chroma_format_idc != 1)
|
||
|
+ /* Only 4:2:0 is supported */
|
||
|
+ return -EINVAL;
|
||
|
+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
|
||
|
+ /* Luma and chroma bit depth mismatch */
|
||
|
+ return -EINVAL;
|
||
|
+ if (sps->bit_depth_luma_minus8 != 0)
|
||
|
+ /* Only 8-bit is supported */
|
||
|
+ return -EINVAL;
|
||
|
+ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) {
|
||
|
+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
|
||
|
+ struct cedrus_ctx *ctx = container_of(ctrl->handler, struct cedrus_ctx, hdl);
|
||
|
+
|
||
|
+ if (sps->chroma_format_idc != 1)
|
||
|
+ /* Only 4:2:0 is supported */
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
|
||
|
+ /* Luma and chroma bit depth mismatch */
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ if (ctx->dev->capabilities & CEDRUS_CAPABILITY_H265_10_DEC) {
|
||
|
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
|
||
|
+ /* Only 8-bit and 10-bit are supported */
|
||
|
+ return -EINVAL;
|
||
|
+ } else {
|
||
|
+ if (sps->bit_depth_luma_minus8 != 0)
|
||
|
+ /* Only 8-bit is supported */
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+ }
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static const struct v4l2_ctrl_ops cedrus_ctrl_ops = {
|
||
|
+ .try_ctrl = cedrus_try_ctrl,
|
||
|
+};
|
||
|
+
|
||
|
static const struct cedrus_control cedrus_controls[] = {
|
||
|
{
|
||
|
.cfg = {
|
||
|
@@ -62,6 +106,7 @@ static const struct cedrus_control cedrus_controls[] = {
|
||
|
{
|
||
|
.cfg = {
|
||
|
.id = V4L2_CID_STATELESS_H264_SPS,
|
||
|
+ .ops = &cedrus_ctrl_ops,
|
||
|
},
|
||
|
.codec = CEDRUS_CODEC_H264,
|
||
|
},
|
||
|
@@ -120,6 +165,7 @@ static const struct cedrus_control cedrus_controls[] = {
|
||
|
{
|
||
|
.cfg = {
|
||
|
.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
|
||
|
+ .ops = &cedrus_ctrl_ops,
|
||
|
},
|
||
|
.codec = CEDRUS_CODEC_H265,
|
||
|
},
|
||
|
@@ -560,6 +606,7 @@ static const struct cedrus_variant sun50i_h6_cedrus_variant = {
|
||
|
CEDRUS_CAPABILITY_MPEG2_DEC |
|
||
|
CEDRUS_CAPABILITY_H264_DEC |
|
||
|
CEDRUS_CAPABILITY_H265_DEC |
|
||
|
+ CEDRUS_CAPABILITY_H265_10_DEC |
|
||
|
CEDRUS_CAPABILITY_VP8_DEC,
|
||
|
.mod_rate = 600000000,
|
||
|
};
|
||
|
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
|
||
|
index f280e81d0..25079901a 100644
|
||
|
--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
|
||
|
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
|
||
|
@@ -32,6 +32,7 @@
|
||
|
#define CEDRUS_CAPABILITY_H264_DEC BIT(2)
|
||
|
#define CEDRUS_CAPABILITY_MPEG2_DEC BIT(3)
|
||
|
#define CEDRUS_CAPABILITY_VP8_DEC BIT(4)
|
||
|
+#define CEDRUS_CAPABILITY_H265_10_DEC BIT(5)
|
||
|
|
||
|
enum cedrus_codec {
|
||
|
CEDRUS_CODEC_MPEG2,
|
||
|
--
|
||
|
2.31.1
|
||
|
|