165 lines
5.0 KiB
Diff
165 lines
5.0 KiB
Diff
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From 640cbf5cbb0ebb7bccd8859f12f5429ca16ae9dd Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Sun, 6 Dec 2020 01:39:24 +0000
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Subject: [PATCH 021/101] drv:phy:sun4i-usb: Rework HCI PHY (aka. "pmu_unk1")
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handling
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As Icenowy pointed out, newer manuals (starting with H6) actually
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document the register block at offset 0x800 as "HCI controller and PHY
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interface", also describe the bits in our "PMU_UNK1" register.
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Let's put proper names to those "unknown" variables and symbols.
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While we are at it, generalise the existing code by allowing a bitmap
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of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
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different bit for the SIDDQ control.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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drivers/phy/allwinner/phy-sun4i-usb.c | 30 ++++++++++++---------------
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1 file changed, 13 insertions(+), 17 deletions(-)
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diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
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index 53846d798..33d31a2c4 100644
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--- a/drivers/phy/allwinner/phy-sun4i-usb.c
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+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
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@@ -44,7 +44,7 @@
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#define REG_PHYCTL_A33 0x10
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#define REG_PHY_OTGCTL 0x20
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-#define REG_PMU_UNK1 0x10
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+#define REG_HCI_PHY_CTL 0x10
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#define PHYCTL_DATA BIT(7)
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@@ -83,6 +83,7 @@
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/* A83T specific control bits for PHY0 */
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#define PHY_CTL_VBUSVLDEXT BIT(5)
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#define PHY_CTL_SIDDQ BIT(3)
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+#define PHY_CTL_H3_SIDDQ BIT(1)
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/* A83T specific control bits for PHY2 HSIC */
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#define SUNXI_EHCI_HS_FORCE BIT(20)
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@@ -116,9 +117,9 @@ struct sun4i_usb_phy_cfg {
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int hsic_index;
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enum sun4i_usb_phy_type type;
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u32 disc_thresh;
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+ u32 hci_phy_ctl_clear;
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u8 phyctl_offset;
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bool dedicated_clocks;
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- bool enable_pmu_unk1;
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bool phy0_dual_route;
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int missing_phys;
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};
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@@ -292,6 +293,12 @@ static int sun4i_usb_phy_init(struct phy *_phy)
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return ret;
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}
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+ if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
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+ val = readl(phy->pmu + REG_HCI_PHY_CTL);
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+ val &= ~data->cfg->hci_phy_ctl_clear;
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+ writel(val, phy->pmu + REG_HCI_PHY_CTL);
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+ }
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+
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if (data->cfg->type == sun8i_a83t_phy ||
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data->cfg->type == sun50i_h6_phy) {
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if (phy->index == 0) {
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@@ -301,11 +308,6 @@ static int sun4i_usb_phy_init(struct phy *_phy)
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writel(val, data->base + data->cfg->phyctl_offset);
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}
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} else {
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- if (phy->pmu && data->cfg->enable_pmu_unk1) {
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- val = readl(phy->pmu + REG_PMU_UNK1);
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- writel(val & ~2, phy->pmu + REG_PMU_UNK1);
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- }
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-
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/* Enable USB 45 Ohm resistor calibration */
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if (phy->index == 0)
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sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
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@@ -916,7 +918,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = false,
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- .enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
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@@ -925,7 +926,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
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.disc_thresh = 2,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = false,
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- .enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
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@@ -934,7 +934,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = true,
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- .enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
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@@ -943,7 +942,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
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.disc_thresh = 2,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = false,
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- .enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
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@@ -952,7 +950,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = true,
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- .enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
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@@ -961,7 +958,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A33,
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.dedicated_clocks = true,
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- .enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
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@@ -978,7 +974,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A33,
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.dedicated_clocks = true,
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- .enable_pmu_unk1 = true,
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+ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
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.phy0_dual_route = true,
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};
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@@ -988,7 +984,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A33,
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.dedicated_clocks = true,
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- .enable_pmu_unk1 = true,
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+ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
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.phy0_dual_route = true,
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};
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@@ -998,7 +994,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A33,
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.dedicated_clocks = true,
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- .enable_pmu_unk1 = true,
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+ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
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.phy0_dual_route = true,
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};
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@@ -1008,7 +1004,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A33,
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.dedicated_clocks = true,
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- .enable_pmu_unk1 = true,
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+ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
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.phy0_dual_route = true,
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};
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--
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2.31.1
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