59 lines
2.1 KiB
Diff
59 lines
2.1 KiB
Diff
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From ef5c913570040df1955dd49cea221783468faeaf Mon Sep 17 00:00:00 2001
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From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
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Date: Sat, 16 Oct 2021 12:53:52 +0200
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Subject: [PATCH 082/478] arm64: dts: rockchip: Add i2s1 on rk356x
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This adds the necessary device tree node on rk3566 and rk3568
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to enable the I2S1 TDM audio controller.
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I2S0 has not been added, as it is connected to HDMI and there is
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no way to test that it's working without a functioning video
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clock (read: VOP2 driver).
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Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
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Link: https://lore.kernel.org/r/20211016105354.116513-4-frattaroli.nicolas@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 25 ++++++++++++++++++++++++
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1 file changed, 25 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 3fa444b25d83..ea8c0e4d71a1 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -622,6 +622,31 @@ spdif: spdif@fe460000 {
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status = "disabled";
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};
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+ i2s1_8ch: i2s@fe410000 {
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+ compatible = "rockchip,rk3568-i2s-tdm";
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+ reg = <0x0 0xfe410000 0x0 0x1000>;
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+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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+ assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
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+ assigned-clock-rates = <1188000000>, <1188000000>;
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+ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
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+ <&cru HCLK_I2S1_8CH>;
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+ clock-names = "mclk_tx", "mclk_rx", "hclk";
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+ dmas = <&dmac1 3>, <&dmac1 2>;
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+ dma-names = "rx", "tx";
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+ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
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+ reset-names = "tx-m", "rx-m";
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+ rockchip,grf = <&grf>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
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+ &i2s1m0_lrcktx &i2s1m0_lrckrx
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+ &i2s1m0_sdi0 &i2s1m0_sdi1
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+ &i2s1m0_sdi2 &i2s1m0_sdi3
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+ &i2s1m0_sdo0 &i2s1m0_sdo1
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+ &i2s1m0_sdo2 &i2s1m0_sdo3>;
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+ #sound-dai-cells = <0>;
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+ status = "disabled";
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+ };
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+
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dmac0: dmac@fe530000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xfe530000 0x0 0x4000>;
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--
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2.35.3
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