404 lines
7.8 KiB
Diff
404 lines
7.8 KiB
Diff
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From ae04430959b3878567cebd3dfdfdf1985b1599d1 Mon Sep 17 00:00:00 2001
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From: Brian Norris <briannorris@chromium.org>
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Date: Fri, 20 Aug 2021 13:38:35 -0700
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Subject: [PATCH 052/478] arm64: dts: rockchip: add RK3399 Gru gpio-line-names
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It's convenient to get nice names for GPIOs. In particular, Chrome OS
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tooling looks for "AP_FLASH_WP" and "AP_FLASH_WP_L". The rest are
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provided for convenience.
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Gru-Bob and Gru-Kevin share the gru-chromebook.dtsi, and for the most
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part they share pin meanings. I omitted a few areas where components
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were available only on one or the other.
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Signed-off-by: Brian Norris <briannorris@chromium.org>
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Reviewed-by: Douglas Anderson <dianders@chromium.org>
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Link: https://lore.kernel.org/r/20210820133829.1.Ica46f428de8c3beb600760dbcd63cf879ec24baf@changeid
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../dts/rockchip/rk3399-gru-chromebook.dtsi | 176 +++++++++++++++++
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.../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 180 ++++++++++++++++++
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2 files changed, 356 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
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index 1384dabbdf40..9b2c679f5eca 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
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@@ -251,6 +251,182 @@ edp_out_panel: endpoint@0 {
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};
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};
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+&gpio0 {
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+ gpio-line-names = /* GPIO0 A 0-7 */
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+ "AP_RTC_CLK_IN",
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+ "EC_AP_INT_L",
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+ "PP1800_AUDIO_EN",
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+ "BT_HOST_WAKE_L",
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+ "WLAN_MODULE_PD_L",
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+ "H1_INT_OD_L",
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+ "CENTERLOGIC_DVS_PWM",
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+ "",
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+
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+ /* GPIO0 B 0-4 */
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+ "WIFI_HOST_WAKE_L",
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+ "PMUIO2_33_18_L",
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+ "PP1500_EN",
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+ "AP_EC_WARM_RESET_REQ",
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+ "PP3000_EN";
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+};
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+
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+&gpio1 {
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+ gpio-line-names = /* GPIO1 A 0-7 */
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+ "",
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+ "",
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+ "SPK_PA_EN",
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+ "",
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+ "TRACKPAD_INT_L",
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+ "AP_EC_S3_S0_L",
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+ "AP_EC_OVERTEMP",
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+ "AP_SPI_FLASH_MISO",
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+
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+ /* GPIO1 B 0-7 */
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+ "AP_SPI_FLASH_MOSI_R",
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+ "AP_SPI_FLASH_CLK_R",
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+ "AP_SPI_FLASH_CS_L_R",
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+ "WLAN_MODULE_RESET_L",
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+ "WIFI_DISABLE_L",
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+ "MIC_INT",
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+ "",
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+ "AP_I2C_DVS_SDA",
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+
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+ /* GPIO1 C 0-7 */
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+ "AP_I2C_DVS_SCL",
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+ "AP_BL_EN",
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+ /*
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+ * AP_FLASH_WP is crossystem ABI. Schematics call it
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+ * AP_FW_WP or CPU1_FW_WP, depending on the variant.
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+ */
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+ "AP_FLASH_WP",
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+ "LITCPU_DVS_PWM",
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+ "AP_I2C_AUDIO_SDA",
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+ "AP_I2C_AUDIO_SCL",
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+ "",
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+ "HEADSET_INT_L";
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+};
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+
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+&gpio2 {
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+ gpio-line-names = /* GPIO2 A 0-7 */
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+ "",
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+ "",
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+ "SD_IO_PWR_EN",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO2 B 0-7 */
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO2 C 0-7 */
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+ "",
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+ "",
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+ "",
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+ "",
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+ "AP_SPI_EC_MISO",
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+ "AP_SPI_EC_MOSI",
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+ "AP_SPI_EC_CLK",
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+ "AP_SPI_EC_CS_L",
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+
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+ /* GPIO2 D 0-4 */
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+ "BT_DEV_WAKE_L",
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+ "",
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+ "WIFI_PCIE_CLKREQ_L",
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+ "WIFI_PERST_L",
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+ "SD_PWR_3000_1800_L";
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+};
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+
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+&gpio3 {
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+ gpio-line-names = /* GPIO3 A 0-7 */
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+ "",
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+ "",
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+ "",
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+ "",
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+ "AP_SPI_TPM_MISO",
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+ "AP_SPI_TPM_MOSI_R",
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+ "AP_SPI_TPM_CLK_R",
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+ "AP_SPI_TPM_CS_L_R",
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+
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+ /* GPIO3 B 0-7 */
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+ "EC_IN_RW",
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+ "",
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+ "AP_I2C_TP_SDA",
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+ "AP_I2C_TP_SCL",
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+ "AP_I2C_TP_PU_EN",
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+ "TOUCH_INT_L",
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+ "",
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+ "",
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+
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+ /* GPIO3 C 0-7 */
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO3 D 0-7 */
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+ "I2S0_SCLK",
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+ "I2S0_LRCK_RX",
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+ "I2S0_LRCK_TX",
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+ "I2S0_SDI_0",
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+ "I2S0_SDI_1",
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+ "",
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+ "I2S0_SDO_1",
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+ "I2S0_SDO_0";
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+};
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+
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+&gpio4 {
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+ gpio-line-names = /* GPIO4 A 0-7 */
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+ "I2S_MCLK",
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+ "AP_I2C_MIC_SDA",
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+ "AP_I2C_MIC_SCL",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO4 B 0-7 */
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO4 C 0-7 */
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+ "AP_I2C_TS_SDA",
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+ "AP_I2C_TS_SCL",
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+ "GPU_DVS_PWM",
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+ "UART_DBG_TX_AP_RX",
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+ "UART_AP_TX_DBG_RX",
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+ "",
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+ "BIGCPU_DVS_PWM",
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+ "EDP_HPD_3V0",
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+
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+ /* GPIO4 D 0-5 */
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+ "SD_CARD_DET_L",
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+ "USB_DP_HPD",
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+ "TOUCH_RESET_L",
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+ "PP3300_DISP_EN",
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+ "",
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+ "SD_SLOT_PWR_EN";
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+};
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+
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ap_i2c_mic: &i2c1 {
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status = "okay";
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
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index 5d7a9d96d163..61afb5f0f15b 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
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@@ -389,6 +389,186 @@ &cru {
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<400000000>;
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};
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+&gpio0 {
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+ gpio-line-names = /* GPIO0 A 0-7 */
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+ "CLK_32K_AP",
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+ "EC_IN_RW_OD",
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+ "SPK_PA_EN",
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+ "WLAN_PERST_1V8_L",
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+ "WLAN_PD_1V8_L",
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+ "WLAN_RF_KILL_1V8_L",
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+ "BIGCPU_DVS_PWM",
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+ "SD_CD_L_JTAG_EN",
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+
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+ /* GPIO0 B 0-5 */
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+ "BT_EN_BT_RF_KILL_1V8_L",
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+ "PMUIO2_33_18_L_PP3300_S0_EN",
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+ "TOUCH_RESET_L",
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+ "AP_EC_WARM_RESET_REQ",
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+ "PEN_RESET_L",
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+ /*
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+ * AP_FLASH_WP_L is crossystem ABI. Schematics call
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+ * it AP_FLASH_WP_R_ODL.
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+ */
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+ "AP_FLASH_WP_L";
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+};
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+
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+&gpio1 {
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+ gpio-line-names = /* GPIO1 A 0-7 */
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+ "PEN_INT_ODL",
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+ "PEN_EJECT_ODL",
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+ "BT_HOST_WAKE_1V8_L",
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+ "WLAN_HOST_WAKE_1V8_L",
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+ "TOUCH_INT_ODL",
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+ "AP_EC_S3_S0_L",
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+ "AP_EC_OVERTEMP",
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+ "AP_SPI_FLASH_MISO",
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+
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+ /* GPIO1 B 0-7 */
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+ "AP_SPI_FLASH_MOSI_R",
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+ "AP_SPI_FLASH_CLK_R",
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+ "AP_SPI_FLASH_CS_L_R",
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+ "SD_CARD_DET_ODL",
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+ "",
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+ "AP_EXPANSION_IO1",
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+ "AP_EXPANSION_IO2",
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+ "AP_I2C_DISP_SDA",
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+
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+ /* GPIO1 C 0-7 */
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+ "AP_I2C_DISP_SCL",
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+ "H1_INT_ODL",
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+ "EC_AP_INT_ODL",
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+ "LITCPU_DVS_PWM",
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+ "AP_I2C_AUDIO_SDA",
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+ "AP_I2C_AUDIO_SCL",
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+ "AP_EXPANSION_IO3",
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+ "HEADSET_INT_ODL",
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+
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+ /* GPIO1 D0 */
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+ "AP_EXPANSION_IO4";
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+};
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+
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+&gpio2 {
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+ gpio-line-names = /* GPIO2 A 0-7 */
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+ "AP_I2C_PEN_SDA",
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+ "AP_I2C_PEN_SCL",
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+ "SD_IO_PWR_EN",
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+ "UCAM_RST_L",
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+ "PP1250_CAM_EN",
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+ "WCAM_RST_L",
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+ "AP_EXPANSION_IO5",
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+ "AP_I2C_CAM_SDA",
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+
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+ /* GPIO2 B 0-7 */
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+ "AP_I2C_CAM_SCL",
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+ "AP_H1_SPI_MISO",
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+ "AP_H1_SPI_MOSI",
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+ "AP_H1_SPI_CLK",
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+ "AP_H1_SPI_CS_L",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO2 C 0-7 */
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+ "UART_EXPANSION_TX_AP_RX",
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+ "UART_AP_TX_EXPANSION_RX",
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+ "UART_EXPANSION_RTS_AP_CTS",
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+ "UART_AP_RTS_EXPANSION_CTS",
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+ "AP_SPI_EC_MISO",
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+ "AP_SPI_EC_MOSI",
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+ "AP_SPI_EC_CLK",
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+ "AP_SPI_EC_CS_L",
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+
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+ /* GPIO2 D 0-4 */
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+ "PP2800_CAM_EN",
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+ "CLK_24M_CAM",
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+ "WLAN_PCIE_CLKREQ_1V8_L",
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+ "",
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+ "SD_PWR_3000_1800_L";
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+};
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+
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+&gpio3 {
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+ gpio-line-names = /* GPIO3 A 0-7 */
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO3 B 0-7 */
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO3 C 0-7 */
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO3 D 0-7 */
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+ "I2S0_SCLK",
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+ "I2S0_LRCK_RX",
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+ "I2S0_LRCK_TX",
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+ "I2S0_SDI_0",
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+ "STRAP_LCDBIAS_L",
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+ "STRAP_FEATURE_1",
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+ "STRAP_FEATURE_2",
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+ "I2S0_SDO_0";
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+};
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+
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+&gpio4 {
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+ gpio-line-names = /* GPIO4 A 0-7 */
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+ "I2S_MCLK",
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+ "AP_I2C_EXPANSION_SDA",
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+ "AP_I2C_EXPANSION_SCL",
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+ "DMIC_EN",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO4 B 0-7 */
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ /* GPIO4 C 0-7 */
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+ "AP_I2C_TS_SDA",
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+ "AP_I2C_TS_SCL",
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+ "GPU_DVS_PWM",
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+ "UART_DBG_TX_AP_RX",
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+ "UART_AP_TX_DBG_RX",
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+ "BL_EN",
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+ "BL_PWM",
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+ "",
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+
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+ /* GPIO4 D 0-5 */
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+ "",
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+ "DISPLAY_RST_L",
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+ "",
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+ "PPVARP_LCD_EN",
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+ "PPVARN_LCD_EN",
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+ "SD_SLOT_PWR_EN";
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+};
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+
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&i2c_tunnel {
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google,remote-bus = <0>;
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};
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--
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2.35.3
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