85 lines
2.7 KiB
Diff
85 lines
2.7 KiB
Diff
|
From 74e4a7637084f25c046c2e1d99cdeffe772f82fd Mon Sep 17 00:00:00 2001
|
||
|
From: Peter Geis <pgwipeout@gmail.com>
|
||
|
Date: Thu, 22 Jul 2021 14:35:27 -0400
|
||
|
Subject: [PATCH 093/478] arm64: dts: rockchip: add rk356x sata controller
|
||
|
nodes
|
||
|
|
||
|
Add the sata controller nodes to the rk356x device tree.
|
||
|
|
||
|
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||
|
---
|
||
|
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 15 ++++++++++++
|
||
|
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 30 ++++++++++++++++++++++++
|
||
|
2 files changed, 45 insertions(+)
|
||
|
|
||
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||
|
index 305d49c587f2..591ebea8527b 100644
|
||
|
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||
|
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||
|
@@ -8,6 +8,21 @@
|
||
|
/ {
|
||
|
compatible = "rockchip,rk3568";
|
||
|
|
||
|
+ sata0: sata@fc000000 {
|
||
|
+ compatible = "snps,dwc-ahci";
|
||
|
+ reg = <0 0xfc000000 0 0x1000>;
|
||
|
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
|
||
|
+ <&cru CLK_SATA0_RXOOB>;
|
||
|
+ clock-names = "sata", "pmalive", "rxoob";
|
||
|
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
+ interrupt-names = "hostc";
|
||
|
+ phys = <&combphy0_us PHY_TYPE_SATA>;
|
||
|
+ phy-names = "sata-phy";
|
||
|
+ ports-implemented = <0x1>;
|
||
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
qos_pcie3x1: qos@fe190080 {
|
||
|
compatible = "rockchip,rk3568-qos", "syscon";
|
||
|
reg = <0x0 0xfe190080 0x0 0x20>;
|
||
|
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||
|
index 72e388212040..2d9f46d36d37 100644
|
||
|
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||
|
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||
|
@@ -192,6 +192,36 @@ scmi_shmem: sram@0 {
|
||
|
};
|
||
|
};
|
||
|
|
||
|
+ sata1: sata@fc400000 {
|
||
|
+ compatible = "snps,dwc-ahci";
|
||
|
+ reg = <0 0xfc400000 0 0x1000>;
|
||
|
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
|
||
|
+ <&cru CLK_SATA1_RXOOB>;
|
||
|
+ clock-names = "sata", "pmalive", "rxoob";
|
||
|
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
+ interrupt-names = "hostc";
|
||
|
+ phys = <&combphy1_usq PHY_TYPE_SATA>;
|
||
|
+ phy-names = "sata-phy";
|
||
|
+ ports-implemented = <0x1>;
|
||
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
+ sata2: sata@fc800000 {
|
||
|
+ compatible = "snps,dwc-ahci";
|
||
|
+ reg = <0 0xfc800000 0 0x1000>;
|
||
|
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
|
||
|
+ <&cru CLK_SATA2_RXOOB>;
|
||
|
+ clock-names = "sata", "pmalive", "rxoob";
|
||
|
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
+ interrupt-names = "hostc";
|
||
|
+ phys = <&combphy2_psq PHY_TYPE_SATA>;
|
||
|
+ phy-names = "sata-phy";
|
||
|
+ ports-implemented = <0x1>;
|
||
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
||
|
+ status = "disabled";
|
||
|
+ };
|
||
|
+
|
||
|
gic: interrupt-controller@fd400000 {
|
||
|
compatible = "arm,gic-v3";
|
||
|
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
||
|
--
|
||
|
2.35.3
|
||
|
|