42 lines
1.5 KiB
Diff
42 lines
1.5 KiB
Diff
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From f7c5b9c2a1af765de0aae3a21073e051e95448bf Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Wed, 28 Jul 2021 14:00:32 -0400
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Subject: [PATCH 033/478] arm64: dts: rockchip: adjust rk3568 pll clocks
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The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
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These are set incorrectly by the bootloader, so fix them here.
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gpll boots at 1188mhz, but to get most accurate dividers for all
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gpll_dividers it needs to run at 1200mhz, otherwise everyone downstream
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isn't quite right.
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ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is
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required to reach a 100mhz clock input for them.
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The vendor-kernel also makes this fix.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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[pulled deeper explanation from discussion into commit message]
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Link: https://lore.kernel.org/r/20210728180034.717953-7-pgwipeout@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 874d8b977679..bef747fb1fe2 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -222,6 +222,8 @@ cru: clock-controller@fdd20000 {
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reg = <0x0 0xfdd20000 0x0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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+ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
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+ assigned-clock-rates = <1200000000>, <200000000>;
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};
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i2c0: i2c@fdd40000 {
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--
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2.35.3
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