57 lines
1.8 KiB
Diff
57 lines
1.8 KiB
Diff
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From 7f8a0e72011bfac4601e445fe3a75171b22ffdd9 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Tue, 10 Mar 2020 06:04:32 +0100
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Subject: [PATCH 115/478] clk: sunxi-ng: Don't use CPU PLL gating and CPUX
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reparenting to HOSC
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It's not necessary when not using dividers on CPU PLL, and it's
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causing cntvct jump backs on H3.
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 21 ---------------------
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1 file changed, 21 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index ec4c92bca173..9d461deb13f8 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -1129,20 +1129,6 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
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.num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
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};
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-static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
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- .common = &pll_cpux_clk.common,
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- /* copy from pll_cpux_clk */
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- .enable = BIT(31),
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- .lock = BIT(28),
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-};
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-
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-static struct ccu_mux_nb sun8i_h3_cpu_nb = {
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- .common = &cpux_clk.common,
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- .cm = &cpux_clk.mux,
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- .delay_us = 1, /* > 8 clock cycles at 24 MHz */
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- .bypass_index = 1, /* index of 24 MHz oscillator */
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-};
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-
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static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
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const struct sunxi_ccu_desc *desc)
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{
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@@ -1161,13 +1147,6 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
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writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
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of_sunxi_ccu_probe(node, reg, desc);
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-
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- /* Gate then ungate PLL CPU after any rate changes */
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- ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
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-
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- /* Reparent CPU during PLL CPU rate changes */
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- ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
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- &sun8i_h3_cpu_nb);
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}
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static void __init sun8i_h3_ccu_setup(struct device_node *node)
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--
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2.35.3
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