77 lines
2.9 KiB
Diff
77 lines
2.9 KiB
Diff
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From b5ad3048ece47d9f863ddc969df0077bd7fb405c Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megi@xff.cz>
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Date: Fri, 3 Jun 2022 19:22:34 +0200
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Subject: [PATCH 199/388] drm/sun4i: tcon: hand over the duty to keep TCON0
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clock to CCU on A64
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As the A64 CCU driver has already the ability to keep TCON0 clock stable
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when HDMI changes its parent's clock, do not protect TCON0 clock on A64
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in the TCON driver to allow PLL-Video0 gets changed by HDMI (the CCU
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will then restore the TCON0 clock rate).
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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# Conflicts:
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# drivers/gpu/drm/sun4i/sun4i_tcon.c
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---
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drivers/gpu/drm/sun4i/sun4i_tcon.c | 15 +++++++++++++--
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drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
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2 files changed, 14 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
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index efe3eb7b7..057714a6a 100644
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--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
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+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
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@@ -108,9 +108,11 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
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if (enabled) {
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clk_prepare_enable(clk);
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- clk_rate_exclusive_get(clk);
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+ if (!tcon->quirks->clk_kept_by_ccu)
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+ clk_rate_exclusive_get(clk);
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} else {
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- clk_rate_exclusive_put(clk);
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+ if (!tcon->quirks->clk_kept_by_ccu)
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+ clk_rate_exclusive_put(clk);
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clk_disable_unprepare(clk);
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}
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}
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@@ -1551,6 +1553,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
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.supports_lvds = true,
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};
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+static const struct sun4i_tcon_quirks sun50i_a64_lcd_quirks = {
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+ .supports_lvds = true,
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+ .has_channel_0 = true,
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+ .clk_kept_by_ccu = true,
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+ .dclk_min_div = 1,
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+ .setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
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+};
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+
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static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
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.supports_lvds = true,
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.has_channel_0 = true,
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@@ -1609,6 +1619,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
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{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
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{ .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
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{ .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
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+ { .compatible = "allwinner,sun50i-a64-tcon-lcd", .data = &sun50i_a64_lcd_quirks },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
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diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
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index 97df39db2..745e1c473 100644
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--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
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+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
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@@ -250,6 +250,7 @@ struct sun4i_tcon_quirks {
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bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
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bool supports_lvds; /* Does the TCON support an LVDS output? */
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bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
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+ bool clk_kept_by_ccu; /* On A64 we rely on CCU to keep TCON0 clock stable */
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u8 dclk_min_div; /* minimum divider for TCON0 DCLK */
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/* callback to handle tcon muxing options */
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--
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2.35.3
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