111 lines
2.8 KiB
Diff
111 lines
2.8 KiB
Diff
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From dacdde4ba975f8933c5c9d91f1fb8505f59f0c83 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megi@xff.cz>
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Date: Sun, 21 May 2023 01:42:25 +0200
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Subject: [PATCH 298/469] arm64: dts: rockchip: rk3399-pinephone-pro:
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Pre-configure DMC
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This enables dynamic DRAM reclocking. The node needs to be okayed
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by U-Boot/firmware combo known to support it. Do not enable &dmc
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by default.
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Signed-off-by: Ondrej Jirman <megi@xff.cz>
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---
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arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 29 ++++++++++++++++
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.../dts/rockchip/rk3399-pinephone-pro.dts | 33 +++++++++++++++++++
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2 files changed, 62 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
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index fee5e7111279..3775d0ea254e 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
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@@ -102,6 +102,31 @@ opp05 {
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opp-microvolt = <1100000 1100000 1150000>;
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};
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};
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+
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+ dmc_opp_table: opp-table-3 {
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+ compatible = "operating-points-v2";
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+
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+ opp00 {
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+ opp-hz = /bits/ 64 <328000000>;
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+ opp-microvolt = <900000>;
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+ };
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+ opp01 {
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+ opp-hz = /bits/ 64 <416000000>;
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+ opp-microvolt = <900000>;
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+ };
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+ opp02 {
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+ opp-hz = /bits/ 64 <666000000>;
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+ opp-microvolt = <900000>;
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+ };
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+ opp03 {
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+ opp-hz = /bits/ 64 <856000000>;
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+ opp-microvolt = <900000>;
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+ };
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+ opp04 {
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+ opp-hz = /bits/ 64 <928000000>;
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+ opp-microvolt = <925000>;
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+ };
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+ };
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};
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&cpu_l0 {
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@@ -128,6 +153,10 @@ &cpu_b1 {
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operating-points-v2 = <&cluster1_opp>;
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};
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+&dmc {
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+ operating-points-v2 = <&dmc_opp_table>;
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+};
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+
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&gpu {
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operating-points-v2 = <&gpu_opp_table>;
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};
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
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index cf2f1a99db9d..f845bd02c5dc 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
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@@ -552,6 +552,39 @@ &cdn_dp {
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phys = <&tcphy0_dp>;
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};
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+&dfi {
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+ status = "okay";
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+};
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+
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+&dmc {
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+ // This node can only be enabled by FDT patching from U-Boot that
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+ // uses Rockchip TPL/TF-A. DMC only works with the downstream firmware.
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+ // If you enabled this on mainline, your phone will lock up on boot.
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+ //status = "okay";
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+
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+ center-supply = <&vdd_center>;
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+
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+ rockchip,pd-idle-ns = <160>;
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+ rockchip,sr-idle-ns = <10240>;
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+ rockchip,sr-mc-gate-idle-ns = <40960>;
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+ rockchip,srpd-lite-idle-ns = <61440>;
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+ rockchip,standby-idle-ns = <81920>;
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+
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+ rockchip,lpddr4_odt_dis_freq = <666000000>;
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+
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+ rockchip,srpd-lite-idle-dis-freq-hz = <0>;
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+ rockchip,standby-idle-dis-freq-hz = <928000000>;
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+ rockchip,sr-mc-gate-idle-dis-freq-hz = <800000000>;
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+ rockchip,pd-idle-dis-freq-hz = <800000000>;
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+ rockchip,sr-idle-dis-freq-hz = <800000000>;
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+};
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+
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+&dmc_opp_table {
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+ opp00 {
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+ opp-suspend;
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+ };
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+};
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+
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&emmc_phy {
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status = "okay";
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};
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--
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2.34.1
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