55 lines
2.0 KiB
Diff
55 lines
2.0 KiB
Diff
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From 4ac22afaa40da590605cd725850b81bfb562b0fb Mon Sep 17 00:00:00 2001
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From: Vyacheslav Bocharov <adeep@lexina.in>
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Date: Thu, 2 Dec 2021 13:10:24 +0300
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Subject: [PATCH 2/2] mmc: meson-gx: change clock phase value on axg SoCs
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Amlogic AXG SoCs seems doesn't work over 50MHz. When phase sets to 270',
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it's working fine over 50MHz on Amlogic AXG SoCs.
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Based on 0dbb54eb3257c243c7968f967a6b183b1edb56c8 by Neil Armstrong
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<narmstrong@baylibre.com>
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To distinguish which value is used adds an u-boot only axg compatible.
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---
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drivers/mmc/meson_gx_mmc.c | 5 +++--
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drivers/mmc/meson_gx_mmc.h | 1 +
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2 files changed, 4 insertions(+), 2 deletions(-)
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diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
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index fcf4f03d1e..718eae42ec 100644
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--- a/drivers/mmc/meson_gx_mmc.c
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+++ b/drivers/mmc/meson_gx_mmc.c
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@@ -68,7 +68,8 @@ static void meson_mmc_config_clock(struct mmc *mmc)
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* Other SoCs use CLK_CO_PHASE_180 by default.
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* It needs to find what is a proper value about each SoCs.
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*/
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- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
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+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1) ||
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+ meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_AXG))
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meson_mmc_clk |= CLK_CO_PHASE_270;
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else
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meson_mmc_clk |= CLK_CO_PHASE_180;
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@@ -322,7 +323,7 @@ int meson_mmc_bind(struct udevice *dev)
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static const struct udevice_id meson_mmc_match[] = {
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{ .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
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- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
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+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_AXG },
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{ .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
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{ /* sentinel */ }
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};
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diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h
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index 8974b78f55..53201cedda 100644
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--- a/drivers/mmc/meson_gx_mmc.h
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+++ b/drivers/mmc/meson_gx_mmc.h
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@@ -12,6 +12,7 @@
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enum meson_gx_mmc_compatible {
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MMC_COMPATIBLE_GX,
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MMC_COMPATIBLE_SM1,
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+ MMC_COMPATIBLE_AXG,
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};
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#define SDIO_PORT_A 0
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--
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2.30.2
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