添加构建Allwinner H616四核2GB RAM SoC WiFi（蓝莓）
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From 82fa50eadf11f01e6315f5e2c2a29845e2a516b8 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Mon, 8 Apr 2019 03:49:26 +0200
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Subject: [PATCH] Fix reset issue on H6 by using R_WDOG
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Inspired by froezuses patch here:
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https://forum.armbian.com/topic/9833-h6-famous-reboot-problem/?page=3
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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plat/allwinner/sun50i_h6/include/sunxi_mmap.h | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
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index f36491a8..f01745a4 100644
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--- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
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+++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
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@@ -58,4 +58,7 @@
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#define SUNXI_R_UART_BASE 0x07080000
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#define SUNXI_R_PIO_BASE 0x07022000
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+#undef SUNXI_WDOG_BASE
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+#define SUNXI_WDOG_BASE SUNXI_R_WDOG_BASE
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+
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#endif /* SUNXI_MMAP_H */
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--
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2.21.0
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@@ -0,0 +1,29 @@
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From 5ff3a09d64b6b9172d9007e3f77116902b9c2965 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Mon, 8 Aug 2016 02:34:27 +0100
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Subject: [PATCH] sunxi: add SRAM regions to EL3 mapping
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Currently we only map the MMIO regions for actual peripheral devices
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in EL3. For the SCPI implementation we need access to the SRAM regions
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as well.
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Add a mapping entry that covers all three SRAM regions on the A64.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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plat/sun50iw1p1/aarch64/sunxi_common.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/plat/sun50iw1p1/aarch64/sunxi_common.c b/plat/sun50iw1p1/aarch64/sunxi_common.c
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index a2fa37a39..8ebcd9852 100644
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--- a/plat/sun50iw1p1/aarch64/sunxi_common.c
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+++ b/plat/sun50iw1p1/aarch64/sunxi_common.c
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@@ -56,6 +56,9 @@ plat_config_t plat_config;
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*/
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const mmap_region_t sunxi_mmap[] = {
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+ // SRAM regions
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+ { 0x0010000, 0x0010000,
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+ 0x0030000, MT_DEVICE | MT_RW | MT_NS },
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// MMI/O region used by peripherals from 0x100.0000 to 0x200.0000
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{ 0x1000000, 0x1000000,
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0x1000000, MT_DEVICE | MT_RW | MT_SECURE },
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@@ -0,0 +1,21 @@
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diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
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index 71ccafa3..e592c029 100644
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--- a/plat/sun50iw1p1/sunxi_power.c
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+++ b/plat/sun50iw1p1/sunxi_power.c
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@@ -252,6 +252,16 @@ static int pmic_setup(const char *dt_name)
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ret = 0x2c;
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}
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}
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+
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+ /** Ditto for sopine64 */
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+ if (!strcmp(dt_name, "sun50i-a64-sopine-baseboard")) {
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+ if (ret == 0x26) { /* check for 1.24V value */
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+ NOTICE("PMIC: fixing DRAM voltage from 1.24V to 1.20V\n");
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+ sunxi_pmic_write(0x24, 0x25);
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+ ret = 0x25;
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+ }
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+ }
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+
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/* reg 24h: DCDC5: 0.80-1.12V: 10mv/step, 1.14-1.84V: 20mv/step */
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if (ret > 0x20)
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ret = ((ret - 0x20) * 2) + 112;
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@@ -0,0 +1,19 @@
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diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
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index db79047..fb1b108 100644
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--- a/plat/sun50iw1p1/sunxi_power.c
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+++ b/plat/sun50iw1p1/sunxi_power.c
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@@ -261,12 +261,8 @@ static int pmic_setup(void)
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* changes. This should be further confined once we are able to
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* reliably detect a Pine64 board.
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*/
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- ret = sunxi_pmic_read(0x24); /* read DCDC5 register */
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- if ((ret & 0x7f) == 0x26) { /* check for 1.24V value */
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- NOTICE("PMIC: fixing DRAM voltage from 1.24V to 1.36V\n");
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- sunxi_pmic_write(0x24, 0x2c);
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- }
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-
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+ sunxi_pmic_write(0x24, 0x25);
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+
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sunxi_pmic_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */
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sunxi_pmic_write(0x16, 0x12); /* DLDO2 = VCC2V5_EDP voltage = 2.5V */
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@@ -0,0 +1,28 @@
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From 3efb52570e581d79f6e451ef88933423a61a9b55 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Mon, 27 Mar 2017 21:56:08 +0100
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Subject: [PATCH] Makefile: (re-)enable A53 errata workaround
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The --fix-cortex-a53-843418 option to the linker was disabled before to
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also support older toolchains which don't know of this option.
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To not loose the bugfix for more recent toolchains introduce a feature
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check, which enables the option if the linker knows about it.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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Makefile | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/Makefile b/Makefile
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index f96e2cb37..87c307ded 100644
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--- a/Makefile
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+++ b/Makefile
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@@ -234,7 +234,7 @@ CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \
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CFLAGS += -ffunction-sections -fdata-sections
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LDFLAGS += --fatal-warnings -O1
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LDFLAGS += --gc-sections
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-#LDFLAGS += --fix-cortex-a53-843419
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+LDFLAGS += $(if $(shell $(LD) -v --fix-cortex-a53-843419 > /dev/null 2>&1 && echo 1),--fix-cortex-a53-843419)
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CC := ${CROSS_COMPILE}gcc
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@@ -0,0 +1,34 @@
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diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
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index a2ded04..75574b9
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--- a/plat/sun50iw1p1/sunxi_power.c
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+++ b/plat/sun50iw1p1/sunxi_power.c
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@@ -229,8 +229,8 @@ static int pmic_setup(const char *dt_name)
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/* Enable DC1SW to power PHY, DLDO4 for WiFi and DLDO1 for HDMI */
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ret = sunxi_pmic_read(0x12);
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- if ((ret & 0xc8) != 0xc8) {
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- ret = sunxi_pmic_write(0x12, ret | 0xc8);
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+ if ((ret & 0xd9) != 0xd9) {
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+ ret = sunxi_pmic_write(0x12, ret | 0xd8);
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if (ret < 0) {
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NOTICE("PMIC: error %d enabling DC1SW/DLDO4/DLDO1\n",
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ret);
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@@ -272,8 +272,17 @@ static int pmic_setup(const char *dt_name)
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INFO("PMIC: enabled Pinebook display\n");
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}
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-
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+
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sunxi_pmic_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */
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+ sunxi_pmic_write(0x21, 60); /* Set DCDC2/CPU voltage to 1.1V */
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+ sunxi_pmic_write(0x16, 0x12); /* DLDO2 = VCC2V5_EDP voltage = 2.5V */
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+ sunxi_pmic_write(0x1c, 0xa); /* FLDO1 = VCC1V2_EDP voltage = 1.2V */
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+ sunxi_pmic_write(0x91, 0x1a); /* GPIO0LDO voltage = 3.3V */
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+ sunxi_pmic_write(0x90, 0x3); /* Enable GPIO0LDO */
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+ sunxi_pmic_write(0x30, sunxi_pmic_read(0x30) | BIT(2)); /* Enable USB at Lime64 */
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+ ret = sunxi_pmic_read(0x13);
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+ /* Enable FLDO1 to power up eDP bridge */
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+ ret = sunxi_pmic_write(0x13, ret | 0x4);
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return 0;
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}
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@@ -0,0 +1,15 @@
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diff --git a/plat/sun50iw1p1/sunxi_security.c b/plat/sun50iw1p1/sunxi_security.c
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index c0036c12..76d296bd 100644
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--- a/plat/sun50iw1p1/sunxi_security.c
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+++ b/plat/sun50iw1p1/sunxi_security.c
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@@ -58,8 +58,9 @@ void sunxi_security_setup(void)
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for (i = 0; i < 6; i++)
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mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff);
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- /* switch RSB to secure */
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+ /* switch RSB to secure
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mmio_write_32(SPC_DECPORT_CLR_REG(3), 0x08);
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+ */
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/* set CCMU mbus_sec, bus_sec, pll_sec to non-secure */
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mmio_write_32(0x01c20000+0x2f0, 0x7);
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